Cypress CY7C1156V18 User Manual

CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
18-Mbit QDR™-II+ SRAM 4-Word Burst  
Architecture (2.0 Cycle Read Latency)  
Features  
Functional Description  
Separate Independent read and write data ports  
Supports concurrent transactions  
300 MHz to 375 MHz clock for high bandwidth  
The CY7C1141V18, CY7C1156V18, CY7C1143V18, and  
CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs,  
equipped with QDR™-II+ architecture. QDR-II+ architecture  
consists of two separate ports to access the memory array. The  
read port has dedicated data outputs to support read operations  
and the write port has dedicated data inputs to support write  
operations. QDR-II+ architecture has separate data inputs and  
data outputs to completely eliminate the need to “turn-around”  
the data bus required with common IO devices. Access to each  
4-Word Burst for reducing address bus frequency  
DoubleDataRate(DDR)interfacesonbothreadandwriteports  
(data transferred at 750 MHz) at 375 MHz  
Read latency of 2.0 clock cycles  
Two input clocks (K and K) for precise DDR timing  
SRAM uses rising edges only  
Echo clocks (CQ and CQ) simplify data capture in high speed  
port is accomplished through  
a
common address bus.  
Addresses for read and write addresses are latched on alternate  
rising edges of the input (K) clock. Accesses to the QDR-II+ read  
and write ports are completely independent of one another. To  
maximize data throughput, both read and write ports are  
equipped with Double Data Rate (DDR) interfaces. Each  
address location is associated with four 8-bit words  
(CY7C1141V18), or 9-bit words (CY7C1156V18), or 18-bit words  
(CY7C1143V18), or 36-bit words (CY7C1145V18) that burst  
sequentially into or out of the device. Because data can be trans-  
ferred into and out of the device on every rising edge of both input  
clocks K and K, memory bandwidth is maximized while simpli-  
fying system design by eliminating bus “turn-arounds”.  
systems  
Single multiplexed address input bus latches address inputs  
for both read and write ports  
Separate Port Selects for depth expansion  
Data valid pin (QVLD) to indicate valid data on the output  
Synchronous internally self-timed writes  
Available in x8, x9, x18, and x36 configurations  
Full data coherency providing most current data  
[1]  
Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD  
Depth expansion is accomplished with Port Selects for each port.  
Port Selects enable each port to operate independently.  
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)  
Offered in both Pb-free and non Pb-free packages  
Variable drive HSTL output buffers  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the K or K input clocks. Writes are  
conducted with on-chip synchronous self-timed write circuitry.  
JTAG 1149.1 compatible test access port  
Delay Lock Loop (DLL) for accurate data placement  
Configurations  
With Read Cycle Latency of 2.0 cycles:  
CY7C1141V18 – 2M x 8  
CY7C1156V18 – 2M x 9  
CY7C1143V18 – 1M x 18  
CY7C1145V18 – 512K x 36  
Selection Guide  
Description  
Maximum Operating Frequency  
Maximum Operating Current  
375 MHz  
375  
333 MHz  
333  
300 MHz  
300  
Unit  
MHz  
mA  
1020  
920  
850  
Note  
1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ  
= 1.4V to VDD  
.
Cypress Semiconductor Corporation  
Document Number: 001-06583 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 06, 2008  
 
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Logic Block Diagram (CY7C1143V18)  
D[17:0]  
18  
Write Write Write Write  
Address  
Register  
A(17:0)  
Reg  
Reg Reg  
Reg  
18  
Address  
Register  
A(17:0)  
18  
RPS  
K
K
Control  
Logic  
CLK  
Gen.  
DOFF  
Read Data Reg.  
72  
CQ  
CQ  
36  
VREF  
Reg.  
Reg.  
Reg.  
WPS  
Control  
Logic  
Q[17:0]  
36  
BWS[1:0]  
18  
18  
QVLD  
Logic Block Diagram (CY7C1145V18)  
D[35:0]  
36  
Write Write Write Write  
Address  
Register  
A(16:0)  
Reg  
Reg Reg  
Reg  
17  
Address  
Register  
A(16:0)  
17  
RPS  
K
K
Control  
Logic  
CLK  
Gen.  
DOFF  
Read Data Reg.  
144  
CQ  
CQ  
72  
VREF  
Reg.  
Reg.  
Reg.  
WPS  
Control  
Logic  
Q[35:0]  
72  
BWS[3:0]  
36  
36  
QVLD  
Document Number: 001-06583 Rev. *D  
Page 3 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Pin Configurations  
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout  
CY7C1141V18 (2M x 8)  
1
2
3
A
6
K
9
A
10  
NC/36M  
11  
CQ  
5
NWS  
7
8
RPS  
A
4
WPS  
NC/72M  
NC/144M  
A
CQ  
1
NC  
NC  
NC  
NC  
NC  
D4  
NC  
NC  
NC  
A
NC/288M  
A
K
NWS  
NC  
NC  
NC  
NC  
NC  
NC  
Q3  
D3  
NC  
B
C
D
0
V
NC  
A
V
SS  
SS  
V
V
V
V
V
SS  
SS  
SS  
SS  
SS  
NC  
NC  
NC  
NC  
NC  
D5  
Q4  
NC  
Q5  
V
V
V
V
V
NC  
NC  
NC  
D2  
NC  
NC  
Q2  
NC  
NC  
ZQ  
D1  
NC  
Q0  
E
F
DDQ  
SS  
SS  
SS  
DDQ  
V
V
V
V
V
DDQ  
DD  
SS  
DD  
DDQ  
V
V
V
V
V
G
DDQ  
DD  
SS  
DD  
DDQ  
V
V
V
V
V
V
V
V
V
H
J
REF  
DDQ  
DDQ  
DD  
SS  
DD  
DDQ  
DDQ  
REF  
DOFF  
NC  
NC  
NC  
Q6  
NC  
D7  
NC  
V
V
V
V
V
NC  
Q1  
NC  
NC  
NC  
NC  
NC  
DDQ  
DD  
SS  
DD  
DDQ  
NC  
NC  
NC  
NC  
NC  
NC  
D6  
NC  
NC  
Q7  
V
V
V
V
V
NC  
NC  
NC  
NC  
NC  
K
L
DDQ  
DD  
SS  
DD  
DDQ  
V
V
V
V
V
DDQ  
SS  
SS  
SS  
DDQ  
V
V
V
V
V
D0  
NC  
NC  
M
N
P
SS  
SS  
SS  
SS  
SS  
V
A
A
A
A
A
V
SS  
SS  
NC  
QVLD  
A
A
A
A
A
A
TDO  
TCK  
A
NC  
A
TMS  
TDI  
R
CY7C1156V18 (2M x 9)  
1
2
NC/72M  
NC  
3
6
K
9
10  
NC/36M  
NC  
11  
CQ  
Q4  
D4  
NC  
Q3  
5
NC  
7
8
4
WPS  
A
CQ  
NC  
NC  
NC  
NC  
A
NC/144M RPS  
A
A
B
C
D
NC  
NC  
NC  
Q5  
NC  
Q6  
NC/288M  
A
K
BWS  
A
A
NC  
NC  
NC  
NC  
NC  
NC  
0
NC  
V
NC  
V
NC  
SS  
SS  
SS  
D5  
V
V
V
V
V
NC  
SS  
SS  
SS  
SS  
NC  
V
V
V
V
V
V
V
V
V
V
V
D3  
E
F
DDQ  
SS  
SS  
SS  
DDQ  
NC  
NC  
NC  
V
V
V
V
NC  
NC  
NC  
ZQ  
D2  
NC  
Q1  
DDQ  
DD  
SS  
DD  
DDQ  
DDQ  
DDQ  
DDQ  
D6  
V
V
V
V
NC  
G
H
J
DDQ  
DD  
SS  
DD  
V
V
V
V
DOFF  
NC  
V
V
V
V
DDQ  
DD  
DDQ  
REF  
REF  
DDQ  
SS  
DD  
NC  
NC  
Q7  
NC  
D8  
NC  
V
V
V
V
NC  
Q2  
NC  
NC  
NC  
NC  
D0  
DDQ  
DD  
SS  
DD  
NC  
NC  
D7  
NC  
NC  
Q8  
V
V
V
V
NC  
NC  
NC  
NC  
NC  
K
L
DDQ  
DD  
SS  
DD  
DDQ  
DDQ  
NC  
V
V
V
V
DDQ  
SS  
SS  
SS  
NC  
NC  
NC  
V
V
V
V
V
D1  
NC  
Q0  
M
N
P
SS  
SS  
SS  
SS  
SS  
SS  
V
A
A
A
A
A
A
V
SS  
NC  
QVLD  
A
A
A
A
A
TDO  
TCK  
A
NC  
A
TMS  
TDI  
R
Document Number: 001-06583 Rev. *D  
Page 4 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Pin Configurations (continued)  
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout  
CY7C1143V18 (1M x 18)  
2
3
5
BWS  
NC  
A
6
K
7
9
10  
NC/72M  
NC  
11  
CQ  
Q8  
D8  
D7  
Q6  
Q5  
D5  
1
4
WPS  
A
8
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
NC/144M NC/36M  
NC/288M RPS  
A
A
B
C
D
E
F
1
Q9  
NC  
D9  
K
BWS  
A
A
NC  
NC  
NC  
NC  
NC  
NC  
0
D10  
Q10  
Q11  
D12  
Q13  
V
NC  
V
Q7  
SS  
SS  
SS  
D11  
NC  
V
V
V
V
V
NC  
SS  
SS  
SS  
SS  
V
V
V
V
V
V
V
D6  
DDQ  
SS  
SS  
SS  
DDQ  
DDQ  
DDQ  
Q12  
D13  
V
V
V
V
NC  
DDQ  
DD  
SS  
DD  
V
V
V
V
NC  
G
DDQ  
DD  
SS  
DD  
V
DOFF  
NC  
V
NC  
V
D14  
V
V
V
V
V
V
V
V
V
ZQ  
D4  
H
J
DDQ  
REF  
DDQ  
DDQ  
DD  
SS  
DD  
DDQ  
DDQ  
REF  
V
V
NC  
Q4  
D3  
NC  
Q1  
NC  
D0  
DDQ  
DD  
SS  
DD  
NC  
NC  
NC  
NC  
NC  
NC  
Q15  
NC  
Q14  
D15  
D16  
Q16  
Q17  
V
V
V
V
V
V
NC  
NC  
NC  
NC  
NC  
Q3  
Q2  
K
L
DDQ  
DD  
SS  
DD  
DDQ  
DDQ  
V
V
V
V
DDQ  
SS  
SS  
SS  
V
V
V
V
V
D2  
D1  
Q0  
M
N
P
SS  
SS  
SS  
SS  
SS  
SS  
D17  
NC  
V
A
A
A
A
A
V
SS  
QVLD  
A
A
A
A
A
A
R
TDO  
A
A
TMS  
TDI  
TCK  
NC  
CY7C1145V18 (512K x 36)  
7
1
2
3
8
9
10  
11  
CQ  
Q8  
D8  
D7  
4
WPS  
A
5
BWS  
BWS  
A
6
K
NC/288M NC/72M  
NC/36M NC/144M  
A
B
C
D
CQ  
BWS  
RPS  
A
2
3
1
0
Q27  
D27  
D28  
Q29  
Q30  
D30  
Q18  
Q28  
D20  
D29  
Q21  
D22  
D18  
D19  
Q19  
Q20  
D21  
Q22  
K
D17  
D16  
Q16  
Q15  
D14  
Q13  
Q17  
Q7  
BWS  
A
V
NC  
V
SS  
SS  
V
V
V
V
V
D15  
D6  
SS  
SS  
SS  
SS  
SS  
V
V
V
V
V
Q6  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
E
F
DDQ  
SS  
SS  
SS  
DDQ  
V
V
V
V
V
Q14  
D13  
DDQ  
DD  
SS  
DD  
DD  
DD  
DD  
DDQ  
V
V
V
V
V
V
V
V
G
H
J
DDQ  
DD  
SS  
DDQ  
V
V
V
V
V
V
V
V
REF  
REF  
DDQ  
DDQ  
DD  
SS  
DDQ  
DDQ  
DOFF  
D31  
Q31  
D23  
V
V
V
V
D12  
Q4  
DDQ  
DD  
SS  
DDQ  
Q32  
Q33  
D33  
D34  
Q35  
D32  
Q24  
Q34  
D26  
D35  
Q23  
D24  
D25  
Q25  
Q26  
V
V
V
V
Q12  
D11  
D10  
Q10  
Q9  
D3  
Q11  
Q1  
D9  
K
L
DDQ  
DD  
SS  
DD  
DDQ  
V
V
V
V
V
V
DDQ  
SS  
SS  
SS  
DDQ  
V
V
V
V
D2  
D1  
Q0  
M
N
P
SS  
SS  
SS  
SS  
SS  
V
A
A
A
A
A
A
V
SS  
SS  
QVLD  
D0  
A
A
A
A
A
TDO  
TCK  
A
A
TMS  
TDI  
R
NC  
Document Number: 001-06583 Rev. *D  
Page 5 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Pin Definitions  
Pin Name  
IO  
Pin Description  
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.  
D[x:0]  
Input-  
Synchronous CY7C1141V18D[7:0]  
CY7C1156V18D[8:0]  
CY7C1143V18D[17:0]  
CY7C1145V18D[35:0]  
WPS  
Input-  
Write Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active,  
Synchronous a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes  
D[x:0] to be ignored.  
,
Input-  
Nibble Write Select 0, 1 Active LOW.(CY7C1141V18 Only) Sampled on the rising edge of the K  
NWS0, NWS1  
Synchronous and K clocks during write operations. This is used to select the nibble that is written into the device  
NWS0 controls D[3:0] and NWS1 controls D[7:4]  
.
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write  
Select causes the corresponding nibble of data to be ignored and not written into the device.  
BWS0, BWS1,  
BWS2, BWS3  
Input-  
Byte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks  
Synchronous during write operations. This is used to select the byte that is written into the device during the current  
portion of the write operations. Bytes not written remain unaltered.  
CY7C1156V18 BWS0 controls D[8:0]  
CY7C1143V18 BWS controls D[8:0] and BWS1 controls D[17:9]  
.
CY7C1145V18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18], and BWS3  
0
controls D[35:27]  
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select  
causes the corresponding byte of data to be ignored and not written into the device.  
A
Input-  
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.  
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is  
organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1141V18, 2M x 9 (4 arrays each of 512K  
x 9) for CY7C1156V18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1143V18, and 512K x 36 (4  
arrays each of 128K x 36) for CY7C1145V18. Therefore, only 19 address inputs are needed to access  
the entire memory array of CY7C1141V18 and CY7C1156V18, 18 address inputs for CY7C1143V18  
and 17 address inputs for CY7C1145V18. These inputs are ignored when the appropriate port is  
deselected.  
Q[x:0]  
Outputs-  
Data Output signals. These pins drive out the requested data during a read operation. Valid data is  
Synchronous driven out on the rising edge of both the K and K clocks during read operations or K and K when in  
single clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.  
CY7C1141V18Q[7:0]  
CY7C1156V18Q[8:0]  
CY7C1143V18Q[17:0]  
CY7C1145V18Q[35:0]  
RPS  
Input-  
Read Port Select Active LOW. Sampled on the rising edge of Positive Input Clock (K). When  
Synchronous active, a read operation is initiated. Deasserting causes the read port to be deselected. When  
deselected, the pending access is enabled to complete and the output drivers are automatically  
tri-stated following the next rising edge of the K clock. Each read access consists of a burst of four  
sequential transfers.  
QVLD  
K
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and  
indicator  
CQ.  
Input-  
Clock  
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device  
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising  
edge of K.  
K
Input-  
Clock  
Negative Input Clock Input. K is used to capture synchronous inputs presented to the device and  
to drive out data through Q[x:0] when in single clock mode.  
CQ  
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input  
clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”  
on page 23.  
Document Number: 001-06583 Rev. *D  
Page 6 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Pin Definitions (continued)  
Pin Name  
CQ  
IO  
Pin Description  
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input  
clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”  
on page 23.  
ZQ  
Input  
Output Impedance Matching Input. This input is used to tune the device outputs to the system data  
bus impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor  
connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables  
the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.  
DOFF  
Input  
DLL Turn Off Active LOW. Connecting this pin to ground turns off the DLL inside the device. The  
timings in the DLL turned off operationis different from those listed in this data sheet. For normal  
operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves  
in QDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to  
167 MHz with QDR-I timing.  
TDO  
Output  
Input  
Input  
Input  
N/A  
TDO for JTAG.  
TCK  
TCK Pin for JTAG.  
TDI  
TDI Pin for JTAG.  
TMS  
TMS Pin for JTAG.  
NC  
Not Connected to the Die. Tie to any voltage level.  
Not Connected to the Die. Tie to any voltage level.  
Not Connected to the Die. Tie to any voltage level.  
Not Connected to the Die. Tie to any voltage level.  
Not Connected to the Die. Tie to any voltage level.  
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and  
NC/36M  
NC/72M  
NC/144M  
NC/288M  
VREF  
N/A  
N/A  
N/A  
N/A  
Input-  
Reference AC measurement points.  
VDD  
VSS  
Power Supply Power Supply Inputs to the Core of the Device.  
Ground  
Ground for the Device.  
VDDQ  
Power Supply Power Supply Inputs for the Outputs of the Device.  
Document Number: 001-06583 Rev. *D  
Page 7 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Write Operations  
Functional Overview  
Write operations are initiated by asserting WPS active at the  
rising edge of the Positive Input Clock (K). On the following K  
clock rise the data presented to D[17:0] is latched and stored into  
the lower 18-bit Write Data register, provided BWS[1:0] are both  
asserted active. On the subsequent rising edge of the Negative  
Input Clock (K) the information presented to D[17:0] is also stored  
into the Write Data register, provided BWS[1:0] are both asserted  
active. This process continues for one more cycle until four 18-bit  
words (a total of 72 bits) of data are stored in the SRAM. The 72  
bits of data are then written into the memory array at the specified  
location. Therefore, write accesses to the device cannot be  
initiated on two consecutive K clock rises. The internal logic of  
the device ignores the second write request. Initiate write  
accesses on every other rising edge of the Positive Input Clock  
(K). This pipelines the data flow such that 18 bits of data can be  
transferred into the device on every rising edge of the input  
clocks (K and K).  
The CY7C1141V18, CY7C1156V18, CY7C1143V18, and  
CY7C1145V18 are synchronous pipelined Burst SRAMs  
equipped with both a read port and a write port. The read port is  
dedicated to read operations and the write port is dedicated to  
write operations. Data flows into the SRAM through the write port  
and out through the read port. These devices multiplex the  
address inputs in order to minimize the number of address pins  
required. By having separate read and write ports, the QDR-II+  
completely eliminates the need to “turn-around” the data bus and  
avoids any possible data contention, thereby simplifying system  
design. Each access consists of four 8-bit data transfers in the  
case of CY7C1141V18, four 9-bit data transfers in the case of  
CY7C1156V18, four 18-bit data transfers in the case of  
CY7C1143V18, and four 36-bit data transfers in the case of  
CY7C1145V18 in two clock cycles.  
Accesses for both ports are initiated on the Positive Input Clock  
(K). All synchronous input and output timing refer to the rising  
edge of the Input clocks (K/K).  
When deselected, the write port ignores all inputs after the  
pending write operations are completed.  
All synchronous data inputs (D[x:0]) pass through input registers  
controlled by the input clocks (K and K). All synchronous data  
outputs (Q[x:0]) pass through output registers controlled by the  
rising edge of the Input clocks (K and K) as well.  
Byte Write Operations  
Byte Write operations are supported by the CY7C1143V18. A  
write operation is initiated as described in the Write Operations.  
The bytes that are written are determined by BWS0 and BWS1,  
which are sampled with each set of 18-bit data words. Asserting  
the appropriate Byte Write Select input during the data portion of  
a write enables the data being presented to be latched and  
written into the device. Deasserting the Byte Write Select input  
during the data portion of a write enables the data stored in the  
device for that byte to remain unaltered. Use this feature to  
simplify read/modify/write operations to a Byte Write operation.  
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass  
through input registers controlled by the rising edge of the input  
clocks (K/K). CY7C1143V18 is described in the following  
sections. The same basic descriptions apply to CY7C1141V18,  
CY7C1156V18, and CY7C1145V18.  
Read Operations  
The CY7C1143V18 is organized internally as four arrays of 256K  
x 18. Accesses are completed in a burst of four sequential 18-bit  
data words. Read operations are initiated by asserting RPS  
active at the rising edge of the Positive Input Clock (K). The  
address presented to Address inputs are stored in the read  
address register. Following the next two K clock rise, the corre-  
sponding lowest order 18-bit word of data is driven onto the  
Q[17:0] using K as the output timing reference. On the subse-  
quent rising edge of K the next 18-bit data word is driven onto  
the Q[17:0]. This process continues until all four 18-bit data words  
are driven out onto Q[17:0]. The requested data is valid 0.45 ns  
from the rising edge of the Input clock K or K. To maintain the  
internallogic, each read access must be allowed to complete.  
Each read access consists of four 18-bit data words and takes  
two clock cycles to complete. Therefore, read accesses to the  
device cannot be initiated on two consecutive K clock rises. The  
internal logic of the device ignores the second read request.  
Initiate read accesses on every other K clock rise. This pipelines  
the data flow such that data is transferred out of the device on  
every rising edge of the input clocks K and K.  
Concurrent Transactions  
The read and write ports on the CY7C1143V18 operate indepen-  
dently of one another. Because each port latches the address  
inputs on different clock edges, the user can read or write to any  
location, regardless of the transaction on the other port. If the  
ports access the same location when a read follows a write in  
successive clock cycles, the SRAM delivers the most recent  
information associated with the specified address location. This  
includes forwarding data from a write cycle that was initiated on  
the previous K clock rise.  
Read accesses and write access must be scheduled such that  
one transaction is initiated on any clock cycle. If both ports are  
selected on the same K clock rise, the arbitration depends on the  
previous state of the SRAM. If both ports were deselected, the  
read port takes priority. If a read was initiated on the previous  
cycle, the write port is based on priority (since read operations  
cannot be initiated on consecutive cycles). If a write was initiated  
on the previous cycle, the read port is based on priority (since  
write operations cannot be initiated on consecutive cycles).  
Therefore, asserting both port selects active from a deselected  
state results in alternating read/write operations initiated, with the  
first access being a read.  
When the read port is deselected, the CY7C1143V18 first  
completes the pending read transactions. Synchronous internal  
circuitry automatically tri-states the outputs following the next  
rising edge of the Positive Input Clock (K). This enables for a  
seamless transition between devices without the insertion of wait  
states in a depth expanded memory.  
Document Number: 001-06583 Rev. *D  
Page 8 of 28  
 
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
synchronized to the input clock of the QDR-II+. The timings for  
the echo clocks are shown in the AC timing table.  
Depth Expansion  
The CY7C1143V18 has a Port Select input for each port. This  
enables easy depth expansion. Both Port Selects are sampled  
on the rising edge of the Positive Input Clock only (K). Each port  
select input can deselect the specified port. Deselecting a port  
does not affect the other port. All pending transactions (read and  
write) are completed before the device is deselected.  
Valid Data Indicator (QVLD)  
QVLD is provided on the QDR-II+ to simplify data capture on high  
speed systems. The QVLD is generated by the QDR-II+ device  
along with data output. This signal is also edge-aligned with the  
echo clock and follows the timing of any data pin. This signal is  
asserted half a cycle before valid data arrives.  
Programmable Impedance  
An external resistor, RQ, must be connected between the ZQ pin  
on the SRAM and VSS to enable the SRAM to adjust its output  
driver impedance. The value of RQ must be 5X the value of the  
intended line impedance driven by the SRAM. The allowable  
range of RQ to guarantee impedance matching with a tolerance  
of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The  
output impedance is adjusted every 1024 cycles upon power up  
to account for drifts in supply voltage and temperature.  
DLL  
These chips use a Delay Lock Loop (DLL) that is designed to  
function between 120 MHz and the specified maximum clock  
frequency. The DLL may be disabled by applying ground to the  
DOFF pin. When the DLL is turned off, the device behaves in  
QDR-I mode (with 1.0 cycle latency and a longer access time).  
For more information, refer to the application note, “DLL Consid-  
erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be  
reset by slowing or stopping the input clocks K and K for a  
minimum of 30 ns. However, it is not necessary for the DLL to be  
reset to lock to the desired frequency. During power up, when the  
DOFF is tied HIGH, the DLL gets locked after 2048 cycles of  
stable clock.  
Echo Clocks  
Echo clocks are provided on the QDR-II+ to simplify data capture  
on high speed systems. Two echo clocks are generated by the  
QDR-II+. CQ is referenced with respect to K and CQ is refer-  
enced with respect to K. These are free running clocks and are  
Document Number: 001-06583 Rev. *D  
Page 9 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Figure 1 shows the four QDR-II+ used in an application.  
Figure 1. Appliation Example  
RQ = 250ohms  
RQ = 250ohms  
ZQ  
CQ/CQ  
Q
ZQ  
CQ/CQ  
Q
Vt  
SRAM #1  
BWS  
SRAM #4  
D
A
D
A
R
K
RPS WPS  
K
K
K
BWS  
RPS WPS  
DATA IN  
DATA OUT  
Address  
R
R
Vt  
Vt  
RPS  
BUS MASTER  
WPS  
BWS  
(CPU or ASIC)  
CLKIN/CLKIN  
Source K  
Source K  
R = 50ohms, Vt = V  
/2  
DDQ  
Truth Table  
The truth table for the CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 follows.[2, 3, 4, 5, 6, 7]  
Operation  
Write Cycle:  
K
RPS WPS  
DQ  
DQ  
DQ  
DQ  
L-H  
H[8] L[9] D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2) ↑  
Load address on the rising  
edge of K; input write data  
on two consecutive K and  
K rising edges  
Read Cycle:  
L-H  
L[9]  
X
Q(A) at K(t + 2) Q(A + 1) at K(t + 2) Q(A + 2) at K(t + 3)Q(A + 3) at K(t + 3) ↑  
(2.0 cycle Latency)  
Load address on the rising  
edge of K; wait one and a  
half cycle; read data on  
two consecutive K and K  
rising edges  
NOP: No Operation  
L-H  
H
X
H
X
D = X  
Q = High-Z  
D = X  
Q = High-Z  
D = X  
Q = High-Z  
D = X  
Q = High-Z  
Standby: Clock Stopped Stopped  
Previous State  
Previous State  
Previous State  
Previous State  
Notes  
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.  
3. Device powers up deselected and the outputs in a tri-state condition.  
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.  
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, t + 2, and t + 3 are the first, second, and third clock cycles respectively succeeding the “t” clock  
cycle.  
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.  
7. IDo K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.  
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.  
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the  
second read orwrite request.  
Document Number: 001-06583 Rev. *D  
Page 10 of 28  
                 
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Write Cycle Descriptions  
The write cycle descriptions of CY7C1141V18 and CY7C1143V18 follows. [2, 10]  
BWS0/ BWS1/  
K
Comments  
K
NWS0 NWS1  
L
L
L–H  
During the data portion of a write sequence:  
CY7C1141V18 both nibbles (D[7:0]) are written into the device.  
CY7C1143V18 both bytes (D[17:0]) are written into the device.  
L
L
L–H  
L-H During the data portion of a write sequence:  
CY7C1141V18 both nibbles (D[7:0]) are written into the device.  
CY7C1143V18 both bytes (D[17:0]) are written into the device.  
L
H
H
L
During the data portion of a write sequence:  
CY7C1141V18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.  
CY7C1143V18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.  
L
L–H During the data portion of a write sequence:  
CY7C1141V18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.  
CY7C1143V18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.  
H
H
L–H  
During the data portion of a write sequence:  
CY7C1141V18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.  
CY7C1143V18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.  
L
L–H During the data portion of a write sequence:  
CY7C1141V18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.  
CY7C1143V18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.  
H
H
H
H
L–H  
No data is written into the devices during this portion of a write operation.  
L–H No data is written into the devices during this portion of a write operation.  
The write cycle descriptions of CY7C1156V18 follows.[2, 10]  
BWS0  
K
L–H  
K
Comments  
L
L
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.  
L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.  
No data is written into the device during this portion of a write operation.  
L–H No data is written into the device during this portion of a write operation.  
H
H
L–H  
Note  
10. Is based on a Write cycle was initiated in accordance with the Write Cycle Description Truth Table. Alter NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 on different  
portions of a Write cycle, as long as the setup and hold requirements are achieved.  
Document Number: 001-06583 Rev. *D  
Page 11 of 28  
 
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
The write cycle descriptions of CY7C1145V18 follows.[2, 10]  
BWS0 BWS1 BWS2 BWS3  
K
K
Comments  
L
L
L
L
L–H  
During the data portion of a write sequence, all four bytes (D[35:0]) are written into  
the device.  
L
L
L
L
L–H  
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into  
the device.  
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
During the data portion of a write sequence, only the lower byte (D[8:0]) is written  
into the device. D[35:9] remains unaltered.  
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written  
into the device. D[35:9] remains unaltered.  
H
H
H
H
H
H
L–H  
During the data portion of a write sequence, only the byte (D[17:9]) is written into  
the device. D[8:0] and D[35:18] remains unaltered.  
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into  
the device. D[8:0] and D[35:18] remains unaltered.  
H
H
H
H
L–H  
During the data portion of a write sequence, only the byte (D[26:18]) is written into  
the device. D[17:0] and D[35:27] remains unaltered.  
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into  
the device. D[17:0] and D[35:27] remains unaltered.  
H
H
L–H  
During the data portion of a write sequence, only the byte (D[35:27]) is written into  
the device. D[26:0] remains unaltered.  
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into  
the device. D[26:0] remains unaltered.  
H
H
H
H
H
H
H
H
L–H  
No data is written into the device during this portion of a write operation.  
L–H No data is written into the device during this portion of a write operation.  
Document Number: 001-06583 Rev. *D  
Page 12 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Instruction Register  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
This register is loaded when it is placed between the TDI and  
TDO pins as shown in “TAP Controller Block Diagram” on  
page 16. Upon power up, the instruction register is loaded with  
the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as described  
in the previous section.  
These SRAMs incorporate a serial boundary scan test access  
port (TAP) in the FBGA package. This part is fully compliant with  
IEEE Standard #1149.1-2001. The TAP operates using JEDEC  
standard 1.8V IO logic levels.  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
(VSS) to prevent clocking of the device. TDI and TMS are inter-  
nally pulled up and may be unconnected. They may alternately  
be connected to VDD through a pull up resistor. TDO must be left  
unconnected. Upon power up, the device comes up in a reset  
state which does not interfere with the operation of the device.  
When the TAP controller is in the Capture IR state, the two least  
significant bits are loaded with a binary “01” pattern to enable for  
fault isolation of the board level serial test path.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between TDI  
and TDO pins. This enables data to be shifted through the SRAM  
with minimal delay. The bypass register is set LOW (VSS) when  
the BYPASS instruction is executed.  
Test Access Port—Test Clock  
The test clock is used only with the TAP controller. All inputs are  
captured on the rising edge of TCK. All outputs are driven from  
the falling edge of TCK.  
Boundary Scan Register  
Test Mode Select  
The boundary scan register is connected to all of the input and  
output pins on the SRAM. Several no connect (NC) pins are also  
included in the scan register to reserve pins for higher density  
devices.  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to leave  
this pin unconnected if the TAP is not used. The pin is pulled up  
internally, resulting in a logic HIGH level.  
The boundary scan register is loaded with the contents of the  
RAM input and output ring when the TAP controller is in the  
Capture-DR state and is then placed between the TDI and TDO  
pins when the controller is moved to the Shift-DR state. Use the  
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions to  
Test Data-In (TDI)  
The TDI pin is used to serially input information into the registers  
and connect to the input of any of the registers. The register  
between TDI and TDO is chosen by the instruction that is loaded  
into the TAP instruction register. For information about loading  
the instruction register, see “TAP Controller State Diagram” on  
page 15 TDI is internally pulled up and unconnected if the TAP  
is unused in an application. TDI is connected to the most signif-  
icant bit (MSb) on any register.  
The “Boundary Scan Order” on page 19 shows the order in which  
the bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSb of the register is connected to  
TDI, and the LSb is connected to TDO.  
Identification (ID) Register  
Test Data-Out (TDO)  
The ID register is loaded with a vendor-specific 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired into  
the SRAM and can be shifted out when the TAP controller is in  
the Shift-DR state. The ID register has a vendor code and other  
information described in the “Identification Register Definitions”  
on page 18.  
The TDO output pin is used to serially clock data-out from the  
registers. The output is active depending upon the current state  
of the TAP state machine (see “Instruction Codes” on page 18).  
The output changes on the falling edge of TCK. TDO is  
connected to the least significant bit (LSb) of any register.  
Performing a TAP Reset  
A Reset is performed by forcing TMS HIGH (VDD) for five rising  
edges of TCK. This RESET does not affect the operation of the  
SRAM and may be performed while the SRAM is operating. At  
power up, the TAP is reset internally to ensure that TDO comes  
up in a high-Z state.  
TAP Instruction Set  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in the “Instruction  
Codes” on page 18. Three of these instructions are listed as  
RESERVED and must not be used. The other five instructions  
are described in this section.  
TAP Registers  
Instructions are loaded into the TAP controller during the Shift-IR  
state when the instruction register is placed between TDI and  
TDO. During this state, instructions are shifted through the  
instruction register through the TDI and TDO pins. To execute  
the instruction after it is shifted in, the TAP controller must be  
moved into the Update-IR state.  
Registers are connected between the TDI and TDO pins and  
enable data to be scanned into and out of the SRAM test circuitry.  
Only one register can be selected at a time through the  
instruction registers. Data is serially loaded into the TDI pin on  
the rising edge of TCK. Data is output on the TDO pin on the  
falling edge of TCK.  
Document Number: 001-06583 Rev. *D  
Page 13 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
IDCODE  
PRELOAD enables an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells  
before the selection of another boundary scan test operation.  
The IDCODE instruction causes a vendor-specific 32-bit code to  
be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO pins and enables  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state. The IDCODE instruction is  
loaded into the instruction register upon power up or whenever  
the TAP controller is supplied a test logic reset state.  
The shifting of data for the SAMPLE and PRELOAD phases can  
occur concurrently when required—that is, while data captured  
is shifted out, shift the preloaded data in.  
BYPASS  
When the BYPASS instruction is loaded in the instruction register  
and the TAP is placed in a Shift-DR state, the bypass register is  
placed between the TDI and TDO pins. The advantage of the  
BYPASS instruction is that it shortens the boundary scan path  
when multiple devices are connected together on a board.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register to  
be connected between the TDI and TDO pins when the TAP  
controller is in a Shift-DR state. The SAMPLE Z command puts  
the output bus into a High-Z state until the next command is  
supplied during the Update IR state.  
EXTEST  
The EXTEST instruction enables the preloaded data to be driven  
out through the system output pins. This instruction also selects  
the boundary scan register to be connected for serial access  
between the TDI and TDO in the shift-DR controller state.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the instruc-  
tion register and the TAP controller is in the Capture-DR state, a  
snapshot of data on the inputs and output pins is captured in the  
boundary scan register.  
EXTEST OUTPUT BUS TRI-STATE  
IEEE Standard 1149.1 mandates that the TAP controller be able  
to put the output bus into a tri-state mode.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because there  
is a large difference in the clock frequencies, it is possible that  
during the Capture-DR state, an input or output undergoes a  
transition. The TAP may then try to capture a signal while in tran-  
sition (metastable state). This does not harm the device, but  
there is no guarantee as to the value that is captured. Repeat-  
able results may not be possible.  
The boundary scan register has a special bit located at bit  
number 47. When this scan cell, called the “extest output bus  
tri-state”, is latched into the preload register during the  
Update-DR state in the TAP controller, it directly controls the  
state of the output (Q-bus) pins, when the EXTEST is entered as  
the current instruction. When HIGH, it enables the output buffers  
to drive the output bus. When LOW, this bit places the output bus  
into a High-Z condition.  
To guarantee that the boundary scan register captures the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture setup plus hold  
times (tCS and tCH). The SRAM clock input might not be captured  
correctly if there is no way in a design to stop (or slow) the clock  
during a SAMPLE/PRELOAD instruction. If this is an issue, it is  
still possible to capture all other signals and simply ignore the  
value of the CK and CK captured in the boundary scan register.  
Set this bit by entering the SAMPLE/PRELOAD or EXTEST  
command, and then shifting the desired bit into that cell, during  
the Shift-DR state. During Update-DR, the value loaded into that  
shift-register cell latches into the preload register. When the  
EXTEST instruction is entered, this bit directly controls the output  
Q-bus pins. Note that this bit is preset HIGH to enable the output  
when the device is powered up, and also when the TAP controller  
is in the Test-Logic-Reset state.  
After the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the boundary  
scan register between the TDI and TDO pins.  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
Document Number: 001-06583 Rev. *D  
Page 14 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
TAP Controller State Diagram  
Figure 2. Tap Controller State Diagram[11]  
TEST-LOGIC  
1
RESET  
0
1
1
1
TEST-LOGIC/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
0
0
1
1
CAPTURE-DR  
CAPTURE-IR  
0
0
SHIFT-DR  
0
SHIFT-IR  
0
1
1
EXIT1-DR  
0
1
EXIT1-IR  
0
1
0
0
PAUSE-DR  
1
PAUSE-IR  
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-DR  
UPDATE-IR  
1
1
0
0
Note  
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.  
Document Number: 001-06583 Rev. *D  
Page 15 of 28  
   
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
TAP Controller Block Diagram  
Figure 3. Tap Controller Block Diagram  
0
Bypass Register  
Selection  
TDI  
Selection  
Circuitry  
2
1
0
0
0
TDO  
Circuitry  
Instruction Register  
29  
31 30  
.
.
2
1
Identification Register  
.
106 .  
.
.
2
1
Boundary Scan Register  
TCK  
TMS  
TAP Controller  
TAP Electrical Characteristics  
The Tap Electrical Characteristics table over the operating range follows.[12, 13, 14]  
Parameter Description Test Conditions  
VOH1 Output HIGH Voltage IOH = 2.0 mA  
Min  
1.4  
1.6  
Max  
Unit  
V
VOH2  
VOL1  
VOL2  
VIH  
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
IOH = 100 μA  
IOL = 2.0 mA  
IOL = 100 μA  
V
0.4  
0.2  
V
V
0.65 VDD VDD + 0.3  
V
VIL  
Input LOW Voltage  
–0.3  
–5  
0.35 VDD  
5
V
IX  
Input and Output Load Current  
GND VI VDD  
μA  
Notes  
12. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.  
13. Overshoot: VIH(AC) < VDDQ + 0.35V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3V (Pulse width less than tCYC/2).  
14. All voltage refer to ground.  
Document Number: 001-06583 Rev. *D  
Page 16 of 28  
       
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
TAP AC Switching Characteristics  
The Tap AC Switching Characteristics over the operating range follows. [15, 16]  
Parameter  
tTCYC  
Description  
Min  
Max  
Unit  
ns  
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH  
50  
tTF  
20  
MHz  
ns  
tTH  
20  
20  
tTL  
TCK Clock LOW  
ns  
Setup Times  
tTMSS  
TMS Setup to TCK Clock Rise  
TDI Setup to TCK Clock Rise  
Capture Setup to TCK Rise  
5
5
5
ns  
ns  
ns  
tTDIS  
tCS  
Hold Times  
tTMSH  
tTDIH  
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
tCH  
Capture Hold after Clock Rise  
Output Times  
tTDOV  
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
10  
ns  
ns  
tTDOX  
0
TAP Timing and Test Condition  
The Tap Timing and Test Conditions for the CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 follows.[16]  
Figure 4. Tap Timing and Test Condition  
0.9V  
ALL INPUT PULSES  
50Ω  
1.8V  
TDO  
0.9V  
0V  
Z = 50  
0
Ω
C = 20 pF  
L
t
t
TH  
TL  
GND  
(a)  
Test Clock  
TCK  
t
TCYC  
t
TMSH  
t
TMSS  
Test Mode Select  
TMS  
t
TDIS  
t
TDIH  
Test Data In  
TDI  
Test Data Out  
TDO  
t
TDOV  
t
TDOX  
Notes  
15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.  
16. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.  
Document Number: 001-06583 Rev. *D  
Page 17 of 28  
   
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Identification Register Definitions  
Value  
Instruction Field  
Description  
CY7C1141V18  
CY7C1156V18  
000  
CY7C1143V18  
000  
CY7C1145V18  
Revision Number  
(31:29)  
000  
000  
Version number.  
Cypress Device ID 11010010101000101 11010010101001101 11010010101010101 11010010101100101 Defines the type of  
(28:12)  
SRAM.  
Cypress JEDEC ID  
(11:1)  
00000110100  
1
00000110100  
1
00000110100  
1
00000110100  
1
Enables unique  
identification of  
SRAM vendor.  
ID Register  
Presence (0)  
Indicates the  
presence of an ID  
register.  
Scan Register Sizes  
Register Name  
Bit Size  
Instruction  
Bypass  
3
1
ID  
32  
107  
Boundary Scan  
Instruction Codes  
Instruction  
EXTEST  
Code  
000  
Description  
Captures the input and output ring contents.  
IDCODE  
001  
Loads the ID register with the vendor ID code and places the register between TDI  
and TDO. This operation does not affect SRAM operation.  
SAMPLE Z  
010  
Captures the input and output contents. Places the boundary scan register between  
TDI and TDO. This forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures the input and output ring contents. Places the boundary scan register  
between TDI and TDO. This operation does not affect the SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do not use: this instruction is reserved for future use.  
Do not use: this instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect  
SRAM operation.  
Document Number: 001-06583 Rev. *D  
Page 18 of 28  
   
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Boundary Scan Order  
Bit #  
0
Bump ID  
6R  
Bit #  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
Bump ID  
11H  
10G  
9G  
Bit #  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
Bump ID  
7B  
6B  
6A  
5B  
5A  
4A  
5C  
4B  
3A  
1H  
1A  
2B  
3B  
1C  
1B  
3D  
3C  
1D  
2C  
3E  
2D  
2E  
1E  
2F  
Bit #  
81  
Bump ID  
3G  
2G  
1J  
1
6P  
82  
2
6N  
83  
3
7P  
11F  
11G  
9F  
84  
2J  
4
7N  
85  
3K  
3J  
5
7R  
86  
6
8R  
10F  
11E  
10E  
10D  
9E  
87  
2K  
1K  
2L  
7
8P  
88  
8
9R  
89  
9
11P  
10P  
10N  
9P  
90  
3L  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
91  
1M  
1L  
10C  
11D  
9C  
92  
93  
3N  
3M  
1N  
2M  
3P  
2N  
2P  
1P  
3R  
4R  
4P  
5P  
5N  
5R  
10M  
11N  
9M  
94  
9D  
95  
11B  
11C  
9B  
96  
9N  
97  
11L  
11M  
9L  
98  
10B  
11A  
Internal  
9A  
99  
100  
101  
102  
103  
104  
105  
106  
10L  
11K  
10K  
9J  
8B  
7C  
9K  
6C  
3F  
10J  
11J  
8A  
1G  
1F  
7A  
Document Number: 001-06583 Rev. *D  
Page 19 of 28  
 
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Power Up Sequence in QDR-II+ SRAM  
DLL Constraints  
During Power Up, when the DOFF is tied HIGH, the DLL gets  
locked after 2048 cycles of stable clock. QDR-II+ SRAMs must  
be powered up and initialized in a predefined manner to prevent  
undefined operations.  
DLL uses K clock as its synchronizing input. The input must  
have low phase jitter, which is specified as tKC Var  
.
The DLL functions at frequencies down to 120 MHz.  
If the input clock is unstable and the DLL is enabled, then the  
DLL may lock onto an incorrect frequency, causing unstable  
SRAM behavior. To avoid this, provide2048 cyclesstable clock  
to relock to the desired clock frequency.  
Power Up Sequence  
ApplypowerwithDOFFtiedHIGH(allotherinputscanbeHIGH  
or LOW)  
Apply VDD before VDDQ  
Apply VDDQ before VREF or at the same time as VREF  
Provide stable power and clock (K, K) for 2048 cycles to lock  
the DLL  
Power Up Waveforms  
Figure 5. Power Up Waveforms  
K
K
Start Normal  
Operation  
Unstable Clock  
> 2048 Stable Clock  
is Stable)  
Clock Start (Clock Starts after V /V  
DD DDQ  
V
/V  
+
V
/V Stable (< 0.1V DC per 50 ns)  
DD DDQ  
DD DDQ  
Fix HIGH (tie to V  
DDQ  
)
DOFF  
Document Number: 001-06583 Rev. *D  
Page 20 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Current into Outputs (LOW)......................................... 20 mA  
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V  
Latch up Current.................................................... > 200 mA  
Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. User guidelines are not tested.  
Storage Temperature ................................ –65°C to + 150°C  
Ambient Temperature with Power Applied. –55°C to + 125°C  
Supply Voltage on VDD Relative to GND .......–0.5V to + 2.9V  
Supply Voltage on VDDQ Relative to GND..... –0.5V to + VDD  
DC Applied to Outputs in High-Z ........0.5V to VDDQ + 0.3V  
DC Input Voltage[13].............................–0.5V to VDDQ + 0.3V  
Operating Range  
Ambient  
[17]  
[17]  
Range  
Commercial  
Industrial  
Temperature (TA)  
VDD  
VDDQ  
0°C to +70°C  
1.8 ± 0.1V  
1.4V to  
VDD  
–40°C to +85°C  
Electrical Characteristics  
The DC Electrical Characteristics over the operating range follows. [14]  
Parameter  
VDD  
Description  
Power Supply Voltage  
IO Supply Voltage  
Test Conditions  
Min  
1.7  
Typ  
Max  
Unit  
1.8  
1.5  
1.9  
V
V
VDDQ  
VOH  
1.4  
VDD  
Output HIGH Voltage  
Output LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Note 18  
Note 19  
VDDQ/2 – 0.12  
VDDQ/2 – 0.12  
VDDQ – 0.2  
VSS  
VDDQ/2 + 0.12  
V
VOL  
VDDQ/2 + 0.12  
V
VOH(LOW)  
VOL(LOW)  
VIH  
IOH = 0.1 mA, Nominal Impedance  
VDDQ  
V
IOL = 0.1 mA, Nominal Impedance  
0.2  
V
VREF + 0.1  
–0.15  
VDDQ + 0.15  
V
VIL  
Input LOW Voltage  
VREF – 0.1  
2
V
IX  
Input Leakage Current  
Output Leakage Current  
Input Reference Voltage[20]  
VDD Operating Supply  
GND VI VDDQ  
2  
μA  
μA  
V
IOZ  
GND VI VDDQ, Output Disabled  
Typical Value = 0.75V  
2  
2
VREF  
0.68  
0.75  
0.95  
663  
708  
766  
201  
212  
227  
[21]  
IDD  
VDD = Max, IOUT = 0 mA, 300 MHz  
mA  
mA  
mA  
mA  
mA  
mA  
f = fmax = 1/tCYC  
333 MHz  
375 MHz  
ISB1  
Automatic Power Down  
Current  
Max VDD  
,
300 MHz  
333 MHz  
375 MHz  
Both Ports Deselected,  
VIN VIH or VIN VIL  
f = fmax =1/tCYC  
,
Inputs Static  
AC Electrical Characteristics  
The AC Electrical Characteristics over the operating range follows.[13]  
Parameter  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
Min  
VREF + 0.2  
–0.24  
Typ  
Max  
Unit  
V
VIH  
VIL  
VDDQ + 0.24  
VREF – 0.2  
V
Notes  
17. Power up: Is based on a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD  
18. Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.  
19. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.  
20. VREF(min) = 0.68V or 0.46VDDQ, whichever is larger, VREF(max) = 0.95V or 0.54 VDDQ, whichever is smaller.  
21. The operation current is calculated with 50% read cycle and 50% write cycle.  
.
Document Number: 001-06583 Rev. *D  
Page 21 of 28  
         
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Capacitance  
Tested initially and after any design or process change that may affect these parameters.  
Parameter  
CIN  
Description  
Input Capacitance  
Test Conditions  
Max  
Unit  
pF  
TA = 25°C, f = 1 MHz,  
5
6
7
V
DD = 1.8V  
CCLK  
Clock Input Capacitance  
Output Capacitance  
pF  
VDDQ = 1.5V  
CO  
pF  
Thermal Resistance  
Tested initially and after any design or process change that may affect these parameters.  
165 FBGA  
Package  
Parameter  
Description  
Test Conditions  
Unit  
ΘJA  
Thermal Resistance  
(junction to ambient)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance, in  
accordance with EIA/JESD51.  
13.48  
°C/W  
ΘJC  
Thermal Resistance  
(junction to case)  
4.15  
°C/W  
AC Test Loads and Waveforms  
Figure 6. AC Test Loads and Waveforms  
V
= 0.75V  
REF  
0.75V  
V
REF  
V
0.75V  
REF  
R = 50  
Ω
OUTPUT  
[22]  
ALL INPUT PULSES  
1.25V  
Z = 50  
0
Ω
OUTPUT  
Device  
Under  
Test  
R = 50  
Ω
L
0.75V  
Device  
Under  
0.25V  
5 pF  
V
= 0.75V  
Slew Rate = 2 V/ns  
REF  
ZQ  
Test  
ZQ  
RQ =  
RQ =  
250Ω  
250Ω  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Notes  
22. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input  
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.  
Document Number: 001-06583 Rev. *D  
Page 22 of 28  
   
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Switching Characteristics  
Over the operating range[22, 23]  
375 MHz  
333 MHz  
300 MHz  
Cypress Consortium  
Parameter Parameter  
Description  
Unit  
Min Max Min Max Min Max  
tPOWER  
tCYC  
tKH  
VDD(Typical) to the First Access[24]  
K Clock Cycle Time  
1
1
1
ms  
ns  
tKHKH  
tKHKL  
tKLKH  
tKHKH  
2.66 8.40 3.0 8.40 3.3 8.40  
Input Clock (K/K) HIGH  
0.425  
0.425  
1.13  
0.425  
0.425  
1.28  
0.425  
0.425  
1.40  
tCYC  
tCYC  
ns  
tKL  
Input Clock (K/K) LOW  
tKHKH  
K Clock Rise to K Clock Rise (rising edge to rising edge)  
Setup Times  
tSA  
tAVKH  
tIVKH  
tIVKH  
Address Setup to K Clock Rise  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
ns  
ns  
ns  
tSC  
Control Setup to K Clock Rise (RPS, WPS)  
tSCDDR  
Double Data Rate Control Setup to Clock (K, K) Rise  
(BWS0, BWS1, BWS2, BWS3)  
0.28  
0.28  
0.28  
tSD  
tDVKH  
D[X:0] Setup to Clock (K/K) Rise  
0.28  
0.28  
0.28  
ns  
Hold Times  
tHA  
tKHAX  
tKHIX  
tKHIX  
Address Hold after K Clock Rise  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
ns  
ns  
ns  
tHC  
Control Hold after K Clock Rise (RPS, WPS)  
tHCDDR  
Double Data Rate Control Hold after Clock (K/K) Rise  
(BWS0, BWS1, BWS2, BWS3)  
0.28  
0.28  
0.28  
tHD  
tKHDX  
D[X:0] Hold after Clock (K/K) Rise  
0.28  
0.28  
0.28  
ns  
Output Times  
tCO  
tCHQV  
K/K Clock Rise to Data Valid  
0.45  
0.45  
0.45  
ns  
ns  
tDOH  
tCHQX  
Data Output Hold after Output K/K Clock Rise  
(Active to Active)  
–0.45  
–0.45  
–0.45  
tCCQO  
tCQOH  
tCQD  
tCHCQV  
tCHCQX  
tCQHQV  
tCQHQX  
tCQHCQL  
K/K Clock Rise to Echo Clock Valid  
Echo Clock Hold after K/K Clock Rise  
Echo Clock High to Data Valid  
0.45  
0.45  
0.45  
ns  
ns  
ns  
ns  
ns  
ns  
–0.45  
–0.45  
–0.45  
0.2  
0.2  
0.2  
tCQDOH  
tCQH  
Echo Clock High to Data Invalid  
Output Clock (CQ/CQ) HIGH[25]  
CQ Clock Rise to CQ Clock Rise[25]  
–0.2  
0.88  
0.88  
–0.2  
1.03  
1.03  
–0.2  
1.15  
1.15  
tCQHCQH tCQHCQH  
(rising edge to rising edge)  
tCHZ  
tCLZ  
tCHQZ  
tCHQX1  
tQVLD  
Clock (K/K) Rise to High-Z (Active to High-Z)[26, 27]  
Clock (K/K) Rise to Low-Z[26, 27]  
Echo Clock High to QVLD Valid[28]  
0.45  
0.45  
0.45  
ns  
ns  
ns  
–0.45  
–0.45  
–0.45  
tQVLD  
–0.20 0.20 –0.20 0.20 –0.20 0.20  
DLL Timing  
tKC Var tKC Var  
tKC lock tKC lock  
Clock Phase Jitter  
0.20  
0.20  
0.20  
ns  
Cycles  
ns  
DLL Lock Time (K)  
K Static to DLL Reset[29]  
2048  
30  
2048  
30  
2048  
30  
tKC Reset tKC Reset  
Notes  
23. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being  
operated and outputs data with the output timings of that frequency range.  
24. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a Read or Write operation can be  
initiated.  
25. These parameters are extrapolated from the input timing parameters (tKHKH – 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already  
included in the tKHKH). These parameters are only guaranteed by design and are not tested in production  
26. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms on page 22. Transition is measured ± 100 mV from steady-state  
voltage.  
27. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO  
.
28. tQVLD spec is applicable for both rising and falling edges of QVLD signal.  
29. Hold to >VIH or <VIL  
.
Document Number: 001-06583 Rev. *D  
Page 23 of 28  
               
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Switching Waveforms  
Read/Write/Deselect Sequence  
Figure 7. Waveform for 2.0 Cycle Read Latency [30, 31, 32]  
NOP  
1
READ  
2
WRITE  
3
READ  
4
WRITE  
5
NOP  
6
7
8
K
t
t
t
t
KH  
KL  
CYC  
KHKH  
K
RPS  
t
t
SC HC  
t
t
SC  
HC  
WPS  
A
A0  
A1  
A2  
A3  
t
t
HD  
t
t
HD  
SA HA  
t
SD  
t
SD  
D10  
D11  
D12  
D13  
D30  
D31  
D32  
D33  
D
t
QVLD  
t
QVLD  
QVLD  
t
DOH  
t
t
CQDOH  
CO  
t
t
CHZ  
t
CLZ  
CQD  
Q
Q22  
Q01  
Q02  
Q23  
Q00  
t
Q03 Q20 Q21  
(Read Latency = 2.0 Cycles)  
CCQO  
CQOH  
CQ  
CQ  
CCQO  
t
t
t
CQHCQH  
CQH  
CQOH  
DON’T CARE  
UNDEFINED  
Notes  
30. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.  
31. Outputs are disabled (High-Z) one clock cycle after a NOP.  
32. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.  
Document Number: 001-06583 Rev. *D  
Page 24 of 28  
     
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com  
for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
375 CY7C1141V18-375BZC  
CY7C1156V18-375BZC  
CY7C1143V18-375BZC  
CY7C1145V18-375BZC  
CY7C1141V18-375BZXC  
CY7C1156V18-375BZXC  
CY7C1143V18-375BZXC  
CY7C1145V18-375BZXC  
CY7C1141V18-375BZI  
CY7C1156V18-375BZI  
CY7C1143V18-375BZI  
CY7C1145V18-375BZI  
CY7C1141V18-375BZXI  
CY7C1156V18-375BZXI  
CY7C1143V18-375BZXI  
CY7C1145V18-375BZXI  
333 CY7C1141V18-333BZC  
CY7C1156V18-333BZC  
CY7C1143V18-333BZC  
CY7C1145V18-333BZC  
CY7C1141V18-333BZXC  
CY7C1156V18-333BZXC  
CY7C1143V18-333BZXC  
CY7C1145V18-333BZXC  
CY7C1141V18-333BZI  
CY7C1156V18-333BZI  
CY7C1143V18-333BZI  
CY7C1145V18-333BZI  
CY7C1141V18-333BZXI  
CY7C1156V18-333BZXI  
CY7C1143V18-333BZXI  
CY7C1145V18-333BZXI  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
Commercial  
Industrial  
Commercial  
Industrial  
Document Number: 001-06583 Rev. *D  
Page 25 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Ordering Information (continued)  
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com  
for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
300 CY7C1141V18-300BZC  
CY7C1156V18-300BZC  
CY7C1143V18-300BZC  
CY7C1145V18-300BZC  
CY7C1141V18-300BZXC  
CY7C1156V18-300BZXC  
CY7C1143V18-300BZXC  
CY7C1145V18-300BZXC  
CY7C1141V18-300BZI  
CY7C1156V18-300BZI  
CY7C1143V18-300BZI  
CY7C1145V18-300BZI  
CY7C1141V18-300BZXI  
CY7C1156V18-300BZXI  
CY7C1143V18-300BZXI  
CY7C1145V18-300BZXI  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
Commercial  
Industrial  
Document Number: 001-06583 Rev. *D  
Page 26 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Package Diagram  
Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180  
BOTTOM VIEW  
PIN 1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
-0.06  
PIN 1 CORNER  
Ø0.50  
(165X)  
+0.14  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00  
5.00  
10.00  
13.00 0.10  
B
13.00 0.10  
B
0.15(4X)  
NOTES :  
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)  
PACKAGE WEIGHT : 0.475g  
JEDEC REFERENCE : MO-216 / DESIGN 4.6C  
PACKAGE CODE : BB0AC  
SEATING PLANE  
C
51-85180-*A  
Document Number: 001-06583 Rev. *D  
Page 27 of 28  
CY7C1141V18, CY7C1156V18  
CY7C1143V18, CY7C1145V18  
Document History Page  
Document Title: CY7C1141V18/CY7C1156V18/CY7C1143V18/CY7C1145V18, 18-Mbit QDR™-II+ SRAM 4-Word Burst Archi-  
tecture (2.0 Cycle Read Latency)  
Document Number: 001-06583  
Orig. of  
Change  
REV.  
ECN No. Issue Date  
Description of Change  
**  
430351  
461654  
See ECN  
See ECN  
NXR  
New data sheet  
*A  
NXR  
Revised the MPNs from  
CY7C1156BV18 to CY7C1156V18  
CY7C1143BV18 to CY7C1143V18  
CY7C1145BV18 to CY7C1145V18  
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH  
,
t
CH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC  
Switching Characteristics table  
Modified Power Up waveform  
*B  
497629  
See ECN  
NXR  
Changed the VDDQ operating voltage to 1.4V to VDD in the Features section, in  
Operating Range table and in the DC Electrical Characteristics table  
Added foot note in page 1  
Changed the Maximum rating of Ambient Temperature with Power Applied from  
–10°C to +85°C to –55°C to +125°C  
Changed VREF (max) spec from 0.85V to 0.95V in the DC Electrical Character-  
istics table and in the note below the table  
Updated foot note 22 to specify Overshoot and Undershoot Spec  
Updated ΘJA and ΘJC values  
Removed x9 part and its related information  
Updated footnote 25  
*C  
1167806  
See ECN VKN/KKVTMP Converted from preliminary to final  
Added x8 and x9 parts  
Changed IDD values from 766 mA to 1020 mA for 375 MHz, 708 mA to 920 mA  
for 333 MHz, 663 mA to 850 mA for 300 MHz  
Changed ISB values from 227 mA to 290 mA for 375 MHz, 212 mA to 260 mA  
for 333 MHz, 201 mA to 250 mA for 300 MHz  
Changed tCYC(max) spec to 8.4 ns for all speed bins  
Changed ΘJA value from 13.48 °C/W to 17.2 °C/W  
Updated Ordering Information table  
*D  
2199066 See ECN  
VKN/AESA Added footnote# 21 related to IDD  
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-06583 Rev. *D  
Revised March 06, 2008  
Page 28 of 28  
QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All  
product and company names mentioned in this document are the trademarks of their respective holders.  

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