Cypress CY7C1041DV33 User Manual

CY7C1041DV33  
4 Mbit (256K x 16) Static RAM  
Features  
Functional Description  
Pin and function compatible with CY7C1041CV33  
The CY7C1041DV33 is a high performance CMOS Static RAM  
organized as 256K words by 16 bits. To write to the device, take  
Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte  
LOW Enable (BLE) is LOW, then data from IO pins (IO to IO )  
High speed  
t = 10 ns  
AA  
0
7
is written into the location specified on the address pins (A to  
0
Low active power  
A
). If Byte HIGH Enable (BHE) is LOW, then data from IO pins  
17  
I  
= 90 mA at 10 ns (industrial)  
Low CMOS standby power  
I = 10 mA  
CC  
(IO to IO ) is written into the location specified on the address  
8
15  
pins (A to A ).  
0
17  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
BLE is LOW, then data from the memory location specified by  
SB2  
2.0V data retention  
Automatic power down when deselected  
TTL compatible inputs and outputs  
Easy memory expansion with CE and OE features  
the address pins appears on IO to IO . If BHE is LOW, then data  
0
7
from memory appears on IO to IO . See the Truth Table on  
8
15  
page 9 for a complete description of read and write modes.  
The input and output pins (IO to IO ) are placed in a high  
0
15  
impedance state when the device is deselected (CE HIGH),  
outputs are disabled (OE HIGH), BHE and BLE are disabled  
(BHE, BLE HIGH), or during a write operation (CE LOW and WE  
LOW).  
Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded  
SOJ, and 44-pin TSOP II packages  
The CY7C1041DV33 is available in a standard 44-pin 400-mil  
wide SOJ and 44-pin TSOP II package with center power and  
ground (revolutionary) pinout and a 48-ball fine-pitch ball grid  
array (FBGA) package.  
Logic Block Diagram  
INPUT BUFFER  
A
0
A
1
A
2
IO –IO  
0
7
A
3
A
256K × 16  
4
IO –IO  
A
6
5
8
15  
A
A
7
A
8
COLUMN  
DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note  
Cypress Semiconductor Corporation  
Document #: 38-05473 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 17, 2008  
   
CY7C1041DV33  
Current into Outputs (LOW) ........................................ 20 mA  
Static Discharge Voltage............. ...............................>2001V  
(MIL-STD-883, Method 3015)  
Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature ................................. –65°C to +150°C  
Latch Up Current..................................................... >200 mA  
Ambient Temperature with  
Power Applied ............................................ –55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND ....–0.3V to +4.6V  
CC  
Ambient  
Temperature  
DC Voltage Applied to Outputs  
in High-Z State .................................... –0.3V to V +0.3V  
Range  
V
Speed  
CC  
CC  
Industrial  
–40°C to +85°C  
3.3V ± 0.3V  
10 ns  
12 ns  
DC Input Voltage ................................ –0.3V to V +0.3V  
CC  
Automotive  
–40°C to +125°C 3.3V ± 0.3V  
DC Electrical Characteristics  
Over the Operating Range  
–10 (Industrial) –12 (Automotive)  
Parameter  
Description  
Test Conditions  
= Min, I = –4.0 mA  
Unit  
Min  
Max  
Min  
Max  
V
V
V
V
I
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Leakage Current  
V
V
2.4  
2.4  
V
V
OH  
CC  
OH  
= Min, I = 8.0 mA  
0.4  
0.4  
OL  
IH  
CC  
OL  
2.0  
–0.3  
–1  
V
+ 0.3  
2.0  
–0.3  
–1  
V
+ 0.3  
V
V
CC  
CC  
[5]  
0.8  
+1  
+1  
0.8  
+1  
+1  
IL  
GND < V < V  
μA  
μA  
IX  
I
CC  
I
Output Leakage  
Current  
GND < V  
< V , Output Disabled  
–1  
–1  
OZ  
OUT  
CC  
I
V
Operating  
V
= Max, f = f  
= 1/t  
RC  
100 MHz  
83 MHz  
66 MHz  
40 MHz  
90  
80  
70  
60  
20  
-
mA  
mA  
mA  
mA  
mA  
CC  
CC  
CC  
MAX  
Supply Current  
95  
85  
75  
25  
I
I
Automatic CE Power Down Max V , CE > V  
Current—TTL Inputs  
SB1  
SB2  
CC  
IH  
V
> V or  
IN  
IN  
IH  
V
< V , f = f  
IL  
MAX  
Automatic CE Power Down Max V  
,
10  
15  
mA  
CC  
Current—CMOS Inputs  
CE > V – 0.3V,  
CC  
V
> V – 0.3V,  
CC  
IN  
or V < 0.3V, f = 0  
IN  
Note  
5. Minimum voltage is –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.  
IH  
CC  
Document #: 38-05473 Rev. *E  
Page 3 of 13  
 
CY7C1041DV33  
Capacitance[6]  
Parameter  
Description  
Input Capacitance  
IO Capacitance  
Test Conditions  
Max  
8
Unit  
pF  
C
C
T = 25°C, f = 1 MHz, V = 3.3V  
IN  
A
CC  
8
pF  
OUT  
Thermal Resistance[6]  
FBGA  
Package  
SOJ  
Package  
TSOP II  
Unit  
Parameter  
Description  
Test Conditions  
Package  
Θ
Thermal Resistance (Junction Still Air, soldered on a 3 × 4.5 inch,  
27.89  
57.91  
50.66  
°C/W  
JA  
to Ambient)  
four layer printed circuit board  
Θ
Thermal Resistance (Junction  
to Case)  
14.74  
36.73  
17.17  
°C/W  
JC  
AC Test Loads and Waveforms  
The AC test loads and waveform diagram follows.  
10 ns device  
ALL INPUT PULSES  
Z = 50Ω  
3.0V  
GND  
OUTPUT  
90%  
10%  
90%  
10%  
50Ω  
30 pF*  
* CAPACITIVE LOAD CONSISTS  
OF ALL COMPONENTS OF THE  
TEST ENVIRONMENT  
1.5V  
(b)  
Fall Time: 1 V/ns  
Rise Time: 1 V/ns  
(a)  
High-Z Characteristics  
R 317Ω  
3.3V  
OUTPUT  
5 pF  
R2  
351Ω  
(c)  
Notes  
6. Tested initially and after any design or process changes that may affect these parameters.  
7. AC characteristics (except High-Z) are tested using the load conditions shown in AC Test Loads and Waveforms (a). High-Z characteristics are tested for all speeds  
using the test load shown in (c).  
Document #: 38-05473 Rev. *E  
Page 4 of 13  
       
CY7C1041DV33  
[8]  
AC Switching Characteristics Over the Operating Range  
–10 (Industrial)  
–12 (Automotive)  
Parameter  
Description  
Unit  
Min  
Max  
Min  
Max  
Read Cycle  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
V
(Typical) to the First Access  
100  
10  
100  
12  
μs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
power  
RC  
CC  
Read Cycle Time  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low-Z  
10  
12  
AA  
3
3
OHA  
ACE  
DOE  
LZOE  
10  
5
12  
6
0
3
0
0
3
0
OE HIGH to High-Z  
5
5
6
6
HZOE  
LZCE  
HZCE  
PU  
CE LOW to Low-Z  
CE HIGH to High-Z  
CE LOW to Power Up  
CE HIGH to Power Down  
Byte Enable to Data Valid  
Byte Enable to Low-Z  
Byte Disable to High-Z  
10  
5
12  
6
PD  
DBE  
LZBE  
HZBE  
0
0
6
6
Write Cycle  
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
10  
7
12  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
SCE  
AW  
7
8
0
0
HA  
0
0
SA  
7
8
PWE  
SD  
Data Setup to Write End  
5
6
Data Hold from Write End  
0
0
HD  
WE HIGH to Low-Z  
3
3
LZWE  
HZWE  
BW  
WE LOW to High-Z  
5
6
Byte Enable to End of Write  
7
8
Notes  
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I /I  
OL OH  
and 30-pF load capacitance.  
9. t  
gives the minimum amount of time that the power supply should be at typical V values until the first memory access is performed.  
POWER  
CC  
10. t  
, t  
, t  
and t  
are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads and Waveforms. Transition is measured when the outputs enter  
HZOE HZCE HZBE,  
HZWE  
a high impedance state.  
11. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given  
HZCE  
LZCE HZOE  
LZOE HZBE  
LZBE  
HZWE  
LZWE  
device.  
Document #: 38-05473 Rev. *E  
Page 5 of 13  
       
CY7C1041DV33  
Data Retention Characteristics Over the Operating Range  
Parameter  
Description  
Conditions  
Min  
Max  
Unit  
V
V
V
for Data Retention  
2.0  
DR  
CC  
I
Data Retention Current  
V
= V = 2.0V,  
Ind’l  
10  
15  
mA  
CCDR  
CC  
DR  
CE > V – 0.3V,  
V
CC  
Auto  
mA  
> V – 0.3V or V < 0.3V  
CC IN  
IN  
[6]  
t
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
CDR  
t
R
RC  
Data Retention Waveform  
DATA RETENTION MODE  
> 2V  
3.0V  
3.0V  
V
VCC  
CE  
DR  
t
t
R
CDR  
Switching Waveforms  
Figure 4. Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Notes  
12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of  
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.  
13. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of t  
and t  
.
HZWE  
SD  
14. No input may exceed V + 0.3V.  
CC  
15. Full device operation requires linear V ramp from V to V  
> 50 μs or stable at V  
> 50 μs.  
CC(min.)  
CC  
DR  
CC(min.)  
16. Device is continuously selected. OE, CE, BHE, and BHE = V .  
IL  
17. WE is HIGH for read cycle.  
Document #: 38-05473 Rev. *E  
Page 6 of 13  
           
CY7C1041DV33  
Switching Waveforms (continued)  
Figure 5. Read Cycle No. 2 (OE Controlled)  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
BHE, BLE  
t
LZOE  
t
HZCE  
t
DBE  
t
LZBE  
t
HZBE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
VCC  
SUPPLY  
CURRENT  
DATA VALID  
t
LZCE  
t
PD  
I
CC
t
PU  
50%  
50%  
I
SB  
Figure 6. Write Cycle No. 1 (CE Controlled)  
t
WC  
ADDRESS  
t
SA  
t
SCE  
CE  
t
AW  
t
HA  
t
PWE  
WE  
t
BW  
BHE, BLE  
t
t
SD  
HD  
DATAIO  
Notes  
18. Address valid prior to or coincident with CE transition LOW.  
19. Data IO is high impedance if OE or BHE and BLE = V  
IH.  
20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.  
Document #: 38-05473 Rev. *E  
Page 7 of 13  
     
CY7C1041DV33  
Switching Waveforms (continued)  
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)  
t
WC  
ADDRESS  
BHE, BLE  
t
SA  
t
BW  
t
AW  
t
HA  
t
PWE  
WE  
CE  
t
SCE  
t
t
HD  
SD  
DATAIO  
Figure 8. Write Cycle No. 3 (WE Controlled, OE HIGH During Write)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
OE  
BHE, BLE  
t
SD  
t
HD  
DATA IO  
NOTE 21  
DATAIN VALID  
t
HZOE  
Note  
21. During this period the IOs are in the output state and input signals should not be applied.  
Document #: 38-05473 Rev. *E  
Page 8 of 13  
 
CY7C1041DV33  
Switching Waveforms (continued)  
Figure 9. Write Cycle No. 4 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
AW  
t
HA  
t
SA  
t
PWE  
WE  
t
BW  
BHE, BLE  
t
HZWE  
t
t
SD  
HD  
DATA IO  
NOTE 21  
t
LZWE  
Truth Table  
IO –IO  
IO –IO  
15  
Mode  
Power  
CE  
OE WE BLE  
BHE  
0
7
8
H
X
L
X
H
H
H
L
X
L
X
High-Z  
High-Z  
Power Down  
Read All Bits  
Standby (I  
)
SB  
L
L
L
L
L
L
L
L
H
L
Data Out  
Data Out  
High-Z  
Data Out  
High-Z  
Active (I  
Active (I  
Active (I  
Active (I  
Active (I  
Active (I  
Active (I  
)
)
)
)
)
)
)
CC  
CC  
CC  
CC  
CC  
CC  
CC  
L
L
Read Lower Bits Only  
Read Upper Bits Only  
Write All Bits  
L
H
L
Data Out  
Data In  
High-Z  
Data In  
High-Z  
X
X
X
H
L
Data In  
Data In  
High-Z  
L
L
H
L
Write Lower Bits Only  
Write Upper Bits Only  
Selected, Outputs Disabled  
L
H
X
H
X
High-Z  
Document #: 38-05473 Rev. *E  
Page 9 of 13  
 
CY7C1041DV33  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
10  
CY7C1041DV33-10BVI  
CY7C1041DV33-10BVXI  
CY7C1041DV33-10BVJXI  
CY7C1041DV33-10VXI  
CY7C1041DV33-10ZSXI  
CY7C1041DV33-12BVXE  
CY7C1041DV33-12VXE  
CY7C1041DV33-12ZSXE  
51-85150  
48-Ball VFBGA  
Industrial  
48-Ball VFBGA (Pb-Free) Pinout - 1  
48-Ball VFBGA (Pb-Free) Pinout - 2  
51-85082  
51-85087  
51-85150  
51-85082  
51-85087  
44-Pin (400-mil) Molded SOJ (Pb-Free)  
44-Pin TSOP II (Pb-Free)  
12  
48-Ball VFBGA (Pb-Free)  
Automotive  
44-Pin (400-mil) Molded SOJ (Pb-Free)  
44-Pin TSOP II (Pb-Free)  
Please contact your local Cypress sales representative for availability of these parts  
Package Diagrams  
Figure 10. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150)  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05(48X)  
A1 CORNER  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
51-85150-*D  
SEATING PLANE  
C
a
Document #: 38-05473 Rev. *E  
Page 10 of 13  
CY7C1041DV33  
Package Diagrams(continued)  
Figure 11. 44-Pin (400-mil) Molded SOJ (51-85082)  
51-85082-*B  
Figure 12. 44-Pin TSOP II (51-85087)  
51-85087-*A  
Document #: 38-05473 Rev. *E  
Page 11 of 13  
CY7C1041DV33  
Document History Page  
Document Title: CY7C1041DV33 4 Mbit (256K x 16) Static RAM  
Document Number: 38-05473  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
201560  
233729  
SWI  
RKF  
See ECN Advance Data sheet for C9 IPP  
*A  
See ECN 1.AC, DC parameters are modified as per EROS(Spec # 01-2165)  
2.Pb-free offering in the ‘Ordering information’  
*B  
351117  
PCI  
See ECN Changed from Advance to Preliminary  
Removed 15 and 20 ns Speed bin  
Corrected DC voltage (min) value in maximum ratings section from - 0.5 to  
- 0.3V  
Redefined I values for Com’l and Ind’l temperature ranges  
CC  
I
(Com’l): Changed from 100, 80 and 67 mA to 90, 80 and 75 mA for 8, 10  
CC  
and 12ns speed bins respectively  
(Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed  
I
CC  
bins respectively  
Added Static Discharge Voltage and latch-up current spec  
Added V  
) spec in Note# 2  
IH(max  
Changed Note# 4 on AC Test Loads  
Changed reference voltage level for measurement of Hi-Z parameters from  
±500 mV to ±200 mV  
Added Data Retention Characteristics/Waveform and footnote # 11, 12  
Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram  
Changed Package Diagram name from 44-Pin TSOP II Z44 to 44-Pin TSOP II  
ZS44 and from 44-Pin (400-mil) Molded SOJ V34 to 44-Pin (400-mil) Molded  
SOJ V44  
Changed part names from Z to ZS in the Ordering Information Table  
Added 8 ns Product Information  
Added Pin-Free Ordering Information  
Shaded Ordering Information Table  
*C  
446328  
480177  
NXR  
VKN  
See ECN Converted from Preliminary to Final  
Removed -8 speed bin  
Removed Commercial Operating Range product information  
Included Automotive Operating Range product information  
Updated Thermal Resistance table  
Updated footnote #8 on High-Z parameter measurement  
Updated the ordering information and replaced Package Name column with  
Package Diagram in the Ordering Information Table  
*D  
*E  
See ECN Added -10BVI product ordering code in the Ordering Information table  
2541850 VKN/PYRS  
07/22/08  
Added -10BVJXI part  
Document #: 38-05473 Rev. *E  
Page 12 of 13  
CY7C1041DV33  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used  
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use  
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support  
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-05473 Rev. *E  
Revised July 17, 2008  
Page 13 of 13  
All product and company names mentioned in this document are the trademarks of their respective holders.  

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