Cypress CY7C1024DV33 User Manual

CY7C1024DV33  
3-Mbit (128K X 24) Static RAM  
Features  
Functional Description  
High speed  
tAA = 10 ns  
Low active power  
ICC = 175 mA at 10 ns  
Low CMOS standby power  
ISB2 = 25 mA  
The CY7C1024DV33 is a high performance CMOS static RAM  
organized as 128K words by 24 bits. This device has an  
automatic power down feature that significantly reduces power  
consumption when deselected.  
To write to the device, enable the chip (CE1 LOW, CE2 HIGH,  
and CE3 LOW), while forcing the Write Enable (WE) input LOW.  
To read from the device, enable the chip by taking CE1 LOW, CE2  
HIGH, and CE3 LOW while forcing the Output Enable (OE) LOW  
and the Write Enable (WE) HIGH. See the Truth Table on page  
7 for a complete description of Read and Write modes.  
Operating voltages of 3.3 ± 0.3V  
2.0V data retention  
The 24 I/O pins (I/O0 to I/O23) are placed in a high impedance  
state when the device is deselected (CE1 HIGH, CE2 LOW, or  
CE3 HIGH) or when the output enable (OE) is HIGH during a  
write operation. (CE1 LOW, CE2 HIGH, CE3 LOW, and WE  
LOW).  
Automatic power down when deselected  
TTL compatible inputs and outputs  
Easy memory expansion with CE1, CE2, and CE3 features  
Available in Pb-free standard 119-ball PBGA  
Logic Block Diagram  
INPUT BUFFER  
I/O0 – I/O23  
128K x 24  
ARRAY  
A(9:0)  
CE1, CE2, CE3  
COLUMN  
DECODER  
WE  
CONTROL LOGIC  
OE  
A(16:10)  
Cypress Semiconductor Corporation  
Document Number: 001-08353 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 6, 2008  
CY7C1024DV33  
DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V  
Current into Outputs (LOW) ........................................ 20 mA  
Static Discharge Voltage............. ...............................>2001V  
(MIL-STD-883, Method 3015)  
Maximum Ratings  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature ................................. –65°C to +150°C  
Ambient Temperature with  
Power Applied ............................................ –55°C to +125°C  
Supply Voltage on VCC Relative to GND [2]....–0.5V to +4.6V  
Latch Up Current..................................................... >200 mA  
Operating Range  
Ambient  
Temperature  
DC Voltage Applied to Outputs  
Range  
VCC  
in High Z State [2]................................... –0.5V to VCC + 0.5V  
Industrial  
–40°C to +85°C  
3.3V ± 0.3V  
DC Electrical Characteristics  
Over the Operating Range  
–10  
Parameter  
Description  
Test Conditions [3]  
Unit  
Min  
Max  
VOH  
VOL  
VIH  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
VCC = Min, IOH = –4.0 mA  
VCC = Min, IOL = 8.0 mA  
2.4  
V
V
0.4  
VCC + 0.3  
0.8  
2.0  
–0.3  
–1  
V
[2]  
VIL  
V
IIX  
Input Leakage Current  
Output Leakage Current  
GND < VI < VCC  
+1  
μA  
μA  
mA  
IOZ  
ICC  
GND < VOUT < VCC, output disabled  
–1  
+1  
VCC Operating Supply  
Current  
VCC = Max, f = fMAX = 1/tRC  
IOUT = 0 mA CMOS levels  
175  
ISB1  
ISB2  
Automatic CE Power Down Max VCC, CE > VIH  
30  
25  
mA  
mA  
Current —TTL Inputs  
VIN > VIH or VIN < VIL, f = fMAX  
Automatic CE Power Down Max VCC, CE > VCC – 0.3V,  
Current — CMOS Inputs  
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0  
Capacitance  
Tested initially and after any design or process changes that may affect these parameters.  
Parameter  
CIN  
Description  
Input Capacitance  
I/O Capacitance  
Test Conditions  
Max  
Unit  
TA = 25°C, f = 1 MHz, VCC = 3.3V  
8
pF  
pF  
COUT  
10  
Thermal Resistance  
Tested initially and after any design or process changes that may affect these parameters.  
119-Ball  
PBGA  
Parameter  
Description  
Test Conditions  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Still air, soldered on a 3 × 4.5 inch,  
four layer printed circuit board  
20.31  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
8.35  
°C/W  
Notes  
2.  
V
(min) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.  
IH CC  
IL  
3. CE refers to a combination of CE , CE , and CE . CE is LOW when CE , CE are LOW and CE is HIGH. CE is HIGH when CE is HIGH, or CE is LOW, or CE is HIGH.  
1
2
3
1
3
2
1
2
3
Document Number: 001-08353 Rev. *C  
Page 3 of 9  
   
CY7C1024DV33  
Figure 2. AC Test Loads and Waveform[4]  
50Ω  
R1 317 Ω  
3.3V  
= 1.5V  
VTH  
OUTPUT  
OUTPUT  
Z = 50Ω  
0
30 pF*  
R2  
351Ω  
5 pF*  
*
Including jig  
(a)  
and scope  
(b)  
*Capacitive Load consists of all  
components of the test environment  
All input pulses  
3.0V  
90%  
10%  
90%  
10%  
GND  
Rise Time > 1V/ns  
Fall Time:> 1V/ns  
(c)  
AC Switching Characteristics  
Over the Operating Range [5]  
–10  
Parameter  
Description  
Unit  
Max  
Min  
Read Cycle  
[6]  
tpower  
tRC  
VCC(Typical) to the First Access  
100  
10  
μs  
Read Cycle Time  
ns  
tAA  
Address to Data Valid  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
Data Hold from Address Change  
CE Active LOW to Data Valid [3]  
OE LOW to Data Valid  
OE LOW to Low Z [7]  
OE HIGH to High Z [7]  
CE Active LOW to Low Z [3, 7]  
CE Deselect HIGH to High Z [3, 7]  
CE Active LOW to Power Up [3, 8]  
CE Deselect HIGH to Power Down [3, 8]  
3
10  
5
1
3
0
5
5
tPD  
10  
Notes  
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). 100 μs (t  
) after reaching the minimum operating  
DD  
power  
V
, normal SRAM operation can begin including reduction in V to the data retention (V  
, 2.0V) voltage.  
DD  
DD  
CCDR  
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use  
output loading as shown in part a) of Figure 2, unless specified otherwise.  
6.  
7.  
t
gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.  
CC  
POWER  
, t  
t
, t  
, t  
, t  
, and t  
are specified with a load capacitance of 5 pF as in part (b) of Figure 2. Transition is measured ±200 mV from steady state  
HZOE HZCE HZWE LZOE LZCE  
LZWE  
voltage.  
8. These parameters are guaranteed by design and are not tested.  
Document Number: 001-08353 Rev. *C  
Page 4 of 9  
           
CY7C1024DV33  
AC Switching Characteristics (continued)  
Over the Operating Range [5]  
–10  
Parameter  
Description  
Unit  
Min  
Max  
Write Cycle [9, 10]  
tWC  
tSCE  
tAW  
Write Cycle Time  
10  
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE active LOW to Write End [3]  
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
7
tHA  
0
tSA  
0
tPWE  
tSD  
7
Data Setup to Write End  
Data Hold from Write End  
WE HIGH to Low Z [7]  
5.5  
0
tHD  
tLZWE  
tHZWE  
3
WE LOW to High Z [7]  
5
Data Retention Characteristics  
Over the Operating Range  
Parameter  
VDR  
Description  
VCC for Data Retention  
Conditions [3]  
Min  
Typ  
Max  
Unit  
2
V
ICCDR  
Data Retention Current  
VCC = 2V, CE > VCC – 0.2V,  
VIN > VCC – 0.2V or VIN < 0.2V  
25  
mA  
[11]  
tCDR  
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
[12]  
tR  
tRC  
Data Retention Waveform  
DATA RETENTION MODE  
3.0V  
3.0V  
VCC  
CE  
V
DR  
>
2V  
t
t
R
CDR  
Notes  
9. The internal write time of the memory is defined by the overlap of CE and CE and CE LOW and WE LOW. Chip enables must be active and WE must be LOW to  
1
2
3
initiate a write. The transition of any of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that  
terminates the write.  
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t  
11. Tested initially and after any design or process changes that may affect these parameters.  
and t  
.
HZWE  
SD  
12. Full device operation requires linear V ramp from V to V  
> 50 μs or stable at V  
> 50 μs.  
CC(min)  
CC  
DR  
CC(min)  
Document Number: 001-08353 Rev. *C  
Page 5 of 9  
       
CY7C1024DV33  
Switching Waveforms  
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [13, 14]  
tRC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Figure 4. Read Cycle No. 2 (OE Controlled) [3, 14, 15]  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
V
CC  
ICC  
t
PU  
SUPPLY  
CURRENT  
50%  
50%  
ISB  
Figure 5. Write Cycle No. 1 (CE Controlled) [3, 16, 17]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
SCE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
Notes  
13. Device is continuously selected. OE, CE = V .  
IL  
14. WE is HIGH for read cycle.  
15. Address valid before or similar to CE transition LOW.  
16. Data I/O is high impedance if OE = V  
.
IH  
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.  
Document Number: 001-08353 Rev. *C  
Page 6 of 9  
         
CY7C1024DV33  
Switching Waveforms (continued)  
Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
OE  
t
t
SD  
HD  
DATA VALID  
IN  
DATA I/O  
NOTE 18  
t
HZOE  
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA I/O  
NOTE 18  
DATA VALID  
t
t
LZWE  
HZWE  
Truth Table  
CE1  
H
X
CE2  
X
CE3  
X
OE  
WE  
X
I/O0 – I/O23  
Mode  
Power  
X
X
X
L
High Z  
High Z  
High Z  
Power Down  
Power Down  
Power Down  
Read  
Standby (ISB  
)
)
)
L
X
X
Standby (ISB  
Standby (ISB  
X
X
H
L
X
L
H
H
Full Data Out  
Full Data In  
High Z  
Active (ICC  
)
)
)
L
H
L
X
H
L
Write  
Active (ICC  
L
H
L
H
Selected, Outputs Disabled Active (ICC  
Note  
18. During this period, the I/Os are in the output state and input signals are not applied.  
Document Number: 001-08353 Rev. *C  
Page 7 of 9  
   
CY7C1024DV33  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
Ordering Code  
(ns)  
Package Type  
10  
CY7C1024DV33-10BGXI  
51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free) Industrial  
Package Diagram  
Figure 8. 119-Ball PBGA (14 x 22 x 2.4 mm)  
51-85115-*B  
Document Number: 001-08353 Rev. *C  
Page 8 of 9  
CY7C1024DV33  
Document History Page  
Document Title: CY7C1024DV33, 3-Mbit (128K X 24) Static RAM  
Document Number: 001-08353  
Orig. of  
Change  
Submission  
Date  
Rev. ECN No.  
Description of Change  
**  
469517  
499604  
NXR  
NXR  
See ECN New data sheet  
*A  
See ECN Added note 1 for NC pins  
Changed ICC specification from 150 mA to 185 mA  
Updated Test Condition for ICC in DC Electrical Characteristics table  
Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics Table  
on page 4  
*B  
*C  
1462586 VKN/SFV  
2604677 VKN/PYRS  
See ECN Converted from preliminary to final  
Updated block diagram  
Changed ICC specification from 185 mA to 225 mA  
Updated thermal specs  
11/12/08 Removed Commercial operating range, Added Industrial operating range  
Removed 8 ns speed bin, Added 10 ns speed bin  
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© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-08353 Rev. *C  
Revised November 6, 2008  
Page 9 of 9  
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