Cypress CY7C1019CV33 User Manual

CY7C1019CV33  
128K x 8 Static RAM  
device has an automatic power-down feature that significantly  
reduces power consumption when deselected.  
Features  
• Pin and function compatible with CY7C1019BV33  
• High speed  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O through I/O ) is then written into the location  
0
7
— t = 10 ns  
AA  
specified on the address pins (A through A ).  
0
16  
• CMOS for optimum speed/power  
• Data retention at 2.0V  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• Center power/ground pinout  
• Automatic power-down when deselected  
• Easy memory expansion with CE and OE options  
The eight input/output pins (I/O through I/O ) are placed in a  
0
7
• Available in Pb-free and non Pb-free 48-ball VFBGA,  
32-pin TSOP II and 400-mil SOJ package  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description  
The CY7C1019CV33 is available in Standard 48-ball FBGA,  
32-pin TSOP II and 400-mil-wide SOJ packages  
The CY7C1019CV33 is a high-performance CMOS static  
RAM organized as 131,072 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and tri-state drivers. This  
Logic Block Diagram  
Pin Configuration  
SOJ/TSOP II  
Top View  
A
A
1
A
A
32  
1
0
16  
31  
30  
2
3
4
5
6
15  
A
A
14  
A
13  
2
I/O  
A
29  
28  
3
0
INPUT BUFFER  
CE  
OE  
I/O  
I/O  
I/O  
27  
26  
1
I/O  
A
0
0
1
7
A
A
2
1
I/O  
V
7
8
9
10  
11  
12  
13  
6
I/O  
2
25  
24  
23  
22  
21  
V
CC  
SS  
A
3
V
A
I/O  
V
CC  
I/O  
4
SS  
128K x 8  
ARRAY  
3
A
5
I/O  
I/O  
2
3
5
4
A
6
I/O  
I/O  
A
4
A
7
A
8
WE  
A
4
12  
I/O  
A
11  
5
20  
19  
A
5
A
10  
14  
15  
16  
I/O  
6
POWER  
DOWN  
A
6
A
9
A
8
COLUMN  
DECODER  
18  
17  
CE  
A
7
I/O  
WE  
7
OE  
Cypress Semiconductor Corporation  
Document #: 38-05130 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 3, 2006  
CY7C1019CV33  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
Static Discharge Voltage............................................>2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-up Current......................................................>200 mA  
Storage Temperature .................................65°C to +150°C  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Ambient  
[2]  
Supply Voltage on V to Relative GND .... –0.5V to +4.6V  
CC  
Range  
Commercial  
Industrial  
Temperature  
0°C to +70°C  
–40°C to +85°C  
V
CC  
DC Voltage Applied to Outputs  
3.3V ± 10%  
[2]  
in High-Z State ....................................–0.5V to V + 0.5V  
CC  
3.3V ± 10%  
[2]  
DC Input Voltage .................................–0.5V to V + 0.5V  
CC  
Electrical Characteristics Over the Operating Range  
–10  
–12  
–15  
Parameter  
Description  
Test Conditions  
= Min.,  
CC  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
V
Output HIGH Voltage  
V
2.4  
2.4  
2.4  
V
OH  
I
= –4.0 mA  
OH  
V
Output LOW Voltage  
V
= Min.,  
= 8.0 mA  
0.4  
0.4  
0.4  
+ 0.3  
V
OL  
CC  
I
OL  
V
V
I
Input HIGH Voltage  
2.0  
–0.3  
–1  
V
+ 0.3  
2.0  
–0.3  
–1  
V
+ 0.3  
2.0  
–0.3  
–1  
V
CC  
V
V
IH  
CC  
CC  
[2]  
Input LOW Voltage  
0.8  
0.8  
+1  
+1  
0.8  
+1  
+1  
IL  
Input Leakage Current GND < V < V  
CC  
+1  
+1  
µA  
µA  
IX  
I
I
Output Leakage  
Current  
GND < V < V ,  
CC  
Output Disabled  
–1  
–1  
–1  
OZ  
I
I
V
Operating  
V
= Max.,  
= 0 mA,  
80  
15  
5
75  
15  
5
70  
15  
5
mA  
mA  
mA  
CC  
CC  
CC  
Supply Current  
I
OUT  
f = f  
= 1/t  
MAX  
RC  
I
I
Automatic CE  
Power-down Current  
—TTL Inputs  
Max. V , CE > V  
CC IH  
SB1  
V
V
> V or  
IN  
IN  
IH  
< V , f = f  
IL  
MAX  
Automatic CE  
Max. V  
,
CC  
SB2  
Power-down Current CE > V – 0.3V,  
CC  
—CMOS Inputs  
V
> V – 0.3V,  
IN CC  
or V < 0.3V, f = 0  
IN  
Capacitance[3]  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
Unit  
pF  
C
C
Input Capacitance  
Output Capacitance  
8
8
IN  
A
V
= 5.0V  
CC  
pF  
OUT  
Notes:  
2. V (min.) = –2.0V for pulse durations of less than 20 ns.  
IL  
3. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05130 Rev. *F  
Page 3 of 10  
CY7C1019CV33  
AC Test Loads and Waveforms[4]  
High-Z characteristics:  
R 317  
ALL INPUT PULSES  
R 317Ω  
3.0V  
3.3V  
90%  
10%  
90%  
10%  
3.3V  
OUTPUT  
OUTPUT  
GND  
R2  
30 pF  
R2  
351Ω  
351Ω  
5 pF  
(b)  
Fall Time: 1 V/ns  
Rise Time: 1 V/ns  
(a)  
(c)  
[5]  
Switching Characteristics Over the Operating Range  
-10  
-12  
-15  
Parameter  
Description  
Min.  
10  
3
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
Read Cycle  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
12  
3
15  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
10  
12  
15  
AA  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
10  
5
12  
6
15  
7
0
3
0
0
3
0
0
3
0
[6, 7]  
5
5
6
6
7
7
OE HIGH to High Z  
[7]  
CE LOW to Low Z  
[6, 7]  
CE HIGH to High Z  
[8]  
CE LOW to Power-Up  
PU  
[8]  
10  
12  
15  
CE HIGH to Power-Down  
PD  
[9, 10]  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
10  
8
12  
9
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
SCE  
AW  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
8
9
0
0
HA  
0
0
0
SA  
7
8
10  
8
WE Pulse Width  
PWE  
SD  
Data Set-Up to Write End  
5
6
Data Hold from Write End  
0
0
0
HD  
[7]  
3
3
3
WE HIGH to Low Z  
LZWE  
HZWE  
[6, 7]  
5
6
7
WE LOW to High Z  
Notes:  
4. AC characteristics (except High-Z) for all speeds are tested using the Thevenin load shown in Figure (a). High-Z characteristics are tested for all speeds using  
the test load shown in Figure (c).  
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.  
6. t  
, t  
, and t  
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
HZOE HZCE  
HZWE  
7. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
8. This parameter is guaranteed by design and is not tested.  
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of  
any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t  
and t  
.
HZWE  
SD  
Document #: 38-05130 Rev. *F  
Page 4 of 10  
CY7C1019CV33  
Switching Waveforms  
[11, 12]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
[12, 13]  
Read Cycle No. 2 (OE Controlled)  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
ICC  
t
PU  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
ISB  
[14, 15]  
Write Cycle No. 1 (CE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
SCE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
Notes:  
11. Device is continuously selected. OE, CE = V .  
IL  
12. WE is HIGH for read cycle.  
13. Address valid prior to or coincident with CE transition LOW.  
14. Data I/O is high impedance if OE = V  
.
IH  
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
Document #: 38-05130 Rev. *F  
Page 5 of 10  
CY7C1019CV33  
Switching Waveforms (continued)  
[14, 15]  
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)  
t
WC  
ADDRESS  
t
SCE  
CE  
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
OE  
t
t
SD  
HD  
DATA VALID  
DATA I/O  
IN  
NOTE 16  
t
HZOE  
[15]  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
NOTE 16  
DATA I/O  
DATA VALID  
t
t
LZWE  
HZWE  
Truth Table  
I/O –I/O  
Mode  
Power  
CE  
H
L
OE  
WE  
X
0
7
X
L
High Z  
Power-Down  
Read  
Standby (I  
)
SB  
H
Data Out  
Data In  
High Z  
Active (I  
Active (I  
Active (I  
)
)
)
CC  
CC  
CC  
L
X
H
L
Write  
L
H
Selected, Outputs Disabled  
Note:  
16. During this period the I/Os are in the output state and input signals should not be applied.  
Document #: 38-05130 Rev. *F  
Page 6 of 10  
CY7C1019CV33  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
10  
CY7C1019CV33-10VC  
CY7C1019CV33-10ZXC  
CY7C1019CV33-10ZXI  
CY7C1019CV33-12VC  
CY7C1019CV33-12ZC  
CY7C1019CV33-12ZXC  
CY7C1019CV33-12VI  
CY7C1019CV33-12BVXI  
CY7C1019CV33-15VC  
CY7C1019CV33-15VXC  
CY7C1019CV33-15ZXC  
CY7C1019CV33-15ZXI  
51-85033 32-pin 400-Mil Molded SOJ  
51-85095 32-pin TSOP II (Pb-Free)  
32-pin TSOP II (Pb-Free)  
Commercial  
Industrial  
12  
15  
51-85033 32-pin 400-Mil Molded SOJ  
51-85095 32-pin TSOP II  
Commercial  
32-pin TSOP II (Pb-Free)  
51-85033 32-pin 400-Mil Molded SOJ  
51-85150 48-ball VFBGA (Pb-Free)  
51-85033 32-pin 400-Mil Molded SOJ  
51-85033 32-pin 400-Mil Molded SOJ (Pb-Free)  
51-85095 32-pin TSOP II (Pb-Free)  
51-85095 32-pin TSOP II (Pb-Free)  
Industrial  
Commercial  
Industrial  
Package Diagrams  
32-pin (400-Mil) Molded SOJ (51-85033)  
51-85033-*B  
Document #: 38-05130 Rev. *F  
Page 7 of 10  
CY7C1019CV33  
Package Diagrams (continued)  
32-pin TSOP II (51-85095)  
51-85095-**  
Document #: 38-05130 Rev. *F  
Page 8 of 10  
CY7C1019CV33  
Package Diagrams (continued)  
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.30 0.05(48X)  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
51-85150-*D  
SEATING PLANE  
C
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05130 Rev. *F  
Page 9 of 10  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1019CV33  
Document History Page  
Document Title: CY7C1019CV33 128K x 8 Static RAM  
Document Number: 38-05130  
Issue  
Date  
Orig. of  
Change  
REV.  
**  
ECN NO.  
109245  
113431  
115047  
119796  
123030  
419983  
Description of Change  
12/16/01  
04/10/02  
08/01/02  
10/11/02  
12/17/02  
See ECN  
HGK  
NSL  
HGK  
DFP  
DFP  
NXR  
New Data Sheet  
AC Test Loads split based on speed  
*A  
*B  
Added TSOP II Package and I Temp. Improved I limits  
CC  
*C  
*D  
*E  
Updated standby current from 5 nA to 5 mA  
Updated Truth Table to reflect single Chip Enable option  
Added 48-ball VFBGA Package  
Added lead-free parts in Ordering Information Table  
Replaced Package Name column with Package Diagram in the Ordering  
Information Table  
*F  
493543  
See ECN  
NXR  
Removed 8 ns speed bin from Product offering  
Added note #1 on page #2  
Changed the description of I from Input Load Current to  
IX  
Input Leakage Current in DC Electrical Characteristics table  
Removed I parameter from DC Electrical Characteristics table  
OS  
Updated Ordering Information  
Document #: 38-05130 Rev. *F  
Page 10 of 10  

HP Hewlett Packard ProLiant DL160 User Manual
Fujitsu Computer Monitor L17 2 User Manual
Electrolux MGH 621 User Manual
Eizo EV2313W User Manual
Dell UltraScan 1476T User Manual
CDA HCG501 User Manual
Black Decker Perfect Broil CTO4400B 11G User Manual
Black Box Computer Hardware IC113C User Manual
Asus Computer Monitor VH236 User Manual
Aluratek AHDURS350F500 User Manual