Cypress CY62167EV30 User Manual

CY62167EV30 MoBL®  
16-Mbit (1M x 16 / 2M x 8) Static RAM  
low active current. Ultra low active current is ideal for providing  
More Battery Life(MoBL ) in portable applications such as  
Features  
®
cellular telephones. The device also has an automatic power  
down feature that reduces power consumption by 99 percent  
when addresses are not toggling. Place the device into standby  
mode when deselected (CE HIGH or CE LOW or both BHE and  
TSOP I Package Configurable as 1M x 16 or 2M x 8 SRAM  
Very High Speed: 45 ns  
Temperature Ranges  
1
2
BLE are HIGH). The input and output pins (I/O through I/O  
)
0
15  
Industrial: –40°C to +85°C  
Automotive-A: –40°C to +85°C  
are placed in a high impedance state when: the device is  
deselected (CE HIGH or CE LOW), outputs are disabled (OE  
1
2
Wide Voltage Range: 2.20V to 3.60V  
HIGH), both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH), or a write operation is in progress (CE LOW,  
1
Ultra Low Standby Power  
Typical standby current: 1.5 μA  
Maximum standby current: 12 μA  
CE HIGH and WE LOW).  
2
To write to the device, take Chip Enables (CE LOW and CE  
1
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O through I/O ) is  
Ultra Low Active Power  
0
7
written into the location specified on the address pins (A through  
Typical active current: 2.2 mA @ f = 1 MHz  
0
A
). If Byte High Enable (BHE) is LOW, then data from the I/O  
19  
Easy Memory Expansion with CE , CE , and OE Features  
1
2
pins (I/O through I/O ) is written into the location specified on  
8
15  
the address pins (A through A ).  
0
19  
Automatic Power Down when Deselected  
To read from the device, take Chip Enables (CE LOW and CE  
1
2
CMOS for Optimum Speed and Power  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appears  
Offered in Pb-free 48-Ball VFBGA and 48-Pin TSOP I  
Packages  
on I/O to I/O . If Byte High Enable (BHE) is LOW, then data from  
0
7
memory appears on I/O to I/O . See the “Truth Table” on  
page 9 for a complete description of read and write modes.  
Functional Description  
8
15  
The CY62167EV30 is a high performance CMOS static RAM  
organized as 1M words by 16 bits or 2M words by 8 bits. This  
device features an advanced circuit design that provides an ultra  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A
A
A
A
A
A
A
A
A
A
A
10  
9
8
7
6
1M × 16 / 2M x 8  
5
4
3
2
1
0
RAM Array  
IO –IO  
0
7
IO –IO  
8
15  
COLUMN DECODER  
BYTE  
BHE  
WE  
CE2  
CE  
CE2  
1
PowerDown  
Circuit  
CE  
1
OE  
BHE  
BLE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05446 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 23, 2009  
CY62167EV30 MoBL®  
[6, 7]  
DC Input Voltage  
...........–0.3V to 3.9V (V (max) + 0.3V  
Maximum Ratings  
CC  
Output Current into Outputs (LOW) ............................ 20 mA  
Exceeding the maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Static Discharge Voltage........................................... >2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature ................................ –65°C to + 150°C  
Latch up Current...................................................... >200 mA  
Ambient Temperature with  
Power Applied ........................................... –55°C to + 125°C  
Operating Range  
Supply Voltage to Ground  
Potential .................................–0.3V to 3.9V V  
Ambient  
V
CC  
Device  
Range  
+ 0.3V  
+ 0.3V  
Temperature  
CC(max)  
CC(max)  
DC Voltage Applied to Outputs  
CY62167EV30LL Industrial/ –40°Cto+85°C 2.2V to 3.6V  
Auto-A  
[6, 7]  
in High Z State  
..................–0.3V to 3.9V V  
Electrical Characteristics  
Over the Operating Range  
45 ns (Industrial/Auto-A)  
Parameter  
Description  
Test Conditions  
Unit  
Min  
2.0  
2.4  
Typ  
Max  
V
Output HIGH Voltage  
2.2 < V < 2.7  
I
I
I
I
= –0.1 mA  
= –1.0 mA  
= 0.1 mA  
= 2.1mA  
V
V
OH  
OL  
IH  
CC  
OH  
OH  
OL  
OL  
2.7 < V < 3.6  
CC  
V
V
V
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
2.2 < V < 2.7  
0.4  
0.4  
V
CC  
2.7 < V < 3.6  
V
CC  
2.2 < V < 2.7  
1.8  
2.2  
V
V
+ 0.3V  
V
CC  
CC  
CC  
2.7 < V < 3.6  
+ 0.3V  
0.6  
V
CC  
2.2 < V < 2.7  
–0.3  
–0.3  
–0.3  
–1  
V
IL  
CC  
2.7 < V < 3.6  
For VFBGA package  
For TSOP I package  
0.8  
V
CC  
0.7  
V
I
Input Leakage Current  
Output Leakage Current  
GND < V < V  
CC  
+1  
+1  
30  
μA  
μA  
mA  
mA  
IX  
I
I
I
GND < V < V , Output Disabled  
–1  
OZ  
O
CC  
V
Operating Supply  
f = f  
= 1/t  
V
= V (max)  
= 0 mA  
25  
CC  
CC  
MAX  
RC  
CC  
CC  
Current  
I
OUT  
f = 1 MHz  
2.2  
4.0  
CMOS levels  
I
I
Automatic CE Power Down  
Current—CMOS Inputs  
CE > V 0.2V or CE < 0.2V  
1.5  
1.5  
12  
12  
μA  
SB1  
1
CC  
2
V
> V 0.2V, V < 0.2V,  
IN  
f = f  
CC IN  
(Address and Data Only),  
MAX  
f = 0 (OE, WE, BHE and BLE), V = 3.60V  
CC  
Automatic CE Power Down  
Current—CMOS Inputs  
CE > V 0.2V or CE < 0.2V,  
μA  
SB2  
1
CC  
2
V
> V 0.2V or V < 0.2V,  
IN  
CC IN  
f = 0, V = 3.60V  
CC  
Capacitance  
Tested initially and after any design or process changes that may affect these parameters.  
Parameter Description Test Conditions  
Input Capacitance T = 25°C, f = 1 MHz,  
Output Capacitance  
Max  
10  
Unit  
pF  
C
IN  
A
V
= V  
CC(typ)  
CC  
C
10  
pF  
OUT  
Notes  
6. V (min) = –2.0V for pulse durations less than 20 ns.  
IL  
7.  
V
(max) = V + 0.75V for pulse durations less than 20 ns.  
IH CC  
8. Full Device AC operation assumes a 100 μs ramp time from 0 to V (min) and 200 μs wait time after V stabilization.  
CC  
CC  
9. Under DC conditions the device meets a V of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7V. This is  
IL  
applicable to TSOP I package only.  
10. Only chip enables (CE and CE ), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the I / I spec. Other inputs can be left floating  
SB2 CCDR  
1
2
Document #: 38-05446 Rev. *E  
Page 3 of 14  
         
CY62167EV30 MoBL®  
Thermal Resistance  
Tested initially and after any design or process changes that may affect these parameters.  
VFBGA  
VFBGA  
Parameter  
Description  
Test Conditions  
TSOP I  
Unit  
(6 x 7 x 1mm) (6 x 8 x 1mm)  
Θ
Thermal Resistance Still Air, soldered on a 3 × 4.5 inch,  
(Junction to Ambient) two-layer printed circuit board  
27.74  
9.84  
55  
16  
60  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
4.3  
°C/W  
JC  
Shaded areas contain preliminary information.  
Figure 3. AC Test Loads and Waveforms  
ALL INPUT PULSES  
90%  
10%  
R1  
V
V
CC  
OUTPUT  
CC  
90%  
10%  
GND  
Fall Time = 1 V/ns  
R2  
30 pF  
Rise Time = 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to: THÉVENIN EQUIVALENT  
R
TH  
OUTPUT  
V
Parameters  
2.2V to 2.7V  
16667  
2.7V to 3.6V  
1103  
Unit  
Ω
R1  
R2  
15385  
1554  
Ω
R
8000  
645  
Ω
TH  
V
1.20  
1.75  
V
TH  
Data Retention Characteristics  
Over the Operating Range  
Parameter  
Description  
Conditions  
Min Typ  
Max Unit  
V
I
V
for Data Retention  
1.5  
V
DR  
CC  
Data Retention Current  
V
= 1.5V to 3.0V, CE > V 0.2V, CE Industrial/ -45ZXI  
8
μA  
CCDR  
CC  
1
CC  
2
Auto-A (TSOP I)  
< 0.2V, V > V 0.2V or V < 0.2V  
IN  
CC  
IN  
V
V
= 1.5V, CE > V 0.2V, CE < 0.2V, Industrial -45BAXI/  
10  
μA  
CC  
1
CC  
2
-45BVXI/  
-45BVI  
> V 0.2V or V < 0.2V  
IN  
CC  
IN  
(VFBGA)  
t
t
Chip Deselect to Data  
Retention Time  
0
ns  
ns  
CDR  
R
Operation Recovery Time  
t
RC  
Figure 4. Data Retention Waveform  
DATA RETENTION MODE  
V
(min)  
> 1.5 V  
V
t
(min)  
V
CC  
V
CC  
DR  
CC  
t
CDR  
R
CE or  
1
BHE.BLE  
or  
CE  
2
Notes  
11. Tested initially and after any design or process changes that may affect these parameters.  
12. Full device operation requires linear V ramp from V to V (min) > 100 μs or stable at V (min) > 100 μs.  
CC  
DR  
CC  
CC  
13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.  
Document #: 38-05446 Rev. *E  
Page 4 of 14  
       
CY62167EV30 MoBL®  
Switching Characteristics  
Over the Operating Range  
45 ns (Industrial/Auto-A)  
Unit  
Parameter  
Description  
Min  
Max  
READ CYCLE  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
45  
AA  
Data Hold from Address Change  
CE LOW and CE HIGH to Data Valid  
10  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
45  
22  
1
2
OE LOW to Data Valid  
OE LOW to LOW Z  
5
10  
0
OE HIGH to High Z  
CE LOW and CE HIGH to Low Z  
18  
18  
1
2
CE HIGH and CE LOW to High Z  
1
2
CE LOW and CE HIGH to Power Up  
1
2
CE HIGH and CE LOW to Power Down  
45  
45  
PD  
1
2
BLE / BHE LOW to Data Valid  
DBE  
LZBE  
HZBE  
BLE / BHE LOW to Low Z  
10  
BLE / BHE HIGH to HIGH Z  
18  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
45  
35  
35  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW and CE HIGH to Write End  
SCE  
AW  
1
2
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
HA  
0
SA  
35  
35  
25  
0
PWE  
BW  
BLE / BHE LOW to Write End  
Data Setup to Write End  
Data Hold from Write End  
SD  
HD  
WE LOW to High-Z  
18  
HZWE  
LZWE  
WE HIGH to Low-Z  
10  
Notes  
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of V (typ)/2, input pulse levels of 0  
CC  
to V (typ), and output loading of the specified I /I as shown in “AC Test Loads and Waveforms” on page 4.  
CC  
OL OH  
15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.  
16. At any temperature and voltage condition, t is less than t , t is less than t , t is less than t , and t is less than t for any device.  
HZCE  
LZCE HZBE  
LZBE HZOE  
LZOE  
HZWE  
LZWE  
17. t  
, t  
, t  
, and t  
transitions are measured when the outputs enter a high impedance state.  
HZOE HZCE HZBE  
HZWE  
18. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE or BLE or both = V , and CE = V . All signals must be ACTIVE to initiate a  
1
IL  
IL  
2
IH  
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.  
Document #: 38-05446 Rev. *E  
Page 5 of 14  
         
CY62167EV30 MoBL®  
Switching Waveforms  
Figure 5 shows address transition controlled read cycle waveforms.  
Figure 5. Read Cycle No. 1  
t
RC  
ADDRESS  
DATA OUT  
t
AA  
t
OHA  
PREVIOUS DATA VALID  
DATA VALID  
Figure 6 shows OE controlled read cycle waveforms.  
Figure 6. Read Cycle No. 2  
ADDRESS  
tRC  
CE1  
CE2  
tPD  
t
HZCE  
tACE  
BHE/BLE  
OE  
tDBE  
tHZBE  
tLZBE  
tHZOE  
tDOE  
tLZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
VCC  
SUPPLY  
CURRENT  
DATA VALID  
tLZCE  
ICC  
ISB  
tPU  
50%  
50%  
Notes  
19. The device is continuously selected. OE, CE = V , BHE, BLE or both = V , and CE = V .  
IH  
1
IL  
IL  
2
20. WE is HIGH for read cycle.  
21. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.  
1
2
Document #: 38-05446 Rev. *E  
Page 6 of 14  
         
CY62167EV30 MoBL®  
Switching Waveforms (continued)  
Figure 7 shows WE controlled write cycle waveforms.  
Figure 7. Write Cycle No. 1  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tAW  
tHA  
tSA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tHD  
tSD  
DATA I/O  
VALID DATA  
tHZOE  
Notes  
22. Data IO is high impedance if OE = V  
.
IH  
23. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.  
1
2
IH  
24. During this period the I/Os are in output state. Do not apply input signals.  
Document #: 38-05446 Rev. *E  
Page 7 of 14  
       
CY62167EV30 MoBL®  
Switching Waveforms (continued)  
Figure 8 shows CE or CE controlled write cycle waveforms.  
1
2
Figure 8. Write Cycle No. 2  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tSA  
tAW  
tHA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tHD  
tSD  
DATA I/O  
VALID DATA  
tHZOE  
Figure 9 shows WE controlled, OE LOW write cycle waveforms.  
Figure 9. Write Cycle No. 3  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tBW  
BHE/BLE  
tAW  
tHA  
tSA  
tPWE  
WE  
tSD  
tHD  
DATA I/O  
VALID DATA  
tLZWE  
t
HZWE  
Document #: 38-05446 Rev. *E  
Page 8 of 14  
   
CY62167EV30 MoBL®  
Switching Waveforms (continued)  
Figure 10 shows BHE/BLE controlled, OE LOW write cycle waveforms.  
Figure 10. Write Cycle No. 4  
tWC  
ADDRESS  
CE1  
CE2  
tSCE  
tAW  
tHA  
tBW  
BHE/BLE  
WE  
tSA  
tPWE  
tSD  
VALID DATA  
tHD  
DATA IO  
Truth Table  
CE  
H
X
CE  
X
WE OE BHE BLE  
Inputs/Outputs  
Mode  
Power  
1
2
X
X
X
H
H
X
X
X
L
X
X
H
L
X
X
H
L
High Z  
High Z  
High Z  
Deselect / Power Down  
Deselect / Power Down  
Deselect / Power Down  
Read  
Standby (I  
Standby (I  
Standby (I  
)
SB  
L
)
SB  
X
X
)
SB  
L
H
H
Data Out (I/O –I/O  
)
Active (I  
Active (I  
)
CC  
0
15  
L
L
H
L
Data Out (I/O –I/O );  
Read  
)
CC  
0
7
High Z (I/O –I/O  
)
8
15  
L
H
H
L
L
H
High Z (I/O –I/O );  
Read  
Active (I  
)
CC  
0
7
Data Out (I/O –I/O  
)
8
15  
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z  
High Z  
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active (I  
Active (I  
Active (I  
Active (I  
Active (I  
)
CC  
)
CC  
)
CC  
L
Data In (I/O –I/O  
)
)
CC  
0
15  
L
H
Data In (I/O –I/O );  
High Z (I/O –I/O  
Write  
)
CC  
0
7
)
8
15  
L
H
L
X
L
H
High Z (I/O –I/O );  
Write  
Active (I  
)
CC  
0
7
Data In (I/O –I/O  
)
8
15  
Document #: 38-05446 Rev. *E  
Page 9 of 14  
   
CY62167EV30 MoBL®  
Ordering Information  
Speed  
Package  
Diagram  
Operating  
Range  
Package Type  
(ns)  
Ordering Code  
CY62167EV30LL-45BAXI  
CY62167EV30LL-45BVI  
CY62167EV30LL-45BVXI  
CY62167EV30LL-45ZXI  
CY62167EV30LL-45ZXA  
45  
001-13297 48-ball VFBGA (6 x 7 x 1 mm) (Pb-free)  
51-85150 48-ball VFBGA (6 x 8 x 1 mm)  
51-85150 48-ball VFBGA (6 x 8 x 1 mm) (Pb-free)  
51-85183 48-pin TSOP I (Pb-free)  
Industrial  
51-85183 48-pin TSOP I (Pb-free)  
Automotive-A  
Shaded areas contain preliminary information. Please contact your local Cypress sales representative for availability of these parts.  
Package Diagrams  
Figure 11. 48-Ball VFBGA (6 x 7 x 1 mm), 001-13297  
NOTES:  
1. ALL DIMENSION ARE IN MM [MAX/MIN]  
2. JEDEC REFERENCE : MO-216  
3. PACKAGE WEIGHT : 0.03g  
001-13297-*A  
Document #: 38-05446 Rev. *E  
Page 10 of 14  
CY62167EV30 MoBL®  
Package Diagrams (continued)  
Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05(48X)  
A1 CORNER  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85150-*D  
Document #: 38-05446 Rev. *E  
Page 11 of 14  
CY62167EV30 MoBL®  
Package Diagrams (continued)  
Figure 13. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183  
DIMENSIONS IN INCHES[MM] MIN.  
JEDEC # MO-142  
MAX.  
0.037[0.95]  
0.041[1.05]  
N
1
0.020[0.50]  
TYP.  
0.472[12.00]  
0.007[0.17]  
0.011[0.27]  
0.002[0.05]  
0.006[0.15]  
0.724 [18.40]  
0.787[20.00]  
0.047[1.20]  
MAX.  
0.004[0.10]  
0.008[0.21]  
0.010[0.25]  
GAUGE PLANE  
0.020[0.50]  
0.028[0.70]  
0°-5°  
51-85183-*A  
Document #: 38-05446 Rev. *E  
Page 12 of 14  
CY62167EV30 MoBL®  
Document History Page  
®
Document Title: CY62167EV30 MoBL 16-Mbit (1M x 16 / 2M x 8) Static RAM  
Document Number: 38-05446  
Orig. of  
Change  
Submission  
Date  
REV.  
ECN NO.  
Description of Change  
**  
202600  
463674  
AJU  
01/23/2004 New Data Sheet  
*A  
NXR  
See ECN  
Converted from Advance Information to Preliminary  
Removed ‘L’ bin and 35 ns speed bin from product offering  
Modified Data sheet to include x8 configurability.  
Changed ball E3 in FBGA pinout from DNU to NC  
Changed the I  
Changed the I  
value from 1.3 μA to 1.5 μA  
value from 40 mA to 25 mA  
SB2(Typ)  
CC(Max)  
Changed Vcc stabilization time in footnote #9 from 100 µs to 200 µs  
Changed the AC Test Load Capacitance value from 50 pF to 30 pF  
Corrected typo in Data Retention Characteristics (tR) from 100 µs to tRC ns  
Changed t  
Changed t  
Changed t  
Changed t  
, t  
, t  
, and t  
from 6 ns to 10 ns  
OHA LZCE LZBE  
LZWE  
from 3 ns to 5 ns.  
LZOE  
, t  
, t  
, and t  
from 15 ns to 18 ns  
HZOE HZCE HZBE  
HZWE  
, t , and t from 40 ns to 35 ns  
SCE AW  
BW  
Changed t from 30 ns to 35 ns  
PE  
Changed t from 20 ns to 25 ns  
SD  
Updated 48 ball FBGA Package Information.  
Updated the Ordering Information table  
*B  
*C  
469169  
NSI  
See ECN  
See ECN  
Minor Change: Moved to external web  
1130323  
VKN  
Converted from preliminary to final  
Changed I max spec from 2.8 mA to 4.0 mA for f=1MHz  
CC  
Changed I typ spec from 22 mA to 25 mA for f=f  
CC  
max  
Changed I max spec from 25 mA to 30 mA for f=f  
CC  
max  
Added V spec for TSOP I package and footnote# 9  
IL  
Added footnote# 10 related to I  
and I  
SB2  
CCDR  
Changed I  
Changed I  
and I  
spec from 8.5 μA to 12 μA  
SB1  
SB2  
spec from 8 μA to 10 μA  
CCDR  
Added footnote# 15 related to AC timing parameters  
*D  
*E  
1323984 VKN/AESA  
See ECN  
Modified I spec for TSOP I package  
CCDR  
Added 48-Ball VFBGA (6 x 7 x 1mm) package  
Added footnote# 1 related to VFBGA (6 x 7 x 1mm) package  
Updated Ordering Information table  
2678799 VKN/PYRS 03/25/2009 Added Automotive-A information  
Document #: 38-05446 Rev. *E  
Page 13 of 14  
CY62167EV30 MoBL®  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used  
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use  
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support  
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-05446 Rev. *E  
Revised March 23, 2009  
Page 14 of 14  
MoBL is aregisteredtrademark andMore Battery Lifeis atrademark of Cypress Semiconductor. All product andcompany names mentioned in this document are the trademarks of their respective holders.  

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