Cypress CY62158E User Manual

CY62158E MoBL®  
8-Mbit (1M x 8) Static RAM  
®
is ideal for providing More Battery Life™ (MoBL ) in portable  
Features  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption. Placing the device into standby mode reduces  
Very high speed: 45 ns  
Wide voltage range: 4.5V – 5.5V  
power consumption significantly when deselected (CE HIGH or  
1
Ultra low active power  
CE LOW).  
2
Typical active current:1.8 mA @ f = 1 MHz  
To write to the device, take Chip Enables (CE LOW and CE  
HIGH) and Write Enable (WE) input LOW. Data on the eight IO  
1
2
Typical active current: 18 mA @ f = f  
max  
pins (IO through IO ) is then written into the location specified  
Ultra low standby power  
Typical standby current: 2 μA  
Maximum standby current: 8 μA  
0
7
on the address pins (A through A ).  
0
19  
To read from the device, take Chip Enables (CE LOW and CE  
1
2
HIGH) and OE LOW while forcing the WE HIGH. Under these  
conditions, the contents of the memory location specified by the  
address pins appear on the IO pins.  
Easy memory expansion with CE , CE and OE features  
1
2
Automatic power down when deselected  
CMOS for optimum speed and power  
Offered in Pb-free 44-Pin TSOP II package  
The eight input and output pins (IO through IO ) are placed in  
0
7
a high impedance state when the device is deselected (CE  
1
HIGH or CE LOW), the outputs are disabled (OE HIGH), or a  
2
write operation is in progress (CE LOW and CE HIGH and WE  
LOW). See the Truth Table on page 8 for a complete description  
of read and write modes.  
1
2
Functional Description  
®
The CY62158E MoBL is a high performance CMOS static RAM  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
organized as 1024K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current. This  
Logic Block Diagram  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
0
DATA IN DRIVERS  
IO  
1
IO  
2
1024K x 8  
ARRAY  
IO  
3
IO  
IO  
IO  
IO  
4
5
6
7
A
A
A
A
9
10  
11  
12  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Cypress Semiconductor Corporation  
Document #: 38-05684 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 16, 2008  
CY62158E MoBL®  
DC Input Voltage  
.....................–0.5V to V  
+ 0.5V  
Maximum Ratings  
CC(max)  
Output Current into Outputs (LOW)............................. 20 mA  
Exceeding the maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Static Discharge Voltage............................................>2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature.................................. –65°C to +150°C  
Latch up Current......................................................>200 mA  
Ambient Temperature with  
Power Applied ............................................ –55°C to +125°C  
Operating Range  
Supply Voltage to Ground Potential0.5V to V  
+ 0.5V  
CC(max)  
Ambient  
Device  
Range  
V
CC  
Temperature  
DC Voltage Applied to Outputs  
in High-Z State  
........................–0.5V to V  
+ 0.5V  
CY62158ELL  
Industrial –40°C to +85°C 4.5V – 5.5V  
CC(max)  
Electrical Characteristics  
Over the Operating Range  
-45  
[2]  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
Min  
Typ  
Max  
Unit  
V
V
I
I
= –1 mA  
= 2.1 mA  
2.4  
OH  
OL  
IH  
OH  
V
V
V
I
0.4  
V
OL  
V
V
= 4.5V to 5.5V  
= 4.5V to 5.5V  
2.2  
–0.5  
–1  
V
+ 0.5V  
V
CC  
CC  
CC  
0.8  
+1  
+1  
25  
3
V
IIL  
Input Leakage Current  
Output Leakage Current  
GND < V < V  
CC  
μA  
μA  
mA  
mA  
IX  
I
I
I
GND < V < V , Output Disabled  
–1  
OZ  
O
CC  
V
Operating Supply  
f = f  
= 1/t  
V
= V  
CCmax  
= 0 mA  
18  
CC  
CC  
MAX  
RC  
CC  
Current  
I
OUT  
f = 1 MHz  
1.8  
CMOS levels  
I
Automatic CE Power down CE > V 0.2V, CE < 0.2V  
2
8
μA  
SB1  
1
CC  
2
Current — CMOS Inputs  
V
> V – 0.2V, V < 0.2V)  
IN CC IN  
f = f  
(Address and Data Only),  
MAX  
f = 0 (OE, and WE), V = V  
CC  
CCmax  
I
Automatic CE Power-down CE > V – 0.2V or CE < 0.2V,  
2
8
μA  
SB2  
1
CC  
2
Current — CMOS Inputs  
V
> V – 0.2V or V < 0.2V,  
IN CC IN  
f = 0, V = V  
CC  
CCmax  
Capacitance  
Tested initially and after any design or process changes that may affect these parameters.  
Parameter Description Test Conditions  
Input Capacitance T = 25°C, f = 1 MHz,  
Output Capacitance  
Max  
10  
Unit  
pF  
C
IN  
A
V
= V  
CC(typ)  
CC  
C
10  
pF  
OUT  
Thermal Resistance  
Tested initially and after any design or process changes that may affect these parameters.  
Parameter  
Description  
Test Conditions  
TSOP II  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 × 4.5 inch,  
two-layer printed circuit board  
75.13  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
8.95  
°C/W  
JC  
Notes  
3. V (min) = –2.0V for pulse durations less than 20 ns.  
IL  
4.  
V
(max) = V + 0.75V for pulse durations less than 20 ns.  
IH CC  
5. Full Device AC operation assumes a 100 μs ramp time from 0 to V (min) and 200 μs wait time after V stabilization.  
CC  
CC  
6. Only chip enables (CE and CE ), must be tied to CMOS levels to meet the I / I spec. Other inputs can be left floating.  
1
2
SB2 CCDR  
Document #: 38-05684 Rev. *D  
Page 3 of 10  
       
CY62158E MoBL®  
Figure 2. AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
V
CC  
3V  
90%  
10%  
OUTPUT  
90%  
10%  
GND  
R2  
100 pF  
Fall Time = 1 V/ns  
Rise Time = 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to: THÉVENIN EQUIVALENT  
R
TH  
OUTPUT  
V
Parameters  
5.0V  
Unit  
R1  
R2  
R
1838  
994  
Ω
Ω
Ω
V
645  
TH  
V
1.75  
TH  
Data Retention Characteristics  
Over the Operating Range  
[2]  
Parameter  
Description  
Conditions  
Min  
Typ  
Max  
Unit  
V
V
V
for Data Retention  
2
DR  
CC  
I
Data Retention Current  
V
= V  
DR  
8
μA  
CCDR  
CC  
CE > V 0.2V, CE < 0.2V,  
1
CC  
2
V
> V 0.2V or V < 0.2V  
CC IN  
IN  
[7]  
t
t
Chip Deselect to Data  
Retention Time  
0
ns  
ns  
CDR  
R
Operation Recovery Time  
t
RC  
Figure 3. Data Retention Waveform  
DATA RETENTION MODE  
V
(min)  
> 2.0 V  
V
t
(min)  
V
CC  
V
CC  
DR  
CC  
t
CDR  
R
CE  
or  
1
CE  
2
Notes  
7. Tested initially and after any design or process changes that may affect these parameters.  
8. Full device operation requires linear V ramp from V to V (min) > 100 μs or stable at V (min) > 100 μs.  
CC  
DR  
CC  
CC  
Document #: 38-05684 Rev. *D  
Page 4 of 10  
     
CY62158E MoBL®  
Switching Characteristics  
Over the Operating Range  
45 ns  
Unit  
Parameter  
Description  
Min  
45  
Max  
Read Cycle  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
45  
AA  
Data Hold from Address Change  
10  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
CE LOW and CE HIGH to Data Valid  
45  
22  
1
2
OE LOW to Data Valid  
OE LOW to Low Z  
5
10  
0
OE HIGH to High Z  
CE LOW and CE HIGH to Low Z  
18  
18  
45  
1
2
CE HIGH or CE LOW to High Z  
1
2
CE LOW and CE HIGH to Power Up  
1
2
CE HIGH or CE LOW to Power Down  
PD  
1
2
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
CE LOW and CE HIGH to Write End  
45  
35  
35  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
SCE  
AW  
1
2
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
HA  
0
SA  
35  
25  
0
PWE  
SD  
Data Setup to Write End  
Data Hold from Write End  
HD  
WE LOW to High Z  
18  
HZWE  
LZWE  
WE HIGH to Low Z  
10  
Notes  
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of V  
/2, input pulse  
CC(typ)  
levels of 0 to V  
, and output loading of the specified I /I as shown in “AC Test Loads and Waveforms” on page 4.  
CC(typ)  
OL OH  
10. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
LZWE  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
11. t  
, t  
, and t  
transitions are measured when the outputs enter a high impedance state.  
HZOE HZCE  
HZWE  
12. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these signals  
1
IL  
2
IH  
can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.  
Document #: 38-05684 Rev. *D  
Page 5 of 10  
       
CY62158E MoBL®  
Switching Waveforms  
Figure 4 shows address transition controlled read cycle waveforms.  
Figure 4. Read Cycle No. 1  
t
RC  
ADDRESS  
DATA OUT  
t
AA  
t
OHA  
PREVIOUS DATA VALID  
DATA VALID  
Figure 5 shows OE controlled read cycle waveforms.  
Figure 5. Read Cycle No. 2  
ADDRESS  
t
RC  
CE  
1
CE  
2
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
VCC  
DATA VALID  
t
LZCE  
t
PD  
ICC  
t
PU  
50%  
SUPPLY  
50%  
ISB  
CURRENT  
Notes  
13. Device is continuously selected. OE, CE = V , CE = V .  
IH  
1
IL  
2
14. WE is HIGH for read cycle.  
15. Address valid before or similar to CE transition LOW and CE transition HIGH.  
1
2
Document #: 38-05684 Rev. *D  
Page 6 of 10  
         
CY62158E MoBL®  
Switching Waveforms (continued)  
Figure 6 shows WE controlled write cycle waveforms.  
Figure 6. Write Cycle No. 1  
t
WC  
ADDRESS  
t
SCE  
CE  
1
CE  
2
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
VALID DATA  
DATA IO  
t
HZOE  
Figure 7 shows CE or CE controlled write cycle waveforms.  
1
2
Figure 7. Write Cycle No. 2  
t
WC  
ADDRESS  
t
SCE  
CE  
1
t
SA  
CE  
2
t
t
HA  
AW  
t
PWE  
WE  
OE  
t
t
HD  
SD  
DATA IO  
VALID DATA  
Notes  
16. Data IO is high impedance if OE = V  
.
IH  
17. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.  
1
2
18. During this period, the IOs are in output state. Do not apply input signals.  
Document #: 38-05684 Rev. *D  
Page 7 of 10  
         
CY62158E MoBL®  
Switching Waveforms (continued)  
Figure 8 shows WE controlled, OE LOW write cycle waveforms.  
Figure 8. Write Cycle No. 3  
t
WC  
ADDRESS  
t
SCE  
CE  
1
CE  
2
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IO  
VALID DATA  
t
t
LZWE  
HZWE  
Truth Table  
CE  
CE  
WE  
OE  
Inputs/Outputs  
High Z  
Mode  
Power  
1
2
H
X
L
L
L
X
L
X
X
H
H
L
X
X
L
Deselect/Power Down  
Deselect/Power Down  
Read  
Standby (I  
Standby (I  
)
)
SB  
High Z  
SB  
H
H
H
Data Out  
High Z  
Active (I  
Active (I  
Active (I  
)
)
)
CC  
CC  
CC  
H
X
Output Disabled  
Write  
Data in  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Package Type  
Ordering Code  
45  
CY62158ELL-45ZSXI  
51-85087 44-Pin TSOP II (Pb-free)  
Industrial  
Document #: 38-05684 Rev. *D  
Page 8 of 10  
   
CY62158E MoBL®  
Package Diagrams  
Figure 9. 44-Pin TSOP II, 51-85087  
51-85087-*A  
Document #: 38-05684 Rev. *D  
Page 9 of 10  
CY62158E MoBL®  
Document History Page  
®
Document Title: CY62158E MoBL 8-Mbit (1M x 8) Static RAM  
Document Number: 38-05684  
Orig. of  
Change  
REV.  
ECN NO. Issue Date  
Description of Change  
**  
270350  
291271  
See ECN  
See ECN  
PCI  
New Data Sheet  
*A  
SYT  
Converted from Advance Information to Preliminary  
Changed input pulse level from V to 3V in the AC Test Loads and Waveforms  
CC  
Modified footnote #9 to include timing reference level of 1.5V and input pulse  
level of 3V  
*B  
1462592  
See ECN VKN/AESA Converted from preliminary to final  
Removed 35 ns speed bin  
Removed “L” parts  
Removed 48-Ball VFBGA package  
Changed I  
Changed I  
Changed I  
Changed I  
Changed I  
Changed I  
Changed t  
Changed t  
Changed t  
Changed t  
spec from 2.3 mA to 3 mA at f=1 MHz  
CC(max)  
spec from 16 mA to 18 mA at f=f  
CC(typ)  
MAX  
spec from 28 mA to 25 mA at f=f  
CC(max)  
SB1(typ)  
SB1(max)  
CCDR(max)  
MAX  
and I  
and I  
spec from 0.9 μA to 2 μA  
SB2(max)  
SB2(typ)  
spec from 4.5 μA to 8 μA  
spec from 4.5 μA to 8 μA  
spec from 3 ns to 5 ns  
spec from 6 ns to 10 ns  
spec from 22 ns to 18 ns  
spec from 30 ns to 35 ns  
LZOE  
LZCE  
HZCE  
PWE  
Changed t spec from 22 ns to 25 ns  
SD  
Changed t  
spec from 6 ns to 10 ns  
LZWE  
Added footnote# 6 related to I  
and I  
SB2  
CCDR  
Updated Ordering information table  
See ECN VKN/PYRS Corrected typo in the Ordering Information table  
See ECN PYRS Corrected ECN number  
*C  
*D  
2428708  
2516494  
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-05684 Rev. *D  
Revised June 16, 2008  
Page 10 of 10  
All products and company names mentioned in this document may be the trademarks of their respective holders.  

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