Cypress CY14B104L User Manual

CY14B104L, CY14B104N  
4 Mbit (512K x 8/256K x 16) nvSRAM  
Features  
Functional Description  
20 ns, 25 ns, and 45 ns Access Times  
The Cypress CY14B104L/CY14B104N is a fast static RAM, with  
a nonvolatile element in each memory cell. The memory is  
Internally organized as 512K x 8 (CY14B104L) or 256K x 16  
(CY14B104N)  
organized as 512K bytes of 8 bits each or 256K words of 16 bits  
each. The embedded nonvolatile elements incorporate  
QuantumTrap technology, producing the world’s most reliable  
nonvolatile memory. The SRAM provides infinite read and write  
cycles, while independent nonvolatile data resides in the highly  
reliable QuantumTrap cell. Data transfers from the SRAM to the  
nonvolatile elements (the STORE operation) takes place  
automatically at power down. On power up, data is restored to  
the SRAM (the RECALL operation) from the nonvolatile memory.  
Both the STORE and RECALL operations are also available  
under software control.  
Hands off Automatic STORE on power down with only a small  
Capacitor  
®
STORE to QuantumTrap nonvolatile elements initiated by  
®
software, device pin, or AutoStore on power down  
RECALL to SRAM initiated by software or power up  
Infinite Read, Write, and Recall Cycles  
200,000 STORE cycles to QuantumTrap  
20 year data retention  
Single 3V +20% to –10% operation  
Commercial and Industrial Temperatures  
48-ball FBGA and 44/54-pin TSOP II packages  
Pb-free and RoHS compliance  
Logic Block Diagram[1, 2, 3]  
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Notes  
1. Address A - A for x8 configuration and Address A - A for x16 configuration.  
0
18  
0
17  
2. Data DQ - DQ for x8 configuration and Data DQ - DQ for x16 configuration.  
0
7
0
15  
3. BHE and BLE are applicable for x16 configuration only.  
Cypress Semiconductor Corporation  
Document #: 001-07102 Rev. *L  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 19, 2008  
     
CY14B104L, CY14B104N  
Pinouts (continued)  
Figure 3. Pin Diagram - 54 Pin TSOP II (x16)  
NC  
54  
53  
52  
51  
50  
49  
HSB  
NC  
1
2
3
[4]  
NC  
A
0
A
17  
A
1
A
16  
4
5
6
A
2
A
15  
A
3
OE  
48  
47  
46  
45  
A
4
BHE  
BLE  
DQ  
7
8
9
10  
11  
12  
13  
14  
CE  
DQ  
DQ  
0
1
15  
DQ  
DQ  
DQ  
V
14  
13  
12  
54 - TSOP II  
(x16)  
DQ  
DQ  
44  
43  
42  
41  
40  
39  
2
3
V
CC  
SS  
Top View  
(not to scale)  
V
SS  
V
CC  
DQ  
DQ  
4
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
11  
DQ  
DQ  
DQ  
DQ  
5
10  
38  
37  
36  
35  
DQ  
DQ  
6
9
8
7
WE  
A
5
V
CAP  
A
14  
34  
33  
32  
31  
30  
29  
28  
A
6
A
13  
A
A
7
A
8
12  
A
11  
A
A
9
10  
NC  
NC  
NC  
NC  
NC  
NC  
25  
26  
27  
Pin Definitions  
Pin Name  
IO Type  
Description  
A – A  
Input  
Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration.  
0
18  
17  
A – A  
Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.  
0
DQ – DQ  
Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on  
0
7
operation.  
DQ – DQ  
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on  
0
15  
operation.  
WE  
Input  
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the specific  
address location.  
Input  
Input  
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.  
CE  
OE  
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read  
cycles. IO pins are tri-stated on deasserting OE HIGH.  
Input  
Input  
Byte High Enable, Active LOW. Controls DQ - DQ .  
BHE  
BLE  
15  
8
Byte Low Enable, Active LOW. Controls DQ - DQ .  
7
0
V
Ground  
Ground for the Device. Must be connected to the ground of the system.  
SS  
V
Power Supply Power Supply Inputs to the Device.  
CC  
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.  
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull  
up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB  
will be driven HIGH for short time with standard output high current.  
HSB  
V
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to  
CAP  
nonvolatile elements.  
NC  
No Connect No Connect. This pin is not connected to the die.  
Document #: 001-07102 Rev. *L  
Page 3 of 25  
CY14B104L, CY14B104N  
Figure 4 shows the proper connection of the storage capacitor  
Device Operation  
(V  
) for automatic store operation. Refer to DC Electrical  
CAP  
The CY14B104L/CY14B104N nvSRAM is made up of two  
functional components paired in the same physical cell. They are  
an SRAM memory cell and a nonvolatile QuantumTrap cell. The  
SRAM memory cell operates as a standard fast static RAM. Data  
in the SRAM is transferred to the nonvolatile cell (the STORE  
operation), or from the nonvolatile cell to the SRAM (the RECALL  
operation). Using this unique architecture, all cells are stored and  
recalled in parallel. During the STORE and RECALL operations,  
SRAM read and write operations are inhibited. The  
CY14B104L/CY14B104N supports infinite reads and writes  
similar to a typical SRAM. In addition, it provides infinite RECALL  
operations from the nonvolatile cells and up to 200K STORE  
page 15 for a complete description of read and write modes.  
. The voltage on  
CAP  
the V  
pin is driven to V by a regulator on the chip. A pull  
CAP  
CC  
up should be placed on WE to hold it inactive during power up.  
This pull up is only effective if the WE signal is tri-state during  
power up. Many MPU’s will tri-state their controls on power up.  
This should be verified when using the pull up. When the  
nvSRAM comes out of power-on-recall, the MPU must be active  
or the WE held inactive until the MPU comes out of reset.  
To reduce unnecessary nonvolatile stores, AutoStore and  
hardware store operations are ignored unless at least one write  
operation has taken place since the most recent STORE or  
RECALL cycle. Software initiated STORE cycles are performed  
regardless of whether a write operation has taken place. The  
HSB signal is monitored by the system to detect if an AutoStore  
cycle is in progress.  
SRAM Read  
Figure 4. AutoStore Mode  
The CY14B104L/CY14B104N performs a read cycle when CE  
and OE are LOW and WE and HSB are HIGH. The address  
Vcc  
specified on pins A  
or A  
determines which of the 524,288  
0-18  
0-17  
data bytes or 262,144 words of 16 bits each are accessed. Byte  
enables (BHE, BLE) determine which bytes are enabled to the  
output, in the case of 16-bit words. When the read is initiated by  
0.1uF  
an address transition, the outputs are valid after a delay of t  
Vcc  
AA  
(read cycle 1). If the read is initiated by CE or OE, the outputs  
are valid at t or at t , whichever is later (read cycle 2). The  
ACE  
DOE  
data output repeatedly responds to address changes within the  
access time without the need for transitions on any control  
WE  
VCAP  
t
AA  
input pins. This remains valid until another address change or  
until CE or OE is brought HIGH, or WE or HSB is brought LOW.  
VCAP  
VSS  
SRAM Write  
A write cycle is performed when CE and WE are LOW and HSB  
is HIGH. The address inputs must be stable before entering the  
write cycle and must remain stable until CE or WE goes HIGH at  
Hardware STORE Operation  
the end of the cycle. The data on the common IO pins DQ  
0–15  
are written into the memory if the data is valid t before the end  
[6]  
SD  
The CY14B104L/CY14B104N provides the HSB pin to control  
and acknowledge the STORE operations. Use the HSB pin to  
request a hardware STORE cycle. When the HSB pin is driven  
LOW, the CY14B104L/CY14B104N conditionally initiates a  
of a WE controlled write or before the end of an CE controlled  
write. The Byte Enable inputs (BHE, BLE) determine which bytes  
are written, in the case of 16bit words. It is recommended that  
OE be kept HIGH during the entire write cycle to avoid data bus  
contention on common IO lines. If OE is left LOW, internal  
STORE operation after t  
. An actual STORE cycle only  
DELAY  
begins if a write to the SRAM has taken place since the last  
STORE or RECALL cycle. The HSB pin also acts as an open  
drain driver that is internally driven LOW to indicate a busy  
condition when the STORE (initiated by any means) is in  
progress.  
circuitry turns off the output buffers t  
after WE goes LOW.  
HZWE  
AutoStore Operation  
When HSB is driven LOW by any means, SRAM read and write  
operations that are in progress are given time to complete before  
the STORE operation is initiated. After HSB goes LOW, the  
CY14B104L/CY14B104N continues SRAM operations for  
The CY14B104L/CY14B104N stores data to the nvSRAM using  
one of the following three storage operations: Hardware Store  
activated by HSB; Software Store activated by an address  
sequence; AutoStore on device power down. The AutoStore  
operation is a unique feature of QuantumTrap technology and is  
enabled by default on the CY14B104L/CY14B104N.  
t
.
DELAY  
During any STORE operation, regardless of how it is initiated,  
the CY14B104L/CY14B104N continues to drive the HSB pin  
LOW, releasing it only when the STORE is complete. Upon  
During a normal operation, the device draws current from V to  
CC  
charge a capacitor connected to the V  
pin. This stored  
CAP  
completion  
of  
the  
STORE  
operation,  
the  
charge is used by the chip to perform a single STORE operation.  
CY14B104L/CY14B104N remains disabled until the HSB pin  
returns HIGH. Leave the HSB unconnected if it is not used.  
If the voltage on the V pin drops below V , the part  
CC  
SWITCH  
automatically disconnects the V  
pin from V . A STORE  
CAP  
CC  
operation is initiated with power provided by the V  
capacitor.  
CAP  
Document #: 001-07102 Rev. *L  
Page 4 of 25  
 
CY14B104L, CY14B104N  
The software sequence may be clocked with CE controlled reads  
or OE controlled reads. After the sixth address in the sequence  
is entered, the STORE cycle commences and the chip is  
disabled. HSB will be driven LOW. It is important to use read  
cycles and not write cycles in the sequence, although it is not  
necessary that OE be LOW for a valid sequence. After the  
Hardware RECALL (Power Up)  
During power up or after any low power condition  
(V < V  
), an internal RECALL request is latched. When  
CC  
SWITCH  
V
again exceeds the sense voltage of V  
, a RECALL  
to complete.  
CC  
SWITCH  
cycle is automatically initiated and takes t  
HRECALL  
During this time, HSB is driven LOW by the HSB driver.  
t
cycle time is fulfilled, the SRAM is activated again for the  
STORE  
read and write operation.  
Software STORE  
Software RECALL  
Transfer data from the SRAM to the nonvolatile memory with a  
software address sequence. The CY14B104L/CY14B104N  
software STORE cycle is initiated by executing sequential CE  
controlled read cycles from six specific address locations in  
exact order. During the STORE cycle an erase of the previous  
nonvolatile data is performed, followed by a program of the  
nonvolatile elements. After a STORE cycle is initiated, further  
input and output are disabled until the cycle is completed.  
Transfer the data from the nonvolatile memory to the SRAM with  
a software address sequence. A software RECALL cycle is  
initiated with a sequence of read operations in a manner similar  
to the software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE controlled read operations must be  
performed.  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x4C63 Initiate RECALL Cycle  
Because a sequence of READs from specific addresses is used  
for STORE initiation, it is important that no other read or write  
accesses intervene in the sequence. Further, no read or write  
operations must be done after the sixth address read for a  
duration of soft-sequence processing time (t ). If these condi-  
SS  
tions are not met, the sequence is aborted and no STORE or  
RECALL takes place.  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared; then, the nonvolatile information is transferred into the  
To initiate the software STORE cycle, the following addresses  
and read sequence must be performed.  
SRAM cells. After the t  
cycle time, the SRAM is again  
RECALL  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x8FC0 Initiate STORE Cycle  
ready for read and write operations. The RECALL operation  
does not alter the data in the nonvolatile elements.  
Table 1. Mode Selection  
A
- A  
X
Mode  
IO  
Power  
Standby  
Active  
CE  
H
L
WE  
X
OE, BHE, BLE  
15  
0
X
L
X
L
Not Selected  
Read SRAM  
Write SRAM  
Output High Z  
Output Data  
Input Data  
H
X
L
L
X
Active  
L
H
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8B45  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
Disable  
Notes  
7. While there are 19 address lines on the CY14B104L (18 address lines on the CY14B104N), only the 13 address lines (A - A ) are used to control software modes.  
14  
2
The rest of the address lines are don’t care.  
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.  
9. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.  
Document #: 001-07102 Rev. *L  
Page 5 of 25  
       
CY14B104L, CY14B104N  
Table 1. Mode Selection (continued)  
[7]  
[3]  
A
- A  
Mode  
IO  
Power  
CE  
WE  
OE, BHE, BLE  
15  
0
L
H
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x4B46  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore Enable  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
Active I  
CC2  
L
L
H
H
L
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Nonvolatile Store Output High Z  
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x4C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile  
Recall  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Active  
If the AutoStore function is disabled or re-enabled, a manual  
STORE operation (hardware or software) must be issued to save  
the AutoStore state through subsequent power down cycles. The  
part comes from the factory with AutoStore enabled.  
Preventing AutoStore  
The AutoStore function is disabled by initiating an AutoStore  
disable sequence. A sequence of read operations is performed  
in a manner similar to the software STORE initiation. To initiate  
the AutoStore disable sequence, the following sequence of CE  
controlled read operations must be performed:  
Data Protection  
The CY14B104L/CY14B104N protects data from corruption  
during low voltage conditions by inhibiting all externally initiated  
STORE and write operations. The low voltage condition is  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x8B45 AutoStore Disable  
detected when V < V  
. If the CY14B104L/CY14B104N  
CC  
SWITCH  
is in a write mode (both CE and WE are LOW) at power up, after  
a RECALL or STORE, the write is inhibited until the SRAM is  
enabled after t  
(HSB to output active). This protects against  
LZHSB  
inadvertent writes during power up or brown out conditions.  
The AutoStore is re-enabled by initiating an AutoStore enable  
sequence. A sequence of read operations is performed in a  
manner similar to the software RECALL initiation. To initiate the  
AutoStore enable sequence, the following sequence of CE  
controlled read operations must be performed:  
Noise Considerations  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x4B46 AutoStore Enable  
Document #: 001-07102 Rev. *L  
Page 6 of 25  
CY14B104L, CY14B104N  
Transient Voltage (<20 ns) on  
Any Pin to Ground Potential .................. –2.0V to V + 2.0V  
Maximum Ratings  
CC  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Package Power Dissipation  
Capability (T = 25°C) ................................................... 1.0W  
A
Storage Temperature ................................. –65°C to +150°C  
Maximum Accumulated Storage Time  
Surface Mount Pb Soldering  
Temperature (3 Seconds).......................................... +260°C  
DC Output Current (1 output at a time, 1s duration).... 15 mA  
At 150°C Ambient Temperature ........................ 1000h  
At 85°C Ambient Temperature ...................... 20 Years  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Ambient Temperature with  
Power Applied ............................................ –55°C to +150°C  
Latch Up Current ................................................... > 200 mA  
Supply Voltage on V Relative to GND ..........–0.5V to 4.1V  
Operating Range  
CC  
Voltage Applied to Outputs  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
V
CC  
in High-Z State.......................................0.5V to V + 0.5V  
CC  
2.7V to 3.6V  
2.7V to 3.6V  
Input Voltage..........................................0.5V to V + 0.5V  
CC  
–40°C to +85°C  
DC Electrical Characteristics  
Over the Operating Range (V = 2.7V to 3.6V)  
CC  
Parameter  
Description  
Average V Current  
Test Conditions  
Min  
Max  
Unit  
I
t
t
t
= 20 ns  
= 25 ns  
= 45 ns  
Commercial  
Industrial  
65  
65  
50  
mA  
mA  
mA  
CC1  
CC  
RC  
RC  
RC  
Values obtained without output loads (I  
= 0 mA)  
= 0 mA).  
OUT  
70  
70  
52  
mA  
mA  
mA  
I
I
Average V Current All Inputs Don’t Care, V = Max  
10  
mA  
CC2  
CC  
CC  
during STORE  
Average current for duration t  
STORE  
AverageV Currentat All inputs cycling at CMOS levels.  
35  
mA  
CC3  
CC  
t
= 200 ns, 3V, 25°C Values obtained without output loads (I  
RC  
OUT  
typical  
I
I
Average V  
Current All Inputs Don’t Care, V = Max  
5
5
mA  
mA  
CC4  
CAP  
CC  
during AutoStore Cycle Average current for duration t  
STORE  
V
Standby Current CE > (V – 0.2V). All others V < 0.2V or > (V – 0.2V). Standby  
CC IN CC  
SB  
CC  
current level after nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
I
Input Leakage Current V = Max, V < V < V  
(except HSB)  
–1  
–100  
–1  
+1  
+1  
+1  
μA  
μA  
μA  
V
IX  
CC  
SS  
IN  
CC  
Input Leakage Current V = Max, V < V < V  
CC  
SS  
IN  
CC  
(for HSB)  
I
Off-State Output  
Leakage Current  
V
= Max, V < V  
< V , CE or OE > V or BHE/BLE > V  
IH  
OZ  
CC  
SS  
OUT  
CC  
IH  
or WE < V  
IL  
V
Input HIGH Voltage  
2.0  
V
+
IH  
CC  
0.5  
V
V
V
V
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Storage Capacitor  
V
– 0.5  
0.8  
V
V
IL  
SS  
I
I
= –2 mA  
= 4 mA  
2.4  
61  
OH  
OL  
OUT  
OUT  
0.4  
V
Between V  
pin and V , 5V Rated  
180  
μF  
CAP  
CAP  
SS  
Notes  
10. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V = 3V. Not 100% tested.  
CC  
11. The HSB pin has I  
= -2 μA for V of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This  
OUT  
O
H
O
H
O
L
parameter is characterized but not tested.  
12. V (Storage capacitor) nominal value is 68 μF.  
CAP  
Document #: 001-07102 Rev. *L  
Page 7 of 25  
       
CY14B104L, CY14B104N  
Data Retention and Endurance  
Parameter  
Description  
Min  
20  
Unit  
Years  
K
DATA  
Data Retention  
R
NV  
Nonvolatile STORE Operations  
200  
C
Capacitance  
In the following table, the capacitance parameters are listed.  
Parameter Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max  
7
Unit  
C
C
T = 25°C, f = 1 MHz,  
pF  
pF  
IN  
A
V
= 0 to 3.0V  
CC  
7
OUT  
Thermal Resistance  
In the following table, the thermal resistance parameters are listed.  
Parameter  
Description  
Test Conditions  
Test conditions follow standard test methods  
48-FBGA 44-TSOP II 54-TSOP II Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient) and procedures for measuring thermal  
28.82  
31.11  
30.73  
°C/W  
impedance, in accordance with EIA/JESD51.  
ΘJC  
Thermal Resistance  
(Junction to Case)  
7.84  
5.56  
6.08  
°C/W  
Figure 5. AC Test Loads  
577Ω  
R1  
for tri-state specs  
577Ω  
3.0V  
OUTPUT  
3.0V  
OUTPUT  
R1  
R2  
789Ω  
R2  
789Ω  
5 pF  
30 pF  
AC Test Conditions  
Input Pulse Levels.................................................... 0V to 3V  
Input Rise and Fall Times (10% - 90%)........................ <3 ns  
Input and Output Timing Reference Levels.................... 1.5V  
Note  
13. These parameters are guaranteed but not tested.  
Document #: 001-07102 Rev. *L  
Page 8 of 25  
 
CY14B104L, CY14B104N  
AC Switching Characteristics  
Parameters  
20 ns  
25 ns  
45 ns  
Description  
Unit  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
Parameters Parameters  
SRAM Read Cycle  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
Read Cycle Time  
20  
25  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ACE  
RC  
ACS  
RC  
AA  
20  
25  
45  
Address Access Time  
20  
10  
25  
12  
45  
20  
AA  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
Byte Enable to Data Valid  
DOE  
OHA  
OE  
OH  
LZ  
3
3
3
3
3
3
LZCE  
8
8
10  
10  
15  
15  
HZCE  
HZ  
0
0
0
0
0
0
LZOE  
OLZ  
OHZ  
PA  
HZOE  
PU  
PD  
20  
10  
25  
12  
45  
20  
PS  
-
-
-
DBE  
Byte Enable to Output Active  
Byte Disable to Output Inactive  
0
0
0
LZBE  
HZBE  
8
10  
15  
SRAM Write Cycle  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
20  
15  
15  
8
25  
20  
20  
10  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
PWE  
SCE  
SD  
WC  
WP  
CW  
DW  
DH  
Write Pulse Width  
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
Output Active after End of Write  
Byte Enable to End of Write  
0
HD  
15  
0
20  
0
30  
0
AW  
AW  
AS  
SA  
0
0
0
HA  
WR  
WZ  
OW  
[16,17]  
8
10  
15  
HZWE  
3
3
3
LZWE  
BW  
-
15  
20  
30  
Switching Waveforms  
[14, 15, 18]  
Figure 6. SRAM Read Cycle #1: Address Controlled  
W5&  
$GGUHVV  
$GGUHVVꢀ9DOLG  
W$$  
2XWSXWꢀ'DWDꢀ9DOLG  
3UHYLRXVꢀ'DWDꢀ9DOLG  
W2+$  
'DWDꢀ2XWSXW  
Notes  
14. WE must be HIGH during SRAM read cycles.  
15. Device is continuously selected with CE, OE and BHE / BLE LOW.  
16. Measured ±200 mV from steady state output voltage.  
17. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.  
18. HSB must remain HIGH during READ and WRITE cycles.  
Document #: 001-07102 Rev. *L  
Page 9 of 25  
         
CY14B104L, CY14B104N  
Figure 7. SRAM Read Cycle #2: CE and OE Controlled  
$GGUHVV  
&(  
$GGUHVVꢀ9DOLG  
W5&  
W+=&(  
W$&(  
W$$  
W/=&(  
W+=2(  
W'2(  
2(  
W+=%(  
W/=2(  
W'%(  
%+(ꢍꢀ%/(  
W/=%(  
+LJKꢀ,PSHGDQFH  
'DWDꢀ2XWSXW  
2XWSXWꢀ'DWDꢀ9DOLG  
W38  
W3'  
$FWLYH  
,
6WDQGE\  
&&  
Figure 8. SRAM Write Cycle #1: WE Controlled  
W:&  
$GGUHVV  
$GGUHVVꢀ9DOLG  
W6&(  
W+$  
&(  
W%:  
%+(ꢍꢀ%/(  
W$:  
W3:(  
:(  
'DWDꢀ,QSXW  
'DWDꢀ2XWSXW  
W6$  
W+'  
W6'  
,QSXWꢀ'DWDꢀ9DOLG  
W/=:(  
W+=:(  
+LJKꢀ,PSHGDQFH  
3UHYLRXVꢀ'DWD  
Notes  
19. CE or WE must be >V during address transitions.  
IH  
Document #: 001-07102 Rev. *L  
Page 10 of 25  
 
CY14B104L, CY14B104N  
Figure 9. SRAM Write Cycle #2: CE Controlled  
tWC  
Address Valid  
Address  
tSA  
tSCE  
tHA  
CE  
tBW  
BHE, BLE  
tPWE  
WE  
tHD  
tSD  
Input Data Valid  
Data Input  
High Impedance  
Data Output  
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled  
W:&  
$GGUHVV  
&(  
$GGUHVVꢀ9DOLG  
W6&(  
W6$  
W+$  
W%:  
%+(ꢍꢀ%/(  
:(  
W$:  
W3:(  
W6'  
W+'  
'DWDꢀ,QSXW  
,QSXWꢀ'DWDꢀ9DOLG  
+LJKꢀ,PSHGDQFH  
'DWDꢀ2XWSXW  
Document #: 001-07102 Rev. *L  
Page 11 of 25  
CY14B104L, CY14B104N  
AutoStore/Power Up RECALL  
CY14B104L/CY14B104N  
Unit  
Parameters  
Description  
Min  
Max  
20  
t
t
t
Power Up RECALL Duration  
ms  
ms  
μs  
V
HRECALL  
STORE Cycle Duration  
8
STORE  
DELAY  
Time Allowed to Complete SRAM Cycle  
Low Voltage Trigger Level  
1
70  
V
t
2.65  
SWITCH  
VCC Rise Time  
150  
μs  
V
VCCRISE  
V
HSB Output Driver Disable Voltage  
HSB High Active Time  
1.9  
HDIS  
HHHD  
PURHH  
LZHSB  
t
t
t
500  
ns  
μs  
μs  
HSB Hold Time after Power-Up Recall Start  
HSB To Output Active Time  
70  
5
Switching Waveforms  
Figure 11. AutoStore or Power Up RECALL  
9&&  
96:,7&+  
9+',6  
95(6(7  
W9&&5,6(  
W6725(  
W6725(  
1RWHꢁꢇ  
1RWHꢁꢇ  
W+++'  
W+++'  
+6%  
287  
1RWHꢁꢃ  
W'(/$<  
W/=+6%  
W385++ꢀ  
W/=+6%  
$XWR6WRUH  
W'(/$<  
32:(5ꢋ83ꢀ  
5(&$//  
W+5(&$//  
W+5(&$//  
5HDGꢀ ꢀ:ULWHꢀ  
,QKLELWHG  
32:(5ꢀ'2:1ꢀ  
$XWR6WRUH  
32:(5ꢋ83ꢀ  
5(&$//  
32:(5ꢋ83ꢀ  
5(&$//  
%52:1ꢀ287ꢀ  
$XWR6WRUH  
5HDGꢀ ꢀ:ULWH  
5HDGꢀ ꢀ:ULWH  
Notes  
20. t  
starts from the time V rises above V  
SWITCH.  
HRECALL  
CC  
21. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.  
22. On a Hardware STORE, Software STORE/RECALL, AutoStore Enable/Disable and AutoStore initiation, SRAM operation continues to be enabled for time t  
.
DELAY  
23. Read and Write cycles are ignored during STORE, RECALL, and while V is below V  
CC  
SWITCH.  
24. HSB pin is driven HIGH to V only by internal 100 kΩ resistor, HSB driver is disabled.  
CC  
Document #: 001-07102 Rev. *L  
Page 12 of 25  
       
CY14B104L, CY14B104N  
Software Controlled STORE/RECALL Cycle  
In the following table, the software controlled STORE/RECALL cycle parameters are listed.  
20 ns  
Max  
25 ns  
45 ns  
Max  
Parameters  
Description  
Unit  
Min  
20  
0
Min  
25  
0
Max  
Min  
45  
0
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
ns  
ns  
ns  
ns  
μs  
μs  
RC  
SA  
CW  
HA  
Clock Pulse Width  
15  
0
20  
0
30  
0
Address Hold Time  
RECALL Duration  
200  
100  
200  
100  
200  
100  
RECALL  
SS  
Soft Sequence Processing Time  
Switching Waveforms  
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle  
W5&  
W5&  
$GGUHVV  
$GGUHVVꢀꢎꢇ  
$GGUHVVꢀꢎꢊ  
W+$  
W&:  
W6$  
W&:  
&(  
2(  
W+$  
W+$  
W66  
W6$  
W+$  
W+++'  
W'(/$<  
W+=&(  
+6%ꢀꢏ6725(ꢀRQO\ꢐ  
'4ꢀꢏ'$7$ꢐ  
W/=&(  
W/=+6%  
+LJK  
,PSHGDQFH  
W6725( ꢅW5(&$//  
5:,  
Figure 13. Autostore Enable / Disable Cycle  
W5&  
W5&  
$GGUHVV  
$GGUHVVꢀꢎꢇ  
W&:  
$GGUHVVꢀꢎꢊ  
W&:  
W6$  
&(  
W6$  
W+$  
W+$  
W+$  
W+$  
2(  
W66  
W+=&(  
W/=&(  
W'(/$<  
'4ꢀꢏ'$7$ꢐ  
5:,  
Notes  
25. The software sequence is clocked with CE controlled or OE controlled reads.  
26. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles. After the sixth address read  
cycle, no further read or write operation must be performed for t duration. If these conditions are not met, the software sequence is aborted.  
SS  
Document #: 001-07102 Rev. *L  
Page 13 of 25  
   
CY14B104L, CY14B104N  
Hardware STORE Cycle  
CY14B104L/CY14B104N  
Unit  
Parameters  
Description  
Min  
Max  
t
t
Hardware STORE Pulse Width  
Hardware STORE LOW to STORE Busy  
15  
ns  
ns  
PHSB  
500  
HLBL  
Switching Waveforms  
Figure 14. Hardware STORE Cycle  
:ULWHꢀODWFKꢀVHW  
W3+6%  
+6%ꢀꢀꢏ,1ꢐ  
W6725(  
W+++'  
W+/%/  
+6%ꢀꢀꢏ287ꢐ  
W'(/$<  
W/=+6%  
'4ꢀꢏ'DWDꢀ2XWꢐ  
:ULWHꢀODWFKꢀQRWꢀVHW  
W3+6%  
+6%ꢀꢀꢏ,1ꢐ  
W+/%/  
W+++'  
+6%ꢀꢀꢏ287ꢐ  
W'(/$<  
W/=+6%  
'4ꢀꢏ'DWDꢀ2XWꢐ  
Figure 15. Soft Sequence Processing  
W66  
W66  
6RIWꢀ6HTXHQFH  
&RPPDQG  
6RIWꢀ6HTXHQFH  
&RPPDQG  
$GGUHVV  
$GGUHVVꢀꢎꢇ  
W6$  
$GGUHVVꢀꢎꢊ  
W&:  
$GGUHVVꢀꢎꢇ  
$GGUHVVꢀꢎꢊ  
W&:  
&(  
9&&  
Notes  
27. This is the amount of time it takes to take action on a soft sequence command. V power must remain HIGH to effectively register command.  
CC  
28. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.  
Document #: 001-07102 Rev. *L  
Page 14 of 25  
   
CY14B104L, CY14B104N  
Truth Table For SRAM Operations  
HSB should remain HIGH for SRAM Operations.  
For x8 Configuration  
[2]  
CE  
H
L
WE  
X
OE  
X
Inputs/Outputs  
Mode  
Deselect/Power down  
Read  
Power  
Standby  
Active  
High Z  
Data Out (DQ –DQ );  
H
L
0
7
L
H
H
High Z  
Data in (DQ –DQ );  
Output Disabled  
Write  
Active  
L
L
X
Active  
0
7
For x16 Configuration  
[2]  
CE  
H
L
WE  
X
OE  
X
BHE  
X
BLE  
X
Inputs/Outputs  
Mode  
Deselect/Power down  
Output Disabled  
Read  
Power  
Standby  
High-Z  
High-Z  
X
X
H
H
Active  
Active  
Active  
L
H
L
L
L
Data Out (DQ –DQ  
)
0
15  
L
H
L
H
L
Data Out (DQ –DQ );  
Read  
0
7
DQ –DQ in High-Z  
8
15  
L
H
L
L
H
Data Out (DQ –DQ );  
Read  
Active  
8
15  
DQ –DQ in High-Z  
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active  
Active  
Active  
Active  
Active  
High-Z  
High-Z  
L
Data In (DQ –DQ  
)
15  
0
L
H
Data In (DQ –DQ );  
Write  
0
7
DQ –DQ in High-Z  
8
15  
L
L
X
L
H
Data In (DQ –DQ );  
Write  
Active  
8
15  
DQ –DQ in High-Z  
0
7
Document #: 001-07102 Rev. *L  
Page 15 of 25  
 
CY14B104L, CY14B104N  
Ordering Information  
Speed  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
44-pin TSOP II  
(ns)  
20  
CY14B104L-ZS20XCT  
CY14B104L-ZS20XIT  
CY14B104L-ZS20XI  
CY14B104L-BA20XCT  
CY14B104L-BA20XIT  
CY14B104L-BA20XI  
CY14B104L-ZSP20XCT  
CY14B104L-ZSP20XIT  
CY14B104L-ZSP20XI  
CY14B104N-ZS20XCT  
CY14B104N-ZS20XIT  
CY14B104N-ZS20XI  
CY14B104N-BA20XCT  
CY14B104N-BA20XIT  
CY14B104N-BA20XI  
CY14B104N-ZSP20XCT  
CY14B104N-ZSP20XIT  
CY14B104N-ZSP20XI  
CY14B104L-ZS25XCT  
CY14B104L-ZS25XIT  
CY14B104L-ZS25XI  
CY14B104L-BA25XIT  
CY14B104L-BA25XI  
CY14B104N-BA25XCT  
CY14B104L-ZSP25XCT  
CY14B104L-ZSP25XIT  
CY14B104L-ZSP25XI  
CY14B104N-ZS25XCT  
CY14B104N-ZS25XIT  
CY14B104N-ZS25XI  
CY14B104N-BA25XCT  
CY14B104N-BA25XIT  
CY14B104N-BA25XI  
CY14B104N-ZSP25XCT  
CY14B104N-ZSP25XIT  
CY14B104N-ZSP25XI  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
Commercial  
Industrial  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
25  
Commercial  
Industrial  
Industrial  
Commercial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Document #: 001-07102 Rev. *L  
Page 16 of 25  
CY14B104L, CY14B104N  
Ordering Information (continued)  
Speed  
Package  
Diagram  
Operating  
Range  
Ordering Code  
(ns)  
Package Type  
44-pin TSOP II  
45  
CY14B104L-ZS45XCT  
CY14B104L-ZS45XIT  
CY14B104L-ZS45XI  
CY14B104L-BA45XCT  
CY14B104L-BA45XIT  
CY14B104L-BA45XI  
CY14B104L-ZSP45XCT  
CY14B104L-ZSP45XIT  
CY14B104L-ZSP45XI  
CY14B104N-ZS45XCT  
CY14B104N-ZS45XIT  
CY14B104N-ZS45XI  
CY14B104N-BA45XCT  
CY14B104N-BA45XIT  
CY14B104N-BA45XI  
CY14B104N-ZSP45XCT  
CY14B104N-ZSP45XIT  
CY14B104N-ZSP45XI  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
Commercial  
Industrial  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.  
Document #: 001-07102 Rev. *L  
Page 17 of 25  
CY14B104L, CY14B104N  
Part Numbering Nomenclature  
CY 14 B 104 L - ZS P 20 X C T  
Option:  
T - Tape & Reel  
Blank - Std.  
Temperature:  
C - Commercial (0 to 70°C)  
I - Industrial (–40 to 85°C)  
Speed:  
20 - 20 ns  
Pb-Free  
25 - 25 ns  
45 - 45 ns  
P - 54 Pin  
Blank - 44 Pin  
Package:  
BA - 48 FBGA  
ZS - TSOP II  
Data Bus:  
L - x8  
N - x16  
Density:  
104 - 4 Mb  
Voltage:  
B - 3.0V  
NVSRAM  
14 - Auto Store + Software Store + Hardware Store  
Cypress  
Document #: 001-07102 Rev. *L  
Page 18 of 25  
CY14B104L, CY14B104N  
Package Diagrams  
Figure 16. 44-Pin TSOP II (51-85087)  
DIMENSION IN MM (INCH)  
MAX  
MIN.  
PIN 1 I.D.  
22  
1
R
O
E
K
A
X
S G  
EJECTOR PIN  
23  
44  
TOP VIEW  
BOTTOM VIEW  
10.262 (0.404)  
10.058 (0.396)  
0.400(0.016)  
0.300 (0.012)  
0.800 BSC  
(0.0315)  
BASE PLANE  
0.10 (.004)  
0.210 (0.0083)  
0.120 (0.0047)  
0°-5°  
18.517 (0.729)  
18.313 (0.721)  
0.597 (0.0235)  
0.406 (0.0160)  
SEATING  
PLANE  
51-85087-*A  
Document #: 001-07102 Rev. *L  
Page 19 of 25  
CY14B104L, CY14B104N  
Package Diagrams (continued)  
Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.30 0.05(48X)  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85128-*D  
Document #: 001-07102 Rev. *L  
Page 20 of 25  
CY14B104L, CY14B104N  
Package Diagrams (continued)  
Figure 18. 54-Pin TSOP II (51-85160)  
51-85160-**  
Document #: 001-07102 Rev. *L  
Page 21 of 25  
CY14B104L, CY14B104N  
Document History Page  
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM  
Document Number: 001-07102  
Submission  
Date  
Orig. of  
Change  
Rev. ECN No.  
Description of Change  
**  
431039  
489096  
See ECN  
See ECN  
TUP  
TUP  
New Data Sheet  
Removed 48 SSOP Package  
*A  
Added 48 FBGA and 54 TSOPII Packages  
Updated Part Numbering Nomenclature and Ordering Information  
Added Soft Sequence Processing Time Waveform  
*B  
499597  
See ECN  
PCI  
Removed 35 ns speed bin  
Added 55 ns speed bin. Updated AC table for the same  
Changed “Unlimited” read/write to “infinite” read/write  
Features section: Changed typical I at 200-ns cycle time to 8 mA  
CC  
Changed STORE cycles from 500K to 200K cycles  
Shaded Commercial grade in operating range table  
Modified Icc/Is specs  
48 FBGA package nomenclature changed from BW to BV  
Modified part nomenclature table. Changes reflected in ordering information  
table  
*C  
517793  
See ECN  
TUP  
Removed 55ns speed bin  
Changed pinout for 44TSOPII and 54TSOPII packages  
Changed I to 1mA  
SB  
Changed I  
to 3mA  
CC4  
Changed V  
Changed V max to Vcc + 0.5V  
min to 35μF  
CAP  
IH  
Changed t  
Changed t  
Changed t  
to 15ms  
to 10ns  
to 15ns  
STORE  
PWE  
SCE  
Changed t to 5ns  
SD  
Changed t  
to 10ns  
AW  
Removed t  
HLBL  
Added Timing Parameters for BHE and BLE - t  
Removed min specification for Vswitch  
, t  
, t  
, t  
DBE LZBE HZBE BW  
Changed t  
to 1ns  
max of 70us  
GLAX  
Added t  
DELAY  
Changed t specification from 70us min to 70us max  
SS  
*D  
774001  
See ECN  
UHA  
Changed the data sheet from Advance information to Preliminary  
48 FBGA package code changed from BV to BA  
Removed 48 FBGA package in X8 configuration in ordering information.  
Changed t  
Changed t  
Changed t  
Changed t  
to 10ns in 15ns part  
DBE  
in 15ns part to 7ns and in 25ns part to10ns  
HZBE  
in 15ns part to 15ns and in 25ns part to 20ns  
BW  
to t  
GLAX  
GHAX  
Changed the value of I  
to 25mA  
CC3  
Changed the value of t  
in 15ns part to15ns  
AW  
Changed A and A Pins in FBGA Pin Configuration to NC  
18  
19  
*E  
914220  
See ECN  
UHA  
Included all the information for 45 ns part in this data sheet  
Document #: 001-07102 Rev. *L  
Page 22 of 25  
CY14B104L, CY14B104N  
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM  
Document Number: 001-07102  
Submission  
Date  
Orig. of  
Change  
Rev. ECN No.  
Description of Change  
*F  
1889928  
See ECN  
vsutmp8/AE- Added Footnotes 1, 2 and 3.  
SA  
Updated logic block diagram  
Added 48-FBGA (X8) Pin Diagram  
Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8).  
Updated pin definitions table.  
Corrected typo in V min spec  
IL  
Changed the value of I  
from 25mA to 13mA  
CC3  
Changed I value from 1mA to 2mA  
SB  
Rearranging of Footnotes.  
Updated ordering information table  
*G  
2267286  
See ECN  
GVCH/PYRS Added BHE and BLE Information in Pin Definitions Table  
Updated Figure 4 (Autostore mode)  
Updated footnote 6  
Changed I  
Changed I  
& I  
from 3 mA to 6 mA  
CC2  
CC3  
CC4  
from 13 mA to 15 mA  
Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max  
value  
Changed I from 2 mA to 3 mA  
SB  
Added input leakage current (I ) for HSB in DC Electrical Characteristics table  
IX  
Corrected typo in t  
Corrected typo in t  
Corrected typo in t  
value from 22 ns to 20 ns for 45 ns part  
value from 22 ns to 15 ns for 45 ns part  
value from 15 ns to 10ns for 15 ns part  
DBE  
HZBE  
AW  
Changed t  
from 100 to 200 us  
RECALL  
Added footnotes 9 and 25; Reframed footnote 14 and 21  
Added footnote 14 to figure 7 (SRAM WRITE Cycle #1)  
*H  
*I  
2483627  
2519319  
See ECN  
06/20/08  
GVCH/PYRS Removed 8 mA typical I at 200 ns cycle time in Feature section  
CC  
Referenced footnote 8 to I  
in DC Characteristics table  
CC3  
Changed I  
from 15 mA to 35 mA  
CC3  
Changed Vcap minimum value from 54 uF to 61 uF  
Changed t to t  
Figure 11:Changed t to t and t  
AVAV  
RC  
t
SA  
AS  
SCE to CW  
GVCH/PYRS Added 20 ns access speed in “Features”  
Added I  
for t =20 ns for both industrial and Commercial temperature  
CC1  
RC  
Grade  
updated Thermal resistance table values for 48-FBGA, 44-TSOP II and  
54-TSOP II Packages  
Added AC Switching Characteristics specs for 20 ns access speed  
Added software controlled STORE/RECALL cycle specs for 20 ns access  
speed  
Updated ordering information and part numbering nomenclature  
Document #: 001-07102 Rev. *L  
Page 23 of 25  
CY14B104L, CY14B104N  
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM  
Document Number: 001-07102  
Submission  
Date  
Orig. of  
Change  
Rev. ECN No.  
Description of Change  
*J  
2600941  
11/04/08  
GVCH/PYRS Removed 15 ns access speed  
Updated Logic block diagram  
Updated footnote 1  
Added footnote 2 and 5  
Pin definition: Updated WE, HSB and NC pin description  
Page 4:Updated SRAM READ, SRAM WRITE, Autostore operation description  
Page 4:Updated Hardware store operation and Hardware RECALL (Power-up)  
description  
Footnote 1 referenced for Mode selection Table  
Page 6:updated Data protection description  
Maximum Ratings: Added Max. Accumulated storage time  
Changed I  
Changed I  
from 6mA to 10mA  
from 6mA to 5mA  
CC2  
CC4  
Changed I from 3mA to 5mA  
SB  
Updated I  
I
I
and I Test conditions  
CC1, CC3 , SB  
OZ  
Changed V  
max value from 82uf to 180uF  
CAP  
Updated footnote 10 and 11  
Added footnote 12  
Added Data retention and Endurance Table  
Updated Input Rise and Fall time in AC test Conditions  
Referenced footnote 15 to t  
parameter  
OHA  
Updated All switching waveforms  
Added Figure 10 (SRAM WRITE CYCLE:BHE and BLE controlled)  
Changed t  
Changed t  
to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively  
from 15ms to 8ms  
DELAY  
STORE  
Added V  
, t  
and t  
parameters  
LZHSB  
HDIS HHHD  
Updated footnote 21  
Added footnote 24  
Software controlled STORE/RECALL cycle table: Changed t to t  
AS  
SA  
Changed t  
to t  
parameter  
GHAX  
HA  
Added t  
DHSB  
Changed t  
to t  
HLHX  
PHSB  
Updated t from 70us to 100us  
SS  
Added Truth table for SRAM operations  
Updated ordering information and part numbering nomenclature  
*K  
*L  
2612931  
2625431  
11/26/08  
12/19/08  
AESA  
Removed Preliminary form header.  
GVCH/DSG Changed t  
to 1us (min) and 70us (max) for all three access time  
DELAY  
Page 4: Removed the text relating to write requested after HSB goes LOW are  
inhibited.  
Page 5: modified software store description to indicate no further read/writes  
permitted for t duration after sixth read cycle.  
SS  
Added parameter t  
to AutoStore power-Up recall table  
PURHH  
Updated Figures 11, 12 and 13.  
Added t parameter  
HLBL  
Removed t  
parameter  
DHSB  
Updated Figure 14;Hardware store cycle  
Changed Simtek trademarks to Cypress  
Document #: 001-07102 Rev. *L  
Page 24 of 25  
CY14B104L, CY14B104N  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 001-07102 Rev. *L  
Revised December 19, 2008  
Page 25 of 25  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective  
holders.  

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