Cypress AutoStore STK17TA8 User Manual

STK17TA8  
128k X 8 AutoStore™ nvSRAM  
with Real Time Clock  
Features  
Description  
nvSRAMCombinedwithIntegratedRealTimeClockFunctions  
(RTC, Watchdog Timer, Clock Alarm, Power Monitor)  
The Cypress STK17TA8 combines a 1 Mb nonvolatile static RAM  
(nvSRAM) with a full featured real time clock in a reliable,  
monolithic integrated circuit.  
Capacitor or Battery Backup for RTC  
25, 45 ns Read Access and Read/Write Cycle Time  
Unlimited Read/Write Endurance  
The 1 Mb nvSRAM is a fast static RAM with a nonvolatile  
Quantum Trap storage element included with each memory cell.  
The SRAM provides the fast access and cycle times, ease of use  
and unlimited read and write endurance of a normal SRAM. Data  
transfers automatically to the nonvolatile storage cells when  
power loss is detected (the STORE operation). On power up,  
data is automatically restored to the SRAM (the RECALL  
operation). Both STORE and RECALL operations are also  
available under software control.  
Automatic nonvolatile STORE on Power Loss  
Nonvolatile STORE Under Hardware or Software Control  
Automatic RECALL to SRAM on Power Up  
Unlimited RECALL Cycles  
The real time clock function provides an accurate clock with leap  
year tracking and a programmable, high accuracy oscillator. The  
Alarm function is programmable for one-time alarms or periodic  
minutes, hours, or days alarms. There is also a programmable  
watchdog timer for processor control.  
200K STORE Cycles  
20-Year nonvolatile Data Retention  
Single 3 V +20%, -10% Power Supply  
Commercial and Industrial Temperatures  
48-pin 300-mil SSOP Package (RoHS-Compliant)  
Logic Block Diagram  
VCC  
VCAP  
Quantum Trap  
1024 X 1024  
A5  
A6  
A7  
A8  
VRTCbat  
VRTCcap  
POWER  
CONTROL  
STORE  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
1024 X 1024  
A9  
RECALL  
A12  
A13  
A14  
A15  
A16  
HSB  
SOFTWARE  
DETECT  
A15 – A0  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
COLUMN I/O  
X1  
COLUMN DEC  
RTC  
X2  
INT  
A0 A1 A2 A3 A4 A10 A11  
A16 – A0  
MUX  
G
E
W
Cypress Semiconductor Corporation  
Document #: 001-52039 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 02, 2009  
STK17TA8  
RF (SSOP-48) Package Thermal Characteristics  
θ 6.2 C/W; θ 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm]  
Absolute Maximum Ratings  
jc  
ja  
Voltage on Input Relative to Ground ................–0.1V to 4.1V  
Voltage on Input Relative to V .........–0.5V to (V + 0.5V)  
SS  
CC  
Note: Stresses greater than those listed under “Absolute  
Maximum Ratings” may cause permanent damage to the device.  
This is a stress rating only, and functional operation of the device  
at conditions above those indicated in the operational sections  
of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
reliablity.  
Voltage on DQ or HSB.....................–0.5V to (V + 0.5V)  
0-7  
CC  
Temperature under Bias ............................... –55°C to 125°C  
Junction Temperature................................... –55°C to 140°C  
Storage Temperature.................................... –65°C to 150°C  
Power Dissipation............................................................. 1W  
DC Output Current (1 output at a time, 1s duration)..... 15mA  
DC Electrical Characteristics  
(V = 2.7V-3.6V)  
CC  
Commercial  
Industrial  
Units  
Notes  
Symbol  
Parameter  
Average V Current  
Min  
Max  
Min  
Max  
I
65  
50  
70  
55  
mA  
mA  
t
t
= 25 ns  
= 45 ns  
CC  
CC  
AVAV  
1
AVAV  
Dependent on output loading and  
cycle rate. Values obtained  
without output loads.  
I
I
Average V Current during  
STORE  
3
3
mA All Inputs Don’t Care, V = max  
CC  
CC  
CC  
2
3
Average current for duration of  
STORE  
cycle (t  
)
STORE  
Average V Current at t  
=
10  
10  
mA W (V – 0.2V)  
CC  
CC  
CC  
AVAV  
200ns  
3V, 25°C, Typical  
All Other Inputs Cycling at CMOS  
Levels  
Dependent on output loading and  
cycle rate. Values obtained  
without output loads.  
I
I
Average V  
<Emphasis>AutoStore™ Cycle  
Current during  
3
3
3
3
mA All Inputs Don’t Care  
CC  
CAP  
4
Average current for duration of  
STORE cycle (t  
)
STORE  
V
Standby Current  
mA E ≥ (V -0.2V)  
SB  
CC  
CC  
(Standby, Stable CMOS Levels)  
All Others V 0.2V or ≥  
IN  
(V -0.2V)  
CC  
Standby current level after  
nonvolatile cycle complete  
I
I
Input Leakage Current  
±1  
±1  
±1  
±1  
mA  
mA  
V
V
= max  
CC  
ILK  
= V to V  
IN  
SS  
CC  
Off-State Output Leakage Current  
V
V
= max  
CC  
OLK  
= V to V , E or G V  
IN  
SS  
CC  
IH  
V
V
V
V
Input Logic “1” Voltage  
Input Logic “0” Voltage  
Output Logic “1” Voltage  
Output Logic “0” Voltage  
2.0  
–0.5  
V
+ 0.5  
2.0  
V + 0.5  
CC  
V
V
V
V
All Inputs  
All Inputs  
IH  
CC  
V
0.8  
V –0.5  
SS  
0.8  
IL  
SS  
2.4  
2.4  
I
I
=–2 mA (except HSB)  
= 4 mA  
OH  
OL  
OUT  
OUT  
0.4  
0.4  
Note: The HSB pin has I  
=-10uA for V of 2.4V, this parameter is characterized but not tested.  
OH  
OUT  
Note: The INT is open-drain and does not source or sink high current when interrupt Register bit D3 is below.  
Document #: 001-52039 Rev. **  
Page 3 of 23  
 
STK17TA8  
DC Electrical Characteristics (continued)  
(V = 2.7V-3.6V)  
CC  
Commercial  
Industrial  
Units  
Notes  
Symbol  
Parameter  
Min  
Max  
70  
Min  
Max  
85  
T
Operating Temperature  
Operating Voltage  
0
40  
2.7  
17  
°C  
A
V
2.7  
17  
3.6  
57  
3.6  
57  
V
3.0V +20%, -10%  
pin and V , 5V  
CC  
V
Storage Capacitance  
μF Between V  
CAP  
CAP  
SS  
rated.  
NV  
Nonvolatile STORE operations  
Data Retention  
200  
20  
200  
20  
K
C
DATA  
Years At 55 °C  
R
AC Test Conditions  
Input Pulse Levels ....................................................0V to 3V  
Input Rise and Fall Times ............................................ <5 ns  
Input and Output Timing Reference Levels .................... 1.5V  
Output Load..................................See Figure 2 and Figure 3  
Capacitance  
(T = 25°C, f = 1.0MHz)  
A
Parameter  
Input Capacitance  
Output Capacitance  
Max  
7
Units  
Conditions  
ΔV = 0 to 3V  
ΔV = 0 to 3V  
Symbol  
C
C
pF  
pF  
IN  
7
OUT  
Figure 2. AC Output Loading  
3.0V  
577 Ohms  
OUTPUT  
30 pF  
789 Ohms  
INCLUDING  
SCOPE AND  
FIXTURE  
Figure 3. AC Output Loading for Tristate Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ  
3.0V  
577 Ohms  
OUTPUT  
5 pF  
789 Ohms  
INCLUDING  
SCOPE AND  
FIXTURE  
Notes  
2. These parameters are guaranteed but not tested.  
Document #: 001-52039 Rev. **  
Page 4 of 23  
     
STK17TA8  
RTC DC Characteristics  
Commercial  
Industrial  
Symbol  
Parameter  
Units  
Notes  
Min  
Max  
300  
3.3  
Min  
Max  
350  
3.3  
IBAK  
VRTCbat  
RTC Backup Current  
nA  
V
From either V  
or V  
RTCcap RTCbat  
RTC Battery Pin Voltage  
1.8  
1.8  
Typical = 3.0 Volts during normal  
operation  
VRTCcap  
tOSCS  
RTC Capacitor Pin Voltage  
RTC Oscillator time to start  
1.2  
2.7  
10  
5
1.2  
2.7  
10  
5
V
Typical = 2.4 Volts during normal  
operation  
sec  
sec  
AtMINTemperature from Power up  
or Enable  
At 25°C from Power up or Enable  
Figure 4. RTC Recommended Component Configuration  
X1  
X2  
Recommended Values  
Y1  
= 32.768 KHz  
= 10M Ohm  
RF  
C1  
= 0 (install cap footprint,  
but leave unloaded)  
C2 = 56 pF ± 10% (do not vary from this value)  
Document #: 001-52039 Rev. **  
Page 5 of 23  
STK17TA8  
SRAM READ Cycles #1 and #2  
Symbols  
NO.  
STK17TA8-25 STK17TA8-45  
Parameter  
Chip Enable Access Time  
Units  
#1  
#2  
Alt.  
Min  
Max  
Min  
Max  
1
2
3
4
5
6
7
t
t
t
t
t
t
t
t
t
t
t
t
t
t
25  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ELQV  
ACS  
RC  
AA  
[3]  
[3]  
t
t
Read Cycle Time  
25  
45  
AVAV  
ELEH  
[4]  
Address Access Time  
25  
12  
45  
20  
AVQV  
AVQV  
GLQV  
AXQX  
ELQX  
EHQZ  
Output Enable to Data Valid  
Output Hold after Address Change  
Address Change or Chip Enable to Output Active  
OE  
OH  
LZ  
[4]  
[4]  
[5]  
t
3
3
3
3
AXQX  
Address Change or Chip Disable to Output  
Inactive  
10  
15  
HZ  
8
9
t
t
t
t
t
t
t
t
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
0
0
0
0
ns  
ns  
ns  
ns  
GLQX  
OLZ  
OHZ  
PA  
10  
25  
15  
45  
GHQZ  
10  
11  
ELICCL  
EHICCH  
PS  
Figure 5. SRAM READ Cycle #1: Address Controlled  
tAVAV  
ADDRESS  
tAVQV  
tAXQX  
DQ (DATA OUT)  
DATA VALID  
Figure 6. SRAM READ Cycle #2: E and G Controlled  
Notes  
3. W must be high during SRAM READ cycles.  
4. Device is continuously selected with E and G both low  
5. Measured ± 200mV from steady state output voltage.  
6. HSB must remain high during READ and WRITE cycles.  
Document #: 001-52039 Rev. **  
Page 6 of 23  
                             
STK17TA8  
SRAM WRITE Cycles #1 and #2  
Symbols  
NO.  
STK17TA8-25 STK17TA8-45  
Parameter  
Write Cycle Time  
Units  
#1  
#2  
Alt.  
Min  
25  
20  
20  
10  
0
Max  
Min  
45  
30  
30  
15  
0
Max  
11  
13  
14  
15  
16  
17  
18  
19  
20  
21  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AVAV  
AVAV  
WC  
Write Pulse Width  
WLWH  
ELWH  
DVWH  
WHDX  
AVWH  
AVWL  
WHAX  
WLEH  
ELEH  
DVEH  
EHDX  
AVEH  
AVEL  
EHAX  
WP  
CW  
DW  
DH  
AW  
AS  
Chip Enable to End of Write  
Data Set-up to End of Write  
Data Hold after End of Write  
Address Set-up to End of Write  
Address Set-up to Start of Write  
Address Hold after End of Write  
Write Enable to Output Disable  
Output Active after End of Write  
20  
0
30  
0
0
0
WR  
WZ  
OW  
10  
15  
WLQZ  
WHQX  
3
3
Figure 7. SRAM WRITE Cycle #1: W Controlled  
tAVAV  
ADDRESS  
tWHAX  
tELWH  
E
tAVWH  
tAVWL  
tWLWH  
W
tDVWH  
tWHDX  
DATA IN  
DATA IN  
DATA VALID  
tWLQZ  
tWHQX  
HIGH IMPEDANCE  
DATA OUT  
PREVIOUS DATA  
Figure 8. SRAM WRITE Cycle #2: E Controlled  
tAVAV  
ADDRESS  
E
tAVEL  
tELEH  
tEHAX  
tAVEH  
tWLEH  
W
tDVEH  
tEHDX  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes  
7. If W is low when E goes low, the outputs remain in the high-impedance state.  
8. E or W must be VIH during address transitions.  
Document #: 001-52039 Rev. **  
Page 7 of 23  
                       
STK17TA8  
AutoStore/Power Up Recall  
Symbols  
NO.  
STK17TA8  
Parameter  
Power-up RECALL Duration  
Units  
Notes  
Standard  
Alternate  
Min  
Max  
40  
22  
23  
24  
25  
t
t
ms  
ms  
V
HRECALL  
STORE  
t
STORE Cycle Duration  
12.5  
2.65  
HLHZ  
V
V
Low Voltage Trigger Level  
SWITCH  
CCRISE  
V
Rise Time  
150  
μS  
CC  
Figure 9. AutoStore/Power Up RECALL  
NOTE: Read and Write cycles will be ignored during STORE, RECALL and while V is below V  
CC  
SWITCH  
Notes  
9.  
t
starts from the time V rises above V  
CC SWITCH  
HRECALL  
10. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place  
11. Industrial Grade Devices require 15 ms MAX.  
Document #: 001-52039 Rev. **  
Page 8 of 23  
           
STK17TA8  
Software-Controlled STORE/RECALL Cycle  
In the following table, the software controlled STORE and RECALL cycle parameters are listed.  
Symbols  
G Cont Alternate  
STK17TA8-35 STK17TA8-45  
NO.  
Parameter  
Units Notes  
E Cont  
Min  
Max  
Min  
Max  
26  
t
t
t
RC  
STORE / RECALL Initiation Cycle  
Time  
25  
45  
ns  
AVAV  
AVAV  
27  
28  
29  
30  
t
t
t
t
t
t
t
t
tAS  
Address Set-up Time  
Clock Pulse Width  
Address Hold Time  
RECALL Duration  
0
20  
1
0
30  
1
ns  
ns  
ns  
μs  
AVEL  
AVGL  
tCW  
ELEH  
GLGH  
GHAX  
RECALL  
EHAX  
RECALL  
100  
100  
Figure 10. Software STORE/RECALL Cycle: E CONTROLLED  
Figure 11. Software STORE/RECALL Cycle: G Controlled  
Notes  
12. The software sequence is clocked on the falling edge of E controlled READs or G controlled READs  
13. The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table W must be high during all six consecutive cycles.  
Document #: 001-52039 Rev. **  
Page 9 of 23  
             
STK17TA8  
Hardware STORE Cycle  
Symbols  
NO.  
STK17TA8  
Min Max  
70  
Parameter  
Units  
Notes  
Standard Alternate  
31  
32  
t
t
t
Hardware STORE to SRAM Disabled  
Hardware STORE Pulse Width  
1
μs  
DELAY  
HLHX  
HLQZ  
15  
ns  
Figure 12. Hardware STORE Cycle  
Soft Sequence Commands  
NO.  
Symbols  
Standard  
Parameter  
STK17TA8  
Min Max  
70  
Units  
Notes  
33  
t
Soft Sequence Processing Time  
μs  
SS  
Figure 13. Soft Sequence Commands  
Notes  
14. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow READ/WRITE cycles to compete.  
15. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.  
16. Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.  
Document #: 001-52039 Rev. **  
Page 10 of 23  
           
STK17TA8  
MODE Selection  
E
W
G
A
-A  
Mode  
I/O  
Power  
Notes  
16  
0
H
L
L
L
X
H
L
X
L
X
L
X
Not Selected  
Read SRAM  
Write SRAM  
Output High Z  
Output Data  
Input Data  
Standby  
Active  
X
X
Active  
H
0x04E38  
0x0B1C7  
0x083E0  
0x07C1F  
0x0703F  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
0x08FC0  
Nonvolatile Store  
Output High Z  
I
CC2  
L
H
L
0x04E38  
0x0B1C7  
0x083E0  
0x07C1F  
0x0703F  
0x04C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Active  
Nonvolatile Recall  
Notes  
17. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.  
18. While there are 17 addresses on the STK17TA8, only the lower 16 are used to control software modes  
19. I/O state depends on the state of G. The I/O table shown assumes G low  
Document #: 001-52039 Rev. **  
Page 11 of 23  
     
STK17TA8  
(activated by HSB), Software Store (activated by an address  
sequence), and AutoStore (on power down).  
nvSRAM Operation  
The STK17TA8 nvSRAM is made up of two functional compo-  
nents paired in the same physical cell. These are the SRAM  
memory cell and a nonvolatile QuantumTrap cell. The SRAM  
memory cell operates like a standard fast static RAM. Data in the  
SRAM can be transferred to the nonvolatile cell (the STORE  
operation), or from the nonvolatile cell to SRAM (the RECALL  
operation). This unique architecture enables all cells to be stored  
and recalled in parallel. During the STORE and RECALL opera-  
tions SRAM READ and WRITE operations are inhibited. The  
STK17TA8 supports unlimited read and writes like a typical  
SRAM. In addition, it provides unlimited RECALL operations  
from the nonvolatile cells and up to 200K STORE operations.  
AutoStore operation, a unique feature of Cypress QuanumTrap  
technology is a standard feature on the STK17TA8.  
During normal operation, the device draws current from V to  
CC  
charge a capacitor connected to the V  
pin. This stored  
CAP  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the V pin drops below V , the part  
CC  
SWITCH  
automatically disconnects the V  
pin from V . A STORE  
CAP  
CC  
operation is initiated with power provided by the V  
capacitor.  
CAP  
Figure 14 shows the proper connection of the storage capacitor  
(V ) for automatic store operation. Refer to the DC Electrical  
CAP  
Characteristics on page 3 for the size of the capacitor. The  
voltage on the V pin is driven to 5V by a charge pump internal  
CAP  
SRAM READ  
to the chip. A pull up should be placed on W to hold it inactive  
during power up.  
The STK17TA8 performs a READ cycle whenever E and G are  
low while W and HSB are high. The address specified on pins  
To reduce unneeded nonvolatile stores, AutoStore and  
Hardware Store operations are ignored unless at least one  
WRITE operation has taken place since the most recent STORE  
or RECALL cycle. Software initiated STORE cycles are  
performed regardless of whether a WRITE operation has taken  
place. The HSB signal can be monitored by the system to detect  
an AutoStore cycle is in progress.  
A
determine which of the 131,072 data bytes are accessed.  
0-16  
When the READ is initiated by an address transition, the outputs  
are valid after a delay of t (READ cycle #1). If the READ is  
AVQV  
initiated by E and G, the outputs are valid at t  
whichever is later (READ cycle #2). The data outputs repeatedly  
respond to address changes within the t access time  
without the need for transitions on any control input pins, and  
remain valid until another address change or until E or G is  
brought high, or W and HSB is brought low.  
or at t  
,
ELQV  
GLQV  
AVQV  
Hardware STORE (HSB) Operation  
The STK17TA8 provides the HSB pin for controlling and  
acknowledging the STORE operations. The HSB pin can be  
used to request a hardware STORE cycle. When the HSB pin is  
driven low, the STK17TA8 conditionally initiates a STORE  
Figure 14. AutoStore Mode  
VCC  
VCAP  
VCC  
operation after t  
. An actual STORE cycle only begins if a  
DELAY  
WRITE to the SRAM took place since the last STORE or  
RECALL cycle. The HSB pin has a very resistive pullup and is  
internally driven low to indicate a busy condition while the  
STORE (initiated by any means) is in progress. This pin should  
be externally pulled up if it is used to drive other inputs.  
W
SRAM READ and WRITE operations that are in progress when  
HSB is driven low by any means are given time to complete  
before the STORE operation is initiated. After HSB goes low, the  
STK17TA8 continues to allow SRAM operations for t  
.
DELAY  
During t  
, multiple SRAM READ operations may take place.  
DELAY  
If a WRITE is in progress when HSB is pulled low, it is allowed a  
time, t , to complete. However, any SRAM WRITE cycles  
DELAY  
requested after HSB goes low is inhibited until HSB returns high.  
SRAM WRITE  
If HSB is not used, it should be left unconnected.  
A WRITE cycle is performed whenever E and W are low and HSB  
is high. The address inputs must be stable prior to entering the  
WRITE cycle and must remain stable until either E or W goes  
high at the end of the cycle. The data on the common I/O pins  
Hardware RECALL (POWER-UP)  
During power up or after any low power condition  
(V <V  
), an internal RECALL request is latched. When  
CC  
SWITCH  
DQ0-7 is written into memory if it is valid t  
before the end  
DVWH  
V
once again exceeds the sense voltage of V  
, a  
SWITCH  
CC  
of a W controlled WRITE or t  
controlled WRITE.  
before the end of an E  
DVEH  
RECALL cycle is automatically initiated and takes t  
complete.  
to  
HRECALL  
It is recommended that G be kept high during the entire WRITE  
cycle to avoid data bus contention on common I/O lines. If G is  
Software STORE  
left low, internal circuitry turns off the output buffers t  
W goes low.  
after  
WLQZ  
Data can be transferred from the SRAM to the nonvolatile  
memory by a software address sequence. The STK17TA8  
software STORE cycle is initiated by executing sequential E  
controlled or G controlled READ cycles from six specific address  
locations in exact order. During the STORE cycle, previous data  
is erased and then the new data is programmed into the nonvol-  
AutoStore Operation  
The STK17TA8 stores data to nvSRAM using one of three  
storage operations. These three operations are Hardware Store  
Document #: 001-52039 Rev. **  
Page 12 of 23  
 
STK17TA8  
atile elements. Once a STORE cycle is initiated, further memory  
inputs and outputs are disabled until the cycle is completed.  
Preventing AutoStore  
Because of the use of nvSRAM to store critical RTC data, the  
AutoStore function cannot be disabled on the STK17TA8.  
To initiate the Software STORE cycle, the following read  
sequence must be performed:  
Best Practices  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x8FC0 Initiate STORE Cycle  
nvSRAM products have been used effectively for over 15 years.  
While ease-of-use is one of the product’s main system values,  
experience gained working with hundreds of applications has  
resulted in the following suggestions as best practices:  
The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sitessometimesreprogramthesevalues. FinalNVpatternsare  
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End  
product’s firmware should not assume an NV array is in a set  
programmed state. Routines that check memory content  
values to determine first time system configuration, cold or  
warm boot status, should always program a unique NV pattern  
(for example, complex 4-byte pattern of 46 E6 49 53 hex or  
more random bytes) as part of the final system manufacturing  
test to ensure these system routines work consistently.  
Once the sixth address in the sequence has been entered, the  
STORE cycle starts and the chip is disabled. It is important that  
READ cycles and not WRITE cycles be used in the sequence  
and that G is active. After the t  
cycle time has been fulfilled,  
STORE  
the SRAM is again activated for READ and WRITE operation.  
Software RECALL  
Data is transferred from nonvolatile memory to the SRAM by a  
software address sequence. A Software RECALL cycle is  
initiated with a sequence of READ operations in a manner similar  
to the Software STORE initiation. To initiate the RECALL cycle,  
the following sequence of E or G controlled or READ operations  
must be performed:  
Power up boot firmware routines should rewrite the nvSRAM  
into the desired state (autostore enabled and so on). While the  
nvSRAM is shipped in a preset state, best practice is to again  
rewrite the nvSRAM into the desired state as a safeguard  
against events that might flip the bit inadvertently (program  
bugs, incoming inspection routines, and so on.  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x4C63 Initiate RECALL Cycle  
The OSCEN bit in the Calibration register at 0x1FFF8 should  
be set to 1 to preserve battery life when the system is in storage  
The V  
value specified in this data sheet includes a minimum  
cap  
Internally, RECALL is a two-step procedure. First, the SRAM  
data is cleared, and second, the nonvolatile information is trans-  
and a maximum value size. Best practice is to meet this  
requirement and not exceed the max V  
nvSRAM internal algorithm calculates V  
on this max Vcap value. Customers that want to use a larger  
value because the  
charge time based  
cap  
ferred into the SRAM cells. After the t  
cycle time, the  
RECALL  
cap  
SRAM is once again be ready for READ or WRITE operations.  
The RECALL operation in no way alters the data in the nonvol-  
atile storage elements.  
V
value to make sure there is extra store charge and store  
cap  
time should discuss their V  
understand any impact on the V  
size selection with Cypress to  
cap  
Data Protection  
voltage level at the end of  
cap  
a t  
period.  
RECALL  
The STK17TA8 protects data from corruption during low-voltage  
conditions by inhibiting all externally initiated STORE and  
WRITE operations. The low voltage condition is detected when  
Low Average Active Power  
CMOS technology provides the STK17TA8 with the benefit of  
power supply current that scales with cycle time. Less current is  
drawn as the memory cycle time becomes longer than 50 ns.  
V
<V  
.
CC  
SWITCH  
If the STK17TA8 is in a WRITE mode (both E and W low) at  
power-up, after a RECALL, or after a STORE, the WRITE will be  
inhibited until a negative transition on E or W is detected. This  
protects against inadvertent writes during power up or brown out  
conditions.  
Figure 15 shows the relationship between  
READ/WRITE cycle time. Worst-case current consumption is  
shown for commercial temperature range, V =3.6V, and chip  
enable at maximum frequency. Only standby current is drawn  
when the chip is disabled. The overall average current drawn by  
the STK17TA8 depends on the following items:  
I
and  
CC  
CC  
Noise Considerations  
The STK17TA8 is a high speed memory and so must have a high  
frequency bypass capacitor of 0.1 µF connected between both  
1. The duty cycle of chip enable.  
2. The overall cycle rate for accesses.  
3. The ration of READs to WRITEs.  
4. The operating temperature.  
5. The VCC level.  
V
pins and V ground plane with no plane break to chip V  
.
CC  
SS  
SS  
Use leads and traces that are as short as possible. As with all  
high speed CMOS ICs, careful routing of power, ground, and  
signals reduces circuit noise.  
6. I/O loading.  
Document #: 001-52039 Rev. **  
Page 13 of 23  
STK17TA8  
Figure 15. Current versus Cycle Time  
You can power the real time clock with either a capacitor or a  
battery. Factors to be considered when choosing a backup  
power source include the expected duration of power outages  
and the cost and reliability trade-off of using a battery versus a  
capacitor.  
If you select a capacitor power source, connect the capacitor to  
the V  
pin and leave the V  
pin unconnected.  
RTCcap  
RTCbat  
Capacitor backup time values based on maximum current specs  
are shown below. Nominal times are approximately three times  
longer.  
Capacitor Value  
0.1 F  
Backup Time  
72 hours  
14 days  
0.47 F  
1.0 F  
30 days  
A capacitor has the obvious advantage of being more reliable  
and not containing hazardous materials. The capacitor is  
recharged every time the power is turned on so that real time  
clock continues to have the same backup time over years of  
operation.  
RTC Operations  
Real Time Clock  
The clock registers maintain time up to 9,999 years in one  
second increments. The user can set the time to any calendar  
time and the clock automatically keeps track of days of the week  
and month, leap years, and century transitions. There are eight  
registers dedicated to the clock functions which are used to set  
time with a write cycle and to read time during a read cycle.  
These registers contain the Time of Day in BCD format. Bits  
defined as "0" are currently not used and are reserved for future  
use by Cypress.  
If you select a battery power source, connect the battery to the  
V
pin and leave the V  
pin unconnected. A 3V lithium  
RTCbat  
RTCcap  
battery is recommended for this application. The battery capacity  
should be chosen for the total anticipated cumulative down-time  
required over the life of the system.  
The real time clock is designed with a diode internally connected  
to the V  
pin. This prevents the battery from ever being  
RTCbat  
charged by the circuit.  
Reading The Clock  
Stopping And Starting The RTC Oscillator  
The user should halt internal updates to the real time clock  
registers before reading clock data to prevent the reading of data  
in transition. Stopping the internal register updates does not  
affect clock accuracy.  
The OSCEN bit in Calibration register at 0x1FFF8 enables RTC  
oscillator operation. This bit is nonvolatile and shipped to  
customers in the “enabled” state (set to 0). OSCEN should be set  
to a 1 to preserve battery life while the system is in storage. This  
turns off the oscillator circuit extending the battery life. If the  
OSCEN bit goes from disabled to enabled, it typically takes 5  
seconds (10 seconds max) for the oscillator to start.  
Write a “1” to the read bit "R" (in the Flags register at 0x1FFF0)  
captures the current time in holding registers. Clock updates will  
not restart until a “0” is written to the read bit. The RTC registers  
can then be read while the internal clock continues to run.  
The STK17TA8 has the ability to detect oscillator failure due to  
loss of backup power. The failure is recorded by the OSCF  
(Oscillator Failed) bit of the Flags register (at address 0x1FFF0).  
Within 20ms after a “0” is written to the read bit, all real time clock  
registers are simultaneously updated.  
When the device is powered on (V goes above V  
), the  
Setting The Clock  
CC  
SWITCH  
OSCEN bit is checked for "enabled" status. If the OSCEN bit is  
enabled and the oscillator is not active within the first 5 ms, the  
OSCF bit is set. The user should check for this condition and then  
write a 0 to clear the flag. When the OSCF flag bit is set, the real  
time clock registers are reset to the “Base Time” (see the section  
"Setting the Clock"), the value last written to the real time clock  
registers.  
Set the write bit “W” (in the Flags register at 0x1FFF0) to a "1" to  
enable the time to be set. The correct day, date and time can then  
be written into the real time clock registers in 24-hour BCD  
format. The time written is referred to as the "Base Time." This  
value is stored in nonvolatile registers and used in calculation of  
the current time. Reset the write bit to "0" to transfer the time to  
the actual clock counters. The clock starts counting at the new  
base time.  
The value of OSCF should be reset to 0 when the real time clock  
registers are written for the first time. This initializes the state of  
this bit which may have become set when the system was first  
powered on.  
Backup Power  
The RTC in intended to keep time even when system power is  
To reset OSCF, set the write bit “W” (in the Flags register at  
0x1FFF0) to a "1" to enable writes to the Flag register. Write a  
“0” to the OSCF bit. and thenreset the write bit to "0" to disable  
writes.  
lost. When primary power, V , drops below V  
time clock switches to the backup power supply connected to  
, the real  
CC  
SWITCH  
either the V or V pin.  
RTCcap  
RTCbat  
The clock oscillator uses a maximum of 300 nanoamps at 2 volts  
to maximize the backup time available from the backup source.  
Document #: 001-52039 Rev. **  
Page 14 of 23  
   
STK17TA8  
The alarm value should be initialized on power-up by software  
since the alarm registers are not nonvolatile.  
Calibrating The Clock  
The RTC is driven by a quartz controlled oscillator with a nominal  
frequency of 32.768 KHz. Clock accuracy will depend on the  
quality of the crystal, specified (usually 35 ppm at 25 C). This  
error could equate to 1.53 minutes gain or loss per month. The  
STK17TA8 employs a calibration circuit that can improve the  
accuracy to +1/-2 ppm at 25 C. The calibration circuit adds or  
subtracts counts from the oscillator divider circuit.  
To set or clear Alarm registers, set the write bit “W” (in the Flags  
register at 0x1FFF0) to a "1" to enable writes to the Alarm  
registers. Write an alarm value to the alarm registers and then  
reset the write bit to "0" to disable writes.  
Watchdog Timer  
The watchdog timer is designed to interrupt or reset the  
processor should the program get hung in a loop and not  
respond in a timely manner. The software must reload the  
watchdog timer before it counts down to zero to prevent this  
interrupt or reset.  
The number of time pulses are added or substracted depends  
upon the value loaded into the five calibration bits found in  
Calibration register (at 0x1FFF8). Adding counts speeds the  
clock up; subtracting counts slows the clock down. The  
Calibration bits occupy the five lower order bits of the register.  
These bits can be set to represent any value between 0 and 31  
in binary form. Bit D5 is a Sign bit, where a “1” indicates positive  
calibration and a “0” indicates negative calibration. Calibration  
occurs during a 64 minute period. The first 62 minutes in the  
cycle may, once per minute, have one second either shortened  
by 128 or lengthened by 256 oscillator cycles.  
The watchdog timer is a free running down counter that uses the  
32 Hz clock (31.25 ms) derived from the crystal oscillator. The  
watchdog timer function does no operate unless the oscillator is  
running.  
The watchdog counter is loaded with a starting value from the  
load register and then counts down to zero setting the watchdog  
flag (WDF) and generating an interrupt if the watchdog interrupt  
is enabled. The watchdog flag bit is reset when the flag register  
is read. The operating software would normally reload the  
counter by setting the watchdog strobe bit (WDS) to 1 within the  
timing interval programmed into the load register.  
If a binary “1” is loaded into the register, only the first 2 minutes  
of the 64 minute cycle is modified; if a binary 6 is loaded, the first  
12 will be affected, and so on. Therefore each calibration step  
has the effect of adding 512 or subtracting 256 oscillator cycles  
for every 125,829,120 actual oscillator cycles. That is +4.068 or  
-2.034 ppm of adjustment per calibration step in the calibration  
register.  
To use the watchdog timer to reset the processor on timeout, the  
INT is tied to processor master reset and Interrupt register is  
programmed to 24h to enable interrupts to pulse the reset pin on  
timeout.  
The calibration register value is determined during system test  
by setting the CAL bit in the Flags register (at 0x1FFF0) to 1. This  
causes the INT pin to toggle at a nominal 512 Hz. This frequency  
can be measured with a frequency counter. Any deviation  
measured from the 512 Hz will indicate the degree and direction  
of the required correction. For example, a reading of 512.01024  
Hz would indicate a +20 ppm error, requiring a -10 (001010) to  
be loaded into the Calibration register. Note that setting or  
changing the calibration register does not affect the frequency  
test output frequency.  
To load the watch dog timer, set a new value into the load register  
by writing a “0” to the watchdog write bit (WDW) of the watchdog  
register (at 01x1FFF7). Then load a new value into the load  
register. Once the new value is loaded, the watchdog write bit is  
then set to 1 to disable watchdog writes. The watchdog strobe  
bit (WDS) is then set to 1 to load this value into the watchdog  
timer.  
Note Setting the load register to zero disables the watchdog  
timer function.  
To set or clear CAL, set the write bit “W” (in the Flags register at  
0x1FFF0) to a "1" to enable writes to the Flag register. Write a  
value to CAL. and then reset the write bit to "0" to disable writes.  
The system software should initialize the watchdog load register  
on power-up to the desired value since the register is not nonvol-  
atile.  
The default Calibration register value from the factory is 00h. The  
user calibration value loaded is retained during a power loss.  
Power Monitor  
Alarm  
The STK17TA8 provides a power monitor function. The power  
monitor is based on an internal band-gap reference circuit that  
The alarm function compares a user-programmable alarm  
time/date (stored in registers 0x1FFF1-5) with the real time clock  
time-of-day/date values. When a match occurs, the alarm flag  
(AF) is set and an interrupt is generated if the alarm interrupt is  
enabled. The alarm flag is automatically reset when the Flags  
register is read.  
compares the V voltage to V  
.
CC  
SWITCH  
When the power supply drops below V  
, the real time clock  
SWITCH  
circuit is switched to the backup supply (battery or capacitor) .  
When operating from the backup source, no data may be read  
or written to the nvSRAM and the clock functions are not  
available to the user. The clock continues to operate in the  
Each of the alarm registers has a match bit as its MSB. Setting  
the match bit to a 1 disables this alarm register from the alarm  
comparison. When the match bit is 0, the alarm register is  
compared with the equivalent real time clock register. Using the  
match bits, the alarm can occur as specifically as one particular  
second on one day of the month or as frequently as once per  
minute.  
background. Updated clock data is available to the user t  
HRECALL  
delay after VCC has been restored to the device.  
When power is lost, the PF flag in the Flags Register is set to  
indicate the power failure and an interrupt is generated if the  
power fail interrupt is enabled (interrupt register=20h). This line  
would normally be tied to the processor master reset input for  
perform power-off reset.  
Note The product requires the match bit for seconds(1x1FFF2 -  
D7) be set to 0 for proper operation of the Alarm Flag and  
Interrupt.  
Document #: 001-52039 Rev. **  
Page 15 of 23  
STK17TA8  
Power Fail Interrupt Enable (PFE). When set to 1, the INT pin is  
driven by a power fail signal from the power monitor circuit. When  
set to 0, only the PF flag is set.  
Interrupts  
The STK17TA8 has a Flags register, Interrupt Register, and  
interrupt logic that can interrupt a microcontroller or generate a  
power-up master reset signal. There are three potential interrupt  
sources: the watchdog timer, the power monitor, and the clock  
alarm. Each can be individually enabled to drive the INT pin by  
setting the appropriate bit in the Interrupt register. In addition,  
each has an associated flag bit in the Flags register that the host  
processor can read to determine the interrupt source. Two bits in  
the Interrupt register determine the operation of the INT pin  
driver.  
High/Low (H/L). When set to a 1, the INT pin is active high and  
the driver mode is push-pull. The INT pin can drive high only  
when V >V  
. When set to a 0, the INT pin is active low  
CC  
SWITCH  
and the drive mode is open-drain. The active low (open drain)  
output is maintained even when power is lost .  
Pulse/Level (P/L). When set to a 1, the INT pin is driven for  
approximately 200 ms when an interrupt occurs. The pulse is  
reset when the Flags register is read. When P/L is set to a 0, the  
INT pin is driven high or low (determined by H/L) until the Flags  
register is read.  
A functional diagram of the interrupt logic is shown below:  
Figure 16. Interrupt Block Diagram  
The Interrupt register is loaded with the default value 00h at the  
factory. The user should configure the Interrupt register to the  
value desired for their desired mode of operation. Once  
configured, the value is retained during power failures.  
WDF  
Watchdog  
Timer  
WIE  
VCC  
PF  
P/L  
Power  
Monitor  
Pin  
Driver  
INT  
Flags Register  
PFE  
The Flags register has three flag bits: WDF, AF, and PF. These  
flags are set by the watchdog time-out, alarm match, or power  
fail monitor respectively. The processor can either poll this  
register or enable interrupts to be informed when a flag is set.  
The flags are automatically reset once the register is read.  
H/L  
VINT  
VSS  
AF  
Clock  
Alarm  
AIE  
The Flags register is automatically loaded with the value 00h on  
power up (with the exception of the OSCF bit).  
Interrupt Register  
Watchdog Interrupt Enable (WIE). When set to 1, the watchdog  
timer drives the INT pin when a watchdog time-out occurs. When  
WIE is set to 0, the watchdog time-out only sets the WDF flag bit.  
Alarm Interrupt Enable (AIE). When set to 1, the INT pin is driven  
when an alarm match occurs. When set to 0, the alarm match  
only sets the AF flag bit.  
Document #: 001-52039 Rev. **  
Page 16 of 23  
STK17TA8  
RTC Register  
BCD Format Data  
Register  
Function / Range  
D7  
0
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0x1FFFF  
0x1FFFE  
10s Years  
0
Years  
Months  
Years: 00-99  
0
10s  
Months: 01-12  
Months  
0x1FFFD  
0
0
10s Day of  
Month  
Day of Month  
Day of Week  
Day of Month: 01-31  
0x1FFFC  
0x1FFFB  
0x1FFFA  
0x1FFF9  
0x1FFF8  
0
0
0
0
0
0
0
0
0
Day of week: 01-07  
Hours: 00-23  
10s Hours  
10s Minutes  
Hours  
Minutes  
Seconds  
Minutes: 00-59  
Seconds: 00-59  
Calibration values*  
10s Seconds  
OSCEN  
[0]  
0
Cal  
Sign  
Calibration[00000]  
0x1FFF7  
0x1FFF6  
WDS  
WDW  
WDT  
Watchdog*  
Interrupts*  
WIE [0]  
AIE [0]  
PFE  
[0]  
0
H/L  
[1]  
P/L [0]  
0
0
0x1FFF5  
0x1FFF4  
0x1FFF3  
0x1FFF2  
0x1FFF1  
0x1FFF0  
M
M
M
M
0
0
10s Alarm Date  
10s Alarm Hours  
Alarm Day  
Alarm, Day of Month: 01-31  
Alarm, hours: 00-23  
Alarm, minutes: 00-59  
Alarm, seconds: 00-59  
Centuries: 00-99  
Alarm Hours  
Alarm Minutes  
Alarm Seconds  
Centuries  
10 Alarm Minutes  
10 Alarm Seconds  
10s Centuries  
AF PF  
WDF  
OSCF  
0
CAL[0]  
W[0]  
R[0]  
Flags*  
* A binary value, not a BCD value.  
0 - Not implemented, reserved for future use.  
Default Settings of nonvolatile Calibration and Interrupt registers from factory  
Calibration Register=00h  
Interrupt Register=00h  
The User should configure to desired value at startup or during operation and the value is then retained during a power failure.  
[ ] designates values shipped from the factory. See “Stopping And Starting The RTC Oscillator” on page 14 .  
Document #: 001-52039 Rev. **  
Page 17 of 23  
STK17TA8  
Register Map Detail  
Real Time Clock – Years  
D4 D3  
0x1FFFF  
D7  
D6  
D5  
D2  
D1  
D0  
10s Years  
Years  
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains  
the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99.  
Real Time Clock – Months  
0x1FFFE  
0x1FFFD  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
0
10s Month  
Months  
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble  
(one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12.  
Real Time Clock – Date  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
10s Day of month  
Day of month  
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9;  
upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31. Leap years are  
automatically adjusted for.  
Real Time Clock – Day  
0x1FFFC  
0x1FFFB  
0x1FFFA  
0x1FFF9  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
0
0
0
Day of week  
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from  
1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the date.  
Real Time Clock – Hours  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
10s Hours  
Hours  
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to  
9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23.  
Real Time Clock – Minutes  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Minutes  
D0  
0
10s Minutes  
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble  
contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59.  
Real Time Clock – Seconds  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Seconds  
D0  
0
10s Seconds  
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble  
contains the upper digit and operates from 0 to 5. The range for the register is 0-59.  
Calibration  
0x1FFF8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
OSCEN  
0
Calibration  
Sign  
Calibration  
OSCEN  
Oscillator Enable. When set to 1, the oscillator is disabled. When set to 0, the oscillator is enabled. Disabling the  
oscillator saves battery/capacitor power during storage.  
Calibration  
Sign  
Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.  
Calibration  
These five bits control the calibration of the clock.  
Document #: 001-52039 Rev. **  
Page 18 of 23  
STK17TA8  
Register Map Detail (continued)  
Watchdog Timer  
D4 D3  
0x1FFF7  
D7  
D6  
D5  
D2  
D1  
D0  
WDS  
WDW  
WDT  
WDS  
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. The bit is cleared automatically  
once the watchdog timer is reset. The WDS bit is write only. Reading it always will return a 0.  
WDW  
Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out value (WDT5-WDT0). This  
allows the user to strobe the watchdog stobe bit without disturbing the time-out value. Set this bit to 0 to allow bits  
5-0 to be written.  
WDT  
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents  
a multiplier of the 32 Hz count (31.25 ms). The range of time-out values is 31.25 ms (a setting of 1) to 2 seconds  
(setting of 3Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the  
WDW bit was cleared to 0 on a previous cycle.  
Interrupt  
0x1FFF6  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
WIE  
AIE  
PFIE  
ABE  
H/L  
P/L  
0
0
WIE  
AIE  
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer drives the INT pin  
as well as setting the WDF flag. When set to 0, the watchdog time-out only sets the WDF flag.  
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as setting the AF flag. When set  
to 0, the alarm match only affects the AF flag.  
PFIE  
Power-Fail Enable. When set to 1, a power failure drives the INT pin as well as setting the PF flag. When set to 0,  
the power failure only sets the PF flag.  
0
Reserved For Future Used  
H/L  
P/L  
High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open drain, active low.  
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approxi-  
mately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the Flags register is read.  
Alarm – Day  
0x1FFF5  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Alarm Date  
D0  
M
0
10s Alarm Date  
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.  
M
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes the  
match circuit to ignore the date value.  
Alarm – Hours  
0x1FFF4  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
M
0
10s Alarm Hours  
Alarm Hours  
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.  
M
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the  
match circuit to ignore the hours value.  
Alarm – Hours  
0x1FFF4  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
M
0
10s Alarm Hours  
Alarm Hours  
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.  
M
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the  
match circuit to ignore the hours value.  
Document #: 001-52039 Rev. **  
Page 19 of 23  
STK17TA8  
Register Map Detail (continued)  
Alarm – Seconds  
D4 D3  
0x1FFF2  
D7  
D6  
D5  
D2  
D1  
D0  
M
10s Alarm Seconds  
Alarm Seconds  
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.  
M
Match. Setting this bit to 0 causes the seconds’ value to be used in the alarm match. Setting this bit to 1 causes  
the match circuit to ignore the seconds value.  
0x1FFF1  
Real Time Clock – Centuries  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
10s Centuries  
Centuries  
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble  
contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.  
Flags  
0x1FFF0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
WDF  
AF  
PF  
OSCF  
0
CAL  
W
R
WDF  
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being  
reset by the user. It is cleared to 0 when the Flags register is read or on power-up.  
AF  
Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm registers  
with the match bits = 0. It is cleared when the Flags register is read or on power-up.  
PF  
Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold V  
to 0 when the Flags register is read or on power-up.  
. It is cleared  
SWITCH  
OSCF  
Oscillator Fail Flag. Set to 1 on power-up only if the oscillator is enabled and not running in the first 5ms of operation.  
This indicates that RTC backup power failed and clock value is no longer valid. The user must reset this bit to 0  
to clear this condition.  
CAL  
W
Calibration Mode. When set to 1, a 512Hz square wave is output on the INT pin. When set to 0, the INT pin resumes  
normal operation. This bit defaults to 0 (disabled) on power up.  
Write Enable. Setting the W bit to 1 freezes updates of the RTC registers and enables writes to RTC registers,  
Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents  
of the RTC registers to be transferred to the timekeeping counters if the time has been changed (a new base time  
is loaded). This bit defaults to 0 on power up.  
R
Read Time. Set R to 1 to captures the current time in holding registers so that clock updates are not seen during  
the reading process. Set R to 0 to enable the holding register to resume clock updates. This bit defaults to 0 on  
power up.  
Document #: 001-52039 Rev. **  
Page 20 of 23  
STK17TA8  
Ordering Information  
STK17TA8-R F 45 ITR  
Packing Option  
Blank=Tube  
TR=Tape and Reel  
Temperature Range  
Blank=Commercial (0 to +70 C)  
I= Industrial (-45 to +85 C)  
Access Time  
25=25 ns  
45=45 ns  
Lead Finish  
F=100% Sn (Matte Tin) RoHS Compliant  
Package  
R=Plastic 48-pin 300 mil SSOP (25 mil pitch)  
Ordering Codes  
Access Times  
(ns)  
Ordering Code  
Description  
Temperature  
STK17TA8-RF25  
STK17TA8-RF45  
3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300  
3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300  
25  
45  
25  
45  
25  
45  
25  
45  
Commercial  
Commercial  
Commercial  
Commercial  
Industrial  
STK17TA8-RF25TR 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300  
STK17TA8-RF45TR 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300  
STK17TA8-RF25I  
STK17TA8-RF45I  
3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300  
3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300  
Industrial  
STK17TA8-RF25ITR 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300  
STK17TA8-RF45ITR 3V 128Kx8 AutoStore nvSRAM+RTC SSOP48-300  
Industrial  
Industrial  
Document #: 001-52039 Rev. **  
Page 21 of 23  
STK17TA8  
Package Diagrams  
Figure 17. 48-Pin SSOP (51-85061)  
51-85061 *C  
Document #: 001-52039 Rev. **  
Page 22 of 23  
 
STK17TA8  
Document History Page  
Document Title: STK17TA8 128k X 8 AutoStore™ nvSRAM with Real Time Clock  
Document Number: 001-52039  
Orig. of  
Change  
Submission  
Date  
Rev. ECN No.  
**  
Description of Change  
2668660 GVCH/PYRS  
03/04/2009  
New Data Sheet  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 001-52039 Rev. **  
Revised March 02, 2009  
Page 23 of 23  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective  
holders.  

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