AT91SAM7L-STK Rev. A Starter Kit
....................................................................................................................
User Guide
6409A–ATARM–30-Jun-08
Table of Contents
Overview ....................................................................................................................1-1
1.1 Scope................................................................................................................................. 1-1
1.2 Deliverables ...................................................................................................................... 1-1
1.3 The AT91SAM7L-STK Rev. A Starter Board..................................................................... 1-1
Setting Up the AT91SAM7L-STK Rev. A Board.........................................................2-1
2.1 Electrostatic Warning......................................................................................................... 2-1
2.2 Requirements..................................................................................................................... 2-1
2.3 Layout ................................................................................................................................ 2-2
2.4 Powering Up the Board...................................................................................................... 2-2
2.5 Getting Started................................................................................................................... 2-2
2.6 AT91SAM7L-STK Rev. A Block Diagram .......................................................................... 2-3
Board Description.......................................................................................................3-1
3.1 AT91SAM7L64/128 Microcontroller................................................................................... 3-1
3.2 AT91SAM7L64/128 Block Diagram ................................................................................... 3-3
3.3 Memory.............................................................................................................................. 3-4
3.4 Clock Circuitry.................................................................................................................... 3-4
3.5 Reset Circuitry ................................................................................................................... 3-4
3.6 Shut Down controller.......................................................................................................... 3-4
3.7 Power Supply Circuitry....................................................................................................... 3-4
3.8 User Interface .................................................................................................................... 3-4
3.9 Debug Interface ................................................................................................................. 3-4
3.10 Expansion Slot................................................................................................................... 3-4
3.11 PIO Usage ......................................................................................................................... 3-5
Configuration..............................................................................................................4-1
4.1 Configuration Straps .......................................................................................................... 4-1
Schematics.................................................................................................................5-1
Errata..........................................................................................................................6-1
AT91SAM7L-STK Rev. A Starter Kit User Guide
i
6409A–ATARM–30-Jun-08
Table of Contents (Continued)
6.1 Q1 Footprint Incorrect........................................................................................................ 6-1
6.2 MAX3318 Control Pull-ups................................................................................................. 6-2
Revision History .........................................................................................................7-1
ii
AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08
Section 1
Overview
1.1
1.2
Scope
The AT91SAM7L-STK rev.A starter kit enables evaluation capabilities and code development of applica-
tions running on an AT91SAM7L64/128.
This guide focuses on the AT91SAM7L-STK rev.A board as an evaluation platform.
Deliverables
The AT91SAM7L-STK rev.A package contains the following items:
„ An AT91SAM7L-STK rev.A board
„ Two AAA batteries
1.3
The AT91SAM7L-STK Rev. A Starter Board
The board is equipped with an AT91SAM7L128 (128-lead LQFP package) together with the following:
„ One DBGU serial communication port
„ One ZIGBEE extension connector
„ One JTAG/ICE debug interface
„ Five user- input push buttons
„ One WakeUP input push button
„ One Reset Push Button
„ One Battery Socket for two AAA batteries
„ One 400 segments dot matrix LCD
AT91SAM7L-STK Rev. A Starter Kit User Guide
1-1
6409A–ATARM–30-Jun-08
Section 2
Setting Up the AT91SAM7L-STK Rev. A Board
2.1
2.2
Electrostatic Warning
The AT91SAM7L-STK rev.A starter board is shipped in a protective anti-static package. The board must
not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be
worn when handling the board. Avoid touching the component pins or any other metallic element.
Requirements
In order to set up the AT91SAM7L-STK rev.A starter board, the following items are needed:
„ The AT91SAM7L-STK rev.A starter board
„ Two AAA batteries
AT91SAM7L-STK Rev. A Starter Kit User Guide
2-1
6409A–ATARM–30-Jun-08
Setting Up the AT91SAM7L-STK Rev. A Board
2.3
Layout
Figure 2-1. AT91SAM7L-STK Rev. A Board Layout
2.4
2.5
Powering Up the Board
The AT91SAM7L-STK rev.A requires 3.0V (2.2V-3.6V) DC input. The power is supplied to the board via
2 AAA batteries or 3.0V VCC pads.
Getting Started
Please refer to the AT91SAM product pages on the Atmel web site, for the most up-to-date information
on getting started with the AT91SAM7L-STK rev.A.
2-2
AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08
Setting Up the AT91SAM7L-STK Rev. A Board
2.6
AT91SAM7L-STK Rev. A Block Diagram
Figure 2-2. AT91SAM7L-STK Block Diagram
SHEET 2
Interfaces
ꢀꢁꢂꢃ
PC[0..29]
PC[0..29]
Interfaces
Processor
SHEET 4
AD[0..3]
AD[0..3]
PA[0..25]
PA[0..25]
PB[0..23]
PB[0..23]
PC[0..29]
PC[0..29]
ERASE
Processor
LCD, KBD
SHEET 3
AD[0..3]
AD[0..3]
PA[0..25]
PA[0..25]
PB[0..23]
PB[0..23]
PC[0..29]
PC[0..29]
ERASE
LCD, KBD
AT91SAM7L-STK Rev. A Starter Kit User Guide
2-3
6409A–ATARM–30-Jun-08
Section 3
Board Description
3.1
AT91SAM7L64/128 Microcontroller
• Incorporates the ARM7TDMI® ARM® Thumb® Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
• Internal High-speed Flash
– 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane
– 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane
– Single Cycle Access at Up to 15 MHz in Worst Case Conditions
– 128-bit Read Access
– Page Programming Time: 4.6 ms, Including Page Auto Erase, Full Erase Time: 10 ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit
– Fast Flash Programming Interface for High Volume Production
• Enhanced Embedded Flash Controller (EEFC)
– Interface of the Flash Block with the 32-bit Internal Bus
– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface
• Internal High-speed SRAM, Single-cycle Access at Maximum Speed
– 6 kbytes
• 2 Kbytes Directly on Main Supply that Can Be Used as Backup SRAM
• 4 Kbytes in the Core
• Memory Controller (MC)
– Enhanced Embedded Flash Controller, Abort Status and Misalignment Detection
• Reset Controller (RSTC)
– Based on Brownout Reset and Low-power Factory-calibrated Brownout Detector
– Provides External Reset Signal Shaping and Reset Source Status
• Clock Generator (CKGR)
– Low-power 32 kHz RC Oscillator, 32 kHz On-chip Oscillator, 2 MHz Fast RC Oscillator and one PLL
• Supply Controller (SUPC)
– Minimizes Device Power Consumption
– Manages the Different Supplies On Chip
– Supports Multiple Wake-up Sources
• Power Management Controller (PMC)
– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode
– Three Programmable External Clock Signals
– Handles Fast Start Up
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
AT91SAM7L-STK Rev. A Starter Kit User Guide
3-1
6409A–ATARM–30-Jun-08
Board Description
• Debug Unit (DBGU)
– Two-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access
Prevention
• Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
• Windowed Watchdog (WDT)
– 12-bit Key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System
– Counter may be Stopped While the Processor is in Debug State or in Idle Mode
• Real-time Clock (RTC)
– Two Hundred Year Calendar with Alarm
– Runs Off the Internal RC or Crystal Oscillator
• Three Parallel Input/Output Controllers (PIOA, PIOB, PIOC)
– Eighty Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up resistor and Synchronous Output
• Eleven Peripheral DMA Controller (PDC) Channels
• One Segmented LCD Controller
– Display Capacity of Forty Segments and Ten Common Terminals
– Software Selectable LCD Output Voltage (Contrast)
• Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Manchester Encoder/Decoder
– Full Modem Line Support on USART1
• One Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• One Four-channel 16-bit PWM Controller (PWMC)
• One Two-wire Interface (TWI)
– Master, Multi-Master and Slave Mode Support, All Atmel® Two-wire EEPROMs and I2C compatible
Devices Supported
– General Call Supported in Slave Mode
• One 4-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os
• SAM-BA® Boot Assistant
– Default Boot Program
– Interface with SAM-BA Graphic User Interface
– In Application Programming Function (IAP)
• IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
• I/Os, including Four High-current Drive I/O lines, Up to 4 mA Each
• Power Supplies
– Embedded 1.8V Regulator, Drawing up to 60 mA for the Core with Programmable Output Voltage
– Single Supply 1.8V - 3.6V
– Zero-power Power-on Reset and Brownout Detector, Fully Programmable
• Fully Static Operation: Up to 36 MHz at 85°C
• Available in a 128-lead LQFP Green and a 144-ball LFBGA Green Package
3-2
AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08
Board Description
3.2
AT91SAM7L64/128 Block Diagram
Figure 3-1. AT91SAM7L64/128 Block Diagram
CAPP1
CAPM1
CAPP2
CAPM2
VDDINLCD
VDD3V6
TDI
TDO
TMS
TCK
Charge
Pump
ICE
ARM7TDMI
Processor
JTAG
SCAN
JTAGSEL
VDDLCD
VDDIO2
LCD
Voltage
Regulator
System Controller
2 MHz RCOSC
TST
FIQ
1.8 V
Voltage
VDDIO1
GND
AIC
IRQ0-IRQ1
Regulator
VDDOUT
PCK0-PCK2
CLKIN
VDDCORE
VDDIO2
Memory Controller
SRAM
PLLRC
PLL
PMC
Embedded
Address
Decoder
2 Kbytes( Back-up)
4 Kbytes (Core)
Flash
XIN
XOUT
OSC
Controller
Abort
Status
Misalignment
Detection
32k RCOSC
VDDCORE
ERASE
Flash
VDDIO1
BOD
POR
64/128 Kbytes
Supply
Controller
VDDIO1
NRST
Peripheral Bridge
ROM (12 Kbytes)
Peripheral Data
Controller
11 Channels
PGMRDY
PGMNVALID
PGMNOE
RSTB
Fast Flash
Programming
Interface
PGMCK
FWUP
PGMM0-PGMM3
PGMD0-PGMD15
PGMNCMD
VDDIO1
PGMEN0-PGMEN2
APB
SAM-BA
RTC
PIT
WDT
PWM0
PWM1
PWM2
PWM3
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
PWMC
PDC
PDC
DRXD
DTXD
DBGU
Timer Counter
PIOA (26 IOs)
PIOB (24 IOs)
PIOC (30 IOs)
TC0
TC1
TC2
TWI
TIOA1
TIOB1
TIOA2
TIOB2
PDC
TWD
TWCK
SEG00-SEG39
COM0-COM9
PDC
PDC
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
ADTRG
AD0
AD1
AD2
AD3
LCD Controller
SPI
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DSR1
DTR1
RI1
PDC
PDC
PDC
USART0
USART1
PDC
PDC
PDC
ADC
ADVREF
AT91SAM7L-STK Rev. A Starter Kit User Guide
3-3
6409A–ATARM–30-Jun-08
Board Description
3.3
Memory
„ 6 Kbytes of Internal single-cycle access High-speed SRAM
„ 64/128 Kbytes of Internal single-cycle access High-speed Flash
3.4
3.5
Clock Circuitry
„ 32.768 KHz standard crystal for the oscillator
Reset Circuitry
„ Internal reset controller with a bi-directional reset pin
„ External reset push button
3.6
3.7
Shut Down controller
„ Programmable shutdown and Wake-Up
„ Wake-up push button.
Power Supply Circuitry
„ For dynamic power consumption, the AT91SAM7L64/128 consumes a maximum of 30 mA on VCC at
full speed 36MHz
„ On board 2 AAA batteries or 3V DC input power pad directly supplied to VCC
3.8
3.9
User Interface
„ Five user- input push buttons, four direction buttons and one ok button
Debug Interface
„ 20-pin JTAG/ICE interface connector
„ One Serial interface (DBGU COM Port) via RS-232 DB9 male socket
3.10
Expansion Slot
„ One ZIGBEE expansion connector for Atmel AT86RF230 adaptor
„ All PIOC signals of the AT91SAM7L64/128 are routed to peripheral extension connector (J6). This
allows the developer to add external hardware components or boards.
3-4
AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08
Board Description
3.11
PIO Usage
Table 3-1. PIO Controller A
I/O Line
PA0
Peripheral A
Peripheral B
Peripheral Usage
Segment LCD PANEL
Powered by
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
COM0
COM1
COM2
COM3
COM4
COM5
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
PA1
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
AT91SAM7L-STK Rev. A Starter Kit User Guide
3-5
6409A–ATARM–30-Jun-08
Board Description
Table 3-2. PIO Controller B
I/O Line
PB0
Peripheral A
Peripheral B
Peripheral Usage
Segment LCD PANEL
Powered by
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
COM6
COM7
COM8
COM9
PB1
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
Segment LCD PANEL
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
NPCS3
NPCS2
NPCS1
RTS1
RTS0
DTR1
PWM0
PWM1
PWM2
PWM3
NPCS1
PCK0
PCK1
NPCS3
3-6
AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08
Board Description
Table 3-3. PIO Controller C
I/O Line
PC0
Peripheral A
CTS1
DCD1
DTR1
DSR1
RI1
Peripheral B
PWM2
TIOA2
TIOB2
TCLK1
TCLK2
NPCS2
PCK2
Peripheral Usage
Powered by
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
User’s Input Buttons
OK
PC1
User’s Input Buttons
User’s Input Buttons
User’s Input Buttons
User’s Input Buttons
ZIGBEE
UP
PC2
RIGHT
DOWN
LEFT
PC3
PC4
PC5
IRQ1
IRQ1
PC6
NPCS1
PWM0
PWM1
PWM2
TWD
ZIGBEE
NPCS1
FORCEOFF
RSIN
PC7
TIOA0
TIOB0
SCK0
MAX3318E
PC8
ZIGBEE
PC9
ZIGBEE
SLP_IR
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
NPCS3
TCLK0
NPCS3
PCK0
TWCK
RXD0
TXD0
RTS0
MAX3318E
FORCEON
INVALID
READY
ENABLE
DRXD
MAX3318E
ADTRG
PWM3
NPCS1
NPCS2
PWM0
PWM1
PWM2
PWM3
TIOA1
TIOB1
PCK1
MAX3318E
CTS0
DRXD
DTXD
NPCS0
MISO
MOSI
SPCK
NPCS3
PCK0
RXD1
TXD1
RTS0
VCC/VBAT MONITOR
MAX3318E
MAX3318E
DTXD
ZIGBEE
ZIGBEE
ZIGBEE
MISO
MOSI
SPCK
PCK2
FIQ
NPCS2
SCK1
RTS1
IRQ0
PWM0
PWM1
AT91SAM7L-STK Rev. A Starter Kit User Guide
3-7
6409A–ATARM–30-Jun-08
Section 4
Configuration
4.1
Configuration Straps
Table 4-1 gives details of configuration straps on the AT91SAM7L-STK rev. A starter board and their
default settings.
Table 4-1.
Designation
J6 pins 39-40
J8
Default Setting
Opened
Closed
Opened
2-3
Feature
Closed for internal flash erase(1)
VCC jumper(2)
SD1
Disables VDDIO2 to VDDLCD connection
SD2
Selects VCC or VDD3V6 to VDDLCD
SD3
Closed
2-3
Enables VDDOUT applying to VDDCORE
SD4
Selects VDDINLCD input
R20
IN
Enables the ICE NRST input
TP1
N.A
RX
TP2
N.A
TX
TP3
N.A
CLKIN
FWUP
ADREF
XOUT
NRSTB
VDDIO2
VDD3V6
VDDOUT
TP4
N.A
TP5
N.A
TP6
N.A
TP7
N.A
TP8
N.A
TP9
N.A
TP10
N.A
Notes: 1. This jumper is used to erase and reinitialize the internal flash content and some of the NVM bits.
2. This jumper is provided for power consumption measurement. By default, it is closed. To use this fea-
ture, the user has to open the strap and insert an ammeter.
AT91SAM7L-STK Rev. A Starter Kit User Guide
4-1
6409A–ATARM–30-Jun-08
5
4
3
2
1
SHEET 2
Interfaces
D
C
B
A
D
C
B
A
DBGU
PC[0..29]
PC[0..29]
Interfaces
Processor
SHEET 4
AD[0..3]
AD[0..3]
PA[0..25]
PB[0..23]
PC[0..29]
PA[0..25]
PB[0..23]
PC[0..29]
ERASE
Processor
SHEET 3
LCD, KBD
AD[0..3]
AD[0..3]
PA[0..25]
PB[0..23]
PC[0..29]
PA[0..25]
PB[0..23]
PC[0..29]
ERASE
LCD, KBD
INIT EDIT
REV MODIF.
A
PP
DES.
17MAR08 XXX XX-XXX-XX
DATE
VER.
REV.
DATE
S1HEET
4
SCALE
AT91SAM7L-STK
Top level
1/1
A
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
J1
PC[0..29]
J2
PC0
PC1
1
1
AAA
AAA
1
PC2
PC3
Pad
PC4
PC5
GND
PC6
J3
1
PC7
D
C
B
A
D
C
B
A
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
Pad
VCC
VCC
GND
U1
VCC
19
2
VCC
GND
C1+
C2
C1
100NF
100NF
R1
100K
R3
100K
18
4
5
R2
C1-
C2+
100K
SERIAL DEBUG PORT
C3
100NF
3
7
6
V+
V-
C2-
INVALID
READY
PC13
PC14
PC7
11
1
C5
100NF
C4
100NF
PC12
J4
R4
20
14
TP1
TESTPOINT
FORCEOFF
FORCEON
NOT POPULATED
1
GND
TX
6
2
7
3
8
DTXD
DRXD
PC17
PC16
GND
17
8
13
12
D1OUT
D2OUT
D1IN
D2IN
TP2
4
9
5
TESTPOINT
GND
RX
D09P24A4GX00
R5 0R
16
9
15
10
R1IN
R2IN
R1OUT
R2OUT
MAX3318E
GND
GND
ZIGBEE INTERFACE
R6 0R
VCC
Note: Pin 1 on Zigbee board RZ502 matches pin 2 on this connector
J5
1
3
2
VCC
R7
10K
4
5
6
Only for AT86RF230Rev.A connexion
not required for Rev.B on
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
U2
D
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
U3
3
5
VCC
VCC
PC19
1
6
4
2
2
4
CP
C
Q
VCC
VCC
PC8
PC21
NC7SZ125P5X
VCC
GND
GND
SLP_TR
MOSI
NPSC1
RSTN
MISO
SPCK
PC9
PC20
PC6
NC7SZ175P6X
VCC
VCC
C7
IRQ1
PC5
GND
C6
NOT POPULATED
NOT POPULATED
GND
GND
GND
INIT EDIT
REV MODIF.
A
PP
DES.
17MAR08 XXX XX-XXX-XX
DATE
VER.
REV.
DATE
S2HEET
4
SCALE
AT91SAM7L-STK
Interfaces
1/1
A
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
BP1
PC1 UP
PC0 OK
PC[0..29]
PB[0..23]
PA[0..25]
3-1437565-0
BP3
BP2
BP4
PC2 RIGHT
D
C
B
A
D
C
B
A
3-1437565-0
3-1437565-0
BP5
3-1437565-0
PC4 LEFT
PA0
PA1
COM0
COM1
COM2
COM3
COM4
COM5
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
PB0
PB1
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
COM6
PC0
OK
UP
RIGHT
DOWN
LEFT
PC3 DOWN
PC1
PA2
PB2
PC2
PA3
PB3
PC3
3-1437565-0
PA4
PB4
PC4
PA5
PB5
PC5
PA6
PB6
PC6
PA7
PB7
PC7
VCC
PA8
PB8
PC8
PA9
PB9
PC9
GND
GND
GND
PA10
PA11
PA12
PA13
PA14
PA15
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
NPCS3
NPCS2
NPCS1
RTS1
VCC/VBAT MONITOR
PA16 SEG10
PA17 SEG11
PA18 SEG12
PA19 SEG13
PA20 SEG14
PA21 SEG15
PA22 SEG16
PA23 SEG17
PA24 SEG18
PA25 SEG19
RTS0
DTR1
VCC
PWM0
PWM1
PWM2
COM7
PWM3
Q1
FDV304P
COM8
COM9
NPSC1/PCK1
PCK0/NPCS3
PC15
1
AD3
AD2
AD1
AD0
AD[0..3]
R8
AD[0..3]
10K
AD3
R9
10K
VCC
VCC
GND
J6
GND
R10
NOT POPULATED
R11
NOT POPULATED
LCD1
PC1 DCD1/TIOA2_WKUP1
PC0
CTS1/PWM2_WKUP0
DTR1/TIOB2_WKUP2
RI1/TCLK2_WKUP4
NPCS1/PCK2_WKUP6
PWM1/TIOB0
1
3
2
LCD_GS08001AA
PC3 DSR1/TCLK1_WKUP3
PC5 IRQ1/NPCS2_WKUP5
PC7 PWM0/TIOA0
PC2
4
PC4
5
6
8
PC6
7
9
PC9 PWM2/SCK0
PC8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PC11 TWCK/TCLK0_WKUP7
PC13 TXD0/PCK0_WKUP9
PC15 CTS0/PWM3_WKUP11
PC17 /DTXD/MPCS2
PC10
PC12
PC14
PC16
PC18
PC20
PC22
PC24
PC26
PC28
TWD/NPCS3
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
RXD0/NPCS3_WKUP8
RTS0/ADTRG_WKUP10
DRXD/NPCS1
PC19 MISO/PWM1
NPCS0/PWM0
PC21 SPCK/PWM3
MOSI/PWM2
PC23 PCK0/TIOB1
MPCS3/TIOA1
PC25 TXD1/PCK2
RXD1/PCK1
PC27 NPCS2/IRQ0_WKUP13
PC29 RTS1/PWM1_WKUP15
RTS0/FIQ_WKUP12
SCK1/PWM0_WKUP14
AD1
AD3
AD0
AD2
ERASE
VCC
ERASE
GND
JS1
GND
INIT EDIT
REV MODIF.
A
PP
DES.
17MAR08 XXX XX-XXX-XX
DATE
VER.
REV.
DATE
S3HEET
4
SCALE
AT91SAM7L-STK
LCD, KBD
1/1
A
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
PC[0..29]
PA[0..25]
PB[0..23]
FORCE WAKE-UP
TP3
TESTPOINT
VCC
U4
AT91SAM7L128-AU
PB0
PB1
PA0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
57
58
59
60
61
63
64
65
66
67
3
D
C
B
A
R12
100K
D
C
B
A
PB0_SEG20
PA0_COM0
PA1_COM1
PA2_COM2
PA3_COM3
PA4_COM4
PA5_COM5
PA6_SEG0
PA1
4
PB1_SEG21
PB2
PA2
5
R13
100K
PB2_SEG22
PB3
PA3
6
PB3_SEG23
PB4
PA4
7
PB4_SEG24
PB5
PA5
8
PB5_SEG25
PB6
PA6
9
PB6_SEG26
PB7
PA7
10
11
12
13
16
17
18
19
20
21
22
23
24
25
26
27
29
30
31
FWKUP
PB7_SEG27
PA7_SEG1
PB8
PA8
PB8_SEG28
PA8_SEG2
PA9_SEG3
BP6
3-1437565-0
PB9
PA9
GND
PB9_SEG29
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
TP4
TESTPOINT
PB10_SEG30
PA10_SEG4
PA11_SEG5
PA12_SEG6
PA13_SEG7
PA14_SEG8
PA15_SEG9
PA16_SEG10
PA17_SEG11
PA18_SEG12
PA19_SEG13
PA20_SEG14
PA21_SEG15
PA22_SEG16
PA23_SEG17
PA24_SEG18
PA25_SEG19
PB11_SEG31
PB12/NPCS3_SEG32
PB13/NPCS2_SEG33
PB14/NPCS1_SEG34
PB15/RTS1_SEG35
PB16/RTS0_SEG36
PB17/DTR1_SEG37
PB18/PWM0_SEG38
PB19/PWM1_SEG39
PB20/PWM2_COM6
PB21/PWM3_COM7
PB22/NPSC1/PCK1_COM8
PB23/PCK0/NPCS3_COM9
C8
NOT POPULATED
VDDOUT
GND
ICE INTERFACE
R14
180R
VCC
VCC
TP5
125
118
CLKIN
R19
NOT POPULATED
R15
100K
R16
100K
R17
100K
R18
100K
AT91SAM7L-LQFP128
TESTPOINT
C9
100NF
J7
FWUP
2
1
4
6
3
69
ADVREF
JTAG_TDI
JTAG_TMS
JTAG_TCK
5
116
82
TDI
8
7
TMS
TCK
TDO
NRST
AD3
AD2
AD1
AD0
10
12
14
16
18
20
9
81
70
71
72
73
AD3
AD2
AD1
AD0
11
13
15
17
19
117
79
JTAG_TDO
JTAG_RST
GND
R20 0R
R21
NOT POPULATED
83
121
122
VCC
AD[0..3]
JTAGSEL
PLLRC
R22
10K
C10
22NF
C11
GND
PLLRCGND
R23
CM415-32.768KDZFB-F
128
127
1
GND
XOUT
XIN/PGMCK
TST
NOT POPULATED
2.2NF
32.768 kHz
XC1
126
NRSTB
VCC
1
2
TP6
TESTPOINT
TP7
TESTPOINT
C12
18PF
C13
18PF
C14
10NF
123
RESET
GNDPLL
GND
NRSTB
BP7
3-1437565-0
ERASE
ERASE
C29
10µF
6V3
C15
C16
C30
R24
10R
220NF 220NF
TP8
100NF
C33
GND
TESTPOINT
TP9
TESTPOINT
10µF
6V3
SD1
GND
VCC
1
C34
10µF
6V3
SOLDER DROP 2 pins open
SAM7L Current measurement
2
SD2
SOLDER DROP 3 pins
JS2
J8
VCC
TP10
SD3
12
1
2
TESTPOINT
SOLDER DROP 3 pins
SD4
3
SOLDER DROP 2 pins closed
INIT EDIT
REV MODIF.
A
PP
DES.
17MAR08 XXX XX-XXX-XX
DATE
VER.
REV.
DATE
S4HEET
4
SCALE
AT91SAM7L-STK
Processor
1/1
GND
A
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
Section 6
Errata
6.1
Q1 Footprint Incorrect
Transistor Q1 is incorrectly connected. The schematic is right but the PCB connections of pins S and D
are swapped => the protection diode is polarized forward (permanent current flow across the bridge) and
the MOS is not operating properly (non accurate battery level measurement).
Problem Fix/Workaround
Remove Q1 in order to avoid the parasitic 150 µA battery drain. If battery measurement is really manda-
tory for some applications, Q1 has to be removed and soldered bottom up, taking care to apply the
correct polarity. Additionally, a 100 KΩ pull-up resistor is needed across gate and source.
6.2
MAX3318 Control Pull-ups
The default configuration of the MAX3318 is ON. This leads to extra power consumption discharging the
batteries when the AT91SAM7L128 enters OFF mode (or does not even drive PC7 and PC12 to put the
MAX3318 in OFF mode).
Problem Fix/Workaround
Remove R1, R2 and R3 and add a 10M Ω pull-down resistor on PC7. This allows to Force OFF the
MAX3318 when the AT91SAM7L128 enters OFF mode and to turn it on when the AT91SAM7L128
wakes up. The user can save power consumption by driving PC7 connected to the FORCEOFF pin of
the MAX3318.
AT91SAM7L-STK Rev. A Starter Kit User Guide
6-1
6409A–ATARM–30-Jun-08
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6409A–ATARM–30-Jun-08
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