Atmel AT89C5132 User Manual

Features  
Programmable Audio Output for Interfacing with Common Audio DAC  
– PCM Format Compatible  
– I2S Format Compatible  
8-bit MCU C51 Core-based (FMAX = 20 MHz)  
2304 Bytes of Internal RAM  
64K Bytes of Code Memory  
– AT89C5132: Flash (100K Write/Erase Cycles)  
4K Bytes of Boot Flash Memory (AT89C5132)  
– ISP: Download from USB (standard) or UART (option)  
USB Rev 1.1 Device Controller  
USB  
– “Full Speed” Data Transmission  
Built-in PLL  
Microcontroller  
with 64K Bytes  
Flash Memory  
MultiMedia Card® Interface Compatibility  
Atmel DataFlash® SPI Interface Compatibility  
IDE/ATAPI Interface  
2 Channels 10-bit ADC, 8 kHz (8 True Bits)  
– Battery Voltage Monitoring  
– Voice Recording Controlled by Software  
Up to 44 Bits of General-purpose I/Os  
– 4-bit Interrupt Keyboard Port for a 4 x n Matrix  
– SmartMedia® Software Interface  
Two Standard 16-bit Timers/Counters  
Hardware Watchdog Timer  
AT89C5132  
Standard Full Duplex UART with Baud Rate Generator  
Two Wire Master and Slave Modes Controller  
SPI Master and Slave Modes Controller  
Power Management  
– Power-on Reset  
– Software Programmable MCU Clock  
– Idle Mode, Power-down Mode  
Operating Conditions  
– 3V, 10%, 25 mA Typical Operating at 25°C  
– Temperature Range: -40°C to +85°C  
Packages  
– TQFP80, PLCC84 (Development Board Only)  
– Dice  
1. Description  
The AT89C5132 is a mass storage device controlling data exchange between various  
Flash modules, HDD and CD-ROM.  
The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Program-  
ming through an embedded 4K Bytes of Boot Flash Memory.  
The AT89C5132 include 2304 Bytes of RAM memory.  
The AT89C5132 provides all the necessary features for man-machine interface  
including, timers, keyboard port, serial or parallel interface (USB, SPI, IDE), ADC  
input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMe-  
dia, MultiMedia, DataFlash cards).  
2. Typical Applications  
Flash Recorder/Writer  
PDA, Camera, Mobile Phone  
PC Add-on  
4173ES–USB–09/07  
AT89C5132  
4. Pin Description  
Figure 4-1. AT89C5132 80-pin TQFP Package  
ALE  
ISP  
1
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
P4.5  
2
P4.4  
P1.0/KIN0  
P1.1/KIN1  
P1.2/KIN2  
P1.3/KIN3  
P1.4  
3
P2.2/A10  
P2.3/A11  
P2.4/A12  
P2.5/A13  
P2.6/A14  
P2.7/A15  
VSS  
4
5
6
7
P1.5  
8
P1.6/SCL  
P1.7/SDA  
VDD  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
VDD  
TQFP80  
MCLK  
MDAT  
MCMD  
RST  
PVDD  
FILT  
PVSS  
VSS  
SCLK  
X2  
DSEL  
X1  
DCLK  
DOUT  
VSS  
TST  
UVDD  
UVSS  
VDD  
3
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Figure 4-2. AT89C5132 84-pin PLCC (1)  
ALE 12  
ISP 13  
74 NC  
73 P4.5  
P1.0/KIN0 14  
P1.1/KIN1 15  
P1.2/KIN2 16  
P1.3/KIN3 17  
P1.4 18  
72 P4.4  
71 P2.2/A10  
70 P2.3/A11  
69 P2.4/A12  
68 P2.5/A13  
67 P2.6/A14  
66 P2.7/A15  
65 VSS  
P1.5 19  
P1.6/SCL 20  
P1.7/SDA 21  
VDD 22  
PLCC84  
64 VDD  
PAVDD 23  
FILT 24  
63 MCLK  
62 MDAT  
61 MCMD  
60 RST  
PAVSS 25  
VSS 26  
X2 27  
59 SCLK  
58 DSEL  
57 DCLK  
56 DOUT  
55 VSS  
NC 28  
X1 29  
TST 30  
UVDD 31  
UVSS 32  
54 VDD  
Note:  
1. For development board only.  
4.1  
Signals  
All the AT89C5132 signals are detailed by functionality in Table 1 to Table 14.  
Table 1. Ports Signal Description  
Signal  
Alternate  
Name  
Type  
Description  
Function  
Port 0  
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written  
to them float and can be used as high impedance inputs. To avoid any parasitic  
P0.7:0  
I/O  
AD7:0  
current consumption, floating P0 inputs must be polarized to VDD or VSS  
.
KIN3:0  
SCL  
SDA  
Port 1  
P1.7:0  
I/O  
P1 is an 8-bit bidirectional I/O port with internal pull-ups.  
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Signal  
Name  
Alternate  
Function  
Type  
Description  
Port 2  
P2.7:0  
I/O  
A15:8  
P2 is an 8-bit bidirectional I/O port with internal pull-ups.  
RXD  
TXD  
INT0  
INT1  
T0  
Port 3  
P3.7:0  
I/O  
P3 is an 8-bit bidirectional I/O port with internal pull-ups.  
T1  
WR  
RD  
MISO  
MOSI  
SCK  
SS  
Port 4  
P4.7:0  
P5.3:0  
I/O  
I/O  
P4 is an 8-bit bidirectional I/O port with internal pull-ups.  
Port 5  
-
P5 is a 4-bit bidirectional I/O port with internal pull-ups.  
Table 2. Clock Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
Input to the on-chip inverting oscillator amplifier  
To use the internal oscillator, a crystal/resonator circuit is connected to this pin.  
If an external oscillator is used, its output is connected to this pin. X1 is the  
clock source for internal timing.  
X1  
I
-
Output of the on-chip inverting oscillator amplifier  
X2  
O
I
To use the internal oscillator, a crystal/resonator circuit is connected to this pin.  
If an external oscillator is used, leave X2 unconnected.  
-
-
PLL Low Pass Filter input  
FILT receives the RC network of the PLL low pass filter.  
FILT  
Table 3. Timer 0 and Timer 1 Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
Timer 0 Gate Input  
INT0 serves as external run control for timer 0, when selected by GATE0 bit in  
TCON register.  
INT0  
I
P3.2  
External Interrupt 0  
INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0  
is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set by a low level  
on INT0.  
Timer 1 Gate Input  
INT1 serves as external run control for timer 1, when selected by GATE1 bit in  
TCON register.  
INT1  
I
P3.3  
External Interrupt 1  
INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1  
is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level  
on INT1.  
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Signal  
Name  
Alternate  
Function  
Type  
Description  
Timer 0 External Clock Input  
T0  
T1  
I
When timer 0 operates as a counter, a falling edge on the T0 pin increments  
the count.  
P3.4  
P3.5  
Timer 1 External Clock Input  
When timer 1 operates as a counter, a falling edge on the T1 pin increments  
the count.  
I
Table 4. Audio Interface Signal Description  
Signal  
Alternate  
Function  
Name  
DCLK  
DOUT  
Type  
O
Description  
DAC Data Bit Clock  
DAC Audio Data  
-
-
O
DAC Channel Select Signal  
DSEL is the sample rate clock output.  
DSEL  
SCLK  
O
O
-
-
DAC System Clock  
SCLK is the oversampling clock synchronized to the digital audio data (DOUT)  
and the channel selection signal (DSEL).  
Table 5. USB Controller Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
I/O  
Description  
USB Positive Data Upstream Port  
This pin requires an external 1.5 KΩ pull-up to VDD for full speed operation.  
D+  
-
-
D-  
I/O  
USB Negative Data Upstream Port  
Table 6. MutiMediaCard Interface Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
MMC Clock output  
Data or command clock transfer.  
MCLK  
O
-
MMC Command line  
Bidirectional command channel used for card initialization and data transfer  
commands. To avoid any parasitic current consumption, unused MCMD input  
MCMD  
MDAT  
I/O  
I/O  
-
must be polarized to VDD or VSS  
.
MMC Data line  
Bidirectional data channel. To avoid any parasitic current consumption, unused  
MDAT input must be polarized to VDD or VSS  
-
.
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Table 7. UART Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
Receive Serial Data  
RXD  
I/O  
RXD sends and receives data in serial I/O mode 0 and receives data in serial  
I/O modes 1, 2 and 3.  
P3.0  
P3.1  
Transmit Serial Data  
TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O  
modes 1, 2 and 3.  
TXD  
O
Table 8. SPI Controller Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
SPI Master Input Slave Output Data Line  
MISO  
I/O  
When in master mode, MISO receives data from the slave peripheral. When in  
slave mode, MISO outputs data to the master controller.  
P4.0  
P4.1  
SPI Master Output Slave Input Data Line  
When in master mode, MOSI outputs data to the slave peripheral. When in  
slave mode, MOSI receives data from the master controller.  
MOSI  
I/O  
SPI Clock Line  
SCK  
SS  
I/O  
I
When in master mode, SCK outputs clock to the slave peripheral. When in  
slave mode, SCK receives clock from the master controller.  
P4.2  
P4.3  
SPI Slave Select Line  
When in controlled slave mode, SS enables the slave mode.  
Table 9. TWI Controller Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
TWI Serial Clock  
When TWI controller is in master mode, SCL outputs the serial clock to the  
slave peripherals. When TWI controller is in slave mode, SCL receives clock  
from the master controller.  
SCL  
I/O  
P1.6  
P1.7  
TWI Serial Data  
SDA is the bidirectional Two Wire data line.  
SDA  
I/O  
Table 10. A/D Converter Signal Description  
Signal  
Alternate  
Function  
Name  
AIN1:0  
AREFP  
Type  
Description  
I
I
A/D Converter Analog Inputs  
Analog Positive Voltage Reference Input  
-
-
Analog Negative Voltage Reference Input  
This pin is internally connected to AVSS.  
AREFN  
I
-
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Table 11. Keypad Interface Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
Keypad Input Lines  
KIN3:0  
I
Holding one of these pins high or low for 24 oscillator periods triggers a  
keypad interrupt.  
P1.3:0  
Table 12. External Access Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
Address Lines  
A15:8  
I/O  
Upper address lines for the external bus.  
Multiplexed higher address and data lines for the IDE interface.  
P2.7:0  
P0.7:0  
Address/Data Lines  
Multiplexed lower address and data lines for the external memory or the IDE  
interface.  
AD7:0  
ALE  
I/O  
O
Address Latch Enable Output  
ALE signals the start of an external bus cycle and indicates that valid address  
information is available on lines A7:0. An external latch is used to demultiplex  
the address from address/data bus.  
-
-
ISP Enable Input  
ISP  
I/O  
This signal must be held to GND through a pull-down resistor at the falling  
reset to force execution of the internal bootloader.  
Read Signal  
RD  
O
O
P3.7  
P3.6  
Read signal asserted during external data memory read operation.  
Write Signal  
WR  
Write signal asserted during external data memory write operation.  
Table 13. System Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
Reset Input  
Holding this pin high for 64 oscillator periods while the oscillator is running  
resets the device. The Port pins are driven to their reset conditions when a  
voltage lower than VIL is applied, whether or not the oscillator is running.  
This pin has an internal pull-down resistor which allows the device to be reset  
RST  
I
-
by connecting a capacitor between this pin and VDD  
.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the  
chip to normal operation.  
Test Input  
TST  
I
-
Test mode entry signal. This pin must be set to VDD  
.
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AT89C5132  
Table 14. Power Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
Digital Supply Voltage  
Connect these pins to +3V supply voltage.  
VDD  
PWR  
-
-
-
-
-
-
-
-
Circuit Ground  
Connect these pins to ground.  
VSS  
GND  
PWR  
GND  
PWR  
GND  
PWR  
GND  
Analog Supply Voltage  
Connect this pin to +3V supply voltage.  
AVDD  
AVSS  
PVDD  
PVSS  
UVDD  
UVSS  
Analog Ground  
Connect this pin to ground.  
PLL Supply voltage  
Connect this pin to +3V supply voltage.  
PLL Circuit Ground  
Connect this pin to ground.  
USB Supply Voltage  
Connect this pin to +3V supply voltage.  
USB Ground  
Connect this pin to ground.  
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4173ES–USB–09/07  
4.2  
Internal Pin Structure  
Table 15. Detailed Internal Pin Structure  
Circuit(1)  
Type  
Pins  
VDD  
Input  
TST  
VDD  
Watchdog Output  
P
Input/Output  
RST  
VSS  
VDD  
VDD  
VDD  
2 osc  
periods  
P1(2)  
P2(3)  
P3  
Latch Output  
P1  
P2  
P3  
Input/Output  
P4  
N
P53:0  
VSS  
VDD  
P0  
P
MCMD  
MDAT  
Input/Output  
ISP  
N
PSEN  
VSS  
VDD  
ALE  
SCLK  
DCLK  
P
Output  
DOUT  
DSEL  
MCLK  
N
VSS  
D+  
D-  
Input/Output  
D+  
D-  
Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the  
Section “DC Characteristics”, page 183.  
2. When the Two Wire controller is enabled, P1, P2, and P3 transistors are disabled allowing  
pseudo open-drain structure.  
3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8).  
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AT89C5132  
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AT89C5132  
5. Address Spaces  
The AT8xC5132 derivatives implement four different address spaces:  
Program/Code Memory  
Boot Memory  
Data Memory  
Special Function Registers (SFRs)  
5.0.1  
Code Memory  
The AT89C5132 implements 64K Bytes of on-chip program/code memory in Flash technology.  
The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and pro-  
gramming. Thanks to the internal charge pump, the high voltage needed for programming or  
erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the AT89C5132  
can be programmed using only one voltage and allows in application software programming  
commonly known as IAP. Hardware programming mode is also available using specific pro-  
gramming tools.  
5.0.2  
5.0.3  
Boot Memory  
Data Memory  
The AT89C5132 implements 4K Bytes of on-chip boot memory provided in Flash technology.  
This boot memory is delivered programmed with a standard bootloader software allowing in sys-  
tem programming commonly known as ISP. It also contains some Application Programming  
Interfaces routines commonly known as API allowing user to develop his own bootloader.  
The AT89C5132 derivatives implement 2304 bytes of on-chip data RAM. This memory is divided  
in two separate areas:  
256 bytes of on-chip RAM memory (standard C51 memory).  
2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX instructions).  
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Peripherals  
The AT8xC5132 peripherals are briefly described in the following sections. For further  
details on how to interface (hardware and software) to these peripherals, please refer to  
the AT8xC5132 complete datasheet.  
Clock Generator System The AT8xC5132 internal clocks are extracted from an on-chip PLL fed by an on-chip  
oscillator. Four clocks are generated respectively for the C51 core, the audio interface,  
and the other peripherals. The C51 and peripheral clocks are derived from the oscillator  
clock. The audio interface sample rates are also obtained by dividing the PLL output  
clock.  
Ports  
The AT8xC5132 implement five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition  
to performing general-purpose I/Os, some ports are capable of external data memory  
operations; others allow for alternate functions. All I/O Ports are bidirectional. Each Port  
contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers  
and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4  
pins serve for both general-purpose I/Os and alternate functions.  
Timers/Counters  
The AT8xC5132 implement the two general-purpose, 16-bit Timers/Counters of a stan-  
dard C51. They are identified as Timer 0, Timer 1, and can independently be configured  
each to operate in a variety of modes as a Timer or as an event Counter. When operat-  
ing as a Timer, a Timer/Counter runs for a programmed length of time, then issues an  
interrupt request. When operating as a Counter, a Timer/Counter counts negative transi-  
tions on an external pin. After a preset number of counts, the Counter issues an interrupt  
request.  
Watchdog Timer  
The AT8xC5132 implement a hardware Watchdog Timer that automatically resets the  
chip if it is allowed to time out. The WDT provides a means of recovering from routines  
that do not complete successfully due to software or hardware malfunctions.  
Audio Output Interface  
The AT8xC5132 implements an audio output interface allowing the decoded audio bit-  
stream to be output in various formats. They are compatible with right and left  
justification PCM and I2S formats and the on-chip PLL allows connection of almost all  
commercial audio DAC families available on the market.  
Universal Serial Bus  
Interface  
The AT8xC5132 implements a full-speed Universal Serial Bus Interface. The USB inter-  
face can be used for the following purposes:  
Download of files by supporting the USB mass storage class.  
In-System Programming by supporting the USB firmware upgrade class.  
MultiMedia Card  
Interface  
The AT8xC5132 implements a MultiMedia Card (MMC) interface compliant to the V2.2  
specification in MultiMedia Card mode. The MMC allows storage of files in removable  
Flash memory cards that can be easily plugged or removed from the application. It can  
also be used for In-System Programming.  
IDE/ATAPI Interface  
The AT8xC5132 provide an IDE/ATAPI interface allowing connection of devices such as  
CD-ROM reader, CompactFlashcards, Hard Disk Drive, etc. It consists of a 16-bit bidi-  
rectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass  
storage interface but could be used for In-System Programming using CD-ROM.  
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AT89C5132  
Serial I/O Interface  
The AT89C5132 implements a serial port with its own baud rate generator providing one  
single synchronous communication mode and three full-duplex Universal Asynchronous  
Receiver Transmitter (UART) communication modes. It is provided for the following  
purposes:  
In System Programming.  
Remote control of the AT89C5132 by a host.  
Serial Peripheral  
Interface  
The AT89C5132 implements a Serial Peripheral Interface (SPI) supporting master and  
slave modes. It is provided for the following purposes:  
Remote control of the AT89C5132 by a host.  
In System Programming.  
Two-wire Controller  
A/D Controller  
The AT89C5132 implements a 2-wire controller supporting the four standard master and  
slave modes with multimaster capability. It is provided for the following purposes:  
Connection of slave devices like LCD controller, audio DAC…  
Remote control of the AT89C5132 by a host.  
In System Programming.  
The AT89C5132 implements a 2-channel 10-bit (8 true bits) analog to digital converter  
(ADC). It is provided for the following purposes:  
Battery monitoring.  
Voice recording.  
Corded remote control.  
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6. Electrical Characteristics  
6.1  
Absolute Maximum Ratings  
*NOTICE:  
Stressing the device beyond the “Absolute Maxi-  
mum Ratings” may cause permanent damage.  
These are stress ratings only. Operation beyond  
the “operating conditions” is not recommended  
and extended exposure beyond the “Operating  
Conditions” may affect device reliability.  
Storage Temperature..................................... -65°C to +150°C  
Voltage on any other Pin to VSS .....................................-0.3to+4.0V  
IOL per I/O Pin ................................................................. 5 mA  
Power Dissipation............................................................. 1 W  
Ambient Temperature Under Bias.................... -40°C to +85°C  
VDD ....................................................................................... 2.7V to 3.3V  
6.2  
DC Characteristics  
6.2.1  
Digital Logic  
Table 1. Digital DC Characteristics  
VDD = 2.7 to 3.3V , TA = -40 to +85°C  
Symbol  
Parameter  
Min  
-0.5  
Typ(1)  
Max  
0.2·VDD - 0.1  
VDD  
Units  
Test Conditions  
VIL  
Input Low Voltage  
V
V
V
VIH1  
Input High Voltage (except RST, X1)  
Input High Voltage (RST, X1)  
0.2·VDD + 1.1  
(2)  
VIH2  
0.7·VDD  
VDD + 0.5  
Output Low Voltage  
VOL1  
(except P0, ALE, MCMD, MDAT, MCLK,  
SCLK, DCLK, DSEL, DOUT)  
0.45  
0.45  
V
IOL= 1.6 mA  
Output Low Voltage  
(P0, ALE, MCMD, MDAT, MCLK, SCLK,  
DCLK, DSEL, DOUT)  
VOL2  
V
V
IOL= 3.2 mA  
Output High Voltage  
(P1, P2, P3, P4 and P5)  
VOH1  
VDD - 0.7  
VDD - 0.7  
IOH= -30 μA  
Output High Voltage  
(P0, P2 address mode, ALE, MCMD,  
MDAT, MCLK, SCLK, DCLK, DSEL,  
DOUT, D+, D-)  
VOH2  
V
IOH= -3.2 mA  
Vin = 0.45 V  
Logical 0 Input Current (P1, P2, P3, P4  
and P5)  
IIL  
-50  
μA  
14  
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AT89C5132  
Table 1. Digital DC Characteristics  
DD = 2.7 to 3.3V , TA = -40 to +85°C  
V
Symbol  
Parameter  
Min  
Typ(1)  
Max  
Units  
Test Conditions  
Input Leakage Current (P0, ALE, MCMD,  
MDAT, MCLK, SCLK, DCLK, DSEL,  
DOUT)  
ILI  
10  
μA  
0.45< VIN< VDD  
Logical 1 to 0 Transition Current  
(P1, P2, P3, P4 and P5)  
ITL  
-650  
200  
μA  
Vin = 2.0 V  
RRST  
CIO  
Pull-Down Resistor  
Pin Capacitance  
50  
90  
10  
kΩ  
pF  
V
TA= 25°C  
VRET  
VDD Data Retention Limit  
1.8  
VDD < 3.3 V  
X1 / X2 mode  
6.5 / 10.5  
8 / 13.5  
12 MHz  
16 MHz  
20 MHz  
(3)  
IDD  
Operating Current  
mA  
9.5 / 17  
VDD < 3.3 V  
X1 / X2 mode  
5.3 / 8.1  
6.4 / 10.3  
7.5 / 13  
12 MHz  
16 MHz  
20 MHz  
(3)  
IDL  
Idle Mode Current  
mA  
IPD  
Power-Down Mode Current  
20  
500  
μA  
VRET < VDD < 3.3 V  
Notes: 1. Typical values are obtained using VDD= 3 V and TA= 25°C. They are not tested and there is no  
guarantee on these values.  
2. Flash retention is guaranteed with the same formula for VDD min down to 0V.  
3. See Table 154 for typical consumption in player mode.  
6.2.2  
IDD, IDL and IPD Test Conditions  
Figure 6-1.  
I
DD Test Condition, Active Mode  
VDD  
VDD  
RST  
VDD  
PVDD  
UVDD  
AVDD  
IDD  
(NC)  
Clock Signal  
X2  
X1  
VDD  
P0  
VSS  
PVSS  
UVSS  
AVSS  
TST  
VSS  
All other pins are unconnected  
15  
4173ES–USB–09/07  
Figure 6-2. IDL Test Condition, Idle Mode  
VDD  
VDD  
PVDD  
UVDD  
AVDD  
IDL  
RST  
VSS  
(NC)  
Clock Signal  
X2  
X1  
VDD  
P0  
VSS  
PVSS  
UVSS  
AVSS  
TST  
VSS  
All other pins are unconnected  
Figure 6-3. IPD Test Condition, Power-Down Mode  
VDD  
VDD  
PVDD  
UVDD  
AVDD  
IPD  
RST  
VSS  
(NC)  
VDD  
X2  
X1  
P0  
MCMD  
MDAT  
TST  
VSS  
PVSS  
UVSS  
AVSS  
VSS  
All other pins are unconnected  
6.2.3  
A-to-D Converter  
Table 2. A-to-D Converter DC Characteristics  
VDD = 2.7 to 3.3V , TA = -40 to +85°C  
Symbol  
Parameter  
Min  
Typ  
Max  
Units Test Conditions  
AVDD  
Analog Supply Voltage  
2.7  
3.3  
V
AVDD = 3.3V  
μA  
AIDD  
Analog Operating Supply Current  
600  
AIN1:0 = 0 to AVDD  
AVDD = 3.3V  
μA  
AIPD  
AVIN  
Analog Standby Current  
Analog Input Voltage  
2
ADEN = 0 or PD = 1  
AVSS  
AVDD  
V
Reference Voltage  
AREFN  
AREFP  
AVREF  
AVSS  
2.4  
V
V
AVDD  
30  
RREF  
CIA  
AREF Input Resistance  
Analog Input capacitance  
10  
kΩ  
TA = 25°C  
10  
pF  
TA = 25°C  
16  
AT89C5132  
4173ES–USB–09/07  
AT89C5132  
6.2.4  
Oscillator and Crystal  
6.2.4.1  
Schematic  
Figure 6-4. Crystal Connection  
X1  
X2  
C1  
C2  
Q
VSS  
Note:  
For operation with most standard crystals, no external components are needed on X1 and X2. It  
may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10  
pF). X1 and X2 may not be used to drive other circuits.  
6.2.4.2  
Parameters  
Table 3. Oscillator and Crystal Characteristics  
VDD = 2.7 to 3.3V , TA = -40 to +85°C  
Symbol  
CX1  
CX2  
CL  
Parameter  
Min  
Typ  
10  
10  
5
Max  
Unit  
pF  
Internal Capacitance (X1 - VSS)  
Internal Capacitance (X2 - VSS)  
Equivalent Load Capacitance (X1 - X2)  
Drive Level  
pF  
pF  
DL  
50  
20  
40  
6
μW  
MHz  
Ω
F
Crystal Frequency  
RS  
Crystal Series Resistance  
Crystal Shunt Capacitance  
CS  
pF  
6.2.5  
Phase Lock Loop  
6.2.5.1  
Schematic  
Figure 6-5. PLL Filter Connection  
FILT  
R
C2  
C1  
VSS  
VSS  
17  
4173ES–USB–09/07  
6.2.5.2  
Parameters  
Table 4. PLL Filter Characteristics  
VDD = 2.7 to 3.3V , TA = -40 to +85°C  
Symbol  
Parameter  
Min  
Typ  
100  
10  
Max  
Unit  
Ω
R
Filter Resistor  
C1  
C2  
Filter Capacitance 1  
Filter Capacitance 2  
nF  
nF  
2.2  
6.2.6  
USB Connection  
6.2.6.1  
Schematic  
Figure 6-6. USB Connection  
VDD  
To Power  
Supply  
RFS  
VBUS  
D+  
D-  
D+  
D-  
RUSB  
RUSB  
GND  
VSS  
6.2.6.2  
Parameters  
Table 16. USB Characteristics  
VDD = 3 to 3.3 V, TA = -40 to +85°C  
Symbol  
RUSB  
Parameter  
Min  
Typ  
27  
Max  
Unit  
Ω
USB Termination Resistor  
USB Full Speed Resistor  
RFS  
1.5  
KΩ  
6.2.7  
In-system Programming  
6.2.7.1  
Schematic  
Figure 6-7. ISP Pull-down Connection  
ISP  
RISP  
VSS  
6.2.7.2  
Parameters  
Table 5. ISP Pull-Down Characteristics  
VDD = 3 to 3.3V , TA = -40 to +85°C  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
RISP  
ISP Pull-Down Resistor  
2.2  
kΩ  
18  
AT89C5132  
4173ES–USB–09/07  
 
AT89C5132  
6.3  
AC Characteristics  
External 8-bit Bus Cycles  
Definition of Symbols  
6.3.1  
6.3.1.1  
Table 6. External 8-bit Bus Cycles Timing Symbol Definitions  
Signals  
Address  
Conditions  
High  
A
D
L
H
L
Data In  
ALE  
Low  
V
X
Z
Valid  
Q
R
W
Data Out  
RD  
No Longer Valid  
Floating  
WR  
6.3.1.2  
Timings  
Test conditions: capacitive load on all pins = 50 pF.  
Table 7. External 8-bit Bus Cycle – Data Read AC Timings  
VDD = 2.7 to 3.3V, TA = -40° to +85°C  
Variable Clock  
Standard Mode  
Variable Clock  
X2 Mode  
Symbol Parameter  
Min  
Max  
Min  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCLCL  
TLHLL  
TAVLL  
TLLAX  
TLLRL  
TRLRH  
TRHLH  
TAVDV  
TAVRL  
TRLDV  
TRLAZ  
TRHDX  
TRHDZ  
Clock Period  
50  
50  
ALE Pulse Width  
2·TCLCL-15  
TCLCL-20  
TCLCL-20  
3·TCLCL-30  
6·TCLCL-25  
TCLCL-20  
TCLCL-15  
Address Valid to ALE Low  
Address hold after ALE Low  
ALE Low to RD Low  
0.5·TCLCL-20  
0.5·TCLCL-20  
1.5·TCLCL-30  
3·TCLCL-25  
RD Pulse Width  
RD high to ALE High  
Address Valid to Valid Data In  
Address Valid to RD Low  
RD Low to Valid Data  
RD Low to Address Float  
Data Hold After RD High  
Instruction Float After RD High  
TCLCL+20  
0.5·TCLCL-20  
0.5·TCLCL+20  
4.5·TCLCL-65  
9·TCLCL-65  
4·TCLCL-30  
2·TCLCL-30  
5·TCLCL-30  
0
2.5·TCLCL-30  
0
0
0
2·TCLCL-25  
TCLCL-25  
19  
4173ES–USB–09/07  
Table 8. External 8-bit Bus Cycle – Data Write AC Timings  
VDD = 2.7 to 3.3V, TA = -40° to +85°C  
Variable Clock  
Standard Mode  
Variable Clock  
X2 Mode  
Symbol Parameter  
Min  
Max  
Min  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCLCL  
TLHLL  
Clock Period  
50  
50  
ALE Pulse Width  
2·TCLCL-15  
TCLCL-20  
TCLCL-20  
3·TCLCL-30  
6·TCLCL-25  
TCLCL-20  
4·TCLCL-30  
7·TCLCL-20  
TCLCL-15  
TCLCL-15  
TAVLL  
Address Valid to ALE Low  
Address hold after ALE Low  
ALE Low to WR Low  
WR Pulse Width  
0.5·TCLCL-20  
0.5·TCLCL-20  
1.5·TCLCL-30  
3·TCLCL-25  
0.5·TCLCL-20  
2·TCLCL-30  
3.5·TCLCL-20  
0.5·TCLCL-15  
TLLAX  
TLLWL  
TWLWH  
TWHLH  
TAVWL  
TQVWH  
TWHQX  
WR High to ALE High  
Address Valid to WR Low  
Data Valid to WR High  
Data Hold after WR High  
TCLCL+20  
0.5·TCLCL+20  
6.3.1.3  
Waveforms  
Figure 6-8. External 8-bit Bus Cycle – Data Read Waveforms  
ALE  
TLHLL  
TLLRL  
TRLRH  
TRHLH  
RD  
TRLDV  
TRHDZ  
TRHDX  
TRLAZ  
TLLAX  
TAVLL  
P0  
P2  
A7:0  
TAVRL  
TAVDV  
D7:0  
Data In  
A15:8  
20  
AT89C5132  
4173ES–USB–09/07  
AT89C5132  
Figure 6-9. External 8-bit Bus Cycle – Data Write Waveforms  
ALE  
TLHLL  
TWHLH  
TLLWL  
TWLWH  
WR  
TAVWL  
TLLAX  
TAVLL  
TQVWH  
TWHQX  
P0  
P2  
A7:0  
D7:0  
Data Out  
A15:8  
6.3.2  
External IDE 16-bit Bus Cycles  
6.3.2.1  
Definition of Symbols  
Table 9. External IDE 16-bit Bus Cycles Timing Symbol Definitions  
Signals  
Conditions  
High  
A
D
L
Address  
Data In  
ALE  
H
L
Low  
V
X
Z
Valid  
Q
R
W
Data Out  
RD  
No Longer Valid  
Floating  
WR  
6.3.2.2  
Timings  
Test conditions: capacitive load on all pins = 50 pF.  
21  
4173ES–USB–09/07  
Table 10. External IDE 16-bit Bus Cycle – Data Read AC Timings  
VDD = 2.7 to 3.3V, TA = -40° to +85°C  
Variable Clock  
Standard Mode  
Variable Clock  
X2 Mode  
Symbol Parameter  
Min  
Max  
Min  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCLCL  
TLHLL  
TAVLL  
TLLAX  
TLLRL  
TRLRH  
TRHLH  
TAVDV  
TAVRL  
TRLDV  
TRLAZ  
TRHDX  
TRHDZ  
Clock Period  
50  
50  
ALE Pulse Width  
2·TCLCL-15  
TCLCL-20  
TCLCL-20  
3·TCLCL-30  
6·TCLCL-25  
TCLCL-20  
TCLCL-15  
Address Valid to ALE Low  
Address hold after ALE Low  
ALE Low to RD Low  
0.5·TCLCL-20  
0.5·TCLCL-20  
1.5·TCLCL-30  
3·TCLCL-25  
0.5·TCLCL-20  
RD Pulse Width  
RD high to ALE High  
Address Valid to Valid Data In  
Address Valid to RD Low  
RD Low to Valid Data  
RD Low to Address Float  
Data Hold After RD High  
Instruction Float After RD High  
TCLCL+20  
0.5·TCLCL+20  
4.5·TCLCL-65  
9·TCLCL-65  
4·TCLCL-30  
2·TCLCL-30  
5·TCLCL-30  
0
2.5·TCLCL-30  
0
0
0
2·TCLCL-25  
TCLCL-25  
Table 11. External IDE 16-bit Bus Cycle – Data Write AC Timings  
VDD = 2.7 to 3.3V, TA = -40° to +85°C  
Variable Clock  
Standard Mode  
Variable Clock  
X2 Mode  
Symbol Parameter  
Min  
Max  
Min  
50  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCLCL  
TLHLL  
Clock Period  
50  
ALE Pulse Width  
2·TCLCL-15  
TCLCL-20  
TCLCL-20  
3·TCLCL-30  
6·TCLCL-25  
TCLCL-20  
4·TCLCL-30  
7·TCLCL-20  
TCLCL-15  
TCLCL-15  
TAVLL  
Address Valid to ALE Low  
Address hold after ALE Low  
ALE Low to WR Low  
WR Pulse Width  
0.5·TCLCL-20  
0.5·TCLCL-20  
1.5·TCLCL-30  
3·TCLCL-25  
TLLAX  
TLLWL  
TWLWH  
TWHLH  
TAVWL  
TQVWH  
TWHQX  
WR High to ALE High  
Address Valid to WR Low  
Data Valid to WR High  
Data Hold after WR High  
TCLCL+20  
0.5·TCLCL-20  
2·TCLCL-30  
0.5·TCLCL+20  
3.5·TCLCL-20  
0.5·TCLCL-15  
22  
AT89C5132  
4173ES–USB–09/07  
AT89C5132  
6.3.2.3  
Waveforms  
Figure 6-10. External IDE 16-bit Bus Cycle – Data Read Waveforms  
ALE  
TLHLL  
TLLRL  
TRLRH  
TRHLH  
RD  
TRLDV  
TRHDZ  
TRHDX  
TRLAZ  
TLLAX  
TAVLL  
P0  
P2  
A7:0  
TAVRL  
TAVDV  
D7:0  
Data In  
A15:8  
D15:81  
Data In  
Note:  
D15:8 is written in DAT16H SFR.  
Figure 6-11. External IDE 16-bit Bus Cycle – Data Write Waveforms  
ALE  
TLHLL  
TWHLH  
TLLWL  
TWLWH  
WR  
TAVWL  
TLLAX  
TAVLL  
TQVWH  
TWHQX  
P0  
P2  
A7:0  
D7:0  
Data Out  
A15:8  
D15:81  
Data Out  
Note:  
D15:8 is the content of DAT16H SFR.  
6.3.3  
SPI Interface  
6.3.3.1  
Definition of Symbols  
Table 12. SPI Interface Timing Symbol Definitions  
Signals  
Conditions  
High  
C
I
Clock  
H
L
Data In  
Data Out  
Low  
O
V
X
Z
Valid  
No Longer Valid  
Floating  
23  
4173ES–USB–09/07  
6.3.3.2  
Timings  
Table 13. SPI Interface Master AC Timing  
VDD = 2.7 to 3.3V, TA = -40° to +85°C  
Symbol  
Parameter  
Min  
Max  
Unit  
Slave Mode  
TCHCH  
Clock Period  
8
TOSC  
TOSC  
TOSC  
ns  
TCHCX  
Clock High Time  
Clock Low Time  
SS Low to Clock edge  
3.2  
3.2  
200  
100  
100  
TCLCX  
TSLCH, TSLCL  
T
T
T
T
T
T
T
IVCL, TIVCH  
CLIX, TCHIX  
CLOV, TCHOV  
CLOX, TCHOX  
CLSH, TCHSH  
IVCL, TIVCH  
CLIX, TCHIX  
Input Data Valid to Clock Edge  
Input Data Hold after Clock Edge  
Output Data Valid after Clock Edge  
Output Data Hold Time after Clock Edge  
SS High after Clock Edge  
Input Data Valid to Clock Edge  
Input Data Hold after Clock Edge  
SS Low to Output Data Valid  
Output Data Hold after SS High  
SS High to SS Low  
ns  
ns  
100  
ns  
0
ns  
0
ns  
100  
100  
ns  
ns  
TSLOV  
TSHOX  
TSHSL  
TILIH  
130  
130  
ns  
ns  
(1)  
Input Rise Time  
2
μs  
μs  
ns  
ns  
TIHIL  
Input Fall Time  
2
TOLOH  
TOHOL  
Output Rise Time  
100  
100  
Output Fall Time  
Master Mode  
TCHCH  
Clock Period  
4
TOSC  
TOSC  
TOSC  
ns  
TCHCX  
Clock High Time  
1.6  
1.6  
50  
50  
TCLCX  
Clock Low Time  
TIVCL, TIVCH  
Input Data Valid to Clock Edge  
Input Data Hold after Clock Edge  
Output Data Valid after Clock Edge  
Output Data Hold Time after Clock Edge  
Input Data Rise Time  
T
T
CLIX, TCHIX  
ns  
CLOV, TCHOV  
65  
ns  
TCLOX, TCHOX  
TILIH  
0
ns  
2
2
μs  
TIHIL  
Input Data Fall Time  
μs  
TOLOH  
Output Data Rise Time  
50  
50  
ns  
TOHOL  
Output Data Fall Time  
ns  
Notes: 1. Value of this parameter depends on software.  
2. Test conditions: capacitive load on all pins = 100 pF  
24  
AT89C5132  
4173ES–USB–09/07  
AT89C5132  
6.3.3.3  
Waveforms  
Figure 6-12. SPI Slave Waveforms (SSCPHA = 0)  
SS  
(input)  
TSLCH  
TCLSH  
TCHSH  
TCHCH  
TSHSL  
TSLCL  
TCLCH  
SCK  
(SSCPOL = 0)  
(input)  
TCHCX  
TCLCX  
TCHCL  
SCK  
(SSCPOL = 1)  
(input)  
TCLOX  
TCHOX  
TCLOV  
TCHOV  
TSLOV  
SLAVE MSB OUT  
TSHOX  
MISO  
(output)  
BIT 6  
SLAVE LSB OUT  
1
TCHIX  
TCLIX  
TIVCH  
TIVCL  
MOSI  
(input)  
MSB IN  
BIT 6  
LSB IN  
Note:  
1. Not Defined but generally the MSB of the character which has just been received.  
Figure 6-13. SPI Slave Waveforms (SSCPHA = 1)  
SS1  
(output)  
TCHCH  
TCLCH  
SCK  
(SSCPOL = 0)  
(output)  
TCHCX  
TCLCX  
TCHCL  
SCK  
(SSCPOL = 1)  
(output)  
TIVCH  
TCHIX  
TIVCL TCLIX  
SI  
(input)  
MSB IN  
BIT 6  
TCLOV  
TCHOV  
LSB IN  
TCLOX  
TCHOX  
SO  
(output)  
Port Data  
MSB OUT  
BIT 6  
LSB OUT  
Port Data  
Note:  
1. Not Defined but generally the LSB of the character which has just been received.  
25  
4173ES–USB–09/07  
Figure 6-14. SPI Master Waveforms (SSCPHA = 0)  
SS1  
(input)  
TSLCH  
TCLSH  
TCHSH  
TSLCL  
TCHCH  
TSHSL  
TCLCH  
SCK  
(SSCPOL = 0)  
(input)  
TCHCX  
TCLCX  
TCHCL  
SCK  
(SSCPOL = 1)  
(input)  
TCHOV  
TCLOV  
TCHOX  
TCLOX  
TSLOV  
SLAVE MSB OUT  
TSHOX  
MISO  
(output)  
BIT 6  
SLAVE LSB OUT  
1
TIVCH  
TIVCL  
TCHIX  
TCLIX  
MOSI  
(input)  
MSB IN  
BIT 6  
LSB IN  
Note:  
1. SS handled by software using general purpose port pin.  
Figure 6-15. SPI Master Waveforms (SSCPHA = 1)  
SS1  
(output)  
TCHCH  
TCLCH  
SCK  
(SSCPOL = 0)  
(output)  
TCHCX  
TCLCX  
TCHCL  
SCK  
(SSCPOL = 1)  
(output)  
TIVCH  
TCHIX  
TIVCL TCLIX  
SI  
(input)  
MSB IN  
TCLOV  
BIT 6  
LSB IN  
TCLOX  
TCHOX  
TCHOV  
SO  
(output)  
Port Data  
MSB OUT  
BIT 6  
LSB OUT  
Port Data  
Note:  
1. SS handled by software using general purpose port pin.  
6.3.4  
Two-wire Interface  
6.3.4.1  
Timings  
Table 17. TWI Interface AC Timing  
26  
AT89C5132  
4173ES–USB–09/07  
AT89C5132  
VDD = 2.7 to 3.3 V, TA = -40 to +85°C  
INPUT  
Min  
OUTPUT  
Min  
Symbol  
THD; STA  
TLOW  
Parameter  
Max  
Max  
(4)  
(4)  
(4)  
Start condition hold time  
SCL low time  
14·TCLCL  
16·TCLCL  
14·TCLCL  
1 μs  
4.0 μs(1)  
4.7 μs(1)  
4.0 μs(1)  
THIGH  
SCL high time  
(2)  
TRC  
SCL rise time  
-
TFC  
SCL fall time  
0.3 μs  
0.3 μs(3)  
20·TCLCL(4)- TRD  
1 μs(1)  
TSU; DAT1  
TSU; DAT2  
TSU; DAT3  
THD; DAT  
TSU; STA  
TSU; STO  
TBUF  
Data set-up time  
250 ns  
250 ns  
250 ns  
0 ns  
SDA set-up time (before repeated START condition)  
SDA set-up time (before STOP condition)  
Data hold time  
(4)  
8·TCLCL  
8·TCLCL(4) - TFC  
4.7 μs(1)  
(4)  
Repeated START set-up time  
STOP condition set-up time  
Bus free time  
14·TCLCL  
14·TCLCL  
14·TCLCL  
1 μs  
(4)  
(4)  
4.0 μs(1)  
4.7 μs(1)  
(2)  
TRD  
SDA rise time  
-
TFD  
SDA fall time  
0.3 μs  
0.3 μs(3)  
Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.  
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this  
must be < 1 μs.  
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maxi-  
mum capacitance on bus-lines SDA and  
SCL= 400 pF.  
4. TCLCL= TOSC= one oscillator clock period.  
6.3.4.2  
Waveforms  
Figure 6-16. Two Wire Waveforms  
Repeated START condition  
START or Repeated START condition  
Trd  
START condition  
Tsu;STA  
STOP condition  
0.7 VDD  
0.3 VDD  
SDA  
(INPUT/OUTPUT)  
Tsu;STO  
Tbuf  
Tfd  
Tsu;DAT3  
Trc  
Tfc  
0.7 VDD  
0.3 VDD  
SCL  
(INPUT/OUTPUT)  
Thigh  
Tsu;DAT2  
Tlow  
Thd;STA  
Thd;DAT  
Tsu;DAT1  
27  
4173ES–USB–09/07  
6.3.5  
MMC Interface  
6.3.5.1  
Definition of Symbols  
Table 14. MMC Interface Timing Symbol Definitions  
Signals  
Clock  
Conditions  
High  
C
D
O
H
L
Data In  
Low  
Data Out  
V
X
Valid  
No Longer Valid  
6.3.5.2  
Timings  
Table 15. MMC Interface AC Timings  
VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL 100pF (10 cards)  
Symbol  
Parameter  
Min  
50  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCHCH  
TCHCX  
TCLCX  
TCLCH  
TCHCL  
TDVCH  
TCHDX  
TCHOX  
TOVCH  
Clock Period  
Clock High Time  
10  
Clock Low Time  
10  
Clock Rise Time  
10  
10  
Clock Fall Time  
Input Data Valid to Clock High  
Input Data Hold after Clock High  
Output Data Hold after Clock High  
Output Data Valid to Clock High  
3
3
5
5
6.3.5.3  
Waveforms  
Figure 6-17. MMC Input Output Waveforms  
TCHCH  
TCHCX  
TCLCX  
MCLK  
TCHCL  
TCLCH  
TIVCH  
TCHIX  
MCMD Input  
MDAT Input  
TCHOX  
TOVCH  
MCMD Output  
MDAT Output  
28  
AT89C5132  
4173ES–USB–09/07  
AT89C5132  
6.3.6  
Audio Interface  
6.3.6.1  
Definition of Symbols  
Table 16. Audio Interface Timing Symbol Definitions  
Signals  
Clock  
Conditions  
High  
C
O
S
H
L
Data Out  
Low  
Data Select  
V
X
Valid  
No Longer Valid  
6.3.6.2  
Timings  
Table 17. Audio Interface AC timings  
VDD = 2.7 to 3.3V, TA = -40 to +85°C, CL 30pF  
Symbol  
TCHCH  
TCHCX  
TCLCX  
TCLCH  
TCHCL  
TCLSV  
Parameter  
Min  
Max  
Unit  
ns  
Clock Period  
325.5(1)  
Clock High Time  
Clock Low Time  
Clock Rise Time  
Clock Fall Time  
30  
30  
ns  
ns  
10  
10  
10  
10  
ns  
ns  
Clock Low to Select Valid  
Clock Low to Data Valid  
ns  
TCLOV  
Note:  
ns  
32-bit format with Fs = 48 kHz.  
6.3.6.3  
Waveforms  
Figure 6-18. Audio Interface Waveforms  
TCHCH  
TCHCX  
TCLCX  
DCLK  
TCHCL  
TCLCH  
TCLSV  
DSEL  
DDAT  
Right  
Left  
TCLOV  
29  
4173ES–USB–09/07  
6.3.7  
Analog to Digital Converter  
6.3.7.1  
Definition of Symbols  
Table 18. Analog to Digital Converter Timing Symbol Definitions  
Signals  
Clock  
Conditions  
High  
C
E
H
L
Enable (ADEN bit)  
Low  
Start Conversion  
(ADSST bit)  
S
6.3.7.2  
Characteristics  
Table 18. Analog to Digital Converter AC Characteristics  
VDD = 2.7 to 3.3 V, TA = -40 to +85°C  
Symbol  
Parameter  
Clock Period  
Min  
Max  
Unit  
μs  
TCLCL  
TEHSH  
TSHSL  
4
Start-up Time  
4
μs  
Conversion Time  
11·TCLCL  
μs  
Differential non-  
linearity error(1)(2)  
DLe  
ILe  
1
2
LSB  
LSB  
Integral non-linearity  
errorss(1)(3)  
OSe  
Ge  
Offset error(1)(4)  
Gain error(1)(5)  
4
4
LSB  
LSB  
Notes: 1. AVDD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code.  
2. The differential non-linearity is the difference between the actual step width and the ideal step  
width (see Figure 6-20).  
3. The integral non-linearity is the peak difference between the center of the actual step and the  
ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 6-20).  
4. The offset error is the absolute difference between the straight line which fits the actual trans-  
fer curve (after removing of gain error), and the straight line which fits the ideal transfer curve  
(see Figure 6-20).  
5. The gain error is the relative difference in percent between the straight line which fits the actual  
transfer curve (after removing of offset error), and the straight line which fits the ideal transfer  
curve (see Figure 6-20).  
30  
AT89C5132  
4173ES–USB–09/07  
AT89C5132  
6.3.7.3  
Waveforms  
Figure 6-19. Analog-to-Digital Converter Internal Waveforms  
CLK  
TCLCL  
ADEN Bit  
TEHSH  
ADSST Bit  
TSHSL  
Figure 6-20. Analog-to-Digital Converter Characteristics  
Offset Gain  
Error Error  
Code Out  
OSe  
Ge  
1023  
1022  
1021  
1020  
1019  
1018  
Ideal Transfer Curve  
7
6
5
Example of an Actual Transfer Curve  
Center of a Step  
4
3
2
1
Integral Non-linearity (ILe)  
Differential Non-linearity (DLe)  
1 LSB  
(Ideal)  
0
0
AVIN (LSBideal)  
1
2
3
4
5
6
7
1018 1019 1020 1021 1022 1023 1024  
Offset  
Error  
OSe  
31  
4173ES–USB–09/07  
6.3.8  
Flash Memory  
6.3.8.1  
Definition of Symbols  
Table 19. Flash Memory Timing Symbol Definitions  
Signals  
ISP  
Conditions  
Low  
S
R
B
L
V
X
RST  
Valid  
FBUSY flag  
No Longer Valid  
6.3.8.2  
Timings  
Table 20. Flash Memory AC Timing  
VDD = 2.7 to 3.3V, TA = -40° to +85°C  
Symbol  
Parameter  
Min  
50  
Typ  
Max  
Unit  
ns  
TSVRL  
TRLSX  
TBHBL  
NFCY  
TFDR  
Input ISP Valid to RST Edge  
Input ISP Hold after RST Edge  
FLASH Internal Busy (Programming) Time  
Number of Flash Write Cycles  
Flash Data Retention Time  
50  
ns  
10  
ms  
100K  
10  
Cycle  
Year  
6.3.8.3  
Waveforms  
Figure 6-21. Flash Memory – ISP Waveforms  
RST  
TSVRL  
TRLSX  
ISP(1)  
Note:  
1. ISP must be driven through a pull-down resistor (see Section “In-system Programming”,  
page 18).  
Figure 6-22. Flash Memory – Internal Busy Waveforms  
FBUSY bit  
TBHBL  
6.3.9  
External Clock Drive and Logic Level References  
6.3.9.1  
Definition of Symbols  
Table 21. External Clock Timing Symbol Definitions  
Signals  
Clock  
Conditions  
High  
C
H
L
Low  
X
No Longer Valid  
32  
AT89C5132  
4173ES–USB–09/07  
AT89C5132  
6.3.9.2  
Timings  
Table 22. External Clock AC Timings  
VDD = 2.7 to 3.3V, TA= -40 to +85°C  
Symbol  
TCLCL  
Parameter  
Min  
50  
10  
10  
3
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
%
Clock Period  
High Time  
TCHCX  
TCLCX  
TCLCH  
TCHCL  
TCR  
Low Time  
Rise Time  
Fall Time  
3
Cyclic Ratio in X2 Mode  
40  
60  
6.3.9.3  
Waveforms  
Figure 6-23. External Clock Waveform  
TCLCH  
TCHCX  
VDD - 0.5  
VIH1  
TCLCX  
VIL  
0.45 V  
TCHCL  
TCLCL  
Figure 6-24. AC Testing Input/Output Waveforms  
INPUTS  
OUTPUTS  
VIH min  
VIL max  
VDD - 0.5  
0.7 VDD  
0.3 VDD  
0.45 V  
Notes: 1. During AC testing, all inputs are driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0.  
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.  
Figure 6-25. Float Waveforms  
VLOAD + 0.1V  
LOAD - 0.1V  
VOH - 0.1V  
OL + 0.1V  
VLOAD  
Timing Reference Points  
V
V
Note:  
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a  
100 mV change from the loading VOH/VOL level occurs with IOL/IOH = 20 mA.  
33  
4173ES–USB–09/07  
7. Ordering Information  
Possible Order Entries(1)  
Max  
Frequency  
(MHz)  
Temperature  
Range  
Memory Size  
Supply  
Voltage  
Product  
Marking  
Part Number  
(Bytes)  
Package  
Packing  
AT89C5132-ROTIL  
64K Flash  
3V  
Industrial  
40  
TQFP80  
Tray  
895132-IL  
Industrial &  
Green  
AT89C5132-ROTUL  
64K Flash  
3V  
40  
TQFP80  
Tray  
895132-UL  
Note:  
1. PLCC84 package only available for development board.  
34  
AT89C5132  
4173ES–USB–09/07  
AT89C5132  
8. Package Information  
8.1  
TQFP80  
35  
4173ES–USB–09/07  
8.2  
PLCC84  
36  
AT89C5132  
4173ES–USB–09/07  
AT89C5132  
9. Datasheet Revision History for AT89C5132  
9.1  
Changes from 4173A-08/02 to 4173B-03/04  
1. Suppression of ROM product version.  
2. Suppression of TQFP64 package.  
9.2  
Changes from 4173B-03/04 - 4173C - 07/04  
1. Add USB connection schematic in USB section.  
2. Add USB termination characteristics in DC Characteristics section.  
3. Page access mode clarification in Data Memory section.  
9.3  
9.4  
Changes from 4173C-07/04 - 4173D - 01/05  
1. Interrupt priority number clarification to match number defined by development tools.  
Changes from to 4317D - 01/05 to 4173E - 09/07  
1. Added green product ordering information.  
2. Removed ‘Preliminary’ status. Product now fully Industrialised.  
37  
4173ES–USB–09/07  
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4173ES–USB–09/07  

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