Analog Devices AD620 User Manual

Low Cost, Low Power  
Instrumentation Amplifier  
a
AD620  
CONNECTION DIAGRAM  
FEATURES  
EASY TO USE  
Gain Set with One External Resistor  
(Gain Range 1 to 1000)  
8-Lead Plastic Mini-DIP (N), Cerdip (Q)  
and SOIC (R) Packages  
Wide Power Supply Range (؎2.3 V to ؎18 V)  
Higher Performance than Three Op Amp IA Designs  
Available in 8-Lead DIP and SOIC Packaging  
Low Power, 1.3 mA max Supply Current  
1
2
3
4
8
7
6
5
R
R
G
G
+V  
–IN  
+IN  
S
OUTPUT  
REF  
EXCELLENT DC PERFORMANCE (“B GRADE”)  
50 V max, Input Offset Voltage  
0.6 V/؇C max, Input Offset Drift  
–V  
S
AD620  
TOP VIEW  
1.0 nA max, Input Bias Current  
100 dB min Common-Mode Rejection Ratio (G = 10)  
1000. Furthermore, the AD620 features 8-lead SOIC and DIP  
packaging that is smaller than discrete designs, and offers lower  
power (only 1.3 mA max supply current), making it a good fit  
for battery powered, portable (or remote) applications.  
LOW NOISE  
9 nV/Hz, @ 1 kHz, Input Voltage Noise  
0.28 V p-p Noise (0.1 Hz to 10 Hz)  
The AD620, with its high accuracy of 40 ppm maximum  
nonlinearity, low offset voltage of 50 µV max and offset drift of  
0.6 µV/°C max, is ideal for use in precision data acquisition  
systems, such as weigh scales and transducer interfaces. Fur-  
thermore, the low noise, low input bias current, and low power  
of the AD620 make it well suited for medical applications such  
as ECG and noninvasive blood pressure monitors.  
EXCELLENT AC SPECIFICATIONS  
120 kHz Bandwidth (G = 100)  
15 s Settling Time to 0.01%  
APPLICATIONS  
Weigh Scales  
ECG and Medical Instrumentation  
Transducer Interface  
Data Acquisition Systems  
Industrial Process Controls  
Battery Powered and Portable Equipment  
The low input bias current of 1.0 nA max is made possible with  
the use of Superβeta processing in the input stage. The AD620  
works well as a preamplifier due to its low input voltage noise of  
9 nV/Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band,  
0.1 pA/Hz input current noise. Also, the AD620 is well suited  
for multiplexed applications with its settling time of 15 µs to  
0.01% and its cost is low enough to enable designs with one in-  
amp per channel.  
PRODUCT DESCRIPTION  
The AD620 is a low cost, high accuracy instrumentation ampli-  
fier that requires only one external resistor to set gains of 1 to  
30,000  
10,000  
25,000  
20,000  
15,000  
10,000  
5,000  
0
3 OP-AMP  
IN-AMP  
1,000  
(3 OP-07s)  
TYPICAL STANDARD  
BIPOLAR INPUT  
IN-AMP  
100  
G = 100  
AD620A  
10  
R
G
AD620 SUPERETA  
BIPOLAR INPUT  
1
IN-AMP  
0.1  
1k  
0
5
10  
15  
20  
10k  
100k  
1M  
10M  
100M  
SUPPLY CURRENT – mA  
SOURCE RESISTANCE – ⍀  
Figure 1. Three Op Amp IA Designs vs. AD620  
Figure 2. Total Voltage Noise vs. Source Resistance  
REV. E  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
© Analog Devices, Inc., 1999  
AD620  
AD620A  
AD620B  
AD620S1  
Model  
Conditions  
Min  
Typ Max  
Min  
Typ Max  
Min  
Typ Max  
Units  
DYNAMIC RESPONSE  
Small Signal –3 dB Bandwidth  
G = 1  
G = 10  
G = 100  
G = 1000  
Slew Rate  
Settling Time to 0.01%  
G = 1–100  
G = 1000  
1000  
800  
120  
12  
1000  
800  
120  
12  
1000  
800  
120  
12  
kHz  
kHz  
kHz  
kHz  
V/µs  
0.75  
1.2  
0.75  
1.2  
0.75  
1.2  
10 V Step  
15  
150  
15  
150  
15  
150  
µs  
µs  
NOISE  
Total RTI Noise = (e2 )+(e /G)2  
Voltage Noise, 1 kHz  
no  
ni  
Input, Voltage Noise, eni  
Output, Voltage Noise, eno  
RTI, 0.1 Hz to 10 Hz  
G = 1  
G = 10  
G = 100–1000  
9
72  
13  
100  
9
72  
13  
100  
9
72  
13  
100  
nV/Hz  
nV/Hz  
3.0  
3.0  
6.0  
3.0  
6.0  
µV p-p  
µV p-p  
µV p-p  
fA/Hz  
pA p-p  
0.55  
0.28  
100  
10  
0.55 0.8  
0.28 0.4  
100  
0.55 0.8  
0.28 0.4  
100  
Current Noise  
0.1 Hz to 10 Hz  
f = 1 kHz  
10  
10  
REFERENCE INPUT  
RIN  
IIN  
20  
20  
20  
kΩ  
VIN+, VREF = 0  
+50 +60  
+VS – 1.6  
1 ± 0.0001  
+50 +60  
+50 +60  
µA  
Voltage Range  
Gain to Output  
–VS + 1.6  
–VS + 1.6  
+VS – 1.6  
–VS + 1.6  
+VS – 1.6  
V
1 ± 0.0001  
1 ± 0.0001  
POWER SUPPLY  
Operating Range4  
Quiescent Current  
Over Temperature  
±2.3  
±18  
1.3  
1.6  
±2.3  
±18  
1.3  
1.6  
±2.3  
±18  
1.3  
1.6  
V
mA  
mA  
VS = ±2.3 V to ±18 V  
0.9  
1.1  
0.9  
1.1  
0.9  
1.1  
TEMPERATURE RANGE  
For Specified Performance  
40 to +85  
40 to +85  
–55 to +125  
°C  
NOTES  
1See Analog Devices military data sheet for 883B tested specifications.  
2Does not include effects of external resistor RG.  
3One input grounded. G = 1.  
4This is defined as the same supply range which is used to specify PSR.  
Specifications subject to change without notice.  
REV. E  
–3–  
AD620  
ABSOLUTE MAXIMUM RATINGS1  
ORDERING GUIDE  
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V  
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 650 mW  
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS  
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .±25 V  
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite  
Storage Temperature Range (Q) . . . . . . . . . . –65°C to +150°C  
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C  
Operating Temperature Range  
AD620 (A, B) . . . . . . . . . . . . . . . . . . . . . . 40°C to +85°C  
AD620 (S) . . . . . . . . . . . . . . . . . . . . . . . . 55°C to +125°C  
Lead Temperature Range  
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300°C  
NOTES  
Model  
Temperature Ranges Package Options*  
AD620AN  
AD620BN  
AD620AR  
40°C to +85°C  
40°C to +85°C  
40°C to +85°C  
N-8  
N-8  
SO-8  
13" REEL  
7" REEL  
SO-8  
AD620AR-REEL –40°C to +85°C  
AD620AR-REEL7 –40°C to +85°C  
AD620BR  
40°C to +85°C  
AD620BR-REEL –40°C to +85°C  
13" REEL  
7" REEL  
Die Form  
Q-8  
AD620BR-REEL7 –40°C to +85°C  
AD620ACHIPS  
AD620SQ/883B  
40°C to +85°C  
–55°C to +125°C  
*N = Plastic DIP; Q = Cerdip; SO = Small Outline.  
1Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
2Specification is for device in free air:  
8-Lead Plastic Package: θJA = 95°C/W  
8-Lead Cerdip Package: θJA = 110°C/W  
8-Lead SOIC Package: θJA = 155°C/W  
METALIZATION PHOTOGRAPH  
Dimensions shown in inches and (mm).  
Contact factory for latest dimensions.  
R
*
+V  
S
G
OUTPUT  
6
7
8
5
REFERENCE  
8
0.0708  
(1.799)  
1
4
3
1
2
0.125  
(3.180)  
–V  
S
R
*
G
+IN  
–IN  
*FOR CHIP APPLICATIONS: THE PADS 1R AND 8R MUST BE CONNECTED IN PARALLEL  
G
G
TO THE EXTERNAL GAIN REGISTER R . DO NOT CONNECT THEM IN SERIES TO R . FOR  
G
G
UNITY GAIN APPLICATIONS WHERE R IS NOT REQUIRED, THE PADS 1R MAY SIMPLY  
G
G
BE BONDED TOGETHER, AS WELL AS THE PADS 8R  
.
G
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the AD620 features proprietary ESD protection circuitry, permanent damage may  
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD  
precautions are recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
–4–  
REV. E  
AD620  
(@ +25؇C, V = ؎15 V, R = 2 k, unless otherwise noted)  
Typical Characteristics  
S
L
50  
2.0  
1.5  
1.0  
SAMPLE SIZE = 360  
40  
30  
+I  
B
–I  
B
0.5  
0
20  
10  
–0.5  
–1.0  
–1.5  
–2.0  
0
–80  
–40  
0
+40  
+80  
–75  
–25  
25  
75  
125  
175  
TEMPERATURE – ؇C  
INPUT OFFSET VOLTAGE – V  
Figure 3. Typical Distribution of Input Offset Voltage  
Figure 6. Input Bias Current vs. Temperature  
2
50  
SAMPLE SIZE = 850  
40  
1.5  
30  
20  
10  
0
1
0.5  
0
–1200  
–600  
0
+600  
+1200  
0
1
2
3
4
5
WARM-UP TIME – Minutes  
INPUT BIAS CURRENT – pA  
Figure 4. Typical Distribution of Input Bias Current  
Figure 7. Change in Input Offset Voltage vs.  
Warm-Up Time  
50  
1000  
SAMPLE SIZE = 850  
40  
GAIN = 1  
100  
30  
GAIN = 10  
20  
10  
10  
GAIN = 100, 1,000  
GAIN = 1000  
BW LIMIT  
0
1
–400  
–200  
0
+200  
+400  
1
10  
100  
1k  
10k  
100k  
FREQUENCY – Hz  
INPUT OFFSET CURRENT – pA  
Figure 5. Typical Distribution of Input Offset Current  
Figure 8. Voltage Noise Spectral Density vs. Frequency,  
(G = 1–1000)  
REV. E  
–5–  
AD620–Typical Characteristics  
1000  
100  
10  
1
1000  
10  
100  
FREQUENCY – Hz  
Figure 9. Current Noise Spectral Density vs. Frequency  
Figure 11. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div  
100,000  
10,000  
FET INPUT  
IN-AMP  
1000  
AD620A  
100  
10  
TIME – 1 SEC/DIV  
1k  
10k  
100k  
1M  
10M  
SOURCE RESISTANCE – ⍀  
Figure 12. Total Drift vs. Source Resistance  
Figure 10a. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)  
+160  
G = 1000  
G = 100  
G = 10  
+140  
+120  
+100  
+80  
G = 1  
+60  
+40  
+20  
0
0.1  
1
10  
100  
1k  
10k  
100k  
1M  
TIME – 1 SEC/DIV  
FREQUENCY – Hz  
Figure 13. CMR vs. Frequency, RTI, Zero to 1 kSource  
Imbalance  
Figure 10b. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)  
–6–  
REV. E  
AD620  
180  
160  
35  
G = 10, 100, 1000  
30  
25  
140  
120  
G = 1000  
G = 1  
20  
15  
100  
80  
G = 100  
G = 10  
G = 1  
10  
5
60  
40  
G = 1000  
G = 100  
20  
0.1  
0
1M  
1
10  
100  
1k  
10k  
100k  
1M  
1k  
10k  
FREQUENCY – Hz  
100k  
FREQUENCY – Hz  
Figure 17. Large Signal Frequency Response  
Figure 14. Positive PSR vs. Frequency, RTI (G = 1–1000)  
+V –0.0  
S
180  
160  
–0.5  
–1.0  
–1.5  
140  
120  
100  
G = 1000  
+1.5  
+1.0  
+0.5  
80  
G = 100  
G = 10  
G = 1  
100k  
60  
40  
–V +0.0  
S
20  
0.1  
0
5
10  
15  
20  
1
10  
100  
1k  
10k  
1M  
SUPPLY VOLTAGE ؎ Volts  
FREQUENCY – Hz  
Figure 15. Negative PSR vs. Frequency, RTI (G = 1–1000)  
Figure 18. Input Voltage Range vs. Supply Voltage, G = 1  
1000  
+V –0.0  
S
–0.5  
R
= 10k⍀  
L
–1.0  
–1.5  
100  
10  
1
R
= 2k⍀  
L
+1.5  
+1.0  
+0.5  
R
= 2k⍀  
L
R
= 10k⍀  
L
–V +0.0  
S
0.1  
100  
1k  
10k  
100k  
1M  
10M  
5
10  
15  
20  
0
FREQUENCY – Hz  
SUPPLY VOLTAGE ؎ Volts  
Figure 16. Gain vs. Frequency  
Figure 19. Output Voltage Swing vs. Supply Voltage,  
G = 10  
REV. E  
–7–  
AD620  
30  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
V
= ؎15V  
S
G = 10  
20  
10  
0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
0
100  
1k  
10k  
LOAD RESISTANCE – ⍀  
Figure 20. Output Voltage Swing vs. Load Resistance  
Figure 23. Large Signal Response and Settling Time,  
G = 10 (0.5 mV = 001%)  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Figure 21. Large Signal Pulse Response and Settling Time  
G = 1 (0.5 mV = 0.01%)  
Figure 24. Small Signal Response, G = 10, RL = 2 k,  
CL = 100 pF  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Figure 22. Small Signal Response, G = 1, RL = 2 k,  
CL = 100 pF  
Figure 25. Large Signal Response and Settling Time,  
G = 100 (0.5 mV = 0.01%)  
–8–  
REV. E  
AD620  
20  
15  
10  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
TO 0.01%  
TO 0.1%  
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
0
0
5
10  
15  
20  
OUTPUT STEP SIZE – Volts  
Figure 26. Small Signal Pulse Response, G = 100,  
Figure 29. Settling Time vs. Step Size (G = 1)  
RL = 2 k, CL = 100 pF  
1000  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
100  
10  
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1
10  
100  
1000  
GAIN  
Figure 27. Large Signal Response and Settling Time,  
G = 1000 (0.5 mV = 0.01%)  
Figure 30. Settling Time to 0.01% vs. Gain, for a 10 V Step  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Figure 28. Small Signal Pulse Response, G = 1000,  
RL = 2 k, CL = 100 pF  
Figure 31a. Gain Nonlinearity, G = 1, RL = 10 kΩ  
(10 µV = 1 ppm)  
REV. E  
–9–  
AD620  
20A  
V
B
20A  
I2  
I1  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
A1  
A2  
10k⍀  
C2  
C1  
10k⍀  
A3  
OUTPUT  
REF  
10k⍀  
10k⍀  
+IN  
R3  
400⍀  
R1  
R2  
– IN  
Q1  
Q2  
R4  
400⍀  
R
G
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
GAIN  
SENSE  
GAIN  
SENSE  
–V  
S
Figure 33. Simplified Schematic of AD620  
THEORY OF OPERATION  
Figure 31b. Gain Nonlinearity, G = 100, RL = 10 kΩ  
(100 µV = 10 ppm)  
The AD620 is a monolithic instrumentation amplifier based on  
a modification of the classic three op amp approach. Absolute  
value trimming allows the user to program gain accurately (to  
0.15% at G = 100) with only one resistor. Monolithic construc-  
tion and laser wafer trimming allow the tight matching and  
tracking of circuit components, thus ensuring the high level of  
performance inherent in this circuit.  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
The input transistors Q1 and Q2 provide a single differential-  
pair bipolar input for high precision (Figure 33), yet offer 10×  
lower Input Bias Current thanks to Superβeta processing. Feed-  
back through the Q1-A1-R1 loop and the Q2-A2-R2 loop main-  
tains constant collector current of the input devices Q1, Q2  
thereby impressing the input voltage across the external gain  
setting resistor RG. This creates a differential gain from the  
inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1.  
The unity-gain subtracter A3 removes any common-mode sig-  
nal, yielding a single-ended output referred to the REF pin  
potential.  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Figure 31c. Gain Nonlinearity, G = 1000, RL = 10 kΩ  
The value of RG also determines the transconductance of the  
preamp stage. As RG is reduced for larger gains, the transcon-  
ductance increases asymptotically to that of the input transistors.  
This has three important advantages: (a) Open-loop gain is  
boosted for increasing programmed gain, thus reducing gain-  
related errors. (b) The gain-bandwidth product (determined by  
C1, C2 and the preamp transconductance) increases with pro-  
grammed gain, thus optimizing frequency response. (c) The  
input voltage noise is reduced to a value of 9 nV/Hz, deter-  
mined mainly by the collector current and base resistance of the  
input devices.  
(1 mV = 100 ppm)  
1k⍀  
10T  
10k⍀  
10k*  
INPUT  
10V p-p  
100k⍀  
V
OUT  
+V  
7
S
2
11k1k⍀  
100⍀  
1
G=1000  
G=1  
The internal gain resistors, R1 and R2, are trimmed to an abso-  
lute value of 24.7 k, allowing the gain to be programmed  
accurately with a single external resistor.  
AD620  
6
G=10  
G=100  
49.94995.49k⍀  
5
8
3
4
The gain equation is then  
–V  
S
49.4 kΩ  
G =  
+ 1  
*ALL RESISTORS 1% TOLERANCE  
RG  
Figure 32. Settling Time Test Circuit  
so that  
49.4 kΩ  
G 1  
RG  
=
–10–  
REV. E  
AD620  
Make vs. Buy: A Typical Bridge Application Error Budget  
The AD620 offers improved performance over “homebrew”  
three op amp IA designs, along with smaller size, fewer compo-  
nents and 10× lower supply current. In the typical application,  
shown in Figure 34, a gain of 100 is required to amplify a bridge  
output of 20 mV full scale over the industrial temperature range  
of –40°C to +85°C. The error budget table below shows how to  
calculate the effect various error sources have on circuit accuracy.  
systems, absolute accuracy and drift errors are by far the most  
significant contributors to error. In more complex systems with  
an intelligent processor, an autogain/autozero cycle will remove all  
absolute accuracy and drift errors leaving only the resolution  
errors of gain nonlinearity and noise, thus allowing full 14-bit  
accuracy.  
Note that for the homebrew circuit, the OP07 specifications for  
input voltage offset and noise have been multiplied by 2. This  
is because a three op amp type in-amp has two op amps at its  
inputs, both contributing to the overall input error.  
Regardless of the system in which it is being used, the AD620  
provides greater accuracy, and at low power and price. In simple  
+10V  
10k*  
10k*  
OP07D  
R = 350⍀  
R = 350⍀  
10k**  
R
G
AD620A  
100**  
499⍀  
OP07D  
10k**  
R = 350⍀  
R = 350⍀  
REFERENCE  
OP07D  
10k*  
10k*  
AD620A MONOLITHIC  
INSTRUMENTATION  
AMPLIFIER, G = 100  
“HOMEBREW” IN-AMP, G = 100  
PRECISION BRIDGE TRANSDUCER  
*0.02% RESISTOR MATCH, 3PPM/؇C TRACKING  
**DISCRETE 1% RESISTOR, 100PPM/؇C TRACKING  
SUPPLY CURRENT = 15mA MAX  
SUPPLY CURRENT = 1.3mA MAX  
Figure 34. Make vs. Buy  
Table I. Make vs. Buy Error Budget  
AD620 Circuit “Homebrew” Circuit  
Error, ppm of Full Scale  
Error Source  
Calculation  
Calculation  
AD620  
Homebrew  
ABSOLUTE ACCURACY at TA = +25°C  
Input Offset Voltage, µV  
Output Offset Voltage, µV  
Input Offset Current, nA  
CMR, dB  
125 µV/20 mV  
1000 µV/100/20 mV  
2 nA × 350 /20 mV  
(150 µV × 2)/20 mV  
((150 µV × 2)/100)/20 mV  
(6 nA × 350 )/20 mV  
16,250  
14,500  
14,118  
14,791  
10,607  
10,150  
14,153  
10,500  
110 dB3.16 ppm, × 5 V/20 mV (0.02% Match × 5 V)/20 mV/100  
Total Absolute Error  
17,558  
11,310  
DRIFT TO +85°C  
Gain Drift, ppm/°C  
Input Offset Voltage Drift, µV/°C  
Output Offset Voltage Drift, µV/°C  
(50 ppm + 10 ppm) × 60°C  
1 µV/°C × 60°C/20 mV  
15 µV/°C × 60°C/100/20 mV  
100 ppm/°C Track × 60°C  
(2.5 µV/°C × 2 × 60°C)/20 mV  
(2.5 µV/°C × 2 × 60°C)/100/20 mV  
13,600  
13,000  
14,450  
16,000  
10,607  
10,150  
Total Drift Error  
17,050  
16,757  
RESOLUTION  
Gain Nonlinearity, ppm of Full Scale  
Typ 0.1 Hz–10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV  
40 ppm  
40 ppm  
(0.38 µV p-p × 2)/20 mV  
14,140  
141,14  
10,140  
13,127  
Total Resolution Error  
Grand Total Error  
14,154  
14,662  
101,67  
28,134  
G = 100, VS = ±15 V.  
(All errors are min/max and referred to input.)  
REV. E  
–11–  
AD620  
+5V  
20k⍀  
7
3
8
3k⍀  
3k⍀  
REF  
IN  
G=100  
499⍀  
6
AD620B  
DIGITAL  
DATA  
OUTPUT  
3k⍀  
3k⍀  
5
10k⍀  
ADC  
1
2
4
AGND  
AD705  
20k⍀  
0.6mA  
MAX  
1.7mA  
0.10mA  
1.3mA  
MAX  
Figure 35. A Pressure Monitor Circuit which Operates on a +5 V Single Supply  
Pressure Measurement  
Medical ECG  
Although useful in many bridge applications such as weigh  
scales, the AD620 is especially suitable for higher resistance  
pressure sensors powered at lower voltages where small size and  
low power become more significant.  
The low current noise of the AD620 allows its use in ECG  
monitors (Figure 36) where high source resistances of 1 Mor  
higher are not uncommon. The AD620’s low power, low supply  
voltage requirements, and space-saving 8-lead mini-DIP and  
SOIC package offerings make it an excellent choice for battery  
powered data recorders.  
Figure 35 shows a 3 kpressure transducer bridge powered  
from +5 V. In such a circuit, the bridge consumes only 1.7 mA.  
Adding the AD620 and a buffered voltage divider allows the  
signal to be conditioned for only 3.8 mA of total supply current.  
Furthermore, the low bias currents and low current noise  
coupled with the low voltage noise of the AD620 improve the  
dynamic range for better performance.  
Small size and low cost make the AD620 especially attractive for  
voltage output pressure transducers. Since it delivers low noise  
and drift, it will also serve applications such as diagnostic non-  
invasive blood pressure measurement.  
The value of capacitor C1 is chosen to maintain stability of the  
right leg drive loop. Proper safeguards, such as isolation, must  
be added to this circuit to protect the patient from possible  
harm.  
+3V  
PATIENT/CIRCUIT  
PROTECTION/ISOLATION  
R1  
10k⍀  
R3  
0.03Hz  
24.9k⍀  
C1  
R
HIGH  
PASS  
OUTPUT  
1V/mV  
G
AD620A  
G = 143  
8.25k⍀  
R2  
24.9k⍀  
FILTER  
R4  
1M⍀  
G = 7  
OUTPUT  
AMPLIFIER  
AD705J  
–3V  
Figure 36. A Medical ECG Monitor Circuit  
–12–  
REV. E  
AD620  
Precision V-I Converter  
INPUT AND OUTPUT OFFSET VOLTAGE  
The AD620, along with another op amp and two resistors, makes  
a precision current source (Figure 37). The op amp buffers the  
reference terminal to maintain good CMR. The output voltage  
VX of the AD620 appears across R1, which converts it to a  
current. This current less only, the input bias current of the op  
amp, then flows out to the load.  
The low errors of the AD620 are attributed to two sources,  
input and output errors. The output error is divided by G when  
referred to the input. In practice, the input errors dominate at  
high gains and the output errors dominate at low gains. The  
total VOS for a given gain is calculated as:  
Total Error RTI = input error + (output error/G)  
Total Error RTO = (input error × G) + output error  
+V  
S
7
REFERENCE TERMINAL  
V
3
8
IN+  
The reference terminal potential defines the zero output voltage,  
and is especially useful when the load does not share a precise  
ground with the rest of the system. It provides a direct means of  
injecting a precise offset to the output, with an allowable range  
of 2 V within the supply voltages. Parasitic resistance should be  
kept to a minimum for optimum CMR.  
+ V  
X
R
AD620  
6
G
R1  
1
2
5
V
IN–  
4
I
L
–V  
S
AD705  
[(V ) – (V )] G  
INPUT PROTECTION  
V
x
IN+  
IN–  
I =  
=
L
R1  
R1  
The AD620 features 400 of series thin film resistance at its  
inputs, and will safely withstand input overloads of up to ±15 V  
or ±60 mA for several hours. This is true for all gains, and power  
on and off, which is particularly important since the signal  
source and amplifier may be powered separately. For longer  
LOAD  
Figure 37. Precision Voltage-to-Current Converter  
(Operates on 1.8 mA, ±3 V)  
time periods, the current should not exceed 6 mA (IIN  
GAIN SELECTION  
VIN/400 ). For input overloads beyond the supplies, clamping  
the inputs to the supplies (using a low leakage diode such as an  
FD333) will reduce the required resistance, yielding lower  
noise.  
The AD620’s gain is resistor programmed by RG, or more pre-  
cisely, by whatever impedance appears between Pins 1 and 8.  
The AD620 is designed to offer accurate gains using 0.1%–1%  
resistors. Table II shows required values of RG for various gains.  
Note that for G = 1, the RG pins are unconnected (RG = ). For  
any arbitrary gain RG can be calculated by using the formula:  
RF INTERFERENCE  
All instrumentation amplifiers can rectify out of band signals,  
and when amplifying small signals, these rectified voltages act as  
small dc offset errors. The AD620 allows direct access to the  
input transistor bases and emitters enabling the user to apply  
some first order filtering to unwanted RF signals (Figure 38),  
where RC Ϸ 1/(2 πf) and where f the bandwidth of the  
AD620; C 150 pF. Matching the extraneous capacitance at  
Pins 1 and 8 and Pins 2 and 3 helps to maintain high CMR.  
49.4 kΩ  
G 1  
RG  
=
To minimize gain error, avoid high parasitic resistance in series  
with RG; to minimize gain drift, RG should have a low TC—less  
than 10 ppm/°C—for the best performance.  
Table II. Required Values of Gain Resistors  
RG  
1% Std Table  
Calculated  
0.1% Std Table Calculated  
Value of RG, Gain  
Value of RG, ⍀  
Gain  
1
2
8
7
49.9 k  
12.4 k  
5.49 k  
1.990  
4.984  
9.998  
49.3 k  
12.4 k  
5.49 k  
2.002  
4.984  
9.998  
C
R
R
–IN  
+IN  
2.61 k  
1.00 k  
499  
19.93  
50.40  
100.0  
2.61 k  
1.01 k  
499  
19.93  
49.91  
100.0  
3
4
6
5
249  
100  
49.9  
199.4  
495.0  
991.0  
249  
98.8  
49.3  
199.4  
501.0  
1,003  
C
Figure 38. Circuit to Attenuate RF Interference  
REV. E  
–13–  
AD620  
COMMON-MODE REJECTION  
GROUNDING  
Instrumentation amplifiers like the AD620 offer high CMR,  
which is a measure of the change in output voltage when both  
inputs are changed by equal amounts. These specifications are  
usually given for a full-range input voltage change and a speci-  
fied source imbalance.  
Since the AD620 output voltage is developed with respect to the  
potential on the reference terminal, it can solve many grounding  
problems by simply tying the REF pin to the appropriate “local  
ground.”  
In order to isolate low level analog signals from a noisy digital  
environment, many data-acquisition components have separate  
analog and digital ground pins (Figure 41). It would be conve-  
nient to use a single ground line; however, current through  
ground wires and PC runs of the circuit card can cause hun-  
dreds of millivolts of error. Therefore, separate ground returns  
should be provided to minimize the current flow from the sensi-  
tive points to the system ground. These ground returns must be  
tied together at some point, usually best at the ADC package as  
shown.  
For optimal CMR the reference terminal should be tied to a low  
impedance point, and differences in capacitance and resistance  
should be kept to a minimum between the two inputs. In many  
applications shielded cables are used to minimize noise, and for  
best CMR over frequency the shield should be properly driven.  
Figures 39 and 40 show active data guards that are configured  
to improve ac common-mode rejections by “bootstrapping” the  
capacitances of input cable shields, thus minimizing the capaci-  
tance mismatch between the inputs.  
+V  
S
ANALOG P.S.  
+15V –15V  
DIGITAL P.S.  
+5V  
– INPUT  
C
C
AD648  
100⍀  
0.1F  
0.1F  
1F  
1
F
1
F
AD620  
V
OUT  
R
G
+
100⍀  
–V  
S
AD620  
DIGITAL  
DATA  
OUTPUT  
AD585  
S/H  
REFERENCE  
AD574A  
ADC  
+ INPUT  
–V  
S
Figure 41. Basic Grounding Practice  
Figure 39. Differential Shield Driver  
+V  
S
– INPUT  
R
G
2
100⍀  
AD620  
V
AD548  
+ INPUT  
OUT  
R
G
2
REFERENCE  
–V  
S
Figure 40. Common-Mode Shield Driver  
–14–  
REV. E  
AD620  
GROUND RETURNS FOR INPUT BIAS CURRENTS  
Input bias currents are those currents necessary to bias the input  
transistors of an amplifier. There must be a direct return path  
for these currents; therefore, when amplifying “floating” input  
sources such as transformers, or ac-coupled sources, there must  
be a dc path from each input to ground as shown in Figure 42.  
Refer to the Instrumentation Amplifier Application Guide (free  
from Analog Devices) for more information regarding in amp  
applications.  
+V  
S
+V  
S
– INPUT  
– INPUT  
R
V
AD620  
G
V
AD620  
OUT  
R
G
OUT  
LOAD  
LOAD  
REFERENCE  
+ INPUT  
REFERENCE  
+ INPUT  
–V  
S
–V  
S
TO POWER  
SUPPLY  
GROUND  
TO POWER  
SUPPLY  
GROUND  
Figure 42b. Ground Returns for Bias Currents with  
Thermocouple Inputs  
Figure 42a. Ground Returns for Bias Currents with  
Transformer Coupled Inputs  
+V  
S
– INPUT  
V
R
G
AD620  
OUT  
LOAD  
+ INPUT  
REFERENCE  
–V  
S
100k⍀  
100k⍀  
TO POWER  
SUPPLY  
GROUND  
Figure 42c. Ground Returns for Bias Currents with AC Coupled Inputs  
REV. E  
–15–  
AD620  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
Plastic DIP (N-8) Package  
0.430 (10.92)  
0.348 (8.84)  
8
5
0.280 (7.11)  
0.240 (6.10)  
1
4
0.325 (8.25)  
0.300 (7.62)  
0.060 (1.52)  
0.015 (0.38)  
PIN 1  
0.195 (4.95)  
0.115 (2.93)  
0.210 (5.33)  
MAX  
0.130  
(3.30)  
MIN  
0.160 (4.06)  
0.115 (2.93)  
0.015 (0.381)  
SEATING  
PLANE  
0.100  
(2.54)  
BSC  
0.022 (0.558)  
0.014 (0.356)  
0.070 (1.77)  
0.045 (1.15)  
0.008 (0.204)  
Cerdip (Q-8) Package  
0.055 (1.4)  
MAX  
0.005 (0.13)  
MIN  
8
5
0.310 (7.87)  
0.220 (5.59)  
4
1
PIN 1  
0.320 (8.13)  
0.290 (7.37)  
0.405 (10.29)  
MAX  
0.060 (1.52)  
0.015 (0.38)  
0.200 (5.08)  
MAX  
0.150  
(3.81)  
MIN  
0.200 (5.08)  
0.125 (3.18)  
0.015 (0.38)  
0.008 (0.20)  
SEATING  
0.070 (1.78)  
0.023 (0.58)  
0.100  
(2.54)  
BSC  
15°  
0°  
PLANE  
0.014 (0.36)  
0.030 (0.76)  
SOIC (SO-8) Package  
0.1968 (5.00)  
0.1890 (4.80)  
8
1
5
4
0.1574 (4.00)  
0.1497 (3.80)  
0.2440 (6.20)  
0.2284 (5.80)  
PIN 1  
0.0688 (1.75)  
0.0532 (1.35)  
0.0196 (0.50)  
x 45°  
0.0099 (0.25)  
0.0098 (0.25)  
0.0040 (0.10)  
8°  
0°  
0.0500  
(1.27)  
BSC  
0.0192 (0.49)  
0.0138 (0.35)  
SEATING  
PLANE  
0.0500 (1.27)  
0.0160 (0.41)  
0.0098 (0.25)  
0.0075 (0.19)  
–16–  
REV. E  

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