AMD Turion™ 64 Mobile Technology
Product Data Sheet
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Compatible with Existing 32-Bit Code Base
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Including support for SSE, SSE2, SSE3*, MMX™,
3DNow!™ technology, and legacy x86 instructions
*SSE3 supported by Rev. E and later processors
Runs existing operating systems and drivers
Local APIC on the chip
754-Pin Package Specific Features
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Refer to the AMD Functional Data Sheet,
754-Pin Package, order# 31410, for functional,
mechanical, and electrical details of 754-pin
packages.
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AMD64 Technology
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AMD64 technology instruction set extensions
64-bit integer registers, 48-bit virtual addresses,
40-bit physical addresses
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Packaging
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754-pin lidless micro PGA
1.27-mm pin pitch
29 x 29-row pin array
40 mm x 40 mm organic substrate
Organic C4 die attach
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Eight additional 64-bit integer registers (16 total)
Eight additional 128-bit SSE registers (16 total)
Enhanced Virus Protection
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No Execute (NX) bit in page-translation tables
specifies whether code can be executed from the
page
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Integrated Memory Controller
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Low-latency, high-bandwidth
72-bitDDR SDRAMat100, 133, 166, and200 MHz
Supports up to two unbuffered SO-DIMMs
ECC checking with double-bit detect and single-bit
correct
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HyperTransport™ Technology to I/O Devices
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One 16-bit link supporting speeds up to 800 MHz
(1600 MT/s) or 3.2 Gbytes/s in each direction
Electrical Interfaces
64-Kbyte 2-Way Associative ECC-Protected
L1 Data Cache
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HyperTransport™ technology: LVDS-like
differential, unidirectional
Two 64-bit operations per cycle, 3-cycle latency
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DDR SDRAM: SSTL_2 per JEDEC specification
Clock, reset, and test signals also use DDR
SDRAM-like electrical specifications.
64-Kbyte 2-Way Associative Parity-Protected
L1 Instruction Cache
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With advanced branch prediction
Power Management
16-Way Associative ECC-Protected
L2 Cache
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Multiple low-power states including Deeper Sleep
(C3 with AltVID)
Exclusive cache architecture—storage in addition
to L1 caches
Up to 1 Mbyte per L2 cache
1 Mbyte and 512-Kbyte options
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System Management Mode (SMM)
ACPI compliant, including support for processor
performance states
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AMD PowerNow!™ technology is designed to
dynamically switch between multiple low-power
states based on application performance
requirements.
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Machine Check Architecture
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Includes hardware scrubbing of major
ECC-protected arrays
Publication #
Issue Date:
32816
September 2006
Revision:
3.05
Advanced Micro Devices
32816 Rev. 3.05 September 2006
AMD Turion™ 64 Mobile Technology Product Data Sheet
Revision History
Date
Revision
Description
September 2006
3.05
Third public release.
Added RoHS compliance statement for socket S1g1 processor-specific features.
August 2006
June 2006
3.03
3.01
Second public release.
Updated Machine Check Architecture section.
Initial public release.
© 2005, 2006 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced Micro Devices, Inc.
(“AMD”) products. AMD makes no representations or warranties with respect to the accuracy
or completeness of the contents of this publication and reserves the right to make changes to
specifications and product descriptions at any time without notice. The information contained
herein may be of a preliminary or advance nature and is subject to change without notice. No
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AMD’s products are not designed, intended, authorized or warranted for use as components in
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Trademarks
AMD, the AMD Arrow logo, AMD Turion and combinations thereof, 3DNow!, and AMD PowerNow! are trademarks of Advanced
Micro Devices, Inc.
HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.
MMX is a trademark of Intel Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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