TM
AMD Sempron
Processor Model 10
with 256K L2 Cache
Data Sheet
Publication # 31994 Rev. A-1
Issue Date: August 2004
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi
1.1
QuantiSpeed™ Architecture Summary. . . . . . . . . . . . . . . . . . . 3
Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Working State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
333 FSB AMD Sempron™ Processor Model 10 with
256K L2 Cache Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical and Thermal Specifications for the
AMD Sempron Processor Model 10 with
256K L2 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
333 FSB AMD Sempron Processor Model 10
SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . 22
333 FSB AMD Athlon System Bus AC Characteristics . . . . . 23
333 FSB AMD Athlon System Bus DC Characteristics . . . . . 24
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 26
Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 27
VCCA AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 27
Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
V
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CC_CORE
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table of Contents
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31994A—1August 2004
SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . 31
7.11 Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.12 Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Thermal Protection Characterization . . . . . . . . . . . . . . . . 36
Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Signal Sequence and Timing Description . . . . . . . . . . . . . 39
Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . 42
Processor Warm Reset Requirements. . . . . . . . . . . . . . . . . . . 42
Northbridge Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
AMD Sempron Processor Model 10 Part Number
27488 OPGA Package Dimensions. . . . . . . . . . . . . . . . . . . . . . 44
AMD Sempron Processor Model 10 Part Number
27493 OPGA Package Dimensions. . . . . . . . . . . . . . . . . . . . . . 46
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1 Pin Diagram and Pin Name Abbreviations. . . . . . . . . . . . . . . 49
10.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3 Detailed Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AMD Athlon System Bus Pins . . . . . . . . . . . . . . . . . . . . . . 68
Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . 69
DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . 69
FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
JTAG Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . 72
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PLL Bypass and Test Pins. . . . . . . . . . . . . . . . . . . . . . . . . . 72
PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SADDIN[1:0]# and SADDOUT[1:0]# Pins. . . . . . . . . . . . . 73
Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
THERMDA and THERMDC Pins. . . . . . . . . . . . . . . . . . . . 73
VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Related Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
List of Figures
Figure 1. Typical AMD Sempron™ Processor Model 10 System
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. AMD Athlon™ System Bus Disconnect Sequence in
the Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CC_CORE
Figure 12. Signal Relationship Requirements During Power-Up
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. AMD Sempron Processor Model 10 Part Number
27488 OPGA Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 14. AMD Sempron Processor Model 10 Part Number
27493 OPGA Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 15. AMD Sempron Processor Model 10 Pin Diagram—
Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 16. AMD Sempron Processor Model 10 Pin Diagram—
Bottomside View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17. OPN Example for the AMD Sempron Processor
Model 10 with 256K L2 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
List of Figures
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
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List of Figures
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
List of Tables
Table 1. Electrical and Thermal Specifications for the
AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 28
CC_CORE
Table 10. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. Guidelines for Platform Thermal Protection of the
Table 16. Mechanical Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. Dimensions for the AMD Sempron Processor
Table 18. Dimensions for the AMD Sempron Processor
Table 25. Constants and Variables Used in Temperature Offset
Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 26. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 27. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
List of Tables
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List of Tables
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
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xii
Revision History
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
1
Overview
The AMD Sempron™ processor model 10 with 256K of L2
cache, the new value brand for every-day computing, performs
at the top of its class. Using QuantiSpeed™ architecture, this
processor is designed to power over 60,000 home and business
applications, and it is compatible with various operating
®
systems including Linux and all existing Windows operating
systems.
The AMD Sempron™ processor model 10 with 256K of L2
cache, based on proven 0.13 micron technology, integrates the
innovative design with the manufacturing expertise of AMD.
The processor delivers excellent performance and low power,
while maximizing system value and maintaining the stable and
compatible Socket A infrastructure of the AMD Sempron
processor. The 4-digit model(+) numbering system helps
identify overall software performance—the higher the number
the better the performance. Detailed technical documentation
and performance benchmarks are available at www.amd.com.
Visit the AMD Sempron processor product comparison site for
more production information.
Delivered in an OPGA package, the AMD Sempron processor
model 10 with 256K of L2 cache has full-featured capabilities
that deliver the integer, floating-point, and 3D multimedia
performance for highly demanding applications running on x86
system platforms. The AMD Sempron processor model 10 with
256K of L2 cache delivers compelling performance for over
60,000 cutting-edge software applications that include:
■
■
■
■
■
■
■
■
■
■
high-speed, smooth stream Internet capability
digital content creation
digital photo editing and digital video
image compression
video encoding for streaming over the Internet
soft DVD
commercial 3D modeling
workstation-class computer-aided design (CAD)
commercial desktop publishing
speech recognition
Chapter 1
Overview
1
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
The AMD Sempron processor model 10 with 256K of L2 cache is
binary-compatible with existing x86 software and backwards
compatible with applications optimized for MMX™, SSE, and
3DNow!™ technology. Using a data format and
single-instruction multiple-data (SIMD) operation based on the
MMX instruction model, the AMD Sempron processor model 10
can produce as many as four, 32-bit, single-precision
floating-point results per clock cycle. The 3DNow! Professional
technology implemented in the AMD Sempron processor model
10 with 256K of L2 cache includes integer multimedia
instructions and software-directed data movement instructions
for optimizing such applications as digital content creation and
streaming video for the internet, as well as instructions for
digital signal processing (DSP) and communications
applications.
The AMD Sempron processor model 10 with 256K of L2 cache
features a seventh-generation microarchitecture with an
integrated, exclusive L2 cache, which supports the growing
processor and system bandwidth requirements of emerging
software, graphics, I/O, and memory technologies. The
high-speed execution core of the AMD Sempron processor
model 10 includes multiple x86 instruction decoders, a
dual-ported 128-Kbyte split level-one (L1) cache, an exclusive
256-Kbyte L2 cache, three independent integer pipelines, three
address calculation pipelines, and a superscalar, pipelined,
out-of-order, three-way floating-point engine. The floating-point
engine is capable of delivering top-of-the-class performance on
numerically complex applications.
The AMD Sempron processor model 10 with 256K of L2 cache
also includes QuantiSpeed™ architecture, a 333-MHz,
2.7-Gigabyte per second AMD Athlon™ system bus, and
3DNow! Professional technology. The AMD Athlon system bus
combines the latest technological advances, such as
point-to-point topology, source-synchronous packet-based
transfers, and low-voltage signaling to provide an extremely
powerful, scalable bus for an x86 processor.
2
Overview
Chapter 1
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
1.1
QuantiSpeed™ Architecture Summary
The following design features summarize the QuantiSpeed
architecture of the AMD Sempron processor model 10 with
256K of L2 cache:
■
A nine-issue, superpipelined, superscalar x86 processor
microarchitecture designed for increased instructions per
cycle (IPC) and high clock frequencies
■
■
Pipelined floating-point unit that executes all x87
(floating-point), MMX, SSE and 3DNow! instructions
Hardware data pre-fetch that increases and optimizes
performance on high-end software applications utilizing
high-bandwidth system capabilitie
s
■
Advanced two-level translation look-aside buffer (TLB)
structures for both enhanced data and instruction address
translation. The AMD Sempron processor model 10 with
QuantiSpeed architecture
incorporates three
TLB
optimizations: the L1 DTLB increases from 32 to 40 entries,
the L2 ITLB and L2 DTLB both use exclusive architecture,
and the TLB entries can be speculatively loaded.
The AMD Sempron processor model 10 delivers excellent
system performance in a cost-effective, industry-standard form
factor. The AMD Sempron processor model 10 is compatible
with motherboards based on Socket A.
Figure 1 on page 4 shows a typical AMD Sempron processor
model 10 with 256K L2 cache system block diagram.
Chapter 1
Overview
3
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Thermal Monitor
AMD Sempron™ Proces-
sor Model 10
AMD Athlon™ System Bus
AGP Bus
AGP
Memory Bus
System Controller
(Northbridge)
SDRAM or DDR
PCI Bus
Peripheral Bus Con-
troller
(Southbridge)
LAN
SCSI
Modem / Audio
LPC Bus
USB
Dual EIDE
BIOS
Figure 1. Typical AMD Sempron™ Processor Model 10 System Block Diagram
4
Overview
Chapter 1
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
2
Interface Signals
This section describes the interface signals utilized by the
AMD Sempron™ processor model 10.
2.1
Overview
The AMD Athlon system bus architecture is designed to deliver
excellent data movement bandwidth for next-generation x86
platforms as well as the high-performance required by
enterprise-class application software. The system bus
architecture consists of three high-speed channels (a
unidirectional processor request channel, a unidirectional
probe channel, and a 64-bit bidirectional data channel),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use an impedance
controlled push-pull, low-voltage, swing-signaling technology
contained within the Socket A socket.
For more information, see “AMD Athlon™ System Bus Signals”
AMD Athlon™ and AMD Duron™ System Bus Specification,
order# 21902.
2.2
Signaling Technology
The AMD Athlon system bus uses a low-voltage, swing-signaling
technology, that has been enhanced to provide larger noise
margins, reduced ringing, and variable voltage levels. The
signals are push-pull and impedance compensated. The signal
inputs use differential receivers that require a reference
voltage (V
). The reference signal is used by the receivers to
REF
determine if a signal is asserted or deasserted by the source.
Termination resistors are not needed because the driver is
impedance-matched to the motherboard and a high impedance
reflection is used at the receiver to bring the signal past the
input threshold.
For more information about pins and signals, see Chapter 10,
Chapter 2
Interface Signals
5
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
2.3
Push-Pull (PP) Drivers
The AMD Sempron processor model 10 supports push-pull (PP)
drivers. The system logic configures the processor with the
configuration parameter called SysPushPull (1=PP). The
impedance of the PP drivers is set to match the impedance of
the motherboard by two external resistors connected to the ZN
and ZP pins.
2.4
AMD Athlon™ System Bus Signals
The AMD Athlon system bus is a clock-forwarded, point-to-
point interface with the following three point-to-point channels:
■
■
■
A 13-bit unidirectional output address/command channel
A 13-bit unidirectional input address/command channel
A 72-bit bidirectional data channel
Specification, order# 21902.
6
Interface Signals
Chapter 2
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
3
Logic Symbol Diagram
diagram shows the logical grouping of the input and output
signals.
Clock
SYSCLK
SYSCLK#
VID[4:0]
COREFB
COREFB#
PWROK
SDATA[63:0]#
{
SDATAINCLK[3:0]#
SDATAOUTCLK[3:0]#
SDATAINVALID#
SDATAOUTVALID#
SFILLVALID#
Voltage
Control
Data
{
Frequency
Control
FID[3:0]
Front-Side Bus
Autodetect
FSB_SENSE[1:0]
SADDIN[14:2]#
SADDINCLK#
Probe/SysCMD
{
FERR
IGNNE#
INIT#
INTR
NMI
A20M#
SMI#
FLUSH#
AMD Sempron™
Processor Model 10
{
SADDOUT[14:2]#
SADDOUTCLK#
Request {
Legacy
PROCRDY
CLKFWDRST
CONNECT
STPCLK#
RESET#
Power
Management
and Initialization
{
{
Thermal
Diode
THERMDA
THERMDC
{
PICCLK
PICD[1:0]
APIC
Figure 2. Logic Symbol Diagram
Chapter 3
Logic Symbol Diagram
7
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
8
Logic Symbol Diagram
Chapter 3
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
4
Power Management
This chapter describes the power management control system
of the AMD Sempron™ Processor Model 10. The power
management features of the processor are compliant with the
ACPI 1.0b and ACPI 2.0 specifications.
4.1
Power Management States
The AMD Sempron processor model 10 supports low-power
Halt and Stop Grant states. These states are used by advanced
configuration and power interface (ACPI) enabled operating
systems for processor power management.
The figure includes the ACPI “Cx” naming convention for these
states.
Execute HLT
C1
Halt
C0
Working4
SMI#, INTR, NMI, INIT#, RESET#
S1
Incoming Probe
Probe Serviced
C2
Probe
State1
Stop Grant
Cache Not Snoopable
Sleep
Stop Grant
Cache Snoopable
Legend
Hardware transitions
Software transitions
Note:
The AMD AthlonTM System Bus is connected during the following states:
1) The Probe state
2) During transitions between the Halt state and the C2 Stop Grant state
3) During transitions between the C2 Stop Grant state and the Halt state
4) C0 Working state
Figure 3. AMD Sempron™ Processor Model 10 Power Management States
Chapter 4
Power Management
9
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
The following sections provide an overview of the power
management states. For more details, refer to the
AMD Athlon™ and AMD Duron™ System Bus Specification,
order# 21902.
Note: In all power management states that the processor is
powered, the system must not stop the system clock
(SYSCLK/SYSCLK#) to the processor.
Working State
Halt State
The Working state is the state in which the processor is
executing instructions.
When the processor executes the HLT instruction, the processor
enters the Halt state and issues a Halt special cycle to the
AMD Athlon system bus. The processor only enters the low
power state dictated by the CLK_Ctl MSR if the system
controller (Northbridge) disconnects the AMD Athlon system
bus in response to the Halt special cycle.
If STPCLK# is asserted, the processor will exit the Halt state
and enter the Stop Grant state. The processor will initiate a
system bus connect, if it is disconnected, then issue a Stop
Grant special cycle. When STPCLK# is deasserted, the
processor will exit the Stop Grant state and re-enter the Halt
state. The processor will issue a Halt special cycle when
re-entering the Halt state.
The Halt state is exited when the processor detects the
assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR
or NMI pins, or via a local APIC interrupt message. When the
Halt state is exited, the processor will initiate an AMD Athlon
system bus connect if it is disconnected.
Stop Grant States
The processor enters the Stop Grant state upon recognition of
assertion of STPCLK# input. After entering the Stop Grant
state, the processor issues a Stop Grant special bus cycle on the
AMD Athlon system bus. The processor is not in a low-power
state at this time, because the AMD Athlon system bus is still
connected. After the Northbridge disconnects the AMD Athlon
system bus in response to the Stop Grant special bus cycle, the
processor enters a low-power state dictated by the CLK_Ctl
MSR. If the Northbridge needs to probe the processor during
the Stop Grant state while the system bus is disconnected, it
10
Power Management
Chapter 4
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
must first connect the system bus. Connecting the system bus
places the processor into the higher power probe state. After
the Northbridge has completed all probes of the processor, the
Northbridge must disconnect the AMD Athlon system bus
again so that the processor can return to the low-power state.
During the Stop Grant states, the processor latches INIT#,
INTR, NMI, SMI#, or a local APIC interrupt message, if they are
asserted.
The Stop Grant state is exited upon the deassertion of
STPCLK# or the assertion of RESET#. When STPCLK# is
deasserted, the processor initiates a connect of the
AMD Athlon system bus if it is disconnected. After the
processor enters the Working state, any pending interrupts are
recognized and serviced and the processor resumes execution
at the instruction boundary where STPCLK# was initially
recognized. If RESET# is sampled asserted during the Stop
Grant state, the processor exits the Stop Grant state and the
reset process begins.
There are two mechanisms for asserting STPCLK#—hardware
and software.
The Southbridge can force STPCLK# assertion for throttling to
protect the processor from exceeding its maximum case
temperature. This is accomplished by asserting the THERM#
input to the Southbridge. Throttling asserts STPCLK# for a
percentage of a predefined throttling period: STPCLK# is
repetitively asserted and deasserted until THERM# is
deasserted.
Software can force the processor into the Stop Grant state by
accessing ACPI-defined registers typically located in the
Southbridge.
The operating system places the processor into the C2 Stop
Grant state by reading the P_LVL2 register in the Southbridge.
If an ACPI Thermal Zone is defined for the processor, the
operating system can initiate throttling with STPCLK# using
the ACPI defined P_CNT register in the Southbridge. The
Northbridge connects the AMD Athlon system bus, and the
processor enters the Probe state to service cache snoops during
Stop Grant for C2 or throttling.
Chapter 4
Power Management
11
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
In C2, probes are allowed, as shown in Figure 3 on page 9
The Stop Grant state is also entered for the S1, Powered On
Suspend, system sleep state based on a write to the SLP_TYP
and SLP_EN fields in the ACPI-defined Power Management 1
control register in the Southbridge. During the S1 Sleep state,
system software ensures no bus master or probe activity occurs.
The Southbridge deasserts STPCLK# and brings the processor
out of the S1 Stop Grant state when any enabled resume event
occurs.
Probe State
The Probe state is entered when the Northbridge connects the
AMD Athlon system bus to probe the processor (for example, to
snoop the processor caches) when the processor is in the Halt or
Stop Grant state. When in the Probe state, the processor
responds to a probe cycle in the same manner as when it is in
the Working state. When the probe has been serviced, the
processor returns to the same state as when it entered the
Probe state (Halt or Stop Grant state). When probe activity is
completed the processor only returns to a low-power state after
the Northbridge disconnects the AMD Athlon system bus again.
4.2
Connect and Disconnect Protocol
Significant power savings of the processor only occur if the
processor is disconnected from the system bus by the
Northbridge while in the Halt or Stop Grant state. The
Northbridge can optionally initiate a bus disconnect upon the
receipt of a Halt or Stop Grant special cycle. The option of
disconnecting is controlled by an enable bit in the Northbridge.
If the Northbridge requires the processor to service a probe
after the system bus has been disconnected, it must first
initiate a system bus connect.
Connect Protocol
In addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD Athlon system bus connect
protocol includes the CONNECT, PROCRDY, and CLKFWDRST
signals and a Connect special cycle.
AMD Athlon system bus disconnects are initiated by the
Northbridge in response to the receipt of a Halt or Stop Grant.
Reconnect is initiated by the processor in response to an
12
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
interrupt for Halt or STPCLK# deassertion. Reconnect is
initiated by the Northbridge to probe the processor.
The Northbridge contains BIOS programmable registers to
enable the system bus disconnect in response to Halt and Stop
Grant special cycles. When the Northbridge receives the Halt or
Stop Grant special cycle from the processor and, if there are no
outstanding probes or data movements, the Northbridge
deasserts CONNECT a minimum of eight SYSCLK periods after
the last command sent to the processor. The processor detects
the deassertion of CONNECT on a rising edge of SYSCLK and
deasserts PROCRDY to the Northbridge. In return, the
Northbridge asserts CLKFWDRST in anticipation of
reestablishing a connection at some later point.
Note: The Northbridge must disconnect the processor from the
AMD Athlon system bus before issuing the Stop Grant
special cycle to the PCI bus or passing the Stop Grant special
cycle to the Southbridge for systems that connect to the
Southbridge with HyperTransport™ technology.
This note applies to current chipset implementation—
alternate chipset implementations that do not require this
are possible.
Note: In response to Halt special cycles, the Northbridge passes the
Halt special cycle to the PCI bus or Southbridge
immediately.
The processor can receive an interrupt after it sends a Halt
special cycle, or STPCLK# deassertion after it sends a Stop
Grant special cycle to the Northbridge but before the
disconnect actually occurs. In this case, the processor sends the
Connect special cycle to the Northbridge, rather than
continuing with the disconnect sequence. In response to the
Connect special cycle, the Northbridge cancels the disconnect
request.
The system is required to assert the CONNECT signal before
returning the C-bit for the connect special cycle (assuming
CONNECT has been deasserted).
For more information, see the AMD Athlon™ and AMD Duron™
System Bus Specification, order# 21902 for the definition of the
C-bit and the Connect special cycle.
Chapter 4
Power Management
13
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
the Stop Grant state and the AMD Athlon system bus
disconnected.
STPCLK#
AMD Athlon™
System Bus
Stop Grant
CONNECT
PROCRDY
CLKFWDRST
PCI Bus
Stop Grant
Figure 4. AMD Athlon™ System Bus Disconnect Sequence in the Stop Grant State
An example of the AMD Athlon system bus disconnect
sequence is as follows:
1. The peripheral controller (Southbridge) asserts STPCLK#
to place the processor in the Stop Grant state.
2. When the processor recognizes STPCLK# asserted, it enters
the Stop Grant state and then issues a Stop Grant special
cycle.
3. When the special cycle is received by the Northbridge, it
deasserts CONNECT, assuming no probes are pending,
initiating a bus disconnect to the processor.
4. The processor responds to the Northbridge by deasserting
PROCRDY.
5. The Northbridge asserts CLKFWDRST to complete the bus
disconnect sequence.
6. After the processor is disconnected from the bus, the
processor enters a low-power state. The Northbridge passes
the Stop Grant special cycle along to the Southbridge.
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Power Management
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Figure 5 shows the signal sequence of events that takes the
processor out of the Stop Grant state, connects the processor to
the AMD Athlon system bus, and puts the processor into the
Working state.
Figure 5. Exiting the Stop Grant State and Bus Connect Sequence
The following sequence of events removes the processor from
the Stop Grant state and connects it to the system bus:
1. The Southbridge deasserts STPCLK#, informing the
processor of a wake event.
2. When the processor recognizes STPCLK# deassertion, it
exits the low-power state and asserts PROCRDY, notifying
the Northbridge to connect to the bus.
3. The Northbridge asserts CONNECT.
4. The Northbridge deasserts CLKFWDRST, synchronizing the
forwarded clocks between the processor and the
Northbridge.
5. The processor issues a Connect special cycle on the system
bus and resumes operating system and application code
execution.
Chapter 4
Power Management
15
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Connect State
Diagram
and processor connect state diagrams, respectively.
.
Condition
Action
1
2
3
4
5
6
7
A disconnect is requested and probes are still pending.
A disconnect is requested and no probes are pending.
A Connect special cycle from the processor.
No probes are pending.
Deassert CONNECT eight SYSCLK periods
after last SysDC sent.
A
B
C
D
Assert CLKFWDRST.
Assert CONNECT.
Deassert CLKFWDRST.
PROCRDY is deasserted.
A probe needs service.
PROCRDY is asserted.
Three SYSCLK periods after CLKFWDRST is deasserted.
Although reconnected to the system interface, the
Northbridge must not issue any non-NOP SysDC
commands for a minimum of four SYSCLK periods after
deasserting CLKFWDRST.
8
Figure 6. Northbridge Connect State Diagram
16 Power Management
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31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Connect
6/B
1
2/B
Connect
Pending 2
Disconnect
Pending
5
Connect
Pending 1
3/A
Disconnect
4/C
Condition
Action
CONNECT is deasserted by the Northbridge (for a
previously sent Halt or Stop Grant special cycle).
A
B
CLKFWDRST is asserted by the Northbridge.
Issue a Connect special cycle.*
1
Processor receives a wake-up event and must cancel
the disconnect request.
Return internal clocks to full speed and assert
PROCRDY.
2
3
4
5
6
C
Deassert PROCRDY and slow down internal clocks.
Note:
*
The Connect special cycle is only issued after a
processor wake-up event (interrupt or STPCLK#
deassertion) occurs. If the AMD Athlon™ system
bus is connected so the Northbridge can probe the
processor, a Connect special cycle is not issued at
that time (it is only issued after a subsequent
processor wake-up event).
Processor wake-up event or CONNECT asserted by
Northbridge.
CLKFWDRST is deasserted by the Northbridge.
Forward clocks start three SYSCLK periods after
CLKFWDRST is deasserted.
Figure 7. Processor Connect State Diagram
Chapter 4
Power Management
17
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
4.3
Clock Control
The processor implements a Clock Control (CLK_Ctl) MSR
(address C001_001Bh) that determines the internal clock
divisor when the AMD Athlon system bus is disconnected.
Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.
18
Power Management
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31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
5
CPUID Support
AMD Sempron™ processor model 10 version and feature set
recognition can be performed through the use of the CPUID
instruction, that provides complete information about the
processor—vendor, type, name, etc., and its capabilities.
Software can make use of this information to accurately tune
the system for maximum performance and benefit to users.
For information on the use of the CPUID instruction see the
following document:
■
AMD Processor Recognition Application Note, order# 20734
Chapter 5
CPUID Support
19
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
20
CPUID Support
Chapter 5
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
6
333 FSB AMD Sempron™ Processor Model 10 with
256K L2 Cache Specifications
This chapter describes the electrical specifications that are
unique to the advanced 333 front-side bus (FSB)
AMD Sempron™ Processor Model 10 with 256K L2 cache.
6.1
Electrical and Thermal Specifications for the AMD Sempron™
Processor Model 10 with 256K L2 Cache
Table 1 shows the electrical and thermal specifications in the
C0 working state and the S1 Stop Grant state for this processor.
Table 1. Electrical and Thermal Specifications for the AMD Sempron™ Processor Model 10 with 256K
L2 Cache
I
(Processor Current)
CC
V
5
CC_CORE
(Core
Thermal Power
Frequency in MHz
(Model Number)
Maximum Die
Temperature
1, 2, 3, 4
Working State C0
Stop Grant S1
Voltage)
Maximum Typical Maximum Typical Maximum Typical
1500 (2200+)
1.60 V
38.75 A
30.9 A
8.10 A
4.94 A
62.0 W
49.4 W
90°C
2000 (2800+)
Notes:
2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the
process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified
current.
3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant
disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of
2003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and
AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.
4. The Stop Grant current consumption is characterized at 50°C and not tested.
5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or
instruction sequences under normal system operation at nominal VCC_CORE . Thermal solutions must monitor the temperature of
the processor to prevent the processor from exceeding its maximum die temperature.
Chapter 6
333 FSB AMD Sempron™ Processor Model 10 with 256K L2 Cache Specifications
21
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
6.2
333 FSB AMD Sempron™ Processor Model 10 SYSCLK and
SYSCLK# AC Characteristics
Table 2 shows the SYSCLK/SYSCLK# differential clock AC
characteristics of this processor.
Table 2. 333 FSB SYSCLK and SYSCLK# AC Characteristics
Symbol
Parameter Description
Clock Frequency
Minimum
Maximum
Units
Notes
50
30%
6
166
MHz
1
Duty Cycle
70%
t
Period
ns
ns
ns
ns
ns
ps
2, 3
1
t
High Time
Low Time
Fall Time
1.0
1.0
2
t
3
t
2
4
t
Rise Time
Period Stability
2
5
300
Notes:
1. The AMD Athlon™ system bus operates at twice this clock frequency.
2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL
to track the jitter. The –20dB attenuation point, as measured into a 20- or 30-pF load must be less than 500 kHz.
3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread
spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.
AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a
maximum rate of 100 kHz.
Figure 8 shows a sample waveform of the SYSCLK signal.
t
2
V
V
Threshold-AC
CROSS
t
3
t
t
4
5
t
1
Figure 8. SYSCLK Waveform
22 333 FSB AMD Sempron™ Processor Model 10 with 256K L2 Cache Specifications
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31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
6.3
333 FSB AMD Athlon™ System Bus AC Characteristics
The AC characteristics of the AMD Athlon system bus of this
based on the source or destination of the signals involved.
Table 3. 333 FSB AMD Athlon™ System Bus AC Characteristics
Group
Symbol
Parameter
Output Rise Slew Rate
Output Fall Slew Rate
Min
1
Max
Units Notes
T
T
3
3
V/ns
V/ns
1
1
RISE
FALL
All Signals
1
Output skew with respect to a
different clock edge
T
–
770
ps
2
SKEW-DIFFEDGE
T
T
Input Data Setup Time
Input Data Hold Time
Capacitance on input clocks
Capacitance on output clocks
RSTCLK to Output Valid
Setup to RSTCLK
300
300
4
ps
ps
pF
pF
ps
ps
ps
3
3
SU
Forward
Clocks
HD
C
C
T
25
12
IN
4
OUT
800
500
500
2000
4, 5
4, 6
4, 6
VAL
SU
T
T
Sync
Hold from RSTCLK
HD
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.
5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of
RSTCLK.
Chapter 6
333 FSB AMD Sempron™ Processor Model 10 with 256K L2 Cache Specifications
23
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
6.4
333 FSB AMD Athlon™ System Bus DC Characteristics
Table 4 shows the DC characteristics of the AMD Athlon
system bus for this processor.
Table 4. 333 FSB AMD Athlon™ System Bus DC Characteristics
Symbol
Parameter
Condition
Min
(0.5 x V
Max
) (0.5 x V
Units Notes
)
CC_CORE
CC_CORE
V
I
DC Input Reference Voltage
mV
1
REF
–50
+50
V
V
Tristate Leakage Pullup
V
V
= V Nominal
–100
µA
µA
mV
mV
VREF_LEAK_P
VREF_LEAK_N
REF
IN
IN
REF
I
Tristate Leakage Pulldown
= V Nominal
100
REF
REF
V
V
V
+200
V
+500
CC_CORE
Input High Voltage
Input Low Voltage
IH
IL
REF
V
–200
–500
–1
REF
V
= VSS
IN
I
Tristate Leakage Pullup
mA
mA
LEAK_P
LEAK_N
(Ground)
= V
V
IN
CC_CORE
I
Tristate Leakage Pulldown
1
7
Nominal
C
R
Input Pin Capacitance
4
pF
Ω
Ω
Ω
IN
0.90 x R
40
1.1 x R
setN,P
Output Resistance
2
2
2
ON
setN,P
R
R
Impedance Set Point, P Channel
Impedance Set Point, N Channel
70
70
setP
setN
40
Notes:
1. VREF is nominally set to 50% of VCC_CORE with actual values that are specific to motherboard design implementation. VREF must be
created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the 50 mV specification listed
above.
2. Measured at VCC_CORE / 2.
24
333 FSB AMD Sempron™ Processor Model 10 with 256K L2 Cache Specifications
Chapter 6
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
7
Electrical Data
This chapter describes the electrical characteristics that apply
to all desktop AMD Sempron™ processors model 10 with 256K
L2 cache.
7.1
Conventions
The conventions used in this chapter are as follows:
■
Current specified as being sourced by the processor is
negative.
■
Current specified as being sunk by the processor is positive.
7.2
Interface Signal Groupings
The electrical data in this chapter is presented separately for
each signal group.
Table 5 defines each group and the signals contained in each
group.
Table 5. Interface Signal Groupings
Signal Group
Signals
Notes
VID[4:0], VCCA, V
COREFB#
, COREFB,
CC_CORE
Power
Frequency
FID[3:0]
SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN#
System Clocks and RSTCLK/RSTCLK#), PLLBYPASSCLK#,
PLLBYPASSCLK
SADDIN[14:2]#, SADDOUT[14:2]#,
AMD Athlon™ SDATAINVAL#, SDATAOUTVAL#,
System Bus
SDATA[63:0]#, SDATAINCLK[3:0]#,
SDATAOUTCLK[3:0]#, CLKFWDRST,
PROCRDY, CONNECT
Chapter 7
Electrical Data
25
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 5. Interface Signal Groupings (continued)
Signal Group
Signals
Notes
Southbridge
FERR, IGNNE#, STPCLK#, FLUSH#
JTAG
Test
TMS, TCK, TRST#, TDI, TDO
PLLBYPASS#, PLLTEST#, PLLMON1,
PLLMON2, SCANCLK1, SCANCLK2,
SCANSHIFTEN, SCANINTEVAL, ANALOG
Miscellaneous DBREQ#, DBRDY, PWROK
APIC
PICD[1:0]#, PICCLK
Thermal
THERMDA, THERMDC
7.3
Voltage Identification (VID[4:0])
Table 6 shows the VID[4:0] DC Characteristics. For more
information on VID[4:0] DC Characteristics, see “VID[4:0]
Table 6. VID[4:0] DC Characteristics
Parameter
Description
Output Current Low
Output High Voltage
Min
6 mA
–
Max
I
OL
V
5.25 V *
OH
Note:
*
The VID pins are either open circuit or pulled to ground. It is recommended that these pins
are not pulled above 5.25 V, which is 5.0 V + 5%.
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Electrical Data
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
7.4
Frequency Identification (FID[3:0])
Table 7 shows the FID[3:0] DC characteristics. For more
Table 7. FID[3:0] DC Characteristics
Parameter
Description
Output Current Low
Min
Max
I
6 mA
OL
1
2.625 V
V
Output High Voltage
–
OH
2
| V – V
| ≤ 1.60 V
OH
CC_CORE
Note:
1. The FID pins must not be pulled above 2.625 V, which is equal to 2.5 V plus a maximum of five percent.
2. Refer to “VCC_2.5V Generation Circuit” found in the section, “Motherboard Required Circuits,” of the AMD Athlon™ Processor-
Based Motherboard Design Guide, order# 24363.
7.5
VCCA AC and DC Characteristics
Table 8 shows the AC and DC characteristics for VCCA. For
Table 8. VCCA AC and DC Characteristics
Symbol
Parameter
Min
2.25
0
Nominal
Max
Units
Notes
2.75
V
–
1
2
V
VCCA Pin Voltage
VCCA Pin Current
2.5
VCCA
| V
– V
| ≤ 1.60 V
CC_CORE
VCCA
I
50
mA/GHz
3
VCCA
Notes:
1. Minimum and Maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted.
2. For more information, refer to the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.
3. Measured at 2.5 V.
7.6
Decoupling
See the AMD Athlon™ Processor-Based Motherboard Design
Guide, order# 24363, or contact your local AMD office for
information about the decoupling required on the motherboard
for use with the AMD Sempron processor model 10.
Chapter 7
Electrical Data
27
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
7.7
VCC_CORE Characteristics
Table 9 shows the AC and DC characteristics for V
. See
CC_CORE
Figure 9 on page 29 for a graphical representation of the
V
waveform.
CC_CORE
Table 9.
V
AC and DC Characteristics
Parameter
CC_CORE
Symbol
Limit in Working State
Units
*
*
V
V
V
V
t
Maximum static voltage above V
Maximum static voltage below V
Maximum excursion above V
Maximum excursion below V
50
mV
CC_CORE_DC_MAX
CC_CORE_DC_MIN
CC_CORE_AC_MAX
CC_CORE_AC_MIN
CC_CORE_NOM
–50
150
mV
mV
CC_CORE_NOM
*
CC_CORE_NOM
*
–100
10
mV
µs
µs
CC_CORE_NOM
Maximum excursion time for AC transients
Negative excursion time for AC transients
MAX_AC
MIN_AC
t
5
Note:
* All voltage measurements are taken differentially at the COREFB/COREFB# pins.
28
Electrical Data
Chapter 7
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
)
CC_CORE
waveform response to perturbation. The t
(negative AC
MIN_AC
transient excursion time) and t
(positive AC transient
MAX_AC
excursion time) represent the maximum allowable time below
or above the DC tolerance thresholds.
t
max_AC
V
CC_CORE_AC_MAX
V
CC_CORE_DC_MAX
V
CC_CORE_NOM
V
CC_CORE_DC_MIN
V
CC_CORE_AC_MIN
t
min_AC
I
I
CORE_MAX
dI /dt
CORE_MIN
Figure 9. V
Voltage Waveform
CC_CORE
Chapter 7
Electrical Data
29
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
7.8
Absolute Ratings
The AMD Sempron processor model 10 should not be subjected
to conditions exceeding the absolute ratings, as such conditions
can adversely affect long-term reliability or result in functional
damage.
Table 10 lists the maximum absolute ratings of operation for the
AMD Sempron processor model 10.
Table 10. Absolute Ratings
Parameter
Description
Min
Max
Max + 0.5 V
CC_CORE
V
V
Processor core voltage supply
–0.5 V
–0.5 V
–0.5 V
CC_CORE
VCCA
Processor PLL voltage supply
Voltage on any signal pin
VCCA Max + 0.5 V
V
V
Max + 0.5 V
PIN
CC_CORE
T
Storage temperature of processor
–40ºC
100ºC
STORAGE
30
Electrical Data
Chapter 7
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
7.9
SYSCLK and SYSCLK# DC Characteristics
Table 11 shows the DC characteristics of the SYSCLK and
SYSCLK# differential clocks. The SYSCLK signal represents
CLKIN and RSTCLK tied together while the SYSCLK# signal
represents CLKIN# and RSTCLK# tied together. For more
information about SYSCLK and SYSCLK#, see “SYSCLK and
Table 11. SYSCLK and SYSCLK# DC Characteristics
Symbol
Description
Min
Max
Units
Crossing before transition is detected (DC)
400
mV
V
Threshold-DC
Crossing before transition is detected (AC)
450
–1
mV
mA
mA
V
Threshold-AC
Leakage current through P-channel pullup to V
I
CC_CORE
LEAK_P
Leakage current through N-channel pulldown to VSS (Ground)
Differential signal crossover
1
I
LEAK_N
VCC_CORE
mV
pF
----------------------- 100
2
V
CROSS
Capacitance *
4
25 *
C
PIN
Note:
*
The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.
SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.
Figure 10 shows the DC characteristics of the SYSCLK and
SYSCLK# signals.
V
V
= 400mV
V
= 450mV
Threshold-AC
CROSS
Threshold-DC
Figure 10. SYSCLK and SYSCLK# Differential Clock Signals
Chapter 7
Electrical Data
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
7.10
General AC and DC Characteristics
Table 12 shows the AMD Sempron processor model 10 AC and
DC characteristics of the Southbridge, JTAG, test, and
miscellaneous pins.
Table 12. General AC and DC Characteristics
Symbol
Parameter Description
Input High Voltage
Condition
Min
Max
Units Notes
(V
/ 2) +
V
V
+
+
CC_CORE
200 mV
CC_CORE
300 mV
V
V
1, 2
1, 2
IH
V
V
V
I
Input Low Voltage
–300
350
mV
mV
mV
mA
IL
V
–
CC_CORE
400
CC_CORE
300
Output High Voltage
Output Low Voltage
Tristate Leakage Pullup
OH
OL
–300
400
V
= VSS
IN
–1
LEAK_P
LEAK_N
(Ground)
V
= V
IN
CC_CORE
I
Tristate Leakage Pulldown
600
–6
µA
Nominal
I
I
Output High Current
Output Low Current
mA
mA
3
3
OH
OL
6
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal VCC_CORE . Scale parameters between VCC_CORE. minimum and VCC_CORE. maximum.
3. IOL and IOH are measured at VOL maximum and VOH minimum, respectively.
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more
information.
32
Electrical Data
Chapter 7
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 12. General AC and DC Characteristics (continued)
Symbol
Parameter Description
Sync Input Setup Time
Condition
Min
2.0
0.0
0.0
20.0
40.0
1.0
Max
Units Notes
T
ns
ps
4, 5
4, 5
5
SU
T
T
T
T
T
T
Sync Input Hold Time
Output Delay with respect to RSTCLK
Input Time to Acquire
Input Time to Reacquire
Signal Rise Time
HD
6.1
ns
DELAY
BIT
ns
7, 8
9–13
6
ns
RPT
RISE
FALL
3.0
3.0
12
V/ns
V/ns
pF
Signal Fall Time
1.0
6
C
T
Pin Capacitance
4
PIN
Time to data valid
100
ns
14
VALID
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal VCC_CORE . Scale parameters between VCC_CORE. minimum and VCC_CORE. maximum.
3. OL and IOH are measured at VOL maximum and VOH minimum, respectively.
I
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more
information.
Chapter 7
Electrical Data
33
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
7.11
Open Drain Test Circuit
Figure 11 is a test circuit that may be used on automated test
equipment (ATE) to test for validity on open-drain pins.
page 32 for timing requirements.
1
V
Termination
50 Ω 3%
Open-Drain Pin
2
I
= Output Current
OL
Notes:
1. V
= 1.2 V for VID and FID pins
= 1.0 V for APIC pins
Termination
Termination
V
2. I = –6 mA for VID and FID pins
OL
I
= –9 mA for APIC pins
OL
Figure 11. General ATE Open-Drain Test Circuit
34
Electrical Data
Chapter 7
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
7.12
Thermal Diode Characteristics
The AMD Sempron processor model 10 provides a diode that
can be used in conjunction with an external temperature sensor
to determine the die temperature of the processor. The diode
anode (THERMDA) and cathode (THERMDC) are available as
For information about thermal design for the AMD Sempron
processor model 10, including layout and airflow
considerations, see the AMD Processor Thermal, Mechanical, and
Chassis Cooling Design Guide, order# 23794, and the cooling
guidelines on http://www.amd.com.
Thermal Diode
Electrical
Characteristics
Table 13 shows the AMD Sempron processor model 10
characteristics of the on-die thermal diode. For information
about calculations for the ideal diode equation and
temperature offset correction, see Appendix A, "Thermal
Diode Calculations," on page 77.
Table 13. Thermal Diode Electrical Characteristics
Parameter
Symbol
Min
Nom
Max
Units
Notes
1
Description
I
Sourcing current
5
300
µA
Lumped ideality
factor
n
1.00000 1.00374 1.00900
2, 3, 4
f, lumped
n
Actual ideality factor
Series Resistance
1.00261
0.93
3, 4
3, 4
f, actual
R
Ω
T
Notes:
1. The sourcing current should always be used in forward bias only.
2. Characterized at 95°C with a forward bias current pair of 10 µA and 100 µA. AMD
recommends using a minimum of two sourcing currents to accurately measure the
temperature of the thermal diode.
3. Not 100% tested. Specified by design and limited characterization.
4. The lumped ideality factor adds the effect of the series resistance term to the actual ideality
factor. The series resistance term indicates the resistance from the pins of the processor to the
on-die thermal diode. The value of the lumped ideality factor depends on the sourcing current
pair used.
Chapter 7
Electrical Data
35
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Thermal Protection
Characterization
The following section describes parameters relating to thermal
protection. The implementation of thermal control circuitry to
control processor temperature is left to the manufacturer to
determine how to implement.
Thermal limits in motherboard design are necessary to protect
the processor from thermal damage. T
is the
SHUTDOWN
temperature for thermal protection circuitry to initiate
shutdown of the processor. T is the maximum time
SD_DELAY
allowed from the detection of the over-temperature condition to
processor shutdown to prevent thermal damage to the
processor.
Systems that do not implement thermal protection circuitry or
that do not react within the time specified by T
can
SD_DELAY
cause thermal damage to the processor during the unlikely
events of fan failure or powering up the processor without a
heat-sink. The processor relies on thermal circuitry on the
motherboard to turn off the regulated core voltage to the
processor in response to a thermal shutdown event.
Thermal protection circuitry reference designs and thermal
solution guidelines are found in the following documents:
AMD Athlon™ Processor-Based Motherboard Design Guide, order#
24363
AMD Thermal, Mechanical, and Chassis Cooling Design Guide,
order# 23794
See http://www.amd.com for more information about thermal
solutions.
36
Electrical Data
Chapter 7
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 14 shows the T
and T
specifications
SD_DELAY
SHUTDOWN
for circuitry in motherboard design necessary for thermal
protection of the processor.
Table 14. Guidelines for Platform Thermal Protection of the Processor
Symbol
Parameter Description
Max Units Notes
T
Thermal diode shutdown temperature for processor protection
125
500
°C
1, 2, 3
1, 3
SHUTDOWN
T
Maximum allowed time from T
detection to processor shutdown
ms
SD_DELAY
SHUTDOWN
Notes:
1. The thermal diode is not 100% tested, it is specified by design and limited characterization.
2. The thermal diode is capable of responding to thermal events of 40°C/s or faster.
3. The AMD Sempron™ processor model 10 provides a thermal diode for measuring die temperature of the processor. The
processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a
thermal shutdown event. Refer to AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363, for thermal
protection circuitry designs.
7.13
APIC Pins AC and DC Characteristics
Table 15 shows the AMD Sempron processor model 10 AC and
DC characteristics of the APIC pins.
Table 15. APIC Pin AC and DC Characteristics
Symbol Parameter Description
Condition
Min
Max
Units Notes
1.7
2.625
V
V
1, 2
3
V
V
V
Input High Voltage
Input Low Voltage
Output High Voltage
IH
V
V
< V
| V – V
| ≤ 1.60 V
CC_CORE
CC_CORE_MAX
IH
CC_CORE
700
–300
mV
V
1
IL
2.625
2
OH
OL
< V
| V – V
| ≤ 1.60 V
V
3
CC_CORE
CC_CORE_MAX
OH
CC_CORE
V
I
Output Low Voltage
–300
–1
400
mV
mA
V
= VSS (Ground)
IN
Tristate Leakage Pullup
LEAK_P
LEAK_N
OL
Tristate Leakage
Pulldown
I
V
= 2.5 V
Max
1
mA
mA
IN
I
V
Output Low Current
9
OL
Notes:
1. Characterized across DC supply voltage range.
2. The 2.625-V value is equal to 2.5 V plus a maximum of five percent.
3. Refer to “VCC_2.5V Generation Circuit” found in the section, “Motherboard Required Circuits,” of the AMD Athlon™ Processor-
Based Motherboard Design Guide, order# 24363.
4. Edge rates indicate the range for characterizing the inputs.
Chapter 7
Electrical Data
37
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 15. APIC Pin AC and DC Characteristics (continued)
Symbol Parameter Description
Condition
Min
1.0
1.0
1
Max
3.0
Units Notes
T
T
T
T
Signal Rise Time
Signal Fall Time
Setup Time
V/ns
V/ns
ns
3
3
RISE
FALL
SU
3.0
Hold Time
1
ns
HD
C
Pin Capacitance
4
12
pF
PIN
Notes:
1. Characterized across DC supply voltage range.
2. The 2.625-V value is equal to 2.5 V plus a maximum of five percent.
3. Refer to “VCC_2.5V Generation Circuit” found in the section, “Motherboard Required Circuits,” of the AMD Athlon™ Processor-
Based Motherboard Design Guide, order# 24363.
4. Edge rates indicate the range for characterizing the inputs.
38
Electrical Data
Chapter 7
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
8
Signal and Power-Up Requirements
The AMD Sempron™ processor model 10 is designed to provide
functional operation if the voltage and temperature parameters
are within the limits of normal operating ranges.
8.1
Power-Up Requirements
Signal Sequence and
Timing Description
Figure 12 shows the relationship between key signals in the
system during a power-up sequence. This figure details the
requirements of the processor.
3.3 V Supply
VCCA (2.5 V)
(for PLL)
VCC_CORE
2
(Processor Core)
Warm reset
condition
1
RESET#
6
4
NB_RESET#
5
PWROK
FID[3:0]
8
7
3
System Clock
Figure 12. Signal Relationship Requirements During Power-Up Sequence
Notes: 1. Figure 12 represents several signals generically by using names not necessarily consistent
with any pin lists or schematics.
Chapter 8
Signal and Power-Up Requirements
39
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Power-Up Timing Requirements. The signal timing requirements are
as follows:
1. RESET# must be asserted before PWROK is asserted.
The AMD Sempron processor model 10 does not set the
correct clock multiplier if PWROK is asserted prior to a
RESET# assertion. It is recommended that RESET# be
asserted at least 10 nanoseconds prior to the assertion of
PWROK.
In practice, a Southbridge asserts RESET# milliseconds
before PWROK is asserted.
2. All motherboard voltage planes must be within
specification before PWROK is asserted.
PWROK is an output of the voltage regulation circuit on the
motherboard. PWROK indicates that V
and all
CC_CORE
other voltage planes in the system are within specification.
The motherboard is required to delay PWROK assertion for
a minimum of three milliseconds from the 3.3 V supply
being within specification. This delay ensures that the
system clock (SYSCLK/SYSCLK#) is operating within
specification when PWROK is asserted.
The processor core voltage, V
, must be within
CC_CORE
specification as dictated by the VID[4:0] pins driven by the
processor before PWROK is asserted. Before PWROK
assertion, the AMD Sempron processor is clocked by a ring
oscillator.
The processor PLL is powered by VCCA. The processor PLL
does not lock if VCCA is not high enough for the processor
logic to switch for some period before PWROK is asserted.
VCCA must be within specification at least five
microseconds before PWROK is asserted.
In practice VCCA, V
, and all other voltage planes
CC_CORE
must be within specification for several milliseconds before
PWROK is asserted.
After PWROK is asserted, the processor PLL locks to its
operational frequency.
3. The system clock (SYSCLK/SYSCLK#) must be running
before PWROK is asserted.
When PWROK is asserted, the processor switches from
driving the internal processor clock grid from the ring
oscillator to driving from the PLL. The reference system
40
Signal and Power-Up Requirements
Chapter 8
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
clock must be valid at this time. The system clocks are
designed to be running after 3.3 V has been within
specification for three milliseconds.
4. PWROK assertion to deassertion of RESET#
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock with
a less than 1 ns phase error. The processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
between PWROK assertion to the deassertion of RESET# be
at least 1.0 milliseconds. Southbridges enforce a delay of
1.5 to 2.0 milliseconds between PWRGD (Southbridge
version of PWROK) assertion and NB_RESET# deassertion.
5. PWROK must be monotonic and meet the timing
switch between the ring oscillator and the PLL after the
initial assertion of PWROK.
6. NB_RESET# must be asserted (causing CONNECT to also
assert) before RESET# is deasserted. In practice all
Southbridges enforce this requirement.
If NB_RESET# does not assert until after RESET# has
deasserted, the processor misinterprets the CONNECT
assertion (due to NB_RESET# being asserted) as the
beginning of the SIP transfer. There must be sufficient
overlap in the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is deasserted.
7. The FID[3:0] signals are valid within 100 ns after PWROK is
asserted. The chipset must not sample the FID[3:0] signals
until they become valid. Refer to the AMD Athlon™
Processor-Based Motherboard Design Guide, order# 24363, for
the specific implementation and additional circuitry
required.
8. The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the AMD Athlon™ Processor-
Based Motherboard Design Guide, order# 24363, for the
specific implementation and additional circuitry required.
Chapter 8
Signal and Power-Up Requirements
41
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Clock Multiplier
Selection (FID[3:0])
The chipset samples the FID[3:0] signals in a chipset-specific
manner from the processor and uses this information to
determine the correct serial initialization packet (SIP). The
chipset then sends the SIP information to the processor for
configuration of the AMD Athlon system bus for the clock
multiplier that determines the processor frequency indicated
by the FID[3:0] code. The SIP is sent to the processor using the
SIP protocol. This protocol uses the PROCRDY, CONNECT, and
CLKFWDRST signals, that are synchronous to SYSCLK.
For more information about FID[3:0], see “FID[3:0] Pins” on
Serial Initialization Packet (SIP) Protocol. Refer to AMD Athlon™ and
AMD Duron™ System Bus Specification, order# 21902 for details
of the SIP protocol.
8.2
Processor Warm Reset Requirements
Northbridge Reset
Pins
RESET# cannot be asserted to the processor without also being
asserted to the Northbridge. RESET# to the Northbridge is the
same as PCI RESET#. The minimum assertion for PCI RESET#
is one millisecond. Southbridges enforce a minimum assertion
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0
milliseconds.
42
Signal and Power-Up Requirements
Chapter 8
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
9
Mechanical Data
The AMD Sempron™ processor model 10 connects to
themotherboard through a Pin Grid Array (PGA) socket named
Socket A. This processor utilizes the Organic Pin Grid Array
(OPGA) package type described in this chapter. For more
information, see the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
9.1
Die Loading
The processor die on the OPGA package is exposed at the top of
the package. This feature facilitates heat transfer from the die
to an approved heat sink. Any heat sink design should avoid
loads on corners and edges of die. The OPGA package has
compliant pads that serve to bring surfaces in planar contact.
Tool-assisted zero insertion force sockets should be designed so
that no load is placed on the ceramic substrate of the package.
Table 16 shows the mechanical loading specifications for the
processor die. It is critical that the mechanical loading of the
Table 16. Mechanical Loading
Location
Die Surface
Dynamic (MAX)
Static (MAX)
Units
lbf
Note
100
10
30
10
1
2
Die Edge
lbf
Notes:
1. Load specified for coplanar contact to die surface.
2. Load defined for a surface at no more than a two-degree angle of inclination to die surface.
Chapter 9
Mechanical Data
43
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
9.2
AMD Sempron™ Processor Model 10 Part Number 27488 OPGA
Package Dimensions
Table 17 shows the part number 27488 OPGA package
dimensions in millimeters assigned to the letters and symbols
Table 17. Dimensions for the AMD Sempron™ Processor Model 10 Part
Number 27488 OPGA Package
Minimum
Maximum
Minimum
Dimension Dimension
Maximum
Letter or
Symbol
Letter or
Symbol
1
1
1
1
Dimension Dimension
49.27 49.78
45.72 BSC
D/E
D1/E1
D2
D3
D4
D5
D6
D7
D8
D9
E2
E9
G/H
A
1.66
–
1.96
4.50
7.42 REF
1.942 REF
3.30
10.78
10.78
8.13
3.60
11.33
11.33
8.68
A1
A2
A3
A4
φP
φb
φb1
S
1.00
0.80
0.116
–
1.20
0.88
–
1.90
6.60
0.50
12.33
3.05
12.88
3.35
–
0.43
12.71
13.26
1.40 REF
13.61 REF
1.435
3.05
2.375
3.31
E3
2.35
7.87
2.65
8.42
L
E4
M
37
E5
7.87
8.42
N
453
E6
11.41
11.41
13.28
11.96
11.96
13.83
e
1.27 BSC
2.54 BSC
E7
e1
2
E8
11.0 g REF
Mass
Note:
1. Dimensions are given in millimeters.
2. The mass consists of the completed package, including processor, surface mounted parts and
pins.
44
Mechanical Data
Chapter 9
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
9.3
AMD Sempron™ Processor Model 10 Part Number 27493 OPGA
Package Dimensions
Table 18 shows the part number 27493 OPGA package
dimensions in millimeters assigned to the letters and symbols
Table 18. Dimensions for the AMD Sempron™ Processor Model 10 Part
Number 27493 OPGA Package
Minimum
Maximum
Minimum
Dimension Dimension
Maximum
Letter or
Symbol
Letter or
Symbol
1
1
1
1
Dimension Dimension
49.27 49.78
45.72 BSC
D/E
D1/E1
D2
D3
D4
D5
D6
D7
D8
D9
E2
G/H
A
–
4.50
1.917 REF
7.42 REF
A1
A2
A3
A4
φP
φb
φb1
S
0.977
0.80
0.116
–
1.177
0.88
–
3.30
10.78
10.78
8.13
3.60
11.33
11.33
8.68
1.90
6.60
0.50
–
12.33
3.05
12.88
3.35
0.43
1.40 REF
12.71
13.26
1.435
3.05
2.375
3.31
13.61 REF
L
E3
2.35
7.87
2.65
8.42
8.42
11.96
13.83
1.96
M
37
E4
N
453
E5
7.87
e
1.27 BSC
2.54 BSC
E6
11.41
13.28
1.66
e1
2
E8
11.0 g REF
Mass
E9
Note:
1. Dimensions are given in millimeters.
2. The mass consists of the completed package, including processor, surface mounted parts and
pins.
46
Mechanical Data
Chapter 9
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
48
Mechanical Data
Chapter 9
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
10
Pin Descriptions
This chapter includes pin diagrams of the organic pin grid array
(OPGA) for the AMD Sempron™ processor model 10, a listing
of pin name abbreviations, and a cross-referenced listing of pin
locations to signal names.
10.1
Pin Diagram and Pin Name Abbreviations
Figure 15 on page 50 shows the staggered Pin Grid Array (PGA)
for the AMD Sempron™ processor model 10. Because some of
the pin names are too long to fit in the grid, they are
order by pin name, along with the abbreviation where
necessary.
Chapter 10
Pin Descriptions
49
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 19. Pin Name Abbreviations
Abbreviation
Full Name
A20M#
Pin
AE1
Abbreviation
Full Name
Pin
AA7
KEY
KEY
KEY
KEY
KEY
KEY
KEY
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AMD
AH6
AJ13
AJ21
AN17
AL17
AL23
AG11
AG13
AK6
AA1
AA3
AG1
W1
AG7
AG9
AG15
AG17
AG27
AG29
A19
A31
C13
E25
E33
F8
ANLOG
ANALOG
CLKFWDRST
CLKIN
CLKFR
CNNCT
CPR#
CLKIN#
CONNECT
COREFB
COREFB#
CPU_PRESENCE#
DBRDY
DBREQ#
FERR
FID[0]
F30
G11
G13
G19
G21
G27
G29
G31
H6
FID[1]
W3
FID[2]
Y1
FID[3]
Y3
FLUSH#
FSB_Sense[0]
FSB_Sense[1]
IGNNE#
INIT#
AL3
AG31
AH30
AJ1
FSB0
FSB1
AJ3
INTR
AL1
AL21
AN21
G7
H8
K7CO
K7CLKOUT
K7CLKOUT#
KEY
H10
H28
H30
H32
J5
K7CO#
KEY
G9
KEY
G15
G17
G23
G25
N7
KEY
J31
KEY
K8
KEY
K30
L31
KEY
KEY
Q7
L35
N31
KEY
Y7
52
Pin Descriptions
Chapter 10
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 19. Pin Name Abbreviations (continued)
Abbreviation
Full Name
Pin
Q31
Abbreviation
Full Name
Pin
AJ19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NMI
S31
AJ27
AK8
U31
U37
W7
AL7
AL9
W31
Y5
AL11
AL25
AL27
AM8
AN7
AN9
AN11
AN25
AN27
AN3
N1
Y31
Y33
AA5
AA31
AC7
AC31
AD8
AD30
AE7
PICCLK
AE31
AF6
PICD#0
PICD[0]#
N3
PICD#1
PLBYP#
PLBYC
PICD[1]#
N5
AF8
PLLBYPASS#
PLLBYPASSCLK
PLLBYPASSCLK#
PLLMON1
PLLMON2
PLLTEST#
AJ25
AN15
AL15
AN13
AL13
AC3
AF10
AF28
AF30
AF32
AG5
AG19
AG21
AG23
AG25
AH8
AJ7
PLBYC#
PLMN1
PLMN2
PLTST#
PRCRDY
PROCREADY
PWROK
AN23
AE3
RESET#
AG3
AN19
AL19
AJ29
AL29
AG33
AJ37
AL35
RCLK
RSTCLK
RCLK#
SAI#0
SAI#1
SAI#2
SAI#3
SAI#4
RSTCLK#
SADDIN[0]#
SADDIN[1]#
SADDIN[2]#
SADDIN[3]#
SADDIN[4]#
AJ9
AJ11
AJ15
AJ17
Chapter 10
Pin Descriptions
53
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 19. Pin Name Abbreviations (continued)
Abbreviation
SAI#5
Full Name
SADDIN[5]#
Pin
AE33
Abbreviation
SD#3
Full Name
Pin
Y35
SDATA[3]#
SDATA[4]#
SDATA[5]#
SDATA[6]#
SDATA[7]#
SDATA[8]#
SDATA[9]#
SDATA[10]#
SDATA[11]#
SDATA[12]#
SDATA[13]#
SDATA[14]#
SDATA[15]#
SDATA[16]#
SDATA[17]#
SDATA[18]#
SDATA[19]#
SDATA[20]#
SDATA[21]#
SDATA[22]#
SDATA[23]#
SDATA[24]#
SDATA[25]#
SDATA[26]#
SDATA[27]#
SDATA[28]#
SDATA[29]#
SDATA[30]#
SDATA[31]#
SDATA[32]#
SDATA[33]#
SDATA[34]#
SDATA[35]#
SDATA[36]#
SAI#6
SADDIN[6]#
AJ35
AG37
AL33
AN37
AL37
AG35
AN29
AN35
AN31
AJ33
J1
SD#4
U35
U33
S37
SAI#7
SADDIN[7]#
SD#5
SAI#8
SADDIN[8]#
SD#6
SAI#9
SADDIN[9]#
SD#7
S33
SAI#10
SAI#11
SAI#12
SAI#13
SAI#14
SAIC#
SADDIN[10]#
SADDIN[11]#
SADDIN[12]#
SADDIN[13]#
SADDIN[14]#
SADDINCLK#
SADDOUT[0]#
SADDOUT[1]#
SADDOUT[2]#
SADDOUT[3]#
SADDOUT[4]#
SADDOUT[5]#
SADDOUT[6]#
SADDOUT[7]#
SADDOUT[8]#
SADDOUT[9]#
SADDOUT[10]#
SADDOUT[11]#
SADDOUT[12]#
SADDOUT[13]#
SADDOUT[14]#
SADDOUTCLK#
SCANCLK1
SD#8
AA33
AE37
AC33
AC37
Y37
SD#9
SD#10
SD#11
SD#12
SD#13
SD#14
SD#15
SD#16
SD#17
SD#18
SD#19
SD#20
SD#21
SD#22
SD#23
SD#24
SD#25
SD#26
SD#27
SD#28
SD#29
SD#30
SD#31
SD#32
SD#33
SD#34
SD#35
SD#36
AA37
AC35
S35
SAO#0
SAO#1
SAO#2
SAO#3
SAO#4
SAO#5
SAO#6
SAO#7
SAO#8
SAO#9
SAO#10
SAO#11
SAO#12
SAO#13
SAO#14
SAOC#
SCNCK1
SCNCK2
SCNINV
SCNSN
SD#0
J3
C7
Q37
Q35
N37
J33
A7
E5
A5
E7
G33
G37
E37
C1
C5
C3
G35
Q33
N33
L33
G1
E1
A3
G5
N35
L37
G3
E3
J37
S1
A37
E35
SCANCLK2
S5
SCANINTEVAL
SCANSHIFTEN
SDATA[0]#
S3
E31
Q5
E29
AA35
W37
W35
A27
A25
E21
SD#1
SDATA[1]#
SD#2
SDATA[2]#
54
Pin Descriptions
Chapter 10
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 19. Pin Name Abbreviations (continued)
Abbreviation
SD#37
Full Name
SDATA[37]#
Pin
C23
Abbreviation
SDOC#2
Full Name
SDATAOUTCLK[2]#
SDATAOUTCLK[3]#
SDATAOUTVALID#
SFILLVALID#
SMI#
Pin
A33
SD#38
SD#39
SD#40
SD#41
SD#42
SD#43
SD#44
SD#45
SD#46
SD#47
SD#48
SD#49
SD#50
SD#51
SD#52
SD#53
SD#54
SD#55
SD#56
SD#57
SD#58
SD#59
SD#60
SD#61
SD#62
SD#63
SDIC#0
SDIC#1
SDIC#2
SDIC#3
SDINV#
SDOC#0
SDOC#1
SDATA[38]#
SDATA[39]#
SDATA[40]#
SDATA[41]#
C27
A23
A35
C35
C33
C31
A29
C29
E23
C25
E17
SDOC#3
SDOV#
SFILLV#
C11
AL31
AJ31
AN5
AC1
Q1
SDATA[42]#
SDATA[43]#
SDATA[44]#
SDATA[45]#
SDATA[46]#
SDATA[47]#
STPC#
STPCLK#
TCK
TDI
U1
TDO
U5
THDA
THDC
THERMDA
THERMDC
TMS
S7
U7
SDATA[48]#
SDATA[49]#
SDATA[50]#
SDATA[51]#
Q3
E13
E11
C15
E9
TRST#
U3
V
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
B4
CC_CORE
V
B8
CC_CORE
V
B12
B16
B20
B24
B28
B32
B36
D2
SDATA[52]#
SDATA[53]#
SDATA[54]#
SDATA[55]#
SDATA[56]#
SDATA[57]#
CC_CORE
V
A13
C9
CC_CORE
V
CC_CORE
V
A9
CC_CORE
V
C21
A21
E19
C19
C17
A11
A17
A15
W33
J35
CC_CORE
V
CC_CORE
V
SDATA[58]#
SDATA[59]#
SDATA[60]#
SDATA[61]#
CC_CORE
V
CC_CORE
V
D4
CC_CORE
V
D8
CC_CORE
V
D12
D16
D20
D24
D28
D32
F12
F16
F20
SDATA[62]#
SDATA[63]#
SDATAINCLK[0]#
SDATAINCLK[1]#
SDATAINCLK[2]#
SDATAINCLK[3]#
SDATAINVALID#
SDATAOUTCLK[0]#
SDATAOUTCLK[1]#
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
E27
E15
AN33
AE35
C37
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
V
CC_CORE
Chapter 10
Pin Descriptions
55
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 19. Pin Name Abbreviations (continued)
Abbreviation
Full Name
Pin
Abbreviation
Full Name
Pin
X30
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F24
F28
F32
F34
F36
H2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
X32
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
X34
X36
Z2
Z4
H4
Z6
H12
H16
H20
H24
K32
K34
K36
M2
M4
M6
M8
P30
P32
P34
P36
R2
Z8
AB30
AB32
AB34
AB36
AD2
AD4
AD6
AF14
AF18
AF22
AF26
AF34
AF36
AH2
AH4
AH10
AH14
AH18
AH22
AH26
AK10
AK14
AK18
AK22
AK26
AK30
R4
R6
R8
T30
T32
T34
T36
V2
V4
V6
V8
56
Pin Descriptions
Chapter 10
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 19. Pin Name Abbreviations (continued)
Abbreviation
Full Name
Pin
AK34
Abbreviation
Full Name
Pin
D22
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CC_CORE
AK36
AJ5
D26
D30
D34
D36
F2
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
CC_CORE
AL5
AM2
AM10
AM14
AM18
AM22
AM26
AM22
AM26
AM30
AM34
AJ23
L1
F4
F6
F10
F14
F18
F22
F26
H14
H18
H22
H26
H34
H36
K2
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VREF_SYS
VSS
L3
L5
L7
J7
K4
VREF_S
W5
K6
B2
M30
M32
M34
M36
P2
VSS
B6
VSS
B10
VSS
B14
VSS
B18
VSS
B22
B26
B30
B34
D6
P4
VSS
P6
VSS
VSS
P8
R30
R32
R34
R36
VSS
VSS
D10
D14
D18
VSS
VSS
Chapter 10
Pin Descriptions
57
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 19. Pin Name Abbreviations (continued)
Table 19. Pin Name Abbreviations (continued)
Abbreviation
Full Name
Pin
Abbreviation
Full Name
Pin
AH12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T2
T4
T6
T8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZN
AH16
AH20
AH24
AH28
AH32
AH34
AH36
AK2
V30
V32
V34
V36
X2
X4
AK4
X6
AK12
AK16
AK20
AK24
AK28
AK32
AM4
X8
Z30
Z32
Z34
Z36
AB2
AB8
AB4
AB6
AD32
AD34
AD36
AF2
AF4
AF12
AF16
AM6
AM12
AM16
AM20
AM24
AM28
AM32
AM36
AC5
ZP
AE5
58
Pin Descriptions
Chapter 10
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
10.2
Pin List
Table 20 on page 60 cross-references Socket A pin location to
signal name.
The “L” (Level) column shows the electrical specification for
this pin. “P” indicates a push-pull mode driven by a single
source. “O” indicates open-drain mode that allows devices to
share the pin.
Note: The AMD Sempron processor supports push-pull drivers. For
The “P” (Port) column indicates if this signal is an input (I),
output (O), or bidirectional (B) signal. The “R” (Reference)
column indicates if this signal should be referenced to VSS (G)
or VCC_CORE (P) planes for the purpose of signal routing with
respect to the current return paths.
Chapter 10
Pin Descriptions
59
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 20. Cross-Reference by Pin Location
Pin
A1
Name
Description
L
-
P
-
R
-
Pin
B24
Name
Description
L
P
R
V
-
-
-
No Pin
CC_CORE
A3
SADDOUT[12]#
SADDOUT[5]#
SADDOUT[3]#
SDATA[55]#
SDATA[61]#
SDATA[53]#
SDATA[63]#
SDATA[62]#
NC Pin
P
P
P
P
P
P
P
P
-
O
O
O
B
B
B
B
B
-
G
G
G
P
P
G
G
G
-
B26
B28
VSS
V
-
-
-
-
-
-
A5
CC_CORE
A7
B30
B32
VSS
V
-
-
-
-
-
-
A9
CC_CORE
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
A33
A35
A37
B2
B34
B36
VSS
V
-
-
-
-
-
-
CC_CORE
C1
SADDOUT[7]#
SADDOUT[9]#
SADDOUT[8]#
SADDOUT[2]#
SDATA[54]#
SDATAOUTCLK[3]#
NC Pin
P
P
P
P
P
P
-
O
O
O
O
B
O
-
G
G
G
G
P
C3
C5
SDATA[57]#
SDATA[39]#
SDATA[35]#
SDATA[34]#
SDATA[44]#
NC Pin
P
P
P
P
P
-
B
B
B
B
B
-
G
G
P
P
G
-
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
D2
G
-
SDATA[51]#
P
P
P
P
P
P
P
P
P
P
P
P
-
B
B
B
B
B
B
B
B
B
B
B
O
-
P
SDATA[60]#
SDATA[59]#
SDATA[56]#
SDATA[37]#
SDATA[47]#
SDATA[38]#
SDATA[45]#
SDATA[43]#
SDATA[42]#
SDATA[41]#
SDATAOUTCLK[1]#
G
G
G
P
SDATAOUTCLK[2]#
SDATA[40]#
SDATA[30]#
VSS
P
P
P
-
O
B
B
-
P
G
P
-
G
G
G
G
G
G
G
-
V
B4
-
-
-
CC_CORE
B6
B8
VSS
-
-
-
-
-
-
V
CC_CORE
B10
B12
VSS
-
-
-
-
-
-
V
CC_CORE
B14
B16
VSS
-
-
-
-
-
-
V
V
CC_CORE
CC_CORE
V
D4
-
-
-
B18
B20
VSS
-
-
-
-
-
-
CC_CORE
V
D6
D8
VSS
-
-
-
-
-
-
CC_CORE
V
B22
VSS
-
-
-
CC_CORE
60
Pin Descriptions
Chapter 10
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 20. Cross-Reference by Pin Location (continued)
Pin
D10
Name
Description
L
-
P
-
R
-
Pin
E33
Name
Description
L
-
P
-
R
-
VSS
V
NC Pin
D12
-
-
-
E35
E37
F2
SDATA[31]#
SDATA[22]#
VSS
P
P
-
B
B
-
P
G
-
CC_CORE
D14
D16
VSS
V
-
-
-
-
-
-
CC_CORE
D18
D20
VSS
V
-
-
-
-
-
-
F4
VSS
-
-
-
F6
VSS
-
-
-
CC_CORE
D22
D24
VSS
V
-
-
-
-
-
-
F8
NC Pin
VSS
-
-
-
F10
F12
-
-
-
CC_CORE
V
-
-
-
D26
D28
VSS
V
-
-
-
-
-
-
CC_CORE
F14
F16
VSS
-
-
-
-
-
-
CC_CORE
V
D30
D32
VSS
V
-
-
-
-
-
-
CC_CORE
F18
F20
VSS
-
-
-
-
-
-
CC_CORE
V
D34
D36
E1
VSS
VSS
-
-
-
-
CC_CORE
-
-
F22
F24
VSS
-
-
-
-
-
-
V
SADDOUT[11]#
SADDOUTCLK#
SADDOUT[4]#
SADDOUT[6]#
SDATA[52]#
SDATA[50]#
SDATA[49]#
SDATAINCLK[3]#
SDATA[48]#
SDATA[58]#
SDATA[36]#
SDATA[46]#
NC Pin
P
P
P
P
P
P
P
P
P
P
P
P
-
O
O
O
O
B
B
B
I
P
G
P
G
P
P
G
G
P
G
P
P
-
CC_CORE
E3
F26
F28
VSS
-
-
-
-
-
-
V
E5
CC_CORE
E7
F30
F32
F34
F36
NC Pin
-
-
-
-
-
-
-
-
-
-
-
-
V
E9
CC_CORE
V
E11
E13
E15
E17
E19
E21
E23
E25
E27
E29
E31
CC_CORE
V
CC_CORE
G1
SADDOUT[10]#
SADDOUT[14]#
SADDOUT[13]#
Key Pin
P
P
P
-
O
O
O
-
P
G
G
-
B
B
B
B
-
G3
G5
G7
G9
Key Pin
-
-
-
G11
G13
G15
G17
NC Pin
-
-
-
SDATAINCLK[2]#
SDATA[33]#
SDATA[32]#
P
P
P
I
G
P
P
NC Pin
-
-
-
B
B
Key Pin
-
-
-
Key Pin
-
-
-
Chapter 10
Pin Descriptions
61
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 20. Cross-Reference by Pin Location(continued)
Pin
G19
Name
Description
L
-
P
-
R
-
Pin
J5
Name
Description
L
-
P
-
R
-
NC Pin
NC Pin
NC Pin
VID[4]
NC Pin
G21
G23
G25
G27
G29
G31
G33
G35
-
-
-
J7
O
-
O
-
-
Key Pin
-
-
-
J31
J33
J35
J37
K2
-
Key Pin
-
-
-
SDATA[19]#
SDATAINCLK[1]#
SDATA[29]#
VSS
P
P
P
-
B
I
G
P
P
-
NC Pin
-
-
-
NC Pin
-
-
-
B
-
NC Pin
-
-
-
SDATA[20]#
SDATA[23]#
P
P
P
-
B
B
B
-
G
G
G
-
K4
VSS
-
-
-
K6
VSS
-
-
-
G37
H2
SDATA[21]#
K8
NC Pin
-
-
-
V
K30
K32
K34
K36
NC Pin
-
-
-
CC_CORE
V
V
H4
-
-
-
-
-
-
CC_CORE
CC_CORE
V
-
-
-
H6
NC Pin
NC Pin
NC Pin
-
-
-
-
-
-
-
-
-
-
-
-
CC_CORE
V
-
-
-
H8
CC_CORE
H10
H12
L1
VID[0]
page 74
page 74
O
O
O
O
-
O
O
O
O
-
-
-
V
L3
VID[1]
CC_CORE
H14
H16
VSS
-
-
-
-
-
-
L5
VID[2]
-
V
L7
VID[3]
-
CC_CORE
H18
H20
VSS
-
-
-
-
-
-
L31
L33
L35
L37
M2
M4
M6
M8
NC Pin
-
V
SDATA[26]#
NC Pin
P
-
B
-
P
-
CC_CORE
H22
H24
VSS
-
-
-
-
-
-
V
SDATA[28]#
P
-
B
-
P
-
CC_CORE
V
H26
H28
H30
H32
H34
H36
J1
VSS
-
-
-
-
-
-
-
-
-
-
-
-
CC_CORE
V
-
-
-
NC Pin
CC_CORE
V
-
-
-
NC Pin
-
-
CC_CORE
V
-
-
-
NC Pin
-
-
CC_CORE
VSS
-
-
M30
M32
M34
M36
VSS
VSS
VSS
VSS
-
-
-
-
-
-
-
-
-
-
-
-
VSS
-
-
SADDOUT[0]#
SADDOUT[1]#
P
P
O
O
J3
62
Pin Descriptions
Chapter 10
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 20. Cross-Reference by Pin Location(continued)
Pin
N1
Name
PICCLK
Description
L
O
O
O
-
P
I
R
-
Pin
R34
Name
Description
L
-
P
-
R
-
VSS
VSS
N3
PICD#[0]
PICD#[1]
Key Pin
NC Pin
B
B
-
-
R36
S1
-
-
-
N5
-
SCANCLK1
SCANINTEVAL
SCANCLK2
THERMDA
NC Pin
page 73
page 73
P
P
P
-
I
-
N7
-
S3
I
-
N31
N33
N35
N37
P2
-
-
-
S5
I
-
SDATA[25]#
SDATA[27]#
SDATA[18]#
VSS
P
P
P
-
B
B
B
-
P
P
G
-
S7
-
-
S31
S33
S35
S37
T2
-
-
-
SDATA[7]#
SDATA[15]#
SDATA[6]#
VSS
P
P
P
-
B
B
B
-
G
P
G
-
P4
VSS
-
-
-
P6
VSS
-
-
-
P8
VSS
-
-
-
T4
VSS
-
-
-
V
P30
P32
P34
P36
-
-
-
T6
VSS
-
-
-
CC_CORE
V
-
-
-
T8
VSS
-
-
-
CC_CORE
V
V
-
-
-
T30
T32
T34
T36
-
-
-
CC_CORE
CC_CORE
V
V
-
-
-
-
-
-
CC_CORE
CC_CORE
V
-
-
-
Q1
Q3
Q5
Q7
Q31
Q33
Q35
Q37
R2
TCK
page 72
page 73
P
P
P
-
I
I
-
-
CC_CORE
V
-
-
-
TMS
CC_CORE
SCANSHIFTEN
Key Pin
I
-
U1
TDI
page 72
page 72
page 72
P
P
P
-
I
I
-
-
-
-
U3
TRST#
NC Pin
-
-
-
U5
TDO
O
-
-
SDATA[24]#
SDATA[17]#
SDATA[16]#
P
P
P
-
B
B
B
-
P
G
G
-
U7
THERMDC
NC Pin
-
U31
U33
U35
U37
V2
-
-
-
SDATA[5]#
SDATA[4]#
NC Pin
P
P
-
B
B
-
G
G
-
V
CC_CORE
V
R4
-
-
-
CC_CORE
V
V
R6
-
-
-
-
-
-
CC_CORE
CC_CORE
V
V
R8
-
-
-
V4
-
-
-
CC_CORE
CC_CORE
V
V6
-
-
-
R30
R32
VSS
VSS
-
-
-
-
-
-
CC_CORE
V
V8
-
-
-
CC_CORE
Chapter 10
Pin Descriptions
63
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 20. Cross-Reference by Pin Location(continued)
Pin
V30
Name
Description
L
-
P
-
R
-
Pin
Z6
Name
Description
L
-
P
-
R
-
V
V
VSS
CC_CORE
CC_CORE
Z8
-
-
-
V32
V34
V36
W1
W3
W5
W7
W31
W33
W35
W37
X2
VSS
-
-
-
VSS
-
-
-
Z30
Z32
Z34
Z36
AA1
AA3
AA5
AA7
VSS
-
-
-
-
-
-
VSS
-
-
-
VSS
FID[0]
FID[1]
page 70
O
O
P
-
O
O
-
-
VSS
-
-
-
-
VSS
-
-
-
VREFSYS
NC Pin
-
DBRDY
DBREQ#
NC
page 69
page 69
P
P
-
O
I
-
-
-
-
NC Pin
-
-
-
-
-
SDATAINCLK[0]#
SDATA[2]#
SDATA[1]#
VSS
P
P
P
-
I
G
G
P
-
Key Pin
-
-
-
B
B
-
AA31 NC Pin
-
-
-
AA33 SDATA[8]#
AA35 SDATA[0]#
AA37 SDATA[13]#
P
P
P
-
B
B
B
-
P
G
G
-
X4
VSS
-
-
-
X6
VSS
-
-
-
AB2
VSS
VSS
VSS
X8
VSS
-
-
-
AB4
-
-
-
V
X30
X32
X34
X36
-
-
-
AB6
-
-
-
CC_CORE
V
-
-
-
AB8
VSS
V
-
-
-
CC_CORE
V
-
-
-
AB30
AB32
AB34
AB36
-
-
-
CC_CORE
CC_CORE
V
V
V
V
-
-
-
-
-
-
CC_CORE
CC_CORE
CC_CORE
CC_CORE
-
-
-
Y1
FID[2]
page 70
O
O
-
O
O
-
-
-
-
-
-
Y3
FID[3]
Y5
NC Pin
-
AC1
AC3
AC5
AC7
STPCLK#
PLLTEST#
ZN
page 72
page 75
P
P
P
-
I
I
-
-
Y7
Key Pin
NC Pin
-
-
-
Y31
Y33
Y35
Y37
Z2
-
-
-
-
-
NC Pin
-
-
-
NC
-
-
SDATA[3]#
SDATA[12]#
P
P
-
B
B
-
G
P
-
AC31 NC Pin
-
-
-
AC33 SDATA[10]#
AC35 SDATA[14]#
AC37 SDATA[11]#
P
P
P
B
B
B
P
G
G
V
CC_CORE
V
Z4
-
-
-
CC_CORE
64
Pin Descriptions
Chapter 10
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 20. Cross-Reference by Pin Location(continued)
Pin
AD2
Name
Description
L
-
P
-
R
-
Pin
Name
Description
L
-
P
-
R
-
V
V
V
AF30 NC Pin
AF32 NC Pin
CC_CORE
AD4
AD6
AD8
-
-
-
-
-
-
CC_CORE
CC_CORE
V
V
-
-
-
AF34
AF36
AG1
AG3
AG5
AG7
AG9
-
-
-
CC_CORE
CC_CORE
-
-
-
NC Pin
-
-
-
-
-
-
AD30 NC Pin
AD32 VSS
AD34 VSS
AD36 VSS
FERR
P
-
O
I
-
-
-
-
-
RESET#
NC Pin
Key Pin
Key Pin
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
I
-
-
-
-
-
-
AE1
AE3
AE5
AE7
A20M#
PWROK
ZP
P
P
P
-
I
-
-
-
I
-
AG11 COREFB
AG13 COREFB#
AG15 Key Pin
AG17 Key Pin
AG19 NC Pin
-
-
page 75
-
-
-
-
NC
-
-
-
-
AE31 NC Pin
-
-
-
-
-
AE33 SADDIN[5]#
AE35 SDATAOUTCLK[0]#
AE37 SDATA[9]#
P
P
P
-
I
G
P
G
-
-
-
O
B
-
AG21 NC Pin
-
-
AG23 NC Pin
-
-
AF2
VSS
AG25 NC Pin
-
-
AF4
VSS
-
-
-
AG27 Key Pin
AG29 Key Pin
AG31 FSB_Sense[0]
AG33 SADDIN[2]#
AG35 SADDIN[11]#
AG37 SADDIN[7]#
-
-
AF6
NC Pin
NC Pin
NC Pin
VSS
-
-
-
-
-
AF8
-
-
-
-
G
G
G
P
-
AF10
AF12
AF14
-
-
-
P
P
P
-
-
-
-
I
V
-
-
-
I
CC_CORE
V
V
AH2
AH4
-
-
AF16
AF18
VSS
-
-
-
-
-
-
CC_CORE
CC_CORE
V
-
-
CC_CORE
AF20 VSS
-
-
-
-
-
-
AH6
AH8
AH10
AMD Pin
NC Pin
-
-
-
-
-
-
-
-
-
V
AF22
CC_CORE
V
AF24 VSS
-
-
-
-
-
-
CC_CORE
V
AF26
AH12 VSS
-
-
-
-
-
-
CC_CORE
V
AH14
AF28 NC Pin
-
-
-
CC_CORE
Chapter 10
Pin Descriptions
65
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 20. Cross-Reference by Pin Location(continued)
Pin
Name
Description
L
-
P
-
R
-
Pin
AK2
Name
Description
L
-
P
-
R
-
AH16 VSS
VSS
VSS
V
AH18
-
-
-
AK4
AK6
AK8
AK10
-
-
-
CC_CORE
AH20 VSS
-
-
-
-
-
-
CPU_PRESENCE#
NC Pin
-
-
-
V
AH22
-
-
-
CC_CORE
V
-
-
-
AH24 VSS
-
-
-
-
-
-
CC_CORE
V
AH26
AK12 VSS
-
-
-
-
-
-
CC_CORE
V
AK14
AH28 VSS
-
-
-
O
-
-
G
-
CC_CORE
AH30 FSB_Sense[1]
AH32 VSS
AK16 VSS
-
-
-
-
-
-
V
AK18
-
CC_CORE
AH34 VSS
-
-
-
AK20 VSS
-
-
-
V
AK22
-
-
-
AH36 VSS
-
-
-
CC_CORE
AJ1
AJ3
AJ5
IGNNE#
INIT#
P
P
-
I
-
AK24 VSS
-
-
-
-
-
-
V
AK26
I
-
CC_CORE
V
-
-
AK28 VSS
-
-
-
-
-
-
CC_CORE
V
AK30
AJ7
NC Pin
page 68
page 73
page 72
-
-
-
-
-
-
-
-
-
I
-
-
CC_CORE
AJ9
NC Pin
AK32 VSS
-
-
-
-
-
-
-
-
-
V
V
AK34
AK36
AJ11
AJ13
AJ15
AJ17
AJ19
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AJ33
AJ35
AJ37
NC Pin
-
-
CC_CORE
CC_CORE
Analog
-
-
NC Pin
-
-
AL1
AL3
AL5
INTR
P
P
-
I
I
-
-
-
-
NC Pin
-
-
FLUSH#
V
NC Pin
-
-
CC_CORE
CLKFWDRST
VCCA
P
-
P
-
AL7
NC Pin
-
-
-
-
-
-
-
I
AL9
NC Pin
PLLBYPASS#
NC Pin
P
-
-
AL11
AL13
AL15
AL17
AL19
AL21
NC Pin
-
-
-
-
I
-
PLLMON2
PLLBYPASSCLK#
CLKIN#
O
P
P
P
P
P
O
I
-
SADDIN[0]#
SFILLVALID#
SADDINCLK#
SADDIN[6]#
SADDIN[3]#
P
P
P
P
P
-
-
I
G
G
P
G
I
P
P
-
I
RSTCLK#
K7CLKOUT
I
I
O
I
I
AL23 CONNECT
P
66
Pin Descriptions
Chapter 10
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 20. Cross-Reference by Pin Location(continued)
Pin
Name
Description
L
-
P
-
R
-
Pin
Name
Description
L
-
P
-
R
-
AL25 NC Pin
AL27 NC Pin
AM32 VSS
V
AM34
-
-
-
-
-
-
CC_CORE
AL29 SADDIN[1]#
P
P
P
P
P
-
I
-
AM36 VSS
-
-
-
-
-
-
AL31
SDATAOUTVALID#
O
I
P
P
G
G
-
AN1
AN3
AN5
AN7
AN9
No Pin
AL33 SADDIN[8]#
AL35 SADDIN[4]#
AL37 SADDIN[10]#
NMI
P
P
-
I
-
I
SMI#
NC Pin
NC Pin
I
-
I
page 72
page 72
page 69
page 69
page 72
-
-
V
AM2
-
-
-
-
CC_CORE
AM4
AM6
AM8
AM10
VSS
-
-
-
-
-
-
-
-
-
-
-
-
AN11 NC Pin
-
-
-
VSS
AN13 PLLMON1
AN15 PLLBYPASSCLK
AN17 CLKIN
O
P
P
P
P
P
-
B
I
-
NC Pin
-
V
I
P
P
-
CC_CORE
AM12 VSS
-
-
-
-
-
-
AN19 RSTCLK
I
V
AM14
AN21 K7CLKOUT#
AN23 PROCRDY
AN25 NC Pin
O
O
-
CC_CORE
AM16 VSS
-
-
-
-
-
-
P
-
V
AM18
CC_CORE
AM20 VSS
-
-
-
-
-
-
AN27 NC Pin
-
-
-
V
AM22
AN29 SADDIN[12]#
AN31 SADDIN[14]#
AN33 SDATAINVALID#
AN35 SADDIN[13]#
AN37 SADDIN[9]#
P
P
P
P
P
I
G
G
P
G
G
CC_CORE
AM24 VSS
-
-
-
-
-
-
I
V
AM26
I
CC_CORE
AM28 VSS
-
-
-
-
-
-
I
V
AM30
I
CC_CORE
Chapter 10
Pin Descriptions
67
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
10.3
Detailed Pin Descriptions
A20M# Pin
AMD Pin
A20M# is an input from the system used to simulate address
wrap-around in the 20-bit 8086.
AMD Socket A processors do not implement a pin at location
AH6. All Socket A designs must have a top plate or cover that
blocks this pin location. When the cover plate blocks this
location, a non-AMD part (e.g., PGA370) does not fit into the
socket. However, socket manufacturers are allowed to have a
contact loaded in the AH6 position. Therefore, motherboard
socket design should account for the possibility that a contact
could be loaded in this position.
AMD Athlon™
System Bus Pins
See the AMD Athlon™ and AMD Duron™ System Bus
Specification, order# 21902 for information about the system
bus pins—PROCRDY, PWROK, RESET#, SADDIN[14:2]#,
SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#,
SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#,
SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#.
Analog Pin
Treat this pin as a NC.
APIC Pins, PICCLK,
PICD[1:0]#
The Advanced Programmable Interrupt Controller (APIC) is a
feature that provides a flexible and expandable means of
delivering interrupts in a system using an AMD processor. The
pins, PICD[1:0], are the bidirectional message-passing signals
used for the APIC and are driven to the Southbridge or a
dedicated I/O APIC. The pin, PICCLK, must be driven with a
valid clock input.
Refer to “VCC_2.5V Generation Circuit” found in the section,
“Motherboard Required Circuits,” of the AMD Athlon™
Processor Motherboard Design Guide, order# 24363 for the
required supporting circuitry.
For more information, see Table 15, “APIC Pin AC and DC
CLKFWDRST Pin
CLKFWDRST resets clock-forward circuitry for both the system
and processor.
Chapter 10
Pin Descriptions
68
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
CLKIN, RSTCLK
(SYSCLK) Pins
Connect CLKIN with RSTCLK and name it SYSCLK. Connect
CLKIN# with RSTCLK# and name it SYSCLK#. Length match
the clocks from the clock generator to the Northbridge and
processor.
See “SYSCLK and SYSCLK#” on page 73 for more information.
CONNECT Pin
CONNECT is an input from the system used for power
management and clock-forward initialization at reset.
COREFB and
COREFB# Pins
COREFB and COREFB# are outputs to the system that provide
processor core voltage feedback to the system.
CPU_PRESENCE# Pin
CPU_PRESENCE# is connected to VSS on the processor
package. If pulled-up on the motherboard, CPU_PRESENCE#
may be used to detect the presence or absence of a processor in
the Socket A-style socket.
DBRDY and DBREQ#
Pins
DBRDY and DBREQ# are routed to the debug connector.
DBREQ# is tied to V
with a pullup resistor.
CC_CORE
FERR Pin
FERR is an output to the system that is asserted for any
unmasked numerical exception independent of the NE bit in
CR0. FERR is a push-pull active High signal that must be
inverted and level shifted to an active Low signal. For more
information about FERR and FERR#, see the “Required
Circuits” chapter of the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
Chapter 10
Pin Descriptions
69
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
FID[3:0] Pins
FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the
4-bit processor clock-to-SYSCLK ratio.
Table 21 describes the encodings of the clock multipliers on
FID[3:0].
Table 21. FID[3:0] Clock Multiplier Encodings
2
FID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Processor Clock to SYSCLK Frequency Ratio
11
11.5
12
1
≥ 12.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
Notes:
1. All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011b, which causes
the SIP configuration for all ratios of 12.5x or greater to be the same.
2. BIOS initializes the CLK_Ctl MSR during the POST routine. This CLK_Ctl setting is used with all
FID combinations and selects a Halt disconnect divisor and a Stop Grant disconnect divisor.
For more information, refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656.
The FID[3:0] signals are open-drain processor outputs that are
pulled High on the motherboard and sampled by the chipset to
determine the SIP (serial initialization packet) that is sent to
the processor. The FID[3:0] signals are valid after PWROK is
asserted. The FID[3:0]signals must not be sampled until they
become valid. See the AMD Athlon™ and AMD Duron™ System
Bus Specification, order# 21902 for more information about
Serialization Initialization Packets and SIP protocol.
The processor FID[3:0] outputs are open-drain and 2.5-V
tolerant. To prevent damage to the processor, do not pull these
70
Pin Descriptions
Chapter 10
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
signals High above 2.5 V. Do not expose these pins to a
differential voltage greater than 1.60 V, relative to the
processor core voltage.
Refer to “VCC_2.5V Generation Circuit” found in the section,
“Motherboard Required Circuits,” of the AMD Athlon™
Processor Motherboard Design Guide, order# 24363 for the
required supporting circuitry.
DC characteristics for FID[3:0].
FSB_Sense[1:0] Pins
FSB_Sense[1:0] pins are either open circuit (logic level of 1) or
are pulled to ground (logic level of 0) on the processor package
with a 1 kΩ resistor. In conjunction with a circuit on the
motherboard, these pins may be used to automatically detect
the front-side bus (FSB) setting of this processor. Proper
detection of the FSB setting requires the implementation of a
pull-up resistor on the motherboard. Refer to the AMD Athlon™
Processor-Based Motherboard Design Guide, order# 24363 and the
technical note FSB_Sense Auto Detection Circuitry for Desktop
Processors, order# TN26673 for more information.
Table 22 is the truth table to determine the FSB of desktop
processors.
Table 22. Front-Side Bus Sense Truth Table
FSB_Sense[1]
FSB_Sense[0]
Bus Frequency
RESERVED
133 MHz
1
1
0
0
0
1
1
0
166 MHz
200 MHz
The FSB_Sense[1:0] pins are 3.3-V tolerant.
FLUSH# must be tied to V with a pullup resistor. If a
FLUSH# Pin
CC_CORE
debug connector is implemented, FLUSH# is routed to the
debug connector.
IGNNE# Pin
INIT# Pin
IGNNE# is an input from the system that tells the processor to
ignore numeric errors.
INIT# is an input from the system that resets the integer
registers without affecting the floating-point registers or the
internal caches. Execution starts at 0_FFFF_FFF0h.
Chapter 10
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INTR Pin
JTAG Pins
INTR is an input from the system that causes the processor to
start an interrupt acknowledge transaction that fetches the
8-bit interrupt vector and starts execution at that location.
TCK, TMS, TDI, TRST#, and TDO are the JTAG interface.
Connect these pins directly to the motherboard debug
connector. Pull TDI, TCK, TMS, and TRST# up to V
pullup resistors.
with
CC_CORE
K7CLKOUT and
K7CLKOUT# Pins
K7CLKOUT and K7CLKOUT# are each run for two to three
inches and then terminated with a resistor pair: 100 ohms to
V
and 100 ohms to VSS. The effective termination
CC_CORE
resistance and voltage are 50 ohms and V
/2.
CC_CORE
Key Pins
These 16 locations are for processor type keying for forwards
and backwards compatibility (G7, G9, G15, G17, G23, G25, N7,
Q7, Y7, AA7, AG7, AG9, AG15, AG17, AG27, and AG29).
Motherboard designers should treat key pins like NC (No
Connect) pins. A socket designer has the option of creating a
top mold piece that allows PGA key pins only where designated.
However, sockets that populate all 16 key pins must be allowed,
so the motherboard must always provide for pins at all key pin
locations.
See “NC Pins“ for more information.
NC Pins
The motherboard should provide a plated hole for an NC pin.
The pin hole should not be electrically connected to anything.
NMI Pin
NMI is an input from the system that causes a non-maskable
interrupt.
PGA Orientation Pins
No pin is present at pin locations A1 and AN1. Motherboard
designers should not allow for a PGA socket pin at these
locations.
For more information, see the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
PLL Bypass and Test
Pins
PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2,
PLLBYPASSCLK, and PLLBYPASSCLK# are the PLL bypass
and test interface. This interface is tied disabled on the
motherboard. All six pin signals are routed to the debug
connector. All four processor inputs (PLLTEST#, PLLBYPASS#,
PLLMON1, and PLLMON2) are tied to V
resistors.
with pullup
CC_CORE
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
PWROK Pin
The PWROK input to the processor must not be asserted until
all voltage planes in the system are within specification and all
system clocks are running within specification.
For more information, Chapter 8, “Signal and Power-Up
SADDIN[1:0]# and
SADDOUT[1:0]# Pins
The AMD Sempron processor model 10 does not support
SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC
with pullup resistors, if this bit is not supported by the
Northbridge (future models can support SADDIN[1]#).
SADDOUT[1:0]# are tied to VCC with pullup resistors if these
pins are supported by the Northbridge. For more information,
see the AMD Athlon™ and AMD Duron™ System Bus
Specification, order# 21902.
Scan Pins
SCANSHIFTEN, SCANCLK1, SCANINTEVAL, and SCANCLK2
are the scan interface. This interface is AMD internal and is
tied disabled with pulldown resistors to ground on the
motherboard.
SMI# Pin
SMI# is an input that causes the processor to enter the system
management mode.
STPCLK# Pin
STPCLK# is an input that causes the processor to enter a lower
power mode and issue a Stop Grant special cycle.
SYSCLK and SYSCLK#
SYSCLK and SYSCLK# are differential input clock signals
provided to the PLL of the processor from a system-clock
generator.
information.
THERMDA and
THERMDC Pins
Thermal Diode anode and cathode pins are used to monitor the
actual temperature of the processor die, providing more
accurate temperature control to the system.
page 35 for more information.
VCCA Pin
VCCA is the processor PLL supply. For information about the
VCCA pin, see Table 5, “VCCA AC and DC Characteristics,” on
page 35 and the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
To prevent damage to the processor, do not pull this signal High
above 2.5 V. Do not expose this pin to a differential voltage
greater than 1.60 V, relative to the processor core voltage.
Chapter 10
Pin Descriptions
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VID[4:0] Pins
The VID[4:0] (Voltage Identification) outputs are used to
dictate the V voltage level. The VID[4:0] pins are
CC_CORE
strapped to ground or left unconnected on the processor
package. The VID[4:0] pins are pulled up on the motherboard
and used by the V
DC/DC converter.
CC_CORE
The VID codes and corresponding voltage levels are shown in
Table 23. VID[4:0] Code to Voltage Definition
V
(V)
V
(V)
VID[4:0]
VID[4:0]
CC_CORE
1.850
1.825
1.800
1.775
1.750
1.725
1.675
1.650
1.625
1.600
1.575
1.550
1.525
1.500
1.475
CC_CORE
1.450
1.425
1.400
1.375
1.350
1.325
1.275
1.250
1.225
1.200
1.175
00000
00001
00010
00011
00100
00101
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10111
11000
11001
11010
11011
11100
11101
11110
11111
1.150
1.125
1.100
No CPU
For more information, see the “Required Circuits” chapter of
the AMD Athlon™ Processor-Based Motherboard Design Guide,
order# 24363.
VREFSYS Pin
VREFSYS (W5) drives the threshold voltage for the system bus
input receivers. The value of VREFSYS is system specific. In
addition, to minimize V
noise rejection from VREFSYS,
CC_CORE
include decoupling capacitors. For more information, see the
AMD Athlon™ Processor-Based Motherboard Design Guide, order#
24363.
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
ZN and ZP Pins
ZN (AC5) and ZP (AE5) are the push-pull compensation circuit
pins. In Push-Pull mode (selected by the SIP parameter
SysPushPull asserted), ZN is tied to V
with a resistor
CC_CORE
that has a resistance matching the impedance Z of the
0
transmission line. ZP is tied to VSS with a resistor that has a
resistance matching the impedance Z of the transmission line.
0
Chapter 10
Pin Descriptions
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
11
Ordering Information
Standard AMD Sempron™ Processor Model 10 Products
AMD standard products are available in several operating ranges. The ordering part
OPN1
SD C 2800 D U T 3 D
Advanced Front-Side Bus: D = 333
Size of L2 Cache: 3 = 256 Kbytes
Die Temperature: T = 90°C
Operating Voltage: U = 1.60 V
Package Type: D = OPGA
Model Number: 2800 operates at 2000 MHz , 2200 operates at 1500 MHz
2
2
Maximum Power: C = Desktop Processor
Architecture Segment: SD = AMD Sempron™ Processor Model 10 with
QuantiSpeed™ Architecture for Desktop Products
Note:
1. Spaces are added to the number shown above for viewing clarity only.
2. This processor is available only with an advanced 333 FSB.
Figure 17. OPN Example for the AMD Sempron™ Processor Model 10 with 256K L2 Cache
Chapter 11
Ordering Information
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78
Ordering Information
Chapter 11
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Appendix A
Thermal Diode Calculations
This section contains information about the calculations for the
on-die thermal diode of the AMD Sempron™ processor model
10. For electrical information about this thermal diode, see
Ideal Diode Equation
The ideal diode equation uses the variables and constants
Table 24. Constants and Variables for the Ideal Diode Equation
Equation Symbol
Variable, Constant Description
Lumped ideality factor
n
f, lumped
k
q
T
Boltzmann constant
Electron charge constant
Diode temperature (Kelvin)
Voltage from base to emitter
V
BE
I
Collector current
Saturation current
C
I
S
Appendix A - Thermal Diode Calculations
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
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Equation (1) shows the ideal diode calculation.
k
q
IC
⎛ ⎞
(1)
VBE = nf, lumped ⋅ -- ⋅ T ⋅ ln ---
⎝ ⎠
IS
difference in the base-to-emitter voltage that leads to finding
dual sourcing currents allows the measurement of the thermal
diode temperature to be more accurate and less susceptible to
die and process revisions. Temperature sensors that utilize
series resistance cancellation can use more than two sourcing
currents and are suitable to be used with the AMD thermal
temperature of a thermal diode.
V
BE, high – VBE, low
T =
--------------------------------------------------------------
k
Ihigh
(2)
⎛
⎞
⎠
nf, lumped ⋅ -- ⋅ ln -------
⎝
q
Ilow
Temperature Offset Correction
A temperature offset may be required to correct the value
measured by a temperature sensor. An offset is necessary if a
difference exists between the lumped ideality factor of the
processor and the ideality factor assumed by the temperature
sensor. The lumped ideality factor can be calculated using the
equations in this section to find the temperature offset that
should be used with the temperature sensor.
Table 25 shows the constants and variables used to calculate the
temperature offset correction.
Table 25. Constants and Variables Used in Temperature Offset Equations
Equation Symbol
Variable, Constant Description
Actual ideality factor
n
f, actual
n
Lumped ideality factor
f, lumped
n
Ideality factor assumed by temperature sensor
High sourcing current
f, TS
I
high
I
Low sourcing current
low
T
Die temperature specification
Temperature offset
die, spec
T
offset
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Appendix A - Thermal Diode Calculations
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
calculate the temperature offset for temperature sensors that
do not employ series resistance cancellation. The result is
added to the value measured by the temperature sensor.
Contact the vendor of the temperature sensor being used for
the value of n
. Refer to the document, On-Die Thermal Diode
f,TS
Characterization, order# 25443, for further details.
Equation (3) shows the equation for calculating the lumped
ideality factor (n
) in sensors that do not employ series
f, lumped
resistance cancellation.
RT ⋅ (Ihigh – Ilow)
nf, lumped = nf, actual
+
----------------------------------------------------------------------
(3)
k
Ihigh
⎛
⎞
--(Tdie, spec + 273.15) ⋅ ln -------
⎝
⎠
q
Ilow
Equation (4) shows the equation for calculating temperature
offset (T ) in sensors that do not employ series resistance
offset
cancellation.
nf, lumped
--------------
nf, TS
⎛
⎞
T
= (Tdie, spec + 273.15) ⋅ 1 –
(4)
offset
⎝
⎠
Equation (5) is the temperature offset for temperature sensors
that utilize series resistance cancellation. Add the result to the
value measured by the temperature sensor. Note that the value
of n
f,TS
nf, actual
---------------
nf, TS
⎛
⎞
⎠
T
= (Tdie, spec + 273.15) ⋅ 1 –
(5)
offset
⎝
Appendix A - Thermal Diode Calculations
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82
Appendix A - Thermal Diode Calculations
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Appendix B
Conventions and
Abbreviations
This section contains information about the conventions and
abbreviations used in this document.
Signals and Bits
■
Active-Low Signals—Signal names containing a pound sign,
such as SFILL#, indicate active-Low signals. They are
asserted in their Low-voltage state and negated in their
High-voltage state. When used in this context, High and Low
are written with an initial upper case letter.
■
■
Signal Ranges—In a range of signals, the highest and lowest
signal numbers are contained in brackets and separated by a
colon (for example, D[63:0]).
Reserved Bits and Signals—Signals or bus bits marked
reserved must be driven inactive or left unconnected, as
indicated in the signal descriptions. These bits and signals
are reserved by AMD for future implementations. When
software reads registers with reserved bits, the reserved bits
must be masked. When software writes such registers, it
must first read the register and change only the
non-reserved bits before writing back to the register.
■
■
Three-State—In timing diagrams, signal ranges that are
high impedance are shown as a straight horizontal line
half-way between the high and low levels.
Invalid and Don’t-Care—In timing diagrams, signal ranges
that are invalid or don't-care are filled with a screen pattern.
Appendix B - Conventions and Abbreviations
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
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Data Terminology
The following list defines data terminology:
Quantities
■
• A word is two bytes (16 bits)
• A doubleword is four bytes (32 bits)
• A quadword is eight bytes (64 bits)
■
■
Addressing—Memory is addressed as a series of bytes on
eight-byte (64-bit) boundaries in which each byte can be
separately enabled.
Abbreviations—The following notation is used for bits and
bytes:
• Kilo (K, as in 4-Kbyte page)
• Mega (M, as in 4 Mbits/sec)
• Giga (G, as in 4 Gbytes of memory space)
■
Little-Endian Convention—The byte with the address
xx...xx00 is in the least-significant byte position (little end).
In byte diagrams, bit positions are numbered from right to
left—the little end is on the right and the big end is on the
left. Data structure diagrams in memory show low addresses
at the bottom and high addresses at the top. When data
items are aligned, bit notation on a 64-bit data bus maps
directly to bit notation in 64-bit-wide memory. Because byte
addresses increase from right to left, strings appear in
reverse order when illustrated.
■
Bit Ranges—In text, bit ranges are shown with a dash (for
example, bits 9–1). When accompanied by a signal or bus
name, the highest and lowest bit numbers are contained in
brackets and separated by a colon (for example, AD[31:0]).
■
■
Bit Values—Bits can either be set to 1 or cleared to 0.
Hexadecimal and Binary Numbers—Unless the context
makes interpretation clear, hexadecimal numbers are
followed by an h and binary numbers are followed by a b.
84
Appendix B - Conventions and Abbreviations
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Abbreviations and Acronyms
Table 26 contains the definitions of abbreviations used in this
document.
Table 26. Abbreviations
Abbreviation
Meaning
Ampere
A
F
Farad
G
Giga–
Gbit
Gbyte
H
Gigabit
Gigabyte
Henry
h
Hexadecimal
Kilo–
K
Kbyte
M
Kilobyte
Mega–
Mbit
Mbyte
MHz
m
Megabit
Megabyte
Megahertz
Milli–
ms
mW
µ
Millisecond
Milliwatt
Micro–
µA
µF
µH
µs
Microampere
Microfarad
Microhenry
Microsecond
Microvolt
nano–
µV
n
nA
nF
nanoampere
nanofarad
nanohenry
nanosecond
Ohm
nH
ns
ohm
p
pico–
pA
picoampere
Appendix B - Conventions and Abbreviations
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
Table 26. Abbreviations (continued)
Abbreviation
Meaning
picofarad
picohenry
picosecond
Second
pF
pH
ps
s
V
Volt
W
Watt
Table 27 contains the definitions of acronyms used in this
document.
Table 27. Acronyms
Abbreviation
ACPI
Meaning
Advanced Configuration and Power Interface
Accelerated Graphics Port
AGP
APCI
AGP Peripheral Component Interconnect
Application Programming Interface
Advanced Programmable Interrupt Controller
Basic Input/Output System
API
APIC
BIOS
BIST
Built-In Self-Test
BIU
Bus Interface Unit
CPGA
DDR
Ceramic Pin Grid Array
Double-Data Rate
DIMM
DMA
DRAM
EIDE
Dual Inline Memory Module
Direct Memory Access
Direct Random Access Memory
Enhanced Integrated Device Electronics
Extended Industry Standard Architecture
Enhanced Programmable Read Only Memory
First In, First Out
EISA
EPROM
FIFO
GART
HSTL
IDE
Graphics Address Remapping Table
High-Speed Transistor Logic
Integrated Device Electronics
Industry Standard Architecture
Joint Electron Device Engineering Council
Joint Test Action Group
ISA
JEDEC
JTAG
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Appendix B - Conventions and Abbreviations
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Table 27. Acronyms (continued)
Abbreviation
LAN
Meaning
Large Area Network
LRU
Least-Recently Used
LVTTL
MSB
MTRR
MUX
NMI
Low Voltage Transistor Transistor Logic
Most Significant Bit
Memory Type and Range Registers
Multiplexer
Non-Maskable Interrupt
Open-Drain
OD
OPGA
PBGA
PA
Organic Pin Grid Array
Plastic Ball Grid Array
Physical Address
PCI
Peripheral Component Interconnect
Page Directory Entry
PDE
PDT
Page Directory Table
PGA
Pin Grid Array
PLL
Phase Locked Loop
PMSM
POS
Power Management State Machine
Power-On Suspend
POST
RAM
ROM
RXA
Power-On Self-Test
Random Access Memory
Read Only Memory
Read Acknowledge Queue
Small Computer System Interface
System DRAM Interface
Synchronous Direct Random Access Memory
Single Instruction Multiple Data
Serial Initialization Packet
System Management Bus
Serial Presence Detect
SCSI
SDI
SDRAM
SIMD
SIP
SMbus
SPD
SRAM
SROM
TLB
Synchronous Random Access Memory
Serial Read Only Memory
Translation Lookaside Buffer
Top of Memory
TOM
TTL
Transistor Transistor Logic
Appendix B - Conventions and Abbreviations
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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
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Table 27. Acronyms (continued)
Abbreviation
VAS
Meaning
Virtual Address Space
Virtual Page Address
Video Graphics Adapter
Universal Serial Bus
Zero Delay Buffer
VPA
VGA
USB
ZDB
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Appendix B - Conventions and Abbreviations
31994A—1August 2004
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
Related Publications
These documents provide helpful information about the
AMD Sempron™ processor model 10, and can be found with
other related documents at the AMD Web site,
http://www.amd.com.
■
AMD Athlon™ Processor x86 Code Optimization Guide, order#
22007
■
■
AMD Processor Recognition Application Note, order# 20734
Methodologies for Measuring Temperature on AMD Athlon™
and AMD Duron™ Processors, order# 24228
■
■
AMD Thermal, Mechanical, and Chassis Cooling Design Guide,
order# 23794
Builders Guide for Desktop/Tower Systems, order# 26003
Other Web sites of interest include the following:
■
■
■
JEDEC home page—www.jedec.org
IEEE home page—www.computer.org
AGP Forum—www.agpforum.or
Appendix B - Conventions and Abbreviations
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90
Appendix B - Conventions and Abbreviations
|