AMD Athlon 10 User Manual

Preliminary Information  
TM  
AMD Athlon XP  
Processor Model 10  
Data Sheet  
Publication # 26237 Rev. C  
Issue Date: May 2003  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
QuantiSpeed™ Architecture Summary. . . . . . . . . . . . . . . . . . . 2  
Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Working State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Advanced 333 Front-Side Bus AMD Athlon™ XP  
Processor Model 10 Specifications. . . . . . . . . . . . . . . . . . . . . . 21  
Electrical and Thermal Specifications for the Advanced  
333 FSB AMD Athlon XP Processor Model 10 . . . . . . . . . . . . 21  
Advanced 333 FSB AMD Athlon XP Processor Model 10  
SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . 22  
Advanced 333 FSB AMD Athlon System Bus  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Advanced 333 FSB AMD Athlon System Bus DC  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Advanced 400 Front-Side Bus AMD Athlon XP  
Processor Model 10 Specifications. . . . . . . . . . . . . . . . . . . . . . 25  
Electrical and Thermal Specifications for the Advanced  
400 FSB AMD Athlon XP Processor Model 10 . . . . . . . . . . . . 25  
Advanced 400 FSB AMD Athlon XP Processor Model 10  
SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . 26  
Advanced 400 FSB AMD Athlon System Bus  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Advanced 400 FSB AMD Athlon System Bus DC  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Table of Contents  
iii  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 30  
Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 31  
VCCA AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 31  
Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
VCC_CORE Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . 35  
8.11 Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
8.12 Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39  
Thermal Protection Characterization . . . . . . . . . . . . . . . . 39  
Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Signal Sequence and Timing Description . . . . . . . . . . . . . 43  
Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . 46  
Processor Warm Reset Requirements. . . . . . . . . . . . . . . . . . . 46  
Northbridge Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
10.1 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
10.2 AMD Athlon XP Processor Model 10 Part Number 27488  
OPGA Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
10.3 AMD Athlon XP Processor Model 10 Part Number 27493  
OPGA Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
11.1 Pin Diagram and Pin Name Abbreviations. . . . . . . . . . . . . . . 53  
11.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
11.3 Detailed Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
AMD Athlon System Bus Pins . . . . . . . . . . . . . . . . . . . . . . 72  
Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . 73  
DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . 73  
iv  
Table of Contents  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  
IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  
INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  
JTAG Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . 76  
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
PLL Bypass and Test Pins. . . . . . . . . . . . . . . . . . . . . . . . . . 76  
PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
SADDIN[1:0]# and SADDOUT[1:0]# Pins. . . . . . . . . . . . . 77  
Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
THERMDA and THERMDC Pins. . . . . . . . . . . . . . . . . . . . 77  
VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78  
ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78  
Table of Contents  
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Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
vi  
Table of Contents  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
List of Figures  
Figure 1. Typical AMD Athlon™ XP Processor Model 10 System  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Figure 3. AMD Athlon XP Processor Model 10 Power  
Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Figure 4. AMD Athlon System Bus Disconnect Sequence in the  
Stop Grant State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Figure 8. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 9. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Figure 10. VCC_CORE Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 13. Signal Relationship Requirements During Power-Up  
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Figure 14. AMD Athlon XP Processor Model 10 Part Number  
27488 OPGA Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Figure 15. AMD Athlon XP Processor Model 10 Part Number  
27493 OPGA Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 51  
Figure 16. AMD Athlon XP Processor Model 10 Pin Diagram  
—Topside View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54  
Figure 17. AMD Athlon XP Processor Model 10 Pin Diagram  
—Bottomside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
Figure 18. OPN Example for the AMD Athlon XP Processor  
Model 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79  
List of Figures  
vii  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
viii  
List of Figures  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
List of Tables  
Table 1.  
Electrical and Thermal Specifications for the Advanced  
Table 2.  
Advanced 333 FSB SYSCLK and SYSCLK# AC  
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Table 5.  
Electrical and Thermal Specifications for the Advanced  
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Table 7.  
Advanced 400 FSB AMD Athlon System Bus AC  
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Table 11. FID[3:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
VCC_CORE AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 32  
Table 14. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Table 19. APIC Pin AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . 41  
Model 10 Part Number 27488 OPGA Package . . . . . . . . . . . . . 48  
Model 10 Part Number 27493 OPGA Package . . . . . . . . . . . . . 50  
List of Tables  
ix  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Revision History  
Date  
Rev  
Description  
Public revision C of the AMD Athlon™ XP Processor Model 10 Data Sheet includes the following  
changes:  
May 2003  
C
February 2003  
B
Initial public release of the AMD Athlon™ XP Processor Model 10 Data Sheet  
Revision History  
xi  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
xii  
Revision History  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
1
Overview  
The AMD Athlon™ XP processor model 10 with QuantiSpeed™  
architecture powers the next generation in computing platforms,  
®
delivering extreme performance for Windows XP.  
The AMD Athlon™ XP processor model 10, based on leading-  
edge 0.13 micron technology and increased on-chip cache,  
integrates the innovative design and manufacturing expertise  
of AMD to deliver improved performance while maintaining the  
stable and compatible Socket A infrastructure of the  
AMD Athlon processor.  
Delivered in an OPGA package, the AMD Athlon XP processor  
model 10 delivers the integer, floating-point, and 3D  
multimedia performance for highly demanding applications  
running on x86 system platforms. The AMD Athlon XP  
processor model 10 delivers compelling performance for  
cutting-edge software applications that include high-speed  
Internet capability, digital content creation, digital photo  
editing, digital video, image compression, video encoding for  
streaming over the Internet, soft DVD, commercial 3D  
modeling, workstation-class computer-aided design (CAD),  
commercial desktop publishing, and speech recognition. The  
AMD Athlon XP processor model 10 also offers the scalability  
and reliability that IT managers and business users require for  
enterprise computing.  
The AMD Athlon XP processor model 10 features a  
seventh-generation microarchitecture with an integrated,  
exclusive L2 cache, which supports the growing processor and  
system bandwidth requirements of emerging software,  
graphics, I/O, and memory technologies. The high-speed  
execution core of the AMD Athlon XP processor model 10  
includes multiple x86 instruction decoders, a dual-ported  
128-Kbyte split level-one (L1) cache, an exclusive 512-Kbyte L2  
cache, three independent integer pipelines, three address  
calculation pipelines, and a superscalar, fully pipelined,  
out-of-order, three-way floating-point engine. The floating-point  
engine is capable of delivering outstanding performance on  
numerically complex applications.  
Chapter 1  
Overview  
1
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
The features of the AMD Athlon XP processor model 10 are  
QuantiSpeed™ architecture, 640 Kbytes of total, high-  
performance, full-speed, on-chip cache, an advanced 400 front-  
side bus (FSB) with a 3.2-Gigabyte per second system bus, or an  
advanced 333 FSB with a 2.7-Gigabyte per second system bus,  
and 3DNow!™ Professional technology. The AMD Athlon system  
bus combines the latest technological advances, such as  
point-to-point topology, source-synchronous packet-based  
transfers, and low-voltage signaling to provide an extremely  
powerful, scalable bus for an x86 processor.  
The AMD Athlon XP processor model 10 is binary-compatible  
with existing x86 software and backwards compatible with  
applications optimized for MMX™, SSE, and 3DNow! technology.  
Using a data format and single-instruction multiple-data (SIMD)  
operations based on the MMX instruction model, the  
AMD Athlon XP processor model 10 can produce as many as four,  
32-bit, single-precision floating-point results per clock cycle. The  
3DNow! Professional technology implemented in the  
AMD Athlon XP processor model 10 includes new integer  
multimedia instructions and software-directed data movement  
instructions for optimizing such applications as digital content  
creation and streaming video for the internet, as well as new  
instructions for digital signal processing (DSP) and  
communications applications.  
1.1  
QuantiSpeed™ Architecture Summary  
The following features summarize the AMD Athlon XP  
processor model 10 QuantiSpeed architecture:  
An advanced nine-issue, superpipelined, superscalar x86  
processor microarchitecture designed for increased  
instructions per cycle (IPC) and high clock frequencies  
Fully pipelined floating-point unit that executes all x87  
(floating-point), MMX, SSE and 3DNow! instructions  
Hardware data pre-fetch that increases and optimizes  
performance on high-end software applications utilizing  
high-bandwidth system capabilities  
Advanced two-level translation look-aside buffer (TLB)  
structures for both enhanced data and instruction address  
translation. The AMD Athlon XP processor model 10 with  
QuantiSpeed architecture  
incorporates  
three  
TLB  
optimizations: the L1 DTLB increases from 32 to 40 entries,  
the L2 ITLB and L2 DTLB both use exclusive architecture,  
and the TLB entries can be speculatively loaded.  
2
Overview  
Chapter 1  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
The AMD Athlon XP processor model 10 delivers excellent  
system performance in a cost-effective, industry-standard form  
factor. The AMD Athlon XP processor model 10 is compatible  
with motherboards based on Socket A.  
Figure 1 shows a typical AMD Athlon XP processor model 10  
system block diagram.  
Thermal Monitor  
AMD Athlon™ XP  
Processor Model 10  
AMD Athlon System Bus  
AGP  
AGP Bus  
Memory Bus  
System Controller  
(Northbridge)  
SDRAM or DDR  
PCI Bus  
Peripheral Bus  
Controller  
(Southbridge)  
LAN  
SCSI  
Modem / Audio  
LPC Bus  
USB  
Dual EIDE  
BIOS  
Figure 1. Typical AMD Athlon™ XP Processor Model 10 System Block Diagram  
Chapter 1  
Overview  
3
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
4
Overview  
Chapter 1  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
2
Interface Signals  
This section describes the interface signals utilized by the  
AMD Athlon™ XP processor model 10.  
2.1  
Overview  
The AMD Athlon™ system bus architecture is designed to  
deliver excellent data movement bandwidth for next-  
generation x86 platforms as well as the high-performance  
required by enterprise-class application software. The system  
bus architecture consists of three high-speed channels (a  
unidirectional processor request channel, a unidirectional  
probe channel, and a 64-bit bidirectional data channel),  
source-synchronous clocking, and a packet-based protocol. In  
addition, the system bus supports several control, clock, and  
legacy signals. The interface signals use an impedance  
controlled push-pull, low-voltage, swing-signaling technology  
contained within the Socket A socket.  
AMD Athlon™ and AMD Duron™ System Bus Specification,  
order# 21902.  
2.2  
Signaling Technology  
The AMD Athlon system bus uses a low-voltage, swing-signaling  
technology, that has been enhanced to provide larger noise  
margins, reduced ringing, and variable voltage levels. The  
signals are push-pull and impedance compensated. The signal  
inputs use differential receivers that require a reference  
voltage (V  
). The reference signal is used by the receivers to  
REF  
determine if a signal is asserted or deasserted by the source.  
Termination resistors are not needed because the driver is  
impedance-matched to the motherboard and a high impedance  
reflection is used at the receiver to bring the signal past the  
input threshold.  
For more information about pins and signals, see Chapter 11,  
Chapter 2  
Interface Signals  
5
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
2.3  
Push-Pull (PP) Drivers  
The AMD Athlon XP processor model 10 supports push-pull  
(PP) drivers. The system logic configures the processor with the  
configuration parameter called SysPushPull (1=PP). The  
impedance of the PP drivers is set to match the impedance of  
the motherboard by two external resistors connected to the ZN  
and ZP pins.  
2.4  
AMD Athlon™ System Bus Signals  
The AMD Athlon system bus is a clock-forwarded, point-to-  
point interface with the following three point-to-point channels:  
A 13-bit unidirectional output address/command channel  
A 13-bit unidirectional input address/command channel  
A 72-bit bidirectional data channel  
For more information, see Chapter 7, “Electrical Data” on page  
23 and the AMD Athlon™ and AMD Duron™ System Bus  
Specification, order# 21902.  
6
Interface Signals  
Chapter 2  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
3
Logic Symbol Diagram  
Figure 2 is the logic symbol diagram of the processor. This  
diagram shows the logical grouping of the input and output  
signals.  
Clock  
SYSCLK  
SYSCLK#  
VID[4:0]  
COREFB  
COREFB#  
PWROK  
SDATA[63:0]#  
{
SDATAINCLK[3:0]#  
SDATAOUTCLK[3:0]#  
SDATAINVALID#  
SDATAOUTVALID#  
SFILLVALID#  
Voltage  
Control  
Data  
{
Frequency  
Control  
FID[3:0]  
Front-Side Bus  
Autodetect  
FSB_SENSE[1:0]  
SADDIN[14:2]#  
SADDINCLK#  
Probe/SysCMD  
{
{
FERR  
IGNNE#  
INIT#  
INTR  
NMI  
A20M#  
SMI#  
FLUSH#  
AMD Athlon™ XP  
Processor Model 10  
{
SADDOUT[14:2]#  
SADDOUTCLK#  
Request  
Legacy  
PROCRDY  
CLKFWDRST  
CONNECT  
STPCLK#  
RESET#  
Power  
Management  
and Initialization  
{
{
Thermal  
Diode  
THERMDA  
THERMDC  
{
PICCLK  
PICD[1:0]  
APIC  
Figure 2. Logic Symbol Diagram  
Chapter 3  
Logic Symbol Diagram  
7
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
8
Logic Symbol Diagram  
Chapter 3  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
4
Power Management  
This chapter describes the power management control system  
of the AMD Athlon™ XP processor model 10. The power  
management features of the processor are compliant with the  
ACPI 1.0b and ACPI 2.0 specifications.  
4.1  
Power Management States  
The AMD Athlon XP processor model 10 supports low-power  
Halt and Stop Grant states. These states are used by advanced  
configuration and power interface (ACPI) enabled operating  
systems for processor power management.  
Figure 3 shows the power management states of the processor.  
The figure includes the ACPI “Cx” naming convention for these  
states.  
Execute HLT  
C1  
Halt  
C0  
Working4  
SMI#, INTR, NMI, INIT#, RESET#  
S1  
Incoming Probe  
Probe Serviced  
C2  
Probe  
State1  
Stop Grant  
Cache Not Snoopable  
Sleep  
Stop Grant  
Cache Snoopable  
Legend  
Hardware transitions  
Software transitions  
Note:  
The AMD AthlonTM System Bus is connected during the following states:  
1) The Probe state  
2) During transitions between the Halt state and the C2 Stop Grant state  
3) During transitions between the C2 Stop Grant state and the Halt state  
4) C0 Working state  
Figure 3. AMD Athlon™ XP Processor Model 10 Power Management States  
Chapter 4 Power Management  
9
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
The following sections provide an overview of the power  
management states. For more details, refer to the  
AMD Athlon™ and AMD Duron™ System Bus Specification,  
order# 21902.  
Note: In all power management states that the processor is  
powered, the system must not stop the system clock  
(SYSCLK/SYSCLK#) to the processor.  
Working State  
Halt State  
The Working state is the state in which the processor is  
executing instructions.  
When the processor executes the HLT instruction, the processor  
enters the Halt state and issues a Halt special cycle to the  
AMD Athlon system bus. The processor only enters the low  
power state dictated by the CLK_Ctl MSR if the system  
controller (Northbridge) disconnects the AMD Athlon system  
bus in response to the Halt special cycle.  
If STPCLK# is asserted, the processor will exit the Halt state  
and enter the Stop Grant state. The processor will initiate a  
system bus connect, if it is disconnected, then issue a Stop  
Grant special cycle. When STPCLK# is deasserted, the  
processor will exit the Stop Grant state and re-enter the Halt  
state. The processor will issue a Halt special cycle when  
re-entering the Halt state.  
The Halt state is exited when the processor detects the  
assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR  
or NMI pins, or via a local APIC interrupt message. When the  
Halt state is exited, the processor will initiate an AMD Athlon  
system bus connect if it is disconnected.  
Stop Grant States  
The processor enters the Stop Grant state upon recognition of  
assertion of STPCLK# input. After entering the Stop Grant  
state, the processor issues a Stop Grant special bus cycle on the  
AMD Athlon system bus. The processor is not in a low-power  
state at this time, because the AMD Athlon system bus is still  
connected. After the Northbridge disconnects the AMD Athlon  
system bus in response to the Stop Grant special bus cycle, the  
processor enters a low-power state dictated by the CLK_Ctl  
MSR. If the Northbridge needs to probe the processor during  
the Stop Grant state while the system bus is disconnected, it  
10  
Power Management  
Chapter 4  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
must first connect the system bus. Connecting the system bus  
places the processor into the higher power probe state. After  
the Northbridge has completed all probes of the processor, the  
Northbridge must disconnect the AMD Athlon system bus  
again so that the processor can return to the low-power state.  
During the Stop Grant states, the processor latches INIT#,  
INTR, NMI, SMI#, or a local APIC interrupt message, if they are  
asserted.  
The Stop Grant state is exited upon the deassertion of  
STPCLK# or the assertion of RESET#. When STPCLK# is  
deasserted, the processor initiates a connect of the  
AMD Athlon system bus if it is disconnected. After the  
processor enters the Working state, any pending interrupts are  
recognized and serviced and the processor resumes execution  
at the instruction boundary where STPCLK# was initially  
recognized. If RESET# is sampled asserted during the Stop  
Grant state, the processor exits the Stop Grant state and the  
reset process begins.  
There are two mechanisms for asserting STPCLK#—hardware  
and software.  
The Southbridge can force STPCLK# assertion for throttling to  
protect the processor from exceeding its maximum case  
temperature. This is accomplished by asserting the THERM#  
input to the Southbridge. Throttling asserts STPCLK# for a  
percentage of a predefined throttling period: STPCLK# is  
repetitively asserted and deasserted until THERM# is  
deasserted.  
Software can force the processor into the Stop Grant state by  
accessing ACPI-defined registers typically located in the  
Southbridge.  
The operating system places the processor into the C2 Stop  
Grant state by reading the P_LVL2 register in the Southbridge.  
If an ACPI Thermal Zone is defined for the processor, the  
operating system can initiate throttling with STPCLK# using  
the ACPI defined P_CNT register in the Southbridge. The  
Northbridge connects the AMD Athlon system bus, and the  
processor enters the Probe state to service cache snoops during  
Stop Grant for C2 or throttling.  
Chapter 4  
Power Management  
11  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
In C2, probes are allowed, as shown in Figure 3 on page 9  
The Stop Grant state is also entered for the S1, Powered On  
Suspend, system sleep state based on a write to the SLP_TYP  
and SLP_EN fields in the ACPI-defined Power Management 1  
control register in the Southbridge. During the S1 Sleep state,  
system software ensures no bus master or probe activity occurs.  
The Southbridge deasserts STPCLK# and brings the processor  
out of the S1 Stop Grant state when any enabled resume event  
occurs.  
Probe State  
The Probe state is entered when the Northbridge connects the  
AMD Athlon system bus to probe the processor (for example, to  
snoop the processor caches) when the processor is in the Halt or  
Stop Grant state. When in the Probe state, the processor  
responds to a probe cycle in the same manner as when it is in  
the Working state. When the probe has been serviced, the  
processor returns to the same state as when it entered the  
Probe state (Halt or Stop Grant state). When probe activity is  
completed the processor only returns to a low-power state after  
the Northbridge disconnects the AMD Athlon system bus again.  
4.2  
Connect and Disconnect Protocol  
Significant power savings of the processor only occur if the  
processor is disconnected from the system bus by the  
Northbridge while in the Halt or Stop Grant state. The  
Northbridge can optionally initiate a bus disconnect upon the  
receipt of a Halt or Stop Grant special cycle. The option of  
disconnecting is controlled by an enable bit in the Northbridge.  
If the Northbridge requires the processor to service a probe  
after the system bus has been disconnected, it must first  
initiate a system bus connect.  
Connect Protocol  
In addition to the legacy STPCLK# signal and the Halt and Stop  
Grant special cycles, the AMD Athlon system bus connect  
protocol includes the CONNECT, PROCRDY, and CLKFWDRST  
signals and a Connect special cycle.  
AMD Athlon system bus disconnects are initiated by the  
Northbridge in response to the receipt of a Halt or Stop Grant.  
Reconnect is initiated by the processor in response to an  
interrupt for Halt or STPCLK# deassertion. Reconnect is  
initiated by the Northbridge to probe the processor.  
12  
Power Management  
Chapter 4  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
The Northbridge contains BIOS programmable registers to  
enable the system bus disconnect in response to Halt and Stop  
Grant special cycles. When the Northbridge receives the Halt or  
Stop Grant special cycle from the processor and, if there are no  
outstanding probes or data movements, the Northbridge  
deasserts CONNECT a minimum of eight SYSCLK periods after  
the last command sent to the processor. The processor detects  
the deassertion of CONNECT on a rising edge of SYSCLK and  
deasserts PROCRDY to the Northbridge. In return, the  
Northbridge asserts CLKFWDRST in anticipation of  
reestablishing a connection at some later point.  
Note: The Northbridge must disconnect the processor from the  
AMD Athlon system bus before issuing the Stop Grant  
special cycle to the PCI bus or passing the Stop Grant special  
cycle to the Southbridge for systems that connect to the  
Southbridge with HyperTransport™ technology.  
This note applies to current chipset implementation—  
alternate chipset implementations that do not require this  
are possible.  
Note: In response to Halt special cycles, the Northbridge passes the  
Halt special cycle to the PCI bus or Southbridge  
immediately.  
The processor can receive an interrupt after it sends a Halt  
special cycle, or STPCLK# deassertion after it sends a Stop  
Grant special cycle to the Northbridge but before the  
disconnect actually occurs. In this case, the processor sends the  
Connect special cycle to the Northbridge, rather than  
continuing with the disconnect sequence. In response to the  
Connect special cycle, the Northbridge cancels the disconnect  
request.  
The system is required to assert the CONNECT signal before  
returning the C-bit for the connect special cycle (assuming  
CONNECT has been deasserted).  
For more information, see the AMD Athlon™ and AMD Duron™  
System Bus Specification, order# 21902 for the definition of the  
C-bit and the Connect special cycle.  
Chapter 4  
Power Management  
13  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Figure 4 shows STPCLK# assertion resulting in the processor in  
the Stop Grant state and the AMD Athlon system bus  
disconnected.  
STPCLK#  
AMD Athlon™  
System Bus  
Stop Grant  
CONNECT  
PROCRDY  
CLKFWDRST  
PCI Bus  
Stop Grant  
Figure 4. AMD Athlon™ System Bus Disconnect Sequence in the Stop Grant State  
An example of the AMD Athlon system bus disconnect  
sequence is as follows:  
1. The peripheral controller (Southbridge) asserts STPCLK#  
to place the processor in the Stop Grant state.  
2. When the processor recognizes STPCLK# asserted, it enters  
the Stop Grant state and then issues a Stop Grant special  
cycle.  
3. When the special cycle is received by the Northbridge, it  
deasserts CONNECT, assuming no probes are pending,  
initiating a bus disconnect to the processor.  
4. The processor responds to the Northbridge by deasserting  
PROCRDY.  
5. The Northbridge asserts CLKFWDRST to complete the bus  
disconnect sequence.  
6. After the processor is disconnected from the bus, the  
processor enters a low-power state. The Northbridge passes  
the Stop Grant special cycle along to the Southbridge.  
14  
Power Management  
Chapter 4  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Figure 5 shows the signal sequence of events that takes the  
processor out of the Stop Grant state, connects the processor to  
the AMD Athlon system bus, and puts the processor into the  
Working state.  
STPCLK#  
PROCRDY  
CONNECT  
CLKFWDRST  
Figure 5. Exiting the Stop Grant State and Bus Connect Sequence  
The following sequence of events removes the processor from  
the Stop Grant state and connects it to the system bus:  
1. The Southbridge deasserts STPCLK#, informing the  
processor of a wake event.  
2. When the processor recognizes STPCLK# deassertion, it  
exits the low-power state and asserts PROCRDY, notifying  
the Northbridge to connect to the bus.  
3. The Northbridge asserts CONNECT.  
4. The Northbridge deasserts CLKFWDRST, synchronizing the  
forwarded clocks between the processor and the  
Northbridge.  
5. The processor issues a Connect special cycle on the system  
bus and resumes operating system and application code  
execution.  
Chapter 4  
Power Management  
15  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Connect State  
Diagram  
Figure 6 below and Figure 7 on page 17 show the Northbridge  
and processor connect state diagrams, respectively.  
4/A  
1
2/A  
Disconnect  
Pending  
Disconnect  
Requested  
Connect  
3/C  
3
5/B  
8
8
Reconnect  
Pending  
Probe  
Pending 2  
Disconnect  
7/D,C  
6/C  
7/D  
Probe  
Pending 1  
Condition  
Action  
1
2
3
4
5
6
7
A disconnect is requested and probes are still pending.  
A disconnect is requested and no probes are pending.  
A Connect special cycle from the processor.  
No probes are pending.  
Deassert CONNECT eight SYSCLK periods  
after last SysDC sent.  
A
B
C
D
Assert CLKFWDRST.  
Assert CONNECT.  
Deassert CLKFWDRST.  
PROCRDY is deasserted.  
A probe needs service.  
PROCRDY is asserted.  
Three SYSCLK periods after CLKFWDRST is deasserted.  
Although reconnected to the system interface, the  
Northbridge must not issue any non-NOP SysDC  
commands for a minimum of four SYSCLK periods after  
deasserting CLKFWDRST.  
8
Figure 6. Northbridge Connect State Diagram  
16 Power Management  
Chapter 4  
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Connect  
6/B  
1
2/B  
Connect  
Pending 2  
Disconnect  
Pending  
5
Connect  
Pending 1  
3/A  
Disconnect  
4/C  
Condition  
Action  
CONNECT is deasserted by the Northbridge (for a  
previously sent Halt or Stop Grant special cycle).  
A
B
CLKFWDRST is asserted by the Northbridge.  
Issue a Connect special cycle.*  
1
Processor receives a wake-up event and must cancel  
the disconnect request.  
Return internal clocks to full speed and assert  
PROCRDY.  
2
3
4
5
6
C
Deassert PROCRDY and slow down internal clocks.  
Note:  
*
The Connect special cycle is only issued after a  
processor wake-up event (interrupt or STPCLK#  
deassertion) occurs. If the AMD Athlon™ system  
bus is connected so the Northbridge can probe the  
processor, a Connect special cycle is not issued at  
that time (it is only issued after a subsequent  
processor wake-up event).  
Processor wake-up event or CONNECT asserted by  
Northbridge.  
CLKFWDRST is deasserted by the Northbridge.  
Forward clocks start three SYSCLK periods after  
CLKFWDRST is deasserted.  
Figure 7. Processor Connect State Diagram  
Chapter 4  
Power Management  
17  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
4.3  
Clock Control  
The processor implements a Clock Control (CLK_Ctl) MSR  
(address C001_001Bh) that determines the internal clock  
divisor when the AMD Athlon system bus is disconnected.  
Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,  
Software, and Debug Developers Guide, order# 21656, for more  
details on the CLK_Ctl register.  
18  
Power Management  
Chapter 4  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
5
CPUID Support  
AMD Athlon™ XP processor model 10 version and feature set  
recognition can be performed through the use of the CPUID  
instruction, that provides complete information about the  
processor—vendor, type, name, etc., and its capabilities.  
Software can make use of this information to accurately tune  
the system for maximum performance and benefit to users.  
For information on the use of the CPUID instruction see the  
following documents:  
AMD Processor Recognition Application Note, order# 20734  
AMD Athlon™ Processor Recognition Application Note  
Addendum, order# 21922  
AMD Athlon™ and AMD Duron™ Processors BIOS, Software,  
and Debug Developers Guide, order# 21656  
Chapter 5  
CPUID Support  
19  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
20  
CPUID Support  
Chapter 5  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
6
Advanced 333 Front-Side Bus AMD Athlon™ XP  
Processor Model 10 Specifications  
This chapter describes the electrical specifications that are  
unique to the advanced 333 front-side bus (FSB)  
AMD Athlon™ XP processor model 10.  
6.1  
Electrical and Thermal Specifications for the Advanced 333 FSB  
AMD Athlon™ XP Processor Model 10  
Table 1 shows the electrical and thermal specifications in the  
C0 working state and the S1 Stop Grant state for this processor.  
Table 1. Electrical and Thermal Specifications for the Advanced 333 FSB AMD Athlon™ XP Processor  
Model 10  
ICC (Processor Current)  
VCC_CORE  
(Core  
Voltage)  
Thermal Power5  
Frequency in MHz  
(Model Number)  
Maximum Die  
Temperature  
Stop Grant S11, 2, 3, 4  
Working State C0  
Maximum Typical Maximum Typical Maximum Typical  
1833 (2500+)  
1917 (2600+)  
2083 (2800+)  
41.4 A  
45.0 A  
32.5 A  
35.4 A  
68.3 W  
74.3 W  
53.7 W  
58.4 W  
1.65 V  
12.1 A  
7.2 A  
85°C  
2167 (3000+)  
Notes:  
1. See Figure 3, "AMD Athlon™ XP Processor Model 10 Power Management States" on page 9.  
2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the  
process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified  
current.  
3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant  
disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of  
2003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and  
AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.  
4. The Stop Grant current consumption is characterized at 50°C and not tested.  
5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or  
instruction sequences under normal system operation at nominal V  
. Thermal solutions must monitor the temperature of  
CC_CORE  
the processor to prevent the processor from exceeding its maximum die temperature.  
Chapter 6  
Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications  
21  
         
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
6.2  
Advanced 333 FSB AMD Athlon™ XP Processor Model 10  
SYSCLK and SYSCLK# AC Characteristics  
Table 2 shows the SYSCLK/SYSCLK# differential clock AC  
characteristics of this processor.  
Table 2. Advanced 333 FSB SYSCLK and SYSCLK# AC Characteristics  
Symbol  
Parameter Description  
Clock Frequency  
Minimum  
Maximum  
Units  
Notes  
50  
30%  
6
166  
MHz  
1
Duty Cycle  
70%  
t1  
t2  
t3  
t4  
t5  
Period  
ns  
ns  
ns  
ns  
ns  
ps  
2, 3  
High Time  
Low Time  
Fall Time  
1.0  
1.0  
2
2
Rise Time  
Period Stability  
± 300  
Notes:  
1. The AMD Athlon™ system bus operates at twice this clock frequency.  
2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL  
to track the jitter. The –20dB attenuation point, as measured into a 20- or 30-pF load must be less than 500 kHz.  
3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread  
spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.  
AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a  
maximum rate of 100 kHz.  
Figure 8 shows a sample waveform of the SYSCLK signal.  
t
2
V
V
Threshold-AC  
CROSS  
t
3
t
t
4
5
t
1
Figure 8. SYSCLK Waveform  
22 Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications  
Chapter 6  
         
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
6.3  
Advanced 333 FSB AMD Athlon™ System Bus  
AC Characteristics  
The AC characteristics of the AMD Athlon system bus of this  
processor are shown in Table 3. The parameters are grouped  
based on the source or destination of the signals involved.  
Table 3. Advanced 333 FSB AMD Athlon™ System Bus AC Characteristics  
Group  
Symbol  
Parameter  
Output Rise Slew Rate  
Output Fall Slew Rate  
Min  
1
Max  
Units Notes  
TRISE  
TFALL  
3
3
V/ns  
V/ns  
1
1
All Signals  
1
Output skew with respect to a  
different clock edge  
TSKEW-DIFFEDGE  
770  
ps  
2
TSU  
Input Data Setup Time  
Input Data Hold Time  
Capacitance on input clocks  
Capacitance on output clocks  
RSTCLK to Output Valid  
Setup to RSTCLK  
300  
300  
4
ps  
ps  
pF  
pF  
ps  
ps  
ps  
3
3
Forward  
Clocks  
THD  
CIN  
25  
12  
COUT  
TVAL  
TSU  
4
800  
500  
500  
2000  
4, 5  
4, 6  
4, 6  
Sync  
THD  
Hold from RSTCLK  
Notes:  
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.  
2. is the maximum skew within a clock forwarded group between any two signals or between any signal and its  
T
SKEW-DIFFEDGE  
forward clock, as measured at the package, with respect to different clock edges.  
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.  
4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.  
5.  
6.  
T
is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.  
VAL  
T
is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. T is hold of CONNECT/CLKFWDRST from rising edge of  
SU  
HD  
RSTCLK.  
Chapter 6  
Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications  
23  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
6.4  
Advanced 333 FSB AMD Athlon™ System Bus DC  
Characteristics  
Table 4 shows the DC characteristics of the AMD Athlon  
system bus for this processor.  
Table 4. Advanced 333 FSB AMD Athlon™ System Bus DC Characteristics  
Symbol  
Parameter  
Condition  
Min  
Max  
Units Notes  
(0.5 x VCC_CORE) (0.5 x VCC_CORE  
)
VREF  
DC Input Reference Voltage  
mV  
1
–50  
+50  
IVREF_LEAK_P VREF Tristate Leakage Pullup  
VIN = VREF Nominal  
–100  
µA  
µA  
mV  
mV  
IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN = VREF Nominal  
100  
VIH  
VIL  
VREF +200  
–500  
VCC_CORE +500  
VREF –200  
Input High Voltage  
Input Low Voltage  
V
IN = VSS  
ILEAK_P  
ILEAK_N  
Tristate Leakage Pullup  
–1  
mA  
mA  
(Ground)  
V
IN = VCC_CORE  
Nominal  
Tristate Leakage Pulldown  
1
CIN  
Input Pin Capacitance  
4
7
pF  
RON  
0.90 x RsetN,P  
1.1 x RsetN,P  
Output Resistance  
2
2
2
RsetP  
RsetN  
Notes:  
Impedance Set Point, P Channel  
Impedance Set Point, N Channel  
40  
40  
70  
70  
1.  
V
is nominally set to 50% of V  
with actual values that are specific to motherboard design implementation. V must be  
REF  
CC_CORE REF  
created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the 50 mV specification listed  
above.  
2. Measured at V  
/ 2.  
CC_CORE  
24  
Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications  
Chapter 6  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
7
Advanced 400 Front-Side Bus AMD Athlon™ XP  
Processor Model 10 Specifications  
This chapter describes the electrical specifications that are  
unique to the advanced 400 front-side bus (FSB)  
AMD Athlon™ XP processor model 10.  
7.1  
Electrical and Thermal Specifications for the Advanced 400 FSB  
AMD Athlon™ XP Processor Model 10  
Table 5 shows the electrical and thermal specifications in the  
C0 working state and the S1 Stop Grant state for this processor.  
Table 5. Electrical and Thermal Specifications for the Advanced 400 FSB AMD Athlon™ XP Processor  
Model 10  
ICC (Processor Current)  
VCC_CORE  
(Core  
Voltage)  
Thermal Power5  
Frequency in MHz  
(Model Number)  
Maximum Die  
Temperature  
Stop Grant S11, 2, 3, 4  
Working State C0  
Maximum Typical Maximum Typical Maximum Typical  
41.4 A  
46.5 A  
32.5 A  
36.6 A  
68.3 W  
76.8 W  
53.7 W  
60.4 W  
2100 (3000+)  
1.65 V  
12.1 A  
7.2 A  
85°C  
2200 (3200+)  
Notes:  
1. See Figure 3, "AMD Athlon™ XP Processor Model 10 Power Management States" on page 9.  
2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the  
process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified  
current.  
3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant  
disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of  
2003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and  
AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.  
4. The Stop Grant current consumption is characterized at 50°C and not tested.  
5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or  
instruction sequences under normal system operation at nominal V  
. Thermal solutions must monitor the temperature of  
CC_CORE  
the processor to prevent the processor from exceeding its maximum die temperature.  
Chapter 7  
Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications  
25  
         
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
7.2  
Advanced 400 FSB AMD Athlon™ XP Processor Model 10  
SYSCLK and SYSCLK# AC Characteristics  
Table 6 shows the SYSCLK/SYSCLK# differential clock AC  
characteristics of this processor.  
Table 6. Advanced 400 FSB SYSCLK and SYSCLK# AC Characteristics  
Symbol  
Parameter Description  
Clock Frequency  
Minimum  
Maximum  
Units  
Notes  
50  
30%  
5
200  
MHz  
1
Duty Cycle  
70%  
t1  
t2  
t3  
t4  
t5  
Period  
ns  
ns  
ns  
ns  
ns  
ps  
2, 3  
High Time  
Low Time  
Fall Time  
1.0  
1.0  
1.5  
1.5  
Rise Time  
Period Stability  
± 300  
Notes:  
1. The AMD Athlon™ system bus operates at twice this clock frequency.  
2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL  
to track the jitter. The –20dB attenuation point, as measured into a 20- or 30-pF load must be less than 500 kHz.  
3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread  
spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.  
AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a  
maximum rate of 100 kHz.  
Figure 9 shows a sample waveform of the SYSCLK signal.  
t
2
V
V
Threshold-AC  
CROSS  
t
3
t
t
4
5
t
1
Figure 9. SYSCLK Waveform  
26 Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications  
Chapter 7  
         
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
7.3  
Advanced 400 FSB AMD Athlon™ System Bus  
AC Characteristics  
The AC characteristics of the AMD Athlon system bus of this  
processor are shown in Table 7. The parameters are grouped  
based on the source or destination of the signals involved.  
Table 7. Advanced 400 FSB AMD Athlon™ System Bus AC Characteristics  
Group  
Symbol  
Parameter  
Output Rise Slew Rate  
Output Fall Slew Rate  
Min  
1
Max  
Units Notes  
TRISE  
TFALL  
3
3
V/ns  
V/ns  
1
1
All Signals  
1
Output skew with respect to a  
different clock edge  
TSKEW-DIFFEDGE  
500  
ps  
2
TSU  
Input Data Setup Time  
Input Data Hold Time  
Capacitance on input clocks  
Capacitance on output clocks  
RSTCLK to Output Valid  
Setup to RSTCLK  
300  
300  
4
ps  
ps  
pF  
pF  
ps  
ps  
ps  
3
3
Forward  
Clocks  
THD  
CIN  
25  
12  
COUT  
TVAL  
TSU  
4
800  
500  
500  
2000  
4, 5  
4, 6  
4, 6  
Sync  
THD  
Hold from RSTCLK  
Notes:  
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.  
2. is the maximum skew within a clock forwarded group between any two signals or between any signal and its  
T
SKEW-DIFFEDGE  
forward clock, as measured at the package, with respect to different clock edges.  
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.  
4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.  
5.  
6.  
T
is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.  
VAL  
T
is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. T is hold of CONNECT/CLKFWDRST from rising edge of  
SU  
HD  
RSTCLK.  
Chapter 7  
Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications  
27  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
7.4  
Advanced 400 FSB AMD Athlon™ System Bus DC  
Characteristics  
Table 8 shows the DC characteristics of the AMD Athlon  
system bus for this processor.  
Table 8. Advanced 400 FSB AMD Athlon™ System Bus DC Characteristics  
Symbol  
Parameter  
Condition  
Min  
Max  
Units Notes  
(0.5 x VCC_CORE) (0.5 x VCC_CORE  
)
VREF  
DC Input Reference Voltage  
mV  
1
–50  
+50  
IVREF_LEAK_P VREF Tristate Leakage Pullup  
VIN = VREF Nominal  
–100  
µA  
µA  
mV  
mV  
IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN = VREF Nominal  
100  
VIH  
VIL  
VREF +150  
–500  
VCC_CORE +500  
VREF –150  
Input High Voltage  
Input Low Voltage  
V
IN = VSS  
ILEAK_P  
ILEAK_N  
Tristate Leakage Pullup  
–1  
mA  
mA  
(Ground)  
V
IN = VCC_CORE  
Nominal  
Tristate Leakage Pulldown  
1
CIN  
Input Pin Capacitance  
4
7
pF  
RON  
0.90 x RsetN,P  
1.1 x RsetN,P  
Output Resistance  
2
2
2
RsetP  
RsetN  
Notes:  
Impedance Set Point, P Channel  
Impedance Set Point, N Channel  
40  
40  
70  
70  
1.  
V
is nominally set to 50% of V  
with actual values that are specific to motherboard design implementation. V must be  
REF  
CC_CORE REF  
created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the 50 mV specification listed  
above.  
2. Measured at V  
/ 2.  
CC_CORE  
28  
Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications  
Chapter 7  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
8
Electrical Data  
This chapter describes the electrical characteristics that apply  
to all desktop AMD Athlon™ XP processors model 10.  
8.1  
Conventions  
The conventions used in this chapter are as follows:  
Current specified as being sourced by the processor is  
negative.  
Current specified as being sunk by the processor is positive.  
8.2  
Interface Signal Groupings  
The electrical data in this chapter is presented separately for  
each signal group.  
Table 9 defines each group and the signals contained in each  
group.  
Table 9. Interface Signal Groupings  
Signal Group  
Signals  
Notes  
VID[4:0], VCCA, VCC_CORE, COREFB,  
COREFB#  
Power  
Frequency  
FID[3:0]  
SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN#  
System Clocks and RSTCLK/RSTCLK#), PLLBYPASSCLK#,  
PLLBYPASSCLK  
Chapter 8  
Electrical Data  
29  
         
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 9. Interface Signal Groupings (continued)  
Signal Group  
Signals  
Notes  
SADDIN[14:2]#, SADDOUT[14:2]#,  
SADDINCLK#, SADDOUTCLK#, SFILLVAL#,  
AMD Athlon™ SDATAINVAL#, SDATAOUTVAL#,  
System Bus  
Southbridge  
SDATA[63:0]#, SDATAINCLK[3:0]#,  
SDATAOUTCLK[3:0]#, CLKFWDRST,  
PROCRDY, CONNECT  
FERR, IGNNE#, STPCLK#, FLUSH#  
JTAG  
Test  
TMS, TCK, TRST#, TDI, TDO  
PLLBYPASS#, PLLTEST#, PLLMON1,  
PLLMON2, SCANCLK1, SCANCLK2,  
SCANSHIFTEN, SCANINTEVAL, ANALOG  
Miscellaneous DBREQ#, DBRDY, PWROK  
APIC  
PICD[1:0]#, PICCLK  
Thermal  
THERMDA, THERMDC  
8.3  
Voltage Identification (VID[4:0])  
Table 10 shows the VID[4:0] DC Characteristics. For more infor-  
mation on VID[4:0] DC Characteristics, see “VID[4:0] Pins” on  
Table 10. VID[4:0] DC Characteristics  
Parameter  
Description  
Output Current Low  
Output High Voltage  
Min  
6 mA  
Max  
IOL  
VOH  
5.25 V *  
Note:  
*
The VID pins are either open circuit or pulled to ground. It is recommended that these pins  
are not pulled above 5.25 V, which is 5.0 V + 5%.  
30  
Electrical Data  
Chapter 8  
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
8.4  
Frequency Identification (FID[3:0])  
Table 11 shows the FID[3:0] DC characteristics. For more  
Table 11. FID[3:0] DC Characteristics  
Parameter  
IOL  
Description  
Output Current Low  
Min  
Max  
6 mA  
2.625 V 1  
| VOH – VCC_CORE | 1.60 V 2  
VOH  
Output High Voltage  
Note:  
1. The FID pins must not be pulled above 2.625 V, which is equal to 2.5 V plus a maximum of five percent.  
2. Refer to “VCC_2.5V Generation Circuit” found in the section, “Motherboard Required Circuits,” of the AMD Athlon™ Processor-  
Based Motherboard Design Guide, order# 24363.  
8.5  
VCCA AC and DC Characteristics  
Table 12 shows the AC and DC characteristics for VCCA. For more information, see  
Table 12. VCCA AC and DC Characteristics  
Symbol  
Parameter  
Min  
2.25  
0
Nominal  
Max  
2.75  
Units  
Notes  
V
1
2
VVCCA  
VCCA Pin Voltage  
VCCA Pin Current  
2.5  
| VVCCA – VCC_CORE | 1.60 V  
IVCCA  
50  
mA/GHz  
3
Notes:  
1. Minimum and Maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted.  
2. For more information, refer to the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.  
3. Measured at 2.5 V.  
8.6  
Decoupling  
See the AMD Athlon™ Processor-Based Motherboard Design  
Guide, order# 24363, or contact your local AMD office for  
information about the decoupling required on the motherboard  
for use with the AMD Athlon XP processor model 10.  
Chapter 8  
Electrical Data  
31  
             
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
8.7  
V
Characteristics  
CC_CORE  
Table 13 shows the AC and DC characteristics for V  
.
CC_CORE  
See Figure 10 on page 33 for a graphical representation of the  
waveform.  
V
CC_CORE  
Table 13. V  
Symbol  
AC and DC Characteristics  
CC_CORE  
Parameter  
Limit in Working State  
Units  
*
*
VCC_CORE_DC_MAX  
VCC_CORE_DC_MIN  
VCC_CORE_AC_MAX  
Maximum static voltage above VCC_CORE_NOM  
50  
mV  
Maximum static voltage below VCC_CORE_NOM  
–50  
150  
mV  
mV  
*
Maximum excursion above VCC_CORE_NOM  
*
VCC_CORE_AC_MIN  
Maximum excursion below VCC_CORE_NOM  
–100  
10  
mV  
µs  
µs  
tMAX_AC  
Maximum excursion time for AC transients  
Negative excursion time for AC transients  
tMIN_AC  
5
Note:  
*
All voltage measurements are taken differentially at the COREFB/COREFB# pins.  
32  
Electrical Data  
Chapter 8  
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Figure 10 shows the processor core voltage (V  
)
CC_CORE  
waveform response to perturbation. The t  
(negative AC  
MIN_AC  
transient excursion time) and t  
(positive AC transient  
MAX_AC  
excursion time) represent the maximum allowable time below  
or above the DC tolerance thresholds.  
t
max_AC  
V
CC_CORE_AC_MAX  
V
V
CC_CORE_DC_MAX  
V
CC_CORE_NOM  
CC_CORE_DC_MIN  
V
CC_CORE_AC_MIN  
t
min_AC  
I
I
CORE_MAX  
dI /dt  
CORE_MIN  
Figure 10. V  
Voltage Waveform  
CC_CORE  
Chapter 8  
Electrical Data  
33  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
8.8  
Absolute Ratings  
The AMD Athlon XP processor model 10 should not be  
subjected to conditions exceeding the absolute ratings, as such  
conditions can adversely affect long-term reliability or result in  
functional damage.  
Table 14 lists the maximum absolute ratings of operation for the  
AMD Athlon XP processor model 10.  
Table 14. Absolute Ratings  
Parameter  
Description  
Min  
Max  
VCC_CORE  
VCCA  
V
V
CC_CORE Max + 0.5 V  
Processor core voltage supply  
–0.5 V  
–0.5 V  
–0.5 V  
Processor PLL voltage supply  
Voltage on any signal pin  
VCCA Max + 0.5 V  
V
CC_CORE Max + 0.5 V  
PIN  
TSTORAGE  
Storage temperature of processor  
–40ºC  
100ºC  
34  
Electrical Data  
Chapter 8  
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
8.9  
SYSCLK and SYSCLK# DC Characteristics  
Table 15 shows the DC characteristics of the SYSCLK and  
SYSCLK# differential clocks. The SYSCLK signal represents  
CLKIN and RSTCLK tied together while the SYSCLK# signal  
represents CLKIN# and RSTCLK# tied together. For more  
information about SYSCLK and SYSCLK#, see “SYSCLK and  
Table 15. SYSCLK and SYSCLK# DC Characteristics  
Symbol  
Description  
Min  
Max  
Units  
Crossing before transition is detected (DC)  
400  
mV  
VThreshold-DC  
Crossing before transition is detected (AC)  
450  
–1  
mV  
mA  
mA  
mV  
pF  
VThreshold-AC  
Leakage current through P-channel pullup to VCC_CORE  
ILEAK_P  
Leakage current through N-channel pulldown to VSS (Ground)  
Differential signal crossover  
1
ILEAK_N  
V
CC_CORE / 2 100  
VCROSS  
Capacitance *  
4
25 *  
C
PIN  
Note:  
*
The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.  
SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.  
Figure 11 shows the DC characteristics of the SYSCLK and  
SYSCLK# signals.  
V
V
= 400mV  
V
= 450mV  
Threshold-AC  
CROSS  
Threshold-DC  
Figure 11. SYSCLK and SYSCLK# Differential Clock Signals  
Chapter 8  
Electrical Data  
35  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
8.10  
General AC and DC Characteristics  
Table 16 shows the AMD Athlon XP processor model 10 AC and  
DC characteristics of the Southbridge, JTAG, test, and miscel-  
laneous pins.  
Table 16. General AC and DC Characteristics  
Symbol  
Parameter Description  
Input High Voltage  
Condition  
Min  
Max  
Units Notes  
(VCC_CORE / 2) +  
200 mV  
VCC_CORE  
300 mV  
+
+
VIH  
V
1, 2  
1, 2  
VIL  
Input Low Voltage  
–300  
350  
mV  
mV  
mV  
mA  
VCC_CORE  
400  
VCC_CORE  
300  
VOH  
VOL  
Output High Voltage  
Output Low Voltage  
Tristate Leakage Pullup  
–300  
400  
VIN = VSS  
ILEAK_P  
–1  
(Ground)  
V
IN = VCC_CORE  
Nominal  
ILEAK_N  
Tristate Leakage Pulldown  
600  
–6  
µA  
IOH  
Output High Current  
mA  
mA  
ns  
3
3
IOL  
Output Low Current  
6
TSU  
Sync Input Setup Time  
Sync Input Hold Time  
2.0  
0.0  
0.0  
4, 5  
4, 5  
5
THD  
ps  
TDELAY  
Notes:  
Output Delay with respect to RSTCLK  
6.1  
ns  
1. Characterized across DC supply voltage range.  
2. Values specified at nominal V  
. Scale parameters between V  
minimum and V  
maximum.  
CC_CORE.  
CC_CORE  
and I are measured at V maximum and V minimum, respectively.  
OL OH OL OH  
CC_CORE.  
3.  
I
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.  
5. These are aggregate numbers.  
6. Edge rates indicate the range over which inputs were characterized.  
7. In asynchronous operation, the signal must persist for this time to enable capture.  
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.  
9. The approximate value for standard case in normal mode operation.  
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.  
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.  
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.  
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other  
configurations.  
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more  
information.  
36  
Electrical Data  
Chapter 8  
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 16. General AC and DC Characteristics (continued)  
Symbol  
Parameter Description  
Input Time to Acquire  
Condition  
Min  
20.0  
40.0  
1.0  
Max  
Units Notes  
TBIT  
ns  
ns  
7, 8  
9–13  
6
TRPT  
TRISE  
TFALL  
Input Time to Reacquire  
Signal Rise Time  
3.0  
3.0  
12  
V/ns  
V/ns  
pF  
Signal Fall Time  
1.0  
6
C
Pin Capacitance  
4
PIN  
TVALID  
Time to data valid  
100  
ns  
14  
Notes:  
1. Characterized across DC supply voltage range.  
2. Values specified at nominal V  
. Scale parameters between V  
minimum and V  
maximum.  
CC_CORE.  
CC_CORE  
and I are measured at V maximum and V minimum, respectively.  
OL OH OL OH  
CC_CORE.  
3.  
I
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.  
5. These are aggregate numbers.  
6. Edge rates indicate the range over which inputs were characterized.  
7. In asynchronous operation, the signal must persist for this time to enable capture.  
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.  
9. The approximate value for standard case in normal mode operation.  
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.  
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.  
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.  
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other  
configurations.  
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more  
information.  
Chapter 8  
Electrical Data  
37  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
8.11  
Open Drain Test Circuit  
Figure 12 is a test circuit that may be used on automated test  
equipment (ATE) to test for validity on open drain pins.  
page 36 for timing requirements.  
1
V
Termination  
50 3%  
Open-Drain Pin  
2
I
= Output Current  
OL  
Notes:  
1. V  
= 1.2 V for VID and FID pins  
= 1.0 V for APIC pins  
Termination  
Termination  
V
2. I = –6 mA for VID and FID pins  
OL  
I
= –9 mA for APIC pins  
OL  
Figure 12. General ATE Open-Drain Test Circuit  
38  
Electrical Data  
Chapter 8  
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
8.12  
Thermal Diode Characteristics  
The AMD Athlon XP processor model 10 provides a diode that  
can be used in conjunction with an external temperature sensor  
to determine the die temperature of the processor. The diode  
anode (THERMDA) and cathode (THERMDC) are available as  
pins on the processor, as described in “THERMDA and  
For information about thermal design for the AMD Athlon XP  
processor model 10, including layout and airflow  
considerations, see the AMD Processor Thermal, Mechanical, and  
Chassis Cooling Design Guide, order# 23794, and the cooling  
guidelines on http://www.amd.com.  
Thermal Diode  
Electrical  
Characteristics  
Table 17 shows the AMD Athlon XP processor model 10  
characteristics of the on-die thermal diode. For information  
about calculations for the ideal diode equation and  
temperature offset correction, see Appendix A, "Thermal  
Diode Calculations," on page 77.  
Table 17. Thermal Diode Electrical Characteristics  
Parameter  
Symbol  
I
Min  
Nom  
Max  
Units  
Notes  
1
Description  
Sourcing current  
5
300  
µA  
Lumped ideality  
factor  
nf, lumped  
1.00000 1.00374 1.00900  
2, 3, 4  
nf, actual  
RT  
Actual ideality factor  
Series Resistance  
1.00261  
0.93  
3, 4  
3, 4  
Notes:  
1. The sourcing current should always be used in forward bias only.  
2. Characterized at 95°C with a forward bias current pair of 10 µA and 100 µA. AMD  
recommends using a minimum of two sourcing currents to accurately measure the  
temperature of the thermal diode.  
3. Not 100% tested. Specified by design and limited characterization.  
4. The lumped ideality factor adds the effect of the series resistance term to the actual ideality  
factor. The series resistance term indicates the resistance from the pins of the processor to the  
on-die thermal diode. The value of the lumped ideality factor depends on the sourcing current  
pair used.  
Thermal Protection  
Characterization  
The following section describes parameters relating to thermal  
protection. The implementation of thermal control circuitry to  
control processor temperature is left to the manufacturer to  
determine how to implement.  
Chapter 8  
Electrical Data  
39  
       
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Thermal limits in motherboard design are necessary to protect  
the processor from thermal damage. T is the  
SHUTDOWN  
temperature for thermal protection circuitry to initiate  
shutdown of the processor. T is the maximum time  
SD_DELAY  
allowed from the detection of the over-temperature condition to  
processor shutdown to prevent thermal damage to the  
processor.  
Systems that do not implement thermal protection circuitry or  
that do not react within the time specified by T  
can  
SD_DELAY  
cause thermal damage to the processor during the unlikely  
events of fan failure or powering up the processor without a  
heat-sink. The processor relies on thermal circuitry on the  
motherboard to turn off the regulated core voltage to the  
processor in response to a thermal shutdown event.  
Thermal protection circuitry reference designs and thermal  
solution guidelines are found in the following documents:  
AMD Athlon™ Processor-Based Motherboard Design Guide,  
order# 24363  
AMD Thermal, Mechanical, and Chassis Cooling Design Guide,  
order# 23794  
See http://www.amd.com for more information about thermal  
solutions.  
Table 18 shows the T  
and T  
specifications  
SD_DELAY  
SHUTDOWN  
for circuitry in motherboard design necessary for thermal  
protection of the processor.  
Table 18. Guidelines for Platform Thermal Protection of the Processor  
Symbol  
Parameter Description  
Max Units Notes  
TSHUTDOWN  
Thermal diode shutdown temperature for processor protection  
125  
500  
°C  
1, 2, 3  
1, 3  
TSD_DELAY Maximum allowed time from TSHUTDOWN detection to processor shutdown  
ms  
Notes:  
1. The thermal diode is not 100% tested, it is specified by design and limited characterization.  
2. The thermal diode is capable of responding to thermal events of 40°C/s or faster.  
3. The AMD Athlon™ XP processor model 10 provides a thermal diode for measuring die temperature of the processor. The  
processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a  
thermal shutdown event. Refer to AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363, for thermal  
protection circuitry designs.  
40  
Electrical Data  
Chapter 8  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
8.13  
APIC Pins AC and DC Characteristics  
Table 19 shows the AMD Athlon XP processor model 10 AC and  
DC characteristics of the APIC pins.  
Table 19. APIC Pin AC and DC Characteristics  
Symbol Parameter Description  
Condition  
Min  
Max  
2.625  
Units Notes  
1.7  
V
V
1, 2  
3
VIH  
VIL  
Input High Voltage  
Input Low Voltage  
Output High Voltage  
V
CC_CORE < VCC_CORE_MAX  
| VIH – VCC_CORE | 1.60 V  
–300  
700  
2.625  
mV  
V
1
2
VOH  
VCC_CORE < VCC_CORE_MAX  
| VOH – VCC_CORE | 1.60 V  
V
3
VOL  
Output Low Voltage  
–300  
–1  
400  
1
mV  
mA  
ILEAK_P  
V
IN = VSS (Ground)  
VIN = 2.5 V  
Tristate Leakage Pullup  
Tristate Leakage  
Pulldown  
ILEAK_N  
mA  
IOL  
VOL Max  
Output Low Current  
Signal Rise Time  
Signal Fall Time  
Setup Time  
9
1.0  
1.0  
1
mA  
V/ns  
V/ns  
ns  
TRISE  
TFALL  
TSU  
3.0  
3.0  
3
3
THD  
Hold Time  
1
ns  
C
Pin Capacitance  
4
12  
pF  
PIN  
Notes:  
1. Characterized across DC supply voltage range.  
2. The 2.625-V value is equal to 2.5 V plus a maximum of five percent.  
3. Refer to “VCC_2.5V Generation Circuit” found in the section, “Motherboard Required Circuits,” of the AMD Athlon™ Processor-  
Based Motherboard Design Guide, order# 24363.  
4. Edge rates indicate the range for characterizing the inputs.  
Chapter 8  
Electrical Data  
41  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
42  
Electrical Data  
Chapter 8  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
9
Signal and Power-Up Requirements  
The AMD Athlon™ XP processor model 10 is designed to  
provide functional operation if the voltage and temperature  
parameters are within the limits of normal operating ranges.  
9.1  
Power-Up Requirements  
Signal Sequence and  
Timing Description  
Figure 13 shows the relationship between key signals in the  
system during a power-up sequence. This figure details the  
requirements of the processor.  
3.3 V Supply  
VCCA (2.5 V)  
(for PLL)  
V
2
CC_CORE  
Warm reset  
condition  
1
RESET#  
6
4
NB_RESET#  
5
PWROK  
FID[3:0]  
8
7
3
System Clock  
Figure 13. Signal Relationship Requirements During Power-Up Sequence  
Notes: 1. Figure 13 represents several signals generically by using names not necessarily consistent  
with any pin lists or schematics.  
Chapter 9  
Signal and Power-Up Requirements  
43  
         
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Power-Up Timing Requirements. The signal timing requirements are  
as follows:  
1. RESET# must be asserted before PWROK is asserted.  
The AMD Athlon XP processor model 10 does not set the  
correct clock multiplier if PWROK is asserted prior to a  
RESET# assertion. It is recommended that RESET# be  
asserted at least 10 nanoseconds prior to the assertion of  
PWROK.  
In practice, a Southbridge asserts RESET# milliseconds  
before PWROK is asserted.  
2. All motherboard voltage planes must be within  
specification before PWROK is asserted.  
PWROK is an output of the voltage regulation circuit on the  
motherboard. PWROK indicates that V  
and all  
CC_CORE  
other voltage planes in the system are within specification.  
The motherboard is required to delay PWROK assertion for  
a minimum of three milliseconds from the 3.3 V supply  
being within specification. This delay ensures that the  
system clock (SYSCLK/SYSCLK#) is operating within  
specification when PWROK is asserted.  
The processor core voltage, V  
, must be within  
CC_CORE  
specification as dictated by the VID[4:0] pins driven by the  
processor before PWROK is asserted. Before PWROK  
assertion, the AMD Athlon processor is clocked by a ring  
oscillator.  
The processor PLL is powered by VCCA. The processor PLL  
does not lock if VCCA is not high enough for the processor  
logic to switch for some period before PWROK is asserted.  
VCCA must be within specification at least five  
microseconds before PWROK is asserted.  
In practice VCCA, V  
, and all other voltage planes  
CC_CORE  
must be within specification for several milliseconds before  
PWROK is asserted.  
After PWROK is asserted, the processor PLL locks to its  
operational frequency.  
3. The system clock (SYSCLK/SYSCLK#) must be running  
before PWROK is asserted.  
When PWROK is asserted, the processor switches from  
driving the internal processor clock grid from the ring  
oscillator to driving from the PLL. The reference system  
44  
Signal and Power-Up Requirements  
Chapter 9  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
clock must be valid at this time. The system clocks are  
designed to be running after 3.3 V has been within  
specification for three milliseconds.  
4. PWROK assertion to deassertion of RESET#  
The duration of RESET# assertion during cold boots is  
intended to satisfy the time it takes for the PLL to lock with  
a less than 1 ns phase error. The processor PLL begins to  
run after PWROK is asserted and the internal clock grid is  
switched from the ring oscillator to the PLL. The PLL lock  
time may take from hundreds of nanoseconds to tens of  
microseconds. It is recommended that the minimum time  
between PWROK assertion to the deassertion of RESET# be  
at least 1.0 milliseconds. Southbridges enforce a delay of  
1.5 to 2.0 milliseconds between PWRGD (Southbridge  
version of PWROK) assertion and NB_RESET# deassertion.  
5. PWROK must be monotonic and meet the timing  
requirements as defined in Table 12, “General AC and DC  
Characteristics,” on page 34. The processor should not  
switch between the ring oscillator and the PLL after the  
initial assertion of PWROK.  
6. NB_RESET# must be asserted (causing CONNECT to also  
assert) before RESET# is deasserted. In practice all  
Southbridges enforce this requirement.  
If NB_RESET# does not assert until after RESET# has  
deasserted, the processor misinterprets the CONNECT  
assertion (due to NB_RESET# being asserted) as the  
beginning of the SIP transfer. There must be sufficient  
overlap in the resets to ensure that CONNECT is sampled  
asserted by the processor before RESET# is deasserted.  
7. The FID[3:0] signals are valid within 100 ns after PWROK is  
asserted. The chipset must not sample the FID[3:0] signals  
until they become valid. Refer to the AMD Athlon™  
Processor-Based Motherboard Design Guide, order# 24363, for  
the specific implementation and additional circuitry  
required.  
8. The FID[3:0] signals become valid within 100 ns after  
RESET# is asserted. Refer to the AMD Athlon™ Processor-  
Based Motherboard Design Guide, order# 24363, for the  
specific implementation and additional circuitry required.  
Chapter 9  
Signal and Power-Up Requirements  
45  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Clock Multiplier  
Selection (FID[3:0])  
The chipset samples the FID[3:0] signals in a chipset-specific  
manner from the processor and uses this information to  
determine the correct serial initialization packet (SIP). The  
chipset then sends the SIP information to the processor for  
configuration of the AMD Athlon system bus for the clock  
multiplier that determines the processor frequency indicated  
by the FID[3:0] code. The SIP is sent to the processor using the  
SIP protocol. This protocol uses the PROCRDY, CONNECT, and  
CLKFWDRST signals, that are synchronous to SYSCLK.  
For more information about FID[3:0], see “FID[3:0] Pins” on  
Serial Initialization Packet (SIP) Protocol. Refer to AMD Athlon™ and  
AMD Duron™ System Bus Specification, order# 21902 for details  
of the SIP protocol.  
9.2  
Processor Warm Reset Requirements  
Northbridge Reset  
Pins  
RESET# cannot be asserted to the processor without also being  
asserted to the Northbridge. RESET# to the Northbridge is the  
same as PCI RESET#. The minimum assertion for PCI RESET#  
is one millisecond. Southbridges enforce a minimum assertion  
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0  
milliseconds.  
46  
Signal and Power-Up Requirements  
Chapter 9  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
10  
Mechanical Data  
The AMD Athlon™ XP processor model 10 connects to  
themotherboard through a Pin Grid Array (PGA) socket named  
Socket A. This processor utilizes the Organic Pin Grid Array  
(OPGA) package type described in this chapter. For more  
information, see the AMD Athlon™ Processor-Based Motherboard  
Design Guide, order# 24363.  
10.1  
Die Loading  
The processor die on the OPGA package is exposed at the top of  
the package. This feature facilitates heat transfer from the die  
to an approved heat sink. Any heat sink design should avoid  
loads on corners and edges of die. The OPGA package has  
compliant pads that serve to bring surfaces in planar contact.  
Tool-assisted zero insertion force sockets should be designed so  
that no load is placed on the ceramic substrate of the package.  
Table 20 shows the mechanical loading specifications for the  
processor die. It is critical that the mechanical loading of the  
heat sink does not exceed the limits shown in Table 20.  
Table 20. Mechanical Loading  
Location  
Die Surface  
Dynamic (MAX)  
Static (MAX)  
Units  
lbf  
Note  
100  
10  
30  
10  
1
2
Die Edge  
lbf  
Notes:  
1. Load specified for coplanar contact to die surface.  
2. Load defined for a surface at no more than a two-degree angle of inclination to die surface.  
Chapter 10  
Mechanical Data  
47  
       
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
10.2  
AMD Athlon™ XP Processor Model 10 Part Number 27488  
OPGA Package Dimensions  
Table 21 shows the part number 27488 OPGA package  
dimensions in millimeters assigned to the letters and symbols  
used in the 27488 package diagram, Figure 14 on page 49.  
Table 21. Dimensions for the AMD Athlon™ XP Processor Model 10 Part  
Number 27488 OPGA Package  
Minimum  
Dimension1 Dimension1  
49.27 49.78  
45.72 BSC  
Maximum  
Minimum  
Maximum  
Letter or  
Symbol  
Letter or  
Symbol  
Dimension1 Dimension1  
D/E  
D1/E1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
E2  
E9  
G/H  
A
1.66  
1.96  
4.50  
7.42 REF  
1.942 REF  
3.30  
10.78  
10.78  
8.13  
3.60  
11.33  
11.33  
8.68  
A1  
A2  
A3  
A4  
φP  
φb  
φb1  
S
1.00  
0.80  
0.116  
1.20  
0.88  
1.90  
6.60  
0.50  
12.33  
3.05  
12.88  
3.35  
0.43  
12.71  
13.26  
1.40 REF  
13.61 REF  
1.435  
3.05  
2.375  
3.31  
E3  
2.35  
7.87  
2.65  
8.42  
L
E4  
M
37  
E5  
7.87  
8.42  
N
453  
E6  
11.41  
11.41  
13.28  
11.96  
11.96  
13.83  
e
1.27 BSC  
2.54 BSC  
E7  
e1  
Mass2  
E8  
11.0 g REF  
Note:  
1. Dimensions are given in millimeters.  
2. The mass consists of the completed package, including processor, surface mounted parts and  
pins.  
48  
Mechanical Data  
Chapter 10  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Figure 14. AMD Athlon™ XP Processor Model 10 Part Number 27488 OPGA Package Diagram  
Chapter 10  
Mechanical Data  
49  
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
10.3  
AMD Athlon™ XP Processor Model 10 Part Number 27493  
OPGA Package Dimensions  
Table 22 shows the part number 27493 OPGA package  
dimensions in millimeters assigned to the letters and symbols  
shown in the 27493 package diagram, Figure 15 on page 51.  
Table 22. Dimensions for the AMD Athlon™ XP Processor Model 10 Part  
Number 27493 OPGA Package  
Minimum  
Dimension1 Dimension1  
49.27 49.78  
45.72 BSC  
Maximum  
Minimum  
Maximum  
Letter or  
Symbol  
Letter or  
Symbol  
Dimension1 Dimension1  
D/E  
D1/E1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
E2  
G/H  
A
4.50  
1.917 REF  
7.42 REF  
A1  
A2  
A3  
A4  
φP  
φb  
φb1  
S
0.977  
0.80  
0.116  
1.177  
0.88  
3.30  
10.78  
10.78  
8.13  
3.60  
11.33  
11.33  
8.68  
1.90  
6.60  
0.50  
12.33  
3.05  
12.88  
3.35  
0.43  
1.40 REF  
12.71  
13.26  
1.435  
3.05  
2.375  
3.31  
13.61 REF  
L
E3  
2.35  
7.87  
2.65  
8.42  
8.42  
11.96  
13.83  
1.96  
M
37  
E4  
N
453  
E5  
7.87  
e
1.27 BSC  
2.54 BSC  
E6  
11.41  
13.28  
1.66  
e1  
Mass2  
E8  
11.0 g REF  
E9  
Note:  
1. Dimensions are given in millimeters.  
2. The mass consists of the completed package, including processor, surface mounted parts and  
pins.  
50  
Mechanical Data  
Chapter 10  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Figure 15. AMD Athlon™ XP Processor Model 10 Part Number 27493 OPGA Package Diagram  
Chapter 10  
Mechanical Data  
51  
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
52  
Mechanical Data  
Chapter 10  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
11  
Pin Descriptions  
This chapter includes pin diagrams of the organic pin grid array  
(OPGA) for the AMD Athlon™ XP processor model 10, a listing  
of pin name abbreviations, and a cross-referenced listing of pin  
locations to signal names.  
11.1  
Pin Diagram and Pin Name Abbreviations  
Figure 16 on page 54 shows the staggered Pin Grid Array (PGA)  
for the AMD Athlon™ XP processor model 10. Because some of  
the pin names are too long to fit in the grid, they are  
abbreviated. Figure 17 on page 55 shows the bottomside view of  
the array. Table 23 on page 56 lists all the pins in alphabetical  
order by pin name, along with the abbreviation where  
necessary.  
Chapter 11  
Pin Descriptions  
53  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
54  
Pin Descriptions  
Chapter 11  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Chapter 11  
Pin Descriptions  
55  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 23. Pin Name Abbreviations  
Abbreviation  
Full Name  
A20M#  
Pin  
AE1  
Abbreviation  
Full Name  
Pin  
AA7  
KEY  
KEY  
KEY  
KEY  
KEY  
KEY  
KEY  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
AMD  
AH6  
AJ13  
AJ21  
AN17  
AL17  
AL23  
AG11  
AG13  
AK6  
AA1  
AA3  
AG1  
W1  
AG7  
AG9  
AG15  
AG17  
AG27  
AG29  
A19  
A31  
C13  
E25  
E33  
F8  
ANLOG  
ANALOG  
CLKFWDRST  
CLKIN  
CLKFR  
CNNCT  
CPR#  
CLKIN#  
CONNECT  
COREFB  
COREFB#  
CPU_PRESENCE#  
DBRDY  
DBREQ#  
FERR  
FID[0]  
F30  
G11  
G13  
G19  
G21  
G27  
G29  
G31  
H6  
FID[1]  
W3  
FID[2]  
Y1  
FID[3]  
Y3  
FLUSH#  
FSB_Sense[0]  
FSB_Sense[1]  
IGNNE#  
INIT#  
AL3  
AG31  
AH30  
AJ1  
FSB0  
FSB1  
AJ3  
INTR  
AL1  
AL21  
AN21  
G7  
H8  
K7CO  
K7CLKOUT  
K7CLKOUT#  
KEY  
H10  
H28  
H30  
H32  
J5  
K7CO#  
KEY  
G9  
KEY  
G15  
G17  
G23  
G25  
N7  
KEY  
J31  
KEY  
K8  
KEY  
K30  
L31  
KEY  
KEY  
Q7  
L35  
N31  
KEY  
Y7  
56  
Pin Descriptions  
Chapter 11  
   
Preliminary Information  
26237C—May 2003  
AMD Athlon™ XP Processor Model 10 Data Sheet  
Table 23. Pin Name Abbreviations (continued)  
Abbreviation  
Full Name  
Pin  
Q31  
Abbreviation  
Full Name  
Pin  
AJ19  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NMI  
S31  
AJ27  
AK8  
U31  
U37  
W7  
AL7  
AL9  
W31  
Y5  
AL11  
AL25  
AL27  
AM8  
AN7  
AN9  
AN11  
AN25  
AN27  
AN3  
N1  
Y31  
Y33  
AA5  
AA31  
AC7  
AC31  
AD8  
AD30  
AE7  
PICCLK  
AE31  
AF6  
PICD#0  
PICD[0]#  
N3  
PICD#1  
PLBYP#  
PLBYC  
PICD[1]#  
N5  
AF8  
PLLBYPASS#  
PLLBYPASSCLK  
PLLBYPASSCLK#  
PLLMON1  
PLLMON2  
PLLTEST#  
AJ25  
AN15  
AL15  
AN13  
AL13  
AC3  
AF10  
AF28  
AF30  
AF32  
AG5  
AG19  
AG21  
AG23  
AG25  
AH8  
AJ7  
PLBYC#  
PLMN1  
PLMN2  
PLTST#  
PRCRDY  
PROCREADY  
PWROK  
AN23  
AE3  
RESET#  
AG3  
AN19  
AL19  
AJ29  
AL29  
AG33  
AJ37  
AL35  
RCLK  
RSTCLK  
RCLK#  
SAI#0  
SAI#1  
SAI#2  
SAI#3  
SAI#4  
RSTCLK#  
SADDIN[0]#  
SADDIN[1]#  
SADDIN[2]#  
SADDIN[3]#  
SADDIN[4]#  
AJ9  
AJ11  
AJ15  
AJ17  
Chapter 11  
Pin Descriptions  
57  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 23. Pin Name Abbreviations (continued)  
Abbreviation  
SAI#5  
Full Name  
SADDIN[5]#  
Pin  
AE33  
Abbreviation  
SD#3  
Full Name  
SDATA[3]#  
Pin  
Y35  
SAI#6  
SADDIN[6]#  
AJ35  
AG37  
AL33  
AN37  
AL37  
AG35  
AN29  
AN35  
AN31  
AJ33  
J1  
SD#4  
SDATA[4]#  
SDATA[5]#  
SDATA[6]#  
SDATA[7]#  
SDATA[8]#  
SDATA[9]#  
SDATA[10]#  
SDATA[11]#  
SDATA[12]#  
SDATA[13]#  
SDATA[14]#  
SDATA[15]#  
SDATA[16]#  
SDATA[17]#  
SDATA[18]#  
SDATA[19]#  
SDATA[20]#  
SDATA[21]#  
SDATA[22]#  
SDATA[23]#  
SDATA[24]#  
SDATA[25]#  
SDATA[26]#  
SDATA[27]#  
SDATA[28]#  
SDATA[29]#  
SDATA[30]#  
SDATA[31]#  
SDATA[32]#  
SDATA[33]#  
SDATA[34]#  
SDATA[35]#  
SDATA[36]#  
U35  
U33  
S37  
SAI#7  
SADDIN[7]#  
SD#5  
SAI#8  
SADDIN[8]#  
SD#6  
SAI#9  
SADDIN[9]#  
SD#7  
S33  
SAI#10  
SAI#11  
SAI#12  
SAI#13  
SAI#14  
SAIC#  
SADDIN[10]#  
SADDIN[11]#  
SADDIN[12]#  
SADDIN[13]#  
SADDIN[14]#  
SADDINCLK#  
SADDOUT[0]#  
SADDOUT[1]#  
SADDOUT[2]#  
SADDOUT[3]#  
SADDOUT[4]#  
SADDOUT[5]#  
SADDOUT[6]#  
SADDOUT[7]#  
SADDOUT[8]#  
SADDOUT[9]#  
SADDOUT[10]#  
SADDOUT[11]#  
SADDOUT[12]#  
SADDOUT[13]#  
SADDOUT[14]#  
SADDOUTCLK#  
SCANCLK1  
SD#8  
AA33  
AE37  
AC33  
AC37  
Y37  
SD#9  
SD#10  
SD#11  
SD#12  
SD#13  
SD#14  
SD#15  
SD#16  
SD#17  
SD#18  
SD#19  
SD#20  
SD#21  
SD#22  
SD#23  
SD#24  
SD#25  
SD#26  
SD#27  
SD#28  
SD#29  
SD#30  
SD#31  
SD#32  
SD#33  
SD#34  
SD#35  
SD#36  
AA37  
AC35  
S35  
SAO#0  
SAO#1  
SAO#2  
SAO#3  
SAO#4  
SAO#5  
SAO#6  
SAO#7  
SAO#8  
SAO#9  
SAO#10  
SAO#11  
SAO#12  
SAO#13  
SAO#14  
SAOC#  
SCNCK1  
SCNCK2  
SCNINV  
SCNSN  
SD#0  
J3  
C7  
Q37  
Q35  
N37  
J33  
A7  
E5  
A5  
E7  
G33  
G37  
E37  
C1  
C5  
C3  
G35  
Q33  
N33  
L33  
G1  
E1  
A3  
G5  
N35  
L37  
G3  
E3  
J37  
S1  
A37  
E35  
SCANCLK2  
S5  
SCANINTEVAL  
SCANSHIFTEN  
SDATA[0]#  
S3  
E31  
Q5  
E29  
AA35  
W37  
W35  
A27  
A25  
E21  
SD#1  
SDATA[1]#  
SD#2  
SDATA[2]#  
58  
Pin Descriptions  
Chapter 11  
Preliminary Information  
26237C—May 2003  
AMD Athlon™ XP Processor Model 10 Data Sheet  
Table 23. Pin Name Abbreviations (continued)  
Abbreviation  
SD#37  
Full Name  
SDATA[37]#  
Pin  
C23  
Abbreviation  
SDOC#2  
Full Name  
SDATAOUTCLK[2]#  
SDATAOUTCLK[3]#  
SDATAOUTVALID#  
SFILLVALID#  
SMI#  
Pin  
A33  
SD#38  
SD#39  
SD#40  
SD#41  
SD#42  
SD#43  
SD#44  
SD#45  
SD#46  
SD#47  
SD#48  
SD#49  
SD#50  
SD#51  
SD#52  
SD#53  
SD#54  
SD#55  
SD#56  
SD#57  
SD#58  
SD#59  
SD#60  
SD#61  
SD#62  
SD#63  
SDIC#0  
SDIC#1  
SDIC#2  
SDIC#3  
SDINV#  
SDOC#0  
SDOC#1  
SDATA[38]#  
SDATA[39]#  
SDATA[40]#  
SDATA[41]#  
C27  
A23  
A35  
C35  
C33  
C31  
A29  
C29  
E23  
C25  
E17  
SDOC#3  
SDOV#  
SFILLV#  
C11  
AL31  
AJ31  
AN5  
AC1  
Q1  
SDATA[42]#  
SDATA[43]#  
SDATA[44]#  
SDATA[45]#  
SDATA[46]#  
SDATA[47]#  
STPC#  
STPCLK#  
TCK  
TDI  
U1  
TDO  
U5  
THDA  
THDC  
THERMDA  
THERMDC  
TMS  
S7  
U7  
SDATA[48]#  
SDATA[49]#  
SDATA[50]#  
SDATA[51]#  
Q3  
E13  
E11  
C15  
E9  
TRST#  
VCC_CORE  
U3  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
B4  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
B8  
B12  
B16  
B20  
B24  
B28  
B32  
B36  
D2  
SDATA[52]#  
SDATA[53]#  
SDATA[54]#  
SDATA[55]#  
SDATA[56]#  
SDATA[57]#  
A13  
C9  
A9  
C21  
A21  
E19  
C19  
C17  
A11  
A17  
A15  
W33  
J35  
SDATA[58]#  
SDATA[59]#  
SDATA[60]#  
SDATA[61]#  
D4  
D8  
D12  
D16  
D20  
D24  
D28  
D32  
F12  
F16  
F20  
SDATA[62]#  
SDATA[63]#  
SDATAINCLK[0]#  
SDATAINCLK[1]#  
SDATAINCLK[2]#  
SDATAINCLK[3]#  
SDATAINVALID#  
SDATAOUTCLK[0]#  
SDATAOUTCLK[1]#  
E27  
E15  
AN33  
AE35  
C37  
Chapter 11  
Pin Descriptions  
59  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 23. Pin Name Abbreviations (continued)  
Abbreviation  
Full Name  
VCC_CORE  
Pin  
Abbreviation  
Full Name  
VCC_CORE  
Pin  
X30  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
F24  
F28  
F32  
F34  
F36  
H2  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
X32  
X34  
X36  
Z2  
Z4  
H4  
Z6  
H12  
H16  
H20  
H24  
K32  
K34  
K36  
M2  
M4  
M6  
M8  
P30  
P32  
P34  
P36  
R2  
Z8  
AB30  
AB32  
AB34  
AB36  
AD2  
AD4  
AD6  
AF14  
AF18  
AF22  
AF26  
AF34  
AF36  
AH2  
AH4  
AH10  
AH14  
AH18  
AH22  
AH26  
AK10  
AK14  
AK18  
AK22  
AK26  
AK30  
R4  
R6  
R8  
T30  
T32  
T34  
T36  
V2  
V4  
V6  
V8  
60  
Pin Descriptions  
Chapter 11  
Preliminary Information  
26237C—May 2003  
AMD Athlon™ XP Processor Model 10 Data Sheet  
Table 23. Pin Name Abbreviations (continued)  
Abbreviation  
Full Name  
VCC_CORE  
Pin  
AK34  
Abbreviation  
Full Name  
Pin  
D22  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
VCC_CORE  
AK36  
AJ5  
D26  
D30  
D34  
D36  
F2  
AL5  
AM2  
AM10  
AM14  
AM18  
AM22  
AM26  
AM22  
AM26  
AM30  
AM34  
AJ23  
L1  
F4  
F6  
F10  
F14  
F18  
F22  
F26  
H14  
H18  
H22  
H26  
H34  
H36  
K2  
VCCA  
VID[0]  
VID[1]  
VID[2]  
VID[3]  
VID[4]  
VREF_SYS  
VSS  
L3  
L5  
L7  
J7  
K4  
VREF_S  
W5  
K6  
B2  
M30  
M32  
M34  
M36  
P2  
VSS  
B6  
VSS  
B10  
VSS  
B14  
VSS  
B18  
VSS  
B22  
B26  
B30  
B34  
D6  
P4  
VSS  
P6  
VSS  
P8  
VSS  
R30  
R32  
R34  
R36  
VSS  
VSS  
D10  
D14  
D18  
VSS  
VSS  
Chapter 11  
Pin Descriptions  
61  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 23. Pin Name Abbreviations (continued)  
Table 23. Pin Name Abbreviations (continued)  
Abbreviation  
Full Name  
Pin  
Abbreviation  
Full Name  
Pin  
AH36  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
T2  
T4  
T6  
T8  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
ZN  
AK2  
AK4  
AK12  
AK16  
AK20  
AK24  
AK28  
AK32  
AM4  
V30  
V32  
V34  
V36  
X2  
X4  
X6  
AM6  
X8  
AM12  
AM16  
AM20  
AM24  
AM28  
AM32  
AM36  
AC5  
Z30  
Z32  
Z34  
Z36  
AB2  
AB8  
AB4  
AB6  
AD32  
AD34  
AD36  
AF2  
ZP  
AE5  
AF4  
AF12  
AF16  
AH12  
AH16  
AH20  
AH24  
AH28  
AH32  
AH34  
62  
Pin Descriptions  
Chapter 11  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
11.2  
Pin List  
Table 24 on page 64 cross-references Socket A pin location to  
signal name.  
The “L(Level) column shows the electrical specification for  
this pin. “P” indicates a push-pull mode driven by a single  
source. “O” indicates open-drain mode that allows devices to  
share the pin.  
Note: The AMD Athlon processor supports push-pull drivers. For  
The “P” (Port) column indicates if this signal is an input (I),  
output (O), or bidirectional (B) signal. The “R” (Reference)  
column indicates if this signal should be referenced to VSS (G)  
or VCC_CORE (P) planes for the purpose of signal routing with  
respect to the current return paths.  
Chapter 11  
Pin Descriptions  
63  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 24. Cross-Reference by Pin Location  
Pin  
A1  
Name  
Description  
L
-
P
-
R
-
Pin  
B24  
Name  
VCC_CORE  
Description  
L
P
R
-
-
-
No Pin  
A3  
SADDOUT[12]#  
SADDOUT[5]#  
SADDOUT[3]#  
SDATA[55]#  
SDATA[61]#  
SDATA[53]#  
SDATA[63]#  
SDATA[62]#  
NC Pin  
P
P
P
P
P
P
P
P
-
O
O
O
B
B
B
B
B
-
G
G
G
P
P
G
G
G
-
B26  
B28  
VSS  
-
-
-
-
-
-
VCC_CORE  
A5  
A7  
B30  
B32  
VSS  
-
-
-
-
-
-
VCC_CORE  
A9  
A11  
A13  
A15  
A17  
A19  
A21  
A23  
A25  
A27  
A29  
A31  
A33  
A35  
A37  
B2  
B34  
B36  
VSS  
-
-
-
-
-
-
VCC_CORE  
C1  
SADDOUT[7]#  
SADDOUT[9]#  
SADDOUT[8]#  
SADDOUT[2]#  
SDATA[54]#  
SDATAOUTCLK[3]#  
NC Pin  
P
P
P
P
P
P
-
O
O
O
O
B
O
-
G
G
G
G
P
C3  
C5  
SDATA[57]#  
SDATA[39]#  
SDATA[35]#  
SDATA[34]#  
SDATA[44]#  
NC Pin  
P
P
P
P
P
-
B
B
B
B
B
-
G
G
P
P
G
-
C7  
C9  
C11  
C13  
C15  
C17  
C19  
C21  
C23  
C25  
C27  
C29  
C31  
C33  
C35  
C37  
D2  
G
-
SDATA[51]#  
SDATA[60]#  
SDATA[59]#  
SDATA[56]#  
SDATA[37]#  
SDATA[47]#  
SDATA[38]#  
SDATA[45]#  
SDATA[43]#  
SDATA[42]#  
SDATA[41]#  
P
P
P
P
P
P
P
P
P
P
P
P
-
B
B
B
B
B
B
B
B
B
B
B
O
-
P
G
G
G
P
SDATAOUTCLK[2]#  
SDATA[40]#  
SDATA[30]#  
P
P
P
-
O
B
B
-
P
G
P
-
VSS  
G
G
G
G
G
G
G
-
VCC_CORE  
B4  
-
-
-
B6  
B8  
VSS  
-
-
-
-
-
-
VCC_CORE  
B10  
B12  
VSS  
-
-
-
-
-
-
VCC_CORE  
B14  
B16  
VSS  
-
-
-
-
-
-
SDATAOUTCLK[1]#  
VCC_CORE  
VCC_CORE  
VCC_CORE  
D4  
-
-
-
B18  
B20  
VSS  
-
-
-
-
-
-
VCC_CORE  
D6  
D8  
VSS  
-
-
-
-
-
-
VCC_CORE  
B22  
VSS  
-
-
-
64  
Pin Descriptions  
Chapter 11  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 24. Cross-Reference by Pin Location  
(continued)  
Pin  
D10  
Name  
Description  
L
-
P
-
R
-
Pin  
E33  
Name  
NC Pin  
Description  
L
-
P
-
R
-
VSS  
VCC_CORE  
D12  
-
-
-
E35  
E37  
F2  
SDATA[31]#  
SDATA[22]#  
VSS  
P
P
-
B
B
-
P
G
-
D14  
D16  
VSS  
-
-
-
-
-
-
VCC_CORE  
D18  
D20  
VSS  
-
-
-
-
-
-
F4  
VSS  
-
-
-
VCC_CORE  
F6  
VSS  
-
-
-
D22  
D24  
VSS  
-
-
-
-
-
-
F8  
NC Pin  
-
-
-
VCC_CORE  
F10  
F12  
VSS  
-
-
-
VCC_CORE  
-
-
-
D26  
D28  
VSS  
-
-
-
-
-
-
VCC_CORE  
F14  
F16  
VSS  
-
-
-
-
-
-
VCC_CORE  
D30  
D32  
VSS  
-
-
-
-
-
-
VCC_CORE  
F18  
F20  
VSS  
-
-
-
-
-
-
VCC_CORE  
D34  
D36  
E1  
VSS  
-
-
-
-
VSS  
-
-
F22  
F24  
VSS  
-
-
-
-
-
-
VCC_CORE  
SADDOUT[11]#  
SADDOUTCLK#  
SADDOUT[4]#  
SADDOUT[6]#  
SDATA[52]#  
SDATA[50]#  
SDATA[49]#  
SDATAINCLK[3]#  
SDATA[48]#  
SDATA[58]#  
SDATA[36]#  
SDATA[46]#  
NC Pin  
P
P
P
P
P
P
P
P
P
P
P
P
-
O
O
O
O
B
B
B
I
P
G
P
G
P
P
G
G
P
G
P
P
-
E3  
F26  
F28  
VSS  
-
-
-
-
-
-
VCC_CORE  
E5  
E7  
F30  
F32  
F34  
F36  
NC Pin  
-
-
-
-
-
-
-
-
-
-
-
-
VCC_CORE  
E9  
VCC_CORE  
VCC_CORE  
E11  
E13  
E15  
E17  
E19  
E21  
E23  
E25  
E27  
E29  
E31  
G1  
SADDOUT[10]#  
SADDOUT[14]#  
SADDOUT[13]#  
Key Pin  
P
P
P
-
O
O
O
-
P
G
G
-
B
B
B
B
-
G3  
G5  
G7  
G9  
Key Pin  
-
-
-
G11  
G13  
G15  
G17  
NC Pin  
-
-
-
SDATAINCLK[2]#  
SDATA[33]#  
SDATA[32]#  
P
P
P
I
G
P
P
NC Pin  
-
-
-
B
B
Key Pin  
-
-
-
Key Pin  
-
-
-
Chapter 11  
Pin Descriptions  
65  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 24. Cross-Reference by Pin Location  
(continued)  
Pin  
G19  
Name  
Description  
L
-
P
-
R
-
Pin  
J5  
Name  
Description  
L
-
P
-
R
-
NC Pin  
NC Pin  
NC Pin  
VID[4]  
NC Pin  
G21  
G23  
G25  
G27  
G29  
G31  
G33  
G35  
-
-
-
J7  
O
-
O
-
-
Key Pin  
-
-
-
J31  
J33  
J35  
J37  
K2  
-
Key Pin  
-
-
-
SDATA[19]#  
SDATAINCLK[1]#  
SDATA[29]#  
VSS  
P
P
P
-
B
I
G
P
P
-
NC Pin  
-
-
-
NC Pin  
-
-
-
B
-
NC Pin  
-
-
-
SDATA[20]#  
SDATA[23]#  
P
P
P
-
B
B
B
-
G
G
G
-
K4  
VSS  
-
-
-
K6  
VSS  
-
-
-
G37  
H2  
SDATA[21]#  
VCC_CORE  
K8  
NC Pin  
-
-
-
K30  
K32  
K34  
K36  
NC Pin  
-
-
-
VCC_CORE  
VCC_CORE  
H4  
-
-
-
-
-
-
VCC_CORE  
VCC_CORE  
-
-
-
H6  
NC Pin  
NC Pin  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H8  
H10  
H12  
NC Pin  
L1  
VID[0]  
O
O
O
O
-
O
O
O
O
-
-
-
VCC_CORE  
L3  
VID[1]  
H14  
H16  
VSS  
-
-
-
-
-
-
L5  
VID[2]  
-
VCC_CORE  
L7  
VID[3]  
-
H18  
H20  
VSS  
-
-
-
-
-
-
L31  
L33  
L35  
L37  
M2  
M4  
M6  
M8  
NC Pin  
SDATA[26]#  
NC Pin  
-
VCC_CORE  
P
-
B
-
P
-
H22  
H24  
VSS  
-
-
-
-
-
-
VCC_CORE  
SDATA[28]#  
VCC_CORE  
P
-
B
-
P
-
H26  
H28  
H30  
H32  
H34  
H36  
J1  
VSS  
-
-
-
-
-
-
-
-
-
-
-
-
VCC_CORE  
VCC_CORE  
VCC_CORE  
-
-
-
NC Pin  
-
-
-
NC Pin  
-
-
-
-
-
NC Pin  
-
-
VSS  
-
-
M30  
M32  
M34  
M36  
VSS  
VSS  
VSS  
VSS  
-
-
-
-
-
-
-
-
-
-
-
-
VSS  
-
-
SADDOUT[0]#  
SADDOUT[1]#  
P
P
O
O
J3  
66  
Pin Descriptions  
Chapter 11  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 24. Cross-Reference by Pin Location  
(continued)  
Pin  
N1  
Name  
PICCLK  
Description  
L
O
O
O
-
P
I
R
-
Pin  
R34  
Name  
Description  
L
-
P
-
R
-
VSS  
VSS  
N3  
PICD#[0]  
PICD#[1]  
Key Pin  
NC Pin  
B
B
-
-
R36  
S1  
-
-
-
N5  
-
SCANCLK1  
SCANINTEVAL  
SCANCLK2  
THERMDA  
NC Pin  
P
P
P
-
I
-
N7  
-
S3  
I
-
N31  
N33  
N35  
N37  
P2  
-
-
-
S5  
I
-
SDATA[25]#  
SDATA[27]#  
SDATA[18]#  
VSS  
P
P
P
-
B
B
B
-
P
P
G
-
S7  
-
-
S31  
S33  
S35  
S37  
T2  
-
-
-
SDATA[7]#  
SDATA[15]#  
SDATA[6]#  
VSS  
P
P
P
-
B
B
B
-
G
P
G
-
P4  
VSS  
-
-
-
P6  
VSS  
-
-
-
P8  
VSS  
-
-
-
T4  
VSS  
-
-
-
VCC_CORE  
P30  
P32  
P34  
P36  
-
-
-
T6  
VSS  
-
-
-
VCC_CORE  
VCC_CORE  
VCC_CORE  
-
-
-
T8  
VSS  
-
-
-
VCC_CORE  
-
-
-
T30  
T32  
T34  
T36  
-
-
-
VCC_CORE  
VCC_CORE  
VCC_CORE  
-
-
-
-
-
-
-
-
-
Q1  
Q3  
Q5  
Q7  
Q31  
Q33  
Q35  
Q37  
R2  
TCK  
page 76  
page 77  
P
P
P
-
I
I
-
-
-
-
-
TMS  
SCANSHIFTEN  
Key Pin  
I
-
U1  
TDI  
P
P
P
-
I
I
-
-
-
-
U3  
TRST#  
NC Pin  
-
-
-
U5  
TDO  
O
-
-
SDATA[24]#  
SDATA[17]#  
P
P
P
-
B
B
B
-
P
G
G
-
U7  
THERMDC  
NC Pin  
-
U31  
U33  
U35  
U37  
V2  
-
-
-
SDATA[16]#  
VCC_CORE  
SDATA[5]#  
SDATA[4]#  
P
P
-
B
B
-
G
G
-
VCC_CORE  
VCC_CORE  
VCC_CORE  
R4  
-
-
-
NC Pin  
VCC_CORE  
R6  
-
-
-
-
-
-
VCC_CORE  
VCC_CORE  
VCC_CORE  
R8  
-
-
-
V4  
-
-
-
V6  
-
-
-
R30  
R32  
VSS  
VSS  
-
-
-
-
-
-
V8  
-
-
-
Chapter 11  
Pin Descriptions  
67  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 24. Cross-Reference by Pin Location  
(continued)  
Pin  
V30  
Name  
Description  
L
-
P
-
R
-
Pin  
Z6  
Name  
VCC_CORE  
Description  
L
-
P
-
R
-
VSS  
VCC_CORE  
Z8  
-
-
-
V32  
V34  
V36  
W1  
W3  
W5  
W7  
W31  
W33  
W35  
W37  
X2  
VSS  
-
-
-
VSS  
-
-
-
Z30  
Z32  
Z34  
Z36  
AA1  
AA3  
AA5  
AA7  
VSS  
-
-
-
-
-
-
VSS  
-
-
-
VSS  
FID[0]  
FID[1]  
page 74  
O
O
P
-
O
O
-
-
VSS  
-
-
-
-
VSS  
-
-
-
VREFSYS  
NC Pin  
-
DBRDY  
DBREQ#  
NC  
page 73  
page 73  
P
P
-
O
I
-
-
-
-
NC Pin  
-
-
-
-
-
SDATAINCLK[0]#  
SDATA[2]#  
SDATA[1]#  
VSS  
P
P
P
-
I
G
G
P
-
Key Pin  
-
-
-
B
B
-
AA31 NC Pin  
-
-
-
AA33 SDATA[8]#  
AA35 SDATA[0]#  
AA37 SDATA[13]#  
P
P
P
-
B
B
B
-
P
G
G
-
X4  
VSS  
-
-
-
X6  
VSS  
-
-
-
AB2  
VSS  
VSS  
VSS  
X8  
VSS  
-
-
-
AB4  
-
-
-
VCC_CORE  
X30  
X32  
X34  
X36  
-
-
-
AB6  
-
-
-
VCC_CORE  
VCC_CORE  
VCC_CORE  
-
-
-
AB8  
VSS  
-
-
-
VCC_CORE  
-
-
-
AB30  
AB32  
AB34  
AB36  
-
-
-
VCC_CORE  
VCC_CORE  
VCC_CORE  
-
-
-
-
-
-
-
-
-
Y1  
FID[2]  
page 74  
O
O
-
O
O
-
-
-
-
-
-
Y3  
FID[3]  
Y5  
NC Pin  
Key Pin  
NC Pin  
NC Pin  
SDATA[3]#  
-
AC1  
AC3  
AC5  
AC7  
STPCLK#  
PLLTEST#  
ZN  
page 78  
P
P
P
-
I
I
-
-
Y7  
-
-
-
Y31  
Y33  
Y35  
Y37  
Z2  
-
-
-
-
-
-
-
-
NC  
-
-
P
P
-
B
B
-
G
P
-
AC31 NC Pin  
-
-
-
SDATA[12]#  
VCC_CORE  
AC33 SDATA[10]#  
AC35 SDATA[14]#  
AC37 SDATA[11]#  
P
P
P
B
B
B
P
G
G
VCC_CORE  
Z4  
-
-
-
68  
Pin Descriptions  
Chapter 11  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 24. Cross-Reference by Pin Location  
(continued)  
Pin  
AD2  
Name  
VCC_CORE  
VCC_CORE  
VCC_CORE  
Description  
L
-
P
-
R
-
Pin  
Name  
Description  
L
-
P
-
R
-
AF30 NC Pin  
AF32 NC Pin  
AD4  
AD6  
AD8  
-
-
-
-
-
-
VCC_CORE  
VCC_CORE  
-
-
-
AF34  
AF36  
AG1  
AG3  
AG5  
AG7  
AG9  
-
-
-
-
-
-
NC Pin  
-
-
-
-
-
-
AD30 NC Pin  
AD32 VSS  
AD34 VSS  
AD36 VSS  
FERR  
P
-
O
I
-
-
-
-
-
RESET#  
NC Pin  
Key Pin  
Key Pin  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
I
-
-
-
-
-
-
AE1  
AE3  
AE5  
AE7  
A20M#  
PWROK  
ZP  
P
P
P
-
I
-
-
-
I
-
AG11 COREFB  
AG13 COREFB#  
AG15 Key Pin  
AG17 Key Pin  
AG19 NC Pin  
-
-
page 78  
-
-
-
-
NC  
-
-
-
-
AE31 NC Pin  
-
-
-
-
-
AE33 SADDIN[5]#  
AE35 SDATAOUTCLK[0]#  
AE37 SDATA[9]#  
P
P
P
-
I
G
P
G
-
-
-
O
B
-
AG21 NC Pin  
-
-
AG23 NC Pin  
-
-
AF2  
AF4  
AF6  
AF8  
VSS  
AG25 NC Pin  
-
-
VSS  
-
-
-
AG27 Key Pin  
AG29 Key Pin  
AG31 FSB_Sense[0]  
AG33 SADDIN[2]#  
AG35 SADDIN[11]#  
AG37 SADDIN[7]#  
-
-
NC Pin  
NC Pin  
-
-
-
-
-
-
-
-
-
G
G
G
P
-
AF10 NC Pin  
AF12 VSS  
-
-
-
P
P
P
-
-
-
-
I
VCC_CORE  
AF14  
-
-
-
I
VCC_CORE  
VCC_CORE  
AH2  
AH4  
-
-
AF16 VSS  
-
-
-
-
-
-
VCC_CORE  
AF18  
-
-
AF20 VSS  
-
-
-
-
-
-
AH6  
AH8  
AH10  
AMD Pin  
-
-
-
-
-
-
-
-
-
VCC_CORE  
AF22  
NC Pin  
VCC_CORE  
AF24 VSS  
-
-
-
-
-
-
VCC_CORE  
AF26  
AH12 VSS  
VCC_CORE  
-
-
-
-
-
-
AH14  
AF28 NC Pin  
-
-
-
Chapter 11  
Pin Descriptions  
69  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 24. Cross-Reference by Pin Location  
(continued)  
Pin  
Name  
Description  
L
-
P
-
R
-
Pin  
AK2  
Name  
Description  
L
-
P
-
R
-
AH16 VSS  
VSS  
VSS  
VCC_CORE  
AH18  
-
-
-
AK4  
AK6  
AK8  
AK10  
-
-
-
AH20 VSS  
-
-
-
-
-
-
CPU_PRESENCE#  
-
-
-
VCC_CORE  
AH22  
NC Pin  
-
-
-
VCC_CORE  
-
-
-
AH24 VSS  
-
-
-
-
-
-
VCC_CORE  
AH26  
AK12 VSS  
-
-
-
-
-
-
VCC_CORE  
AK14  
AH28 VSS  
-
-
-
O
-
-
G
-
AH30 FSB_Sense[1]  
AH32 VSS  
AK16 VSS  
-
-
-
-
-
-
VCC_CORE  
AK18  
-
AH34 VSS  
-
-
-
AK20 VSS  
-
-
-
VCC_CORE  
AK22  
-
-
-
AH36 VSS  
-
-
-
AJ1  
AJ3  
AJ5  
IGNNE#  
P
P
-
I
-
AK24 VSS  
-
-
-
-
-
-
VCC_CORE  
AK26  
INIT#  
I
-
VCC_CORE  
-
-
AK28 VSS  
-
-
-
-
-
-
VCC_CORE  
AK30  
AJ7  
NC Pin  
page 72  
page 77  
page 76  
-
-
-
-
-
-
-
-
-
I
-
-
AJ9  
NC Pin  
AK32 VSS  
-
-
-
-
-
-
-
-
-
VCC_CORE  
AK34  
AK36  
AJ11  
AJ13  
AJ15  
AJ17  
AJ19  
AJ21  
AJ23  
AJ25  
AJ27  
AJ29  
AJ31  
AJ33  
AJ35  
AJ37  
NC Pin  
-
-
VCC_CORE  
INTR  
Analog  
-
-
NC Pin  
-
-
AL1  
AL3  
AL5  
P
P
-
I
I
-
-
-
-
NC Pin  
-
-
FLUSH#  
VCC_CORE  
NC Pin  
-
-
CLKFWDRST  
VCCA  
P
-
P
-
AL7  
AL9  
NC Pin  
NC Pin  
-
-
-
-
-
-
-
I
PLLBYPASS#  
NC Pin  
P
-
-
AL11 NC Pin  
-
-
-
-
I
-
AL13 PLLMON2  
AL15 PLLBYPASSCLK#  
O
P
P
P
P
P
O
I
-
SADDIN[0]#  
SFILLVALID#  
SADDINCLK#  
SADDIN[6]#  
SADDIN[3]#  
P
P
P
P
P
-
-
I
G
G
P
G
AL17  
AL19 RSTCLK#  
AL21 K7CLKOUT  
AL23 CONNECT  
CLKIN#  
I
P
P
-
I
I
I
O
I
I
P
70  
Pin Descriptions  
Chapter 11  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 24. Cross-Reference by Pin Location  
(continued)  
Pin  
Name  
Description  
L
-
P
-
R
-
Pin  
Name  
Description  
page 73  
page 73  
L
-
P
-
R
-
AL25 NC Pin  
AL27 NC Pin  
AN11 NC Pin  
-
-
-
AN13 PLLMON1  
AN15 PLLBYPASSCLK  
AN17 CLKIN  
O
P
P
P
P
P
-
B
I
-
AL29 SADDIN[1]#  
P
P
P
P
P
-
I
-
-
AL31  
SDATAOUTVALID#  
O
I
P
P
G
G
-
I
P
P
-
AL33 SADDIN[8]#  
AL35 SADDIN[4]#  
AL37 SADDIN[10]#  
AN19 RSTCLK  
I
I
AN21 K7CLKOUT#  
AN23 PROCRDY  
AN25 NC Pin  
O
O
-
I
P
-
VCC_CORE  
AM2  
-
AM4  
AM6  
AM8  
AM10  
VSS  
VSS  
-
-
-
-
-
-
-
-
-
-
-
-
AN27 NC Pin  
-
-
-
AN29 SADDIN[12]#  
AN31 SADDIN[14]#  
AN33 SDATAINVALID#  
AN35 SADDIN[13]#  
AN37 SADDIN[9]#  
P
P
P
P
P
I
G
G
P
G
G
NC Pin  
I
VCC_CORE  
I
AM12 VSS  
-
-
-
-
-
-
I
VCC_CORE  
AM14  
I
AM16 VSS  
-
-
-
-
-
-
VCC_CORE  
AM18  
AM20 VSS  
-
-
-
-
-
-
VCC_CORE  
AM22  
AM24 VSS  
-
-
-
-
-
-
VCC_CORE  
AM26  
AM28 VSS  
-
-
-
-
-
-
VCC_CORE  
AM30  
AM32 VSS  
-
-
-
-
-
-
VCC_CORE  
AM34  
AM36 VSS  
-
-
-
-
I
-
-
-
-
-
-
AN1  
AN3  
AN5  
AN7  
AN9  
No Pin  
NMI  
P
P
-
SMI#  
NC Pin  
NC Pin  
I
-
-
-
Chapter 11  
Pin Descriptions  
71  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
11.3  
Detailed Pin Descriptions  
A20M# Pin  
AMD Pin  
A20M# is an input from the system used to simulate address  
wrap-around in the 20-bit 8086.  
AMD Socket A processors do not implement a pin at location  
AH6. All Socket A designs must have a top plate or cover that  
blocks this pin location. When the cover plate blocks this  
location, a non-AMD part (e.g., PGA370) does not fit into the  
socket. However, socket manufacturers are allowed to have a  
contact loaded in the AH6 position. Therefore, motherboard  
socket design should account for the possibility that a contact  
could be loaded in this position.  
AMD Athlon™  
System Bus Pins  
See the AMD Athlon™ and AMD Duron™ System Bus  
Specification, order# 21902 for information about the system  
bus pins—PROCRDY, PWROK, RESET#, SADDIN[14:2]#,  
SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#,  
SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#,  
SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#.  
Analog Pin  
Treat this pin as a NC.  
APIC Pins, PICCLK,  
PICD[1:0]#  
The Advanced Programmable Interrupt Controller (APIC) is a  
feature that provides a flexible and expandable means of  
delivering interrupts in a system using an AMD processor. The  
pins, PICD[1:0], are the bidirectional message-passing signals  
used for the APIC and are driven to the Southbridge or a  
dedicated I/O APIC. The pin, PICCLK, must be driven with a  
valid clock input.  
Refer to “VCC_2.5V Generation Circuit” found in the section,  
“Motherboard Required Circuits,” of the AMD Athlon™  
Processor Motherboard Design Guide, order# 24363 for the  
required supporting circuitry.  
For more information, see Table 15, “APIC Pin AC and DC  
Characteristics,” on page 40.  
CLKFWDRST Pin  
CLKFWDRST resets clock-forward circuitry for both the system  
and processor.  
Chapter 11  
Pin Descriptions  
72  
                     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
CLKIN, RSTCLK  
(SYSCLK) Pins  
Connect CLKIN with RSTCLK and name it SYSCLK. Connect  
CLKIN# with RSTCLK# and name it SYSCLK#. Length match  
the clocks from the clock generator to the Northbridge and  
processor.  
CONNECT Pin  
CONNECT is an input from the system used for power  
management and clock-forward initialization at reset.  
COREFB and  
COREFB# Pins  
COREFB and COREFB# are outputs to the system that provide  
processor core voltage feedback to the system.  
CPU_PRESENCE# Pin  
CPU_PRESENCE# is connected to VSS on the processor  
package. If pulled-up on the motherboard, CPU_PRESENCE#  
may be used to detect the presence or absence of a processor in  
the Socket A-style socket.  
DBRDY and DBREQ#  
Pins  
DBRDY and DBREQ# are routed to the debug connector.  
DBREQ# is tied to V  
with a pullup resistor.  
CC_CORE  
FERR Pin  
FERR is an output to the system that is asserted for any  
unmasked numerical exception independent of the NE bit in  
CR0. FERR is a push-pull active High signal that must be  
inverted and level shifted to an active Low signal. For more  
information about FERR and FERR#, see the “Required  
Circuits” chapter of the AMD Athlon™ Processor-Based  
Motherboard Design Guide, order# 24363.  
Chapter 11  
Pin Descriptions  
73  
                 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
FID[3:0] Pins  
FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the  
4-bit processor clock-to-SYSCLK ratio.  
Table 25 describes the encodings of the clock multipliers on  
FID[3:0].  
Table 25. FID[3:0] Clock Multiplier Encodings  
FID[3:0]2  
Processor Clock to SYSCLK Frequency Ratio  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
11  
11.5  
12  
12.51  
5
5.5  
6
6.5  
7
7.5  
8
8.5  
9
9.5  
10  
10.5  
Notes:  
1. All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011b, which causes  
the SIP configuration for all ratios of 12.5x or greater to be the same.  
2. BIOS initializes the CLK_Ctl MSR during the POST routine. This CLK_Ctl setting is used with all  
FID combinations and selects a Halt disconnect divisor and a Stop Grant disconnect divisor.  
For more information, refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,  
Software, and Debug Developers Guide, order# 21656.  
The FID[3:0] signals are open-drain processor outputs that are  
pulled High on the motherboard and sampled by the chipset to  
determine the SIP (serial initialization packet) that is sent to  
the processor. The FID[3:0] signals are valid after PWROK is  
asserted. The FID[3:0]signals must not be sampled until they  
become valid. See the AMD Athlon™ and AMD Duron™ System  
Bus Specification, order# 21902 for more information about  
Serialization Initialization Packets and SIP protocol.  
The processor FID[3:0] outputs are open-drain and 2.5-V  
tolerant. To prevent damage to the processor, do not pull these  
74  
Pin Descriptions  
Chapter 11  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
signals High above 2.5 V. Do not expose these pins to a  
differential voltage greater than 1.60 V, relative to the  
processor core voltage.  
Refer to “VCC_2.5V Generation Circuit” found in the section,  
“Motherboard Required Circuits,” of the AMD Athlon™  
Processor Motherboard Design Guide, order# 24363 for the  
required supporting circuitry.  
See “Frequency Identification (FID[3:0])” on page 25 for the  
DC characteristics for FID[3:0].  
FSB_Sense[1:0] Pins  
FSB_Sense[1:0] pins are either open circuit (logic level of 1) or  
are pulled to ground (logic level of 0) on the processor package  
with a 1 kresistor. In conjunction with a circuit on the  
motherboard, these pins may be used to automatically detect  
the front-side bus (FSB) setting of this processor. Proper  
detection of the FSB setting requires the implementation of a  
pull-up resistor on the motherboard. Refer to the AMD Athlon™  
Processor-Based Motherboard Design Guide, order# 24363 and the  
technical note FSB_Sense Auto Detection Circuitry for Desktop  
Processors, order# TN26673 for more information.  
Table 26 is the truth table to determine the FSB of desktop  
processors.  
Table 26. Front-Side Bus Sense Truth Table  
FSB_Sense[1]  
FSB_Sense[0]  
Bus Frequency  
RESERVED  
133 MHz  
1
1
0
0
0
1
1
0
166 MHz  
200 MHz  
The FSB_Sense[1:0] pins are 3.3-V tolerant.  
FLUSH# must be tied to V with a pullup resistor. If a  
FLUSH# Pin  
CC_CORE  
debug connector is implemented, FLUSH# is routed to the  
debug connector.  
IGNNE# Pin  
INIT# Pin  
IGNNE# is an input from the system that tells the processor to  
ignore numeric errors.  
INIT# is an input from the system that resets the integer  
registers without affecting the floating-point registers or the  
internal caches. Execution starts at 0_FFFF_FFF0h.  
Chapter 11  
Pin Descriptions  
75  
                 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
INTR Pin  
JTAG Pins  
INTR is an input from the system that causes the processor to  
start an interrupt acknowledge transaction that fetches the 8-bit  
interrupt vector and starts execution at that location.  
TCK, TMS, TDI, TRST#, and TDO are the JTAG interface.  
Connect these pins directly to the motherboard debug connector.  
Pull TDI, TCK, TMS, and TRST# up to V  
resistors.  
with pullup  
CC_CORE  
K7CLKOUT and  
K7CLKOUT# Pins  
K7CLKOUT and K7CLKOUT# are each run for two to three  
inches and then terminated with a resistor pair: 100 ohms to  
V
and 100 ohms to VSS. The effective termination  
CC_CORE  
resistance and voltage are 50 ohms and V  
/2.  
CC_CORE  
Key Pins  
These 16 locations are for processor type keying for forwards and  
backwards compatibility (G7, G9, G15, G17, G23, G25, N7, Q7, Y7,  
AA7, AG7, AG9, AG15, AG17, AG27, and AG29). Motherboard  
designers should treat key pins like NC (No Connect) pins. A  
socket designer has the option of creating a top mold piece that  
allows PGA key pins only where designated. However, sockets  
that populate all 16 key pins must be allowed, so the motherboard  
must always provide for pins at all key pin locations.  
See “NC Pins“ for more information.  
NC Pins  
The motherboard should provide a plated hole for an NC pin. The  
pin hole should not be electrically connected to anything.  
NMI Pin  
NMI is an input from the system that causes a non-maskable  
interrupt.  
PGA Orientation Pins  
No pin is present at pin locations A1 and AN1. Motherboard  
designers should not allow for a PGA socket pin at these  
locations.  
For more information, see the AMD Athlon™ Processor-Based  
Motherboard Design Guide, order# 24363.  
PLL Bypass and Test  
Pins  
PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2,  
PLLBYPASSCLK, and PLLBYPASSCLK# are the PLL bypass and  
test interface. This interface is tied disabled on the motherboard.  
All six pin signals are routed to the debug connector. All four  
processor inputs (PLLTEST#, PLLBYPASS#, PLLMON1, and  
PLLMON2) are tied to V  
with pullup resistors.  
CC_CORE  
PWROK Pin  
The PWROK input to the processor must not be asserted until  
all voltage planes in the system are within specification and all  
system clocks are running within specification.  
76  
Pin Descriptions  
Chapter 11  
                         
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
SADDIN[1:0]# and  
SADDOUT[1:0]# Pins  
The AMD Athlon XP processor model 10 does not support  
SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC  
with pullup resistors, if this bit is not supported by the  
Northbridge (future models can support SADDIN[1]#).  
SADDOUT[1:0]# are tied to VCC with pullup resistors if these  
pins are supported by the Northbridge. For more information,  
see the AMD Athlon™ and AMD Duron™ System Bus  
Specification, order# 21902.  
Scan Pins  
SCANSHIFTEN, SCANCLK1, SCANINTEVAL, and SCANCLK2  
are the scan interface. This interface is AMD internal and is  
tied disabled with pulldown resistors to ground on the  
motherboard.  
SMI# Pin  
SMI# is an input that causes the processor to enter the system  
management mode.  
STPCLK# Pin  
STPCLK# is an input that causes the processor to enter a lower  
power mode and issue a Stop Grant special cycle.  
SYSCLK and SYSCLK#  
SYSCLK and SYSCLK# are differential input clock signals  
provided to the PLL of the processor from a system-clock  
generator.  
information.  
THERMDA and  
THERMDC Pins  
Thermal Diode anode and cathode pins are used to monitor the  
actual temperature of the processor die, providing more  
accurate temperature control to the system.  
See Table 13, “Thermal Diode Electrical Characteristics,” on  
page 37 for more information.  
VCCA Pin  
VCCA is the processor PLL supply. For information about the  
VCCA pin, see Table 5, “VCCA AC and DC Characteristics,” on  
page 35 and the AMD Athlon™ Processor-Based Motherboard  
Design Guide, order# 24363.  
To prevent damage to the processor, do not pull this signal High  
above 2.5 V. Do not expose this pin to a differential voltage  
greater than 1.60 V, relative to the processor core voltage.  
VID[4:0] Pins  
The VID[4:0] (Voltage Identification) outputs are used to  
dictate the V  
voltage level. The VID[4:0] pins are  
CC_CORE  
strapped to ground or left unconnected on the processor  
package. The VID[4:0] pins are pulled up on the motherboard  
and used by the V  
DC/DC converter.  
CC_CORE  
Chapter 11  
Pin Descriptions  
77  
                             
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
The VID codes and corresponding voltage levels are shown in  
Table 27. VID[4:0] Code to Voltage Definition  
VCC_CORE (V)  
VCC_CORE (V)  
VID[4:0]  
VID[4:0]  
00000  
00001  
00010  
00011  
00100  
00101  
00111  
01000  
01001  
01010  
01011  
01100  
01101  
01110  
01111  
1.850  
1.825  
1.800  
1.775  
1.750  
1.725  
1.675  
1.650  
1.625  
1.600  
1.575  
1.550  
1.525  
1.500  
1.475  
10000  
10001  
10010  
10011  
10100  
10101  
10111  
11000  
11001  
11010  
11011  
11100  
11101  
11110  
11111  
1.450  
1.425  
1.400  
1.375  
1.350  
1.325  
1.275  
1.250  
1.225  
1.200  
1.175  
1.150  
1.125  
1.100  
No CPU  
For more information, see the “Required Circuits” chapter of  
the AMD Athlon™ Processor-Based Motherboard Design Guide,  
order# 24363.  
VREFSYS Pin  
VREFSYS (W5) drives the threshold voltage for the system bus  
input receivers. The value of VREFSYS is system specific. In  
addition, to minimize V  
noise rejection from VREFSYS,  
CC_CORE  
include decoupling capacitors. For more information, see the  
AMD Athlon™ Processor-Based Motherboard Design Guide, order#  
24363.  
ZN and ZP Pins  
ZN (AC5) and ZP (AE5) are the push-pull compensation circuit  
pins. In Push-Pull mode (selected by the SIP parameter  
SysPushPull asserted), ZN is tied to V  
with a resistor  
CC_CORE  
that has a resistance matching the impedance Z of the  
0
transmission line. ZP is tied to VSS with a resistor that has a  
resistance matching the impedance Z of the transmission line.  
0
78  
Pin Descriptions  
Chapter 11  
       
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
12  
Ordering Information  
Standard AMD Athlon™ XP Processor Model 10 Products  
AMD standard products are available in several operating ranges. The ordering part  
numbers (OPN) are formed by a combination of the elements, as shown in Figure 18.  
OPN1  
AXD A 3200 D K V 4 E  
Advanced Front-Side Bus: D = 333, E = 400  
Size of L2 Cache: 4 = 512 Kbytes  
Die Temperature: V = 85°C  
Operating Voltage: K = 1.65 V  
Package Type: D = OPGA  
Model Number: 2500 operates at 1833 MHz ,  
2
2
2600 at 1917 MHz  
2800 at 2083 MHz ,  
3000 at 2100 MHz ,  
3000 at 2167 MHz ,  
2
3
2
3
3200 at 2200 MHz  
Maximum Power: A = Desktop Processor  
Architecture Segment: AXD = AMD Athlon™ XP Processor Model 10 with  
QuantiSpeed™ Architecture for Desktop Products  
Note:  
1. Spaces are added to the number shown above for viewing clarity only.  
2. This processor is available only with an advanced 333 FSB.  
3. This processor is available only with an advanced 400 FSB.  
Figure 18. OPN Example for the AMD Athlon™ XP Processor Model 10  
Chapter 12  
Ordering Information  
79  
         
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
80  
Ordering Information  
Chapter 12  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Appendix A  
Thermal Diode Calculations  
This section contains information about the calculations for the  
on-die thermal diode of the AMD Athlon™ XP processor model  
10. For electrical information about this thermal diode, see  
Table 13, “Thermal Diode Electrical Characteristics,” on  
page 37.  
Ideal Diode Equation  
The ideal diode equation uses the variables and constants  
Table 28. Constants and Variables for the Ideal Diode Equation  
Equation Symbol  
Variable, Constant Description  
Lumped ideality factor  
nf, lumped  
k
q
Boltzmann constant  
Electron charge constant  
Diode temperature (Kelvin)  
Voltage from base to emitter  
T
VBE  
IC  
IS  
Collector current  
Saturation current  
Appendix A - Thermal Diode Calculations  
81  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Equation (1) shows the ideal diode calculation.  
k
q
IC  
   
---  
--  
(1)  
VBE = nf, lumped ⋅ ⋅ T ln  
   
IS  
Sourcing two currents and using Equation (1) derives the  
difference in the base-to-emitter voltage that leads to finding  
the diode temperature as shown in Equation (2). The use of  
dual sourcing currents allows the measurement of the thermal  
diode temperature to be more accurate and less susceptible to  
die and process revisions. Temperature sensors that utilize  
series resistance cancellation can use more than two sourcing  
currents and are suitable to be used with the AMD thermal  
diode. Equation (2) is the formula for calculating the  
temperature of a thermal diode.  
V
BE, high VBE, low  
--------------------------------------------------------------  
T =  
k
Ihigh  
(2)  
--  
nf, lumped ⋅ ⋅ ln  
-------  
q
Ilow  
Temperature Offset Correction  
A temperature offset may be required to correct the value  
measured by a temperature sensor. An offset is necessary if a  
difference exists between the lumped ideality factor of the  
processor and the ideality factor assumed by the temperature  
sensor. The lumped ideality factor can be calculated using the  
equations in this section to find the temperature offset that  
should be used with the temperature sensor.  
Table 29 shows the constants and variables used to calculate the  
temperature offset correction.  
Table 29. Constants and Variables Used in Temperature Offset Equations  
Equation Symbol  
Variable, Constant Description  
Actual ideality factor  
nf, actual  
nf, lumped  
nf, TS  
Lumped ideality factor  
Ideality factor assumed by temperature sensor  
High sourcing current  
Ihigh  
Ilow  
Low sourcing current  
Tdie, spec  
Toffset  
Die temperature specification  
Temperature offset  
82  
Appendix A - Thermal Diode Calculations  
       
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
calculate the temperature offset for temperature sensors that  
do not employ series resistance cancellation. The result is  
added to the value measured by the temperature sensor.  
Contact the vendor of the temperature sensor being used for  
the value of n  
. Refer to the document, On-Die Thermal Diode  
f,TS  
Characterization, order# 25443, for further details.  
Equation (3) shows the equation for calculating the lumped  
ideality factor (n  
) in sensors that do not employ series  
f, lumped  
resistance cancellation.  
RT ⋅ (Ihigh Ilow)  
nf, lumped = nf, actual + ----------------------------------------------------------------------  
(3)  
k
Ihigh  
--  
-------  
(Tdie, spec + 273.15) ⋅ ln  
q
Ilow  
Equation (4) shows the equation for calculating temperature  
offset (T ) in sensors that do not employ series resistance  
offset  
cancellation.  
nf, lumped  
nf, TS  
T
= (Tdie, spec + 273.15) ⋅ 1 --------------  
(4)  
offset  
Equation (5) is the temperature offset for temperature sensors  
that utilize series resistance cancellation. Add the result to the  
value measured by the temperature sensor. Note that the value  
of n  
in Equation (5) may not equal the value used in  
f,TS  
nf, actual  
nf, TS  
T
= (Tdie, spec + 273.15) ⋅ 1 ---------------  
(5)  
offset  
Appendix A - Thermal Diode Calculations  
83  
     
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
84  
Appendix A - Thermal Diode Calculations  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Appendix B  
Conventions and  
Abbreviations  
This section contains information about the conventions and  
abbreviations used in this document.  
Signals and Bits  
Active-Low Signals—Signal names containing a pound sign,  
such as SFILL#, indicate active-Low signals. They are  
asserted in their Low-voltage state and negated in their  
High-voltage state. When used in this context, High and Low  
are written with an initial upper case letter.  
Signal Ranges—In a range of signals, the highest and lowest  
signal numbers are contained in brackets and separated by a  
colon (for example, D[63:0]).  
Reserved Bits and Signals—Signals or bus bits marked  
reserved must be driven inactive or left unconnected, as  
indicated in the signal descriptions. These bits and signals  
are reserved by AMD for future implementations. When  
software reads registers with reserved bits, the reserved bits  
must be masked. When software writes such registers, it  
must first read the register and change only the  
non-reserved bits before writing back to the register.  
Three-State—In timing diagrams, signal ranges that are  
high impedance are shown as a straight horizontal line  
half-way between the high and low levels.  
Invalid and Don’t-Care—In timing diagrams, signal ranges  
that are invalid or don't-care are filled with a screen pattern.  
Appendix B - Conventions and Abbreviations  
85  
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Data Terminology  
The following list defines data terminology:  
Quantities  
A word is two bytes (16 bits)  
A doubleword is four bytes (32 bits)  
A quadword is eight bytes (64 bits)  
Addressing—Memory is addressed as a series of bytes on  
eight-byte (64-bit) boundaries in which each byte can be  
separately enabled.  
AbbreviationsThe following notation is used for bits and  
bytes:  
Kilo (K, as in 4-Kbyte page)  
Mega (M, as in 4 Mbits/sec)  
Giga (G, as in 4 Gbytes of memory space)  
See Table 30 on page 87 for more abbreviations.  
Little-Endian Convention—The byte with the address  
xx...xx00 is in the least-significant byte position (little end).  
In byte diagrams, bit positions are numbered from right to  
left—the little end is on the right and the big end is on the  
left. Data structure diagrams in memory show low addresses  
at the bottom and high addresses at the top. When data  
items are aligned, bit notation on a 64-bit data bus maps  
directly to bit notation in 64-bit-wide memory. Because byte  
addresses increase from right to left, strings appear in  
reverse order when illustrated.  
Bit Ranges—In text, bit ranges are shown with a dash (for  
example, bits 9–1). When accompanied by a signal or bus  
name, the highest and lowest bit numbers are contained in  
brackets and separated by a colon (for example, AD[31:0]).  
Bit Values—Bits can either be set to 1 or cleared to 0.  
Hexadecimal and Binary Numbers—Unless the context  
makes interpretation clear, hexadecimal numbers are  
followed by an h and binary numbers are followed by a b.  
86  
Appendix B - Conventions and Abbreviations  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Abbreviations and Acronyms  
Table 30 contains the definitions of abbreviations used in this  
document.  
Table 30. Abbreviations  
Abbreviation  
Meaning  
Ampere  
A
F
Farad  
G
Giga-  
Gbit  
Gbyte  
GHz  
H
Gigabit  
Gigabyte  
Gigahertz  
Henry  
h
Hexadecimal  
Kilo-  
K
Kbyte  
lbf  
Kilobyte  
Foot-pound  
Mega-  
M
Mbit  
Mbyte  
MHz  
m
Megabit  
Megabyte  
Megahertz  
Milli-  
ms  
mW  
µ
Millisecond  
Milliwatt  
Micro-  
µA  
µF  
Microampere  
Microfarad  
Microhenry  
Microsecond  
Microvolt  
nano-  
µH  
µs  
µV  
n
nA  
nanoampere  
nanofarad  
nanohenry  
nanosecond  
Ohm  
nF  
nH  
ns  
ohm  
Appendix B - Conventions and Abbreviations  
87  
   
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 30. Abbreviations (continued)  
Abbreviation  
Meaning  
pico-  
p
pA  
pF  
pH  
ps  
s
picoampere  
picofarad  
picohenry  
picosecond  
Second  
V
Volt  
W
Watt  
Table 31 contains the definitions of acronyms used in this  
document.  
Table 31. Acronyms  
Abbreviation  
ACPI  
Meaning  
Advanced Configuration and Power Interface  
Accelerated Graphics Port  
AGP  
APCI  
AGP Peripheral Component Interconnect  
Application Programming Interface  
Advanced Programmable Interrupt Controller  
Basic Input/Output System  
API  
APIC  
BIOS  
BIST  
Built-In Self-Test  
BIU  
Bus Interface Unit  
CPGA  
DDR  
Ceramic Pin Grid Array  
Double-Data Rate  
DIMM  
DMA  
DRAM  
EIDE  
Dual Inline Memory Module  
Direct Memory Access  
Direct Random Access Memory  
Enhanced Integrated Device Electronics  
Extended Industry Standard Architecture  
Enhanced Programmable Read Only Memory  
First In, First Out  
EISA  
EPROM  
FIFO  
GART  
HSTL  
IDE  
Graphics Address Remapping Table  
High-Speed Transistor Logic  
Integrated Device Electronics  
88  
Appendix B - Conventions and Abbreviations  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 31. Acronyms (continued)  
Abbreviation  
ISA  
Meaning  
Industry Standard Architecture  
Instructions Per Cycle  
IPC  
JEDEC  
JTAG  
LAN  
Joint Electron Device Engineering Council  
Joint Test Action Group  
Large Area Network  
LRU  
Least-Recently Used  
LVTTL  
MSB  
MTRR  
MUX  
NMI  
Low Voltage Transistor Transistor Logic  
Most Significant Bit  
Memory Type and Range Registers  
Multiplexer  
Non-Maskable Interrupt  
Open-Drain  
OD  
OPGA  
PA  
Organic Pin Grid Array  
Physical Address  
PBGA  
PCI  
Plastic Ball Grid Array  
Peripheral Component Interconnect  
Page Directory Entry  
PDE  
PDT  
Page Directory Table  
PGA  
Pin Grid Array  
PLL  
Phase Locked Loop  
PMSM  
POS  
Power Management State Machine  
Power-On Suspend  
POST  
PP  
Power-On Self-Test  
Push-Pull  
RAM  
ROM  
RXA  
Random Access Memory  
Read Only Memory  
Read Acknowledge Queue  
Small Computer System Interface  
System DRAM Interface  
Synchronous Direct Random Access Memory  
Single Instruction Multiple Data  
Serial Initialization Packet  
System Management Bus  
Serial Presence Detect  
SCSI  
SDI  
SDRAM  
SIMD  
SIP  
SMbus  
SPD  
Appendix B - Conventions and Abbreviations  
89  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Table 31. Acronyms (continued)  
Abbreviation  
SRAM  
SROM  
TLB  
Meaning  
Synchronous Random Access Memory  
Serial Read Only Memory  
Translation Lookaside Buffer  
Top of Memory  
TOM  
TTL  
Transistor Transistor Logic  
Virtual Address Space  
Virtual Page Address  
VAS  
VPA  
VGA  
Video Graphics Adapter  
Universal Serial Bus  
USB  
ZDB  
Zero Delay Buffer  
90  
Appendix B - Conventions and Abbreviations  
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
Related Publications  
These documents provide helpful information about the  
AMD Athlon™ XP processor model 10, and can be found with  
other related documents at the AMD Web site,  
http://www.amd.com.  
AMD Athlon™ Processor x86 Code Optimization Guide, order#  
22007  
AMD Processor Recognition Application Note, order# 20734  
Methodologies for Measuring Temperature on AMD Athlon™  
and AMD Duron™ Processors, order# 24228  
AMD Thermal, Mechanical, and Chassis Cooling Design Guide,  
order# 23794  
Builders Guide for Desktop/Tower Systems, order# 26003  
Other Web sites of interest include the following:  
JEDEC home page—www.jedec.org  
IEEE home page—www.computer.org  
AGP Forum—www.agpforum.or  
Appendix B - Conventions and Abbreviations  
91  
 
Preliminary Information  
AMD Athlon™ XP Processor Model 10 Data Sheet  
26237C—May 2003  
92  
Appendix B - Conventions and Abbreviations  

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