C141-E104-02EN
MHL2300AT, MHM2200AT,
MHM2150AT, MHM2100AT
DISK DRIVES
PRODUCT MANUAL
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Revision History
(1/1)
Edition
Date
Revised section (*1)
(Added/Deleted/Altered)
Details
—
01
02
2000-02-15
—
2000-09-20 -Table 1.1
- Specification (Number of Sections for
MHL2300AT) was altered.
- Table 1.2
- Order No. was changed.
- (16) SET MAX in Section
- SET MAX commands are added.
5.3.2
- Table 5.17
- Values of host termination for DIOR-,
DIOW- and DMACK- signals are
changed.
*1 Section(s) with asterisk (*) refer to the previous edition when those were deleted.
C141-E104-02EN
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Preface
This manual describes the MHL Series and MHM Series, 2.5-inch hard disk drives.
These drives have a built-in controller that is compatible with the ATA interface.
This manual describes the specifications and functions of the drives and explains in
detail how to incorporate the drives into user systems. This manual assumes that
the reader has a basic knowledge of hard disk drives and their implementations in
computer systems.
This manual consists of seven chapters and sections explaining the special
terminology and abbreviations used in this manual:
Overview of Manual
CHAPTER 1
Device Overview
This chapter gives an overview of the MHL Series and MHM Series and describes
their features.
CHAPTER 2
Device Configuration
This chapter describes the internal configurations of the MHL Series and MHM
Series and the configuration of the systems in which they operate.
CHAPTER 3
Installation Conditions
This chapter describes the external dimensions, installation conditions, and switch
settings of the MHL Series and MHM Series.
CHAPTER 4
This chapter describes the operation theory of the MHL Series and MHM Series.
CHAPTER 5 Interface
Theory of Device Operation
This chapter describes the interface specifications of the MHL Series and MHM
Series.
CHAPTER 6
Operations
This chapter describes the operations of the MHL Series and MHM Series.
Terminology
This section explains the special terminology used in this manual.
Abbreviation
This section gives the meanings of the definitions used in this manual.
C141-E104-02EN
i
Preface
Conventions for Alert Messages
This manual uses the following conventions to show the alert messages. An alert
message consists of an alert signal and alert statements. The alert signal consists of
an alert symbol and a signal word or just a signal word.
The following are the alert signals and their meanings:
This indicates a hazardous situation could result in
minor or moderate personal injury if the user does
not perform the procedure correctly. This alert
signal also indicates that damages to the product or
other property may occur if the user does not perform
the procedure correctly.
CAUTION
This indicates information that could help the user
use the product more efficiently.
IMPORTANT
In the text, the alert signal is centered, followed below by the indented message. A
wider line space precedes and follows the alert message to show where the alert
message begins and ends. The following is an example:
(Example)
CAUTION
Data corruption: Avoid mounting the disk drive near strong
magnetic sources such as loud speakers. Ensure that the disk drive is
not affected by external magnetic fields.
The main alert messages in the text are also listed in the “Important Alert Items.”
Operating Environment
This product is designed to be used in offices or computer rooms.
For details regarding the operating environment of use, refer to the
(Cnnn-Xnnn) and the
(Cnnn-Xnnn).
Attention
Please forward any comments you may have regarding this manual.
To make this manual easier for users to understand, opinions from readers are
needed. Please write your opinions or requests on the Comment at the back of this
manual and forward it to the address described in the sheet.
ii
C141-E104-02EN
Preface
Liability Exception
“Disk drive defects” refers to defects that involve adjustment, repair, or
replacement.
Fujitsu is not liable for any other disk drive defects, such as those caused by user
misoperation or mishandling, inappropriate operating environments, defects in the
power supply or cable, problems of the host system, or other causes outside the
disk drive.
C141-E104-02EN
iii
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Important Alert Items
Important Alert Messages
The important alert messages in this manual are as follows:
A hazardous situation could result in minor or moderate personal
CAUTION
injury if the user does not perform the procedure correctly. Also,
damage to the predate or other property, may occur if the user does not
perform the procedure correctly.
Task
Alert message
Page
3-8
Normal Operation
Data corruption: Avoid mounting the disk near strong
magnetic sources such as loud speakers. Ensure that the disk
drive is not affected by external magnetic fields.
Damage: Do not press the cover of the disk drive. Pressing
it too hard, the cover and the spindle motor contact, which
may cause damage to the disk drive.
Static: When handling the device, disconnect the body
ground (500 kΩ or greater). Do not touch the printed circuit
board, but hold it by the edges.
C141-E104-02EN
v
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Manual Organization
MHL2300AT, MHM2200AT,
MHM2150AT, MHM2100AT
• Device Overview
• Device Configuration
• Installation Conditions
• Theory of Device Operation
• Interface
DISK DRIVES
PRODUCT MANUAL
(C141-E104)
• Operations
<This manual>
MHL2300AT, MHM2200AT,
MHM2150AT, MHM2100AT
• Maintenance and Diagnosis
• Removal and Replacement Procedure
DISK DRIVES
MAINTENANCE MANUAL
(C141-F043)
C141-E104-02EN
vii
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Contents
CHAPTER 1 Device Overview ....................................................................... 1-1
1.1 Features 1-2
1.1.1 Functions and performance 1-2
1.1.2 Adaptability 1-2
1.1.3 Interface 1-3
1.2 Device Specifications 1-4
1.2.1 Specifications summary 1-4
1.2.2 Model and product number 1-5
1.3 Power Requirements 1-5
1.4 Environmental Specifications 1-7
1.5 Acoustic Noise 1-8
1.6 Shock and Vibration 1-8
1.7 Reliability 1-9
1.8 Error Rate 1-10
1.9 Media Defects 1-10
CHAPTER 2 Device Configuration................................................................ 2-1
2.1 Device Configuration 2-2
2.2 System Configuration 2-4
2.2.1 ATA interface 2-4
2.2.2 1 drive connection 2-4
2.2.3 2 drives connection 2-4
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Contents
CHAPTER 3 Installation Conditions..............................................................3-1
3.1 Dimensions 3-2
3.2 Mounting 3-4
3.3 Cable Connections 3-10
3.3.1 Device connector 3-10
3.3.2 Cable connector specifications 3-11
3.3.3 Device connection 3-11
3.3.4 Power supply connector (CN1) 3-12
3.4 Jumper Settings 3-12
3.4.1 Location of setting jumpers 3-12
3.4.2 Factory default setting 3-13
3.4.3 Master drive-slave drive setting 3-13
3.4.4 CSEL setting 3-14
CHAPTER 4 Theory of Device Operation......................................................4-1
4.1 Outline 4-2
4.2 Subassemblies 4-2
4.2.1 Disk 4-2
4.2.2 Head 4-2
4.2.3 Spindle 4-3
4.2.4 Actuator 4-3
4.2.5 Air filter 4-3
4.3 Circuit Configuration 4-4
4.4 Power-on Sequence 4-7
4.5 Self-calibration 4-8
4.5.1 Self-calibration contents 4-8
4.5.2 Execution timing of self-calibration 4-9
4.5.3 Command processing during self-calibration 4-10
4.6 Read/write Circuit 4-10
4.6.1 Read/write preamplifier (HDIC) 4-10
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Contents
4.6.2 Write circuit 4-11
4.6.3 Read circuit 4-13
4.6.4 Digital PLL circuit 4-14
4.7 Servo Control 4-15
4.7.1 Servo control circuit 4-15
4.7.2 Data-surface servo format 4-18
4.7.3 Servo frame format 4-20
4.7.4 Actuator motor control 4-21
4.7.5 Spindle motor control 4-22
CHAPTER 5 Interface..................................................................................... 5-1
5.1 Physical Interface 5-2
5.1.1 Interface signals 5-2
5.1.2 Signal assignment on the connector 5-3
5.2 Logical Interface 5-6
5.2.1 I/O registers 5-7
5.2.2 Command block registers 5-8
5.2.3 Control block registers 5-13
5.3 Host Commands 5-13
5.3.1 Command code and parameters 5-14
5.3.2 Command descriptions 5-16
5.3.3 Error posting 5-83
5.4 Command Protocol 5-85
5.4.1 Data transferring commands from device to host 5-85
5.4.2 Data transferring commands from host to device 5-87
5.4.3 Commands without data transfer 5-89
5.4.4 Other commands 5-90
5.4.5 DMA data transfer commands 5-90
5.5 Ultra DMA Feature Set 5-92
5.5.1 Overview 5-92
5.5.2 Phases of operation 5-93
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Contents
5.5.2.1 Ultra DMA burst initiation phase 5-93
5.5.2.2 Data transfer phase 5-94
5.5.2.3 Ultra DMA burst termination phase 5-94
5.5.3 Ultra DMA data in commands 5-95
5.5.3.1 Initiating an Ultra DMA data in burst 5-95
5.5.3.2 The data in transfer 5-96
5.5.3.3 Pausing an Ultra DMA data in burst 5-96
5.5.3.4 Terminating an Ultra DMA data in burst 5-97
5.5.4 Ultra DMA data out commands 5-100
5.5.4.1 Initiating an Ultra DMA data out burst 5-100
5.5.4.2 The data out transfer 5-100
5.5.4.3 Pausing an Ultra DMA data out burst 5-101
5.5.4.4 Terminating an Ultra DMA data out burst 5-102
5.5.5 Ultra DMA CRC rules 5-104
5.5.6 Series termination required for Ultra DMA 5-106
5.6 Timing 5-107
5.6.1 PIO data transfer 5-107
5.6.2 Multiword DMA data transfer 5-109
5.6.3 Transfer of Ultra DMA data 5-110
5.6.3.1 Starting of Ultra DMA data In Burst 5-110
5.6.3.2 Ultra DMA data burst timing requirements 5-111
5.6.3.3 Sustained Ultra DMA data in burst 5-113
5.6.3.4 Host pausing an Ultra DMA data in burst 5-114
5.6.3.5 Device terminating an Ultra DMA data in burst 5-115
5.6.3.6 Host terminating an Ultra DMA data in burst 5-116
5.6.3.7 Initiating an Ultra DMA data out burst 5-117
5.6.3.8 Sustained Ultra DMA data out burst 5-118
5.6.3.9 Device pausing an Ultra DMA data out burst 5-119
5.6.3.10 Host terminating an Ultra DMA data out burst 5-120
5.6.3.11 Device terminating an Ultra DMA data in burst 5-121
5.6.4 Power-on and reset 5-122
CHAPTER 6 Operations .................................................................................6-1
6.1 Device Response to the Reset 6-2
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Contents
6.1.1 Response to power-on 6-2
6.1.2 Response to hardware reset 6-4
6.1.3 Response to software reset 6-5
6.1.4 Response to diagnostic command 6-6
6.2 Address Translation 6-7
6.2.1 Default parameters 6-7
6.2.2 Logical address 6-8
6.3 Power Save 6-9
6.3.1 Power save mode 6-9
6.3.2 Power commands 6-11
6.4 Defect Management 6-11
6.4.1 Spare area 6-12
6.4.2 Alternating defective sectors 6-12
6.5 Read-Ahead Cache 6-14
6.5.1 Data buffer configuration 6-14
6.5.2 Caching operation 6-14
6.5.3 Usage of read segment 6-16
6.5.3.1 Mis-hit (no hit) 6-16
6.5.3.2 Sequential read 6-17
6.5.3.3 Full hit (hit all) 6-20
6.5.3.4 Partially hit 6-21
6.6 Write Cache 6-22
Glossary
..................................................................................................GL-1
Acronyms and Abbreviations......................................................................... AB-1
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xiii
Contents
Illustrations
Figures
Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-7
Figure 2.1 Disk drive outerview (the MHL Series and MHM Series) 2-2
Figure 2.2 Configuration of disk media heads 2-3
Figure 2.3 1 drive system configuration 2-4
Figure 2.4 2 drives configuration 2-4
Figure 3.1 Dimensions (MHL/MHM series) 3-2
Figure 3.2 Orientation (Sample: MHL2300AT) 3-4
Figure 3.3 Mounting frame structure 3-5
Figure 3.4 Location of breather 3-6
Figure 3.5 Surface temperature measurement points
(Sample: MHL2300AT) 3-7
Figure 3.6 Service area (Sample: MHL2300AT) 3-8
Figure 3.7 Handling cautions 3-9
Figure 3.8 Connector locations (Sample: MHL2300AT) 3-10
Figure 3.9 Cable connections 3-11
Figure 3.10 Power supply connector pins (CN1) 3-12
Figure 3.11 Jumper location 3-12
Figure 3.12 Factory default setting 3-13
Figure 3.13 Jumper setting of master or slave device 3-13
Figure 3.14 CSEL setting 3-14
Figure 3.15 Example (1) of Cable Select 3-14
Figure 3.16 Example (2) of Cable Select 3-15
Figure 4.1 Head structure 4-3
Figure 4.2 Power Supply Configuration 4-5
Figure 4.3 Circuit Configuration 4-6
Figure 4.4 Power-on operation sequence 4-8
Figure 4.5 Read/write circuit block diagram 4-12
Figure 4.6 Frequency characteristic of programmable filter 4-13
Figure 4.7 Block diagram of servo control circuit 4-15
Figure 4.8 Physical sector servo configuration on disk surface 4-19
Figure 4.9 Servo frame format 4-20
Figure 5.1 Interface signals 5-2
Figure 5.2 Execution example of READ MULTIPLE command 5-20
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Contents
Figure 5.3 Read Sector(s) command protocol 5-86
Figure 5.4 Protocol for command abort 5-87
Figure 5.5 WRITE SECTOR(S) command protocol 5-88
Figure 5.6 Protocol for the command execution without data transfer 5-90
Figure 5.7 Normal DMA data transfer 5-91
Figure 5.8 An example of generation of parallel CRC 5-105
Figure 5.9 Ultra DMA termination with pull-up or pull-down 5-106
Figure 5.10 Data transfer timing 5-108
Figure 5.11 Multiword DMA data transfer timing (mode 2) 5-109
Figure 5.12 Starting of Ultra DMA data In Burst transfer 5-110
Figure 5.13 Sustained Ultra DMA data in burst 5-113
Figure 5.14 Host pausing an Ultra DMA data in burst 5-114
Figure 5.15 Device terminating an Ultra DMA data in burst 5-115
Figure 5.16 Host terminating an Ultra DMA data in burst 5-116
Figure 5.17 Initiating an Ultra DMA data out burst 5-117
Figure 5.18 Sustained Ultra DMA data out burst 5-118
Figure 5.19 Device pausing an Ultra DMA data out burst 5-119
Figure 5.20 Host terminating an Ultra DMA data out burst 5-120
Figure 5.21 Device terminating an Ultra DMA data out burst 5-121
Figure 5.22 Power on Reset Timing 5-122
Figure 6.1 Response to power-on 6-3
Figure 6.2 Response to hardware reset 6-4
Figure 6.3 Response to software reset 6-5
Figure 6.4 Response to diagnostic command 6-6
Figure 6.5 Address translation (example in CHS mode) 6-8
Figure 6.6 Address translation (example in LBA mode) 6-9
Figure 6.7 Sector slip processing 6-12
Figure 6.8 Alternate cylinder assignment 6-13
Figure 6.9 Data buffer configuration 6-14
Tables
Table 1.1 Specifications 1-4
Table 1.2 Model names and product numbers 1-5
Table 1.3 Current and power dissipation 1-6
Table 1.4 Environmental specifications 1-7
Table 1.5 Acoustic noise specification 1-8
Table 1.6 Shock and vibration specification 1-8
Table 3.1 Surface temperature measurement points and standard values 3-7
Table 3.2 Cable connector specifications 3-11
C141-E104-02EN
xv
Contents
Table 4.1 Self-calibration execution timechart 4-10
Table 4.2 Write precompensation algorithm 4-11
Table 5.1 Signal assignment on the interface connector 5-3
Table 5.2 I/O registers 5-7
Table 5.3 Command code and parameters 5-14
Table 5.4 Information to be read by IDENTIFY DEVICE command 5-32
Table 5.5 Features register values and settable modes 5-41
Table 5.6 Diagnostic code 5-52
Table 5.7 Features Register values (subcommands) and functions 5-64
Table 5.8 Format of device attribute value data 5-68
Table 5.9 Format of insurance failure threshold value data 5-68
Table 5.10 SMART error log data format 5-72
Table 5.11 SMART self test log data format 5-74
Table 5.12 Contents of security password 5-76
Table 5.13 Contents of SECURITY SET PASSWORD data 5-80
Table 5.14 Relationship between combination of Identifier and Security level,
and operation of the lock function 5-80
Table 5.15 Command code and parameters 5-83
Table 5.16 Parallel generation equation of CRC polynomial 5-105
Table 5.17 Recommended series termination for Ultra DMA 5-106
Table 5.18 Ultra DMA data burst timing requirements 5-111
Table 6.1 Default parameters 6-7
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CHAPTER 1 Device Overview
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Features
Device Specifications
Power Requirements
Environmental Specifications
Acoustic Noise
Shock and Vibration
Reliability
Error Rate
Media Defects
Overview and features are described in this chapter, and specifications and power
requirement are described.
The MHL Series and MHM Series are 2.5-inch hard disk drives with built-in disk
controllers. These disk drives use the AT-bus hard disk interface protocol and are
compact and reliable.
C141-E104-02EN
1-1
Device Overview
1.1 Features
1.1.1 Functions and performance
The following features of the MHL Series and MHM Series are described.
(1) Compact
The MHL2300AT has 3 built-in disks (the diameter is 65mm[2.5inch]), and its
height is 12.5 mm (0.492 inch). The MHM2200AT, MHM2150AT and
MHM2100AT have 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its
height is 9.5 mm (0.374 inch).
(2) Large capacity
The disk drive can record up to 10 GB (formatted) on one disk using the 16/17
MTR recording method and 15 recording zone technology. The MHL Series and
MHM Series have a formatted capacity of 30 GB (MHL2300AT), 20 GB
(MHM2200AT), 15 GB (MHM2150AT) and 10 GB (MHM2100AT) respectively.
(3) High-speed Transfer rate
The disk drives (the MHL Series and MHM Series) have an internal data rate up
to 28.7 MB/s. The disk drive supports an external data rate up to 66.6 MB/s (U-
DMA mode 4).
(4) Average positioning time
Use of a rotary voice coil motor in the head positioning mechanism greatly
increases the positioning speed. The average positioning time is 12 ms (at read).
1.1.2 Adaptability
(1) Power save mode
The power save mode feature for idle operation, stand by and sleep modes makes
The disk drives (the MHL Series and MHM Series) ideal for applications where
power consumption is a factor.
(2) Wide temperature range
The disk drives (the MHL Series and MHM Series) can be used over a wide
temperature range (5°C to 55°C).
(3) Low noise and vibration
In Ready status, the noise of the disk drives (the MHL Series and MHM Series) is
only about 30 dBA (measured at 1 m apart from the drive under the idle mode).
1-2
C141-E104-02EN
1.1 Features
1.1.3 Interface
(1) Connection to interface
With the built-in ATA interface controller, the disk drives (the MHL Series and
MHM Series) can be connected to an ATA interface of a personal computer.
(2) 2 MB data buffer
The disk drives (the MHL Series and MHM Series) uses a 2 MB data buffer to
transfer data between the host and the disk media.
In combination with the read-ahead cache system described in item (3) and the
write cache described in item (7), the buffer contributes to efficient I/O
processing.
(3) Read-ahead cache system
After the execution of a disk read command, the disk drive automatically reads the
subsequent data block and writes it to the data buffer (read ahead operation). This
cache system enables fast data access. The next disk read command would
normally cause another disk access. But, if the read ahead data corresponds to the
data requested by the next read command, the data in the buffer can be transferred
instead.
(4) Master/slave
The disk drives (the MHL Series and MHM Series) can be connected to ATA
interface as daisy chain configuration. Drive 0 is a master device, drive 1 is a
slave device.
(5) Error correction and retry by ECC
If a recoverable error occurs, the disk drives (the MHL Series and MHM Series)
themselves attempt error recovery. The ECC has improved buffer error correction
for correctable data errors.
(6) Self-diagnosis
The disk drives (the MHL Series and MHM Series) have a diagnostic function to
check operation of the controller and disk drives. Executing the diagnostic
command invokes self-diagnosis.
(7) Write cache
When the disk drives (the MHL Series and MHM Series) receive a write
command, the disk drives post the command completion at completion of
transferring data to the data buffer completion of writing to the disk media. This
feature reduces the access time at writing.
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1-3
Device Overview
1.2 Device Specifications
1.2.1 Specifications summary
Table 1.1 shows the specifications of the disk drives (MHL Series and MHM Series).
Table 1.1 Specifications (1/2)
MHL2300AT MHM2200AT MHM2150AT MHM2100AT
Format Capacity (*1)
Number of Heads
30 GB
6
20 GB
4
15 GB
3
10 GB
2
Number of Cylinders (User)
Number of Sectors (User)
Bytes per Sector
19,904
512
58,605,120
39,070,080
29,498,112
19,640,880
Recording Method
Track Density
16/17 MTR
32,300 TPI (1271 track/mm)
499.7 Kbpi (19.67 k bit/mm)
4,200 rpm ± 1%
Bit Density
Rotational Speed
Average Latency
7.14 ms
Positioning time (read and seek)
•
•
•
Minimum (Track to Track)
Average
1.5 ms (typ.)
Read: 12 ms (typ.)
22 ms (typ.)
Maximum (Full)
Start/Stop time
•
•
Start (0 rpm to Drive Read)
Stop (at Power Down)
Typ.: 5 sec
Typ.: 5 sec
Interface
ATA-5 (Max. Cable length: 0.46 m)
Data Transfer Rate
•
•
To/From Media
To/From Host
16.4 to 28.7 MB/s
66.6 MB/s Max.
(U-DMA mode 4)
Data Buffer Size
2 MB
Physical Dimensions
(Height × Width × Depth)
12.5 mm ×
100.0 mm ×
70.0 mm
9.5 mm × 100.0 mm ×70.0 mm
Weight
134 g
98 g
*1: Capacity under the LBA mode.
1-4
C141-E104-02EN
1.3 Power Requirements
Under the CHS mode (normal BIOS specification), formatted capacity,
number of cylinders, number of heads, and number of sectors are as
follows.
Table 1.1 Specifications (2/2)
Model
Capacity
No. of Cylinder
No. of Heads
No. of Sectors
MHL2300AT
MHM2200AT
MHM2150AT
MHM2100AT
8.45 GB
8.45 GB
8.45 GB
8.45 GB
16,383
16,383
16,383
16,383
16
16
16
16
63
63
63
63
1.2.2 Model and product number
Table 1.2 lists the model names and product numbers of the MHL Series and
MHM Series.
Table 1.2 Model names and product numbers
Model Name
Capacity
Mounting screw
Order No.
(user area)
MHL2300AT
MHM2200AT
MHM2150AT
MHM2100AT
30 GB
20 GB
15 GB
10 GB
M3, depth 3
M3, depth 3
M3, depth 3
M3, depth 3
CA05428-B061
CA05429-B041
CA05429-B031
CA05429-B021
1.3 Power Requirements
(1) Input Voltage
•
+ 5 V ± 5 %
(2) Ripple
+5 V
Maximum
Frequency
100 mV (peak to peak)
DC to 1 MHz
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1-5
Device Overview
(3) Current Requirements and Power Dissipation
Table 1.3 lists the current and power dissipation.
Table 1.3 Current and power dissipation
Typical RMS Current
Typical Power (*3)
MHL Series MHM Series MHL Series
MHM Series
4.5 W
Spin up (*1)
Idle
0.9 A
190 mA
520 mA
490 mA
50 mA
20 mA
—
0.9 A
160 mA
500 mA
460 mA
50 mA
20 mA
—
4.5 W
0.95 W
2.6 W
0.8 W
R/W (on track) (*2)
Seek (*5)
Standby
2.5 W
2.45 W
0.25 W
0.1 W
2.3 W
0.25 W
0.1 W
Sleep
Energy
Efficiency (*4)
0.032 W/GB
(rank E)
0.040 W/GB
(rank E / MHM2200AT)
0.040 W/GB
(rank E / MHM2150AT)
0.080 W/GB
(rank D / MHM2100AT)
*1
*2
*3
*4
Current at starting spindle motor.
At 30% disk accessing.
Power requirements reflect nominal values for +5V power.
Energy efficiency based on the Law concerning the Rational Use of Energy
indicates the value obtained by dividing power consumption by the storage
capacity. (Japan only)
*5
The seek average current is specified based on three operations per 100
msec.
(4) Current fluctuation (Typ.) at +5V when power is turned on
1-6
C141-E104-02EN
1.4 Environmental Specifications
Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on
(5) Power on/off sequence
The voltage detector circuits (the MHL Series and MHM Series) monitor +5 V.
The circuits do not allow a write signal if either voltage is abnormal. These
prevent data from being destroyed and eliminates the need to be concerned with
the power on/off sequence.
1.4 Environmental Specifications
Table 1.4 lists the environmental specifications.
Table 1.4 Environmental specifications
Item
Specification
Temperature
• Operating
5°C to 55°C (ambient)
5°C to 60°C (disk enclosure surface)
–40°C to 65°C
• Non-operating
• Thermal Gradient
Humidity
20°C/h or less
• Operating
8% to 90% RH (Non-condensing)
5% to 95% RH (Non-condensing)
• Non-operating
• Maximum Wet Bulb
29°C (Operating)
40°C (Non-operating)
Altitude (relative to sea level)
• Operating
–300 to 3,000 m
–300 to 12,000 m
• Non-operating
C141-E104-02EN
1-7
Device Overview
1.5 Acoustic Noise
Table 1.5 lists the acoustic noise specification.
Table 1.5 Acoustic noise specification
Item
Specification
Sound Pressure
• Idle mode (DRIVE READY)
30 dBA typical at 1 m
Note:
Measure the noise from the cover top surface.
1.6 Shock and Vibration
Table 1.6 lists the shock and vibration specification.
Table 1.6 Shock and vibration specification
Item
Specification
Vibration (swept sine, one octave per minute)
• Operating
5 to 500 Hz, 1.0G 0-peak (MHL series)
5 to 400 Hz, 1.0G 0-peak (MHM series)
(without non-recovered errors) (9.8 m/s2 0-peak)
• Non-operating
5 to 500 Hz, 5G 0-peak (MHL series)
5 to 400 Hz, 5G 0-peak (MHM series)
(no damage) (49 m/s2 0-peak)
Shock (half-sine pulse)
• Operating
175G 0-peak (1,715 m/s2 0-peak)
2 ms duration (without non-recovered errors)
• Non-operating
600G 0-peak (5,880 m/s2 0-peak)
2 ms duration (no damage)
MHL series
700G 0-peak (6,860 m/s2 0-peak)
2 ms duration (no damage)
MHM series
120G 0-peak (1,176 m/s2 0-peak)
11 ms duration (no damage)
1-8
C141-E104-02EN
1.7 Reliability
1.7
Reliability
(1) Mean time between failures (MTBF)
Conditions of 300,000 h Power-on time 250H/month or less 3000H/years
or less
Operating time 20% or less of power-on time
CSS operations 50/day or less
Total 50,000 or less
Power on/off
Environment
1/day or more needed.
5 to 55°C/8 to 90%
But humidity bulb temperature
29°C or less
MTBF is defined as follows:
Total operation time in all fields
MTBF=
(H)
number of device failure in all fields (*1)
*1 “Disk drive defects” refers to defects that involve repair, readjustment, or
replacement. Disk drive defects do not include failures caused by external
factors, such as damage caused by handling, inappropriate operating
environments, defects in the power supply host system, or interface cable.
(2) Mean time to repair (MTTR)
The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist
maintenance staff member.
(3) Service life
In situations where management and handling are correct, the disk drive requires
no overhaul for five years when the DE surface temperature is less than 48°C.
When the DE surface temperature exceeds 48°C, the disk drives requires no
overhaul for five years or 20,000 hours of operation, whichever occurs first.
Refer to item (3) in Subsection 3.2 for the measurement point of the DE surface
temperature. Also the operating conditions except the environment temperature
are based on the MTBF conditions.
(4) Data assurance in the event of power failure
Except for the data block being written to, the data on the disk media is assured in
the event of any power supply abnormalities. This does not include power supply
abnormalities during disk media initialization (formatting) or processing of
defects (alternative block assignment).
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1-9
Device Overview
1.8 Error Rate
Known defects, for which alternative blocks can be assigned, are not included in
the error rate count below. It is assumed that the data blocks to be accessed are
evenly distributed on the disk media.
(1) Unrecoverable read error
Read errors that cannot be recovered by maximum read retries of drive without
user’s retry and ECC corrections shall occur no more than 10 times when reading
data of 1014 bits. Read retries are executed according to the disk drive’s error
recovery procedure, and include read retries accompanying head offset operations.
(2) Positioning error
Positioning (seek) errors that can be recovered by one retry shall occur no more
than 10 times in 107 seek operations.
1.9 Media Defects
Defective sectors are replaced with alternates when the disk (the MHL Series and
MHM Series) are formatted prior to shipment from the factory (low level format).
Thus, the hosts see a defect-free devices.
Alternate sectors are automatically accessed by the disk drive. The user need not
be concerned with access to alternate sectors.
1-10
C141-E104-02EN
CHAPTER 2 Device Configuration
2.1
2.2
Device Configuration
System Configuration
This chapter describes the internal configurations of the hard disk drives and the
configuration of the systems in which they operate.
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2-1
Device Configuration
2.1 Device Configuration
Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE),
read/write preamplifier, and controller PCA. The disk enclosure contains the disk
media, heads, spindle motors, actuators, and a circulating air filter.
MHL Series
MHM Series
Figure 2.1 Disk drive outerview
(1) Disk
The outer diameter of the disk is 65 mm. The inner diameter is 20 mm. The
number of disks used varies with the model, as described below. The disks are
rated at over 50,000 start/stop operations.
MHL2300AT: 3 disks
MHM2200AT: 2 disks
MHM2150AT: 2 disks
MHM2100AT: 1 disk
(2) Head
The heads are of the contact start/stop (CSS) type. The head touches the disk
surface while the disk is not rotating and automatically lifts when the disk starts.
Figure 2.2 illustrates the configuration of the disks and heads of each model. In
the disk surface, servo information necessary for controlling positioning and
read/write and user data are written. Numerals 0 to 5 indicate read/write heads.
2-2
C141-E104-02EN
2.1 Device Configuration
Head
5
4
Head
3
Head
3
3
2
2
2
Head
1
1
0
1
0
1
0
0
MHL2300AT
MHM2200AT
MHM2150AT
(Either of head 0 or
MHM2100AT
head 3 is mounted.)
Figure 2.2 Configuration of disk media heads
(3) Spindle motor
The disks are rotated by a direct drive Hall-less DC motor.
(4) Actuator
The actuator uses a revolving voice coil motor (VCM) structure which consumes
low power and generates very little heat. The head assembly at the edge of the
actuator arm is controlled and positioned by feedback of the servo information
read by the read/write head. If the power is not on or if the spindle motor is
stopped, the head assembly stays in the specific CSS zone on the disk and is fixed
by a mechanical lock.
(5) Air circulation system
The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk
enclosure features a closed loop air circulation system that relies on the blower
effect of the rotating disk. This system continuously circulates the air through the
circulation filter to maintain the cleanliness of the air within the disk enclosure.
(6) Read/write circuit
The read/write circuit uses a LSI chip for the read/write preamplifier. It improves
data reliability by preventing errors caused by external noise.
(7) Controller circuit
The controller circuit consists of an LSI chip to improve reliability. The high-
speed microprocessor unit (MPU) achieves a high-performance AT controller.
C141-E104-02EN
2-3
Device Configuration
2.2 System Configuration
2.2.1 ATA interface
Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a
44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6 MB/s,
Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 4 transfer
at 66.6 MB/s.
2.2.2 1 drive connection
MHL2300AT
MHM2200AT
MHM2150AT
MHM2100AT
Figure 2.3 1 drive system configuration
2.2.3 2 drives connection
MHL2300AT
MHM2200AT
(Host adaptor)
MHM2150AT
MHM2100AT
MHL2300AT
MHM2200AT
MHM2150AT
MHM2100AT
Note:
When the drive that is not conformed to ATA is connected to the disk drive above
configuration, the operation is not guaranteed.
Figure 2.4 2 drives configuration
2-4
C141-E104-02EN
2.2 System Configuration
IMPORTANT
HA (host adaptor) consists of address decoder, driver, and receiver.
ATA is an abbreviation of “AT attachment”. The disk drive is
conformed to the ATA-4 interface.
At high speed data transfer (PIO mode 3, mode 4, or DMA mode 2
U-DMA mode 4), occurrence of ringing or crosstalk of the signal
lines (AT bus) between the HA and the disk drive may be a great
cause of the obstruction of system reliability. Thus, it is necessary
that the capacitance of the signal lines including the HA and cable
does not exceed the ATA-5 standard, and the cable length between
the HA and the disk drive should be as short as possible.
No need to push the top cover of the disk drive. If the over-power
worked, the cover could be contacted with the spindle motor. Thus,
that could be made it the cause of failure.
C141-E104-02EN
2-5
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CHAPTER 3 Installation Conditions
3.1
3.2
3.3
3.4
Dimensions
Mounting
Cable Connections
Jumper Settings
This chapter gives the external dimensions, installation conditions, surface
temperature conditions, cable connections, and switch settings of the hard disk
drives.
C141-E104-02EN
3-1
Installation Conditions
3.1 Dimensions
Figure 3.1 illustrates the dimensions of the disk drive and positions of the
mounting screw holes. All dimensions are in mm.
Figure 3.1 Dimensions (MHL series) (1/2)
3-2
C141-E104-02EN
3.1 Dimensions
Figure 3.1 Dimensions (MHM series) (2/2)
C141-E104-02EN
3-3
Installation Conditions
3.2 Mounting
(1) Orientation
Figure 3.2 illustrates the allowable orientations for the disk drive.
gravity
(a) Horizontal –1
(b) Horizontal –1
gravity
(c) Vertical –1
(d) Vertical –2
gravity
(e) Vertical –3
(f) Vertical –4
Figure 3.2 Orientation (Sample: MHL2300AT)
3-4
C141-E104-02EN
3.2 Mounting
(2) Frame
The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame
is connected to SG.
IMPORTANT
Use M3 screw for the mounting screw and the screw length should
satisfy the specification in Figure 3.3.
The tightening torque must be 0.49N·m(5kgf·cm).
When attaching the HDD to the system frame, do not allow the
system frame to touch parts (cover and base) other than parts to
which the HDD is attached.
(3) Limitation of mounting
Do not use the center hole. For screw length, see Figure 3.3.
Note)
These dimensions are recommended values; if it is not possible to
satisfy them, contact us.
Side surface
mounting
2.5
2.5
Bottom surface mounting
DE
2.5
2.5
2
B
PCA
A
Frame of system
cabinet
Frame of system
cabinet
3.0 or less
Details of A
Screw
Screw
3.0 or less
Details of B
Figure 3.3 Mounting frame structure
C141-E104-02EN
3-5
Installation Conditions
IMPORTANT
Because of breather hole mounted to the HDD, do not allow this to
close during mounting.
Locating of breather hole is shown as Figure 3.4 in both MHL
series and MHM series.
For breather hole of Figure 3.4, at least, do not allow its around φ3
to block.
Figure 3.4 Location of breather
3-6
C141-E104-02EN
3.2 Mounting
(4) Ambient temperature
The temperature conditions for a disk drive mounted in a cabinet refer to the
ambient temperature at a point 3 cm from the disk drive. The ambient
temperature must satisfy the temperature conditions described in Section 1.4, and
the airflow must be considered to prevent the DE surface temperature from
exceeding 60°C.
Provide air circulation in the cabinet such that the PCA side, in particular,
receives sufficient cooling. To check the cooling efficiency, measure the surface
temperatures of the DE. Regardless of the ambient temperature, this surface
temperature must meet the standards listed in Table 3.1. Figure 3.5 shows the
temperature measurement point.
1
Figure 3.5 Surface temperature measurement points (Sample: MHL2300AT)
Table 3.1 Surface temperature measurement points and standard values
No.
1
Measurement point
DE cover
Temperature
60°C max
C141-E104-02EN
3-7
Installation Conditions
(5) Service area
Figure 3.6 shows how the drive must be accessed (service areas) during and after
installation.
Mounting screw hole
Cable connection
Mounting screw hole
Figure 3.6 Service area (Sample: MHL2300AT)
CAUTION
Data corruption: Avoid mounting the disk drive near strong
magnetic sources such as loud speakers. Ensure that the disk drive
is not affected by external magnetic fields.
Damage: Do not press the cover of the disk drive. Pressing it too
hard, the cover and the spindle motor contact, which may cause
damage to the disk drive.
Static: When handling the device, disconnect the body ground
(500 kΩ or greater). Do not touch the printed circuit board, but
hold it by the edges.
(6) Handling cautions
Please keep the following cautions, and handle the HDD under the safety
environment.
3-8
C141-E104-02EN
3.2 Mounting
- General notes
ESD mat
Wrist strap
Shock absorbing mat
Use the Wrist strap.
Place the shock absorbing mat on the
operation table, and place ESD mat on it.
Do not hit HDD each other.
Do not stack when carrying.
Do not place HDD vertically
to avoid falling down.
Do not drop.
Figure 3.7 Handling cautions
- Installation
(1)
(2)
Please use the driver of a low impact when you use an electric driver.
HDD is occasionally damaged by the impact of the driver.
Please observe the tightening torque of the screw strictly.
M3 ······· 0.49 N·m (5 Kg·cm)
- Recommended equipments
Contents
Model
JX-1200-3056-8
76000DES (ASK7876)
SS-3000
Maker
SUMITOMO 3M
COMKYLE
HIOS
ESD
Wrist strap
ESD mat
Shock
Low shock driver
C141-E104-02EN
3-9
Installation Conditions
3.3 Cable Connections
3.3.1 Device connector
The disk drive has the connectors and terminals listed below for connecting
external devices. Figure 3.8 shows the locations of these connectors and
terminals.
PCA
Connector,
setting pins
Figure 3.8 Connector locations (Sample: MHL2300AT)
3-10
C141-E104-02EN
3.3 Cable Connections
3.3.2 Cable connector specifications
Table 3.2 lists the recommended specifications for the cable connectors.
Table 3.2 Cable connector specifications
Name
Model
Manufacturer
BERG
ATA interface and power
supply cable (44-pin type)
Cable socket
(44-pin type)
89361-144
IMPORTANT
For the host interface cable, use a ribbon cable. A twisted cable or
a cable with wires that have become separated from the ribbon may
cause crosstalk between signal lines. This is because the interface
is designed for ribbon cables and not for cables carrying differential
signals.
3.3.3 Device connection
Figure 3.9 shows how to connect the devices.
Figure 3.9 Cable connections
C141-E104-02EN
3-11
Installation Conditions
3.3.4 Power supply connector (CN1)
Figure 3.10 shows the pin assignment of the power supply connector (CN1).
Figure 3.10 Power supply connector pins (CN1)
3.4 Jumper Settings
3.4.1 Location of setting jumpers
Figure 3.11 shows the location of the jumpers to select drive configuration and
functions.
Figure 3.11 Jumper location
3-12
C141-E104-02EN
3.4 Jumper Settings
3.4.2 Factory default setting
Figure 3.12 shows the default setting position at the factory.
Open
Figure 3.12 Factory default setting
3.4.3 Master drive-slave drive setting
Master drive (disk drive #0) or slave drive (disk drive #1) is selected.
Open
1
2
C
D
A
B
A
1
2
C
Short
Open
D
B
Open
(a) Master drive
(b) Slave drive
Figure 3.13 Jumper setting of master or slave drive
Note:
Pins A and C should be open.
C141-E104-02EN
3-13
Installation Conditions
3.4.4 CSEL setting
Figure 3.14 shows the cable select (CSEL) setting.
Open
1
2
C
A
D
B
Short
Note:
The CSEL setting is not depended on setting between pins Band D.
Figure 3.14 CSEL setting
Figure 3.15 and 3.16 show examples of cable selection using unique interface
cables.
By connecting the CSEL of the master drive to the CSEL Line (conducer) of the
cable and connecting it to ground further, the CSEL is set to low level. The drive
is identified as a master drive. At this time, the CSEL of the slave drive does not
have a conductor. Thus, since the slave drive is not connected to the CSEL
conductor, the CSEL is set to high level. The drive is identified as a slave drive.
drive
drive
Figure 3.15 Example (1) of Cable Select
3-14
C141-E104-02EN
3.4 Jumper Settings
drive
drive
Figure 3.16 Example (2) of Cable Select
C141-E104-02EN
3-15
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CHAPTER 4 Theory of Device Operation
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Outline
Subassemblies
Circuit Configuration
Power-on Sequence
Self-calibration
Read/write Circuit
Servo Control
This chapter explains basic design concepts of the disk drive. Also, this chapter
explains subassemblies of the disk drive, each sequence, servo control, and
electrical circuit blocks.
C141-E104-02EN
4-1
Theory of Device Operation
4.1 Outline
This chapter consists of two parts. First part (Section 4.2) explains mechanical
assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a
servo information recorded in the disk drive and drive control method.
4.2 Subassemblies
The disk drive consists of a disk enclosure (DE) and printed circuit assembly
(PCA).
The DE contains all movable parts in the disk drive, including the disk, spindle,
actuator, read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.5.
The PCA contains the control circuits for the disk drive. The disk drive has one
PCA. For details, see Sections 4.3.
4.2.1 Disk
The DE contains disks with an outer diameter of 65 mm and an inner diameter of
20 mm. The MHL2300AT have three disks and MHM2200AT and
MHM2150AT have two disks and MHM2100AT have one disk.
The head contacts the disk each time the disk rotation stops; the disk surface is
durable at least 50,000 CSS (Contact Start/Stop) or more.
Servo data is recorded on each cylinder (total 66). Servo data written at factory is
read out by the read head. For servo data, see Section 4.7.
4.2.2 Head
Figure 4.1 shows the head structures. MHL2300AT has 6 heads and
MHM2200AT has 4 heads and MHM2150AT has 3 heads and MHM2100AT has
2 heads. These heads are raised from the disk surface as the spindle motor the
rated rotation speed.
4-2
C141-E104-02EN
4.2 Subassemblies
Head
5
4
Head
3
Head
3
3
2
2
2
Head
1
1
0
1
0
1
0
0
MHL2300AT
MHM2200AT
MHM2150AT
(Either of head 0 or
MHK2100AT
head 3 is mounted.)
Figure 4.1 Head structure
4.2.3 Spindle
The spindle consists of a disk stack assembly and spindle motor. The disk stack
assembly is activated by the direct drive sensor-less DC spindle motor, which has
a speed of 4,200 rpm ±1%. The spindle is controlled with detecting a PHASE
signal generated by counter electromotive voltage of the spindle motor at starting.
4.2.4 Actuator
The actuator consists of a voice coil motor (VCM) and a head carriage. The
VCM moves the head carriage along the inner or outer edge of the disk. The head
carriage position is controlled by feeding back the difference of the target position
that is detected and reproduced from the servo information read by the read/write
head.
4.2.5 Air filter
There are two types of air filters: a breather filter and a circulation filter.
The breather filter makes an air in and out of the DE to prevent unnecessary
pressure around the spindle when the disk starts or stops rotating. When disk
drives are transported under conditions where the air pressure changes a lot,
filtered air is circulated in the DE.
The circulation filter cleans out dust and dirt from inside the DE. The disk drive
cycles air continuously through the circulation filter through an enclosed loop air
cycle system operated by a blower on the rotating disk.
C141-E104-02EN
4-3
Theory of Device Operation
4.3 Circuit Configuration
Figure 4.2 shows the power supply configuration of the disk drive, and Figure 4.3
shows the disk drive circuit configuration.
(1) Read/write circuit
The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and
read channel (RDC).
The PreAMP consists of the write current switch circuit, that flows the write
current to the head coil, and the voltage amplifier circuit, that amplitudes the read
output from the head.
The RDC is the read demodulation circuit using the Modified Extended Partial
Response (MEEPR), and contains the Viterbi detector, programmable filter,
adaptable transversal filter, times base generator, data separator circuits, 16/17
MTR (Maximum Transitions Limited) encoder Run Length and servo
demodulation circuit.
(2) Servo circuit
The position and speed of the voice coil motor are controlled by 2 closed-loop
servo using the servo information recorded on the data surface. The servo
information is an analog signal converted to digital for processing by a MPU and
then reconverted to an analog signal for control of the voice coil motor.
The MPU precisely sets each head on the track according on the servo
information on the media surface.
(3) Spindle motor driver circuit
The circuit measures the interval of a PHASE signal generated by counter-
electromotive voltage of a motor at the MPU and controls the motor speed
comparing target speed.
(4) Controller circuit
Major functions are listed below.
•
•
•
•
•
•
Data buffer (2 MB) management
ATA interface control and data transfer control
Sector format control
Defect management
ECC control
Error recovery and self-diagnosis
4-4
C141-E104-02EN
4.3 Circuit Configuration
5V
HDC
SVC
HDIC
MCU
FROM
- 3V
3.3V
SDRAM
RDC
Figure 4.2 Power Supply Configuration
C141-E104-02EN
4-5
Theory of Device Operation
Printed
Circuit
Board
FROM
Program
Memory
16 bit
Local Bus
Host
ATA
HDC
MPU
Interface
(Hard Disk
Controller)
(Micro
Processor
Unit)
SVC
Control
Signal
RDC
Control
Signal
Read
and
Write
Data
Data
Buffer
Bus
HDIC
Control
Signal
16 bit
SDRAM
RDC
Read
Channel
SVC
Data
Motor
Servo
Pulse
and
Position
Signal
Buffer
RAM
Controller
and
Driver
Write Data
HDIC
Read Data
Disk
Enclosure Head
(Read/Write
Preamplifier)
Voice
Coil
Motor
Spindle
Motor
Read
Head
Read Data
Write Data
Write
Head
Figure 4.3 Circuit Configuration
4-6
C141-E104-02EN
4.3 Circuit Configuration
4.4 Power-on Sequence
Figure 4.4 describes the operation sequence of the disk drive at power-on. The
outline is described below.
a) After the power is turned on, the disk drive executes the MPU bus test,
internal register read/write test, and work RAM read/write test. When the
self-diagnosis terminates successfully, the disk drive starts the spindle motor.
b) The disk drive executes self-diagnosis (data buffer read/write test) after
enabling response to the ATA bus.
c) After confirming that the spindle motor has reached rated speed, the disk
drive releases the heads from the actuator magnet lock mechanism by
applying current to the VCM. This unlocks the heads which are parked at the
inner circumference of the disks.
d) The disk drive positions the heads onto the SA area and reads out the system
information.
e) The disk drive executes self-seek-calibration. This collects data for VCM
torque and mechanical external forces applied to the actuator, and updates the
calibrating value.
f) The drive becomes ready. The host can issue commands.
C141-E104-02EN
4-7
Theory of Device Operation
Power-on
Start
a)
Self-diagnosis 1
- MPU bus test
- Internal register
write/read test
- Work RAM write/read
test
The spindle motor starts.
b)
c)
Self-diagnosis 2
- Data buffer write/read
test
d)
Initial on-track and read
out of system information
Confirming spindle motor
speed
e)
f)
Execute self-calibration
Releasing heads from
Actuator lock
Drive ready state
(command waiting state)
End
Figure 4.4 Power-on operation sequence
4.5 Self-calibration
The disk drive occasionally performs self-calibration in order to sense and
calibrate mechanical external forces on the actuator, and VCM torque. This
enables precise seek and read/write operations.
4.5.1 Self-calibration contents
(1) Sensing and compensating for external forces
The actuator suffers from torque due to the FPC forces and winds accompanying
disk revolution. The torque vary with the disk drive and the cylinder where the
head is positioned. To execute stable fast seek operations, external forces are
occasionally sensed.
The firmware of the drive measures and stores the force (value of the actuator
motor drive current) that balances the torque for stopping head stably. This
includes the current offset in the power amplifier circuit and DAC system.
4-8
C141-E104-02EN
4.5 Self-calibration
The forces are compensated by adding the measured value to the specified current
value to the power amplifier. This makes the stable servo control.
To compensate torque varying by the cylinder, the disk is divided into 23 areas
from the innermost to the outermost circumference and the compensating value is
measured at the measuring cylinder on each area at factory calibration. The
measured values are stored in the SA cylinder. In the self-calibration, the
compensating value is updated using the value in the SA cylinder.
(2) Compensating open loop gain
Torque constant value of the VCM has a dispersion for each drive, and varies
depending on the cylinder that the head is positioned. To realize the high speed
seek operation, the value that compensates torque constant value change and loop
gain change of the whole servo system due to temperature change is measured and
stored.
For sensing, the firmware mixes the disturbance signal to the position signal at the
state that the head is positioned to any cylinder. The firmware calculates the loop
gain from the position signal and stores the compensation value against to the
target gain as ratio.
For compensating, the direction current value to the power amplifier is multiplied
by the compensation value. By this compensation, loop gain becomes constant
value and the stable servo control is realized.
To compensate torque constant value change depending on cylinder, whole
cylinders from most inner to most outer cylinder are divided into 16 partitions at
calibration in the factory, and the compensation data is measured for
representative cylinder of each partition. This measured value is stored in the SA
area. The compensation value at self-calibration is calculated using the value in
the SA area.
4.5.2 Execution timing of self-calibration
Self-calibration is executed when:
•
•
•
The power is turned on.
The disk drive receives the RECALIBRATE command from the host.
The self-calibration execution timechart of the disk drive specifies self-
calibration.
The disk drive performs self-calibration according to the timechart based on the
time elapsed from power-on. The timechart is shown in Table 4.1. After power-
on, self-calibration is performed about every five or ten or fifteen minutes for the
first 60 minutes or six RECALIBRATE command executions, and about every 30
minutes after that.
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4-9
Theory of Device Operation
Table 4.1 Self-calibration execution timechart
Time elapsed
Time elapsed
(accumulated)
1
2
3
4
5
6
7
At power-on
Initial calibration
About 5 minutes
About 5 minutes
About 10 minutes
About 10 minutes
About 15 minutes
About 15 minutes
About 5 minutes
About 10 minutes
About 20 minutes
About 30 minutes
About 45 minutes
About 60 minutes
8
.
.
.
Every about 30
minutes
.
4.5.3 Command processing during self-calibration
If the disk drive receives a command execution request from the host while
executing self-calibration according to the timechart, the disk drive terminates
self-calibration and starts executing the command precedingly. In other words, if
a disk read or write service is necessary, the disk drive positions the head to the
track requested by the host, reads or writes data, and restarts calibration.
This enables the host to execute the command without waiting for a long time,
even when the disk drive is performing self-calibration. The command execution
wait time is about maximum 40 ms.
4.6 Read/write Circuit
The read/write circuit consists of the read/write preamplifier (HDIC), the write
circuit, the read circuit, and the time base generator in the read channel (RDC).
Figure 4.4 is a block diagram of the read/write circuit.
4.6.1 Read/write preamplifier (HDIC)
HDIC equips a read preamplifier and a write current switch, that sets the bias
current to the MR device and the current in writing. Each channel is connected to
each data head, and HDIC switches channel by serial I/O. HDIC generates a write
unsafe signal (WUS) when a write error occurs due to head short-circuits or head
disconnection, that avoids error writing.
4-10
C141-E104-02EN
4.6 Read/write Circuit
4.6.2 Write circuit
The write data is output from the hard disk controller (HDC) with the NRZ data
format, and sent to the encoder circuit in the RDC. The NRZ write data is
converted from 16-bit data to 17-bit data by the encoder circuit then sent to the
HDIC, and the data is written onto the media.
(1) 16/17 MTR MEEPRML
This device converts data using the 16/17 MTR (Maximum Transitions Run
Length Limited) algorithm.
This code is converted so that a maximum of three 1’s are placed continuously
and so that there are two or fewer 1’s in a 17-bit border.
(2) Write precompensation
Write precompensation compensates, during a write process, for write non-
linearity generated at reading. Table 4.2 shows the write precompensation
algorithm.
Table 4.2 Write precompensation algorithm
Bits
Compensation
111001
111010
:
–7
–6
111111
000000
000001
:
–1
±0
+1
010000
:
+16
+32
100000
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4-11
Theory of Device Operation
HDIC
WDX/WDY
RDX/RDY
SD
SC
SE
RDC
Serial I/O
Registers
AGC
Amplifier
Write
PreCompen-
sation
Digital
PLL
Programmable
Filter
Flash
Digitizer
ServoPulse
Detector
MEEPR
Viterbi
Detect
16/17
ENDEC
Position
A/B/C/D
(to reg)
WTGATE
REFCLK
DATA RWCLK SRV_CLK
[7:0]
RDGATE
SRV_OUT[1:0]
Figure 4.5 Read/write circuit block diagram
4-12
C141-E104-02EN
4.6 Read/write Circuit
4.6.3 Read circuit
The head read signal from the PreAMP is regulated by the automatic gain control
(AGC) circuit. Then the output is converted into the sampled read data pulse by
the programmable filter circuit and the flash digitizer circuit. This clock signal is
converted into the NRZ data by the 16/17 GCR decoder circuit based on the read
data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to
the HDC.
(1) AGC circuit
The AGC circuit automatically regulates the output amplitude to a constant value
even when the input amplitude level fluctuates. The AGC amplifier output is
maintained at a constant level even when the head output fluctuates due to the
head characteristics or outer/inner head positions.
(2) Programmable filter circuit
The programmable filter circuit has a low-pass filter function that eliminates
unnecessary high frequency noise component and a high frequency boost-up
function that equalizes the waveform of the read signal.
Cut-off frequency of the low-pass filter and boost-up gain are controlled from the
register in read channel by an instruction of the serial data signal from MPU
(M5). The MPU optimizes the cut-off frequency and boost-up gain according to
the transfer frequency of each zone.
Figure 4.6 shows the frequency characteristic sample of the programmable filter.
-3 dB
Figure 4.6 Frequency characteristic of programmable filter
C141-E104-02EN
4-13
Theory of Device Operation
(3) Flash digitizer circuit
This circuit is 10-tap sampled analog transversal filter circuit that cosine-equalizes
the head read signal to the Modified Extended Partial Response (MEEPR)
waveform.
(4) Viterbi detection circuit
The sample hold waveform output from the flash digitizer circuit is sent to the
Viterbi detection circuit. The Viterbi detection circuit demodulates data
according to the survivor path sequence.
(5) MEEPRM
This circuit converts the 17-bit read data into the 16-bit NRZ data.
4.6.4 Digital PLL circuit
The drive uses constant density recording to increase total capacity. This is
different from the conventional method of recording data with a fixed data
transfer rate at all data area. In the constant density recording method, data area is
divided into zones by radius and the data transfer rate is set so that the recording
density of the inner cylinder of each zone is nearly constant. The drive divides
data area into 15 zones to set the data transfer rate.
The MPU transfers the data transfer rate setup data (SD/SC) to the RDC that
includes the Digital PLL circuit to change the data transfer rate.
4-14
C141-E104-02EN
4.6 Read/write Circuit
4.7 Servo Control
The actuator motor and the spindle motor are submitted to servo control. The
actuator motor is controlled for moving and positioning the head to the track
containing the desired data. To turn the disk at a constant velocity, the actuator
motor is controlled according to the servo data that is written on the data side
beforehand.
4.7.1 Servo control circuit
Figure 4.7 is the block diagram of the servo control circuit. The following
describes the functions of the blocks:
(1)
MPU
SVC
(3)
(4)
Power
(2)
Servo
burst
capture
DAC
Head
DSP
unit
VCM current
Amp
CSR
(7)
Position Sense
VCM
(5)
(6)
Driver
Spindle
motor
control
Spindle
motor
CSR: Current Sense Resister
VCM: Voice Coil Motor
Figure 4.7 Block diagram of servo control circuit
(1) Microprocessor unit (MPU)
The MPU includes the DSP unit, and the MPU starts the spindle motor, moves the
heads to the reference cylinders, seeks the specified cylinder, and executes
calibration according to the internal operations of the MPU. Main internal
operation of the MPU are shown below.
C141-E104-02EN
4-15
Theory of Device Operation
The major internal operations are listed below.
a. Spindle motor start
Starts the spindle motor and accelerates it to normal speed when power is
applied.
b. Move head to reference cylinder
Drives the VCM to position the head at the any cylinder in the data area. The
logical initial cylinder is at the outermost circumference (cylinder 0).
c. Seek to specified cylinder
Drives the VCM to position the head to the specified cylinder.
d. Calibration
Senses and stores the thermal offset between heads and the mechanical forces
on the actuator, and stores the calibration value.
4-16
C141-E104-02EN
4.7 Servo Control
(2) Servo burst capture circuit
The servo burst capture circuit reproduces signals (position signals) that indicate
the head position from the servo data on the data surface. SERVO A, SERVO B,
SERVO C and SERVO D burst signals shown in Figure 4.9 followed the servo
mark, cylinder gray and index information are output from the servo area on the
data surface via the data head. The servo signals do A/D-convert by Fourier-
demodulator in the servo burst capture circuit. At that time the AGC circuit is in
hold mode. The A/D converted data is recognized by the MPU as position
information with A-B and C-D processed.
(3) D/A converter (DAC)
The D/A converter (DAC) converts the VCM drive current value (digital value)
calculated by the DSP unit into analog values and transfers them to the power
amplifier.
(4) Power amplifier
The power amplifier feeds currents, corresponding to the DAC output signal
voltage to the VCM.
(5) Spindle motor control circuit
The spindle motor control circuit controls the sensor-less spindle motor. This
circuit detects number of revolution of the motor by the interrupt generated
periodically, compares with the target revolution speed, then flows the current
into the motor coil according to the differentiation (aberration).
(6) Driver circuit
The driver circuit is a power amplitude circuit that receives signals from the
spindle motor control circuit and feeds currents to the spindle motor.
(7) VCM current sense resistor (CSR)
This resistor controls current at the power amplifier by converting the VCM
current into voltage and feeding back.
C141-E104-02EN
4-17
Theory of Device Operation
4.7.2 Data-surface servo format
Figure 4.8 describes the physical layout of the servo frame. The three areas
indicated by (1) to (3) in Figure 4.8 are described below.
(1) Inner guard band
The head is in contact with the disk in this space when the spindle starts turning
or stops, and the rotational speed of the spindle can be controlled on this cylinder
area for head moving.
(2) Data area
This area is used as the user data area SA area.
(3) Outer guard band
This area is located at outer position of the user data area, and the rotational speed
of the spindle can be controlled on this cylinder area for head moving.
4-18
C141-E104-02EN
4.7 Servo Control
Servo frame
(66 servo frames per revolution)
OGB
IGB
Data area
expand
CYLn
CYLn – 1 (n: even number)
CYLn + 1
!" Diameter
direction
W/R Recovery
Servo Mark
Gray Code
W/R Recovery
Servo Mark
Gray Code
W/R Recovery
Servo Mark
Gray Code
#
#
Erase
Servo B
Servo C
Erase
Servo A
Erase
Erase
Servo B
Servo A
Erase
Circumference
Direction
Erase
Servo D
PAD
Servo C
Erase
Erase: DC erase
area
Figure 4.8 Physical sector servo configuration on disk surface
C141-E104-02EN
4-19
Theory of Device Operation
4.7.3 Servo frame format
As the servo information, the IDD uses the two-phase servo generated from the
gray code and servo A to D. This servo information is used for positioning
operation of radius direction and position detection of circumstance direction.
The servo frame consists of 6 blocks; write/read recovery, servo mark, gray code,
servo A to D, and PAD. Figure 4.9 shows the servo frame format.
Figure 4.9 Servo frame format
4-20
C141-E104-02EN
4.7 Servo Control
(1) Write/read recovery
This area is used to absorb the write/read transient and to stabilize the AGC.
(2) Servo mark
This area generates a timing for demodulating the gray code and position-
demodulating the servo A to D by detecting the servo mark.
(3) Gray code (including index bit)
This area is used as cylinder address. The data in this area is converted into the
binary data by the gray code demodulation circuit
(4) Servo A, servo B, servo C, servo D
This area is used as position signals between tracks and the IDD control at on-
track so that servo A level equals to servo B level.
(5) PAD
This area is used as a gap between servo and data.
4.7.4 Actuator motor control
The voice coil motor (VCM) is controlled by feeding back the servo data recorded
on the data surface. The MPU fetches the position sense data on the servo frame
at a constant interval of sampling time, executes calculation, and updates the
VCM drive current.
The servo control of the actuator includes the operation to move the head to the
reference cylinder, the seek operation to move the head to the target cylinder to
read or write data, and the track-following operation to position the head onto the
target track.
(1) Operation to move the head to the reference cylinder
The MPU moves the head to the reference cylinder when the power is turned.
The reference cylinder is in the data area.
When power is applied the heads are moved from the inner circumference shunt
zone to the normal servo data zone in the following sequence:
a) Micro current is fed to the VCM to press the head against the inner
circumference.
b) Micro current is fed to the VCM to move the head toward the outer
circumference.
c) When the servo mark is detected the head is moved slowly toward the outer
circumference at a constant speed.
C141-E104-02EN
4-21
Theory of Device Operation
d) If the head is stopped at the reference cylinder from there. Track following
control starts.
(2) Seek operation
Upon a data read/write request from the host, the MPU confirms the necessity of
access to the disk. If a read/write instruction is issued, the MPU seeks the desired
track.
The MPU feeds the VCM current via the D/A converter and power amplifier to
move the head. The MPU calculates the difference (speed error) between the
specified target position and the current position for each sampling timing during
head moving. The MPU then feeds the VCM drive current by setting the
calculated result into the D/A converter. The calculation is digitally executed by
the firmware. When the head arrives at the target cylinder, the track is followed.
(3) Track following operation
Except during head movement to the reference cylinder and seek operation under
the spindle rotates in steady speed, the MPU does track following control. To
position the head at the center of a track, the DSP drives the VCM by feeding
micro current. For each sampling time, the VCM drive current is determined by
filtering the position difference between the target position and the position
clarified by the detected position sense data. The filtering includes servo
compensation. These are digitally controlled by the firmware.
4.7.5 Spindle motor control
Hall-less three-phase twelve-pole motor is used for the spindle motor, and the 3-
phase full/half-wave analog current control circuit is used as the spindle motor
driver (called SVC hereafter). The firmware operates on the MPU manufactured
by Fujitsu. The spindle motor is controlled by sending several signals from the
MPU to the SVC. There are three modes for the spindle control; start mode,
acceleration mode, and stable rotation mode.
(1) Start mode
When power is supplied, the spindle motor is started in the following sequence:
a) After the power is turned on, the MPU sends a signal to the SVC to charge
the charge pump capacitor of the SVC. The charged amount defines the
current that flows in the spindle motor.
b) When the charge pump capacitor is charged enough, the MPU sets the SVC
to the motor start mode. Then, a current (approx. 0.7 A) flows into the
spindle motor.
c) The SVC generates a phase switching signal by itself, and changes the phase
of the current flowed in the motor in the order of (V-phase to U-phase), (W-
phase to U-phase), (W-phase to V-phase), (U-phase to V-phase), (U-phase to
W-phase), and (V-phase to W-phase) (after that, repeating this order).
4-22
C141-E104-02EN
4.7 Servo Control
d) During phase switching, the spindle motor starts rotating in low speed, and
generates a counter electromotive force. The SVC detects this counter
electromotive force and reports to the MPU using a PHASE signal for speed
detection.
e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a
specific period, the MPU resets the SVC and starts from the beginning.
When a PHASE signal is sent, the SVC enters the acceleration mode.
(2) Acceleration mode
In this mode, the MPU stops to send the phase switching signal to the SVC. The
SVC starts a phase switching by itself based on the counter electromotive force.
Then, rotation of the spindle motor accelerates. The MPU calculates a rotational
speed of the spindle motor based on the PHASE signal from the SVC, and waits
till the rotational speed reaches 4,200 rpm. When the rotational speed reaches
4,200 rpm, the SVC enters the stable rotation mode.
(3) Stable rotation mode
The SVC calculates a time for one revolution of the spindle motor based on the
PHASE signal. The MPU takes a difference between the current time and a time
for one revolution at 4,200 rpm that the MPU already recognized. Then, the MPU
keeps the rotational speed to 4,200 rpm by charging or discharging the charge
pump for the different time. For example, when the actual rotational speed is
4,000 rpm, the time for one revolution is 15.000 ms. And the time for one
revolution at 4,200 rpm is 14.286 ms. Therefore, the MPU charges the charge
pump for 0.714 ms × k (k: constant value). This makes the flowed current into the
motor higher and the rotational speed up. When the actual rotational speed is
faster than 4,200 rpm, the MPU discharges the pump the other way. This control
(charging/discharging) is performed every 1 revolution.
C141-E104-02EN
4-23
This page is intentionally left blank.
CHAPTER 5 Interface
5.1
5.2
5.3
5.4
5.5
5.6
Physical Interface
Logical Interface
Host Commands
Command Protocol
Ultra DMA Feature Set
Timing
This chapter gives details about the interface, and the interface commands and
timings.
C141-E104-02EN
5-1
Interface
5.1 Physical Interface
5.1.1 Interface signals
Figure 5.1 shows the interface signals.
Host
IDD
DATA 0-15: DATA BUS
DMACK-: DMA ACKNOWLEDGE
DMARQ: DMA REQUEST
INTRO: INTERRUPT REQUEST
DIOW-: I/O WRITE
STOP: STOP DURING ULTRA DMA DATA BURSTS
DIOR-:I/O READ
HDMARDY:DMA READY DURING ULTRA DMA DATA IN BURSTS
HSTROBE:DATA STROBE DURING ULTRA DMA DATA OUT BURST
PDIAG-: PASSED DIAGNOSTICS
CBLID-: CABLE TYPE IDENTIFIER
DASP-: DEVICE ACTIVE/SLAVE PRESENT
IORDY:I/O READY
DDMARDY:DMA READY DURING ULTRA DMA DATA OUT BURSTS
DSTROBE: DATA STROBE DURING ULTRA DMA DATA IN BURSTS
DA 0-2: DEVICE ADDRESS
CS0-: CHIP SELECT 0
CS1-: CHIP SELECT 1
RESET-: RESET
CSEL: CABLE SELECT
MSTR: Master
ENCSEL: ENABLE CSEL
+5V DC: +5 volt
GND: GROUND
Figure 5.1
Interface signals
5-2
C141-E104-02EN
5.1 Physical Interface
5.1.2 Signal assignment on the connector
Table 5.1 shows the signal assignment on the interface connector.
Table 5.1 Signal assignment on the interface connector
Pin No.
Signal
Pin No.
Signal
A
C
MSTR
B
D
MSTR/ENCSEL
ENCSEL
(KEY)
unused
(KEY)
E
F
1
RESET–
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
GND
2
GND
3
4
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
(KEY)
5
6
7
8
9
10
12
14
16
18
20
22
24
26
11
13
15
17
19
21
23
25
DMARQ
GND
DIOW-, STOP
GND
DIOR-, HDMRDY,
HSTROBE
GND
27
IORDY, DDMARDY,
DSTROBE
28
CSEL
29
31
33
35
37
39
41
43
DMACK–
INTRQ
DA1
30
32
34
36
38
40
42
44
GND
reserved (IOCS16-)
PDIAG–, CBLID–
DA2
DA0
CS0–
CS1–
DASP–
+5 VDC
GND
GND
+5 VDC
unused
C141-E104-02EN
5-3
Interface
[signal]
[I/O]
I
[Description]
ENCSEL
This signal is used to set master/slave using the CSEL signal (pin 28).
Pins B and D
Open: Sets master/slave using the CSEL signal
is disabled.
Short: Sets master/slave using the CSEL signal
is enabled.
MSTR-
I
I
MSTR, I, Master/slave setting
Pin A, B, C, D open: Master setting
Pin A, B Short:
Slave setting
RESET-
DATA 0-15
DIOW-
Reset signal from the host. This signal is low active and is
asserted for a minimum of 25 µs during power on.
I/O Sixteen-bit bi-directional data bus between the host and the
device. These signals are used for data transfer
I
Signal asserted by the host to write to the device register or data
port.
STOP
I
DIOW- must be negated by the host before starting the Ultra
DMA transfer. The STOP signal must be negated by the host
before data is transferred during the Ultra DMA transfer. During
data transfer in Ultra DMA mode, the assertion of the STOP
signal asserted by the host later indicates that the transfer has been
suspended.
DIOR-
I
I
Read strobe signal from the host to read the device register or data
port
HDMARDY-
Flow control signal for Ultra DMA data In transfer (READ DMA
command). This signal is asserted by the host to inform the
device that the host is ready to receive the Ultra DMA data In
transfer. The host can negate the HDMARDY- signal to suspend
the Ultra DMA data In transfer.
HSTROBE
INTRQ
I
Data Out Strobe signal from the host during Ultra DMA data Out
transfer (WRITE DMA command). Both the rising and falling
edges of the HSTROBE signal latch data from Data 15-0 into the
device. The host can suspend the inversion of the HSTROBE
signal to suspend the Ultra DMA data Out transfer.
O
Interrupt signal to the host.
This signal is negated in the following cases:
− assertion of RESET- signal
− Reset by SRST of the Device Control register
− Write to the command register by the host
− Read of the status register by the host
− Completion of sector data transfer
(without reading the Status register)
The signal output line has a high impedance when no devices are
selected or interruption is disabled.
5-4
C141-E104-02EN
5.1 Physical Interface
[signal]
CS0-
[I/O]
I
[Description]
Chip select signal decoded from the host address bus. This signal
is used by the host to select the command block registers.
CS1-
I
I
-
Chip select signal decoded from the host address bus. This signal
is used by the host to select the control block registers.
DA 0-2
Binary decoded address signals asserted by the host to access task
file registers.
KEY
Key pin for prevention of erroneous connector insertion
PDIAG-
I/O This signal is an input mode for the master device and an output
mode for the slave device in a daisy chain configuration. This
signal indicates that the slave device has been completed self
diagnostics.
This signal is pulled up to +5 V through 10 kΩ resistor at each device.
CBLID-
DASP-
IORDY
I/O This signal is used to detect the type of cable installed in the
system.
This signal is pulled up to +5 V through 10 kΩ resistor at each device.
I/O This is a time-multiplexed signal that indicates that the device is
active and a slave device is present.
This signal is pulled up to +5 V through 10 kΩ resistor at each device.
O
O
This signal requests the host system to delay the transfer cycle
when the device is not ready to respond to a data transfer request
from the host system.
DDMARDY
-
Flow control signal for Ultra DMA data Out transfer (WRITE
DMA command). This signal is asserted by the device to inform
the host that the device is ready to receive the Ultra DMA data
Out transfer. The device can negate the DDMARDY- signal to
suspend the Ultra DMA data Out transfer.
DSTROBE
CSEL
O
I
Data In Strobe signal from the device during Ultra DMA data In
transfer. Both the rising and falling edges of the DSTROBE
signal latch data from Data 15-0 into the host. The device can
suspend the inversion of the DSTROBE signal to suspend the
Ultra DMA data In transfer.
This signal to configure the device as a master or a slave device.
− When CSEL signal is grounded, the IDD is a master device.
− When CSEL signal is open, the IDD is a slave device.
This signal is pulled up with 240 kΩ resistor at each device.
DMACK-
I
The host system asserts this signal as a response that the host
system receive data or to indicate that data is valid.
C141-E104-02EN
5-5
Interface
[signal]
[I/O]
O
[Description]
DMARQ
This signal is used for DMA transfer between the host system and
the device. The device asserts this signal when the device
completes the preparation of DMA data transfer to the host system
(at reading) or from the host system (at writing).
The direction of data transfer is controlled by the DIOR and
DIOW signals. This signal hand shakes with the DMACK-signal.
In other words, the device negates the DMARQ signal after the
host system asserts the DMACK signal. When there is other data
to be transferred, the device asserts the DMARQ signal again.
When the DMA data transfer is performed, IOCS16-, CS0- and
CS1- signals are not asserted. The DMA data transfer is a 16-bit
data transfer.
+5 VDC
GND
I
-
+5 VDC power supplying to the device.
Grounded signal at each signal wire.
Note:
“I” indicates input signal from the host to the device.
“O” indicates output signal from the device to the host.
“I/O” indicates common output or bi-directional signal between the host
and the device.
5.2 Logical Interface
The device can operate for command execution in either address-specified mode;
cylinder-head-sector (CHS) or Logical block address (LBA) mode. The
IDENTIFY DEVICE information indicates whether the device supports the LBA
mode. When the host system specifies the LBA mode by setting bit 6 in the
Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates
the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder
Low, and Sector Number registers are LBA bits.
The sector No. under the LBA mode proceeds in the ascending order with the start
point of LBA0 (defined as follows).
LBA0 = [Cylinder 0, Head 0, Sector 1]
Even if the host system changes the assignment of the CHS mode by the
INITIALIZE DEVICE PARAMETER command, the sector LBA address is not
changed.
LBA = [((Cylinder No.) × (Number of head) + (Head No.)) × (Number of
sector/track)] + (Sector No.) − 1
5-6
C141-E104-02EN
5.2 Logical Interface
5.2.1 I/O registers
Communication between the host system and the device is done through input-
output (I/O) registers of the device.
These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to
DA2 from the host system. Table 5.2. shows the coding address and the function
of I/O registers.
Table 5.2 I/O registers
I/O registers
Host I/O
address
CS0– CS1–
DA2
DA1
DA0
Read operation Write operation
Command block registers
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
L
Data
Data
X’1F0’
X’1F1’
X’1F2’
X’1F3’
X’1F4’
X’1F5’
X’1F6’
X’1F7’
—
Error Register
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Status
Features
L
H
H
L
Sector Count
Sector Number
Cylinder Low
Cylinder High
Device/Head
Command
(Invalid)
L
H
L
H
H
H
H
X
L
H
L
H
H
X
H
X
(Invalid)
Control block registers
H
H
L
L
H
H
H
H
L
Alternate Status Device Control
X’3F6’
X’3F7’
H
—
—
Notes:
1.
The Data register for read or write operation can be accessed by 16 bit data
bus (DATA0 to DATA15).
2.
The registers for read or write operation other than the Data registers can be
accessed by 8 bit data bus (DATA0 to DATA7).
3.
4.
When reading the Drive Address register, bit 7 is high-impedance state.
H indicates signal level High and L indicates signal level Low.
And the LBA mode is specified, the Device/Head, Cylinder High, Cylinder
Low, and Sector Number registers indicate LBA bits 27 to 24, 23 to 16, 15
to 8, and 7 to 0.
C141-E104-02EN
5-7
Interface
5.2.2 Command block registers
(1) Data register (X’1F0’)
The Data register is a 16-bit register for data block transfer between the device
and the host system. Data transfer mode is PIO or DMA mode.
(2) Error register (X’1F1’)
The Error register indicates the status of the command executed by the device.
The contents of this register are valid when the ERR bit of the Status register is 1.
This register contains a diagnostic code after power is turned on, a reset , or the
EXECUTIVE DEVICE DIAGNOSTIC command is executed.
[Status at the completion of command execution other than diagnostic command]
Bit 7
Bit 6
UNC
Bit 5
X
Bit 4
Bit 3
X
Bit 2
Bit 1
Bit 0
ICRC
IDNF
ABRT TK0NF AMNF
X: Unused
- Bit 7: Interface CRC Error (ICRC). This bit indicates that a CRC error
occurred during Ultra DMA transfer.
- Bit 6: Uncorrectable Data Error (UNC). This bit indicates that an
uncorrectable data error has been encountered.
- Bit 5: Unused
- Bit 4: ID Not Found (IDNF). This bit indicates an error except for bad
sector, uncorrectable error and SB not found.
- Bit 3: Unused
- Bit 2: Aborted Command (ABRT). This bit indicates that the requested
command was aborted due to a device status error (e.g. Not Ready,
Write Fault) or the command code was invalid.
- Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not
found during RECALIBRATE command execution.
- Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not
Found error occurred.
5-8
C141-E104-02EN
5.2 Logical Interface
[Diagnostic code]
X’01’: No Error Detected.
X’02’: HDC Register Compare Error
X’03’: Data Buffer Compare Error.
X’05’: ROM Sum Check Error.
X’80’: Device 1 (slave device) Failed.
Error register of the master device is valid under two devices (master
and slave) configuration. If the slave device fails, the master device
posts X’80’ OR (the diagnostic code) with its own status (X’01’ to
X’05’).
However, when the host system selects the slave device, the diagnostic
code of the slave device is posted.
(3) Features register (X’1F1’)
The Features register provides specific feature to a command. For instance, it is
used with SET FEATURES command to enable or disable caching.
(4) Sector Count register (X’1F2’)
The Sector Count register indicates the number of sectors of data to be transferred
in a read or write operation between the host system and the device. When the
value in this register is X’00’, the sector count is 256.
When this register indicates X’00’ at the completion of the command execution,
this indicates that the command is completed successfully. If the command is not
completed successfully, this register indicates the number of sectors to be
transferred to complete the request from the host system. That is, this register
indicates the number of remaining sectors that the data has not been transferred
due to the error.
The contents of this register has other definition for the following commands;
INITIALIZE DEVICE PARAMETERS, SET FEATURES, IDLE, STANDBY and
SET MULTIPLE MODE.
(5) Sector Number register (X’1F3’)
The contents of this register indicates the starting sector number for the
subsequent command. The sector number should be between X’01’ and [the
number of sectors per track defined by INITIALIZE DEVICE PARAMETERS
command.
Under the LBA mode, this register indicates LBA bits 7 to 0.
C141-E104-02EN
5-9
Interface
(6) Cylinder Low register (X’1F4’)
The contents of this register indicates low-order 8 bits of the starting cylinder
address for any disk-access.
At the end of a command, the contents of this register are updated to the current
cylinder number.
Under the LBA mode, this register indicates LBA bits 15 to 8.
(7) Cylinder High register (X’1F5’)
The contents of this register indicates high-order 8 bits of the disk-access start
cylinder address.
At the end of a command, the contents of this register are updated to the current
cylinder number. The high-order 8 bits of the cylinder address are set to the
Cylinder High register.
Under the LBA mode, this register indicates LBA bits 23 to 16.
(8) Device/Head register (X’1F6’)
The contents of this register indicate the device and the head number.
When executing INITIALIZE DEVICE PARAMETERS command, the contents
of this register defines “the number of heads minus 1” (a maximum head No.).
Bit 7
X
Bit 6
L
Bit 5
X
Bit 4
DEV
Bit 3
HS3
Bit 2
HS2
Bit 1
HS1
Bit 0
HS0
- Bit 7: Unused
- Bit 6: L. 0 for CHS mode and 1 for LBA mode.
- Bit 5: Unused
- Bit 4: DEV bit. 0 for the master device and 1 for the slave device.
- Bit 3: HS3 CHS mode head address 3 (23). LBA bit 27.
- Bit 2: HS2 CHS mode head address 2 (22). LBA bit 26.
- Bit 1: HS1 CHS mode head address 1 (21). LBA bit 25.
- Bit 0: HS0 CHS mode head address 0 (20). LBA bit 24.
5-10
C141-E104-02EN
5.2 Logical Interface
(9) Status register (X’1F7’)
The contents of this register indicate the status of the device. The contents of this
register are updated at the completion of each command. When the BSY bit is
cleared, other bits in this register should be validated within 400 ns. When the
BSY bit is 1, other bits of this register are invalid. When the host system reads
this register while an interrupt is pending, it is considered to be the Interrupt
Acknowledge (the host system acknowledges the interrupt). Any pending
interrupt is cleared (negating INTRQ signal) whenever this register is read.
Bit 7
BSY
Bit 6
Bit 5
DF
Bit 4
DSC
Bit 3
DRQ
Bit 2
0
Bit 1
0
Bit 0
ERR
DRDY
- Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is
accessed. Then this bit is cleared when the command is completed.
However, even if a command is being executed, this bit is 0 while data
transfer is being requested (DRQ bit = 1).When BSY bit is 1, the host
system should not write the command block registers. If the host
system reads any command block register when BSY bit is 1, the
contents of the Status register are posted. This bit is set by the device
under following conditions:
(a) Within 400 ns after RESET- is negated or SRST is set in the
Device Control register, the BSY bit is set. the BSY bit is cleared,
when the reset process is completed.
The BSY bit is set for no longer than 15 seconds after the IDD
accepts reset.
(b) Within 400 ns from the host system starts writing to the
Command register.
(c) Within 5 µs following transfer of 512 bytes data during execution
of the READ SECTOR(S), WRITE SECTOR(S), or WRITE
BUFFER command.
Within 5 µs following transfer of 512 bytes of data and the
appropriate number of ECC bytes during execution of READ
LONG or WRITE LONG command.
- Bit 6: Device Ready (DRDY) bit. This bit indicates that the device is
capable to respond to a command.
The IDD checks its status when it receives a command. If an error is
detected (not ready state), the IDD clears this bit to 0. This is cleared
to 0 at power-on and it is cleared until the rotational speed of the
spindle motor reaches the steady speed.
C141-E104-02EN
5-11
Interface
- Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault
(write fault) condition has been detected.
If a write fault is detected during command execution, this bit is
latched and retained until the device accepts the next command or
reset.
- Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device
heads are positioned over a track.
In the IDD, this bit is always set to 1 after the spin-up control is
completed.
- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to
transfer data of word unit or byte unit between the host system and the
device.
- Bit 2: Always 0.
- Bit 1: Always 0.
- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the
previous command was being executed. The Error register indicates
the additional information of the cause for the error.
(10) Command register (X’1F7’)
The Command register contains a command code being sent to the device. After
this register is written, the command execution starts immediately.
Table 5.3 lists the executable commands and their command codes. This table
also lists the necessary parameters for each command which are written to certain
registers before the Command register is written.
5-12
C141-E104-02EN
5.3 Host Commands
5.2.3 Control block registers
(1) Alternate Status register (X’3F6’)
The Alternate Status register contains the same information as the Status register
of the command block register.
The only difference from the Status register is that a read of this register does not
imply Interrupt Acknowledge and INTRQ signal is not reset.
Bit 7
BSY
Bit 6
Bit 5
DF
Bit 4
DSC
Bit 3
DRQ
Bit 2
0
Bit 1
0
Bit 0
ERR
DRDY
(2) Device Control register (X’3F6’)
The Device Control register contains device interrupt and software reset.
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
Bit 1
nIEN
Bit 0
0
SRST
- Bit 2: SRST is the host software reset bit. When this bit is set, the device is
held reset state. When two device are daisy chained on the interface,
setting this bit resets both device simultaneously.
The slave device is not required to execute the DASP- handshake.
- Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the
host. When this bit is 0 and the device is selected, an interruption
(INTRQ signal) can be enabled through a tri-state buffer. When this
bit is 1 or the device is not selected, the INTRQ signal is in the high-
impedance state.
5.3 Host Commands
The host system issues a command to the device by writing necessary parameters
in related registers in the command block and writing a command code in the
Command register.
The device can accept the command when the BSY bit is 0 (the device is not in
the busy status).
The host system can halt the uncompleted command execution only at execution
of hardware or software reset.
C141-E104-02EN
5-13
Interface
When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data
transfer) and the host system writes to the command register, the correct device
operation is not guaranteed.
5.3.1 Command code and parameters
Table 5.3 lists the supported commands, command code and the registers that
needed parameters are written.
Table 5.3 Command code and parameters (1 of 2)
Command code (Bit)
Parameters used
Command name
7
6
5
4
3
2
1
0
FR SC SN CY DH
READ SECTOR(S)
0
1
1
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
1
1
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
1
0
X
X
0
1
1
1
0
1
1
0
0
0
0
1
0
1
0
0
1
0
1
0
X
X
0
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
X
X
0
0
0
1
1
0
0
0
1
1
0
0
R
0
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
N
N
N*
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
Y
N
N
Y
Y
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
Y
N
N
Y
Y
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
D
Y
Y
D
D
D
D
Y
D
D*
Y
Y
D
D
D
READ MULTIPLE
READ DMA
R
R
1
READ VERIFY SECTOR(S)
WRITE MULTIPLE
WRITE DMA
R
0
WRITE VERIFY
WRITE SECTOR(S)
RECALIBRATE
R
X
X
1
SEEK
INITIALIZE DEVICE PARAMETERS
IDENTIFY DEVICE
IDENTIFY DEVICE DMA
SET FEATURES
0
0
1
SET MULTIPLE MODE
SET MAX
0
1
READ NATIVE MAX ADDRESS
EXECUTE DEVICE DIAGNOSTIC
READ LONG
0
0
R
R
0
WRITE LONG
READ BUFFER
WRITE BUFFER
0
IDLE
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
1
5-14
C141-E104-02EN
5.3 Host Commands
Table 5.3 Command code and parameters (2 of 2)
Command code (Bit)
Parameters used
Command name
7
6
5
4
3
2
1
0
FR SC SN CY DH
IDLE IMMEDIATE
1
1
0
1
0
1
1
0
0
0
1
0
0
0
1
1
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
D
D
D
D
D
STANDBY
1
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
STANDBY IMMEDIATE
SLEEP
1
1
0
1
0
1
1
0
0
0
1
0
0
0
0
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
CHECK POWER MODE
1
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
SMART
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
0
1
1
0
0
0
1
1
0
0
1
0
1
1
0
1
Y
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
D
D
D
D
D
D
D
D
SECURITY DISABLE PASSWORD
SECURITY ERASE PREPARE
SECURITY ERASE UNIT
SECURITY FREEZE LOCK
SECURITY SET PASSWORD
SECURITY UNLOCK
FLUSH CACHE
Notes:
FR: Features Register
CY: Cylinder Registers
SC: Sector Count Register
DH: Drive/Head Register
SN: Sector Number Register
R:
Retry at error
1 = Without retry
0 = With retry
Y:
Necessary to set parameters
C141-E104-02EN
5-15
Interface
Y*: Necessary to set parameters under the LBA mode.
N: Not necessary to set parameters (The parameter is ignored if it is set.)
N*: May set parameters
D: The device parameter is valid, and the head parameter is ignored.
D*: The command is addressed to the master device, but both the master device
and the slave device execute it.
X:
Do not care
5.3.2 Command descriptions
The contents of the I/O registers to be necessary for issuing a command and the
example indication of the I/O registers at command completion are shown as
following in this subsection.
Example: READ SECTOR(S)
At command issuance (I/O registers setting contents)
Bit
7
6
5
4
0
3
0
2
0
1
0
0
0
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
0
x
0
1
x
L
DV Head No. / LBA [MSB]
Start cylinder address [MSB] / LBA
Start cylinder address [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
At command completion (I/O registers contents to be read)
Bit
7
6
5
4
3
2
1
0
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV Head No. / LBA [MSB]
End cylinder address [MSB] / LBA
End cylinder address [LSB] / LBA
End sector No. / LBA [LSB]
X’00’
Error information
5-16
C141-E104-02EN
5.3 Host Commands
CM: Command register
DH: Device/Head register
FR: Features register
ST: Status register
CH: Cylinder High register ER: Error register
CL: Cylinder Low register
L: LBA (logical block address) setting bit
SN: Sector Number register DV: Device address. bit
SC: Sector Count register
Note:
x, xx: Do not care (no necessary to set)
1.
When the L bit is specified to 1, the lower 4 bits of the DH register and all
bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH
register are the MSB (most significant bit) and bits of the SN register are
the LSB (least significant bit).
2.
3.
At error occurrence, the SC register indicates the remaining sector count of data
transfer.
In the table indicating I/O registers contents in this subsection, bit indication is
omitted.
(1) READ SECTOR(S) (X’20’ or X’21’)
This command reads data of sectors specified in the Sector Count register from
the address specified in the Device/Head, Cylinder High, Cylinder Low and
Sector Number registers. Number of sectors can be specified to 256 sectors in
maximum. To specify 256 sectors reading, ‘00’ is specified. For the DRQ,
INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.
If the head is not on the track specified by the host, the device performs an
implied seek. After the head reaches to the specified track, the device reads the
target sector.
If an error occurs, retry reads are attempted to read the target sector before
reporting an error, irrespective of the R bit setting.
The DRQ bit of the Status register is always set prior to the data transfer
regardless of an error condition.
Upon the completion of the command execution, command block registers contain
the cylinder, head, and sector addresses (in the CHS mode) or logical block
address (in the LBA mode) of the last sector read.
If an unrecoverable error occurs in a sector, the read operation is terminated at the
sector where the error occurred.
C141-E104-02EN
5-17
Interface
Command block registers contain the cylinder, the head, and the sector addresses
of the sector (in the CHS mode) or the logical block address (in the LBA mode)
where the error occurred, and remaining number of sectors of which data was not
transferred.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
0
x
0
1
x
0
0
0
0
R
L
DV Start head No. /LBA
[MSB]
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
(R: Retry)
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV End head No. /LBA [MSB]
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
*1
If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(2) READ MULTIPLE (X’C4’)
This command operates similarly to the READ SECTOR(S) command. The
device does not generate an interrupt (assertion of the INTRQ signal) on each
every sector. An interrupt is generated after the transfer of a block of sectors for
which the number is specified by the SET MULTIPLE MODE command.
5-18
C141-E104-02EN
5.3 Host Commands
The implementation of the READ MULTIPLE command is identical to that of the
READ SECTOR(S) command except that the number of sectors is specified by
the SET MULTIPLE MODE command are transferred without intervening
interrupts. In the READ MULTIPLE command operation, the DRQ bit of the
Status register is set only at the start of the data block, and is not set on each
sector.
The number of sectors (block count) to be transferred without interruption is
specified by the SET MULTIPLE MODE command. The SET MULTIPLE
MODE command should be executed prior to the READ MULTIPLE command.
When the READ MULTIPLE command is issued, the Sector Count register
contains the number of sectors requested (not a number of the block count or a
number of sectors in a block).
Upon receipt of this command, the device executes this command even if the
value of the Sector Count register is less than the defined block count (the value
of the Sector Count should not be 0).
If the number of requested sectors is not divided evenly (having the same number
of sectors [block count]), as many full blocks as possible are transferred, then a
final partial block is transferred. The number of sectors in the partial block to be
transferred is n where n = remainder of (“number of sectors”/”block count”).
If the READ MULTIPLE command is issued before the SET MULTIPLE MODE
command is executed or when the READ MULTIPLE command is disabled, the
device rejects the READ MULTIPLE command with an ABORTED COMMAND
error.
If an unrecoverable error occurs, reading sector is stopped at the sector where the
error occurred. Command block registers contain the cylinder, the head, the
sector addresses (in the CHS mode) or the logical block address (in the LBA
mode) of the sector where the error occurred, and remaining number of sectors
that had not transferred after the sector where the error occurred.
An interrupt is generated when the DRQ bit is set at the beginning of each block or a
partial block.
Figure 5.2 shows an example of the execution of the READ MULTIPLE
command.
•
Block count specified by SET MULTIPLE MODE command = 4 (number of
sectors in a block)
•
READ MULTIPLE command specifies;
Number of requested sectors = 9 (Sector Count register = 9)
↓
Number of sectors in incomplete block = remainder of 9/4 =1
C141-E104-02EN
5-19
Interface
Figure 5.2 Execution example of READ MULTIPLE command
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1
x
1
0
x
0
0
1
0
0
L
DV Start head No. /LBA
[MSB]
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV End head No. /LBA [MSB]
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00(*1)
Error information
*1
If the command is terminated due to an error, the remaining number of
sectors for which data was not transferred is set in this register.
5-20
C141-E104-02EN
5.3 Host Commands
(3) READ DMA (X’C8’ or X’C9’)
This command operates similarly to the READ SECTOR(S) command except for
following events.
•
•
•
The data transfer starts at the timing of DMARQ signal assertion.
The device controls the assertion or negation timing of the DMARQ signal.
The device posts a status as the result of command execution only once at
completion of the data transfer.
When an error, such as an unrecoverable medium error, that the command
execution cannot be continued is detected, the data transfer is stopped without
transferring data of sectors after the erred sector. The device generates an
interrupt using the INTRQ signal and posts a status to the host system. The
format of the error information is the same as the READ SECTOR(S) command.
In LBA mode
The logical block address is specified using the start head No., start cylinder No.,
and first sector No. fields. At command completion, the logical block address of
the last sector and remaining number of sectors of which data was not transferred,
like in the CHS mode, are set.
The host system can select the DMA transfer mode by using the SET FEATURES
command.
•
•
Multiword DMA transfer mode 0 to 2
Ultra DMA transfer mode 0 to 4
At command issuance (I/O registers setting contents)
1F7H(CM)
1
x
1
0
x
0
1
0
0
R
1F6H(DH)
L
DV Start head No. /LBA
[MSB]
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
C141-E104-02EN
5-21
Interface
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV End head No. /LBA [MSB]
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
*1
If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(4) READ VERIFY SECTOR(S) (X’40’ or X’41’)
This command operates similarly to the READ SECTOR(S) command except that
the data is not transferred to the host system.
After all requested sectors are verified, the device clears the BSY bit of the Status
register and generates an interrupt. Upon the completion of the command
execution, the command block registers contain the cylinder, head, and sector
number of the last sector verified.
If an unrecoverable error occurs, the verify operation is terminated at the sector
where the error occurred. The command block registers contain the cylinder, the
head, and the sector addresses (in the CHS mode) or the logical block address (in
the LBA mode) of the sector where the error occurred. The Sector Count register
indicates the number of sectors that have not been verified.
5-22
C141-E104-02EN
5.3 Host Commands
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
0
x
1
0
x
0
0
0
0
R
L
DV Start head No. /LBA
[MSB]
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV End head No. /LBA [MSB]
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
*1
If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(5) WRITE SECTOR(S) (X’30’ or X’31’)
This command writes data of sectors from the address specified in the
Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the
address specified in the Sector Count register. Number of sectors can be specified
to 256 sectors in maximum. Data transfer begins at the sector specified in the
Sector Number register. For the DRQ, INTRQ, and BSY protocols related to data
transfer, see Subsection 5.4.2.
If the head is not on the track specified by the host, the device performs an
implied seek. After the head reaches to the specified track, the device writes the
target sector.
If an error occurs when writing to the target sector, retries are attempted
irrespectively of the R bit setting.
The data stored in the buffer, and CRC code and ECC bytes are written to the data
field of the corresponding sector(s). Upon the completion of the command
execution, the command block registers contain the cylinder, head, and sector
addresses of the last sector written.
C141-E104-02EN
5-23
Interface
If an error occurs during multiple sector write operation, the write operation is
terminated at the sector where the error occurred. Command block registers
contain the cylinder, the head, the sector addresses (in the CHS mode) or the
logical block address (in the LBA mode) of the sector where the error occurred.
Then the host can read the command block registers to determine what error has
occurred and on which sector the error has occurred.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
0
x
0
1
x
1
0
0
0
R
L
DV Start head No. /LBA
[MSB]
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
Status information
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
x
L
x
DV End head No. /LBA [MSB]
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
*1
If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
5-24
C141-E104-02EN
5.3 Host Commands
(6) WRITE MULTIPLE (X’C5’)
This command is similar to the WRITE SECTOR(S) command. The device does
not generate interrupts (assertion of the INTRQ) signal) on each sector but on the
transfer of a block which contains the number of sectors for which the number is
defined by the SET MULTIPLE MODE command.
The implementation of the WRITE MULTIPLE command is identical to that of
the WRITE SECTOR(S) command except that the number of sectors is specified
by the SET MULTIPLE MODE command are transferred without intervening
interrupts. In the WRITE MULTIPLE command operation, the DRQ bit of the
Status register is required to set only at the start of the data block, not on each
sector.
The number of sectors (block count) to be transferred without interruption is
specified by the SET MULTIPLE MODE command. The SET MULTIPLE
MODE command should be executed prior to the WRITE MULTIPLE command.
When the WRITE MULTIPLE command is issued, the Sector Count register contains
the number of sectors requested (not a number of the block count or a number of
sectors in a block).
Upon receipt of this command, the device executes this command even if the
value of the Sector Count register is less than the defined block count the value of
the Sector Count should not be 0).
If the number of requested sectors is not divided evenly (having the same number
of sectors [block count]), as many full blocks as possible are transferred, then a
final partial block is transferred. The number of sectors in the partial block to be
transferred is n where n = remainder of (“number of sectors”/”block count”).
If the WRITE MULTIPLE command is issued before the SET MULTIPLE
MODE command is executed or when WRITE MULTIPLE command is disabled,
the device rejects the WRITE MULTIPLE command with an ABORTED
COMMAND error.
Disk errors encountered during execution of the WRITE MULTIPLE command are
posted after attempting to write the block or the partial block that was transferred.
Write operation ends at the sector where the error was encountered even if the sector is
in the middle of a block. If an error occurs, the subsequent block shall not be
transferred. Interrupts are generated when the DRQ bit of the Status register is set at
the beginning of each block or partial block.
The contents of the command block registers related to addresses after the transfer
of a data block containing an erred sector are undefined. To obtain a valid error
information, the host should retry data transfer as an individual request.
C141-E104-02EN
5-25
Interface
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1
x
1
0
x
0
0
1
0
1
L
DV Start head No. /LBA
[MSB]
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV End head No. /LBA [MSB]
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00
Error information
(7) WRITE DMA (X’CA’ or X’CB’)
This command operates similarly to the WRITE SECTOR(S) command except for
following events.
•
•
•
The data transfer starts at the timing of DMARQ signal assertion.
The device controls the assertion or negation timing of the DMARQ signal.
The device posts a status as the result of command execution only once at
completion of the data transfer or completion of processing in the device.
•
The device posts a status as the result of command execution only once at
completion of the data transfer.
When an error, such as an unrecoverable medium error, that the command
execution cannot be continued is detected, the data transfer is stopped without
transferring data of sectors after the erred sector. The device generates an
interrupt using the INTRQ signal and posts a status to the host system. The
format of the error information is the same as the WRITE SECTOR(S) command.
5-26
C141-E104-02EN
5.3 Host Commands
A host system can select the following transfer mode using the SET FEATURES
command.
•
•
Multiword DMA transfer mode 0 to 2
Ultra DMA transfer mode 0 to 4
At command issuance (I/O registers setting contents)
1F7H(CM)
1
x
1
0
x
0
1
0
1
R
1F6H(DH)
L
DV Start head No. /LBA
[MSB]
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV End head No. /LBA [MSB]
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
*1
If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(8) WRITE VERIFY (X’3C’)
This command operates similarly to the WRITE SECTOR(S) command except
that the device verifies each sector immediately after being written. The verify
operation is a read and check for data errors without data transfer. Any error that
is detected during the verify operation is posted.
After all sectors are verified, the last interruption (INTRQ for command
termination) is generated.
C141-E104-02EN
5-27
Interface
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
0
x
0
1
x
1
1
1
0
0
L
DV Start head No. /LBA
[MSB]
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV End head No. /LBA [MSB]
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
*1
If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(9) RECALIBRATE (X’1x’, x: X’0’ to X’F’)
This command performs the calibration. Upon receipt of this command, the
device sets BSY bit of the Status register and performs a calibration. When the
device completes the calibration, the device updates the Status register, clears the
BSY bit, and generates an interrupt.
This command can be issued in the LBA mode.
5-28
C141-E104-02EN
5.3 Host Commands
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
0
x
0
x
0
x
1
x
x
x
x
DV xx
xx
xx
xx
xx
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
Note:
Also executable in LBA mode.
(10) SEEK (X’7x’, x : X’0’ to X’F’)
This command performs a seek operation to the track and selects the head
specified in the command block registers. After completing the seek operation,
the device clears the BSY bit in the Status register and generates an interrupt.
The IDD always sets the DSC bit (Drive Seek Complete status) of the Status
register to 1.
In the LBA mode, this command performs the seek operation to the cylinder and
head position in which the sector is specified with the logical block address.
C141-E104-02EN
5-29
Interface
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
0
x
1
1
x
1
x
x
x
x
L
DV Head No. /LBA [MSB]
Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
xx
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV Head No. /LBA [MSB]
Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
xx
Error information
(11) INITIALIZE DEVICE PARAMETERS (X’91’)
The host system can set the number of sectors per track and the maximum head
number (maximum head number is “number of heads minus 1”) per cylinder with
this command. Upon receipt of this command, the device sets the BSY bit of
Status register and saves the parameters. Then the device clears the BSY bit and
generates an interrupt.
When the SC register is specified to X’00’, an ABORTED COMMAND error is
posted. Other than X’00’ is specified, this command terminates normally.
The parameters set by this command are retained even after reset or power save
operation regardless of the setting of disabling the reverting to default setting.
In LBA mode
The device ignores the L bit specification and operates with the CHS mode
specification. An accessible area of this command within head moving in the LBA
mode is always within a default area. It is recommended that the host system refers the
addressable user sectors (total number of sectors) in word 60 to 61 of the parameter
information by the IDENTIFY DEVICE command.
5-30
C141-E104-02EN
5.3 Host Commands
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
0
x
0
x
1
0
0
0
1
DV Max. head No.
xx
xx
xx
Number of sectors/track
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
x
x
DV Max. head No.
Number of sectors/track
Error information
(12) IDENTIFY DEVICE (X’EC’)
The host system issues the IDENTIFY DEVICE command to read parameter
information (512 bytes) from the device. Upon receipt of this command, the drive
sets the BSY bit of Status register and sets required parameter information in the
sector buffer. The device then sets the DRQ bit of the Status register, and
generates an interrupt. After that, the host system reads the information out of the
sector buffer. Table 5.4 shows the arrangements and values of the parameter
words and the meaning in the buffer.
C141-E104-02EN
5-31
Interface
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
x
1
x
0
1
1
0
0
DV xx
xx
xx
xx
xx
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 8)
Word
0
Value
X’045A’
*2
Description
General Configuration *1
1
Number of cylinders *2
Detailed Configuration
Number of Heads *2
Undefined
2
X’C837’
*2
3
4-5
6
X’0000’
*2
Number of sectors per track *2
Undefined
7-9
10-19
20
21
22
X’0000’
Set by a device
X’0000’
X’0400’
X’0004’
Serial number (ASCII code, 20 characters, right)
Undefined
Buffer Size (1 LSB: 512 Byte)
Number of ECC bytes transferred at READ LONG or
WRITE LONG command
5-32
C141-E104-02EN
5.3 Host Commands
Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 8)
Word
23-26
27-46
47
Value
–
Description
Firmware revision (ASCII code, 8 characters, left)
Model name (ASCII code, 40 characters, left)
Set by a device
X’8010’
Maximum number of sectors per interrupt on
READ/WRITE MULTIPLE command
48
49
X’0000’
X’0B00’
X’0000’
X’0200’
X’0000’
X’0007’
(Variable)
(Variable)
(Variable)
(Variable)
*6
Reserved
Capabilities *3
50
Reserved
51
PIO data transfer mode *4
Reserved
52
53
Enable/disable setting of words 54-58 and 64-70, 88 *5
Number of current Cylinders
Number of current Head
Number of current sectors per track
Total number of current sectors
54
55
56
57-58
59
Transfer sector count currently set by READ/WRITE
MULTIPLE command *6
60-61
*2
Total number of user addressable sectors (LBA mode only)
*2
62
63
64
65
X’0000’
X’xx07’
X’0003’
X’0078’
Reserved
Multiword DMA transfer mode *7
Advance PIO transfer mode support status *8
Minimum multiword DMA transfer cycle time per word :
120 [ns]
66
67
68
X’0078’
X’00F0’
X’0078’
Manufacturer’s recommended DMA transfer cycle time :
120 [ns]
Minimum PIO transfer cycle time without IORDY flow
control : 240 [ns]
Minimum PIO transfer cycle time with IORDY flow control
: 120 [ns]
69-79
80
X’0000’
X’003C’
X’0000’
X’346B’
X’4008’
X’4000’
Reserved
Major version number *9
Minor version number (not reported)
Support of command sets *10
Support of command sets *11
Support of command sets/function
81
82
83
84
C141-E104-02EN
5-33
Interface
Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 8)
Word
85
Value
*12
Description
Valid of command sets/function *12
Valid of command sets/function *13
Default of command sets/function
Ultra DMA transfer mode *14
Security Erase Unit execution time (Unit: 2 min.)
Enhanced Security Erase Unit execution time (Unit: 2 min.)
Advance power management level
Master password revision
86
*13
87
X’4000’
X’xx1F’
Set by a device
X’0000’
(Variable)
(Variable)
*15
88
89
90
91
92
93
Hardware configuration
94-127
128
129-159
160-254
255
X’0000’
(Variable)
X’0000’
X’0000’
X’xxA5’
Reserved
Security status *16
Undefined
Reserved
Check sum (The 2 complement of the lower order byte
resulting from summing bits 7 to 0 of word 0 to 254 and
word 255, in byte units.)
*1 Word 0: General configuration
Bit 15:
ATA device = 0, ATAPI device = 1
Bit 14-8: Undefined
Bit 7:
Removable disk drive = 1
Bit 6:
Fixed drive = 1
Bit 5-3:
Bit 2:
Undefined
IDENTIFY DEVICE Valid = 0
Reserved
Bit 1-0:
*2 Word 1, 3, 6, 60-61
MHL2300AT
MHM2200AT
X’3FFF’
X’10’
MHM2150AT
X’3FFF’
X’10’
MHM2100AT
X’3FFF’
X’10’
Word 01
Word 03
Word 06
Word 60-61
X’3FFF’
X’10’
X’3F’
X’3F’
X’3F’
X’3F’
X’37E3E40’
X’2542980’
X’1C21B00’
X’12BB230’
*3 Word 49: Capabilities
Bit 15-14: Reserved
5-34
C141-E104-02EN
5.3 Host Commands
Table 5.4 Information to be read by IDENTIFY DEVICE command (4 of 8)
Bit 13:
Bit 12:
Bit 11:
Standby timer value. Factory default is 0.
Reserved
IORDY support
1=Supported
Bit 10:
IORDY inhibition
Undefined
0=Disable inhibition
Bit 9-0:
Bit 9, 8: Always 1
*4 Word 51: PIO data transfer mode
Bit 15-8: PIO data transfer mode
X’02’=PIO mode 2
Bit 7-0:
Undefined
*5 Word 53: Enable/disable setting of word 54-58 and 64-70
Bit 15-3: Reserved
Bit 2:
Bit 1:
Bit 0:
Enable/disable setting of word 88
Enable/disable setting of word 64-70
Enable/disable setting of word 54-58
1=Enable
1=Enable
1=Enable
*6 Word 59: Transfer sector count currently set by READ/WRITE
MULTIPLE
command
Bit 15-9: Reserved
Bit 8:
Multiple sector transfer 1=Enable
Bit 7-0:
Transfer sector count currently set by READ/WRITE
MULTIPLE command without interrupt supports 2, 4, 8 and 16
sectors.
*7 Word 63: Multiword DMA transfer mode
Bit 15-8: Currently used multiword DMA transfer mode
Bit 7-0:
Supportable multiword DMA transfer mode
Bit 2=1 Mode 2
Bit 1=1 Mode 1
Bit 0=1 Mode 0
*8 Word 64: Advance PIO transfer mode support status
Bit 15-8: Reserved
Bit 7-0:
Advance PIO transfer mode
C141-E104-02EN
5-35
Interface
Table 5.4 Information to be read by IDENTIFY DEVICE command (5 of 8)
Bit 1 = 1 Mode 4
Bit 0 = 1 Mode 3
*9 WORD 80
Bit 15-6: Reserved
Bit 5:
Bit 4:
ATA/ATAPI-5 supported = 1
ATA/ATAPI-4 supported = 1
ATA-3 supported = 1
ATA-2 supported = 1
Undefined
Bit 3:
Bit 2:
Bit 1-0:
*10 WORD 82
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bit 11:
Bit 10:
Bit 9:
Undefined
'1' = Supports the NOP command.
'1' = Supports the READ BUFFER command.
'1' = Supports the WRITE BUFFER command.
Undefined
'1' = Supports the Host Protected Area feature set.
'1' = Supports the DEVICE RESET command.
'1' = Supports the SERVICE interrupt.
'1' = Supports the release interrupt.
Bit 8:
Bit 7:
Bit 6:
'1' = Supports the read cache function.
'1' = Supports the write cache function.
'1' = Supports the PACKET command feature set.
'1' = Supports the power management feature set.
'1' = Supports the Removable Media feature set.
'1' = Supports the Security Mode feature set.
'1' = Supports the SMART feature set.
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
*11 WORD 83
Bits 15-7: Undefined
Bit 6:
'1' = When the power is turned on, spin is started by the SET
FEATURES sub-command.
5-36
C141-E104-02EN
5.3 Host Commands
Table 5.4 Information to be read by IDENTIFY DEVICE command (6 of 8)
Bit 5:
Bit 4:
'1' = Supports the Power-Up In Standby set.
'1' = Supports the Removable Media Status Notification feature
set.
Bit 3:
Bit 2:
'1' = Supports the Advanced Power Management feature set.
'1' = Supports the CFA (Compact Flash Association) feature set.
'1' = Supports the READ/WRITE DMA QUEUED command.
'1' = Supports the DOWNLOAD MICROCODE command.
Bit 1:
Bit 0:
*12 WORD 85
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bit 11:
Bit 10:
Bit 9:
Undefined.
'1' = Enables the NOP command.
'1' = Enables the READ BUFFER command.
'1' = Enables the WRITE BUFFER command.
Undefined.
'1' = Enables the Host Protected Area function.
'1' = Enables the DEVICE RESET command.
'1' = Enables the SERVICE interrupt.
'1' = Enables the release interrupt.
Bit 8:
Bit 7:
Bit 6:
'1' = Enables the read cache function.
'1' = Enables the write cache function.
'1' = Enables the P PACKET command set.
'1' = Enables the Power Management function.
'1' = Enables the Removable Media function.
'1' = Enables the Security Mode function.
'1' = Enables the SMART function.
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
*13 WORD 86
Bits 15-7: '1' = Reserved
Bit 6:
Bit 5
Same definition as WORD 83.
Enables the Power-Up In Standby function.
Bit 4:
Bit 3:
'1' = Enables the Removable Media Status Notification function.
'1' = Enables the Advanced Power Management function.
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5-37
Interface
Table 5.4 Information to be read by IDENTIFY DEVICE command (7 of 8)
Bits 2-0: Same definition as WORD 83.
*14 WORD 88
Bit 15-8: Currently used Ultra DMA transfer mode
Bit 7-0:
Supportable Ultra DMA transfer mode
Bit 4 = '1': Mode 4
Bit 3 = '1': Mode 3
Bit 2 = '1': Mode 2
Bit 1 = '1': Mode 1
Bit 0 = '1': Mode 0
*15 WORD 93
Bits 15-14: Reserved
Bit 13:
'1' = CBLID- is a level higher than VIH.
'0' = CBLID- is a level lower than VIL.
Bits 12-8: In the case of Device 1 (slave drive), a valid value is set.
Bit 12:
Bit 11:
Reserved
'1' = Device asserts PDIAG-.
Bit 10, 9: Method for deciding the device No. of Device 1.
'00' = Reserved
'01' = Using a jumper.
'10' = Using the CSEL signal.
'11' = Other method.
Bit 8:
Reserved
Bits 7-0: In the case of Device 0 (master drive), a valid value is set.
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Reserved
'1' = Device 1 is selected, Device 0 responds.
'1' = Device 0, assertion of DASP- was detected.
'1' = Device 0, assertion of PDIAG- was detected.
'1' = Device 0, an error was not detected in the self-
diagnosis.
Bit 2, 1: Method for deciding the device No. of Device 0.
5-38
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5.3 Host Commands
Table 5.4 Information to be read by IDENTIFY DEVICE command (8 of 8)
'00' = Reserved
'01' = Using a jumper.
'10' = Using the CSEL signal.
'11' = Other method.
Reserved
Bit 0:
*16 WORD 128
Bit 15-9: Reserved
Bit 8:
Bit 7-6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Security level. 0: High, 1: Maximum
Reserved
1: Enhanced security erase supported
1: Security counter expired
1: Security frozen
1: Security locked
1: Security enabled
1: Security supported
(13) IDENTIFY DEVICE DMA (X’EE’)
When this command is not used to transfer data to the host in DMA mode, this
command functions in the same way as the Identify Device command.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
x
1
x
0
1
1
1
0
DV xx
xx
xx
xx
xx
xx
C141-E104-02EN
5-39
Interface
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
(14) SET FEATURES (X’EF’)
The host system issues the SET FEATURES command to set parameters in the
Features register for the purpose of changing the device features to be executed.
For the transfer mode (Feature register = 03), detail setting can be done using the
Sector Count register.
Upon receipt of this command, the device sets the BSY bit of the Status register
and saves the parameters in the Features register. Then, the device clears the BSY
bit, and generates an interrupt.
If the value in the Features register is not supported or it is invalid, the device
posts an ABORTED COMMAND error.
Table 5.5 lists the available values and operational modes that may be set in the
Features register.
5-40
C141-E104-02EN
5.3 Host Commands
Table 5.5 Features register values and settable modes
Drive operation mode
Features
Register
X’02’
X’03’
Enables the write cache function.
Transfer mode depends on the contents of the Sector Count register.
(Details are given later.)
X’05’
X’55’
X’66’
X’82’
X’85’
X’AA’
X’BB’
Enables the advanced power management function.
Disables read cache function.
Disables the reverting to power-on default settings after software reset.
Disables the write cache function.
Disables the advanced power management function.
Enables the read cache function.
Specifies the transfer of 4-byte ECC for READ LONG and WRITE
LONG commands.
X’CC’
Enables the reverting to power-on default settings after software reset.
At power-on or after hardware reset, the default mode is the same as that is set
with a value greater than X’85’ (except for write cache). If X’66’ is specified, it
allows the setting value greater than X’AA’ which may have been modified to a
new value since power-on, to remain the same even after software reset.
C141-E104-02EN
5-41
Interface
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
x
1
x
0
1
1
1
1
DV xx
xx
xx
xx
xx or transfer mode
[See Table 5.5]
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
The host sets X’03’ to the Features register. By issuing this command with
setting a value to the Sector Count register, the transfer mode can be selected.
Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits
specifies the binary mode value.
The IDD supports following values in the Sector Count register value. If other
value than below is specified, an ABORTED COMMAND error is posted.
PIO default transfer mode
00000 000 (X’00’)
PIO flow control transfer mode X
00001 000 (X’08’: Mode 0)
00001 001 (X’09’: Mode 1)
00001 010 (X’0A’: Mode 2)
00001 011 (X’0B’: Mode 3)
00001 100 (X’0C’: Mode 4)
5-42
C141-E104-02EN
5.3 Host Commands
Multiword DMA transfer mode X
Ultra DMA transfer mode X
00100 000 (X’20’: Mode 0)
00100 001 (X’21’: Mode 1)
00100 010 (X’22’: Mode 2)
01000 000 (X’40’: Mode 0)
01000 001 (X’41’: Mode 1)
01000 010 (X’42’: Mode 2)
01000 011 (X’43’: Mode 3)
01000 100 (X’44’: Mode 4)
The host writes the Sector Count register with the desired power management
level and executes this command with the Features register X’05’, and then
Advanced Power Management is enabled.
Level
Sector Count register
Power management without standby
Power management with standby
Reserved
80h-FEh
01h-7Fh
FFh, 00h
(15) SET MULTIPLE MODE (X’C6’)
This command enables the device to perform the READ MULTIPLE and
WRITE MULTIPLE commands. The block count (number of sectors in a
block) for these commands are also specified by the SET MULTIPLE MODE
command.
The number of sectors per block is written into the Sector Count register. The
IDD supports 2, 4, 8, 16 and 32 (sectors) as the block counts.
Upon receipt of this command, the device sets the BSY bit of the Status register
and checks the contents of the Sector Count register. If the contents of the Sector
Count register is valid and is a supported block count, the value is stored for all
subsequent READ MULTIPLE and WRITE MULTIPLE commands. Execution
of these commands is then enabled. If the value of the Sector Count register is not
a supported block count, an ABORTED COMMAND error is posted and the
READ MULTIPLE and WRITE MULTIPLE commands are disabled.
If the contents of the Sector Count register is 0, 1 when the SET MULTIPLE
MODE command is issued, the READ MULTIPLE and WRITE MULTIPLE
commands are disabled.
When the SET MULTIPLE MODE command operation is completed, the device
clears the BSY bit and generates an interrupt.
C141-E104-02EN
5-43
Interface
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
x
0
x
0
0
1
1
0
DV xx
xx
xx
xx
Sector count/block
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
x
x
DV xx
Sector count/block
Error information
After power-on or after hardware reset, the READ MULTIPLE and WRITE
MULTIPLE command operation are disabled as the default mode.
The mode established before software reset is retained if disable default (Features
Reg. = 66h setting) has been defined by the SET FEATURES command. If
disable default has not been defined after the software is the READ MULTIPLE
and WRITE MULTIPLE commands are disabled.
The parameters for the multiple commands which are posted to the host system
when the IDENTIFY DEVICE command is issued are listed below. See
Subsection 5.32 for the IDENTIFY DEVICE command.
5-44
C141-E104-02EN
5.3 Host Commands
Word 47
Bit 7-0 = 10:
Maximum number of sectors that can be transferred per interrupt
by the READ MULTIPLE and WRITE MULTIPLE commands.
The READ MULTIPLE and WRITE MULTIPLE commands are
Word 59 = 0000: disabled.
The READ MULTIPLE and WRITE MULTIPLE commands are
= 01xx: enabled. “xx” indicates the current setting for number of sectors
that can be transferred per interrupt by the READ MULTIPLE and
WRITE MULTIPLE commands.
e.g. 0110 = Block count of 16 has been set by the SET
MULTIPLE MODE command.
(16) SET MAX (F9)
Each SET MAX command is determined by the Features Register value.
SET MAX Features Register Values
Value
Command
00h
01h
02h
03h
04h
Obsolete
SET MAX SET PASSWORD
SET MAX LOCK
SET MAX UNLOCK
SET MAX FREEZE LOCK
Reserved
05h - FFh
•
SET MAX ADDRESS
This command allows the maximum address accessible by the user to be set in
LBA or CHS mode. Upon receipt of the command, the device sets the BSY bit
and saves the maximum address specified in the DH, CH, CL and SN registers.
Then, it clears BSY and generates an interrupt.
The new address information set by this command is reflected in Words 1, 54, 57,
58, 60 and 61 of IDENTIFY DEVICE information. If an attempt is made to
perform a read or write operation for an address beyond the new address space, an
ID Not Found error will result.
When SC register bit 0, VV (Value Volatile), is 1, the value set by this command
is held even after power on and the occurrence of a hard reset. When the VV bit is
0, the value set by this command becomes invalid when the power is turned on or
a hard reset occurs, and the maximum address returns to the value (default value if
not set) most lately set when VV bit = 1.
C141-E104-02EN
5-45
Interface
After power on and the occurrence of a hard reset, the host can issue this
command only once when VV bit = 1. If this command with VV bit = 1 is issued
twice or more, any command following the first time will result in an Aborted
Command error.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
1
x
1
1
0
0
1
L
DV Max head/LBA [MSB]
Max. cylinder [MSB]/Max. LBA
Max. cylinder [LSB]/Max. LBA
Max. sector/Max. LBA [LSB]
xx
xx
VV
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
x
x
DV Max head/LBA [MSB]
Max. cylinder [MSB]/Max. LBA
Max. cylinder [LSB]/Max. LBA
Max. sector/Max. LBA [LSB]
xx
Error information
•
SET MAX SET PASSWORD (FR=01h)
This command requests a transfer of 1 sector of data from the host, and defines
the contents of SET MAX password.
The READ NATIVE MAX ADDRESS command is not executed just before this
command. The command is the SET MAX ADDRESS command if it is the
command just after the READ NATIVE MAX ADDRESS command is executed.
If the device is in the Set Max Locked or Set Max Freeze Locked state:
51h, 04h: ABORTED command
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C141-E104-02EN
5.3 Host Commands
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
1
x
1
1
0
0
1
L
DV xx
xx
xx
xx
xx
01
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
xx
xx
xx
xx
xx
Error information
Password information
Words
Contents
0
Reserved
1 to 16
Password (32 bytes)
Reserved
17 to 255
•
SET MAX LOCK (FR=02h)
After this command is completed, any other SET MAX commands except SET
MAX UNLOCK and SET MAX FREEZE LOCK commands are rejected. And
the device returns command aborted.
The device remains in the SET MAX LOCK state until a power cycle or the
acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command.
The READ NATIVE MAX ADDRESS command is not executed just before this
command. The command is the SET MAX ADDRESS command if it is the
command just after the READ NATIVE MAX ADDRESS command is executed.
C141-E104-02EN
5-47
Interface
If the device is in the Set Max Locked or Set Max Freeze Locked state:
51h, 04h: ABORTED command
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
1
x
1
1
0
0
1
L
DV xx
xx
xx
xx
xx
02
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
xx
xx
xx
xx
xx
Error information
•
SET MAX UNLOCK (FR=03h)
This command requests a transfer of single sector of data from the host, and
defines the contents of SET MAX ADDRESS password. The data transferred
controls the function of this command.
The password supplied in the sector of data transferred shall be compared with the
stored password.
If the password compare fails, the device returns command aborted and
decrements the Unlock counter, and remains in the Set Max Lock state. On the
acceptance of the SET MAX LOCK command, the Unlock counter is set to a
value of five. When this counter reaches zero, then SET MAX UNLOCK
command shall return command aborted until a power cycle.
If the password compare matches, then the device shall make a transition to the
Set Max Unlocked state and all SET MAX commands will be accepted.
5-48
C141-E104-02EN
5.3 Host Commands
If this command is accepted in the Set Max Unlocked state, the device terminates
normally.
The READ NATIVE MAX ADDRESS command is not executed just before this
command. The command is the SET MAX ADDRESS command if it is the
command just after the READ NATIVE MAX ADDRESS command is executed.
If the device is in the Set Max Locked or Set Max Freeze Locked state:
51h, 04h: ABORTED command
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
1
x
1
1
0
0
1
L
DV xx
xx
xx
xx
xx
03
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
xx
xx
xx
xx
xx
Error information
•
SET MAX FREEZE LOCK (FR=04h)
After the device made a transition to the Set Max Freeze Lock state, the following
commands are rejected, then the device returns command aborted:
−
−
−
−
SET MAX ADDRESS
SET MAX SET PASSWORD
SET MAX LOCK
SET MAX UNLOCK
C141-E104-02EN
5-49
Interface
The READ NATIVE MAX ADDRESS command is not executed just before this
command. The command is the SET MAX ADDRESS command if it is the
command just after the READ NATIVE MAX ADDRESS command is executed.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
x
1
x
1
1
0
0
1
DV xx
xx
xx
xx
xx
04
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
xx
xx
xx
xx
xx
Error information
(17) READ NATIVE MAX ADDRESS (F8)
This command posts the maximum address intrinsic to the device, which can be
set by the SET MAX ADDRESS command. Upon receipt of this command, the
device sets the BSY bit and indicates the maximum address in the DH, CH, CL
and SN registers. Then, it clears BSY and generates an interrupt.
5-50
C141-E104-02EN
5.3 Host Commands
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
1
x
1
1
0
0
0
L
DV xx
xx
xx
xx
xx
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
x
x
DV Max head/LBA [MSB]
Max. cylinder [MSB]/Max. LBA
Max. cylinder [LSB]/Max. LBA
Max. sector/Max. LBA [LSB]
xx
Error information
(18) EXECUTE DEVICE DIAGNOSTIC (X’90’)
This command performs an internal diagnostic test (self-diagnosis) of the device.
This command usually sets the DRV bit of the Drive/Head register is to 0
(however, the DV bit is not checked). If two devices are present, both devices
execute self-diagnosis.
If device 1 is present:
•
•
Both devices shall execute self-diagnosis.
The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG-
signal.
•
•
•
If the device 1 does not assert the PDIAG- signal but indicates an error, the
device 0 shall append X’80’ to its own diagnostic status.
The device 0 clears the BSY bit of the Status register and generates an
interrupt. (The device 1 does not generate an interrupt.)
A diagnostic status of the device 0 is read by the host system. When a
diagnostic failure of the device 1 is detected, the host system can read a status
of the device 1 by setting the DV bit (selecting the device 1).
C141-E104-02EN
5-51
Interface
When device 1 is not present:
•
•
The device 0 posts only the results of its own self-diagnosis.
The device 0 clears the BSY bit of the Status register, and generates an
interrupt.
Table 5.6 lists the diagnostic code written in the Error register which is 8-bit code.
If the device 1 fails the self-diagnosis, the device 0 “ORs” X’80’ with its own
status and sets that code to the Error register.
Table 5.6 Diagnostic code
Code
Result of diagnostic
No error detected.
X’01’
X’03’
X’05’
X’8x’
Data buffer compare error
ROM sum check error
Failure of device 1
attention: The device responds normally to this command without executing
internal diagnostic test.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
0
x
0
x
1
0
0
0
0
DV
Head No. /LBA [MSB]
xx
xx
xx
xx
xx
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C141-E104-02EN
5.3 Host Commands
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
x
x
DV
Head No. /LBA [MSB]
01H (*1)
01H
Diagnostic code
*1
This register indicates X’00’ in the LBA mode.
(19) READ LONG (X’22’ or X’23’)
This command operates similarly to the READ SECTOR(S) command except that
the device transfers the data in the requested sector and the ECC bytes to the host
system. The ECC error correction is not performed for this command. This
command is used for checking ECC function by combining with the WRITE
LONG command.
Number of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed
by the SET FEATURES command.
The READ LONG command supports only single sector operation.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
0
x
0
1
x
0
0
0
1
R
L
DV Head No. /LBA [MSB]
Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
01
xx
(R: Retry)
C141-E104-02EN
5-53
Interface
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV Head No. /LBA [MSB]
Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
00 (*1)
Error information
*1
If the command is terminated due to an error, this register indicates 01.
(20) WRITE LONG (X’32’ or X’33’)
This command operates similarly to the READ SECTOR(S) command except that
the device writes the data and the ECC bytes transferred from the host system to
the disk medium. The device does not generate ECC bytes by itself. The WRITE
LONG command supports only single sector operation.
The number of ECC bytes to be transferred is fixed to 4 bytes and can not be
changed by the SET FEATURES command.
This command is operated under the following conditions:
•
READ LONG issued → WRITE LONG (Same address) issues sequence
(After READ LONG is issued, WRITE LONG can be issued consecutively.)
If above condition is not satisfied, the command operation is not guaranteed.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
0
x
0
1
x
1
0
0
1
R
L
DV Head No. /LBA [MSB]
Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
01
xx
5-54
C141-E104-02EN
5.3 Host Commands
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
L
x
DV Head No. /LBA [MSB]
Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
00 (*1)
Error information
*1
If the command is terminated due to an error, this register indicates 01.
(21) READ BUFFER (X’E4’)
The host system can read the current contents of the sector buffer of the device by
issuing this command. Upon receipt of this command, the device sets the BSY bit
of Status register and sets up the sector buffer for a read operation. Then the
device sets the DRQ bit of Status register, clears the BSY bit, and generates an
interrupt. After that, the host system can read up to 512 bytes of data from the
buffer.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
1
1
0
1
0
0
x
x
DV xx
xx
xx
xx
xx
xx
C141-E104-02EN
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Interface
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
(22) WRITE BUFFER (X’E8’)
The host system can overwrite the contents of the sector buffer of the device with
a desired data pattern by issuing this command. Upon receipt of this command,
the device sets the BSY bit of the Status register. Then the device sets the DRQ
bit of Status register and clears the BSY bit when the device is ready to receive
the data. After that, 512 bytes of data is transferred from the host and the device
writes the data to the sector buffer, then generates an interrupt.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
1
x
1
x
1
1
0
0
0
DV xx
xx
xx
xx
xx
xx
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5.3 Host Commands
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
(23) IDLE (X’97’ or X’E3’)
Upon receipt of this command, the device sets the BSY bit of the Status register,
and enters the idle mode. Then, the device clears the BSY bit, and generates an
interrupt. The device generates an interrupt even if the device has not fully
entered the idle mode. If the spindle of the device is already rotating, the spin-up
sequence shall not be implemented.
By using this command, the automatic power-down function is enabled and the
timer immediately starts the countdown. When the timer reaches the specified
value, the device enters standby mode.
Enabling the automatic power-down function means that the device automatically
enters the standby mode after a certain period of time. When the device enters the
idle mode, the timer starts countdown. If any command is not issued while the
timer is counting down, the device automatically enters the standby mode. If any
command is issued while the timer is counting down, the timer is initialized and
the command is executed. The timer restarts countdown after completion of the
command execution.
The period of timer count is set depending on the value of the Sector Count
register as shown below.
Sector Count register value
[X’00’]
Point of timer
30 minutes
0
1 to 3
[X’01’ to X’03’]
[X’04’ to X’F0’]
15 seconds
4 to 240
(Value ×5) seconds
30 minutes
241 to 251 [X’F1’ to X’FB’]
252
253
[X’FC’]
[X’FD’]
21 minutes
30 minutes
254 to 255 [X’FE’ to X’FF’]
21 minutes 15 seconds
C141-E104-02EN
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Interface
attention: The automatic power-down is executed if no command is coming for
30 min.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
X’97’ or X’E3’
x
xx
xx
xx
x
x
DV xx
Period of timer
xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
(24) IDLE IMMEDIATE (X’95’ or X’E1’)
Upon receipt of this command, the device sets the BSY bit of the Status register,
and enters the idle mode. Then, the device clears the BSY bit, and generates an
interrupt. This command does not support the automatic power-down function.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
X’95’ or X’E1’
x
xx
xx
xx
xx
xx
x
x
DV xx
5-58
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5.3 Host Commands
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
(25) STANDBY (X’96’ or X’E2’)
Upon receipt of this command, the device sets the BSY bit of the Status register
and enters the standby mode. The device then clears the BSY bit and generates an
interrupt. The device generates an interrupt even if the device has not fully
entered the standby mode. If the device has already spun down, the spin-down
sequence is not implemented.
By using this command, the automatic power-down function is enabled and the
timer starts the countdown when the device returns to idle mode.
When the timer value reaches 0 (a specified time has padded), the device enters
standby mode.
Under the standby mode, the spindle motor is stopped. Thus, when the command
involving a seek such as the READ SECTOR(s) command is received, the device
processes the command after driving the spindle motor.
attention: The automatic power-down is executed if no command is coming for
30 min.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
X’96’ or X’E2’
x
xx
xx
xx
x
x
DV xx
Period of timer
xx
C141-E104-02EN
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Interface
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
(26) STANDBY IMMEDIATE (X’94’ or X’E0’)
Upon receipt of this command, the device sets the BSY bit of the Status register
and enters the standby mode. The device then clears the BSY bit and generates an
interrupt. This command does not support the automatic power-down sequence.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
X’94’ or X’E0’
x
xx
xx
xx
xx
xx
x
x
DV xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
5-60
C141-E104-02EN
5.3 Host Commands
(27) SLEEP (X’99’ or X’E6’)
This command is the only way to make the device enter the sleep mode.
Upon receipt of this command, the device sets the BSY bit of the Status register
and enters the sleep mode. The device then clears the BSY bit and generates an
interrupt. The device generates an interrupt even if the device has not fully
entered the sleep mode.
In the sleep mode, the spindle motor is stopped and the ATA interface section is
inactive. All I/O register outputs are in high-impedance state.
The only way to release the device from sleep mode is to execute a software or
hardware reset.
At command issuance (I/O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
X’99’ or X’E6’
x
xx
xx
xx
xx
xx
x
x
DV xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
xx
x
x
DV xx
Error information
C141-E104-02EN
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Interface
(28) CHECK POWER MODE (X’98’ or X’E5’)
The host checks the power mode of the device with this command.
The host system can confirm the power save mode of the device by analyzing the
contents of the Sector Count and Sector registers.
The device sets the BSY bit and sets the following register value. After that, the
device clears the BSY bit and generates an interrupt.
Power save mode
Sector Count register
X’00’
• During moving to standby mode
• Standby mode
• During returning from the standby mode
• Idle mode
X’FF’
X’FF’
• Active mode
At command issuance (I/O registers setting contents)
1F7H(CM) X’98’ or X’E5’
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
x
xx
xx
xx
xx
xx
x
x
DV xx
At command completion (I/O registers contents to be read)
1F7H(ST)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
Status information
x
xx
xx
xx
x
x
DV xx
X’00’ ,X’80’ or X’FF’
Error information
5-62
C141-E104-02EN
5.3 Host Commands
(29) SMART (X’B0)
This command performs operations for device failure predictions according to a
subcommand specified in the FR register. If the value specified in the FR register
is supported, the Aborted Command error is posted.
It is necessary for the host to set the keys (CL = 4Fh and CH = C2h) in the CL and
CH registers prior to issuing this command. If the keys are set incorrectly, the
Aborted Command error is posted.
In the default setting, the failure prediction feature is enabled.
The device collects or updates several items to forecast failures. In the following
sections, the values of items collected or updated by the device to forecast failures
are referred to as attribute values.
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Interface
Table 5.7 Features Register values (subcommands) and functions (1 of 3)
Features Resister
X’D0’
Function
SMART Read Attribute Values:
A device that received this subcommand asserts the BSY bit and saves all
the updated attribute values. The device then clears the BSY bit and
transfers 512-byte attribute value information to the host.
* For information about the format of the attribute value information, see
Table 5.8.
X’D1’
X’D2’
SMART Read Attribute Thresholds:
This subcommand is used to transfer 512-byte insurance failure threshold
value data to the host.
* For information about the format of the insurance failure threshold value
data, see Table 5.9.
SMART Enable-Disable Attribute AutoSave:
This subcommand is used to enable (SC register ≠ 00h) or disable (SC
register = 00h) the setting of the automatic saving feature for the device
attribute data. The setting is maintained every time the device is turned off
and then on. When the automatic saving feature is enabled, the attribute
values are saved before the device enters the power saving mode. However,
if the failure prediction feature is disabled, the attribute values are not
automatically saved.
When the device receives this subcommand, it asserts the BSY bit, enables
or disables the automatic saving feature, then clears the BSY bit.
X’D3’
X’D4’
SMART Save Attribute Values:
When the device receives this subcommand, it asserts the BSY bit, saves
device attribute value data, then clears the BSY bit.
SMART Executive Off-line Immediate:
A device which receives this command asserts the BSY bit, then starts
collecting the off-line data specified in the SN register, or stops.
In the off-line mode, after BSY is cleared, off-line data are collected. In the
captive mode, it collects off-line data with the BSY assertion as is, then
clears the BSY when collection of data is completed.
SN Off-line data collection mode
00h: Off-line diagnosis (off-line mode)
01h: Simple self test (off-line mode)
02h: Comprehensive self test (off-line mode)
7Fh: Self test stop
81h: Simple self test (captive mode)
82h: Comprehensive self test (captive mode)
5-64
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5.3 Host Commands
Table 5.7 Features Register values (subcommands) and functions (2 of 3)
Features Resister
X’D5’
Function
SMART Read Log Sector:
A device which receives this sub-command asserts the BSY bit, then reads
the log sector specified in the SN register. Next, it clears the BSY bit and
transmits the log sector to the host computer.
SN:
01h:
06h:
Log sector
SMART error log
SMART self test log
80h-9Fh: Host vendor log
* See Table 5.10 concerning the SMART error log data format.
See Table 5.11 concerning the SMART self test log data format.
X’D6’
SMART Write Log Sector:
A device which receives this sub-command asserts the BSY bit and when it
has prepared to receive data from the host computer, it sets DRQ and clears
the BSY bit. Next, it receives data from the host computer and writes the
specified log sector in the SN register.
SN:
Log sector
80h-9Fh: Host vendor log
* The host can write any desired data in the host vendor log.
SMART Enable Operations:
This subcommand enables the failure prediction feature. The setting is
maintained even when the device is turned off and then on.
When the device receives this subcommand, it asserts the BSY bit, enables
the failure prediction feature, then clears the BSY bit.
X’D8’
X’D9’
SMART Disable Operations:
This subcommand disables the failure prediction feature. The setting is
maintained even when the device is turned off and then on.
When the device receives this subcommand, it asserts the BSY bit, disables
the failure prediction feature, then clears the BSY bit.
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Interface
Table 5.7 Features Register values (subcommands) and functions (3 of 3)
Features Resister
X’DA’
Function
SMART Return Status:
When the device receives this subcommand, it asserts the BSY bit and saves the
current device attribute values. Then the device compares the device attribute
values with insurance failure threshold values. If there is an attribute value
exceeding the threshold, F4h and 2Ch are loaded into the CL and CH registers.
If there are no attribute values exceeding the thresholds, 4Fh and C2h are loaded
into the CL and CH registers. After the settings for the CL and CH registers
have been determined, the device clears the BSY bit
X’DB’
SMART Enable/Disable Auto Off-line:
This sets automatic off-line data collection in the enabled (when the SC
register specification ≠ 00h) or disabled (when the SC register specification
= 00) state. This setting is preserved whether the drive’s power is switched
on or off.
If four hours have passed since the power was switched on, or since the last
time that off-line data were collected, off-line data collection is performed
without relation to any command from the host computer.
The host must regularly issue the SMART Read Attribute Values subcommand
(FR register = D0h), SMART Save Attribute Values subcommand (FR register =
D3h), or SMART Return Status subcommand (FR register = DAh) to save the
device attribute value data on a medium.
Alternative, the device must issue the SMART Enable-Disable Attribute
AutoSave subcommand (FR register = D2h) to use a feature which regularly save
the device attribute value data to a medium.
The host can predict failures in the device by periodically issuing the SMART Return
Status subcommand (FR register = DAh) to reference the CL and CH registers.
If an attribute value is below the insurance failure threshold value, the device is
about to fail or the device is nearing the end of its life . In this case, the host
recommends that the user quickly backs up the data.
At command issuance (I-O registers setting contents)
1F7H(CM)
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(FR)
1
x
0
x
1
x
1
0
0
0
0
DV xx
Key (C2h)
Key (4Fh)
xx
xx
Subcommand
5-66
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5.3 Host Commands
At command completion (I-O registers setting contents)
1F7H(ST) Status information
1F6H(DH)
1F5H(CH)
1F4H(CL)
1F3H(SN)
1F2H(SC)
1F1H(ER)
x
x
x
DV xx
Key-failure prediction status (C2h-2Ch)
Key-failure prediction status (4Fh-F4h)
xx
xx
Error information
The attribute value information is 512-byte data; the format of this data is shown
below. The host can access this data using the SMART Read Attribute Values
subcommand (FR register = D0h). The insurance failure threshold value data is
512-byte data; the format of this data is shown below. The host can access this
data using the SMART Read Attribute Thresholds subcommand (FR register =
D1h).
C141-E104-02EN
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Interface
Table 5.8 Format of device attribute value data
Byte
00
Item
Data format version number
01
02
Attribute 1
Attribute ID
Status flag
03
04
05
Current attribute value
Attribute value for worst case so far
Raw attribute value
06
07 to 0C
0D
Reserved
0E to 169 Attribute 2 to
attribute 30
(The format of each attribute value is the same
as that of bytes 02 to 0D.)
16A
16B
Off-line data collection status
Self test execution status
16C, 16D Off-line data collection execution time [sec.]
16E
16F
Reserved
Off-line data collection capability
Trouble prediction capability flag
Error logging capability
170, 171
172
173
Vendor unique
174
Simple self test execution time [min.]
Comprehensive self test execution time [min.]
175
176 to 181 Reserved
182 to 1FE Vendor unique
1FF
Check sum
Table 5.9 Format of insurance failure threshold value data
Byte Item
00
01
Data format version number
02
Threshold 1 Attribute ID
03
Insurance failure threshold
Reserved
04 to 0D
0E to 169 Threshold 2 to (The format of each threshold value is the same as
Threshold 30 that of bytes 02 to 0D.)
16A to 17B Reserved
17C to 1FE Vendor unique
1FF Check sum
5-68
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5.3 Host Commands
•
•
Data format version number
The data format version number indicates the version number of the data
format of the device attribute values or insurance failure thresholds. The data
format version numbers of the device attribute values and insurance failure
thresholds are the same. When a data format is changed, the data format
version numbers are updated.
Attribute ID
The attribute ID is defined as follows:
Attribute ID
Attribute name
(Indicates unused attribute data.)
Read error rate
0
1
2
Throughput performance
Spin up time
3
4
Start/stop count
5
Re-allocated sector count
Seek error rate
7
8
Seek time performance
9
Power-on time
10
12
Number of retries made to activate the spindle motor
Number of power-on-power-off times
13 to 198 (Reserved)
199
200
Ultra ATA CRC error rate
Write error rate
201 to 255 (Unique to vendor)
•
Status Flag
Bit
0
Meaning
If this bit 1, it indicates that if the attribute exceeds the threshold,
it is the attribute covered by the drive warranty.
1
If this bit is 1 (0), it indicates the attribute only updated by an on-
line test (off-line test).
2
3
4
If this bit 1, it indicates the attribute that represents performance.
If this bit 1, it indicates the attribute that represents an error rate.
If this bit 1, it indicates the attribute that represents the
number of occurrences.
5
If this bit 1, it indicates the attribute that can be collected/saved
even if the drive fault prediction function is disabled.
6 to 15
Reserve bit
C141-E104-02EN
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Interface
•
•
Current attribute value
The current attribute value is the normalized raw attribute data. The value
varies between 01h and 64h. The closer the value gets to 01h, the higher the
possibility of a failure. The device compares the attribute values with
thresholds. When the attribute values are larger than the thresholds, the
device is operating normally.
Attribute value for the worst case so far
This is the worst attribute value among the attribute values collected to date.
This value indicates the state nearest to a failure so far.
•
•
Raw attribute value
Raw attributes data is retained.
Off-line data collection status
Bits 0 to 6: Indicates the situation of off-line data collection according to the
table below.
Bit 7:
If this bit is 1, it indicates that the automatic off-line data
collection function is enabled.
Status Byte
Meaning
0
2
4
Off-line data collection is not started.
Off-line data collection has been completed normally.
Off-line data collection has been suspended by a command
interrupt.
5
6
Off-line data collection has been aborted by a command
interrupt.
Off-line data collection has been aborted by a fatal error.
•
Self test execution status
Bits 0 to 3: Indicates the rest of self-test in 0 to 9 (corresponding 0 to 90%).
Bits 4 to 7: Indicates the self-test execution status at the following table.
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C141-E104-02EN
5.3 Host Commands
Self-test
Meaning
execution status
0
Self-test has been completed normally or has not been
executed.
1
2
3
4
Self-test has been stopped by the host computer.
Self-test has been suspended by hard or soft reset.
Self-test has been aborted by a fatal error.
Self-test has been completed abnormally by an unknown
meaning.
5
Self-test has been completed abnormally by write test.
Self-test has been completed abnormally by serbo test.
Self-test has been completed abnormally by read test.
Reserved
6
7
8 to 14
15
Self-test is in progress.
•
Off-line data collection capability
Indicates the method of off-line data collection carried out by the drive. If the
off-line data collection capability is 0, it indicates that off-line data collection
is not supported.
Bit
Meaning
Indicates that Execute Off-Line Immediate is supported.
Vendor unique
0
1
2
Indicates that off-line data collection being executed is
aborted when a new command is received.
3
4
Indicates that supports off-line read scan function.
Indicates that supports self-test function.
•
Failure prediction capability flag
Bit 0: The attribute value data is saved to a media before the device enters
power saving mode.
Bit 1: The device automatically saves the attribute value data to a media
after the previously set operation.
Bits 2 to 15: Reserved bits
•
Error logging capability
Bit 0: Indicates that error logging function.
Bits 1 to 7: Reserved bits
C141-E104-02EN
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Interface
•
•
Check sum
Two’s complement of the lower byte, obtained by adding 511-byte data one
byte at a time from the beginning.
Insurance failure threshold
The limit of a varying attribute value. The host compares the attribute values
with the thresholds to identify a failure.
If an unrecoverable error is detected during execution of a command received by
the device from the host computer, the device saves the SMART error log on the
disk medium.
The host computer can issue the SMART Read Log Sector sub-command (FR
register = D5h, SN register = 01h) and read the SMART error log.
Table 5.10 SMART error log data format (1/2)
Byte
00
Item
Error log version number
Error log index
01
02
Error log 1
Command Data 1
Device Control register
Features register
03
04
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Device/Head register
Command register
05
06
07
08
09
0A to 0D
Elapsed time [ms] from the point
when the power is turned on
until command reception
0E to 3D
Command Data 2 to 5 (The format of each type of
command data is the same as
that of byte 02 to 0D.)
3E
3F
40
41
42
43
Error data
Reserved
Error register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
5-72
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5.3 Host Commands
Table 5.10 SMART error log data format (2/2)
Byte
44
Item
Error log 1
Error data
Device/Head register
Status register
Vendor unique
Status
45
46 to 58
59
5A, 5B
5C to 1C3
Total power on time [hour]
Error log 2 (The format of each error log is the same as Byte 02 to
to
5B.)
Error log 5
1C4, 1C5 Number of unrecoverable errors that have occurred.
1C6 to 1FE Reserved
1FF
Check sum
•
•
Error log index
Indicates the latest error log number. If an error has not occurred, 00 is
displayed.
Error log 1 to 5
When an error occurs, the error log index value is incremented and
information at the time the error occurred is recorded in the error log area
specified by this value. When the error log index exceeds 05, it returns to 01.
•
Command data 1 to 5
Indicates five commands data in order received by the device until the error
occurs. Commands for which an error occurred are included in Command
Data 5.
•
•
Error data
Indicates the I/O register values when the error is reported.
Status
Bits 0 to 3: Indicates the drive status when received error commands
according to the following table.
Bits 4 to 7: Vendor unique
C141-E104-02EN
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Interface
Status
Meaning
0
Unclear status
Sleep status
1
2
3
Standby status
Active status or idle status (BSY bit = 0)
Off-line data collection being executed
Reserved
4
5 to F
The host computer can issue the SMART Execute Off-line Immediate sub-
command (FR Register = D4h) and cause the device to execute a self test. When
the self test is completed, the device saves the SMART self test log to the disk
medium.
The host computer can issue the SMART Read Log Sector sub-command (FR
Register = D5h, SN Register = 06h) and can read the SMART self test log.
Table 5.11 SMART self test log data format
Byte
Item
00, 01
02
Self test log data format version number
Self test log 1 Self test mode (SN Register Value)
03
Self test execution status
04, 05
Total power on time until the self test is
completed. [hours]
06
Self test error No.
Error LBA
07 to 0A
0B to 19
Vendor unique
1A to 1F9 Self test log 2 to 21
(Each log data format is the same as that in
byte 02 to 19.)
1FA, 1FB Vendor unique
1FC
Self test index
1FD, 1FE Reserved
1FF
Check sum
•
•
Self test log 1 to 21
When executes self test, the self test index value is incremented and the self
test execution result is recorded in the self log test area specified by this
value. When the self test index exceeds 21, it returns to 01.
Self test index
Indicates the latest self test log number. If the self test has not been executed,
00h is displayed.
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C141-E104-02EN
5.3 Host Commands
(30) SECURITY DISABLE PASSWORD (F6h)
This command invalidates the user password already set and releases the lock
function.
The host transfers the 512-byte data shown in Table 5.12 to the device. The
device compares the user password or master password in the transferred data
with the user password or master password already set, and releases the lock
function if the passwords are the same.
Although this command invalidates the user password, the master password is
retained. To recover the master password, issue the SECURITY SET
PASSWORD command and reset the user password.
If the user password or master password transferred from the host does not match,
the Aborted Command error is returned.
Issuing this command while in LOCKED MODE or FROZEN MODE returns the
Aborted Command error.
(The section about the SECURITY FREEZE LOCK command describes
LOCKED MODE and FROZEN MODE.)
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Interface
Table 5.12 Contents of security password
Word Contents
0
Control word
Bit 0: Identifier
0 = Compares the user passwords.
1 = Compares the master passwords.
Bits 1 to 15: Reserved
1 to 16
Password (32 bytes)
17 to 255 Reserved
At command issuance (I-O register contents))
1F7h(CM)
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(FR)
1
x
1
x
1
x
1
0
1
1
0
DV xx
xx
xx
xx
xx
xx
At command completion (I-O register contents)
1F7h(ST) Status information
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(ER)
x
xx
xx
xx
xx
x
x
DV xx
Error information
(31) SECURITY ERASE PREPARE (F3h)
The SECURITY ERASE UNIT command feature is enabled by issuing the
SECURITY ERASE PREPARE command and then the SECURITY ERASE
UNIT command. The SECURITY ERASE PREPARE command prevents data
from being erased unnecessarily by the SECURITY ERASE UNIT command.
Issuing this command during FROZEN MODE returns the Aborted Command
error.
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5.3 Host Commands
At command issuance (I-O register contents)
1F7h(CM)
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(FR)
1
x
1
x
1
x
1
0
0
1
1
DV xx
xx
xx
xx
xx
xx
At command completion (I-O register contents)
1F7h(ST) Status information
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(ER)
x
xx
xx
xx
xx
x
x
DV xx
Error information
(32) SECURITY ERASE UNIT (F4h)
This command erases all user data. This command also invalidates the user
password and releases the lock function.
The host transfers the 512-byte data shown in Table 5.10 to the device. The
device compares the user password or master password in the transferred data
with the user password or master password already set. The device erases user
data, invalidates the user password, and releases the lock function if the
passwords are the same.
Although this command invalidates the user password, the master password is
retained. To recover the master password, issue the SECURITY SET
PASSWORD command and reset the user password.
If the SECURITY ERASE PREPARE command is not issued immediately before
this command is issued, the Aborted Command error is returned.
Issuing this command while in FROZEN MODE returns the Aborted Command
error.
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Interface
At command issuance (I-O register contents)
1F7h(CM)
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(FR)
1
x
1
x
1
x
1
0
1
0
0
DV xx
xx
xx
xx
xx
xx
At command completion (I-O register contents)
1F7h(ST) Status information
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(ER)
x
xx
xx
xx
xx
x
x
DV xx
Error information
(33) SECURITY FREEZE LOCK (F5h)
This command puts the device into FROZEN MODE. The following commands
used to change the lock function return the Aborted Command error if the device
is in FROZEN MODE.
•
•
•
•
SECURITY SET PASSWORD
SECURITY UNLOCK
SECURITY DISABLE PASSWORD
SECURITY ERASE UNIT
FROZEN MODE is canceled when the power is turned off, or when hardware is
reseted. If this command is reissued in FROZEN MODE, the command is
completed and FROZEN MODE remains unchanged.
Issuing this command during LOCKED MODE returns the Aborted Command
error.
The following medium access commands return the Aborted Command error
when the device is in LOCKED MODE:
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C141-E104-02EN
5.3 Host Commands
• READ DMA
• WRITE DMA
• SECURITY DISABLE PASSWORD
• READ LONG
• WRITE LONG
• SECURITY FREEZE LOCK
• READ MULTIPLE • WRITE MULTIPLE • SECURITY SET PASSWORD
• READ SECTORS
• WRITE SECTORS
• WRITE VERIFY
At command issuance (I-O register contents)
1F7h(CM)
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(FR)
1
x
1
x
1
x
1
0
1
0
1
DV xx
xx
xx
xx
xx
xx
At command completion (I-O register contents)
1F7h(ST) Status information
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(ER)
x
xx
xx
xx
xx
x
x
DV xx
Error information
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Interface
(34) SECURITY SET PASSWORD (F1h)
This command enables a user password or master password to be set.
The host transfers the 512-byte data shown in Table 5.13 to the device. The
device determines the operation of the lock function according to the
specifications of the Identifier bit and Security level bit in the transferred data.
(Table 5.14)
Issuing this command in LOCKED MODE or FROZEN MODE returns the
Aborted Command error.
Table 5.13 Contents of SECURITY SET PASSWORD data
Word
0
Contents
Control word
Bit 0 Identifier
0 = Sets a user password.
1 = Sets a master password.
Bits 1 to 7 Reserved
Bit 8 Security level
0 = High
1 = Maximum
Bits 9 to 15 Reserved
1 to 16
17
Password (32 bytes)
Master password version number
18 to 255 Reserved
Table 5.14 Relationship between combination of Identifier and Security level, and
operation of the lock function
Identifier
User
Level
High
Description
The specified password is saved as a new user password.
The lock function is enabled after the device is turned off
and then on. LOCKED MODE can be canceled using the
user password or the master password already set.
Master
User
High
The specified password is saved as a new master password.
The lock function is not enabled.
Maximum The specified password is saved as a new user password.
The lock function is enabled after the device is turned off
and then on. LOCKED MODE can be canceled using the
user password only. The master password already set
cannot cancel LOCKED MODE.
Master
Maximum The specified password is saved as a new master password.
The lock function is not enabled.
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C141-E104-02EN
5.3 Host Commands
At command issuance (I-O register contents)
1F7h(CM)
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(FR)
1
x
1
x
1
x
1
0
0
0
1
DV xx
xx
xx
xx
xx
xx
At command completion (I-O register contents)
1F7h(ST) Status information
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(ER)
x
xx
xx
xx
xx
x
x
DV xx
Error information
(35) SECURITY UNLOCK
This command cancels LOCKED MODE.
The host transfers the 512-byte data shown in Table 5.12 to the device. Operation
of the device varies as follows depending on whether the host specifies the master
password.
•
When the master password is selected
When the security level is LOCKED MODE is high, the password is
compared with the master password already set. If the passwords are the
same, LOCKED MODE is canceled. Otherwise, the Aborted Command error
is returned. If the security level in LOCKED MODE is set to the highest
level, the Aborted Command error is always returned.
•
When the user password is selected
The password is compared with the user password already set. If the
passwords are the same, LOCKED MODE is canceled. Otherwise, the
Aborted Command error is returned.
If the password comparison fails, the device decrements the UNLOCK counter.
The UNLOCK counter initially has a value of five. When the value of the
UNLOCK counter reaches zero, this command or the SECURITY ERASE UNIT
command causes the Aborted Command error until the device is turned off and
then on, or until a hardware reset is executed. Issuing this command with
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Interface
LOCKED MODE canceled (in UNLOCK MODE) has no affect on the UNLOCK
counter.
Issuing this command in FROZEN MODE returns the Aborted Command error.
At command issuance (I-O register contents)
1F7h(CM)
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(FR)
1
x
1
x
1
x
1
0
0
1
0
DV xx
xx
xx
xx
xx
xx
At command completion (I-O register contents)
1F7h(ST) Status information
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(ER)
x
xx
xx
xx
xx
x
x
DV xx
Error information
(36) FLUSH CACHE (E7)
This command is used to order to write every write cache data stored by the
device into the medium. BSY bit is held at "1" until every data has been written
normally or an error has occurred. The device performs every error recovery so
that the data are read correctly.
When executing this command, the reading of the data may take several seconds
if much data are to be read.
In case a non-recoverable error has occurred while the data is being read, the error
generation address is put into the command block register before ending the
command. This error sector is deleted from the write cache data, and the
remaining cache data is written into the medium by the execution of the next
Flush Cache command.
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5.3 Host Commands
At command issuance (I-O register contents)
1F7h(CM)
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(FR)
1
x
1
x
1
x
0
0
1
1
1
DV xx
xx
xx
xx
xx
xx
At command completion (I-O register contents to be read)
1F7h(ST) Status information
1F6h(DH)
1F5h(CH)
1F4h(CL)
1F3h(SN)
1F2h(SC)
1F1h(ER)
x
xx
xx
xx
xx
x
x
DV xx
Error information
5.3.3 Error posting
Table 5.15 lists the defined errors that are valid for each command.
Table 5.15 Command code and parameters (1 of 2)
Command name
Error register (X’1F1’)
Status register (X’1F7’)
ICRC
UNC
V
INDF
V
ABRT
V
TK0NF
DRDY
DWF
V
ERR
V
READ SECTOR(S)
WRITE SECTOR(S)
READ MULTIPLE
WRITE MULTIPLE
READ DMA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
WRITE DMA
V
V
V
V
WRITE VERIFY
V
V
V
V
V
V
READ VERIFY SECTOR(S)
V
V
V
V
V:
*:
Valid on this command
See the command descriptions.
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Interface
Table 5.15 Command code and parameters (2 of 2)
Command name
Error register (X’1F1’)
Status register (X’1F7’)
ICRC
UNC
INDF
ABRT
V
V
V
V
V
V
V
V
V
*
TK0NF
V
DRDY
DWF
V
ERR
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
RECALIBRATE
V
V
V
V
V
V
V
V
V
SEEK
V
V
INITIALIZE DEVICE PARAMETERS
IDENTIFY DEVICE
IDENTIFY DEVICE DMA
SET FEATURES
V
V
V
V
SET MULTIPLE MODE
SET MAX ADDRESS
READ NATIVE MAX ADDRESS
EXECUTE DEVICE DIAGNOSTIC
READ LONG
V
V
V
V
*
*
*
V
V
*
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
WRITE LONG
READ BUFFER
WRITE BUFFER
IDLE
IDLE IMMEDIATE
STANDBY
STANDBY IMMEDIATE
SLEEP
CHECK POWER MODE
SMART
V
SECURITY DISABLE PASSWORD
SECURITY ERASE PREPARE
SECURITY ERASE UNIT
SECURITY FREEZE LOCK
SECURITY SET PASSWORD
SECURITY UNLOCK
FLUSH CACHE
V
Invalid command
V:
*:
Valid on this command
See the command descriptions.
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C141-E104-02EN
5.4 Command Protocol
5.4 Command Protocol
The host should confirm that the BSY bit of the Status register of the device is 0
prior to issue a command. If BSY bit is 1, the host should wait for issuing a
command until BSY bit is cleared to 0.
Commands can be executed only when the DRDY bit of the Status register is 1.
However, the following commands can be executed even if DRDY bit is 0.
•
•
EXECUTE DEVICE DIAGNOSTIC
INITIALIZE DEVICE PARAMETERS
5.4.1 Data transferring commands from device to host
The execution of the following commands involves data transfer from the device
to the host.
•
•
•
•
•
•
IDENTIFY DEVICE.
IDENTIFY DEVICE DMA
READ SECTOR(S)
READ LONG
READ BUFFER
SMART
The execution of these commands includes the transfer one or more sectors of
data from the device to the host. In the READ LONG command, 516 bytes are
transferred. Following shows the protocol outline.
a) The host writes any required parameters to the Features, Sector Count, Sector
Number, Cylinder, and Device/Head registers.
b) The host writes a command code to the Command register.
c) The device sets the BSY bit of the Status register and prepares for data
transfer.
d) When one sector of data is available for transfer to the host, the device sets
DRQ bit and clears BSY bit. The drive then asserts INTRQ signal.
e) After detecting the INTRQ signal assertion, the host reads the Status register.
The host reads one sector of data via the Data register. In response to the
Status register being read, the device negates the INTRQ signal.
f) The drive clears DRQ bit to 0. If transfer of another sector is requested, the
device sets the BSY bit and steps d) and after are repeated.
Even if an error is encountered, the device prepares for data transfer by setting the
DRQ bit. Whether or not to transfer the data is determined for each host. In other
C141-E104-02EN
5-85
Interface
words, the host should receive the relevant sector of data (512 bytes of uninsured
dummy data) or release the DRQ status by resetting.
Figure 5.3 shows an example of READ SECTOR(S) command protocol, and
Figure 5.4 shows an example protocol for command abort.
Figure 5.3 Read Sector(s) command protocol
IMPORTANT
For transfer of a sector of data, the host needs to read Status register
(X’1F7’) in order to clear INTRQ (interrupt) signal. The Status
register should be read within a period from the DRQ setting by the
device to 50 ms after the completion of the sector data transfer.
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5.4 Command Protocol
Note that the host does not need to read the Status register for the
reading of a single sector or the last sector in multiple-sector
reading. If the timing to read the Status register does not meet
above condition, normal data transfer operation is not guaranteed.
When the host new command even if the device requests the data
transfer (setting in DRQ bit), the correct device operation is not
guaranteed.
Figure 5.4 Protocol for command abort
5.4.2 Data transferring commands from host to device
The execution of the following commands involves Data transfer from the host to
the drive.
•
•
•
•
•
•
•
•
WRITE SECTOR(S)
WRITE LONG
WRITE BUFFER
WRITE VERIFY
SECURITY DISABLE PASSWORD
SECURITY ERASE UNIT
SECURITY SET PASSWORD
SECURITY UNCLOK
The execution of these commands includes the transfer one or more sectors of
data from the host to the device. In the WRITE LONG command, 516 bytes are
transferred. Following shows the protocol outline.
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Interface
a) The host writes any required parameters to the Features, Sector Count, Sector
Number, Cylinder, and Device/Head registers.
b) The host writes a command code in the Command register. The drive sets the
BSY bit of the Status register.
c) When the device is ready to receive the data of the first sector, the device sets
DRQ bit and clears BSY bit.
d) The host writes one sector of data through the Data register.
e) The device clears the DRQ bit and sets the BSY bit.
f) When the drive completes transferring the data of the sector, the device clears
BSY bit and asserts INTRQ signal. If transfer of another sector is requested,
the drive sets the DRQ bit.
g) After detecting the INTRQ signal assertion, the host reads the Status register.
h) The device resets INTRQ (the interrupt signal).
i) If transfer of another sector is requested, steps d) and after are repeated.
Figure 5.5 shows an example of WRITE SECTOR(S) command protocol.
Figure 5.5 WRITE SECTOR(S) command protocol
5-88
C141-E104-02EN
5.4 Command Protocol
IMPORTANT
For transfer of a sector of data, the host needs to read Status register
(X’1F7’) in order to clear INTRQ (interrupt) signal. The Status
register should be read within a period from the DRQ setting by the
device to 50 µs after the completion of the sector data transfer.
Note that the host does not need to read the Status register for the
first and the last sector to be transferred. If the timing to read the
Status register does not meet above condition, normal data transfer
operation is not assured guaranteed.
When the host issues the command even if the drive requests the
data transfer (DRQ bit is set), or when the host executes resetting,
the device correct operation is not guaranteed.
5.4.3 Commands without data transfer
Execution of the following commands does not involve data transfer between the
host and the device.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RECABLIBRATE
SEEK
READY VERIFY SECTOR(S)
EXECUTE DEVICE DIAGNOSTIC
INITIALIZE DEVICE PARAMETERS
SET FEATURES
SET MULTIPLE MODE
SET MAX ADDRESS
READ NATIVE MAX ADDRESS
IDLE
IDLE IMMEDIATE
STANDBY
STANDBY IMMEDIATE
CHECK POWER MODE
SECURITY ERASE PREPARE
SECURITY FREEZE LOCK
FLUSH CACHE
Figure 5.6 shows the protocol for the command execution without data transfer.
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Interface
Figure 5.6 Protocol for the command execution without data transfer
5.4.4 Other commands
•
•
•
READ MULTIPLE
SLEEP
WRITE MULTIPLE
See the description of each command.
5.4.5 DMA data transfer commands
•
•
READ DMA
WRITE DMA
Starting the DMA transfer command is the same as the READ SECTOR(S) or
WRITE SECTOR(S) command except the point that the host initializes the DMA
channel preceding the command issuance.
Interruption processing for DMA transfer does not issue interruptions in any
intermediate sector when a multisector command is executed.
The following outlines the protocol:
The interrupt processing for the DMA transfer differs the following point.
•
The interrupt processing for the DMA transfer differs the following point.
a) The host writes any parameters to the Features, Sector Count, Sector Number,
Cylinder, and Device/Head register.
b) The host initializes the DMA channel
c) The host writes a command code in the Command register.
d) The device sets the BSY bit of the Status register.
e) The device asserts the DMARQ signal after completing the preparation of
data transfer. The device asserts either the BSY bit or DRQ bit during DMA
data transfer.
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5.5 Ultra DMA Feature Set
f) When the command execution is completed, the device clears both BSY and
DRQ bits and asserts the INTRQ signal. Then, the host reads the Status
register.
g) The host resets the DMA channel.
Figure 5.7 shows the correct DMA data transfer protocol.
f
g
d
d
f
e
d
f
e
Figure 5.7 Normal DMA data transfer
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Interface
5.5 Ultra DMA Feature Set
5.5.1 Overview
Ultra DMA is a data transfer protocol used with the READ DMA and WRITE
DMA commands. When this protocol is enabled it shall be used instead of the
Multiword DMA protocol when these commands are issued by the host. This
protocol applies to the Ultra DMA data burst only. When this protocol is used
there are no changes to other elements of the ATA protocol (e.g.: Command
Block Register access).
Several signal lines are redefined to provide new functions during an Ultra DMA
burst. These lines assume these definitions when 1) an Ultra DMA Mode is
selected, and 2) a host issues a READ DMA or a WRITE DMA, command
requiring data transfer, and 3) the host asserts DMACK-. These signal lines
revert back to the definitions used for non-Ultra DMA transfers upon the negation
of DMACK- by the host at the termination of an Ultra DMA burst. All of the
control signals are unidirectional. DMARQ and DMACK- retain their standard
definitions.
With the Ultra DMA protocol, the control signal (STROBE) that latches data
from DD (15:0) is generated by the same agent (either host or device) that drives
the data onto the bus. Ownership of DD (15:0) and this data strobe signal are
given either to the device during an Ultra DMA data in burst or to the host for an
Ultra DMA data out burst.
During an Ultra DMA burst a sender shall always drive data onto the bus, and
after a sufficient time to allow for propagation delay, cable settling, and setup
time, the sender shall generate a STROBE edge to latch the data. Both edges of
STROBE are used for data transfers so that the frequency of STROBE is limited
to the same frequency as the data. The highest fundamental frequency on the
cable shall be 16.67 million transitions per second or 8.33 MHz (the same as the
maximum frequency for PIO Mode 4 and DMA Mode 2).
Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature
and the Ultra DMA Modes the device is capable of supporting. The Set transfer
mode subcommand in the SET FEATURES command shall be used by a host to
select the Ultra DMA Mode at which the system operates. The Ultra DMA Mode
selected by a host shall be less than or equal to the fastest mode of which the
device is capable. Only the Ultra DMA Mode shall be selected at any given time.
All timing requirements for a selected Ultra DMA Mode shall be satisfied.
Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0
and 1. Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA
Mode 0.
An Ultra DMA capable device shall retain its previously selected Ultra DMA
Mode after executing a Software reset sequence. An Ultra DMA capable device
shall clear any previously selected Ultra DMA Mode and revert to its default non-
Ultra DMA Modes after executing a Power on or hardware reset.
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5.5 Ultra DMA Feature Set
Both the host and device perform a CRC function during an Ultra DMA burst. At
the end of an Ultra DMA burst the host sends the its CRC data to the device. The
device compares its CRC data to the data sent from the host. If the two values do
not match the device reports an error in the error register at the end of the
command. If an error occurs during one or more Ultra DMA bursts for any one
command, at the end of the command, the device shall report the first error that
occurred.
5.5.2 Phases of operation
An Ultra DMA data transfer is accomplished through a series of Ultra DMA data
in or data out bursts. Each Ultra DMA burst has three mandatory phases of
operation: the initiation phase, the data transfer phase, and the Ultra DMA burst
termination phase. In addition, an Ultra DMA burst may be paused during the
data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for
each of these phases, 5.6.4 defines the specific timing requirements). In the
following rules DMARDY- is used in cases that could apply to either
DDMARDY- or HDMARDY-, and STROBE is used in cases that could apply to
either DSTROBE or HSTROBE. The following are general Ultra DMA rules.
a) An Ultra DMA burst is defined as the period from an assertion of DMACK-
by the host to the subsequent negation of DMACK-.
b) A recipient shall be prepared to receive at least two data words whenever it
enters or resumes an Ultra DMA burst.
5.5.2.1 Ultra DMA burst initiation phase
a) The Ultra DMA burst initiation phase is started by the assertion of DMARQ
signal by the device, and is ended when the transmitting side has inverted
STROBE signal for transmitting the first data.
b) The Ultra DMA burst requires the assertion of DMARQ signal by the device.
c) The host asserts DMACK-signal when it is able to start the requested burst.
d) The host always asserts DMACK signal after detecting the first assertion of
DMARQ signal.
e) Ultra DMA data in burst
The device starts transmission of the data to DD (15 : 0) when;
•
•
•
DMACK-signal assertion has been detected,
STOP signal negation has been detected, or
HDMARDY-signal assertion has been detected.
f) Ultra DMA data out burst
The device should not invert the state of this signal in the period from the
moment of DMARQ signal assertion or DDMARDY-signal assertion to the
moment of inversion of the first STROBE signal.
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g) Ultra DMA data in burst
The device should not invert the state of this signal in the period from the
moment of STOP signal negation or HDMARDY-signal assertion to the
moment of inversion of the first STROBE signal.
5.5.2.2 Data transfer phase
a) The Data transfer phase is defined as the period from The Ultra DMA burst
initiation phase to Ultra DMA burst termination phase.
b) The receiving side stops the Ultra DMA burst temporarily by negating
DMARDY-signal, and then restarts the Ultra DMA burst by asserting again.
c) The transmitting side stops the Ultra DMA burst temporarily by not-
performing inversion of STROBE signal, and then restarts the Ultra DMA
burst by restarting the inversion.
d) When the transmitting side has stopped the inversion of STROBE signal, the
receiving side should not output termination request signal immediately.
The receiving side should negate DMARDY signal when no termination
request signal has been received from the transmission side, and then should
output the termination request signal when a certain wait time has elapsed.
e) The transmitting side is allowed to send STROBE signal at a transfer speed
that is lower than the one in the transferable fastest Ultra DMA mode, but is
not allowed to send the STROBE signal at a higher speed than this.
The receiving side should be able to receive the data in the transferable
fastest Ultra DMA mode.
5.5.2.3 Ultra DMA burst termination phase
a) The transmitting side or receiving side is allowed to end the Ultra DMA
burst.
b) The Ultra DMA burst termination is not the end of the command execution.
When the Ultra DMA burst termination has occurred before the ending of the
command, the command should be ended by starting a new Ultra DMA burst,
or the host should issue command abort by outputting hard reset or soft reset
to the device.
c) The Ultra DMA burst should be stopped temporarily before the receiving side
outputs the ending request.
d) The host outputs the ending request by asserting STOP signal, and then the
device negates DMARQ signal to confirm it.
e) The device outputs the ending request by negating DMARQ signal, and then
the host asserts STOP signal to confirm it.
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f) Once the transmitting side has outputted the ending request, the output state
of STROBE signal should not be changed unless the receiving side has
confirmed it. Then, if the STROBE signal is not in asserted state, The
transmitting side should assert the STROBE signal. However, the assertion of
the STROBE signal should not cause the data transfer to occur.
g) The transmitting side should return the STROBE signal to its asserted state
immediately after receiving the ending request from the receiving side.
However, the returning of the STROBE signal to its asserted state should not
cause the data transfer to occur and CRC to be perform.
h) Once the receiving side has outputted the ending request, the negated state of
the DMARDY signal should not be changed for the remaining Ultra DMA
burst to be performed.
i) The receiving side should neglect the inversion of the STROBE signal if
DMARQ signal has been negated or STOP signal has been asserted.
5.5.3 Ultra DMA data in commands
5.5.3.1 Initiating an Ultra DMA data in burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.1 and 5.6.4.2 for specific timing requirements):
1) The host shall keep DMACK- in the negated state before an Ultra DMA burst
is initiated.
2) The device shall assert DMARQ to initiate an Ultra DMA burst. After
assertion of DMARQ the device shall not negate DMARQ until after the first
negation of DSTROBE.
3) Steps (3), (4) and (5) may occur in any order or at the same time. The host
shall assert STOP.
4) The host shall negate HDMARDY-.
5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep
CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at
the end of the burst.
6) Steps (3), (4) and (5) shall have occurred at least tACK before the host asserts
DMACK-. The host shall keep DMACK- asserted until the end of an Ultra
DMA burst.
7) The host shall release DD (15:0) within tAZ after asserting DMACK-.
8) The device may assert DSTROBE tZIORDY after the host has asserted
DMACK-. Once the device has driven DSTROBE the device shall not
release DSTROBE until after the host has negated DMACK- at the end of an
Ultra DMA burst.
9) The host shall negate STOP and assert HDMARDY- within tENV after
asserting DMACK-. After negating STOP and asserting HDMARDY-, the
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host shall not change the state of either signal until after receiving the first
transition of DSTROBE from the device (i.e., after the first data word has
been received).
10) The device shall drive DD (15:0) no sooner than tZAD after the host has
asserted DMACK-, negated STOP, and asserted HDMARDY-.
11) The device shall drive the first word of the data transfer onto DD (15:0).
This step may occur when the device first drives DD (15:0) in step (10).
12) To transfer the first word of data the device shall negate DSTROBE within tFS
after the host has negated STOP and asserted HDMARDY-. The device shall
negate DSTROBE no sooner than tDVS after driving the first word of data onto
DD (15:0).
5.5.3.2 The data in transfer
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.3 and 5.6.4.2):
1) The device shall drive a data word onto DD (15:0).
2) The device shall generate a DSTROBE edge to latch the new word no sooner
than tDVS after changing the state of DD (15:0). The device shall generate a
DSTROBE edge no more frequently than tCYC for the selected Ultra DMA
Mode. The device shall not generate two rising or two falling DSTROBE
edges more frequently than 2tCYC for the selected Ultra DMA mode.
3) The device shall not change the state of DD (15:0) until at least tDVH after
generating a DSTROBE edge to latch the data.
4) The device shall repeat steps (1), (2) and (3) until the data transfer is
complete or an Ultra DMA burst is paused, whichever occurs first.
5.5.3.3 Pausing an Ultra DMA data in burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.4 and 5.6.4.2 for specific timing requirements).
a) Device pausing an Ultra DMA data in burst
1) The device shall not pause an Ultra DMA burst until at least one data
word of an Ultra DMA burst has been transferred.
2) The device shall pause an Ultra DMA burst by not generating DSTROBE
edges.
NOTE - The host shall not immediately assert STOP to initiate Ultra
DMA burst termination when the device stops generating STROBE
edges. If the device does not negate DMARQ, in order to initiate
ULTRA DMA burst termination, the host shall negate HDMARDY- and
wait tRP before asserting STOP.
3) The device shall resume an Ultra DMA burst by generating a DSTROBE
edge.
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b) Host pausing an Ultra DMA data in burst
1) The host shall not pause an Ultra DMA burst until at least one data word
of an Ultra DMA burst has been transferred.
2) The host shall pause an Ultra DMA burst by negating HDMARDY-.
3) The device shall stop generating DSTROBE edges within tRFS of the host
negating HDMARDY-.
4) If the host negates HDMARDY- within tSR after the device has generated
a DSTROBE edge, then the host shall be prepared to receive zero or one
additional data words. If the host negates HDMARDY- greater than tSR
after the device has generated a DSTROBE edge, then the host shall be
prepared to receive zero, one or two additional data words. The
additional data words are a result of cable round trip delay and tRFS
timing for the device.
5) The host shall resume an Ultra DMA burst by asserting HDMARDY-.
5.5.3.4 Terminating an Ultra DMA data in burst
a) Device terminating an Ultra DMA data in burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.5 and 5.6.4.2 for specific timing
requirements):
1) The device shall initiate termination of an Ultra DMA burst by not
generating DSTROBE edges.
2) The device shall negate DMARQ no sooner than tSS after generating the
last DSTROBE edge. The device shall not assert DMARQ again until
after the Ultra DMA burst is terminated.
3) The device shall release DD (15:0) no later than tAZ after negating
DMARQ.
4) The host shall assert STOP within tLI after the device has negated
DMARQ. The host shall not negate STOP again until after the Ultra
DMA burst is terminated.
5) The host shall negate HDMARDY- within tLI after the device has
negated DMARQ. The host shall continue to negate HDMARDY- until
the Ultra DMA burst is terminated. Steps (4) and (5) may occur at the
same time.
6) The host shall drive DD (15:0) no sooner than tZAH after the device has
negated DMARQ. For this step, the host may first drive DD (15:0) with
the result of its CRC calculation (see 5.5.5):
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7) If DSTROBE is negated, the device shall assert DSTROBE within tLI
after the host has asserted STOP. No data shall be transferred during this
assertion. The host shall ignore this transition on DSTROBE.
DSTROBE shall remain asserted until the Ultra DMA burst is
terminated.
8) If the host has not placed the result of its CRC calculation on DD (15:0)
since first driving DD (15:0) during (6), the host shall place the result of
its CRC calculation on DD (15:0) (see 5.5.5).
9) The host shall negate DMACK- no sooner than tMLI after the device has
asserted DSTROBE and negated DMARQ and the host has asserted
STOP and negated HDMARDY-, and no sooner than tDVS after the host
places the result of its CRC calculation on DD (15:0).
10) The device shall latch the host's CRC data from DD (15:0) on the
negating edge of DMACK-.
11) The device shall compare the CRC data received from the host with the
results of its own CRC calculation. If a miscompare error occurs during
one or more Ultra DMA bursts for any one command, at the end of the
command the device shall report the first error that occurred (see 5.5.5).
12) The device shall release DSTROBE within tIORDYZ after the host negates
DMACK-.
13) The host shall not negate STOP no assert HDMARDY- until at least tACK
after negating DMACK-.
14) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at
least tACK after negating DMACK.
b) Host terminating an Ultra DMA data in burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.6 and 5.6.4.2 for specific timing
requirements):
1) The host shall not initiate Ultra DMA burst termination until at least one
data word of an Ultra DMA burst has been transferred.
2) The host shall initiate Ultra DMA burst termination by negating
HDMARDY-. The host shall continue to negate HDMARDY- until the
Ultra DMA burst is terminated.
3) The device shall stop generating DSTROBE edges within tRFS of the host
negating HDMARDY-.
4) If the host negates HDMARDY- within tSR after the device has generated
a DSTROBE edge, then the host shall be prepared to receive zero or one
additional data words. If the host negates HDMARDY- greater than tSR
after the device has generated a DSTROBE edge, then the host shall be
prepared to receive zero, one or two additional data words. The
additional data words are a result of cable round trip delay and tRFS
timing for the device.
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5) The host shall assert STOP no sooner than tRP after negating
HDMARDY-. The host shall not negate STOP again until after the Ultra
DMA burst is terminated.
6) The device shall negate DMARQ within tLI after the host has asserted
STOP. The device shall not assert DMARQ again until after the Ultra
DMA burst is terminated.
7) If DSTROBE is negated, the device shall assert DSTROBE within tLI
after the host has asserted STOP. No data shall be transferred during this
assertion. The host shall ignore this transition on DSTROBE.
DSTROBE shall remain asserted until the Ultra DMA burst is
terminated.
8) The device shall release DD (15:0) no later than tAZ after negating
DMARQ.
9) The host shall drive DD (15:0) no sooner than tZAH after the device has
negated DMARQ. For this step, the host may first drive DD (15:0) with
the result of its CRC calculation (see 5.5.5).
10) If the host has not placed the result of its CRC calculation on DD (15:0)
since first driving DD (15:0) during (9), the host shall place the result of
its CRC calculation on DD (15:0) (see 5.5.5).
11) The host shall negate DMACK- no sooner than tMLI after the device has
asserted DSTROBE and negated DMARQ and the host has asserted
STOP and negated HDMARDY-, and no sooner than tDVS after the host
places the result of its CRC calculation on DD (15:0).
12) The device shall latch the host's CRC data from DD (15:0) on the
negating edge of DMACK-.
13) The device shall compare the CRC data received from the host with the
results of its own CRC calculation. If a miscompare error occurs during
one or more Ultra DMA burst for any one command, at the end of the
command, the device shall report the first error that occurred (see 5.5.5).
14) The device shall release DSTROBE within tIORDYZ after the host negates
DMACK-.
15) The host shall neither negate STOP nor assert HDMARDY- until at least
t
ACK after the host has negated DMACK-.
16) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at
least tACK after negating DMACK.
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5.5.4 Ultra DMA data out commands
5.5.4.1 Initiating an Ultra DMA data out burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.7 and 5.6.4.2 for specific timing requirements):
1) The host shall keep DMACK- in the negated state before an Ultra DMA burst
is initiated.
2) The device shall assert DMARQ to initiate an Ultra DMA burst.
3) Steps (3), (4), and (5) may occur in any order or at the same time. The host
shall assert STOP.
4) The host shall assert HSTROBE.
5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep
CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at
the end of the burst.
6) Steps (3), (4), and (5) shall have occurred at least tACK before the host asserts
DMACK-. The host shall keep DMACK- asserted until the end of an Ultra
DMA burst.
7) The device may negate DDMARDY- tZIORDY after the host has asserted
DMACK-. Once the device has negated DDMARDY-, the device shall not
release DDMARDY- until after the host has negated DMACK- at the end of
an Ultra DMA burst.
8) The host shall negate STOP within tENV after asserting DMACK-. The host
shall not assert STOP until after the first negation of HSTROBE.
9) The device shall assert DDMARDY- within tLI after the host has negated
STOP. After asserting DMARQ and DDMARDY- the device shall not
negate either signal until after the first negation of HSTROBE by the host.
10) The host shall drive the first word of the data transfer onto DD (15:0). This
step may occur any time during Ultra DMA burst initiation.
11) To transfer the first word of data: the host shall negate HSTROBE no sooner
than tLI after the device has asserted DDMARDY-. The host shall negate
HSTROBE no sooner than tDVS after the driving the first word of data onto
DD (15:0).
5.5.4.2 The data out transfer
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.8 and 5.6.4.2 for specific timing requirements):
1) The host shall drive a data word onto DD (15:0).
2) The host shall generate an HSTROBE edge to latch the new word no sooner
than tDVS after changing the state of DD (15:0). The host shall generate an
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HSTROBE edge no more frequently than tCYC for the selected Ultra DMA
Mode. The host shall not generate two rising or falling HSTROBE edges
more frequently than 2 tCYC for the selected Ultra DMA mode.
3) The host shall not change the state of DD (15:0) until at least tDVH after
generating an HSTROBE edge to latch the data.
4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete
or an Ultra DMA burst is paused, whichever occurs first.
5.5.4.3 Pausing an Ultra DMA data out burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.9 and 5.6.4.2 for specific timing requirements).
a) Host pausing an Ultra DMA data out burst
1) The host shall not pause an Ultra DMA burst until at least one data word
of an Ultra DMA burst has been transferred.
2) The host shall pause an Ultra DMA burst by not generating an
HSTROBE edge.
Note: The device shall not immediately negate DMARQ to initiate Ultra
DMA burst termination when the host stops generating HSTROBE
edges. If the host does not assert STOP, in order to initiate Ultra DMA
burst termination, the device shall negate DDMARDY- and wait tRP
before negating DMARQ.
3) The host shall resume an Ultra DMA burst by generating an HSTROBE
edge.
b) Device pausing an Ultra DMA data out burst
1) The device shall not pause an Ultra DMA burst until at least one data
word of an Ultra DMA burst has been transferred.
2) The device shall pause an Ultra DMA burst by negating DDMARDY-.
3) The host shall stop generating HSTROBE edges within tRFS of the device
negating DDMARDY-.
4) If the device negates DDMARDY- within tSR after the host has generated
an HSTROBE edge, then the device shall be prepared to receive zero or
one additional data words. If the device negates DDMARDY- greater
than tSR after the host has generated an HSTROBE edge, then the device
shall be prepared to receive zero, one or two additional data words. The
additional data words are a result of cable round trip delay and tRFS
timing for the host.
5) The device shall resume an Ultra DMA burst by asserting DDMARDY-.
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5.5.4.4 Terminating an Ultra DMA data out burst
a) Host terminating an Ultra DMA data out burst
The following stops shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.10 and 5.6.4.2 for specific timing
requirements):
1) The host shall initiate termination of an Ultra DMA burst by not
generating HSTROBE edges.
2) The host shall assert STOP no sooner than tSS after it last generated an
HSTROBE edge. The host shall not negate STOP again until after the
Ultra DMA burst is terminated.
3) The device shall negate DMARQ within tLI after the host asserts STOP.
The device shall not assert DMARQ again until after the Ultra DMA
burst is terminated.
4) The device shall negate DDMARDY- with tLI after the host has negated
STOP. The device shall not assert DDMARDY- again until after the
Ultra DMA burst termination is complete.
5) If HSTROBE is negated, the host shall assert HSTROBE with tLI after
the device has negated DMARQ. No data shall be transferred during this
assertion. The device shall ignore this transition on HSTROBE.
HSTROBE shall remain asserted until the Ultra DMA burst is
terminated.
6) The host shall place the result of its CRC calculation on DD (15:0) (see
5.5.5)
7) The host shall negate DMACK- no sooner than tMLI after the host has
asserted HSTROBE and STOP and the device has negated DMARQ and
DDMARDY-, and no sooner than tDVS after placing the result of its CRC
calculation on DD (15:0).
8) The device shall latch the host's CRC data from DD (15:0) on the
negating edge of DMACK-.
9) The device shall compare the CRC data received from the host with the
results of its own CRC calculation. If a miscompare error occurs during
one or more Ultra DMA bursts for any one command, at the end of the
command, the device shall report the first error that occurred (see 5.5.5).
10) The device shall release DDMARDY- within tIORDYZ after the host has
negated DMACK-.
11) The host shall neither negate STOP nor negate HSTROBE until at least
t
ACK after negating DMACK-.
12) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until
at least tACK after negating DMACK.
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b) Device terminating an Ultra DMA data out burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.11 and 5.6.4.2 for specific timing
requirements):
1) The device shall not initiate Ultra DMA burst termination until at least
one data word of an Ultra DMA burst has been transferred.
2) The device shall initiate Ultra DMA burst termination by negating
DDMARDY-.
3) The host shall stop generating an HSTROBE edges within tRFS of the
device negating DDMARDY-.
4) If the device negates DDMARDY- within tSR after the host has generated
an HSTROBE edge, then the device shall be prepared to receive zero or
one additional data words. If the device negates DDMARDY- greater
than tSR after the host has generated an HSTROBE edge, then the device
shall be prepared to receive zero, one or two additional data words. The
additional data words are a result of cable round trip delay and tRFS
timing for the host.
5) The device shall negate DMARQ no sooner than tRP after negating
DDMARDY-. The device shall not assert DMARQ again until after the
Ultra DMA burst is terminated.
6) The host shall assert STOP with tLI after the device has negated
DMARQ. The host shall not negate STOP again until after the Ultra
DMA burst is terminated.
7) If HSTROBE is negated, the host shall assert HSTROBE with tLI after
the device has negated DMARQ. No data shall be transferred during this
assertion. The device shall ignore this transition of HSTROBE.
HSTROBE shall remain asserted until the Ultra DMA burst is
terminated.
8) The host shall place the result of its CRC calculation on DD (15:0) (see
5.5.5).
9) The host shall negate DMACK- no sooner than tMLI after the host has
asserted HSTROBE and STOP and the device has negated DMARQ and
DDMARDY-, and no sooner than tDVS after placing the result of its CRC
calculation on DD (15:0).
10) The device shall latch the host's CRC data from DD (15:0) on the
negating edge of DMACK-.
11) The device shall compare the CRC data received from the host with the
results of its own CRC calculation. If a miscompare error occurs during
one or more Ultra DMA bursts for any one command, at the end of the
command, the device shall report the first error that occurred (see 5.5.5).
12) The device shall release DDMARDY- within tIORDYZ after the host has
negated DMACK-.
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13) The host shall neither negate STOP nor HSTROBE until at least tACK after
negating DMACK-.
14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until
at least tACK after negating DMACK.
5.5.5 Ultra DMA CRC rules
The following is a list of rules for calculating CRC, determining if a CRC error
has occurred during an Ultra DMA burst, and reporting any error that occurs at
the end of a command.
a) Both the host and the device shall have a 16-bit CRC calculation function.
b) Both the host and the device shall calculate a CRC value for each Ultra DMA
burst.
c) The CRC function in the host and the device shall be initialized with a seed
of 4ABAh at the beginning of an Ultra DMA burst before any data is
transferred.
d) For each STROBE transition used for data transfer, both the host and the
device shall calculate a new CRC value by applying the CRC polynomial to
the current value of their individual CRC functions and the word being
transferred. CRC is not calculated for the return of STROBE to the asserted
state after the Ultra DMA burst termination request has been acknowledged.
e) At the end of any Ultra DMA burst the host shall send the results of its CRC
calculation function to the device on DD (15:0) with the negation of
DMACK-.
f) The device shall then compare the CRC data from the host with the calculated
value in its own CRC calculation function. If the two values do not match,
the device shall save the error and report it at the end of the command. A
subsequent Ultra DMA burst for the same command that does not have a
CRC error shall not clear an error saved from a previous Ultra DMa burst in
the same command. If a miscompare error occurs during one or more Ultra
DMA bursts for any one command, at the end of the command, the device
shall report the first error that occurred.
g) For READ DMA or WRITE DMA commands: When a CRC error is
detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2
in the Error register) to one. ICRC is defined as the "Interface CRC Error"
bit. The host shall respond to this error by re-issuing the command.
h) A host may send extra data words on the last Ultra DMA burst of a data out
command. If a device determines that all data has been transferred for a
command, the device shall terminate the burst. A device may have already
received more data words than were required for the command. These extra
words are used by both the host and the device to calculate the CRC, but, on
an Ultra DMA data out burst, the extra words shall be discarded by the
device.
i) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.
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Note: Since no bit clock is available, the recommended approach for
calculating CRC is to use a word clock derived from the bus strobe. The
combinational logic shall then be equivalent to shifting sixteen bits serially
through the generator polynomial where DD0 is shifted in first and DD15 is
shifted in last.
CRCOUT
16
DD0–DD15
16
CRCIN
F1–f16
Latch
16
Combination
logic
Word
clock
16
Figure 5.8 An example of generation of parallel CRC
Table 5.16 Parallel generation equation of CRC polynomial
CRCINO=f16
CRCIN8 = f8 XOR f13
CRCIN1=f15
CRCIN9 = f7 XOR f12
CRCIN2=f14
CRCIN10 = f6 XOR f11
CRCIN3=f13
CRCIN11 = f5 XOR f10
CRCIN4=f12
CRCIN12 = f4 XOR f9 XOR f16
CRCIN13 = f3 XOR f8 XOR f15
CRCIN14 = f2 XOR f7 XOR f14
CRCIN15 = f1 XOR f6 XOR f13
CRCIN5=f11 XOR f
CRCIN6=f10 XOR f15
CRCIN7=f9 XOR f14
f1 = DD0 XOR CRCOUT15
f2 = DD1 XOR CRCOUT14
f3 = DD2 XOR CRCOUT13
f4 = DD3 XOR CRCOUT12
f9 = DD8 XOR CRCOUT7 XOR f5
f10 = DD9 XOR CRCOUT6 XOR f6
f11 = DD10 XOR CRCOUT5 XOR f7
f12 = DD11 XOR CRCOUT4 XOR f1 XOR f8
f5 = DD4 XOR CRCOUT11 XOR f1 f13 = DD12 XOR CRCOUT3 XOR f2 XOR f9
f6 = DD5 XOR CRCOUT10 XOR f2 f14 = DD13 XOR CRCOUT2 XOR f3 XOR f10
f7 = DD6 XOR CRCOUT9 XOR f3 f15 = DD14 XOR CRCOUT1 XOR f4 XOR f11
f8 = DD7 XOR CRCOUT8 XOR f4 f16 = DD15 XOR CRCOUT0 XOR f5 XOR f12
DD :
Data from bust
f : Feedback
CRCIN : Output of combination logic (the next CRC)
CROUT : Result of 16 bit latch (current CRC)
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5.5.6 Series termination required for Ultra DMA
Series termination resistors are required at both the host and the device for
operation in any of the Ultra DMA Modes. The following table describes
recommended values for series termination at the host and the device.
Table 5.17 Recommended series termination for Ultra DMA
Signal
Host Termination
Device Termination
DIOR-:HDMARDY-:HSTROBE
DIOW-:STOP
22 Ω
22 Ω
33 Ω
33 Ω
22 Ω
33 Ω
82 Ω
82 Ω
82 Ω
82 Ω
82 Ω
CS0-, CS1-
82 Ω
DA0, DA1, DA2
DMACK-
82 Ω
82 Ω
DD15 through DD0
DMARQ
120 Ω (100 MHz)
22 Ω
INTRQ
22 Ω
IORDY:DDMARDY-:DSTROBE
22 Ω
Note: Only those signals requiring termination are listed in this table. If a signal is
not listed, series termination is not required for operation in an Ultra DMA Mode.
For signals also requiring a pull-up or pull-down resistor at the host see Figure 5.9.
Vcc
DMARQ
IORDY
Figure 5.9 Ultra DMA termination with pull-up or pull-down
Configuration of cable
For the configuration of the cable (common use of primary port and secondary
port), DMACK signal should not be used in common. It is not recommended to
use DIOR-, DIOW- and IORDY signal in common.
5-106
C141-E104-02EN
5.6 Timing
5.6 Timing
5.6.1 PIO data transfer
Figure 5.10 shows of the data transfer timing between the device and the host
system.
C141-E104-02EN
5-107
Interface
Figure 5.10 Data transfer timing
5-108
C141-E104-02EN
5.6 Timing
5.6.2 Multiword DMA data transfer
Figure 5.11 shows the multiword DMA data transfer timing between the device
and the host system.
Delay time from DIOR-/DIOW- assertion to DMARQ negation
Figure 5.11 Multiword DMA data transfer timing (mode 2)
C141-E104-02EN
5-109
Interface
5.6.3 Transfer of Ultra DMA data
Figures 5.12 to 5.21 define the timings concerning every phase for the Ultra DMA
Burst.
Table 5.18 includes the timing for each Ultra DMA mode.
5.6.3.1 Starting of Ultra DMA data In Burst
The timing for each Ultra DMA mode is included in 5.6.3.2.
DMARQ
(device)
tUI
DMACK-
(host)
tFS
tACK
tENV
tZAD
STOP
(host)
tACK
tENV
tFS
HDMARDY-
(host)
tZAD
tZIORDY
DSTROBE
(device)
tAZ
tVDS
tDVH
DD (15:0)
tACK
DA0,DA1,DA2,
CS0-,CS1-
Note :
The definitions of STOP, HDMARDY- and DSTROBE signals are
valid before the assertion of DMACK signal.
Figure 5.12 Starting of Ultra DMA data In Burst transfer
5-110
C141-E104-02EN
5.6 Timing
5.6.3.2 Ultra DMA data burst timing requirements
Table 5.18 Ultra DMA data burst timing requirements (1 of 2)
NAME
MODE 0
(in ns)
MODE 1
(in ns)
MODE 2
(in ns)
MODE 3
(in ns)
MODE 4
(in ns)
COMMENT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (see Notes 1 and 2)
t2CYCTYP
tCYC
240
160
120
90
60
Typical sustained average two cycle
time
112
73
54
39
25
Cycle time allowing for asymmetry
and clock variations (from
STROBE edge to STROBE edge)
t2CYC
230
154
115
86
57
Two cycle time allowing for clock
variations (from rising edge to next
rising edge or from falling edge to
next falling edge of STROBE)
tDS
15
5
10
5
7
5
7
5
5
5
6
Data setup time (at recipient)
(see Note 4)
tDH
tDVS
Data hold time (at recipient)
(see Note 4)
70
48
30
20
Data valid setup time at sender (from
data valid until STROBE edge)
(see Note 5)
tDVH
6
0
6
0
6
0
6
0
6
0
Data valid hold time at sender (from
STROBE edge until data may
become invalid) (see Note 5)
tFS
230
150
200
150
170
150
130
100
120 First STROBE time (for device to
first negate DSTROBE from STOP
during a data in burst)
tLI
0
0
0
0
0
100 Limited interlock time (see Note 3)
tMLI
20
20
20
20
20
Interlock time with minimum
(see Note 3)
tUI
0
0
0
0
0
Unlimited interlock time (see Note 3)
tAZ
10
10
10
10
10
Maximum time allowed for output
drivers to release (from asserted or
negated)
tZAH
tZAD
tENV
20
0
20
0
20
0
20
0
20
0
Minimum delay time required
for output
Drivers to assert or negate (from
released)
20
70
50
75
20
70
30
70
20
70
20
60
20
55
NA
60
20
55
Envelope time (from DMACK- to
STOP and HDMARDY- during
data in burst initiation and from
DMACK to STOP during data out
burst initiation)
tSR
NA STROBE-to-DMARDY-time (if
DMARDY- is negated before this long
after STROBE edge, the recipient shall
receive no more than one additional
data word)
tRFS
60
Ready-to-Final-STROBE time
(After negating DMARDY-,
STROBE edges should not be sent
beyond this period)
tRP
160
125
100
100
100
Ready-to-pause time (that recipient
shall wait to pause after negating
DMARDY-)
tIORDYZ
20
20
20
20
20
MaximumtimebeforereleasingIORDY
C141-E104-02EN
5-111
Interface
Table 5.18 Ultra DMA data burst timing requirements (2 of 2)
NAME
MODE 0
(in ns)
MODE 1
(in ns)
MODE 2
(in ns)
MODE 3
(in ns)
MODE 4
(in ns)
COMMENT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (see Notes 1 and 2)
tZIORDY
tACK
tSS
0
0
0
0
0
Minimum time before driving
IORDY
20
50
20
50
20
50
20
50
20
50
Setup and hold times for DMACK-
(before assertion or negation)
Time from STROBE edge to
negation of DMARQ or assertion of
STOP (when sender terminates a
burst)
Notes:
1) Unless otherwise specified, timing parameters shall be measured at the connector of the sender or receiver to which the parameter
applies (see Note 5 for exceptions). For example, the sender shall stop generating STROBE edges tRFS after the negation of
DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the connector of the sender.
2) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
3)
tUI, tMLI and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for
the other agent to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a
limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum.
4) Special cabling shall be required in order to meet data setup (tDS) and data hold (tDH) times in modes 3 and 4.
5) Timing for tDVS and tDVH shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.
5-112
C141-E104-02EN
5.6 Timing
5.6.3.3 Sustained Ultra DMA data in burst
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
t2CYC
tCYC
tCYC
t2CYC
DSTROBE
at device
tDVH
tDVH
tDVH
tDVS
tDVS
DD(15:0)
at device
DSTROBE
at host
tDH
tDS
tDS
tDH
tDH
DD(15:0)
at host
Note:
DD (15:0) and DSTROBE are shown at both the host and the device
to emphasize that cable setting time as well as cable propagation
delay shall not allow the data signals to be considered stable at the
host until some time after they are driven by the device.
Figure 5.13 Sustained Ultra DMA data in burst
C141-E104-02EN
5-113
Interface
5.6.3.4 Host pausing an Ultra DMA data in burst
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
DMARQ
(device)
DMACK-
(host)
tRP
STOP
(host)
tSR
HDMARDY-
(host)
tRFS
DSTROBE
(device)
DD(15:0)
(device)
Notes:
1) The host may assert STOP to request termination of the Ultra DMA
burst no sooner than tRP after HDMARDY- is negated.
2) If the tSR timing is not satisfied, the host may receive zero, one or
two more data words from the device.
Figure 5.14 Host pausing an Ultra DMA data in burst
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5.6 Timing
5.6.3.5 Device terminating an Ultra DMA data in burst
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
DMARQ
(device)
tMLI
DMACK-
(host)
tACK
tLI
tLI
STOP
(host)
tACK
tLI
HDMARDY-
(host)
tSS
tIORDYZ
DSTROBE
(device)
tZAH
tAZ
tDVS
tDVH
DD(15:0)
CRC
tACK
DA0, DA1, DA2,
CS0-, CS1-
Note:
The definitions for the STOP, HDMARDY- and DSTROBE signal
lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 5.15 Device terminating an Ultra DMA data in burst
C141-E104-02EN
5-115
Interface
5.6.3.6 Host terminating an Ultra DMA data in burst
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
DMARQ
(device)
tLI
tMLI
DMACK-
(host)
tZAH
tACK
tAZ
tRP
STOP
(host)
tACK
HDMARDY-
(host)
tRFS
tMLI
tLI
tIORDYZ
DSTROBE
(device)
tDVS tDVH
CRC
DD(15:0)
tACK
DA0, DA1, DA2,
CS0, CS1
Note:
The definitions for the STOP, HDMARDY- and DSTROBE signal
lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 5.16 Host terminating an Ultra DMA data in burst
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C141-E104-02EN
5.6 Timing
5.6.3.7 Initiating an Ultra DMA data out burst
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
DMARQ
(device)
tUI
DMACK-
(host)
tENV
tACK
STOP
(host)
tLI
tUI
tZIORDY
DDMARDY-
(device)
tACK
HSTROBE
(host)
tDVS
tDVH
DD(15:0)
(host)
tACK
DA0, DA1, DA2
CS0-, CS1-
Note:
The definitions for the STOP, DDMARDY- and HSTROBE signal
lines are not in effect until DMARQ and DMACK are asserted.
Figure 5.17 Initiating an Ultra DMA data out burst
C141-E104-02EN
5-117
Interface
5.6.3.8 Sustained Ultra DMA data out burst
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
t2CYC
tCYC
tCYC
t2CYC
HSTROBE
at host
tDVH
tDVS
tDVH
tDVS
tDVH
DD(15:0)
at host
HSTROBE
at device
tDS
tDH
tDS
tDH
tDH
DD(15:0)
at device
Note:
DD (15:0) and HSTROBE signals are shown at both the device and
the host to emphasize that cable setting time as well as cable
propagation delay shall not allow the data signals to be considered
stable at the device until some time after they are driven by the host.
Figure 5.18 Sustained Ultra DMA data out burst
5-118
C141-E104-02EN
5.6 Timing
5.6.3.9 Device pausing an Ultra DMA data out burst
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
tRP
DMARQ
(device)
DMACK-
(host)
STOP
(host)
tSR
DDMARDY-
(device)
tRFS
HSTROBE
(host)
DD(15:0)
(host)
Notes:
1) The device may negate DMARQ to request termination of the Ultra
DMA burst no sooner than tRP after DDMARDY- is negated.
2) If the tSR timing is not satisfied, the device may receive zero, one or
two more data words from the host.
Figure 5.19 Device pausing an Ultra DMA data out burst
C141-E104-02EN
5-119
Interface
5.6.3.10 Host terminating an Ultra DMA data out burst
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
tLI
DMARQ
(device)
tMLI
DMACK-
(host)
tLI
tACK
tSS
STOP
(host)
tLI
tIORDYZ
DDMARDY-
(device)
tACK
HSTROBE
(host)
tDVS
tDVH
DD(15:0)
(host)
CRC
tACK
DA0, DA1, DA2
CS0-, CS1-
Note:
The definitions for the STOP, DDMARDY- and HSTROBE signal
lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 5.20 Host terminating an Ultra DMA data out burst
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C141-E104-02EN
5.6 Timing
5.6.3.11 Device terminating an Ultra DMA data in burst
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
DMARQ
(device)
DMACK-
(host)
tACK
tLI
tMLI
STOP
(host)
tRP
tIORDYZ
DDMARDY-
(device)
tRFS
tACK
tLI
tMLI
HSTROBE
(host)
tDVS
tDVS
DD(15:0)
(host)
CRC
tACK
DA0, DA1, DA2,
CS0-, CS1-
Note:
The definitions for the STOP, DDMARDY- and HSTROBE signal
lines are no longer in effect after DMARQ and DMACK are
negated.
Figure 5.21 Device terminating an Ultra DMA data out burst
C141-E104-02EN
5-121
Interface
5.6.4 Power-on and reset
Figure 5.22 shows power-on and reset (hardware and software reset) timing.
(1) Only master device is present
Power-on Reset
RESET–
(2) Master and slave devices are present (2-drives configuration)
PDIAG- negation
31
Figure 5.22 Power on Reset Timing
5-122
C141-E104-02EN
CHAPTER 6 Operations
6.1 Device Response to the Reset
6.2 Address Translation
6.3 Power Save
6.4 Defect Management
6.5 Read-Ahead Cache
6.6 Write Cache
C141-E104-02EN
6-1
Operations
6.1 Device Response to the Reset
This section describes how the PDIAG- and DASP- signals responds when the
power of the IDD is turned on or the IDD receives a reset or diagnostic command.
6.1.1 Response to power-on
After the master device (device 0) releases its own power-on reset state, the
master device shall check a DASP- signal for up to 450 ms to confirm presence of
a slave device (device 1). The master device recognizes presence of the slave
device when it confirms assertion of the DASP- signal. Then, the master device
checks a PDIAG- signal to see if the slave device has successfully completed the
power-on diagnostics.
If the master device cannot confirm assertion of the DASP- signal within 450 ms,
the master device recognizes that no slave device is connected.
After the slave device (device 1) releases its own power-on reset state, the slave
device shall report its presence and the result of power-on diagnostics to the
master device as described below:
DASP- signal: Asserted within 400 ms.
PDIAG- signal: Negated within 1 ms and asserted within 30 seconds.
6-2
C141-E104-02EN
6.1 Device Response to the Reset
Power on
Master device
Power On Reset-
Status Reg.
BSY bit
Max. 31 sec.
Checks DASP- for up to
450 ms.
If presence of a slave device is
confirmed, PDIAG- is checked for
up to 31 seconds.
Slave device
Power On Reset-
BSY bit
Max. 1 ms.
PDIAG-
DASP-
Max. 30 sec.
Max. 400 ms.
Figure 6.1 Response to power-on
C141-E104-02EN
6-3
Operations
6.1.2 Response to hardware reset
Response to RESET- (hardware reset through the interface) is similar to the
power-on reset.
Upon receipt of hardware reset, the master device checks a DASP- signal for up to
450 ms to confirm presence of a slave device. The master device recognizes the
presence of the slave device when it confirms assertion of the DASP- signal.
Then the master device checks a PDIAG- signal to see if the slave device has
successfully completed the self-diagnostics.
If the master device cannot confirm assertion of the DASP- signal within 450 ms,
the master device recognizes that no slave device is connected.
After the slave device receives the hardware reset, the slave device shall report its
presence and the result of the self-diagnostics to the master device as described
below:
DASP- signal: Asserted within 400 ms.
PDIAG- signal: Negated within 1 ms and asserted within 30 seconds.
Reset-
Master device
Status Reg.
BSY bit
Max. 31 sec.
If presence of a slave device is
Checks DASP- for up to
450 ms.
confirmed, PDIAG- is checked for
up to 31 seconds.
Slave device
BSY bit
Max. 1 ms.
PDIAG-
DASP-
Max. 30 sec.
Max. 400 ms.
.
Figure 6.2 Response to hardware reset
6-4
C141-E104-02EN
6.1 Device Response to the Reset
6.1.3 Response to software reset
The master device does not check the DASP- signal for a software reset. If a
slave device is present, the master device checks the PDIAG- signal for up to 15
seconds to see if the slave device has completed the self-diagnosis successfully.
After the slave device receives the software reset, the slave device shall report its
presence and the result of the self-diagnostics to the master device as described
below:
PDIAG- signal: negated within 1 ms and asserted within 30 seconds
When the IDD is set to a slave device, the IDD asserts the DASP- signal when
negating the PDIAG- signal, and negates the DASP- signal when asserting the
PDIAG- signal.
X'3F6' Reg.
X"0C"
X"00"
or X"04"
Master device
Status Reg.
BSY bit
Max. 31 sec.
If the slave device is preset, PDIAG- is checked for
up to 31 seconds.
Slave device
BSY bit
Max. 1 ms.
PDIAG-
DASP-
Max. 30 sec.
Figure 6.3 Response to software reset
C141-E104-02EN
6-5
Operations
6.1.4 Response to diagnostic command
When the master device receives an EXECUTE DEVICE DIAGNOSTIC
command and the slave device is present, the master device checks the PDIAG-
signal for up to 6 seconds to see if the slave device has completed the self-
diagnosis successfully.
The master device does not check the DASP- signal.
After the slave device receives the EXECUTE DEVICE DIAGNOSTIC
command, it shall report the result of the self-diagnostics to the master device as
described below:
PDIAG- signal: negated within 1 ms and asserted within 5 seconds
When the IDD is set to a slave device, the IDD asserts the DASP- signal when
negating the PDIAG- signal, and negates the DASP- signal when asserting the
PDIAG- signal.
X'1F7' Reg.
Write
Master device
Status Reg.
BSY bit
Max. 6 sec.
If the slave device is preset, PDIAG- signal is checked for
up to6 seconds.
Slave device
BSY bit
Max. 1 ms.
PDIAG-
DASP-
Max. 5 sec.
Figure 6.4 Response to diagnostic command
6-6
C141-E104-02EN
6.2 Address Translation
6.2 Address Translation
When the IDD receives any command which involves access to the disk medium,
the IDD always implements the address translation from the logical address (a
host-specified address) to the physical address (logical to physical address
translation).
Following subsections explains the CHS translation mode.
6.2.1 Default parameters
In the logical to physical address translation, the logical cylinder, head, and sector
addresses are translated to the physical cylinder, head, and sector addresses based
on the number of heads and the number of sectors per track which are specified
with an INITIALIZE DEVICE PARAMETERS command. This is called as the
current translation mode.
If the number of heads and the number of sectors are not specified with an
INITIALIZE DEVICE PARAMETERS command, the default values listed in
Table 6.1 are used. This is called the default translation mode. The parameters in
Table 6.1 are called BIOS specification.
Table 6.1 Default parameters
MHL2300AT
16,383
16
MHM2200AT MHM2150AT MHM2100AT
Number of cylinders
Number of heads
16,383
16
16,383
16
16,383
16
Parameters
(logical)
Number of sectors/track
63
63
63
63
Formatted capacity (MB)
30,005.82
20,003.88
15,103.03
10,056.13
As long as the formatted capacity of the IDD does not exceed the value shown on
Table 6.1, the host can freely specify the number of cylinders, heads, and sectors
per track.
Generally, the device recognizes the number of heads and sectors per track with
the INITIALIZE DEVICE PARAMETER command. However, it cannot
recognize the number of cylinders. In other words, there is no way for the device
to recognize a host access area on logical cylinders. Thus the host should manage
cylinder access to the device.
The host can specify a logical address freely within an area where an address can
be specified (within the specified number of cylinders, heads, and sectors per
track) in the current translation mode.
The host can read an addressable parameter information from the device by the
IDENTIFY DEVICE command (Words 54 to 56).
C141-E104-02EN
6-7
Operations
6.2.2 Logical address
(1) CHS mode
Logical address assignment starts from physical cylinder (PC) 0, physical head
(PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of
sectors per track that is specified by the INITIALIZE DEVICE PARAMETERS
command. If the last sector of a physical track is used, the track is switched and
the next logical sector is placed in the initial sector of the subsequent physical
track.
Figure 6.5 shows an example of 6 heads configuration. (assuming there is no track
skew).
Physical sector
1
2
3
62 63 64
126 127
504 505 506
Physical cylinder 0
Physical head 0
LS
63
LS
LS1
63
LS
LS1
LS1 LS2
63
LH0
LH8
LH1
LH9
LH8
Physical sector
1
2
61 62
LS
Physical cylinder 1
Physical head 0
LS3LS4
LS1LS2
63
ex: Zone 0 in 6-head device
Physical parameter
– Physical head: 0 to 5
– Physical sector: 1 to 506
Specification of INITIALIZE DEVICE PARAMETERS command
– Logical head: 0 to 15
– Logical sector: 1 to 63
Figure 6.5 Address translation (example in CHS mode)
6-8
C141-E104-02EN
6.3 Power Save
(2) LBA mode
Logical address assignment in the LBA mode starts from physical cylinder 0,
physical head 0, and physical sector 1. If the last sector of a physical track is
used, the track is switched and the next LBA is assigned to the initial sector of the
subsequent physical track.
Figure 6.6 shows an example of 4 heads configuration (assuming there is no track
skew).
626
627
625
626
626
627
627
628
629
1252 1253
6
5
627
Figure 6.6 Address translation (example in LBA mode)
6.3 Power Save
The host can change the power consumption state of the device by issuing a
power command to the device.
6.3.1 Power save mode
There are four types of power consumption state of the device including active
mode where all circuits are active.
In the power save mode, power supplying to the part of the circuit is turned off.
There are three types of power save modes:
•
•
•
Idle mode
Standby mode
Sleep mode
C141-E104-02EN
6-9
Operations
The drive moves from the Active mode to the idle mode by itself.
Regardless of whether the power down is enabled, the device enters the idle
mode. The device also enters the idle mode in the same way after power-on
sequence is completed.
And, the automatic power-down is executed if no command is coming for 30 min.
(default)
(1) Active mode
In this mode, all the electric circuit in the device are active or the device is under
seek, read or write operation.
A device enters the active mode under the following conditions:
•
•
A command other than power commands is issued.
A reset command is received.
(2) Idle mode
In this mode, circuits on the device is set to power save mode.
The device enters the Idle mode under the following conditions:
•
•
After completion of power-on sequence.
After completion of the command execution other than SLEEP and STANDBY
commands.
•
After completion of the reset sequence
(3) Standby mode
In this mode, the VCM circuit is turned off and the spindle motor is stopped.
The device can receive commands through the interface. However if a command
with disk access is issued, response time to the command under the standby mode
takes longer than the active or Idle mode because the access to the disk medium
cannot be made immediately.
The drive enters the standby mode under the following conditions:
•
A STANDBY or STANDBY IMMEDIATE command is issued in the active
or idle mode.
•
•
When automatic power down sequence is enabled, the timer has elapsed.
A reset is issued in the sleep mode.
6-10
C141-E104-02EN
6.4 Defect Management
When one of following commands is issued, the command is executed normally
and the device is still stayed in the standby mode.
•
•
•
•
•
Reset (hardware or software)
STANDBY command
STANDBY IMMEDIATE command
INITIALIZE DEVICE PARAMETERS command
CHECK POWER MODE command
(4) Sleep mode
The power consumption of the drive is minimal in this mode. The drive enters
only the standby mode from the sleep mode. The only method to return from the
standby mode is to execute a software or hardware reset.
The drive enters the sleep mode under the following condition:
•
A SLEEP command is issued.
Issued commands are invalid (ignored) in this mode.
6.3.2 Power commands
The following commands are available as power commands.
•
IDLE
IDLE IMMEDIATE
•
•
•
•
•
STANDBY
STANDBY IMMEDIATE
SLEEP
CHECK POWER MODE
6.4 Defect Management
Defective sectors of which the medium defect location is registered in the system
space are replaced with spare sectors in the formatting at the factory shipment.
All the user space area are formatted at shipment from the factory based on the
default parameters listed in Table 6.1.
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Operations
6.4.1 Spare area
Following two types of spare area are provided for every physical head.
1) Spare cylinder for sector slip:
used for alternating defective sectors at formatting in shipment (4 cylinders)
2) Spare cylinder for alternative assignment:
used for automatic alternative assignment at read error occurrence.
(4 cylinders)
6.4.2 Alternating defective sectors
The two alternating methods described below are available:
(1) Sector slip processing
A defective sector is not used and is skipped and a logical sector address is
assigned to the subsequent normal sector (physically adjacent sector to the
defective sector).
When defective sector is present, the sector slip processing is performed in the
formatting.
Figure 6.7 shows an example where (physical) sector 5 is defective on head 0 in
cylinder 0.
504
505
506
1
1
2
3
3
4
4
5
6
5
7
6
8
7
2
(unused)
503504505
Note:
If an access request to physical sector 5 is specified, the device
accesses physical sector 6 instead of sector 5.
Figure 6.7 Sector slip processing
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6.4 Defect Management
(2) Alternate cylinder assignment
A defective sector is assigned to the spare sector in the alternate cylinder.
This processing is performed when the alternate assignment is specified in the
FORMAT TRACK command or when the automatic alternate processing is
performed at read error occurrence.
Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in
cylinder 0.
Index
Sector (Physical)
1
2
3
4
4
5
6
6
7
7
505
505
506
506
Cylinder 0
Head 0
Defective
sector
1
2
3
(unused)
Sector (Logical)
Alternate
cylinder
Already
assigned
Head 0
Defective sector is assigned to unassigned sector.
Notes:
1) 4 alternate cylinders are provided for each head in zone 14 (inner
side).
2) When an access request to physical sector 5 is specified, the device
accesses the alternated sector in the alternate cylinder instead of
sector 5. When an access request to sectors next to sector 5 is
specified, the device seeks to cylinder 0, head 0, and continues the
processing.
Figure 6.8 Alternate cylinder assignment
(3) Automatic alternate assignment
The device performs the automatic alternate assignment when ECC correction
performance is increased during read error retry, a read error is recovered. Before
automatic alternate assignment, the device performs rewriting the corrected data
to the erred sector and rereading. If no error occurs at rereading, the automatic
alternate assignment is not performed.
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Operations
An unrecoverable write error occurs during write error retry, automatic alternate
assignment is performed.
6.5 Read-Ahead Cache
After read command which involves read data from the disk medium is
completed, the read-ahead cache function reads the subsequent data blocks
automatically and stores the data to the data buffer.
When the next command requests to read the read-ahead data, the data can be
transferred from the data buffer without accessing the disk medium. The host can
thus access data at higher speed.
6.5.1 Data buffer configuration
The drive has a 2 MB data buffer. The buffer is used by divided into three parts;
for read commands, for write commands, and for MPU work (see Figure 6.9).
2 MB (2,097,152 bytes)
for read commands
for write commands
for MPU work
65,536 bytes
1,048,576 bytes (2048 sector)
983,040 bytes (1920 sector)
Figure 6.9 Data buffer configuration
The read-ahead operation is performed at execution of the READ SECTOR(S),
READ MULTIPLE, or READ DMA command, and read-ahead data is stored in
the buffer for read commands.
6.5.2 Caching operation
Caching operation is performed only at issuance of the following commands. The
device transfers data from the data buffer to the host system at issuance of
following command if following data exist in the data buffer.
•
•
All sectors to be processed by the command
A part of data including load sector to be processed by the command
When a part of data to be processed exist in the data buffer, remaining data are
read from the medium and are transferred to the host system.
(1) Commands that are object of caching operation
Follow commands are object of caching operation.
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6.5 Read-Ahead Cache
•
•
•
READ SECTOR (S)
READ MULTIPLE
READ DMA
When caching operation is disabled by the SET FEATURES command, no
caching operation is performed.
(2) Data that are object of caching operation
Follow data are object of caching operation.
1) Read-ahead data read from the medium to the data buffer after completion of
the command that are object of caching operation.
2) Data transferred to the host system once by requesting with the command that
are object of caching operation (except for the cache invalid data by some
reasons).
3) Remaining data in the data buffer (for write command) transferred from the
host system by the command that writes data onto the disk medium, such as
the WRITE SECTOR (S), WRITE DMA, WRITE MULTIPLE.
Followings are definition of in case that the write data is treated as a cache data.
However, since the hit check at issuance of read command is performed to the
data buffer for read command preferentially, caching write data is limited to the
case that the hit check is missed at the data buffer for read command.
•
When all data requested by the read command are stored in the data buffer for
write command (hit all), the device transfers data from the data buffer for
write command. At this time, the read-ahead operation to the data subsequent
to the requested data is not performed.
•
Even if a part of data requested by the read command are stored in the data
buffer for write command (hit partially), all data are read from the disk
medium without transferring from the data buffer for write command.
(3) Invalidating caching data
Caching data in the data buffer is invalidated in the following case.
1) Following command is issued to the same data block as caching data.
−
−
−
WRITE SECTOR(S)
WRITE DMA
WRITE MULTIPLE
2) Command other than following commands is issued (all caching data are
invalidated)
−
−
READ SECTOR (S)
READ DMA
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Operations
−
−
−
−
READ MULTIPLE
WRITE SECTOR(S)
WRITE MULTIPLE
WRITE VERIFY SECTOR(S)
3) Caching operation is inhibited by the SET FEATURES command.
4) Issued command is terminated with an error.
5) Soft reset or hard reset occurs, or power is turned off.
6) The device enters the sleep mode.
7) Under the state that the write data is kept in the data buffer for write
command as a caching data, new write command is issued. (write data kept
until now are invalidated)
6.5.3 Usage of read segment
This subsection explains the usage of the read segment buffer at following cases.
6.5.3.1 Mis-hit (no hit)
A lead block of the read-requested data is not stored in the data buffer. The
requested data is read from the disk media.
The read-ahead operation is performed only when the last sector address of the
previous read command and the lead sector address of this read command is
sequential (see item (2)).
1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the
lead of segment.
HAP
DAP
Segment only for read
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6.5 Read-Ahead Cache
2) Transfers the requested data that already read to the host system with reading
the requested data from the disk media.
Stores the read-requested
data upto this point
HAP
Empty area
Read-requested data
DAP
3) After reading the requested data and transferring the requested data to the
host system had been completed, the disk drive stops command execution
without performing the read-ahead operation.
HAP
(stopped)
Empty area
Read-requested data
(stopped)
DAP
4) Following shows the cache enabled data for next read command.
Empty area
Cache enabled data
Start LBA
6.5.3.2 Sequential read
Last LBA
When the disk drive receives the read command that targets the sequential address
to the previous read command, the disk drive starts the read-ahead operation.
a. Sequential command just after non-sequential command
When the previously executed read command is an non-sequential
command and the last sector address of the previous read command is
sequential to the lead sector address of the received read command, the
disk drive assumes the received command is a sequential command and
performs the read-ahead operation after reading the requested data.
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Operations
1) At receiving the sequential read command, the disk drive sets the DAP and
HAP to the start address of the segment and reads the requested data from the
load of the segment.
HAP
DAP
Mis-hit data
Empty area
2) The disk drive transfers the requested data that is already read to the host
system with reading the requested data.
HAP
Requested data
Mis-hit data
Empty area
DAP
3) After completion of the reading and transferring the requested data to the host
system, the disk drive performs the read-ahead operation continuously.
HAP (Completion of transferring requested data)
Requested data
Empty area
Read-ahead data
DAP
4) The disk drive performs the read-ahead operation for all area of segment with
overwriting the requested data. Finally, the cache data in the buffer is as
follows.
HAP
Read-ahead data
DAP
Last LBA Start LBA
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6.5 Read-Ahead Cache
b. Sequential hit
When the previously executed read command is the sequential command
and the last sector address of the previous read command is sequential to
the lead sector address of the received read command, the disk drive
transfers the hit data in the buffer to the host system.
The disk drive performs the read-ahead operation of the new continuous
data to the empty area that becomes vacant by data transfer at the same
time as the disk drive starts transferring data to the host system.
1) In the case that the contents of buffer is as follows at receiving a read
command;
HAP (Continued from the previous read request data)
Read-ahead data
Hit data
DAP
Last LBA Start LBA
2) The disk drive starts the read-ahead operation to the empty area that becomes
vacant by data transfer at the same time as the disk drive starts transferring hit
data.
HAP
Read-ahead data
New read-ahead data
Hit data
DAP
3) After completion of data transfer of hit data, the disk drive performs the read-
ahead operation for the data area of which the disk drive transferred hit data.
HAP
DAP
Read-ahead data
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Operations
4) Finally, the cache data in the buffer is as follows.
Read-ahead data
Start LBA
Last LBA
c. Non-sequential command immediately after sequential command
When a sequential read command (first read) has been executed, the first
read operation should be stopped if a non-sequential read command has
been received and then, ten or more of the non-sequential read
commands have been received. (Refer to 6.5.3.1.)
The figure that describes the first read operation is the same as that
shown in the sub-section a.
6.5.3.3 Full hit (hit all)
All requested data are stored in the data buffer. The disk drive starts transferring
the requested data from the address of which the requested data is stored. After
completion of command, a previously existed cache data before the full hit
reading are still kept in the buffer, and the disk drive does not perform the read-
ahead operation.
1) In the case that the contents of the data buffer is as follows for example and
the previous command is a sequential read command, the disk drive sets the
HAP to the address of which the hit data is stored.
Last position at previous read command
HAP (set to hit position for data transfer)
HAP
Cache data
Full hit data
Cache data
DAP
Last position at previous read command
0
2) The disk drive transfers the requested data but does not perform the read-
ahead operation.
HAP
(stopped)
Cache data
Full hit data
Cache data
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6.5 Read-Ahead Cache
3) The cache data for next read command is as follows.
Cache data
Start LBA
Last LBA
6.5.3.4 Partially hit
A part of requested data including a lead sector are stored in the data buffer. The
disk drive starts the data transfer from the address of the hit data corresponding to
the lead sector of the requested data, and reads remaining requested data from the
disk media directly. The disk drive does not perform the read-ahead operation
after data transfer.
Following is an example of partially hit to the cache data.
Cache data
Last LBA
Start LBA
1) The disk drive sets the HAP to the address where the partially hit data is
stored, and sets the DAP to the address just after the partially hit data.
HAP
Partially hit data
Lack data
DAP
2) The disk drive starts transferring partially hit data and reads lack data from
the disk media at the same time. However, the disk drive does not perform
the read-ahead operation newly.
HAP
(stopped)
Requested data to be transferred
Partially hit data
Lack data
DAP
(stopped)
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Operations
3) The cache data for next read command is as follows.
Cache data
Start LBA
Last LBA
6.6 Write Cache
The write cache function of the drive makes a high speed processing in the case
that data to be written by a write command is physically sequent the data of
previous command and random write operation is performed.
When the drive receives a write command, the drive starts transferring data of
sectors requested by the host system and writing on the disk medium. After
transferring data of sectors requested by the host system, the drive generates the
interrupt of command complete. Also, the drive sets the normal end status in the
Status register.
The drive continues writing data on the disk medium. When all data requested by
the host are written on the disk medium, actual write operation is completed.
The drive receives the next command continuously. If the received command is a
“sequential write” (data to be written by a command is physically sequent to data
of previous command), the drive starts data transfer and receives data of sectors
requested by the host system. At this time, if the write operation of the previous
command is still been executed, the drive continuously executes the write
operation of the next command from the sector next to the last sector of the
previous write operation. Thus, the latency time for detecting a target sector of
the next command is eliminated. This shortens the access time.
The drive generates an interrupt of command complete after completion of data
transfer requested by the host system as same as at previous command.
When the write operation of the previous command had been completed, the
latency time occurs to search the target sector.
If the received command is not a “sequential write”, the drive receives data of sectors
requested by the host system as same as “sequential write”. The drive generates the
interrupt of command complete after completion of data transfer requested by the host
system. Received data is processed after completion of the write operation to the disk
medium of the previous command.
Even if a hard reset or soft reset is received or the write cache function is disabled
by the SET FEATURES command during unwritten data is kept, the instruction is
not enabled until remaining unwritten data is written onto the disk medium.
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C141-E104-02EN
6.6 Write Cache
The drive uses a cache data of the last write command as a read cache data. When
a read command is issued to the same address after the write command (cache
hit), the read operation to the disk medium is not performed.
If an error occurs during the write operation, the device retries the processing. If the
error cannot be recovered by retry, automatic alternate assignment is performed. For
details about automate alternate assignment, see item (3) of Section 6.4.2.
The write cache function is operated with the following command.
•
•
•
WRITE SECTOR(S)
WRITE MULTIPLE
WRITE DMA
IMPORTANT
When Write Cache is permitted, the writing of the data transferred
from the host by the above mentioned Write Cache permit
command into the disk medium may not be completed at the
moment a normal ending interrupt has occurred.
In case a non-recoverable error has occurred during receiving more
than one write command, it is difficult for the host to identify a
command that caused the error.
(However, the error is not reported to the hose if an error at writing
has been processed normally.)
Therefore, note that it is difficult for the host to retry an operation
that caused a non-recoverable error.
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6-23
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Glossary
Actuator
AT bus
Head positioning assembly. The actuator consists of a voice coil motor and head
arm. If positions the read-write (R-W) head.
A bus between the host CPU and adapter board
ATA (AT Attachment) standard
The ATA standard is for a PC AT interface regulated to establish compatibility
between products manufactured by different vendors. Interfaces based on this
standard are called ATA interfaces.
BIOS standard for drives
The BIOS standard collectively refers to the parameters defined by the host,
which, for example, include the number of cylinders, the number of heads, and the
number of sectors per track in the drive. The physical specifications of the drive
do not always correspond to these parameters.
The BIOS of a PC AT cannot make full use of the physical specifications of these
drivers. To make the best use of these drives, a BIOS that can handle the standard
parameters of these drives is required.
Command
Data block
DE
Commands are instructions to input data to and output data from a drive.
Commands are written in command registers.
A data block is the unit used to transfer data. A data block normally indicates a
single sector.
Disk enclosure. The DE includes the disks, built-in spindle motor, actuator,
heads, and air filter. The DE is sealed to protect these components from dust.
Master (Device 0)
The master is the first drive that can operate on the AT bus. The master is daisy-
chained with the second drive which can operate in conformity with the ATA
standard.
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GL-1
Glossary
MTBF
Mean time between failures. The MTBF is calculated by dividing the total
operation time (total power-on time) by the number of failures in the disk drive
during operation.
MTTR
Mean time to repair. The MTTR is the average time required for a service person
to diagnose and repair a faulty drive.
PIO (Programmed input-output)
Mode to transfer data under control of the host CPU
Positioning
Sum of the seek time and mean rotational delay
Power save mode
The power save modes are idle mode, standby mode, and sleep mode.
In idle mode, the drive is neither reading, writing, nor seeking data. In standby
mode, the spindle motor is stopped and circuits other than the interface control
circuit are sleeping. The drive enters sleep mode when the host issues the SLEEP
command.
Reserved
Reserved bits, bytes, and fields are set to zero and unusable because they are
reserved for future standards.
Rotational delay
Time delay due to disk rotation. The mean delay is the time required for half a
disk rotation. The mean delay is the average time required for a head to reach a
sector after the head is positioned on a track.
Seek time
The seek time is the time required for a head to move from the current track to
another track. The seek time does not include the mean rotational delay.
Slave (Device 1)
The slave is a second drive that can operate on the AT bus. The slave is daisy-
chained with the first drive operating in conformity with the ATA standard.
GL-2
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Glossary
Status
VCM
The status is a piece of one-byte information posted from the drive to the host
when command execution is ended. The status indicates the command
termination state.
Voice coil motor. The voice coil motor is excited by one or more magnets. In
this drive, the VCM is used to position the heads accurately and quickly.
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Acronyms and Abbreviations
HDD
Hard disk drive
A
I
ABRT Aborted command
AIC
AMNF Address mark not found
ATA AT attachment
Automatic idle control
IDNF
ID not found
IRQ14 Interrupt request 14
L
AWG American wire gage
LED
MB
Light emitting diode
B
M
BBK
BIOS
Bad block detected
Basic input-output system
Mega-byte
MB/S Mega-byte per seconds
C
MPU
Micro processor unit
CORR Corrected data
P
CH
Cylinder high register
CL
Cylinder low register
Command register
Current sense register
Current start/stop
Cylinder register
PCA
PIO
Printed circuit assembly
Programmed input-output
CM
CSR
CSS
CY
R
RLL
Run-length-limited
D
S
dBA
DE
DH
dB A-scale weighting
Disk enclosure
Device/head register
SA
SC
SG
SN
ST
System area
Sector count register
Signal ground
Sector number register
Status register
DRDY Drive ready
DRQ
DSC
DWF
Ddata request bit
Drive seek complete
Drive write fault
T
E
TPI
Track per inches
TRONF Track 0 not found
ECC
ER
Error checking and correction
Error register
Typ
Typical
ERR
Error
U
F
UNC
VCM
Uncorrectable ECC error
FR
Feature register
V
H
Voice coil motor
HA
Host adapter
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C141-E104-02EN
MHL2300AT, MHM2200AT, MHM2150AT, MHM2100AT DISK
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