CY25818/19
Spread Spectrum Clock Generator
Features
Applications
• 8- to 32-MHz input frequency range
• CY25818: 8–16 MHz
• Printers and MFPs
• LCD panels and notebook PCs
• Digital copiers
• CY25819: 16–32 MHz
• Separate modulated and unmodulated clocks
• Accepts clock, crystal, and resonator inputs
• Down spread modulation
• PDAs
• Automotive
• CD-ROM, VCD, and DVD
• Networking and LAN/WAN
• Scanners
• Power-down function
• Low-power dissipation
— CY25818 = 33 mW-typ @ 8 MHz
— CY25818 = 56 mW-typ @ 16 MHz
— CY25819 = 36 mW-typ @ 16 MHz
— CY25819 = 63 mW-typ @ 32 MHz
• Low cycle-to-cycle jitter
• Modems
• Embedded digital systems
Benefits
• Peak electromagnetic interference (EMI) reduction by
8–16 dB
— SSCLK = 250 ps-typ
• Fast time to market
• Cost reduction
— REFOUT = 275 ps-typ
• Available in 8-pin (150-mil) SOIC package
Block Diagram
Pin Configuration
300K
REFERENCE
DIVIDER
PD and
CP
LF
1
8
XIN/CLKIN
XOUT
1
2
3
4
8
7
6
5
XIN/CLKIN
Vss
XOUT
Vdd
CY25818
CY25819
VCO
COUNTER
MODULATION
CONTROL
VCO
PD#
S0
7
2
VDD
VSS
SSCLK
REFCLK
DIVIDER
4
5
SSCLK
INPUT
DECODER
and
MUX
REFCLK
3
6
8-pin SOIC
PD#
S0
Cypress Semiconductor Corporation
Document #: 38-07362 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 11, 2006
CY25818/19
3-Level Digital Inputs
Modulation Rate
S0 digital input is designed to sense three logic levels desig-
nated as HIGH “1,” LOW “0,” and MIDDLE “M.” With this
3-Level digital input logic, the 3-Level logic is able to detect
three different logic levels.
Spread Spectrum Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (fmax) and
minimum frequency of the clock (fmin) determine this band of
frequencies. The time required to transition from fmin to fmax
and back to fmin is the period of the Modulation Rate, Tmod.
The Modulation Rates of SSCG clocks are generally referred
to in terms of frequency, and fmod = 1/Tmod.
The S0 pin includes an on-chip 20K (10K/10K) resistor divider.
No external application resistors are needed to implement
3-Level logic, as follows.
Logic Level “0”: 3-Level logic pin connected to GND.
Logic Level “M”: 3-Level logic pin left floating (no connection.)
Logic Level “1”: 3-Level logic pin connected to Vdd.
The input clock frequency, fin, and the internal divider
determine the Modulation Rate.
In the case of CY25818/19 devices, the (Spread Spectrum)
Modulation Rate, fmod, is given by the following formula:
Figure 1 illustrates how to implement 3-Level Logic.
LOGIC
HIGH (H)
fmod = f /DR
LOGIC
LOW (0)
LOGIC
MIDDLE (M)
IN
where fmod is the Modulation Rate, f is the Input Frequency,
IN
and DR is the Divider Ratio, as given in Table 3.
VDD
S0
S0
S0
to VSS
to VDD
UNCONNECTED
VSS
Figure 1. 3-Level Logic
Table 3. Modulation Rate Divider Ratios
Product
CY25818
CY25819
Input Frequency Range
8–16 MHz
Divider Ratio (DR)
256
512
16–32 MHz
Maximum Ratings[1, 2]
Input Voltage Relative to Vss:...............................Vss + 0.3V
Operating Temperature:................................... 0°C to + 70°C
Storage Temperature:................................ –65°C to + 150°C
Supply Voltage (Vdd): ..................................................+ 5.5V
Input Voltage Relative to Vdd:.............................. Vdd + 0.3V
Table 4. DC Electrical Characteristics Vdd = 3.3V ±10%, T = 0°C to +70°C and C = 15 pF (unless otherwise noted)
A
L
Parameter
Description
Power Supply Range
Input HIGH Voltage
Conditions
Min.
Typ.
3.3
Max.
3.63
Vdd
0.60 Vdd
0.15 Vdd
–
Unit
V
Vdd
2.97
V
V
V
V
V
V
V
S0 Input
0.85 Vdd
Vdd
0.50 Vdd
0.0
V
INH
INM
INL
Input MIDDLE Voltage S0 Input
0.40 Vdd
V
Input LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input Capacitance
Input Capacitance
S0 Input
0.0
2.4
2.0
–
V
I
I
I
I
= 4 ma, SSCLK and REFCLK
= 6 ma, SSCLK and REFCLK
= 4 ma, SSCLK Output
–
V
OH1
OH2
OL1
OL2
OH
OH
OL
OL
–
–
V
–
0.4
V
= 10 ma, SSCLK Output
–
–
1.2
V
C
C
X
(Pin 1) and X (Pin 8)
OUT
6.0
3.5
–
7.5
9.0
pF
pF
mA
mA
mA
IN1
IN2
IN
All Digital Inputs
4.5
6.0
I
I
I
Power Supply Current F =8 MHz, no load
10.0
19.0
150
12.5
23.0
250
DD1
DD3
DD4
IN
Power Supply Current F =32 MHz, no load
–
IN
Power Supply Current PD# = Vss
–
Document #: 38-07362 Rev. *B
Page 3 of 7
CY25818/19
Table 5. Timing Electrical Characteristics Vdd = 3.3V ±10%, T = 0°C to +70°C and C = 15 pF (unless otherwise noted)
A
L
Min.
8
Parameter
ICLKFR1
ICLKFR2
trise1
Description
Input Frequency Range
Input Frequency Range
Clock Rise Time
Conditions
Typ.
–
Max.
16
Unit
MHz
MHz
ns
CY25818
CY25819
16
–
32
SSCLK and REFCLK, 0.4V to 2.4V
SSCLK and REFCLK, 0.4V to 2.4V
2.0
2.0
20
3.0
3.0
50
4.0
4.0
80
tfall1
Clock Fall Time
ns
CDCin
Input Clock Duty Cycle
X
%
IN
CDCout
CCJss
Output Clock Duty Cycle SSCLK and REFCLK @ 1.5V
45
50
55
%
Cycle-to-Cycle Jitter
Cycle-to-Cycle Jitter
SSCLK; F = F
= 8–32 MHz
250
275
350
375
ps
IN
OUT
CCJref
REFCLK; F = F
= 8–32 MHz
OUT
ps
IN
Characteristics Curves
20
19
18
17
16
15
14
13
12
11
The following curves demonstrate the characteristic behavior
of the CY25818/19 when tested over a number of environ-
mental and application specific parameters. These are typical
performance curves and are not meant to replace any
parameter specified in Table 4 and Table 5.
CY25818
CY25819
8 - 16 M Hz
16 - 32 M Hz
300
290
REFCLK CY25819
REFCLK CY25818
280
270
260
250
10
8
12
16
20
24
28
32
S S CLK CY25819
240
Fr equency ( M Hz )
230
S S CLK CY25818
220
Figure 4. IDD (mA) vs. Frequency (MHz)
210
200
3.1
3
8
12
16
20
24
28
32
Fr equency ( M Hz )
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
CY25819@32 MHz
Figure 2. CCJ (ps) vs. Frequency (MHz)
2.75
2.5
1.9
1.8
12 MHz
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
2.25
2
VDD (volts)
32.0MHz
Figure 5. Bandwidth% vs. Vdd
1.75
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temp (C)
Figure 3. Bandwidth% vs. Temperature
Notes:
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Operation at any Absolute Maximum Rating is not implied.
Document #: 38-07362 Rev. *B
Page 4 of 7
CY25818/19
SSCG Profiles
CY25818/19 SSCG products use a non-linear “optimized”
frequency profile as shown in Figure 6 and Figure 7. The use
of Cypress proprietary “optimized” frequency profile maintains
flat energy distribution over the fundamental and higher order
harmonics. This results in additional EMI reduction in
electronic systems.
Figure 7. CY25819 Spread Spectrum Profile
[4]
(Frequency vs. Time)
Figure 6. CY25818 Spread Spectrum Profile
[3]
(Frequency vs. Time)
Application Schematic
Vdd
C3
0.1 uF
7
C2
Vdd
1
XIN
4
14.3 MHz
or
27.0 MHz
27 pF
C3
SSCLK
REFCLK
14.3 MHz (CY25818)
27.0 MHz (CY25819)
5
8
XOUT
27 pF
CY25818
CY25819
6
PD#
3
S0
Vss
2
Figure 8. Typical Application Schematic
Notes:
3. X = 16.0 MHz; S0 = 1; SSCLK = 16.0 MHz; BW = –2.14%.
IN
4. Xin = 32.0MHz; S0 = 1; SSCLK = 32.0 MHz; BW = -2.15%
Document #: 38-07362 Rev. *B
Page 5 of 7
CY25818/19
Ordering Information
Part Number
CY25818SC
Package Type
Product Flow
Commercial, 0° to 70°C
8-pin SOIC
CY25818SCT
CY25819SC
8-pin SOIC–Tape and Reel
8-pin SOIC
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
CY25819SCT
Lead-free
8-pin SOIC–Tape and Reel
CY25818SXC
CY25818SXCT
CY25819SXC
CY25819SXCT
8-pin SOIC
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
8-pin SOIC–Tape and Reel
8-pin SOIC
8-pin SOIC–Tape and Reel
Package Drawing and Dimensions
8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
0.150[3.810]
0.157[3.987]
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07362 Rev. *B
Page 6 of 7
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY25818/19
Document History Page
Document Title: CY25818/19 Spread Spectrum Clock Generator
Document Number: 38-07362
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
112462
122701
448097
Description of Change
03/21/02
12/28/02
See ECN
OXC
RBI
New Data Sheet
*A
Added power up requirements to maximum rating information.
Add Lead-free devices
*B
RGL
Document #: 38-07362 Rev. *B
Page 7 of 7
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