Analog Devices AD604 User Manual

Dual, Ultralow Noise  
Variable Gain Amplifier  
AD604  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Ultralow input noise at maximum gain  
0.80 nV/√Hz, 3.0 pA/√Hz  
PAOx  
–DSXx  
+DSXx  
VGNx  
2 independent linear-in-dB channels  
Absolute gain range per channel programmable  
0 dB to 48 dB (preamplifier gain = 14 dB) through 6 dB to  
54 dB (preamplifier gain = 20 dB)  
1.0 dB gain accuracy  
GAIN CONTROL  
AND SCALING  
VREF  
DIFFERENTIAL  
ATTENUATOR  
R-1.5R  
LADDER NETWORK  
PAIx  
OUTx  
AFA  
0dB TO –48.4dB  
Bandwidth: 40 MHz (−3 dB)  
VOCM  
PROGRAMMABLE  
ULTRALOW NOISE  
PREAMPLIFIER  
Input resistance: 300 kΩ  
FIXED GAIN  
AMPLIFIER  
34.4dB  
Variable gain scaling: 20 dB/V through 40 dB/V  
Stable gain with temperature and supply variations  
Single-ended unipolar gain control  
Power shutdown at lower end of gain control  
Drive ADCs directly  
G = 14dB TO 20dB  
PRECISION PASSIVE  
INPUT ATTENUATOR  
Figure 1.  
APPLICATIONS  
Ultrasound and sonar time-gain controls  
High performance AGC systems  
Signal measurement  
GENERAL DESCRIPTION  
www.BDTIC.com/ADI  
Preamplifier gains between 5 and 10 (14 dB and 20 dB) provide  
overall gain ranges per channel of 0 dB through 48 dB and 6 dB  
through 54 dB. The two channels of the AD604 can be cascaded  
to provide greater levels of gain range by bypassing the preamplifier  
of the second channel. However, in multiple channel systems,  
cascading the AD604 with other devices in the AD60x VGA  
family that do not include a preamplifier may provide a more  
efficient solution. The AD604 provides access to the output of  
the preamplifier, allowing for external filtering between the  
preamplifier and the differential attenuator stage.  
The AD604 is an ultralow noise, very accurate, dual-channel,  
linear-in-dB variable gain amplifier (VGA) optimized for time-  
based variable gain control in ultrasound applications; however,  
it supports any application requiring low noise, wide bandwidth,  
variable gain control. Each channel of the AD604 provides a  
300 kΩ input resistance and unipolar gain control for ease of  
use. User-determined gain ranges, gain scaling (dB/V), and dc  
level shifting of output further optimize performance.  
Each channel of the AD604 uses a high performance  
preamplifier that provides an input-referred noise voltage of  
0.8 nV/√Hz. The very accurate linear-in-dB response of the  
AD604 is achieved with the differential input exponential  
amplifier (DSX-AMP) architecture. Each DSX-AMP comprises  
a variable attenuator of 0 dB to 48.36 dB followed by a high  
speed fixed-gain amplifier. The attenuator is a 7-stage  
R-1.5R ladder network. The attenuation between tap points is  
6.908 dB and 48.36 dB for the ladder network.  
Note that scale factors up to 40 dB/V are achievable with reduced  
accuracy for scales above 30 dB/V. The gain scales linearly in  
decibels with control voltages of 0.4 V to 2.4 V with the 20 dB/V  
scale. Below and above this gain control range, the gain begins  
to deviate from the ideal linear-in-dB control law. The gain  
control region below 0.1 V is not used for gain control. When  
the gain control voltage is <50 mV, the amplifier channel is  
powered down to 1.9 mA.  
The equation for the linear-in-dB gain response is  
The AD604 is available in 24-lead SSOP, SOIC, and PDIP  
packages and is guaranteed for operation over the −40°C to  
+85°C temperature range.  
G (dB) =  
(Gain Scaling (dB/V) × VGN (V)) + (Preamp Gain (dB) – 19 dB)  
Rev. E  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113 ©1996–2008 Analog Devices, Inc. All rights reserved.  
 
AD604  
SPECIFICATIONS  
Each amplifier channel at TA = 25°C, VS = 5 V, RS = 50 Ω, RL = 500 Ω, CL = 5 pF, VREF = 2.50 V (scaling = 20 dB/V), 0 dB to 48 dB gain  
range (preamplifier gain = 14 dB), VOCM = 2.5 V, C1 and C2 = 0.1 μF (see Figure 37), unless otherwise noted.  
Table 1.  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
INPUT CHARACTERISTICS  
Preamplifier  
Input Resistance  
Input Capacitance  
Input Bias Current  
Peak Input Voltage  
300  
8.5  
−27  
400  
200  
kΩ  
pF  
mA  
mV  
mV  
Preamplifier gain = 14 dB  
Preamplifier gain = 20 dB  
VGN = 2.9 V, RS = 0 Ω  
Input Voltage Noise  
Preamplifier gain = 14 dB  
Preamplifier gain = 20 dB  
Independent of gain  
RS = 50 Ω, f = 10 MHz, VGN = 2.9 V  
RS = 200 Ω, f = 10 MHz, VGN = 2.9 V  
0.8  
0.73  
3.0  
2.3  
1.1  
nV/√Hz  
nV/√Hz  
pA/√Hz  
dB  
Input Current Noise  
Noise Figure  
dB  
DSX  
Input Resistance  
Input Capacitance  
Peak Input Voltage  
Input Voltage Noise  
Input Current Noise  
Noise Figure  
175  
3.0  
2.5  
1.8  
2.7  
8.4  
12  
Ω
pF  
V
nV/√Hz  
pA/√Hz  
dB  
dB  
dB  
2
VGN = 2.9 V  
VGN = 2.9 V  
RS = 50 Ω, f = 10 MHz, VGN = 2.9 V  
RS = 200 Ω, f = 10 MHz, VGN = 2.9 V  
f = 1 MHz, VGN = 2.65 V  
www.BDTIC.com/ADI  
Common-Mode Rejection Ratio  
−20  
OUTPUT CHARACTERISTICS  
−3 dB Bandwidth  
Slew Rate  
Output Signal Range  
Constant with gain  
VGN = 1.5 V, output = 1 V step  
RL ≥ 500 Ω  
40  
170  
2.5 1.5  
MHz  
V/μs  
V
Output Impedance  
f = 10 MHz  
2
Ω
Output Short-Circuit Current  
40  
mA  
Harmonic Distortion  
HD2  
VGN = 1 V, VOUT = 1 V p-p  
f = 1 MHz  
−54  
−67  
−43  
−48  
dBc  
dBc  
dBc  
dBc  
HD3  
HD2  
HD3  
f = 1 MHz  
f = 10 MHz  
f = 10 MHz  
Two-Tone Intermodulation Distortion (IMD)  
VGN = 2.9 V, VOUT = 1 V p-p  
f = 1 MHz  
−74  
−71  
−12.5  
dBc  
dBc  
dBm  
f = 10 MHz  
Third-Order Intercept  
f = 10 MHz, VGN = 2.65 V, VOUT = 1 V p-p,  
input referred  
1 dB Compression Point  
Channel-to-Channel Crosstalk  
f = 1 MHz, VGN = 2.9 V, output referred  
VOUT = 1 V p-p, f = 1 MHz,  
15  
−30  
dBm  
dB  
Channel 1: VGN = 2.65 V, inputs shorted,  
Channel 2: VGN = 1.5 V (mid gain)  
Group Delay Variation  
VOCM Input Resistance  
1 MHz < f < 10 MHz, full gain range  
2
45  
ns  
kΩ  
Rev. E | Page 3 of 32  
 
AD604  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
ACCURACY  
Absolute Gain Error  
0 dB to 3 dB  
3 dB to 43 dB  
0.25 V < VGN < 0.400 V  
0.400 V < VGN < 2.400 V  
2.400 V < VGN < 2.65 V  
0.400 V < VGN < 2.400 V  
VREF = 2.500 V, VOCM = 2.500 V  
VREF = 2.500 V, VOCM = 2.500 V  
−1.2  
−1.0  
−3.5  
+0.75  
0.3  
−1.25  
0.25  
30  
+3  
+1.0  
+1.2  
dB  
dB  
dB  
dB/V  
mV  
mV  
43 dB to 48 dB  
Gain Scaling Error  
Output Offset Voltage  
Output Offset Variation  
GAIN CONTROL INTERFACE  
Gain Scaling Factor  
−50  
19  
+50  
50  
30  
VREF = 2.5 V, 0.4 V < VGN < 2.4 V  
VREF = 1.67 V  
Preamplifier gain = 14 dB  
Preamplifier gain = 20 dB  
20 dB/V, VREF = 2.5 V  
20  
30  
21  
dB/V  
dB/V  
dB  
dB  
V
μA  
MΩ  
μs  
Gain Range  
0 to 48  
6 to 54  
0.1 to 2.9  
−0.4  
2
Input Voltage (VGN) Range  
Input Bias Current  
Input Resistance  
Response Time  
48 dB gain change  
0.2  
VREF Input Resistance  
POWER SUPPLY  
10  
kΩ  
Specified Operating Range  
One complete channel  
One DSX only  
5
5
V
V
Power Dissipation  
One complete channel  
One DSX only  
VPOS, one complete channel  
VPOS, one DSX only  
VNEG, one preamplifier only  
VPOS, VGN < 50 mV, one channel  
VNEG, VGN < 50 mV, one channel  
48 dB gain change, VOUT = 2 V p-p  
220  
95  
32  
19  
−12  
1.9  
−150  
0.6  
mW  
mW  
mA  
mA  
mA  
mA  
μA  
μs  
Quiescent Supply Current  
36  
23  
−15  
www.BDTIC.com/ADI  
Powered Down  
3.0  
Power-Up Response Time  
Power-Down Response Time  
0.4  
μs  
Rev. E | Page 4 of 32  
AD604  
ABSOLUTE MAXIMUM RATINGS  
Stresses above those listed under Absolute Maximum Ratings  
Table 2.  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Parameter1, 2  
Rating  
Supply Voltage VS  
Pin 17 to Pin 20 (with Pin 16, Pin 22 = 0 V)  
Input Voltages  
6.5 V  
Pin 1, Pin 2, Pin 11, Pin 12  
VPOS/2 2 V  
continuous  
Pin 4, Pin 9  
Pin 5, Pin 8  
Pin 6, Pin 7, Pin 13, Pin 14, Pin 23, Pin 24  
Internal Power Dissipation  
PDIP (N)  
2 V  
ESD CAUTION  
VPOS, VNEG  
VPOS, 0 V  
2.2 W  
SOIC (RW)  
1.7 W  
SSOP (RS)  
1.1 W  
Operating Temperature Range  
Storage Temperature Range  
Lead Temperature, Soldering 60 sec  
−40°C to +85°C  
−65°C to +150°C  
300°C  
θJA  
AD604AN  
AD604AR  
AD604ARS  
105°C/W  
73°C/W  
112°C/W  
θJC  
AD604AN  
AD604AR  
AD604ARS  
35°C/W  
38°C/W  
34°C/W  
www.BDTIC.com/ADI  
1 Pin 1, Pin 2, Pin 11 to Pin 14, Pin 23, and Pin 24 are part of a single-supply  
circuit. The part is likely to suffer damage if any of these pins are accidentally  
connected to VN.  
2 When driven from an external low impedance source.  
3 Using MIL-STD-883 test method G43-87 with a 1S (2-layer) test board.  
Rev. E | Page 5 of 32  
           
AD604  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
–DSX1  
+DSX1  
PAO1  
FBK1  
PAI1  
1
2
3
4
5
6
7
8
9
24 VGN1  
23 VREF  
22 OUT1  
21 GND1  
20 VPOS  
19 VNEG  
18 VNEG  
17 VPOS  
16 GND2  
15 OUT2  
14 VOCM  
13 VGN2  
AD604  
COM1  
COM2  
PAI2  
TOP VIEW  
(Not to Scale)  
FBK2  
PAO2 10  
+DSX2 11  
–DSX2 12  
Figure 2. Pin Configuration  
Table 3. Pin Function Descriptions  
Pin No.  
Mnemonic  
–DSX1  
+DSX1  
PAO1  
Description  
1
2
3
Channel 1 Negative Signal Input to DSX1.  
Channel 1 Positive Signal Input to DSX1.  
Channel 1 Preamplifier Output.  
4
FBK1  
Channel 1 Preamplifier Feedback Pin.  
5
PAI1  
Channel 1 Preamplifier Positive Input.  
6
7
8
COM1  
COM2  
PAI2  
Channel 1 Signal Ground. When this pin is connected to positive supply, Preamplifier 1 shuts down.  
Channel 2 Signal Ground. When this pin is connected to positive supply, Preamplifier 2 shuts down.  
Channel 2 Preamplifier Positive Input.  
9
FBK2  
PAO2  
+DSX2  
–DSX2  
VGN2  
Channel 2 Preamplifier Feedback Pin.  
Channel 2 Preamplifier Output.  
Channel 2 Positive Signal Input to DSX2.  
Channel 2 Negative Signal Input to DSX2.  
Channel 2 Gain Control Input and Power-Down Pin. If this pin is grounded, the device is off; otherwise, positive  
voltage increases gain.  
www.BDTIC.com/ADI  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VOCM  
OUT2  
GND2  
VPOS  
VNEG  
VNEG  
VPOS  
GND1  
OUT1  
VREF  
Input to this pin defines the common mode of the output at OUT1 and OUT2.  
Channel 2 Signal Output.  
Ground.  
Positive Supply.  
Negative Supply.  
Negative Supply.  
Positive Supply.  
Ground.  
Channel 1 Signal Output.  
Input to this pin sets gain scaling for both channels to 2.5 V = 20 dB/V and 1.67 V = 30 dB/V.  
Channel 1 Gain Control Input and Power-Down Pin. If this pin is grounded, the device is off; otherwise, positive  
voltage increases gain.  
VGN1  
Rev. E | Page 6 of 32  
 
AD604  
TYPICAL PERFORMANCE CHARACTERISTICS  
Unless otherwise noted, G (preamplifier) = 14 dB, VREF = 2.5 V (20 dB/V scaling), f = 1 MHz, RL = 500 Ω, CL = 5 pF, TA = 25°C, and  
VSS  
=
5 V.  
50  
40.0  
37.5  
35.0  
32.5  
30.0  
27.5  
25.0  
22.5  
20.0  
40  
30  
20  
10  
0
THEORETICAL  
3 CURVES  
–40°C,  
+25°C,  
+85°C  
ACTUAL  
–10  
0.1  
0.5  
0.9  
1.3  
1.7  
2.1  
2.5  
2.9  
1.25  
1.50  
1.75  
2.00  
2.25  
2.50  
VGN (V)  
VREF (V)  
Figure 3. Gain vs. VGN for Three Temperatures  
Figure 6. Gain Scaling vs. VREF  
2.0  
1.5  
1.0  
0.5  
60  
50  
G (PREAMP) = +14dB  
(0dB TO +48dB)  
40  
G (PREAMP) = +20dB  
(+6dB TO +54dB)  
30  
+25°C  
–40°C  
www.BDTIC.com/ADI  
0
20  
–0.5  
10  
+85°C  
DSX ONLY  
(–14dB TO +34dB)  
–1.0  
0
–1.5  
–10  
–20  
–2.0  
0.2  
0.7  
1.2  
1.7  
2.2  
2.7  
0.1  
0.5  
0.9  
1.3  
1.7  
2.1  
2.5  
2.9  
VGN (V)  
VGN (V)  
Figure 7. Gain Error vs. VGN  
Figure 4. Gain vs. VGN for Different Preamplifier Gains  
50  
2.0  
1.5  
1.0  
ACTUAL  
40  
30  
20  
10  
0
ACTUAL  
30dB/V  
VREF = 1.67V  
0.5  
FREQ = 1MHz  
0
20dB/V  
VREF = 2.5V  
–0.5  
–1.0  
–1.5  
–2.0  
FREQ = 5MHz  
FREQ = 10MHz  
–10  
0.1  
0.2  
0.7  
1.2  
1.7  
2.2  
2.7  
0.5  
0.9  
1.3  
1.7  
2.1  
2.5  
2.9  
VGN (V)  
VGN (V)  
Figure 8. Gain Error vs. VGN at Different Frequencies  
Figure 5. Gain vs. VGN for Different Gain Scalings  
Rev. E | Page 7 of 32  
 
AD604  
50  
40  
2.0  
VGN = 2.5V  
VGN = 2.9V  
1.5  
30  
1.0  
VGN = 1.5V  
VGN = 0.5V  
VGN = 0.1V  
20  
20dB/V  
VREF = 2.5V  
0.5  
10  
0
0
–10  
–20  
–30  
–40  
–50  
–0.5  
–1.0  
–1.5  
–2.0  
30dB/V  
VREF = 1.67V  
VGN = 0V  
0.2  
0.7  
1.2  
1.7  
2.2  
2.7  
100k  
1M  
10M  
FREQUENCY (Hz)  
100M  
VGN (V)  
Figure 9. Gain Error vs. VGN for Two Gain Scaling Values  
Figure 12. AC Response for Various Values of VGN  
25  
2.55  
2.54  
2.53  
2.52  
2.51  
2.50  
2.49  
2.48  
2.47  
N = 50  
VOCM = 2.5V  
VGN1 = 1.0V  
VGN2 = 1.0V  
ΔG(dB) =  
20  
–40°C  
G(CH1) – G(CH2)  
15  
10  
5
+25°C  
+85°C  
www.BDTIC.com/ADI  
2.46  
0
2.45  
0.2  
–1.0 –0.8 –0.6 –0.4 –0.2  
0.1  
0.3  
0.5  
0.7  
0.9  
0.7  
1.2  
1.7  
2.2  
2.7  
DELTA GAIN (dB)  
VGN (V)  
Figure 10. Gain Match; VGN1 = VGN2 = 1.0 V  
Figure 13. Output Offset vs. VGN for Three Temperatures  
25  
20  
15  
10  
5
210  
N = 50  
VGN1 = 2.50V  
VGN2 = 2.50V  
ΔG(dB) =  
190  
170  
150  
130  
110  
90  
G(CH1) – G(CH2)  
+85°C  
+25°C  
1.7  
–40°C  
0
–1.0 –0.8 –0.6 –0.4 –0.2  
0.1  
0.3  
0.5  
0.7  
0.9  
0.1  
0.5  
0.9  
1.3  
VGN (V)  
2.1  
2.5  
2.9  
DELTA GAIN (dB)  
Figure 11. Gain Match; VGN1 = VGN2 = 2.50 V  
Figure 14. Output Referred Noise vs. VGN for Three Temperatures  
Rev. E | Page 8 of 32  
AD604  
1000  
100  
10  
10  
VGN = 2.9V  
1
R
ALONE  
1
SOURCE  
0.1  
0.1  
0.1  
0.5  
0.9  
1.3  
1.7  
2.1  
2.5  
2.9  
1
10  
100  
1k  
VGN (V)  
R
()  
SOURCE  
Figure 18. Input Referred Noise vs. RSOURCE  
Figure 15. Input Referred Noise vs. VGN  
16  
15  
14  
13  
12  
11  
10  
9
900  
850  
800  
750  
700  
650  
600  
VGN = 2.9V  
VGN = 2.9V  
8
7
6
5
4
www.BDTIC.com/ADI  
3
2
1
1
10  
100  
1k  
10k  
–40  
–20  
0
20  
40  
60  
80 90  
R
()  
TEMPERATURE (°C)  
SOURCE  
Figure 16. Input Referred Noise vs. Temperature  
Figure 19. Noise Figure vs. RSOURCE  
40  
35  
30  
25  
20  
15  
10  
5
770  
765  
760  
755  
750  
745  
740  
VGN = 2.9V  
R
= 240Ω  
S
0
100k  
1M  
10M  
0
0.4  
0.8  
1.2  
1.6  
2.0  
2.4  
2.8  
FREQUENCY (Hz)  
VGN (V)  
Figure 17. Input Referred Noise vs. Frequency  
Figure 20. Noise Figure vs. VGN  
Rev. E | Page 9 of 32  
AD604  
–20  
–30  
–40  
–45  
–50  
–55  
–60  
–65  
–70  
V
= 1V p-p  
V
= 1V p-p  
O
O
VGN = 1V  
VGN = 1V  
–40  
–50  
–60  
HD2  
–70  
–80  
HD3  
–90  
–100  
–110  
–120  
9.96  
9.98  
10.00  
10.02  
10.04  
100k  
1M  
10M  
FREQUENCY (Hz)  
100M  
FREQUENCY (MHz)  
Figure 24. Intermodulation Distortion  
Figure 21. Harmonic Distortion vs. Frequency  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
5
0
V
= 1V p-p  
O
INPUT  
HD2 (10MHz)  
SIGNAL  
LIMIT  
–5  
800mV p-p  
–10  
–15  
–20  
–25  
10MHz  
HD3 (10MHz)  
1MHz  
HD2 (1MHz)  
www.BDTIC.com/ADI  
–30  
HD3 (1MHz)  
–35  
0.1  
0.5  
0.9  
1.3  
1.7  
2.1  
2.5  
2.9  
0.5  
0.9  
1.3  
1.7  
2.1  
2.5  
2.9  
VGN (V)  
VGN (V)  
Figure 22. Harmonic Distortion vs. VGN  
Figure 25. 1 dB Compression vs. VGN  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
25  
V
= 1V p-p  
R
S
V
= 1V p-p  
O
O
VGN = 1V  
DUT  
20  
15  
10  
5
50Ω  
500Ω  
f
= 1MHz  
HD2 (10MHz)  
HD3 (10MHz)  
HD2 (1MHz)  
0
f
= 10MHz  
HD3 (1MHz)  
–5  
–10  
–15  
0
50  
100  
R
150  
200  
250  
0.4  
0.9  
1.4  
1.9  
2.4  
2.9  
()  
VGN (V)  
SOURCE  
Figure 26. Third-Order Intercept vs. VGN  
Figure 23. Harmonic Distortion vs. RSOURCE  
Rev. E | Page 10 of 32  
AD604  
2V  
V
= 2V p-p  
O
VGN = 1.5V  
500mV  
2.9V 100  
90  
10  
0%  
0.1V  
500mV  
100ns  
–2V  
253ns  
100ns/DIV  
1.253µs  
Figure 27. Large Signal Pulse Response  
Figure 30. Gain Response  
0
200  
VGN1 = 1V  
V
= 200mV p-p  
O
V
V
= 1V p-p  
VGN = 1.5V  
OUT1  
= GND  
–10  
–20  
–30  
–40  
–50  
–60  
IN2  
VGN2 = 2.9V  
VGN2 = 2V  
TRIG'D  
–200  
VGN2 = 1.5V  
VGN2 = 0.1V  
www.BDTIC.com/ADI  
–70  
100k  
1M  
10M  
FREQUENCY (Hz)  
100M  
253ns  
100ns/DIV  
1.253µs  
Figure 28. Small Signal Pulse Response  
Figure 31. Crosstalk (Channel 1 to Channel 2) vs. Frequency  
0
500mV  
–10  
2.9V  
100  
90  
VGN = 2.9V  
–20  
VGN = 2.5V  
–30  
VGN = 2V  
–40  
10  
0%  
0V  
–50  
VGN = 0.1V  
500mV  
200ns  
–60  
100k  
1M  
10M  
FREQUENCY (Hz)  
100M  
Figure 32. DSX Common-Mode Rejection Ratio vs. Frequency  
Figure 29. Power-Up/Power-Down Response  
Rev. E | Page 11 of 32  
AD604  
1M  
100k  
10k  
1k  
40  
35  
30  
25  
20  
15  
10  
5
+I (AD604) = +I (PA) + +I (DSX)  
S
S
S
–I (AD604) = –I (PA)  
S
S
AD604 (+I  
)
S
DSX (+I )  
S
100  
10  
PREAMP (±I )  
S
+I (VGN = 0)  
S
0
–40  
1
1k  
–20  
0
20  
40  
60  
80 90  
10k  
100k  
1M  
10M  
100M  
TEMPERATURE (°C)  
FREQUENCY (Hz)  
Figure 33. Input Impedance vs. Frequency  
Figure 35. Supply Current (One Channel) vs. Temperature  
27.6  
27.4  
27.2  
27.0  
26.8  
26.6  
26.4  
26.2  
26.0  
25.8  
20  
18  
16  
14  
VGN = 0.1V  
12  
10  
VGN = 2.9V  
www.BDTIC.com/ADI  
8
6
100k  
–40  
–20  
0
20  
40  
60  
80 90  
1M  
10M  
100M  
TEMPERATURE (°C)  
FREQUENCY (Hz)  
Figure 34. Input Bias Current vs. Temperature  
Figure 36. Group Delay vs. Frequency  
Rev. E | Page 12 of 32  
AD604  
THEORY OF OPERATION  
The AD604 is a dual-channel VGA with an ultralow noise  
preamplifier. Figure 37 shows the simplified block diagram of  
one channel. Each identical channel consists of a preamplifier  
with gain setting resistors (R5, R6, and R7) and a single-supply  
X-AMP® (hereafter called DSX, differential single-supply X-AMP)  
made up of the following:  
example, if the preamp gain is set to 14 dB and VREF is set to  
2.50 V (to establish a gain scaling of 20 dB/V), the gain equation  
simplifies to  
G (dB) = 20 (dB/V) × VGN (V) – 5 dB  
The desired gain can then be achieved by setting the unipolar  
gain control (VGN) to a voltage within its nominal operating  
range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is  
monotonic for a complete gain control voltage range of 0.1 V to  
2.9 V. Maximum gain can be achieved at a VGN of 2.9 V.  
A precision passive attenuator (differential ladder).  
A gain control block.  
A VOCM buffer with supply splitting resistors  
(R3 and R4).  
The inputs VREF and VOCM are common to both channels.  
They are decoupled to ground, minimizing interchannel  
crosstalk. For the highest gain scaling accuracy, VREF should  
have an external low impedance voltage source. For low accuracy  
20 dB/V applications, the VREF input can be decoupled with a  
capacitor to ground. In this mode, the gain scaling is determined  
by the midpoint between VPOS and GND; therefore, care  
should be taken to control the supply voltage to 5 V. The input  
resistance looking into the VREF pin is 10 kΩ 20%.  
An active feedback amplifier (AFA) with gain setting  
resistors (R1 and R2). To understand the active-feedback  
amplifier topology, refer to the AD830 data sheet. The  
AD830 is a practical implementation of the idea.  
The preamplifier is powered by a 5 V supply, while the DSX  
uses a single +5 V supply. The linear-in-dB gain response of the  
AD604 can generally be described by  
G (dB) = Gain Scaling (dB/V) × Gain Control (V) +  
(Preamp Gain (dB) − 19 dB)  
The DSX portion of the AD604 is a single-supply circuit, and  
the VOCM pin is used to establish the dc level of the midpoint  
of this portion of the circuit. The VOCM pin only needs an  
external decoupling capacitor to ground to center the midpoint  
between the supply voltages (5 V, GND); however, the VOCM  
can be adjusted to other voltage levels if the dc common-mode  
(1)  
Each channel provides between 0 dB to 48.4 dB and 6 dB to 54.4  
dB of gain, depending on the user-determined preamplifier  
gain. The center 40 dB of gain is exactly linear-in-dB while the  
gain error increases at the top and bottom of the range. The gain  
www.BDTIC.com/ADI  
level of the output is important to the user (for example, see the  
of the preamplifier is typically either 14 dB or 20 dB but can be  
set to intermediate values by a single external resistor (see the  
a 10-Bit, 40 MSPS ADC). The input resistance looking into the  
VOCM pin is 45 kΩ 20%.  
Preamplifier section for details). The gain of the DSX can vary  
from −14 dB to +34.4 dB, as determined by the gain control  
voltage (VGN). The VREF input establishes the gain scaling;  
the useful gain scaling range is between 20 dB/V and 40 dB/V  
for a VREF voltage of 2.5 V and 1.25 V, respectively. For  
VREF  
VGNx  
GAIN  
CONTROL  
175  
C1  
C2  
PAIx  
PAOx  
EXT.  
+DSXx  
–DSXx  
DISTRIBUTED G  
Ao  
M
R7  
DIFFERENTIAL  
ATTENUATOR  
G1  
G2  
40Ω  
FBKx  
R5  
32Ω  
OUTx  
175Ω  
R6  
VPOS  
R3  
8Ω  
COMx  
200kΩ  
R2  
20Ω  
R1  
820Ω  
VOCM  
C3  
EXT.  
R4  
200kΩ  
Figure 37. Simplified Block Diagram of a Single Channel of the AD604  
Rev. E | Page 13 of 32  
   
AD604  
preamplifier to be 17.7 dB. The −3 dB small signal bandwidth of  
one complete channel of the AD604 (preamplifier and DSX) is  
40 MHz and is independent of gain.  
PREAMPLIFIER  
The input capability of the following single-supply DSX (2.5 2 V  
for a +5 V supply) limits the maximum input voltage of the  
preamplifier to 400 mV for the 14 dB gain configuration or  
200 mV for the 20 dB gain configuration.  
To achieve optimum specifications, power and ground manage-  
ment are critical to the AD604. Large dynamic currents result  
because of the low resistances needed for the desired noise  
performance. Most of the difficulty is with the very low gain  
setting resistors of the preamplifier that allow for a total input  
referred noise, including the DSX, as low as 0.8 nV/√Hz. The  
consequently large dynamic currents have to be carefully  
handled to maintain performance even at large signal levels.  
20  
The preamplifier gain can be programmed to 14 dB or 20 dB by  
either shorting the FBK1 node to PAO1 (14 dB) or by leaving  
the FBK1 node open (20 dB). These two gain settings are very  
accurate because they are set by the ratio of the on-chip resistors.  
Any intermediate gain can be achieved by connecting the  
appropriate resistor value between PAO1 and FBK1 according  
to Equation 2 and Equation 3.  
OPEN  
19  
(
R7 || REXT + R5 + R6  
)
VOUT  
VIN  
40Ω  
18  
17  
16  
15  
14  
13  
12  
11  
10  
G =  
=
(2)  
(3)  
R6  
[
R6 × G −  
(
R5 + R6 × R7  
)
]
REXT  
=
R7 −  
(
R6 × G  
)
+
(R5 + R6)  
SHORT  
Because the internal resistors have an absolute tolerance of 20%,  
the gain can be in error by as much as 0.33 dB when REXT is 30 Ω,  
where it is assumed that REXT is exact.  
IN  
V
IN  
150Ω  
50Ω  
40Ω  
R
EXT  
8Ω  
32Ω  
Figure 38 shows how the preamplifier is set to gains of 14 dB,  
17.5 dB, and 20 dB. The gain range of a single channel of the  
AD604 is 0 dB to 48 dB when the preamplifier is set to 14 dB  
(Figure 38a), 3.5 dB to 51.5 dB for a preamp gain of 17.5 dB  
(Figure 38b), and 6 dB to 54 dB for the highest preamp gain of  
20 dB (Figure 38c).  
100k  
1M  
10M  
FREQUENCY (Hz)  
100M  
Figure 39. AC Response for Preamplifier Gains of 14 dB, 17.5 dB, and 20 dB  
The preamplifier uses a dual 5 V supply to accommodate large  
dynamic currents and a ground referenced input. The preamplifier  
PAI1  
output is also ground referenced and requires a common-mode  
level shift into the single-supply DSX. The two external coupling  
capacitors (C1 and C2 in Figure 37) connected to the PAO1 and  
+DSXx, and –DSXx, nodes and ground, respectively, perform  
this function (see the AC Coupling section). In addition, they  
eliminate any offset that would otherwise be introduced by the  
preamplifier. It should be noted that an offset of 1 mV at the  
input of the DSX is amplified by 34.4 dB (× 52.5) when the gain  
control voltage is at its maximum; this equates to 52.5 mV at the  
output. AC coupling is consequently required to keep the offset  
from degrading the output signal range.  
PAO1  
R7  
40  
R6  
8Ω  
R5  
32Ω  
COM1  
FBK1  
a. PREAMP GAIN = 14dB  
PAI1  
PAO1  
R7  
40Ω  
R10  
40Ω  
R6  
8Ω  
R5  
32Ω  
COM1  
FBK1  
b. PREAMP GAIN = 17.5dB  
The gain-setting preamplifier feedback resistors are small  
enough (8 Ω and 32 Ω) that even an additional 1 Ω in the  
ground connection at Pin COM1 (the input common-mode  
reference) seriously degrades gain accuracy and noise performance.  
This node is sensitive, and careful attention is necessary to  
minimize the ground impedance. All connections to the COM1  
node should be as short as possible.  
PAI1  
PAO1  
R7  
40Ω  
R6  
8Ω  
R5  
32Ω  
COM1  
FBK1  
c. PREAMP GAIN = 20dB  
Figure 38. Preamplifier Gain Programmability  
The preamplifier, including the gain setting resistors, has a  
noise performance of 0.71 nV/√Hz and 3 pA/√Hz. Note that a  
significant portion of the total input referred voltage noise is  
due to the feedback resistors. The equivalent noise resistance  
presented by R5 and R6 in parallel is nominally 6.4 Ω, which  
contributes 0.33 nV/√Hz to the total input referred voltage noise.  
For a preamplifier gain of 14 dB, the −3 dB small signal bandwidth  
of the preamplifier is 130 MHz. When the gain is at its maximum  
of 20 dB, the bandwidth is reduced by half to 65 MHz. Figure 39  
shows the ac response for the three preamp gains shown in  
Figure 38. Note that the gain for an REXT of 40 Ω should be  
17.5 dB, but the mismatch between the internal resistors and  
the external resistor causes the actual gain for this particular  
Rev. E | Page 14 of 32  
       
AD604  
The larger portion of the input referred voltage noise comes  
from the amplifier with 0.63 nV/√Hz. The current noise is  
independent of gain and depends only on the bias current in  
the input stage of the preamplifier, which is 3 pA/√Hz.  
A unique circuit technique is used to interpolate continuously  
among the tap points, thereby providing continuous attenuation  
from 0 dB to −48.36 dB. The ladder network, together with the  
interpolation mechanism, can be considered a voltage-controlled  
potentiometer.  
The preamplifier can drive 40 Ω (the nominal feedback resistors)  
and the following 175 Ω ladder load of the DSX with low  
distortion. For example, at 10 MHz and 1 V at the output, the  
preamplifier has less than −45 dB of second and third harmonic  
distortion when driven from a low (25 Ω) source resistance.  
Because the DSX circuit uses a single voltage power supply, the  
input biasing is provided by the VOCM buffer driving the MID  
node (see Figure 41). Without internal biasing, the user would  
have to dc bias the inputs externally. If not done carefully, the  
biasing network can introduce additional noise and offsets. By  
providing internal biasing, the user is relieved of this task and  
only needs to ac-couple the signal into the DSX. Note that the  
input to the DSX is still fully differential if driven differentially;  
that is, Pin +DSXx and Pin −DSXx see the same signal but with  
opposite polarity (see the Ultralow Noise, Differential Input-  
In applications that require more than 48 dB of gain range, two  
AD604 channels can be cascaded. Because the preamplifier has  
a limited input signal range and consumes over half (120 mW)  
of the total power (220 mW), and its ultralow noise is not necessary  
after the first AD604 channel, a shutdown mechanism that  
disables only the preamplifier is provided. To shut down the  
preamplifier, connect the COM1 pin and/or COM2 pin to the  
positive supply; the DSX is unaffected. For additional details,  
refer to the Applications Information section.  
What changes is the load seen by the driver; it is 175 Ω when  
each input is driven single-ended but 350 Ω when driven  
differentially. This is easily explained by thinking of the ladder  
network as two 175 Ω resistors connected back-to-back with  
the middle node, MID, being biased by the VOCM buffer. A  
differential signal applied between the +DSXx and −DSXx  
nodes results in zero current into the MID node, but a single-  
ended signal applied to either input, +DSXx or –DSXx, while  
the other input is ac-grounded causes the current delivered by  
the source to flow into the VOCM buffer via the MID node.  
1
2
3
4
5
6
7
8
9
–DSX1  
+DSX1  
PAO1  
FBK1  
PAI1  
24  
23  
22  
21  
20  
19  
18  
17  
16  
VGN1  
VREF  
OUT1  
GND1  
VPOS  
COM1AD604VNEG  
COM2  
PAI2  
VNEG  
VPOS  
GND2  
FBK2  
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The ladder resistor value of 175 Ω provides the optimum  
10  
11  
12  
15  
14  
13  
PAO2  
OUT2  
VOCM  
VGN2  
balance between the load driving capability of the preamplifier  
and the noise contribution of the resistors. An advantage of the  
X-AMP architecture is that the output referred noise is constant  
vs. gain over most of the gain range. Figure 41 shows that the  
tap resistance is equal for all taps after only a few taps away  
from the inputs. The resistance seen looking into each tap is  
54.4 Ω, which makes 0.95 nV/√Hz of Johnson noise spectral  
density. Because there are two attenuators, the overall noise  
contribution of the ladder network is √2 times 0.95 nV/√Hz  
or 1.34 nV/√Hz, a large fraction of the total DSX noise. The  
balance of the DSX circuit components contributes another  
1.2 nV/√Hz, which together with the attenuator produces  
1.8 nV/√Hz of total DSX input referred noise.  
+DSX2  
–DSX2  
Figure 40. Shutdown of Preamplifiers Only  
DIFFERENTIAL LADDER (ATTENUATOR)  
The attenuator before the fixed-gain amplifier of the DSX is  
realized by a differential 7-stage R-1.5R resistive ladder network  
with an untrimmed input resistance of 175 Ω single-ended or  
350 Ω differential. The signal applied at the input of the ladder  
network is attenuated by 6.908 dB per tap; thus, the attenuation  
at the first tap is 0 dB, at the second, 13.816 dB, and so on, all  
the way to the last tap where the attenuation is 48.356 dB  
(see Figure 41).  
–6.908dB  
R
R
–13.82dB  
R
R
–20.72dB  
R
R
–27.63dB  
R
R
–34.54dB  
R
R
–41.45dB  
R
R
–48.36dB  
R
+DSXx  
1.5R  
1.5R  
1.5R  
1.5R  
1.5R  
1.5R  
1.5R  
175Ω  
MID  
1.5R  
1.5R  
1.5R  
1.5R  
1.5R  
1.5R  
1.5R  
175Ω  
R
–DSXx  
NOTES  
1. R = 96Ω  
2. 1.5R = 144Ω  
Figure 41. R-1.5R Dual Ladder Network  
Rev. E | Page 15 of 32  
   
AD604  
From these equations, it can be seen that all gain curves intercept at  
the same −5 dB point; this intercept is +6 dB higher (+1 dB) if  
the preamplifier gain is set to +20 dB or +14 dB lower (−19 dB)  
if the preamplifier is not used at all. Outside the central linear  
range, the gain starts to deviate from the ideal control law but  
still provides another 8.4 dB of range. For a given gain scaling,  
AC COUPLING  
The DSX portion of the AD604 is a single-supply circuit and,  
therefore, its inputs need to be ac-coupled to accommodate  
ground-based signals. External Capacitors C1 and C2 in Figure 37  
level shift the ground referenced preamplifier output from  
ground to the dc value established by VOCM (nominal 2.5 V).  
C1 and C2, together with the 175 Ω looking into each of the  
DSX inputs (+DSXx and −DSXx), act as high-pass filters with  
corner frequencies depending on the values chosen for C1 and  
C2. As an example, for values of 0.1 μF at C1 and C2, combined  
with the 175 Ω input resistance at each side of the differential  
ladder of the DSX, the −3 dB high-pass corner is 9.1 kHz.  
VREF can be calculated as shown in Equation 7.  
2.500 V × 20 dB/V  
VREF =  
(7)  
Gain Scale  
Usable gain control voltage ranges are 0.1 V to 2.9 V for the  
20 dB/V scale and 0.1 V to 1.45 V for the 40 dB/V scale. VGN  
voltages of less than 0.1 V are not used for gain control because  
below 50 mV the channel (preamplifier and DSX) is powered  
down. This can be used to conserve power and, at the same  
time, to gate off the signal. The supply current for a powered-  
down channel is 1.9 mA; the response time to power the device  
on or off is less than 1 μs.  
If the AD604 output needs to be ground referenced, another  
ac coupling capacitor is required for level shifting. This  
capacitor also eliminates any dc offsets contributed by the DSX.  
With a nominal load of 500 Ω and a 0.1 μF coupling capacitor,  
this adds a high-pass filter with −3 dB corner frequency at about  
3.2 kHz.  
ACTIVE FEEDBACK AMPLIFIER (FIXED-GAIN AMP)  
The choice for all three of these coupling capacitors depends on  
the application. They should allow the signals of interest to pass  
unattenuated while, at the same time, they can be used to limit  
the low frequency noise in the system.  
To achieve single-supply operation and a fully differential input  
to the DSX, an active feedback amplifier (AFA) is used. The  
AFA is an op amp with two gm stages; one of the active stages is  
used in the feedback path (therefore the name), while the other  
is used as a differential input. Note that the differential input is  
an open-loop gm stage that requires it to be highly linear over  
the expected input signal range. In this design, the gm stage that  
senses the voltages on the attenuator is a distributed one; for  
GAIN CONTROL INTERFACE  
The gain control interface provides an input resistance of  
approximately 2 MΩ at VGN1 and gain scaling factors from  
20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to 1.25 V,  
respectively. The gain scales linearly in decibels for the center 40  
dB of gain range, which for VGN is equal to 0.4 V to 2.4 V for  
the 20 dB/V scale and 0.2 V to 1.2 V for the 40 dB/V scale. Figure  
42 shows the ideal gain curves for a nominal preamplifier gain  
of 14 dB, which are described by the following equations:  
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example, there are as many gm stages as there are taps on the  
ladder network. Only a few of them are on at any one time,  
depending on the gain control voltage.  
The AFA makes a differential input structure possible because  
one of its inputs (G1) is fully differential; this input is made up  
of a distributed gm stage. The second input (G2) is used for  
feedback. The output of G1 is some function of the voltages  
sensed on the attenuator taps, which is applied to a high-gain  
amplifier (A0). Because of negative feedback, the differential  
input to the high-gain amplifier has to be zero; this in turn  
implies that the differential input voltage to G2 times gm2 (the  
transconductance of G2) has to be equal to the differential  
input voltage to G1 times gm1 (the transconductance of G1).  
G (20 dB/V) = 20 × VGN – 5, VREF = 2.500 V  
G (20 dB/V) = 30 × VGN – 5, VREF = 1.666 V  
G (20 dB/V) = 40 × VGN – 5, VREF = 1.250 V  
(4)  
(5)  
(6)  
50  
45  
40  
35  
40dB/V  
30dB/V  
20dB/V  
Therefore, the overall gain function of the AFA is  
30  
25  
20  
15  
10  
5
VOUT  
g m1 R1 + R2  
=
×
(8)  
LINEAR-IN-dB RANGE  
OF AD604 WITH  
PREAMPLIFIER  
SET TO 14dB  
VATTEN  
g m2  
R2  
where:  
V
V
OUT is the output voltage.  
ATTEN is the effective voltage sensed on the attenuator.  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
(R1 + R2)/R2 = 42  
gm1/gm2 = 1.25  
–5  
GAIN CONTROL VOLTAGE (VGN)  
Figure 42. Ideal Gain Curves vs. VGN  
The overall gain is thus 52.5 (34.4 dB).  
Rev. E | Page 16 of 32  
     
AD604  
The AFA offers the following additional features:  
Under normal operating conditions, it is best to connect a  
decoupling capacitor to VOCM, in which case, the common-  
mode voltage of the DSX is half the supply voltage, which allows  
for maximum signal swing. Nevertheless, the common-mode  
voltage can be shifted up or down by directly applying a voltage  
to VOCM. It can also be used as another signal input, the only  
limitation being the rather low slew rate of the VOCM buffer.  
The ability to invert the signal by switching the positive  
and negative inputs to the ladder network  
The possibility of using DSX1 input as a second signal  
input  
Fully differential high-impedance inputs when both  
preamplifiers are used with one DSX (the other DSX could  
still be used alone)  
If the dc level of the output signal is not critical, another coupling  
capacitor is normally used at the output of the DSX; again, this  
is done for level shifting and to eliminate any dc offsets contributed  
by the DSX (see the AC Coupling section).  
Independent control of the DSX common-mode voltage  
www.BDTIC.com/ADI  
Rev. E | Page 17 of 32  
AD604  
APPLICATIONS INFORMATION  
The basic circuit in Figure 43 shows the connections for one  
channel of the AD604. The signal is applied at Pin 5. RGN is  
normally 0, in which case the preamplifier is set to a gain of 5  
(14 dB). When FBK1 is left open, the preamplifier is set to a  
gain of 10 (20 dB), and the gain range shifts up by 6 dB. The ac  
coupling capacitors before −DSX1 and +DSX1 should be selected  
according to the required lower cutoff frequency. In this example,  
the 0.1 μF capacitors, together with the 175 Ω seen looking into  
each of the DSXx input pins, provide a −3 dB high-pass corner  
of about 9.1 kHz. The upper cutoff frequency is determined by  
the bandwidth of the channel, which is 40 MHz. Note that the  
signal can be simply inverted by connecting the output of the  
preamplifier to −DSX1 instead of +DSX1; this is due to the fully  
differential input of the DSX.  
VREF requires a voltage of 1.25 V to 2.5 V, with between 40 dB/V  
and 20 dB/V gain scaling, respectively. Voltage VGN controls  
the gain; its nominal operating range is from 0.25 V to 2.65 V  
for 20 dB/V gain scaling and 0.125 V to 1.325 V for 40 dB/V  
scaling. When VGNx is grounded, the channel powers down  
and disables its output.  
COM1 is the main signal ground for the preamplifier and needs  
to be connected with as short a connection as possible to the input  
ground. Because the internal feedback resistors of the preamplifier  
are very small for noise reasons (8 Ω and 32 Ω nominally), it is  
of utmost importance to keep the resistance in this connection  
to a minimum. Furthermore, excessive inductance in this  
connection can lead to oscillations.  
Because of the ultralow noise and wide bandwidth of the  
AD604, large dynamic currents flow to and from the power  
supply. To ensure the stability of the part, careful attention to  
supply decoupling is required. A large storage capacitor in  
parallel with a smaller high-frequency capacitor connected at  
the supply pins, together with a ferrite bead coming from the  
supply, should be used to ensure high-frequency stability.  
0.1µF  
1
24  
23  
22  
21  
20  
19  
18  
VGN  
–DSX1  
+DSX1  
PAO1  
VGN1  
VREF  
OUT1  
2
3
+2.5V  
0.1µF  
0.1µF  
OUT  
RGN  
4
FBK1AD604 GND1  
R
L
V
5
IN  
PAI1  
VPOS  
VNEG  
VNEG  
500  
+5V  
–5V  
6
COM1  
COM2  
PAI2  
7
8
To provide for additional flexibility, COM1 can be used to  
disable the preamplifier. When COM1 is connected to VP, the  
preamplifier is off, yet the DSX portion can be used independently.  
This may be of value when cascading the two DSX stages in the  
AD604. In this case, the first DSX output signal with respect to  
VPOS 17  
9
16  
15  
14  
13  
FBK2  
PAO2  
+DSX2  
–DSX2  
GND2  
OUT2  
VOCM  
VGN2  
10  
11  
12  
0.1µF  
www.BDTIC.com/ADI  
noise is large and using the second preamplifier at this point  
Figure 43. Basic Connections for a Single Channel  
would waste power (see Figure 44).  
In Figure 43, the output is ac-coupled for optimum performance.  
For dc coupling, as shown in Figure 52, the capacitor can be  
eliminated if VOCM is biased at the same 3.3 V common-mode  
voltage as the analog-to-digital converter, AD9050.  
Rev. E | Page 18 of 32  
     
AD604  
C1  
0.1µF  
1
2
–DSX1  
+DSX1  
VGN1 24  
VREF 23  
OUT1 22  
VREF  
C2  
0.1µF  
AD604  
3
PAO1  
FBK1  
PAI1  
VSET (<0V)  
4
21  
20  
19  
18  
17  
16  
15  
14  
13  
GND1  
VPOS  
VNEG  
VNEG  
VPOS  
GND2  
OUT2  
VOCM  
VGN2  
5
R8  
VIN  
(MAX  
800mV p-p)  
+5V  
–5V  
–5V  
+5V  
C11  
1µF  
R1  
49.9  
2kΩ  
2
– (V1)  
1V  
6
COM1  
COM2  
PAI2  
R4  
C8  
LOW-  
PASS  
2kΩ  
0.33µF  
7
OFFS  
NULL  
FILTER  
1
2
3
8
7
6
5
NC  
+V  
+5V  
8
+5V  
V1 = V × G  
IN  
R7  
1kΩ  
S
8
7
6
5
AD711  
9
FBK2  
PAO2  
+DSX2  
–DSX2  
C7  
0.33µF  
X1  
X2 VP  
AD835  
W
OUT  
VG  
C10  
1µF  
10  
11  
12  
C3  
0.1µF  
OFFS  
NULL  
4
–5V  
–V  
S
C7  
0.1µF  
R3  
C6  
1kΩ  
Y1 Y2 VN  
Z
4
0.56µF  
2
– (A)  
1
2
3
R2  
IF V1 = A × cos (wt)  
453Ω  
2
C4  
0.1µF  
–5V  
R6  
2kΩ  
C9  
0.33µF  
R5  
2kΩ  
RF OUT  
FB  
FB  
+5V  
–5V  
C12  
0.1µF  
C13  
0.1µF  
ALL SUPPLY PINS ARE DECOUPLED AS SHOWN.  
Figure 44. AGC Amplifier with 82 dB of Gain Range  
Figure 45 and Figure 46 show the gain range and gain error for  
the AD604 connected as shown in Figure 44. The gain range is  
−14 dB to +82 dB; the useful range is 0 dB to +82 dB if the RF  
ULTRALOW NOISE AGC AMPLIFIER WITH 82 dB TO  
96 dB GAIN RANGE  
Figure 44 shows an implementation of an AGC amplifier with  
output amplitude is controlled to 400 mV (+2 dBm). The main  
82 dB of gain range using a single AD604. The signal is applied  
limitation on the lower end of the signal range is the input  
to connector VIN and, because the signal source is 50 Ω, a  
capability of  
terminating resistor (R1) of 49.9 Ω is added. The signal is then  
the preamplifier. This limitation can be overcome by adding an  
amplified by 14 dB (Pin FBK1 shorted to PAO1) through the  
attenuator in front of the preamplifier, but that would defeat the  
Channel 1 preamplifier and is further processed by the Channel 1  
advantage of the ultralow noise preamplifier. It should be noted  
DSX. Next, the signal is applied directly to the Channel 2 DSX. The  
that the second preamplifier is not used because its ultralow  
second preamplifier is powered down by connecting its COM2 pin  
noise and the associated high-power consumption are overkill  
to the positive supply as explained in the Preamplifier section.  
after the first DSX stage. It is disabled in this application by  
C1 and C2 level shift the signal from the preamplifier into the  
first DSX and, at the same time, eliminate any offset contribution  
of the preamplifier. C3 and C4 have the same offset cancellation  
purpose for the second DSX. Each set of capacitors, combined  
with the 175 Ω input resistance of the corresponding DSX,  
provides a high-pass filter with a −3 dB corner frequency of  
about 9.1 kHz. VOCM is decoupled to ground by a 0.1 μF  
capacitor, while VREF can be externally provided; in this  
application, the gain scale is set to 20 dB/V by applying 2.500 V.  
Because each DSX amplifier operates from a single 5 V supply,  
the output is ac-coupled via C6 and C7. The output signal can  
be monitored at the connector labeled RF OUT.  
connecting the COM2 pin to the positive supply. Nevertheless,  
the second preamplifier can be used, if so desired, and the  
useful gain range increases by 14 dB to encompass 0 dB to  
96 dB of gain. For the same +2 dBm output, this allows signals  
as small as −94 dBm to be measured.  
To achieve the highest gains, the input signal must be band-  
limited to reduce the noise; this is especially true if the second  
preamplifier is used. If the maximum signal at OUT2 of the AD604  
is limited to 400 mV (+2 dBm), the input signal level at the  
AGC threshold is +25 μV rms (−79 dBm). The circuit as shown in  
Figure 44 has about 40 MHz of noise bandwidth; the 0.8 nV/√Hz  
of input referred voltage noise spectral density of the AD604  
results in an rms noise of 5.05 μV in the 40 MHz bandwidth.  
Rev. E | Page 19 of 32  
   
AD604  
The 50 Ω termination resistor, in parallel with the 50 Ω source  
resistance of the signal generator, forms an effective resistance of  
25 Ω as seen by the input of the preamplifier, creating 4.07 μV of  
rms noise at a bandwidth of 40 MHz. The noise floor of this  
channel is consequently 6.5 μV rms, the rms sum of these two  
main noise sources. The minimum detectable signal (MDS) for  
this circuit is +6.5 μV rms (−90.7 dBm). Generally, the measured  
signal should be about a factor of three larger than the noise  
floor, in this case 19.5 μV rms. Note that the 25 μV rms signal  
that this AGC circuit can correct for is just slightly above the  
MDS. Of course, the sensitivity of the input can be improved by  
band-limiting the signal; if the noise bandwidth is reduced by a  
factor of four to 10 MHz, the noise floor of the AGC circuit with a  
50 Ω termination resistor drops to +3.25 μV rms (−96.7 dBm).  
Further noise improvement can be achieved by an input matching  
network or by transformer coupling of the input signal.  
90  
the incoming signal frequency, while passing the low frequency  
AM information. The following integrator with a time constant of  
2 ms set by R8 and C11 integrates the error signal presented by  
the low-pass filter and changes VG until the error signal is equal  
to VSET  
.
For example, if the signal presented to the detector is V1 = A ×  
cos(ωt) as indicated in Figure 44, the output of the squarer is  
−(V1)2/1 V. The reason for all the minus signs in the detection  
circuitry is the necessity of providing negative feedback in the  
control loop; actually, if VSET becomes greater than 0 V, the  
control loop provides positive feedback. Squaring A × cos(ωt)  
results in two terms, one at dc and one at 2ω; the following low-  
pass filter passes only the −(A)2/2 dc term. This dc voltage is  
now forced equal to the voltage, VSET, by the control loop. The  
squarer, together with the low-pass filter, functions as a mean-  
square detector. As should be evident by controlling the value of  
VSET, the amplitude of the voltage V1 can be set at the input of  
80  
the AD835; if VSET equals −80 mV, the AGC output signal  
amplitude is 400 mV.  
f = 1MHz  
70  
60  
50  
Figure 47 shows the control voltage, VGN, vs. the input power at  
frequencies of 1 MHz (solid line) and 10 MHz (dashed line) at  
an output regulated level of 2 dBm (800 mV p-p). The AGC  
threshold is evident at a PIN of about −79 dBm; the highest input  
power that can still be accommodated is about +3 dBm. At this  
level, the output starts being distorted because of clipping in the  
preamplifier.  
40  
30  
20  
10  
0
–10  
–20  
4.5  
www.BDTIC.com/ADI  
–30  
0.1  
0.5  
0.9  
1.3  
1.7  
2.1  
2.5  
2.9  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
VGN (V)  
Figure 45. Cascaded Gain vs. VGN (Based on Figure 44)  
4
f = 1MHz  
3
2
10MHz  
1MHz  
1
0
–1  
–2  
–3  
–4  
–80  
–70  
–60  
–50  
–40  
–30  
(dBm)  
–20  
–10  
0
10  
P
IN  
Figure 47. Control Voltage vs. Input Power of the Circuit in Figure 44  
As previously mentioned, the second preamplifier can be used  
to extend the range of the AGC circuit in Figure 44. Figure 48  
shows the modifications that must be made to Figure 46 to achieve  
96 dB of gain and dynamic range. Because of the extremely high  
gain, the bandwidth must be limited to reject some of the noise.  
Furthermore, limiting the bandwidth helps suppress high-  
frequency oscillations. The added components act as a low-pass  
filter and dc block (C5 decouples the 2.5 V common-mode  
output of the first DSX). The ferrite bead has an impedance of  
about 5 Ω at 1 MHz, 30 Ω at 10 MHz, and 70 Ω at 100 MHz.  
The bead, combined with R2 and C6, forms a 1 MHz low-pass  
filter.  
0.2  
0.7  
1.2  
1.7  
2.2  
2.7  
VGN (V)  
Figure 46. Cascaded Gain Error vs. VGN (Based on Figure 44)  
The descriptions of the detector circuitry functions, comprising  
a squarer, a low-pass filter, and an integrator, follow. At this  
point, it is necessary to make some assumptions about the input  
signal. The following explanation of the detector circuitry presumes  
an amplitude modulated RF carrier where the modulating signal is  
at a much lower frequency than the RF signal. The AD835  
multiplier functions as the detector by squaring the output signal  
presented to it by the AD604. A low-pass filter following the  
squaring operation removes the RF signal component at twice  
Rev. E | Page 20 of 32  
     
AD604  
At 1 MHz, the attenuation is about −0.2 dB, increasing to −6 dB  
at 10 MHz and −28 dB at 100 MHz. Signals less than approximately  
1 MHz are not significantly affected.  
the signal amplitude compared with when they are driven  
single-ended.  
AD604  
Figure 49 shows the control voltage vs. the input power at 1 MHz to  
the circuit shown in Figure 48; note that the AGC threshold is at  
−95 dBm. The output signal level is set to 800 mV p-p by applying  
−80 mV to the VSET connector.  
1
2
3
4
5
6
7
8
9
24  
23  
22  
–DSX1  
VGN1  
VREF  
OUT1  
VREF  
C1  
C2  
+DSX1  
PAO1  
0.1µF  
0.1µF  
VOUT+  
R1  
C7  
FBK1  
PAI1  
GND1 21  
453  
0.1µF  
VIN+  
VPOS  
VNEG  
20  
19  
+5V  
–5V  
–5V  
+5V  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
–DSX1  
+DSX1  
PAO1  
FBK1  
VGN1  
VREF  
OUT1  
GND1  
COM1  
COM2  
PAI2  
VNEG 18  
3
VIN–  
C4  
VPOS  
17  
C6  
0.1µF  
4
R2  
453Ω  
16  
FBK2  
GND2  
5
PAI1 AD604 VPOS  
15  
VOUT–  
VG  
10 PAO2  
OUT2  
C3  
0.1µF  
0.1µF  
6
COM1  
COM2  
PAI2  
VNEG  
VNEG  
VPOS  
GND2  
OUT2  
VOCM  
VGN2  
11  
12  
14  
+DSX2  
–DSX2  
VOCM  
7
13  
VGN2  
R2  
499Ω  
C6  
560pF  
C5  
0.1µF  
8
9
FBK2  
PAO2  
+DSX2  
–DSX2  
FB  
FB  
+5V  
–5V  
10  
11  
12  
C3  
0.1µF  
C5  
0.1µF  
C13  
0.1µF  
C12  
0.1µF  
ALL SUPPLY PINS ARE DECOUPLED AS SHOWN.  
FB  
Figure 50. Ultralow Noise, Differential Input-Differential Output VGA  
FAIR-RITE  
Figure 51 displays the output signals VOUT+ and VOUT− after  
a −20 dB attenuator formed between the 453 Ω resistors shown  
in Figure 50 and the 50 Ω loads presented by the oscilloscope  
plug-in. R1 and R2 are inserted to ensure a nominal load of 500 Ω  
at each output. The differential gain of the circuit is set to 20 dB  
by applying a control voltage, VGN, of 1 V; the gain scaling is  
20 dB/V for a VREF of 2.500 V; the input frequency is 10 MHz,  
and the differential input amplitude is 100 mV p-p. The resulting  
differential output amplitude is 1 V p-p as can be seen on the  
scope photo when reading the vertical scale as 200 mV/div.  
#2643000301  
Figure 48. Modifications of the AGC Amplifier to Create 96 dB of Gain Range  
4.5  
4.0  
3.5  
3.0  
www.BDTIC.com/ADI  
2.5  
2.0  
1.5  
1.0  
0.5  
0
1MHz  
20mV  
20ns  
ACTUAL  
V
OUT  
+500mV  
100  
90  
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10  
0
10  
P
(dBm)  
IN  
Figure 49. Control Voltage vs. Input Power of the Circuit in Figure 48  
ULTRALOW NOISE, DIFFERENTIAL INPUT-  
DIFFERENTIAL OUTPUT VGA  
10  
–500mV  
0%  
Figure 50 shows how to use both preamplifiers and DSXs to  
create a high impedance, differential input-differential output  
VGA. This application takes advantage of the differential inputs  
to the DSXs. Note that the input is not truly differential in the  
sense that the common-mode voltage needs to be at ground to  
achieve maximum input signal swing. This has largely to do  
with the limited output swing capability of the output drivers of  
the preamplifiers; they clip around 2.2 V due to having to drive  
an effective load of about 30 Ω. If a different input common-mode  
voltage needs to be accommodated, ac coupling (as in Figure 48)  
is recommended. The differential gain range of this circuit runs  
from 6 dB to 54 dB, which is 6 dB higher than each individual  
channel of the AD604 because the DSX inputs now see twice  
20mV  
NOTES  
1. THE OUTPUT AFTER 10× ATTENUATER FORMED  
BY 453TOGETHER WITH 50OF 7A24 PLUG-IN.  
Figure 51. Output of VGA in Figure 50 for VGN = 1 V  
Rev. E | Page 21 of 32  
           
AD604  
The gain is controlled by means of a digital byte that is input to  
an AD7226 DAC that outputs the analog gain control signal.  
The output common-mode voltage of the AD604 is set to VPOS/2  
by means of an internal voltage divider. The VOCM pin is  
bypassed with a 0.1 μF capacitor to ground.  
MEDICAL ULTRASOUND TGC DRIVING THE  
AD9050, A 10-BIT, 40 MSPS ADC  
The AD604 is an ideal candidate for the time gain control (TGC)  
amplifier that is required in medical ultrasound systems to limit  
the dynamic range of the signal that is presented to the ADC.  
Figure 52 shows a schematic of an AD604 driving an AD9050  
in a typical medical ultrasound application.  
The DSX output is optionally filtered and then buffered by  
an AD9631 op amp, a low distortion, low noise amplifier. The  
op amp output is ac-coupled into the self-biasing input of an  
AD9050 ADC that is capable of outputting 10 bits at a 40 MSPS  
sampling rate.  
15  
16  
17  
18  
19  
24  
25  
26  
27  
28  
20  
22  
(MSB) D9  
0.1µF  
0.1µF  
D8  
D7  
AD9050  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
–DSX1  
+DSX1  
PAO1  
FBK1  
PAI1  
VGN1  
VREF  
OUT1  
GND1  
VPOS  
VNEG  
VNEG  
VPOS  
GND2  
3
4
VREF  
OUT  
1kΩ  
1kΩ  
0.1µF  
VREF  
D6  
3
IN  
FILTER  
5
D5  
4
COMP  
J2  
A/D  
OUTPUT  
ANALOG  
INPUT  
6
D4  
5
REF  
BP  
+5V  
0.1µF  
AD9631  
2
3
9
AINB  
D3  
6
0.1µF  
COM1  
COM2  
PAI2  
–IN  
+IN  
6
50Ω  
50Ω  
10  
13  
14  
OUT  
AIN  
D2  
7
–5V  
0.1µF  
ENCODE  
D1  
8
OR  
(LSB) D0  
9
FBK2  
PAO2  
+DSX2  
OPTIONAL  
V
10  
11  
OUT2 15  
VOCM 14  
VGN2 13  
0.1µF  
DD  
0.1µF  
V
DD  
12 –DSX2  
0.1µF  
1kΩ  
AD604  
CLK  
100Ω  
0.1µF  
0.1µF  
0.1µF  
www.BDTIC.com/ADI  
20  
19  
18  
17  
16  
1
V
B
V
C
OUT  
OUT  
2
V
V
V
A
V
D
OUT  
OUT  
V
3
+15V  
SSAD7226  
DD  
A0  
A1  
4
VREF  
REF  
5
AGND  
DGND  
WR 15  
6
DB7  
(MSB)  
DB0  
14  
7
(LSB)  
8
13  
DB6  
DB5  
DB4  
DB1  
DB2 12  
11  
9
10  
DB3  
DIGITAL GAIN CONTROL  
Figure 52. TGC Circuit for Medical Ultrasound Application  
Rev. E | Page 22 of 32  
     
AD604  
C3  
0.1µF  
VG1  
1
2
VGN1 24  
VREF 23  
OUT1 22  
GND1 21  
–DSX1  
+DSX1  
PAO1  
FBK1  
PAI1  
VREF  
OUT1  
C1  
C4  
0.1µF  
0.1µF  
3
PAO1  
IN1  
C2  
R1  
NOTE 2 R2  
RGN  
5pF  
500Ω  
4
NOTE 3  
C12  
0.1µF  
AD604  
OPTIONAL  
5
VPOS  
VNEG  
VNEG  
VPOS  
GND2  
OUT2  
VOCM  
VGN2  
20  
19  
18  
17  
16  
15  
14  
13  
C11  
0.1µF  
+5V  
6
COM1  
COM2  
PAI2  
7
–5V  
C10  
0.1µF  
8
IN2  
C9  
0.1µF  
NOTE 3  
9
FBK2  
PAO2  
C8  
5pF  
R3  
RGN  
R4  
500Ω  
OUT2  
PAO2  
10  
C7  
0.1µF  
C6  
0.1µF  
11 +DSX2  
12 –DSX2  
VOCM  
VG2  
0.1µF  
C5  
0.1µF  
NOTES  
1. PAO1 AND PAO2 ARE USED TO MEASURE PREAMPS.  
2. RGN = 0 NOMINALLY; PREAMP GAIN = 5, RGN = OPEN; PREAMP GAIN = 10.  
3. WHEN MEASURING BW WITH 50SPECTRUM ANALYZER, USE 450IN SERIES.  
Figure 53. Basic Test Board  
HP3577B  
OUT  
R
A
HP11636B  
POWER  
SPLITTER  
www.BDTIC.com/ADI  
50  
0.1µF  
450Ω  
PAI  
AD604  
DUT  
49.9Ω  
Figure 54. Setup for Gain Measurements  
Rev. E | Page 23 of 32  
AD604  
EVALUATION BOARD  
Figure 55 is a photograph of the AD604 evaluation board assembly.  
Multiple input connections, test points, jumper selectable options,  
and on-board trims offer convenience when configuring the  
AD604 in various operating modes.  
The evaluation board requires only a dual 5 V supply capable of  
200 mA or higher to operate both channels. Prior to shipment,  
the evaluation board is fully tested. Users need only attach  
power supply leads and the appropriate test equipment to  
the board.  
Because of this flexibility, not all component positions on the  
board are populated when the board is shipped. Installing or  
changing additional parts is optional.  
The AD604-EVALZ is fabricated on a 4-layer board with inner  
power and ground layers. The AD604 is a stable, trouble-free  
device; however, as with all high-frequency integrated circuits,  
power and ground planes help to ensure consistency in  
performance.  
Figure 56. AD604 Evaluation Board—Component Side Silk Screen  
DSX INPUT CONNECTIONS  
The DSX inputs can be connected in single-ended or differential  
www.BDTIC.com/ADI  
configurations. SMA connectors are provided for each of the  
inputs and are labeled CHx VGA IN (+) and CHx VGA IN (−).  
JP6 and JP15 select between the preamplifier outputs and the  
DSX inputs.  
For direct drive of the Channel 1 VGA, insert a jumper in the  
top position of JP6. For direct drive of the Channel 2 VGA,  
insert a jumper in JP14 and verify that there are no jumpers in  
JP12 and JP13. Refer to the schematic shown in Figure 61 for  
circuit details.  
Differential DSX Inputs  
Differential inputs are possible using both polarities of the  
VGA SMA connectors and appropriate jumpers. Inserting a  
jumper in the lower position of JP5 selects the negative input  
Figure 55. AD604 Evaluation Board Assembly  
of Channel 1. A jumper in the top position of JP6 selects the  
USING THE PREAMPLIFIER  
positive input of Channel 1. A jumper in the JP16 rightmost  
position selects the negative input of Channel 2, and a jumper  
in JP14 selects the positive input. Verify that there are no jumpers  
in JP15 or JP13.  
To use the preamplifiers, simply connect a signal source to CH1  
PREAMP IN and/or CH2 PREAMP IN via the SMA connectors.  
Referring to the schematic in Figure 61, the input lines are  
terminated with 50 Ω resistors at locations R7 and R8.  
Because the VGA section of the AD604 uses a single 5 V supply,  
the DSX inputs are ac-coupled. Decoupling capacitors are provided  
on the evaluation board.  
To enable the preamplifiers, insert jumpers in the JP8 and JP9  
rightmost positions; this connects COM1 and COM2 to ground.  
Power down the preamplifiers by inserting jumpers in the JP8  
and JP9 leftmost positions.  
The DSX input impedance is approximately 200 Ω. Optional  
66.5 Ω resistors can be installed across the inputs at positions  
R5, R6, R9, and R10 to establish a 50 Ω terminating load.  
Rev. E | Page 24 of 32  
   
AD604  
Connecting the DSX Inputs to the Preamplifiers  
OUTPUTS  
To connect the DSX inputs to the preamplifiers, install jumpers  
in the JP6 lower position and in JP15. Verify that the jumpers in  
JP13 and JP14 are removed.  
The DSX outputs are available on OUT1 and OUT2 SMA  
connectors and are series terminated with decoupling capacitors  
and 49.9 Ω series resistors. These components can be replaced  
to accommodate other output impedances.  
Cascaded DSX  
DC OPERATING CONDITIONS  
To channel-cascade the two channels, insert a jumper in JP13.  
The resulting single-channel gain range is 96 dB. Verify that  
JP14 and JP15 are removed.  
Table 4 lists the trimmers and their functions provided for  
convenient dc level adjustments of gain, reference voltage,  
and output common-mode voltage. Table 5 lists the jumpers  
and their functions.  
The gains of cascaded VGAs can be controlled independently  
or in common. For common control, insert a jumper in the top  
position of JP4. To use the trimmer as a gain control, insert a  
jumper in JP1. For external control, remove JP1 and connect a  
signal source at VGN1 or VGN2 test loop.  
Table 4. Trimmer Functions  
Trimmer  
Function  
R1  
R2  
R3  
R4  
Gain of Channel 1  
PREAMPLIFIER GAIN  
Reference voltage adjustment  
Output common-mode voltage adjustment  
Channel 2 gain adjustment  
Jumpers in JP7 and JP12 select between two preamplifier gains:  
14 dB and 20 dB. Intermediate gains are derived by installing  
resistors in the R11 and R12 positions. The 14 dB and 20 dB  
preset gains are accurate due to close matching of thin film  
resistors. The gain accuracy after installing external resistors is  
subject to inherent tolerance of absolute accuracy.  
Table 5. Jumpers  
Jumper No.  
Function  
1
2
3
4
5
6
7
8
9
12  
13  
14  
15  
16  
Connects R1 gain adjust wiper to VGN1.  
Connects R2 reference voltage trimmer to VREF input.  
www.BDTIC.com/ADI  
Connects common-mode voltage trimmer to VOCM.  
Connects VGN2 to R4 Channel 2 gain trimmer or to VGN1 or common gain adjustment.  
Connects –DSX1 to CH1 VGA IN (−) or to ground.  
Connects +DSX1 (ac-coupled) to preamplifier output of Channel 1 or to the CH 1 VGA IN (+) SMA connector.  
When open, the Preamp 1 gain is 20 dB; Preamp 1 gain is 14 dB when a shunt is installed.  
Shunt in left position disables Preamp 1; shunt in rightmost position enables Preamp 1.  
Shunt in left position disables Preamp 2; shunt in rightmost position enables Preamp 2.  
When open, the Preamp 2 gain is 20 dB; Preamp 2 gain is 14 dB when a shunt is installed.  
Cascades DSX2 with DSX 1 when a jumper is inserted.  
Connects +DSX2 (ac-coupled) to preamplifier output of Channel 2 or to the CH 2 VGA IN (+) SMA connector.  
Connects +DSX2 (ac-coupled) to preamplifier output of Channel 2.  
Connects –DSX2 to CH2 VGA IN (−) or to ground.  
Rev. E | Page 25 of 32  
     
AD604  
EVALUATION BOARD ARTWORK AND SCHEMATIC  
Figure 57. Component Side Copper  
Figure 59. Internal Ground Plane  
www.BDTIC.com/ADI  
Figure 58. Secondary Side Copper  
Figure 60. Internal Power Plane  
Rev. E | Page 26 of 32  
 
AD604  
+5V  
J1  
GND1 GND2 GND3 GND4  
CH1 VGA  
IN (–)  
–DSX1  
GN1  
ADJ  
R1  
10kΩ  
C8  
JP5  
0.1µF  
A
VREF  
JP1  
R5  
+5V  
B
AD604  
VGN1  
JP2  
J2  
U1  
VREF  
ADJ  
R2  
10kΩ  
CH1 VGA  
IN (+)  
+DSX1  
1
2
3
4
5
6
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
–DSX1  
+DSX1  
PAO1  
FBK1  
PAI1  
VGN1  
VREF  
OUT1  
C9  
JP6  
C5  
0.1µF  
1nF  
A
C13  
0.1µF  
R6  
C6  
0.1µF  
B
PAO1  
OUT1  
+5V  
J3  
OUT1  
R13  
49.9Ω  
R11  
JP8  
JP7  
J5  
CH 1 PREAMP  
IN  
GND1  
VPOS  
PAI1  
+5V  
+5V  
GND  
–5V  
–5V  
R7  
49.9Ω  
COM1  
COM2  
PAI2  
VNEG  
VNEG  
VPOS  
GND2  
OUT2  
VOCM  
VGN2  
C4  
0.1µF  
C3  
10µF  
10V  
JP9  
+
J6  
CH 2 PREAMP  
IN  
7
8
PAI2  
C1  
10µF  
10V  
+
C2  
0.1µF  
R8  
49.9Ω  
JP12  
PAO2  
9
FBK2  
PAO2  
+DSX2  
–DSX2  
C14  
0.1µF  
R14  
49.9Ω  
R12  
OUT2  
JP15  
J7  
10  
J4  
OUT2  
CH2 VGA  
IN (+)  
+DSX2  
VOCM  
JP14  
11  
12  
+5V  
C7  
0.1µF  
JP13  
C10  
0.1µF  
R9  
JP3  
R3 VOCM  
1kADJ  
J8  
CH1 VGA  
IN (–)  
–DSX2  
JP16  
C11  
0.1µF  
VGN2  
JP4  
+5V  
A
B
A
B
GN2  
ADJ  
R10  
R4  
C12  
1nF  
1kΩ  
NOTES  
1. PARTS IN GRAY ARE NOT INSTALLED.  
Figure 61. Evaluation Board Schematic  
www.BDTIC.com/ADI  
Table 6. Bill of Materials  
Qty. Type  
Description  
Reference Designator  
Manufacturer  
Part Number  
TP-104-01-02  
TP-104-01-06  
TP-104-01-00  
TP-104-01-07  
1
1
5
14  
Test loop  
Red  
Blue  
Black  
Purple  
+5 V  
−5 V  
Components Corp.  
Components Corp.  
Components Corp.  
Test loop  
Test loop  
Test loop  
GND, GND1, GND2, GND3, GND4  
+DSX1, +DSX2, −DSX1, −DSX2, OUT1, OUT2, PAI1, Components Corp.  
PAI2, PAO1, PAO2, VGN1, VGN2, VOCM, VREF  
2
10  
2
8
8
6
4
4
Capacitor  
Capacitor  
Capacitor  
Tantalum 10 μF, 10 V, A size C1, C3  
Nichicon  
Panasonic  
Panasonic  
Amphenol  
Berg  
Molex  
Bourns  
Panasonic  
F931A106MAA  
PCC1840CT-ND  
ECU-V1H102KBN  
901-143-6RFX  
69157-2  
22-11-2032  
3361P-1-103G  
ERJ-6ENF49R9  
0.1 μF, 50 V, 20%, 0805  
C2, C4, C6, C7, C8, C9, C10, C11, C13, C14  
SM, 1000 pF, 50 V, 0805  
C5, C12  
Connector SMA FEM PC Mount, RA  
J1, J2, J3, J4, J5, J6, J7, J8  
JP1, JP2, JP3, JP7, JP12, JP13, JP14, JP15  
JP4, JP5, JP6, JP8, JP9, JP16  
R1, R2, R3, R4  
Header  
Header  
Trimmer  
Resistor  
0.1center 2-pin  
0.1center 3-pin  
10 kΩ, 1/4" SM  
49.9 Ω, 1%, 1/10 W, 0805  
R7, R8, R13, R14  
1
Integrated 40 MHz dual low  
U1  
Analog Devices, Inc. AD604AR  
circuit  
noise VGA  
10  
Jumper  
Mini jumper; install in  
headers at JP1, JP2, JP3,  
JP4 lower, JP5 lower, JP6  
lower, JP8 right, JP9 right,  
JP15, JP16 left  
Rev. E | Page 27 of 32  
 
AD604  
OUTLINE DIMENSIONS  
1.280 (32.51)  
1.250 (31.75)  
1.230 (31.24)  
24  
1
13  
12  
0.280 (7.11)  
0.250 (6.35)  
0.240 (6.10)  
0.325 (8.26)  
0.310 (7.87)  
0.300 (7.62)  
0.100 (2.54)  
BSC  
0.060 (1.52)  
MAX  
0.195 (4.95)  
0.130 (3.30)  
0.115 (2.92)  
0.210 (5.33)  
MAX  
0.015  
(0.38)  
MIN  
0.150 (3.81)  
0.130 (3.30)  
0.115 (2.92)  
0.015 (0.38)  
GAUGE  
0.014 (0.36)  
0.010 (0.25)  
0.008 (0.20)  
PLANE  
SEATING  
PLANE  
0.022 (0.56)  
0.018 (0.46)  
0.014 (0.36)  
0.430 (10.92)  
MAX  
0.005 (0.13)  
MIN  
0.070 (1.78)  
0.060 (1.52)  
0.045 (1.14)  
COMPLIANT TO JEDEC STANDARDS MS-001  
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.  
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.  
Figure 62. 24-Lead Plastic Dual In-Line Package [PDIP]  
Narrow Body  
(N-24-1)  
Dimensions shown in inches and (millimeters)  
www.BDTIC.com/ADI  
15.60 (0.6142)  
15.20 (0.5984)  
24  
13  
7.60 (0.2992)  
7.40 (0.2913)  
1
10.65 (0.4193)  
10.00 (0.3937)  
12  
0.75 (0.0295)  
0.25 (0.0098)  
45°  
2.65 (0.1043)  
2.35 (0.0925)  
0.30 (0.0118)  
0.10 (0.0039)  
8°  
0°  
COPLANARITY  
0.10  
SEATING  
PLANE  
0.51 (0.0201)  
0.31 (0.0122)  
1.27 (0.0500)  
BSC  
1.27 (0.0500)  
0.40 (0.0157)  
0.33 (0.0130)  
0.20 (0.0079)  
COMPLIANT TO JEDEC STANDARDS MS-013-AD  
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.  
Figure 63. 24-Lead Standard Small Outline Package [SOIC_W]  
Wide Body  
(RW-24)  
Dimensions shown in millimeters and (inches)  
Rev. E | Page 28 of 32  
 
AD604  
8.50  
8.20  
7.90  
13  
12  
24  
5.60  
5.30  
5.00  
8.20  
7.80  
7.40  
1
0.25  
0.09  
1.85  
1.75  
1.65  
2.00 MAX  
8°  
4°  
0°  
0.95  
0.75  
0.55  
0.38  
0.22  
0.05 MIN  
SEATING  
PLANE  
COPLANARITY  
0.10  
0.65 BSC  
COMPLIANT TO JEDEC STANDARDS MO-150-AG  
Figure 64. 24-Lead Shrink Small Outline Package [SSOP]  
(RS-24)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model  
AD604AN  
Temperature Range  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
Package Description  
Package Option  
24-Lead Plastic Dual In-Line Package [PDIP]  
24-Lead Plastic Dual In-Line Package [PDIP]  
24-Lead Standard Small Outline Package [SOIC_W]  
24-Lead Standard Small Outline Package [SOIC_W]  
24-Lead Standard Small Outline Package [SOIC_W]  
24-Lead Standard Small Outline Package [SOIC_W]  
24-Lead Shrink Small Outline Package [SSOP]  
24-Lead Shrink Small Outline Package [SSOP]  
24-Lead Shrink Small Outline Package [SSOP]  
24-Lead Shrink Small Outline Package [SSOP]  
24-Lead Shrink Small Outline Package [SSOP]  
24-Lead Shrink Small Outline Package [SSOP]  
Evaluation Board  
N-24-1  
N-24-1  
RW-24  
RW-24  
RW-24  
RW-24  
RS-24  
RS-24  
RS-24  
RS-24  
RS-24  
RS-24  
AD604AR  
AD604AR-REEL  
AD604ARZ-RL1  
AD604ARS  
AD604ARS-REEL  
AD604ARS-REEL7  
AD604ARSZ-RL1  
AD604ARSZ-R71  
AD604-EVALZ1  
1 Z = RoHS Compliant Part.  
Rev. E | Page 29 of 32  
     
AD604  
NOTES  
www.BDTIC.com/ADI  
Rev. E | Page 30 of 32  
AD604  
NOTES  
www.BDTIC.com/ADI  
Rev. E | Page 31 of 32  
AD604  
NOTES  
www.BDTIC.com/ADI  
©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D00540-0-10/08(E)  
Rev. E | Page 32 of 32  
 

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