ML605 Hardware
User Guide
UG534 (v1.2.1) January 21, 2010
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Table of Contents
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Related Xilinx Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1. Virtex-6 XC6VLX240T-1FFG1156 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2. 512 MB DDR3 Memory SODIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. 128 Mb Platform Flash XL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4. 32 MB Linear BPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ML605 Flash Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5. System ACE CF and CompactFlash Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6. USB JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Oscillator (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Oscillator Socket (Single-Ended, 2.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SMA Connectors (Differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8. Multi-Gigabit Transceivers (GTX MGTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9. PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. SFP Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SGMII GTX Transceiver Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13. USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
14. DVI Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
15. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8 Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
16. Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Ethernet PHY Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
FPGA INIT and DONE LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
17. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
User LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
User Pushbutton Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
User SMA GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LCD Display (16 Character x 2 Lines). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
18. Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Power On/Off Slide Switch SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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FPGA_PROG_B Pushbutton SW4 (Active-Low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SYSACE_RESET_B Pushbutton SW3 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
19. VITA 57.1 FMC HPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
20. VITA 57.1 FMC LPC Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
21. Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
AC Adapter and Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Onboard Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
22. System Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4
ML605 Hardware User Guide
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Preface
About This Guide
This manual accompanies the Virtex®-6 FPGA ML605 Evaluation Board and contains
information about the ML605 hardware and software tools.
Guide Contents
This manual contains the following chapters:
•
Chapter 1, “ML605 Evaluation Board,” provides an overview of the embedded
development board and details the components and features of the ML605 board.
•
•
•
•
Additional Documentation
The following documents are also available for download at
•
Virtex-6 Family Overview
The features and product selection of the Virtex-6 family are outlined in this overview.
•
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-6 family.
•
•
Virtex-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
Virtex-6 FPGA Configuration Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
•
Virtex-6 FPGA Clocking Resources User Guide
This guide describes the clocking resources available in all Virtex-6 devices, including
the MMCM and PLLs.
ML605 Hardware User Guide
5
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Preface: About This Guide
•
•
•
Virtex-6 FPGA Memory Resources User Guide
The functionality of the block RAM and FIFO are described in this user guide.
Virtex-6 FPGA SelectIO Resources User Guide
This guide describes the SelectIO™ resources available in all Virtex-6 devices.
Virtex-6 FPGA GTX Transceivers User Guide
This guide describes the GTX transceivers available in all Virtex-6 FPGAs except the
XC6VLX760.
•
•
•
•
Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in all Virtex-6 FPGAs except the XC6VLX760.
Virtex-6 FPGA DSP48E1 Slice User Guide
This guide describes the architecture of the DSP48E1 slice in Virtex-6 FPGAs and
provides configuration examples.
Virtex-6 FPGA System Monitor User Guide
The System Monitor functionality available in all Virtex-6 devices is outlined in this
guide.
Virtex-6 FPGA PCB Design Guide
This guide provides information on PCB design for Virtex-6 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
Additional Support Resources
To search the database of silicon and software questions and answers or to create a
technical support case in WebCase, see the Xilinx website at:
6
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Chapter 1
ML605 Evaluation Board
Overview
The ML605 board enables hardware and software developers to create or evaluate designs
targeting the Virtex®-6 XC6VLX240T-1FFG1156 FPGA.
The ML605 provides board features common to many embedded processing systems.
Some commonly used features include: a DDR3 SODIMM memory, an 8-lane PCI
Express® interface, a tri-mode Ethernet PHY, general purpose I/O, and a UART.
Additional user desired features can be added through mezzanine cards attached to the
onboard high-speed VITA-57 FPGA Mezzanine Connector (FMC) high pin count (HPC)
expansion connector, or the onboard VITA-57 FMC low pin count (LPC) connector.
“Features,” page 8 provides a general listing of the board features with details provided in
Additional Information
Additional information and support material is located at:
This information includes:
•
•
•
Current version of this user guide in PDF format
Example design files for demonstration of Virtex-6 FPGA features and technology
Demonstration hardware and software configuration files for the System ACE™ CF
controller, Platform Flash configuration storage device, and linear flash chip
•
•
•
•
•
Reference design files
Schematics in PDF and DxDesigner formats
Bill of materials (BOM)
Printed-circuit board (PCB) layout in Allegro PCB format
Gerber files for the PCB (Many free or shareware Gerber file viewers are available on
the internet for viewing and printing these files.)
•
Additional documentation, errata, frequently asked questions, and the latest news
For information about the Virtex-6 family of FPGA devices, including product highlights,
data sheets, user guides, and application notes, see the Virtex-6 FPGA documentation page
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Chapter 1: ML605 Evaluation Board
Features
The ML605 provides the following features:
•
•
•
•
•
•
•
♦
♦
♦
♦
Fixed 200 MHz oscillator (differential)
Socketed 2.5V oscillator (single-ended)
SMA connectors (differential)
SMA connectors for MGT clocking
•
♦
♦
♦
♦
♦
♦
FMC - HPC connector
FMC - LPC connector
SMA
PCIe
SFP Module connector
Ethernet PHY SGMII interface
•
♦
♦
Gen1 8-lane (x8)
Gen2 4-lane (x4)
•
•
•
•
•
•
♦
♦
♦
♦
♦
♦
♦
IIC EEPROM - 1 KB
DDR3 SODIMM socket
DVI CODEC
DVI connector
FMC HPC connector
FMC LPC connector
SFP module connector
8
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Overview
•
•
♦
♦
♦
♦
Ethernet status
FPGA INIT
FPGA DONE
System ACE CF Status
♦
♦
♦
♦
♦
♦
♦
USER LED Group 1 - GPIO (8)
USER LED Group 2 - directional (5)
User pushbuttons - directional (5)
CPU reset pushbutton
User DIP switch - GPIO (8-pole)
User SMA GPIO connectors (2)
LCD character display (16 characters x 2 lines)
•
♦
♦
♦
♦
Power on/off slide switch
System ACE CF reset pushbutton
System ACE CF bitstream image select DIP switch
Configuration MODE DIP switch
•
•
•
♦
♦
PMBus voltage and current monitoring via TI power controller
•
♦
♦
♦
♦
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Chapter 1: ML605 Evaluation Board
Block Diagram
Figure 1-1 shows a high-level block diagram of the ML605 and its peripherals.
X-Ref Target Figure 1-1
-
JTAG USB Mini-B
USB JTAG Circuit
System ACE CF
S.A. CompactFlash
S.A. 8-bit MPU I/F
VITA 57.1 FMC
HPC Connector
VITA 57.1 FMC
LPC Connector
BANK32
BANK12, 13 BANK15,16
BANK14,22 BANK34,116
BANK23,24
SYSMON I/F
INIT, DONE LEDs
PROG PB, MODE SW
Platform Flash
Linear BPI Flash
BANK24
BANK34
BANK112,113
BANK0
IIC Bus
IIC EEPROM
FMC HPC
BANK33
BANK34
DVI Codec
VGA Video
DVI Video Connector
BANK32
BANK33
Virtex-6
FPGA
DDR3 SODIMM IIC
FMC LPC
XC6VLX240T - 1FFG1156
10/100/1000
Ethernet PHY
MII/GMII/RMII
SFP Module
Connector
SGMII
BANK116
BANK 25, 35
BANK 26, 36
BANK114
BANK115
SODIMM Socket
204-pin, DDR3
Decoupling Caps
PCIe X8 Edge Connector
MGT SMA REF Clock
MGT RX/TX SMA Port
BANK14, 33, 36 BANK24,34
BANK14
BANK24
User LED/SW
User DIP SW
User LCD
200 MHz LVDS Clock
SMA Clock
User S.E. 2.5V Clock
USB Controller
Host Type “A”
Peripheral Mini-B
Connectors
CP2103 USB-TO-UART
Bridge
MEM Vterm
Regulator
USB Mini-B
UG534_01_092709
Figure 1-1: ML605 High-Level Block Diagram
Related Xilinx Documents
Prior to using the ML605 Evaluation Board, users should be familiar with Xilinx resources.
locations for additional documentation on Xilinx tools and solutions:
•
•
•
•
ISE: www.xilinx.com/ise
Intellectual Property: www.xilinx.com/ipcenter
Answer Browser: www.xilinx.com/support
10
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Detailed Description
Detailed Description
the section headings in this document.
X-Ref Target Figure 1-2
-
18a
13
20
19
16c
13
17a
21c
23
10
7b
7c
17e
18d
18c
17d
16b
21d
5
2
18b
12
6
7d
16a
1
22
21a
21b
11
8
3
17f
17c
21a
14
8
4
17b
7a
9
(on backside)
15
UG534_02_123009
Figure 1-2: ML605 Board Photo
Table 1-1: ML605 Features
Schematic
Number
Feature
Virtex-6 FPGA
Notes
Page
2 - 12
15
1
2
3
4
XC6VLX240T-1FFG1156
DDR3 SODIMM
Micron 512 MB MT4JSF6464HY-1G1
Xilinx XCF128X-FTG64C
128 Mb Platform Flash XL
Linear BPI Flash
25
Numonyx JS28F256P30T95
26
System ACE CF controller, CF Xilinx XCCACE-TQ144I
5
6
13
46
connector
(bottom of board)
JTAG cable connector (USB
Mini-B)
USB JTAG download circuit
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Chapter 1: ML605 Evaluation Board
Table 1-1: ML605 Features (Cont’d)
Schematic
Page
Number
Feature
Notes
200 MHz OSC, oscillator socket, SMA
connectors
Clock generation
30
30
a. 200 MHz oscillator (on
backside)
Epson 200 MHz 2.5V LVDS OSC
7
b. Oscillator socket, single-
ended
MMD Components 66 MHz 2.5V
SMA pair
30
30
30
30
21
23
24
c. SMA connectors
d. MGT REFCLK SMA
connectors
SMA pair
8
9
GTX RX/TX port
SMA x4
PCIe Gen1 (8-lane),
Gen2 (4-lane)
Card edge connector, 8-lane
AMP 136073-1
10
11
SFP connector and cage
Ethernet (10/100/1000) with
SGMII
Marvell M88E1111 EPHY
USB Mini-B, USB-to-UART
bridge
12
Silicon Labs CP2103GM bridge
33
USB-A Host, USB Mini-B
peripheral connectors
Cypress CY7C67300-100AXI
controller
13
14
15
27
28, 29
32
Video - DVI connector
Chrontel CH7301C-TF Video codec
IIC NV EEPROM, 8 Kb
(on backside)
ST Microelectronics M24C08-
WDW6TP
Status LEDs
13, 24, 31
24
a. Ethernet status
Right-angle link rate and direction
LEDs
16
b. FPGA INIT, DONE
c. System ACE CF status
User I/O
Init (red), Done (green)
31
13
Status (green), Error (red)
31
a. User LEDs, green (8)
User I/O (active-High)
User I/O (active-High)
User I/O (active-High)
30, 31, 33
b. User pushbuttons, N.O.
momentary (5)
31
c. User LEDs, green (5)
31
31
17
d. User DIP switch (8-pole) User I/O (active-High)
e. User GPIO SMA
SMA pair
30
33
connectors
f. LCD 16 character x 2 line
Displaytech S162D BA BC
display
12
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Detailed Description
Table 1-1: ML605 Features (Cont’d)
Schematic
Page
Number
Feature
Notes
Switches
13, 25, 39
39
a. Power On/Off
Slide switch
active-Low
b. FPGA_PROG_B
pushbutton
13
18
c. System ACE CF Image
Select
4-pole DIP switch (active-High)
25
d. Mode Switch
6-pole DIP switch (active-High)
Samtec ASP-134486-01
25
19
20
FMC - HPC connector
FMC - LPC connector
Power management
a. PMBus controllers
b. Voltage regulators
16 -19
20
Samtec ASP-134603-01
35 - 44
35, 40
2 x TI UCD9240PFC
36-38, 43,
44
2 x PTD08A020W, 3 x PTD08A010W
21
c. 12V power input
connector
6-pin Molex mini-fit connector
4-pin ATX disk type connector
2x6 DIP male pin header
39
39
34
13
d. 12V power input
connector
System Monitor Interface
connector
22
23
System ACE Error DS30 LED Jumper on = enable LED
disable jumper J69 Jumper off = disable LED
1. Virtex-6 XC6VLX240T-1FFG1156 FPGA
A Virtex-6 XC6VLX240T-1FFG1156 FPGA is installed on the embedded development
board.
Keep-Out areas and drill holes are defined around the FPGA to support an Ironwood
Electronics SG-BGA-6046 FPGA socket.
References
Configuration
The ML605 supports configuration in the following modes:
•
•
•
•
Slave SelectMAP (using Platform Flash XL with the onboard 47 MHz oscillator)
Master BPI-Up (using Linear BPI Flash device)
JTAG (using the included USB-A to Mini-B cable)
JTAG (using System ACE CF and CompactFlash card)
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Chapter 1: ML605 Evaluation Board
The ML605 supports Master BPI-Up, JTAG, and Slave SelectMAP. These are selected by
Table 1-2: Virtex-6 FPGA Configuration Modes
(1)
Configuration Mode
M[2:0]
000
001
010
011
100
101
110
111
Bus Width
CCLK Direction
Output
(2)
Master Serial
1
1
(2)
Master SPI
Output
Master BPI-Up(2)
Master BPI-Down(2)
Master SelectMAP(2)
JTAG
8, 16
8, 16
8, 16
1
Output
Output
Output
Input (TCK)
Input
Slave SelectMAP
Slave Serial(3)
8, 16, 32
1
Input
Notes:
1. The parallel configuration modes bus is auto-detected by the configuration logic.
2. In Master configuration mode, the CCLK pin is the clock source for the Virtex-6 FPGA internal
configuration logic. The Virtex-6 FPGA CCLK output pin must be free from reflections to avoid
double-clocking the internal configuration logic. See the Virtex-6 FPGA Configuration User Guide for
more details. [Ref 5]
3. This is the default setting due to internal pull-up termination on mode pins.
page 75) is M[2:0]=010, which selects Master BPI-Up at board power-on. Switch S1 position 4 must
be OFF to disable the System ACE controller from attempting to boot if a CF card is present.
References
See the Virtex-6 FPGA Configuration User Guide for detailed configuration information.
I/O Voltage Rails
There are 16 I/O banks available on the Virtex-6 device. The voltage applied to the FPGA
Table 1-3: Voltage Rails
U1 FPGA Bank
Bank 0
I/O Rail
VCC2V5_FPGA
FMC_VIO_B_M2C
VCC2V5_FPGA
VCC2V5_FPGA
VCC2V5_FPGA
VCC2V5_FPGA
VCC2V5_FPGA
VCC2V5_FPGA
Voltage
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
Bank 12(1)
Bank 13
Bank 14
Bank 15
Bank 16
Bank 22
Bank 23
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Detailed Description
Table 1-3: Voltage Rails (Cont’d)
U1 FPGA Bank
Bank 24
I/O Rail
Voltage
2.5V
1.5V
1.5V
2.5V
2.5V
2.5V
1.5V
1.5V
VCC2V5_FPGA
VCC1V5_FPGA
VCC1V5_FPGA
VCC2V5_FPGA
VCC2V5_FPGA
VCC2V5_FPGA
VCC1V5_FPGA
VCC1V5_FPGA
Bank 25
Bank 26
Bank 32
Bank 33
Bank 34
Bank 35
Bank 36
Notes:
1. The VITA 57.1 specification stipulates that the Bank 12 voltage named
FMC_VIO_B_M2C is supplied by the FMC card plugged onto the relevant
FMC connector (ML605 J64). FMC_VIO_B_M2C cannot exceed the base
board (ML605) Vadj of the FMC connector. The ML605 FMC Vadj
maximum is 2.5V.
References
See the Xilinx Virtex-6 FPGA documentation for more information at
2. 512 MB DDR3 Memory SODIMM
A 512MB DDR3 SODIMM is provided as a flexible and efficient form-factor volatile
memory for user applications. The ML605 SODIMM socket is wired to support a
maximum SODIMM size of 2 GB.
The ML605 DDR3 64-bit wide interface has been tested to 800 MT/s.
The DDR3 interface is implemented in FPGA banks 25, 26, 35, and 36. DCI VRP/N resistor
connections are only implemented banks 26 and 36. DCI functionality in banks 25 and 35 is
achieved in the UCF by cascading DCI between adjacent banks as follows:
CONFIG DCI_CASCADE = "36 35";
CONFIG DCI_CASCADE = "26 25";
Table 1-4 shows the connections and pin numbers for the DDR3 SODIMM.
Table 1-4: DDR3 SODIMM Connections
J1 SODIMM
U1 FPGA Pin
Schematic Net Name
Pin Number
Pin Name
L14
A16
B16
E16
D16
J17
DDR3_A0
DDR3_A1
DDR3_A2
DDR3_A3
DDR3_A4
DDR3_A5
98
97
96
95
92
91
A0
A1
A2
A3
A4
A5
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Table 1-4: DDR3 SODIMM Connections (Cont’d)
J1 SODIMM
Pin Number
U1 FPGA Pin
Schematic Net Name
Pin Name
A6
A15
B15
G15
F15
M16
M15
H15
J15
DDR3_A6
DDR3_A7
DDR3_A8
DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A12
DDR3_A13
DDR3_A14
DDR3_A15
DDR3_BA0
DDR3_BA1
DDR3_BA2
90
86
A7
89
A8
85
A9
107
84
A10/AP
A11
83
A12_BC_N
A13
119
80
D15
C15
K19
J19
A14
78
A15
109
108
79
BA0
BA1
L15
BA2
J11
E13
F13
K11
L11
K13
K12
D11
M13
J14
DDR3_D0
DDR3_D1
DDR3_D2
DDR3_D3
DDR3_D4
DDR3_D5
DDR3_D6
DDR3_D7
DDR3_D8
DDR3_D9
DDR3_D10
DDR3_D11
DDR3_D12
DDR3_D13
DDR3_D14
DDR3_D15
DDR3_D16
DDR3_D17
DDR3_D18
DDR3_D19
5
DQ0
DQ1
7
15
17
4
DQ2
DQ3
DQ4
6
DQ5
16
18
21
23
33
35
22
24
34
36
39
41
51
53
DQ6
DQ7
DQ8
DQ9
B13
B12
G10
M11
C12
A11
G11
F11
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
D14
C14
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Detailed Description
Table 1-4: DDR3 SODIMM Connections (Cont’d)
J1 SODIMM
U1 FPGA Pin
Schematic Net Name
Pin Number
Pin Name
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
G12
G13
F14
H14
C19
G20
E19
F20
A20
A21
E22
E23
G21
B21
A23
A24
C20
D20
J20
DDR3_D20
DDR3_D21
DDR3_D22
DDR3_D23
DDR3_D24
DDR3_D25
DDR3_D26
DDR3_D27
DDR3_D28
DDR3_D29
DDR3_D30
DDR3_D31
DDR3_D32
DDR3_D33
DDR3_D34
DDR3_D35
DDR3_D36
DDR3_D37
DDR3_D38
DDR3_D39
DDR3_D40
DDR3_D41
DDR3_D42
DDR3_D43
DDR3_D44
DDR3_D45
DDR3_D46
DDR3_D47
DDR3_D48
DDR3_D49
DDR3_D50
DDR3_D51
DDR3_D52
DDR3_D53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
G22
D26
F26
B26
E26
C24
D25
D27
C25
C27
B28
D29
B27
G27
A28
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Chapter 1: ML605 Evaluation Board
Table 1-4: DDR3 SODIMM Connections (Cont’d)
J1 SODIMM
Pin Number
U1 FPGA Pin
Schematic Net Name
Pin Name
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM0
E24
G25
F28
B31
H29
H28
B30
A30
E29
F29
E11
B11
E14
D19
B22
A26
A29
A31
DDR3_D54
DDR3_D55
DDR3_D56
DDR3_D57
DDR3_D58
DDR3_D59
DDR3_D60
DDR3_D61
DDR3_D62
DDR3_D63
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
DDR3_DM4
DDR3_DM5
DDR3_DM6
DDR3_DM7
174
176
181
183
191
193
180
182
192
194
11
28
DM1
46
DM2
63
DM3
136
153
170
187
DM4
DM5
DM6
DM7
E12
D12
J12
DDR3_DQS0_N
DDR3_DQS0_P
DDR3_DQS1_N
DDR3_DQS1_P
DDR3_DQS2_N
DDR3_DQS2_P
DDR3_DQS3_N
DDR3_DQS3_P
DDR3_DQS4_N
DDR3_DQS4_P
DDR3_DQS5_N
DDR3_DQS5_P
DDR3_DQS6_N
DDR3_DQS6_P
DDR3_DQS7_N
10
12
DQS0_N
DQS0_P
DQS1_N
DQS1_P
DQS2_N
DQS2_P
DQS3_N
DQS3_P
DQS4_N
DQS4_P
DQS5_N
DQS5_P
DQS6_N
DQS6_P
DQS7_N
27
H12
A14
A13
H20
H19
C23
B23
A25
B25
G28
H27
D30
29
45
47
62
64
135
137
152
154
169
171
186
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Detailed Description
Table 1-4: DDR3 SODIMM Connections (Cont’d)
J1 SODIMM
U1 FPGA Pin
Schematic Net Name
Pin Number
Pin Name
C30
DDR3_DQS7_P
188
DQS7_P
F18
E17
E18
K18
K17
D17
B17
C17
L19
M18
M17
H18
G18
L16
K16
DDR3_ODT0
DDR3_ODT1
116
120
30
ODT0
ODT1
DDR3_RESET_B
DDR3_S0_B
RESET_B
S0_B
114
121
198
113
115
110
73
DDR3_S1_B
S1_B
DDR3_TEMP_EVENT
DDR3_WE_B
EVENT_B
WE_B
DDR3_CAS_B
DDR3_RAS_B
DDR3_CKE0
CAS_B
RAS_B
CKE0
DDR3_CKE1
74
CKE1
DDR3_CLK0_N
DDR3_CLK0_P
DDR3_CLK1_N
DDR3_CLK1_P
103
101
104
102
CK0_N
CK0_P
CK1_N
CK1_P
The Memory Interface Generator (MIG) tool guidelines specify a set of U1 FPGA “No
Connect” pins. These should be added to the UCF as CONFIG PROHIBIT pins as follows:
CONFIG PROHIBIT = H22;
CONFIG PROHIBIT = F21;
CONFIG PROHIBIT = B20;
CONFIG PROHIBIT = F19;
CONFIG PROHIBIT = C13;
CONFIG PROHIBIT = M12;
CONFIG PROHIBIT = L13;
CONFIG PROHIBIT = K14;
CONFIG PROHIBIT = F25;
CONFIG PROHIBIT = C29;
CONFIG PROHIBIT = C28;
CONFIG PROHIBIT = D24;
References
ML605 Hardware User Guide
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Chapter 1: ML605 Evaluation Board
3. 128 Mb Platform Flash XL
A 128 Mb Xilinx XCF128X-FTG64C Platform Flash XL device is used with an onboard
47 MHz oscillator (X4) to configure the FPGA in less than 100 ms from power valid as
required by the PCI Express Card Electromechanical Specification. This allows the PCIe
interface to be recognized and enumerated when plugged into a host PC.
To achieve the fastest configuration speed, the FPGA mode pins are set to Slave SelectMAP
and the onboard 47 MHz clock source external to the FPGA is used for configuration.
Configuration DIP switch S2, switch 1, controls the 47 MHz oscillator enable as outlined in
Considerations for the Configuration Flash,” page 23 for FPGA design recommendations.
4. 32 MB Linear BPI Flash
A Numonyx JS28F256P30 Linear BPI Flash memory (P30) on the ML605 provides 32 MB of
non-volatile storage that can be used for configuration as well as software storage. The
Linear BPI Flash shares the dual use configuration pins in parallel with the XCF128
Platform Flash XL.
The P30_CS net is used to select the P30 or the XCF128. Power-on configuration is selected
by the P30_CS net which is tied to a dip switch S2 (selects pullup/pulldown) and is also
wired to an FPGA non-config pin. The dip switch allows power selection for the
configuration device P30 or XCF128XL. The dip switch selection can be overridden by the
FPGA after configuration by controlling the logic level of the P30_CS signal.
Figure 1-3 shows a block diagram for the Platform Flash and BPI Flash.
X-Ref Target Figure 1-3
-
U27
S1 Switch 4
OFF = Disable System ACE,
enable U4/U27 flash boot
ON = Enable System ACE boot when
CF card is present
PLATFORM
FLASH
FLASH_A[22:0]
FLASH_D[15:0]
FPGA U1
FPGA U1
Bank 24
A
D
VCC2V5
Bank 34
U10
6
CE
S2 SWITCH 6
ON = U4 BPI Upper Half
OFF = U4 BPI Lower Half
PLATFLASH_FCS_B
P30_CS_SEL
(FPGA U1 pin AJ12)
VCC2V5
U4
510
S2-2
11
BPI
FLASH
2
1
FLASH_A[23]
S2 SWITCH 2
ON = U4 BOOT
OFF = U27 BOOT
FPGA U1
Bank 24
4.7K
A
D
E
VCC2V5
VCC2V5
510
S2-6
7
FPGA_FCS_B
6
FPGA U1
Bank 24
4
3
A23
FLASH_CE_B
4.7K
UG534_03_011110
Figure 1-3: Platform Flash and BPI Flash Block Diagram
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Detailed Description
ML605 Flash Boot Options
power-up, before FPGA configuration, DIP switch S2 switch 2 selects which flash device,
U4 (BPI) or U27 (Platform Flash), provides the boot bitstream. Typically S2 switch 2 will be
open/OFF to select the U27 Platform Flash. Given that the mode switches (S2 switch
3/M0, switch 4/M1 and switch 5/M2) are set to Slave SelectMAP mode, then U27, driven
at 47 MHz, can load a PCIe core bitstream before a host PC motherboard can scan its PCIe
slots.When S2 switch 2 is closed/ON at power up, the FPGA will be configured from the
BPI flash device U4. Note that U4 address bit A23 is switched by S2 switch 6, which allows
the lower or upper half of U4 to be chosen as a data source.
Table 1-5 shows the connections and pin numbers for the boot flash devices.
Table 1-5: Platform Flash and BPI Flash Connections
U4 BPI Flash
U27 Platform Flash
Pin Number Pin Name
A1 A00
U1 FPGA Pin
Schematic Net Name
Pin Number
Pin Name
A1
AL8
AK8
AC9
AD10
C8
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
29
25
24
23
22
21
20
19
8
A2
B1
C1
D1
D2
A2
C2
A3
B3
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A3
A4
A5
B8
A6
E9
A7
E8
A8
A8
A9
A9
7
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
C3
D3
C4
A5
B5
D9
6
C9
5
D10
C10
F10
4
3
2
C5
D7
D8
A7
B7
F9
1
AH8
AG8
AP9
AN9
AF10
AF9
AL9
AA23
55
18
17
16
11
10
9
C7
C8
A8
G1
NC
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Chapter 1: ML605 Evaluation Board
Table 1-5: Platform Flash and BPI Flash Connections (Cont’d)
U4 BPI Flash
U27 Platform Flash
Pin Number Pin Name
U1 FPGA Pin
Schematic Net Name
Pin Number
Pin Name
AF24
AF25
W24
V24
H24
H25
P24
FLASH_D0
FLASH_D1
FLASH_D2
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
FLASH_D8
FLASH_D9
FLASH_D10
FLASH_D11
FLASH_D12
FLASH_D13
FLASH_D14
FLASH_D15
34
36
39
41
47
49
51
53
35
37
40
42
48
50
52
54
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
F2
DQ00
E2
G3
E4
E5
G5
G6
H7
E1
E3
F3
DQ01
DQ02
DQ03
DQ04
DQ05
DQ06
DQ07
DQ08
DQ09
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
R24
G23
H23
N24
N23
F23
F4
F5
F24
H5
G7
E7
L24
M23
J26
FLASH_WAIT
FPGA_FWE_B
56
14
WAIT
/WE
/OE
NA(1)
G8
NA(1)
/W
/G
AF23
AA24
K8
FPGA_FOE_B
32
F8
FPGA_CCLK
NA(1)
NA(1)
NA(1)
NA(1)
30
NA(1)
NA(1)
NA(1)
NA(1)
/OE
F1
K
AC23
Y24
PLATFLASH_L_B
FPGA_FCS_B(2)
PLATFLASH_FCS_B(3)
FLASH_CE_B(4)
H1
/L
NA(1)
B4
NA(1)
/E
NA(1)
NA(1)
NA(1)
NA(1)
Notes:
1. Not Applicable
2. FPGA control flash memory select signal connected to pin U10.3
3. Platform Flash select signal connected to pin U10.6
4. BPI Flash select signal connected to pin U10.4
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Detailed Description
FPGA Design Considerations for the Configuration Flash
After FPGA configuration, the FPGA design can disable the configuration flash or access
the configuration flash to read/write code or data.
When the FPGA design does not use the configuration flash, the FPGA design must drive
the FPGA FCS_B pin High in order to disable the configuration flash and put the flash into
a quiescent, low-power state. Otherwise, the Platform Flash XL, in particular, can continue
to drive its array data onto the data bus causing unnecessary switching noise and power
consumption.
For FPGA designs that access the flash for reading/writing stored code or data, connect
the FPGA design or EDK embedded memory controller (EMC) peripheral to the flash
through the pins defined in Table 1-5, page 21.
The Platform Flash XL defaults to a synchronous read mode. Typically, the Platform Flash
XL requires an initialization procedure to put the Platform Flash XL into the common,
asynchronous read mode before accessing stored code or data. To put the Platform Flash
XL into asynchronous read mode, apply the Set Configuration Register command
sequence. See the Platform Flash XL High-Density Configuration and Storage Device Data Sheet
for details on the Set Configuration Register command. [Ref 17]
References
information.
Also, see the Platform Flash XL High-Density Configuration and Storage Device Data Sheet
ML605 Hardware User Guide
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Chapter 1: ML605 Evaluation Board
5. System ACE CF and CompactFlash Connector
The Xilinx System ACE CompactFlash (CF) configuration controller allows a Type I or
Type II CompactFlash card to program the FPGA through the JTAG port. Both hardware
and software data can be downloaded through the JTAG port. The System ACE CF
controller supports up to eight configuration images on a single CompactFlash card. The
configuration address switches allow the user to choose which of the eight configuration
images to use.
The CompactFlash (CF) card shipped with the board is correctly formatted to enable the
System ACE CF controller to access the data stored in the card. The System ACE CF
controller requires a FAT16 file system, with only one reserved sector permitted, and a
sector-per-cluster size of more than one (UnitSize greater than 512). The FAT16 file system
supports partitions of up to 2 GB. If multiple partitions are used, the System ACE CF
directory structure must reside in the first partition on the CompactFlash, with the
xilinx.sysfile located in the root directory. The xilinx.sysfile is used by the System
ACE CF controller to define the project directory structure, which consists of one main
folder containing eight sub-folders used to store the eight ACE files containing the
configuration images. Only one ACE file should exist within each sub-folder. All folder
names must be compliant to the DOS 8.3 short file name format. This means that the folder
names can be up to eight characters long, and cannot contain the following reserved
characters: < > " / \ |. This DOS 8.3 file name restriction does not apply to the actual ACE
file names. Other folders and files may also coexist with the System ACE CF project within
the FAT16 partition. However, the root directory must not contain more than a total of 16
folder and/or file entries, including deleted entries. When ejecting or unplugging the
CompactFlash device, it is important to safely stop any read or write access to the
CompactFlash device to avoid data corruption.
System ACE CF error and status LEDs indicate the operational state of the System ACE CF
controller:
•
•
•
•
A blinking red error LED indicates that no CompactFlash card is present.
A solid red error LED indicates an error condition during configuration.
A blinking green status LED indicates a configuration operation is ongoing.
A solid green status LED indicates a successful download.
Note: Jumper J69 can be removed to disable the Red Error LED circuit. It is recommended that this
jumper is installed during operations utilizing the CompactFlash card.
Every time a CompactFlash card is inserted into the System ACE CF socket, a
configuration operation is initiated. Pressing the System ACE CF reset button re-programs
the FPGA.
page 53 for more details.
The System ACE CF MPU port is connected to the FPGA. This connection allows the FPGA
to use the System ACE CF controller to reconfigure the system or access the CompactFlash
card as a generic FAT file system.
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Detailed Description
Table 1-6 lists the System ACE CF connections.
Table 1-6: System ACE CF Connections
U19 XCCACETQ144I
Pin Number Pin Name
U1 FPGA Pin
Schematic Net Name
AM15
AJ17
AJ16
AP16
AG16
AH15
AF16
AN15
AC15
AP15
AG17
AH17
AG15
AF15
AK14
AJ15
AJ14
L9
SYSACE_D0
SYSACE_D1
66
65
63
62
61
60
59
58
70
69
68
67
45
44
43
39
42
41
77
76
81
80
82
85
93
MPD00
MPD01
MPD02
MPD03
MPD04
MPD05
MPD06
MPD07
MPA00
MPA01
MPA02
MPA03
MPA04
MPA05
MPA06
MPBRDY
MPCE
SYSACE_D2
SYSACE_D3
SYSACE_D4
SYSACE_D5
SYSACE_D6
SYSACE_D7
SYSACE_MPA00
SYSACE_MPA01
SYSACE_MPA02
SYSACE_MPA03
SYSACE_MPA04
SYSACE_MPA05
SYSACE_MPA06
SYSACE_MPBRDY
SYSACE_MPCE
SYSACE_MPIRQ
SYSACE_MPOE
SYSACE_MPWE
SYSACE_CFGTDI
FPGA_TCK
MPIRQ
MPOE
AL15
AL14
AC8
MPWE
CFGTDI
CFGTCK
CFGTDO
CFGTMS
CLK
AE8
AD8
FPGA_TDI
AF8
FPGA_TMS
AE16
CLK_33MHZ_SYSACE(1)
Notes:
1. The System ACE CF clock is sourced from U28 32.000 MHz osc.
References
ML605 Hardware User Guide
25
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Chapter 1: ML605 Evaluation Board
6. USB JTAG
JTAG configuration is provided through onboard USB-to-JTAG configuration logic where
a computer host accesses the ML605 JTAG chain through a Type-A (computer host side) to
Type-Mini-B (ML605 side) USB cable.
any time under any mode pin setting. JTAG initiated configuration takes priority over the
mode pin settings.
X-Ref Target Figure 1-4
-
J17
J18
3.3V
2.5V
J22
FMC HPC
TDI TDO
FMC LPC
TDI TDO
System ACE CF
FPGA
U1
TSTTDI CFGTDO
TDI
J64
J63
U19
TSTTDO CFGTDI
TDO
UG534_04_081309
Figure 1-4: JTAG Chain Diagram
FMC bypass jumpers J17 and J18 must be connected between pins 1-2 (bypass) to enable
JTAG access to the FPGA on the basic ML605 board (without FMC expansion modules
expansion connectors are populated with an expansion module that has a JTAG chain, the
respective jumper(s) must be set to connect pins 2-3 in order to include the FMC expansion
module's JTAG chain in the main ML605 JTAG chain.
X-Ref Target - Figure 1-5
J17
1
2
3
FMC_TDI_BUF
FMC_LPC_TDI
FMC_HPC_TDO
Bypass FMC HPC J64 = Jumper 1-2
Include FMC HPC J64 = Jumper 2-3
H - 1x3
UG534_05_081309
Figure 1-5: VITA 57.1 FMC HPC (J64) JTAG Bypass Jumper J17
X-Ref Target - Figure 1-6
J18
1
FMC_LPC_TDI
Bypass FMC LPC J63 = Jumper 1-2
2
SYSACE_TDI
Include FMC LPC J63 = Jumper 2-3
3
FMC_LPC_TDO
H - 1x3
UG534_06_081309
Figure 1-6: VITA 57.1 FMC LPC (J63) JTAG Bypass Jumper J18
26
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Detailed Description
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and
software debug.
The JTAG connector (USB Mini-B J22) allows a host computer to download bitstreams to
the FPGA using the Xilinx iMPACT software tool. In addition, the JTAG connector allows
debug tools such as the ChipScope™ Pro Analyzer tool or a software debugger to access
the FPGA. The iMPACT software tool can also program the BPI flash via the USB J22
connection. iMPACT can download a temporary design to the FPGA through the JTAG.
This provides a connection within the FPGA from the FPGA's JTAG port to the FPGA's BPI
interface. Through the connection made by the temporary design in the FPGA, iMPACT
can indirectly program the BPI flash or the Platform Flash XL from the JTAG USB J22
connector.
7. Clock Generation
There are three FPGA fabric clock sources available on the ML605.
Oscillator (Differential)
The ML605 has one 2.5V LVDS differential 200 MHz oscillator (U11) soldered onto the
board and wired to an FPGA global clock input.
•
•
Crystal oscillator: Epson EG-2121CA-200.0000M-LHPA
PPM frequency jitter: 50 ppm
Oscillator Socket (Single-Ended, 2.5V)
One populated single-ended clock socket (X5) is provided for user applications. The option
of 3.3V or 2.5V power may be selected via a 0 ohm resistor selection. The X5 socket is
populated with a 66 MHz 2.5V single-ended MMD Components MBH2100H-66.000 MHz
oscillator.
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X-Ref Target Figure 1-7
-
Silkscreened outline
has beveled corner
Socket has notch
in crossbar
UG534_07_092109
Figure 1-7: ML605 Oscillator Socket Pin 1 Location Identifiers
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X-Ref Target Figure 1-8
-
Oscillator body has
one square corner
Oscillator top has
corner dot marking
UG534_08_092109
Figure 1-8: ML605 Oscillator Pin 1 Location Identifiers
SMA Connectors (Differential)
A high-precision clock signal can be provided to the FPGA using differential clock signals
through the onboard 50-ohm SMA connectors J58(P)/J55(N).
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Chapter 1: ML605 Evaluation Board
GTX SMA Clock
The ML605 includes a pair of SMA connectors for a GTX (MGT) Clock as described in
X-Ref Target Figure 1-9
-
J30 32K10K-400E3
2
GND1
3
GND2
GND3
GND4
GND5
GND6
GND7
4
SMA_REFCLK_C_N1
5
6
7
8
SIG
SMA_REFCLK_N
SMA_REFCLK_P
J31 32K10K-400E3
2
3
GND1
GND2
4
GND3
5
SMA_REFCLK_C_P1
SIG
GND4
GND5
GND6
GND7
6
7
8
UG534_09_081309
Figure 1-9: GTX SMA Clock
Table 1-7: GTX SMA Clock Connections
U1 FPGA Pin
Schematic Net Name
SMA_REFCLK_N
SMA_REFCLK_P
SMA Pin
J30.1
F5
F6
J31.1
30
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Detailed Description
8. Multi-Gigabit Transceivers (GTX MGTs)
The ML605 provides access to 20 MGTs.
•
•
•
•
•
•
Eight (8) of the MGTs are wired to the PCIe x8 Endpoint (P1) edge connector fingers
Eight (8) of the MGTs are wired to the FMC HPC connector (J64)
One (1) MGT is wired to SMA connectors (J26, J27)
One (1) MGTs is wired to the FMC LPC connector (J63)
One (1) MGT is wired to the SFP Module connector (P4)
One (1) MGT is used for an SGMII connection to the Ethernet PHY (U80)
X-Ref Target Figure 1-10
-
Note: xxxMHz = user specified frequency
GTX_X0Y19
SGMII
SMA
GTX_X0Y18
REFCLK0
SGMII 125 MHz LVDS
SMA xxx MHz LVDS
REFCLK1
GTX_X0Y17
GTX_X0Y16
SFP
FMC#2
FMC#2 LPC xxxMHz GBTCLK0 LVDS
AC coupling on Mezz
GTX_X0Y15
GTX_X0Y14
REFCLK0
PCIe Lane1
PCIe Lane 2
100 MHz LVDS
REFCLK1
GTX_X0Y13
PCIe Lane 3
PCIe Lane 4
100 MHz in from
PCIe Fingers
PCIe
250 MHz LVDS
GTX_X0Y12
ICS874001
ICS
854104
PCIe Lane 5
PCIe Lane 6
GTX_X0Y11
GTX_X0Y10
(HCSL)
No Connect
REFCLK0
No Connect
REFCLK1
No Connect
GTX_X0Y09
PCIe Lane 7
PCIe Lane 8
GTX_X0Y08
GTX_X0Y07
GTX_X0Y06
REFCLK0
FMC#1
FMC#1
FMC#1 HPC xxx MHz LVDS GBTCLK0
AC coupling on Mezz
(LVDS)
FMC#1 HPC CLK2_M2C
REFCLK1
ICS
854104
(LVDS)
GTX_X0Y05
GTX_X0Y04
FMC#1
FMC#1
PCIe
To FPGA CLK2_M2C_IO CC pin
GTX_X0Y03
FMC#1
FMC#1
FMC#1 HPC xxx MHz LVDS GBTCLK1
AC coupling on Mezz
GTX_X0Y02
REFCLK0
REFCLK1
(LVDS)
FMC#1 HPC CLK3_M2C
ICS
854104
(LVDS)
GTX_X0Y01
GTX_X0Y00
FMC#1
FMC#1
To FPGA CLK3_M2C_IO CC pin
UG534_10_101409
Figure 1-10: MGT Clocking
References
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UG534 (v1.2.1) January 21, 2010
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Chapter 1: ML605 Evaluation Board
9. PCI Express Endpoint Connectivity
The 8-lane PCIe edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1
application and 5.0 GT/s for a Gen2 application. The Virtex FPGA GTX MGTs are used for
the multi-gigabit per second serial interfaces.
The ML605 board trace impedance on all PCIe lanes supports both Gen1 and Gen2
applications. The ML605 supports up to Gen1 x8 and Gen2 x4 as shipped with a -1 speed
grade for the LX240T device.
Figure 1-11, page 32 is a diagram of the PCIe MGT bank 114 and 115 clocking.
X-Ref Target Figure 1-11
-
Note: PCIe edge connector signal nomenclature is
from perspective of the system/motherboard.
P1
U14
U9
PCIE_100M_MGT1_P/N
Q1/NQ1
CLK/NCLK
Q0/NQ0
CLK/NCLK Q/NQ
PCIE_CLK_Q0_P/N
REFCLK+,-
ICS874001
ICS854104
PCIE_100M_MGT0_C_P/N
PCIE_250M_MGT1_C_P/N
PCIE_250M_MGT1_P/N
PCIE_100M_MGT0_P/N
U1
U1
PERp,n[7:0]
Bank 115
Bank 114
PETp,n[7:0]
MGTREFCLK0 P/N
MGTREFCLK0 P/N
MGTTX
P/N[3:0]
MGTRX
P/N[3:0]
MGTTX
P/N[7:4]
MGTRX
P/N[7:4]
PCIe
8-Lane
Edge
PCIE_TX[7:0]_P/N
PCIE_RX[7:0]_P/N
Connector
UG534_11_100809
Figure 1-11: PCIe MGT Banks 114 and 115 Clocking
size selection is 1-lane (J42 pins 1 and 2 jumpered).
X-Ref Target Figure 1-12
-
J42
1
3
5
2
4
6
PCIE_PRSNT_X1
PCIE_PRSNT_X4
PCIE_PRSNT_X8
PCIE_PRSNT_B
H-2X3
UG534_12_111709
Figure 1-12: PCIe Lane Size Select Jumper J42
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Detailed Description
Table 1-8 shows the PCIe connector (P1) that provides up to 8-lane access through the GTX
transceivers to the Virtex-6 FPGA integrated Endpoint block for PCIe designs.
Table 1-8: PCIe Edge Connector Connections
P1 PCIe Edge Connector
U1 FPGA
Pin
Package
Placement
Schematic Net Name
Description
Pin Number
A16
A17
A21
A22
A25
A26
A29
A30
A35
A36
A39
A40
A43
A44
A47
A48
B14
Pin Name
PERp0
PERn0
PERp1
PERn1
PERp2
PERn2
PERp3
PERn3
PERp4
PERn4
PERp5
PERn5
PERp6
PERn6
PERp7
PERn7
PETp0
PETn0
PETp1
PETn1
PETp2
PETn2
PETp3
PETn3
PETp4
PETn4
PETp5
PETn5
PETp6
PETn6
F1
F2
PCIE_TXO_P
PCIE_TXO_N
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX2_P
PCIE_TX2_N
PCIE_TX3_P
PCIE_TX3_N
PCIE_TX4_P
PCIE_TX4_N
PCIE_TX5_P
PCIE_TX5_N
PCIE_TX6_P
PCIE_TX6_N
PCIE_TX7_P
PCIE_TX7_N
PCIE_RXO_P
PCIE_RXO_N
PCIE_RX1_P
PCIE_RX1_N
PCIE_RX2_P
PCIE_RX2_N
PCIE_RX3_P
PCIE_RX3_N
PCIE_RX4_P
PCIE_RX4_N
PCIE_RX5_P
PCIE_RX5_N
PCIE_RX6_P
PCIE_RX6_N
Integrated Endpoint block
transmit pair
GTXE1_X0Y15
GTXE1_X0Y14
GTXE1_X0Y13
GTXE1_X0Y11
GTXE1_X0Y10
GTXE1_X0Y9
GTXE1_X0Y8
GTXE1_X0Y7
GTXE1_X0Y15
GTXE1_X0Y14
GTXE1_X0Y13
GTXE1_X0Y11
GTXE1_X0Y10
GTXE1_X0Y9
GTXE1_X0Y8
H1
H2
K1
K2
M1
M2
P1
P2
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
T1
T2
V1
V2
Y1
Y2
J3
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
receive pair
J4
B15
K5
K6
L3
L4
N3
N4
R3
R4
U3
U4
W3
W4
B19
Integrated Endpoint block
receive pair
B20
B23
Integrated Endpoint block
receive pair
B24
B27
Integrated Endpoint block
receive pair
B28
B33
Integrated Endpoint block
receive pair
B34
B37
Integrated Endpoint block
receive pair
B38
B41
Integrated Endpoint block
receive pair
B42
ML605 Hardware User Guide
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Chapter 1: ML605 Evaluation Board
Table 1-8: PCIe Edge Connector Connections (Cont’d)
P1 PCIe Edge Connector
U1 FPGA
Package
Placement
Schematic Net Name
Pin
Description
Pin Number
B45
Pin Name
PETp7
PETn7
Q0
AA3
AA4
P6
PCIE_RX7_P
Integrated Endpoint block
receive pair
GTXE1_X0Y7
GTXE1_X0Y6
GTXE1_X0Y4
PCIE_RX7_N
B46
PCIE_100M_MGT0_P
PCIE_100M_MGT0_N
PCIE_250M_MGT1_P
PCIE_250M_MGT1_N
PCIE_CLK_QO_P
U14.16
U14.15
U9.18
U9.17
A13
Sourced from U14 ICS854104
clock driver
P5
NQ0
V6
Q
Sourced from U9 ICS874001
clock multiplier/driver
V5
NQ
U14.6
REFCLK+
Integrated Endpoint block
differential clock pair from PCIe
edge connector
U14.7
PCIE_CLK_QO_N
PCIE_PRSNT_B
A14
A1
REFCLK-
PRSNT#1
J42.2,4,6
J42 Lane Size Select jumper
Integrated Endpoint block wake
signal, not connected on ML605
board
AD22
PCIE_WAKE_B
PCIE_PERST_B
B11
WAKE#
PERST
Integrated Endpoint block reset
signal
AE13
A11
Notes:
1. PCIE_TXn_P/N pairs are capacitively coupled to FPGA
2. PCIE_100M_MGT0_P/N pairs are capacitively coupled to FPGA
3. PCIE_250M_MGT1_P/N pairs are capacitively coupled to FPGA
4. PCIE_PERST_B is level-shifted by U32
5. For ML605, access is through MGT Banks 114 and 115
The PCIe interface obtains its power from the DC power supply provided with the ML605
or through the 12V ATX power supply connector. The PCIe edge connector is not used for
any power connections.
The board can be powered by one of two 12V sources; J60, a 6-pin (2x3) molex-type
connector and J25, a 4-pin (inline) ATX disk drive type connector.
The 6-pin molex-type connector provides 60W (12V @ 5A) from the AC power adapter
provided with the board while the 4-pin ATX disk drive connector is provided for users
who want to power their board while it is installed inside a PC chassis.
For applications requiring additional power, such as the use of expansion cards drawing
significant power, a larger AC adapter might be required. If a different AC adapter is used,
its load regulation should be better than 10%.
ML605 power switch SW2 turns the board on and off by controlling the 12V supply to the
board.
Caution! Never apply power to the power brick connector (J60) and the 4-pin ATX disk drive
connector (J25) at the same time as this will result in damage to the board. See Figure 1-23,
page 53. Never connect an auxiliary PCIe 6-pin molex power connector to J60 6-pin molex on
the ML605 board as this could result in damage to the PCIe motherboard and/or ML605 board.
The 6-pin molex connector is marked with a no PCIe power label to warn users of the potential
hazard.
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Detailed Description
References
See the following websites for more Virtex-6 FPGA Integrated Endpoint Block for PCI
Express information:
•
•
express_v6pciexpressendpointblock.htm
In addition, see the PCI Express specifications for more information. [Ref 27]
10. SFP Module Connector
The board contains a small form-factor pluggable (SFP) connector and cage assembly that
accepts SFP modules. The SFP interface is connected to MGT Bank 116 on the FPGA. The
SFP module serial ID interface is connected to the "SFP" IIC bus (see “15. IIC Bus,” page 42
for more information). The control and status signals for the SFP module are connected to
Table 1-9: SFP Module Control and Status
SFP Control/Status
Board Connection
Signal
Test Point J52
SFP_TX_FAULT
SFP_TX_DISABLE
SFP_MOD_DETECT
SFP_RT_SEL
High = Fault
Low = Normal Operation
Jumper J65
Off = SFP Disabled
On = SFP Enabled
Test Point J53
High = Module Not Present
Low = Module Present
Jumper J54
Jumper Pins 1-2 = Full Bandwidth
Jumper Pins 2-3 = Reduced Bandwidth
Test Point J51
SFP_LOS
High = Loss of Receiver Signal
Low = Normal Operation
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Table 1-10: SFP Module Connections
P4 SFP Module Connector
U1 FPGA Pin
Schematic Net Name
Pin Number
Pin Name
RDP_13
E3
E4
SFP_RX_P
SFP_RX_N
13
12
18
19
8
RDN_12
TDP_18
C3
SFP_TX_P
C4
SFP_TX_N
TDN_19
LOS
V23
AP12
SFP_LOS
SFP_TX_DISABLE(1)
3
TX_DISABLE
Notes:
1. The SFP TX Disable pin 3 is driven by transistor Q22, the base of which is driven
by the FPGA signal SFP_TX_DISABLE_FPGA.
11. 10/100/1000 Tri-Speed Ethernet PHY
The ML605 utilizes the onboard Marvell Alaska PHY device (88E1111) for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, and
provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-in
magnetics.
Table 1-11: PHY Default Interface Mode
Jumper Settings
Mode
J66
J67
J68
GMII/MII to copper
(default)
Jumper over pins 1-2 Jumper over pins 1-2
Jumper over pins 2-3 Jumper over pins 2-3
No jumper
SGMII to copper,
no clock
No jumper
Jumper on
RGMII
Jumper over pins 1-2
No jumper
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY
address 0b00111using the settings shown in Table 1-12. These settings can be overwritten
via software commands passed over the MDIO interface.
Table 1-12: Board Connections for PHY Configuration Pins
Connection on
Board
Bit[2]
Bit[1]
Bit[0]
Pin
Definition and Value Definition and Value Definition and Value
CFG0
CFG1
CFG2
CFG3
CFG4
VCC 2.5V
Ground
PHYADR[2] = 1
ENA_PAUSE = 0
ANEG[3] = 1
PHYADR[1] = 1
PHYADR[4] = 0
ANEG[2] = 1
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
VCC 2.5V
VCC 2.5V
VCC 2.5V
ANEG[0] = 1
ENA_XC = 1
HWCFG_MD[2] = 1 HWCFG_MD[1] = 1 HWCFG_MD[0] = 1
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Detailed Description
Table 1-12: Board Connections for PHY Configuration Pins (Cont’d)
Connection on
Board
Bit[2]
Bit[1]
Bit[0]
Pin
Definition and Value Definition and Value Definition and Value
CFG5
CFG6
VCC 2.5V
DIS_FC = 1
DIS_SLEEP = 1
INT_POL = 1
HWCFG_MD[3] = 1
75/50 OHM = 0
PHY_LED_RX
SEL_BDT = 0
SGMII GTX Transceiver Clock Generation
An Integrated Circuit Systems ICS844021I chip generates a high-quality, low-jitter, 125-
MHz LVDS clock from an inexpensive 25-MHz crystal oscillator. This clock is sent to the
GTX driving the SGMII interface. Series AC coupling capacitors are also present to allow
the clock input of the FPGA to set the common mode voltage.
X-Ref Target Figure 1-13
-
VDDA_SGMIICLK
VDD_SGMIICLK
ICS84402II
1
2
8
VDDA
VDD
Q0
SGMIICLK_QO_P
SGMIICLK_QO_N
7
6
5
SGMIICLK_QO_C_P
SGMIICLK_QO_C_N
GND
X3
SGMIICLK_XTAL_OUT
SGMIICLK_XTAL_IN
3
1
2
R132
DNP
1%
NQ0
OE
XTAL_OUT
4
XTAL_IN
U82
1/16W
25.000MHZ
125.00 MHz Clock
GND_SGMIICLK
UG534_13_111709
Figure 1-13: Ethernet SGMII Clock - 125 MHz
Table 1-13 shows the connections and pin numbers for the PHY.
Table 1-13: Ethernet PHYConnections
U80 M88E1111
U1 FPGA Pin
Schematic Net Name
Pin Number
Pin Name
MDIO
MDC
AN14
AP14
AH14
AH13
AL13
AK13
AP11
AG12
AM13
AN13
AF14
AE14
AN12
PHY_MDIO
PHY_MDC
PHY_INT
33
35
32
36
115
114
7
INT_B
RESET_B
CRS
PHY_RESET
PHY_CRS
PHY_COL
COL
PHY_RXCLK
PHY_RXER
PHY_RXCTL_RXDV
PHY_RXD0
PHY_RXD1
PHY_RXD2
PHY_RXD3
RXCLK
RXER
RXDV
RXD0
RXD1
RXD2
RXD3
8
4
3
128
126
125
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Chapter 1: ML605 Evaluation Board
Table 1-13: Ethernet PHYConnections (Cont’d)
U80 M88E1111
U1 FPGA Pin
Schematic Net Name
Pin Number
Pin Name
RXD4
AM12
AD11
AC12
AC13
AH12
AD12
AH10
AJ10
AM11
AL11
AG10
AG11
AL10
AM10
AE11
AF11
A3
PHY_RXD4
124
123
121
120
14
PHY_RXD5
RXD5
PHY_RXD6
RXD6
PHY_RXD7
RXD7
PHY_TXC_GTXCLK
PHY_TXCLK
PHY_TXER
GTXCLK
TXCLK
TXER
10
13
PHY_TXCTL_TXEN
PHY_TXD0
16
TXEN
TXD0
18
PHY_TXD1
19
TXD1
PHY_TXD2
20
TXD2
PHY_TXD3
24
TXD3
PHY_TXD4
25
TXD4
PHY_TXD5
26
TXD5
PHY_TXD6
28
TXD6
PHY_TXD7
29
TXD7
SGMII_TX_P
SGMII_TX_N
SGMII_RX_P
SGMII_RX_N
113
112
107
105
SIN_P
SIN_N
SOUT_P
SOUT_N
A4
B5
B6
References
See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information.
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Detailed Description
12. USB-to-UART Bridge
The ML605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U34) which
allows connection to a host computer with a USB cable. The USB cable is supplied in this
evaluation kit (Type A end to host computer, Type Mini-B end to ML605 connector J21).
Table 1-14 details the ML605 J21 pinout.
Xilinx UART IP is expected to be implemented in the FPGA fabric (for instance, Xilinx XPS
UART Lite. The FPGA supports the USB-to-UART bridge using four signal pins: Transmit
(TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the
CP2103GM USB-to-UART bridge to appear as a COM port to host computer
communications application software (for example, HyperTerm or TeraTerm). The VCP
device driver must be installed on the host PC prior to establishing communications with
the ML605. Refer to the evaluation kit Getting Started Guide for driver installation
instructions.
Table 1-14: USB Type B Pin Assignments and Signal Definitions
USB Connector
Signal Name
Description
Pin
1
VBUS
+5V from host system (not used)
Bidirectional differential serial data (N-side)
Bidirectional differential serial data (P-side)
Signal ground
2
USB_DATA_N
USB_DATA_P
GROUND
3
4
Table 1-15: USB-to-UART Connections
UART function Schematic Net U34 CP2103GM UART Function
U1 FPGA Pin
in FPGA
RTS, output
CTS, input
TX, data out
RX, data in
Name
Pin
in CP2103GM
T24
T23
J25
USB_1_CTS
USB_1_RTS
USB_1_RX
USB_1_TX
22
CTS, input
23
RTS, output
RXD, data in
TXD, data out
24
J24
25
References
drivers.
In addition, see some of the Xilinx UART IP specifications at:
•
•
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Chapter 1: ML605 Evaluation Board
13. USB Controller
The ML605 provides USB support via a Cypress CY7C67300 EZ-Host™ Programmable
Embedded USB Host and Peripheral Controller (U81). The host port is a USB Type-A
connector (J5). A USB keyboard (without an internal USB hub) will be able to connect to
this USB Host port to demonstrate functionality. The peripheral port is a USB Type Mini-
B (J20).
Table 1-16: USB Controller Connections
U81 USB Controller
U1 FPGA
Schematic Net Name
Pin
Number
Pin
Pin Name
Y32
W26
W27
R33
R34
T30
T31
T29
V28
V27
U25
Y28
W32
W31
Y29
W29
Y34
Y33
Y31
Y27
W25
T25
V25
USB_A0_LS
USB_A1_LS
USB_CS_B_LS
USB_D0_LS
USB_D1_LS
USB_D2_LS
USB_D3_LS
USB_D4_LS
USB_D5_LS
USB_D6_LS
USB_D7_LS
USB_D8_LS
USB_D9_LS
USB_D10_LS
USB_D11_LS
USB_D12_LS
USB_D13_LS
USB_D14_LS
USB_D15_LS
USB_INT_LS
USB_RD_B_LS
USB_RESET_B_LS
USB_WR_B_LS
52
50
49
94
93
92
91
90
89
87
86
66
65
61
60
59
58
57
56
46
47
85
48
GPIO19_A0_CS0_52
50_GPIO20_A1_CS1
49_GPIO21_CS_N
GPIO0_D0_94
GPIO1_D1_93
GPIO2_D2_92
GPIO3_D3_91
GPIO4_D4_90
GPIO5_D5_89
GPIO6_D6_87
GPIO7_D7_86
GPIO8_D8_MISO_66
GPIO9_D9_nSSI_65
GPIO10_D10_SCK_61
GPIO11_D11_MOSI_60
GPIO12_D12_59
GPIO13_D13_58
GPIO14_D14_57
GPIO15_D15_SSI_N_56
46_GPIO24_INT_IORDY_IRQ0
47_GPIO23_RD_N_IOR
RESET_N_85
48_GPIO22_WR_N_IOW
References
The FPGA requires implementation of a peripheral controller in order to communicate
with the Cypress USB device. See the XPS External Peripheral Controller (EPC) v1.02a Data
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Detailed Description
14. DVI Codec
The ML605 features a DVI connector (P3) to support an external video monitor. The DVI
circuitry utilizes a Chrontel CH7301C (U38) capable of 1600 X 1200 resolution with 24-bit
color. The video interface chip drives both the digital and analog signals to the DVI
connector. A DVI monitor can be connected to the board directly. A VGA monitor can also
be connected to the board using the supplied DVI-to-VGA adaptor. The Chrontel
CH7301C is controlled by way of the video IIC bus.
monitor's configuration parameters. These parameters can be read by the FPGA using the
Table 1-17: DVI Controller Connections
U38 Chrontel CH7301C
U1 FPGA Pin Schematic Net Name
Pin Number
Pin Name
D0
AJ19
AH19
AM17
AM16
AD17
DVI_D0
DVI_D1
63
62
61
60
59
58
55
54
53
52
51
50
2
D1
DVI_D2
D2
DVI_D3
D3
DVI_D4
D4
AE17
DVI_D5
D5
AK18
DVI_D6
D6
AK17
DVI_D7
D7
AE18
DVI_D8
D8
AF18
DVI_D9
D9
AL16
DVI_D10
DVI_D11
DVI_DE
D10
AK16
D11
AD16
DE
AN17
AP17
DVI_H
4
H
DVI_RESET_B_LS
DVI_V
13
5
RESET_B
V
AD15
AC17
DVI_XCLK_N
DVI_XCLK_P
DVI_GPIO0
DVI_GPIO1
56
57
8
XCLK_N
XCLK_P
GPIO0
GPIO1
AC18
No Connect
No Connect
7
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Chapter 1: ML605 Evaluation Board
15. IIC Bus
The ML605 implements four IIC bus interfaces at the FPGA.
The "MAIN" IIC bus hosts four items:
•
•
•
•
FPGA U1 Bank 34 "MAIN" IIC interface
8Kb NV Memory U6
FMC HPC connector J64
DDR3 SODIMM Socket J1
The "DVI" IIC bus hosts two items:
•
•
FPGA U1 Bank 34 "DVI" IIC interface
DVI codec U38 and DVI connector J63
The "LPC" IIC bus hosts two items:
•
•
FPGA U1 Bank 33 "LPC" IIC interface
FMC LPC connector J63
The "SFP" IIC bus hosts two items:
•
•
FPGA U1 Bank 13 "SFP" IIC interface
SFP module connector P4
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Detailed Description
X-Ref Target Figure 1-14
-
U1
IIC_SDA_MAIN_LS
IIC_SCL_MAIN_LS
IIC_SDA_SFP
IIC_SCL_SFP
BANK 34
BANK 13
IIC_SDA_DVI
LEVEL
U6
SHIFTER
BANK 34
BANK 33
IIC_SCL_DVI
ST MICRO
M24C08-WDW6TP
FMC_LPC_IIC_SDA_LS
FMC_LPC_IIC_SCL_LS
Addr: 0b1010100
through
0b1010111
J64
LEVEL
LEVEL
LEVEL
J63
SHIFTER SHIFTER
SHIFTER
FMC HPC
COLUMN C
2 Kb EEPROM on
any FMC LPC
Mezzanine Card
FMC LPC
COLUMN C
2 Kb EEPROM on
any FMC LPC
Mezzanine Card
Addr: 0b1010001
FMC_LPC_IIC_SCL
FMC_LPC_IIC_SDA
Addr: 0b1010000
J1
P3
DVI CONN
DDR3 SODIMM
IIC_CLK_DVI_F
IIC_SCL_MAIN
SOCKET
Addr: 0b1010011
IIC_SDA_DVI_F
2 Kb EEPROM
Addr: 0b0011011
Temperature Sensor
IIC_SDA_MAIN
Addr: 0b1010000
U38
DVI CODEC
CHRONTEL
P4
SFP_MOD_DEF2
SFP_MOD_DEF1
SFP MODULE
CONNECTOR
CH730C-TF
Addr: 0b1010000
Addr: 0b1110110
UG534_14_092109
Figure 1-14: IIC Bus Topology
ML605 Hardware User Guide
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8 Kb NV Memory
The ML605 hosts an 8 Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage
memory device (U6). The IIC address of U7 is 0b1010100, and U6 is not write protected
(WP pin 7 is tied to GND).
X-Ref Target Figure 1-15
-
VCC3V3
1
U6
VCC3V3
VCC3V3
2
IIC SCL MAIN
IIC SDA MAIN
6
5
SCL
SDA
7
WP
1
2
C65
X5R
10V
1
2
3
A0
A1
A2
8
4
VCC
GND
0.1UF
M24C08-WDW6TP
IIC Address = 0b1010100
1
R305
DNP
1%
2
1/16W
UG534_15_072109
Figure 1-15: IIC Memory U6
Table 1-18: IIC Memory Connections
IIC Memory U6
FPGA U1 Pin
Schematic Net Name
Pin Number
Pin Name
A0
Not Applicable
Not Applicable
Not Applicable
N10
Tied to GND
1
2
3
5
6
7
Tied to GND
A1
Pulled up (0 ohm) to VCC3V3
IIC_SDA_MAIN
IIC_SCL_MAIN
Tied to GND
A2
SDA
SCL
WP
P11
Not Applicable
References
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Detailed Description
16. Status LEDs
Table 1-19 defines the status LEDs.
Table 1-19: Status LEDs
Designator
Signal Name
SYSACE_STAT_LED
Color
Label
Description
System ACE CF Status
DS1
GREEN System ACE CF
Status LED
DS2
TI_PWRGOOD and
MGT_TI_PWRGOOD
GREEN POWER GOOD
Both UCD9240 controllers
report power good
DS13
DS23
FPGA_DONE
LED_GRN
GREEN DONE
GREEN STATUS
RED
FPGA configured successfully
USB JTAG Connection Status
(Dual LED)
LED_RED
DS25
DS27
DS28
DS29
DS30
12V
GREEN 12V
12V Power On
MGT_AVCC
GREEN AVCC GD
GREEN MGT_AVTT
GREEN DDR3 PWR GD
MGT AVCC Power On
MGT AVTT Power On
DDR3 VTTDDR Power Good
System ACE CF Error
MGT_AVTT
DDR3_VTTDDR_PWRGOOD
SYSACE_ERR_LED
RED
System ACE CF
Error LED
DS31
DS32
FPGA_INIT_B
RED
INIT
FPGA Initialization in progress
FMC Power Good
DVI_GPIO1_FMC_C2M_PG
GREEN FMC PWR GD
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Chapter 1: ML605 Evaluation Board
Ethernet PHY Status LEDs
The Ethernet PHY status LEDs are mounted to be visible when the ML605 board is
installed into a PC motherboard. They are mounted in right-angle, plastic housings and
can be seen on the connector end of the board. This cluster of six LEDs is installed adjacent
to the RJ45 Ethernet jack P2.
X-Ref Target Figure 1-16
-
Direction
Indicator
Link Rate
(Mbps)
DUP
TX
RX
10
100
1000
P2
End view of ML605 Ethernet jack and
status LEDs when installed vertically
in a PC chassis
UG534_16_101209
Figure 1-16: Ethernet PHY Status LEDs
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FPGA INIT and DONE LEDs
The typical Xilinx FPGA power up and configuration status LEDs are present on the
ML605.
The red INIT LED DS31 comes on momentarily after the FPGA powers up and during its
internal power-on process. The DONE LED DS13 comes on after the FPGA programming
bitstream has been downloaded and the FPGA successfully configured.
X-Ref Target Figure 1-17
-
VCC2V5
1
VCC2V5
R419
330
5%
1/16W
Q14
2
FPGA INIT B
FPGA_DONE
1
NDS336P
1
R3
27.4
1%
1
R4
27.4
1%
2
2
1/16W
1/16W
UG534_17_011310
Figure 1-17: FPGA INIT and DONE LEDs
Table 1-20: FPGA INIT and DONE LED Connections
FPGA U1 Pin Schematic Net Name
Controlled LED
P8
R8
FPGA_INIT_B
FPGA_DONE
DS31 INIT, Red
DS13 DONE, Green
17. User I/O
The ML605 provides the following user and general purpose I/O capabilities:
•
•
•
•
•
•
User LEDs (8) with parallel wired GPIO male pin header
User Pushbutton (5) switches with associated direction LEDs
CPU Reset pushbutton switch
User DIP switch (8-pole)
User SMA GPIO
LCD Display (16 char x 2 lines)
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User LEDs
The ML605 provides two groups of active-High LEDs as described in Figure 1-18 and
Table 1-21.
X-Ref Target Figure 1-18
-
J62
1
2
3
4
5
6
7
8
GPIO_LED_0
GPIO_LED_1
GPIO_LED_2
GPIO_LED_3
GPIO_LED_4
GPIO_LED_5
GPIO_LED_6
GPIO_LED_7
H-1X8
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
R5
27.4
1%
R6
27.4
1%
R7
27.4
1%
R8
27.4
1%
R9
27.4
1%
R10
27.4
1%
R11
27.4
1%
R12
27.4
1%
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
GPIO_LED_C
GPIO_LED_W
GPIO_LED_E
GPIO_LED_S
GPIO_LED_N
This group of LEDs is mounted
adjacent to their respective “direction”
pushbuttons, as seen on the right side
of the LCD on the board photo (Figure
1-2).
1
2
1
2
1
2
1
2
1
2
R13
27.4
1%
R14
27.4
1%
R15
27.4
1%
R16
27.4
1%
R17
27.4
1%
1/16W
1/16W
1/16W
1/16W
1/16W
UG534_18_081109
Figure 1-18: User LEDs and GPIO Connector, Directional LEDs
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Table 1-21: User LED Connections
FPGA U1 Pin Schematic Net Name GPIO J62 Pin
Controlled LED
AC22
AC24
AE22
AE23
AB23
AG23
AE24
AD24
AP24
AD21
AE21
AH28
AH27
GPIO_LED_0
GPIO_LED_1
GPIO_LED_2
GPIO_LED_3
GPIO_LED_4
GPIO_LED_5
GPIO_LED_6
GPIO_LED_7
GPIO_LED_C
GPIO_LED_W
GPIO_LED_E
GPIO_LED_S
GPIO_LED_N
1
2
3
4
5
6
7
8
–
–
–
–
–
DS12
DS11
DS9
DS10
DS15
DS14
DS22
DS21
DS16
DS17
DS19
DS18
DS20
User Pushbutton Switches
The ML605 provides six active-High pushbutton switches:
•
SW5, SW6, SW7, SW8 and SW9, arranged in a diamond configuration to depict
“directional” headings North, South, East, West and Center respectively
•
SW10 CPU Reset pushbutton
The six pushbuttons all have the same active-High topology as the sample shown in
X-Ref Target Figure 1-19
-
VCC1V5
Pushbutton
1
2
4
P1
P4
3
4.7K
R401
CPU RESET
5%
1/16W
P2
P3
sw10
UG534_19_072109
Figure 1-19: User Pushbutton Switch (Typical)
ML605 Hardware User Guide
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Table 1-22: User Pushbutton Switch Connections
Pushbutton
Switch Pin
U1 FPGA Pin
Schematic Net Name
A19
A18
G17
H17
G26
H10
GPIO_SW_N
GPIO_SW_S
GPIO_SW_E
GPIO_SW_W
GPIO_SW_C
CPU_RESET
SW5.2
SW6.2
SW7.2
SW8.2
SW9.2
SW10.2
User DIP Switch
Table 1-23.
X-Ref Target Figure 1-20
-
VCC1V5
SW1
1
16
GPIO DIP SW1
GPIO DIP SW2
GPIO DIP SW3
GPIO DIP SW4
GPIO DIP SW5
GPIO DIP SW6
GPIO DIP SW7
GPIO DIP SW8
2
3
4
5
6
7
8
15
14
13
12
11
10
9
SDMX-8-X
UG534_20_072109
Figure 1-20: User 8-pole DIP Switch
Table 1-23: User DIP Switch Connections
U1 FPGA Pin
Schematic Net Name
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
GPIO_DIP_SW4
GPIO_DIP_SW5
GPIO_DIP_SW6
GPIO_DIP_SW7
GPIO_DIP_SW8
DIP Switch Pin
SW1.1
D22
C22
L21
L20
C18
B18
K22
K21
SW1.2
SW1.3
SW1.4
SW1.5
SW1.6
SW1.7
SW1.8
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User SMA GPIO
The ML605 includes an pair of SMA connectors for GPIO as described in Figure 1-21 and
Table 1-24.
X-Ref Target Figure 1-21
-
J56 32K10K-400E3
2
GND1
3
GND2
4
GND3
SIG GND4
GND5
1
5
6
7
8
GND6
GND7
USER SMA GPIO N
USER SMA GPIO P
J76 32K10K-400E3
2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
3
4
5
6
7
8
1
SIG
UG534_21_072109
Figure 1-21: User SMA GPIO
Table 1-24: User SMA Connections
U1 FPGA Pin
Schematic Net Name
USER_SMA_GPIO_N
USER_SMA_GPIO_P
SMA Pin
J56.1
W34
V34
J57.1
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LCD Display (16 Character x 2 Lines)
The ML605 board has a 16-character x 2-line LCD (Display Tech S162D BA BC, installed
onto J41 2x7 header) on the board to display text information. Potentiometer R270 adjusts
the contrast of the LCD. A ST2378E (U33) 2.5V-to-5V level-shifter is used to shift the
voltage level between the FPGA and the LCD. The data interface to the LCD is connected
to the FPGA to support 4-bit mode only. The LCD module has a connector that allows the
LCD to be removed from the board to access to the components below it.
Caution! Care should be taken not to scratch or damage the surface of the LCD window.
X-Ref Target Figure 1-22
-
VCC5
VCC5
R158
J41
LCD_DB6
LCD_DB7
LCD_DB5
1
3
5
7
9
11
13
2
4
6
8
10
12
14
32
32
6.81K
1%
LCD_DB4
NC
NC
LCD_RW
LCD_VEE
NC
NC
R270
0-2K
1/2W
20%
LCD_E
32
LCD_RS
2
silkscreen:
“LCD Contrast”
SSW-107-01-T-D
UG534_22_073109
Figure 1-22: LCD Header J41 and Contrast Trimpot R270
Table 1-25: LCD Header Connections
U1 FPGA Pin
AD14
AK11
Schematic Net Name
LCD_DB4_LS
LCD_DB5_LS
LCD_DB6_LS
LCD_DB7_LS
LCD_RW_LS
LCD_RS_LS
J41 Pin
4
3
AJ11
2
AE12
1
AC14
10
11
9
T28
AK12
LCD_E_LS
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Detailed Description
18. Switches
The ML605 Evaluation board includes the following switches:
•
•
•
•
•
Power On/Off Slide Switch SW2
FPGA_PROG_B SW4 (active-Low)
SYSACE_RESET_B SW3 (active-Low)
System ACE CF CompactFlash Image Select DIP Switch S1 (active-High)
MODE, Boot EEPROM Select and CCLK Osc Enable DIP switch S2 (active-High)
Power On/Off Slide Switch SW2
SW2 is the ML605 board main power on/off switch. Sliding the switch actuator from the
off to on position applies 12V power from either J60 (6-pin Mini-Fit) or J25 (4-pin ATX)
power connector to the VCC12_P power plane via the 1mΩ 1% 3W series current sense
sensing. Green LED DS25 will illuminate when the ML605 board power is on. See section
“21. Power Management,” page 65 for details on the onboard power system.
X-Ref Target Figure 1-23
-
VCC12_P
J60
12v
DPDT
R346
1
NC
NC
VCC12_P_IN
1
2
5
3
I1 I1
I2 I2
4
2
5
3
12v
1
2
4
R322
E1
E1
E2
E2
0.001R
NC
NC
1.00K
+
C280
330UF
1
2
N/C
N/C
6
1%
1/16W
3W
0.5%
Y14880R00100B09R
16V
ELEC
COM
COM
SW2
1201M2S3ABE2
6
39-30-1060
CAUTION!
PCIe
DO NOT plug a PC ATX power supply 6-pin connector into
the J60 connector on the ML605 board. The ATX 6-pin
connector has a different pinout than J60 and will damage
the ML605 board and void the board warranty.
Power
ATX Peripheral Cable Connector
can plug into J25 when ML605 is
in PC and the desk top AC adapter
(brick) is not used.
DO NOT plug an auxilliary PCIe 6-pin molex power
connector into the J60 connector as this could damage the
PCIe motherboard and/or the ML605 board. J60 is marked
with a NO PCIE POWER label to warn users of the poten-
tial hazard.
J25
1
12V
2
COM
3
DO NOT apply power to J60 and the 4-pin ATX disk drive
connector J25 at the same time as this will damage the
ML605 board.
COM
NC
4
5V
350211-1
UG534_23 _081209
Figure 1-23: Power On/Off Slide Switch SW2
ML605 Hardware User Guide
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FPGA_PROG_B Pushbutton SW4 (Active-Low)
This switch grounds the FPGA's PROG_B pin when pressed. This action clears the FPGA.
See the Virtex-6 FPGA Data Sheet for more information on clearing the contents of the
FPGA. [Ref 4]
X-Ref Target Figure 1-24
-
VCC2V5
FPGA PROG
Pushbutton
FPGA_PROG_B
1
4
P1
P4
2
3
P2
P3
SW4
Silkscreen:
PROG
UG534_24_073109
Figure 1-24: FPGA PROG_B Pushbutton SW4
SYSACE_RESET_B Pushbutton SW3 (Active-Low)
When the System ACE CF configuration mode pin is high (enabled by closing DIP switch
S1 switch 4), the System ACE CF controller configures the FPGA from the CompactFlash
card when a card is inserted or the SYSACE RESET button is pressed. See “5. System ACE
CF and CompactFlash Connector,” page 24 for more details.
X-Ref Target Figure 1-25
-
silkscreen:
“SYSACE RESET”
SYSACE_RESET_B
Pushbutton
1
2
4
P1
P4
3
P2
P3
SW3
UG534_25_073109
Figure 1-25: System ACE CF RESET_B Pushbutton SW3
54
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Detailed Description
System ACE CF CompactFlash Image Select DIP Switch S1
System ACE CF CompactFlash (CF) image select DIP switch S1, switches 1–3, select which
offer eight binary addresses. When ON (High), the S1 switch 4 enables the System ACE CF
controller to configure the FPGA from the CF card when a card is inserted or when the
SYSACE RESET button is pressed. See “5. System ACE CF and CompactFlash Connector,”
page 24 for more details about the System ACE controller.
X-Ref Target
-
Figure 1-26
VCC2V5
1
2
1
1
2
2
S1
5
6
7
8
4
3
2
1
SYSACE_CFGMODEPIN
SYSACE_CFGADDR2
SYSACE_CFGADDR1
SYSACE_CFGADDR0
2
2
2
2
SDMX-4-X
1
1
1
1
UG534_26_110409
Figure 1-26: System ACE CF CompactFlash Image Select DIP Switch S1
Note: S1 switch 4 is the System ACE controller enable switch. When ON, this switch allows the
System ACE to boot at power-on if it finds a CF card present. In order to boot from BPI Flash U4 or
Xilinx Platform Flash (U27) without System ACE contention, S1 switch 4 must be OFF.
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Chapter 1: ML605 Evaluation Board
Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2
Oscillator Enable: S2 switch 1, CCLK_EXTERNAL, controls the enable pin of the 47 MHz
oscillator SiT8102 (X4). When switch 1 is closed (CCLK_EXTERNAL High), X4 drives a
47 MHz clock onto the FPGA_CCLK signal.
Boot EEPROM Select: S2 switch 2 is used to select the between the Xilinx Platform Flash or
the Numonyx Linear BPI Flash for the FPGA boot memory device.
Upper or Lower Address Select: S2 switch 6 is used to select the upper or lower half of
flash memory U4 as the source of the FPGA bitstream image. When FLASH_A23 is High,
the upper half of the address is selected. When FLASH_A23 is Low, the lower half of the
address is selected.
X-Ref Target Figure 1-27
-
VCC2V5
1
2
1
1
2
2
S2
7
8
9
10
11
12
6
5
4
3
2
1
FLASH_A23
FPGA_M2
FPGA_M1
FPGA_M0
P30_CS_SEL
CCLK EXTERNAL
SDMX-6-X
1
2
1
2
1
2
1
2
1
2
1
2
UG534_27_110409
Figure 1-27: Multi-Purpose Select DIP Switch S2
Table 1-26 shows the FPGA configuration modes controlled by S2 switches 3, 4, and 5.
Table 1-26: ML605 Configuration Modes
Configuration Mode
Master BPI-Up
JTAG
M[2:0]
010
Bus Width
8, 16
CCLK
Output
101
1
Input (TCK)
Input
Slave SelectMAP
110
8, 16, 32
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Detailed Description
Table 1-27: Switch S2 Configuration Details
Switch
Configuration Mode/Method
Slave SelectMAP
JTAG
Master BPI
Switch
Net Name
System ACE CF Platform Flash XL P30 Linear Flash
S2.1
S2.2
S2.3
S2.4
S2.5
S2.6
CCLK_EXTERNAL
P30_CS_SEL
FPGA_M0
Off
On(1)
On
On
Off
Off
On
Off
Off
FPGA_M1
Off
On
On
FPGA_M2
On
On
Off
FLASH_A23
Off
Don't Care
Off(2)
Notes:
1. In JTAG mode, S2.2 is shown as ON for FPGA access to the P30 Linear Flash. Alternatively, set S2.2 to
OFF for FPGA access to the Platform Flash XL.
2. In Master BPI mode, S2.6 is shown as OFF for selecting initial configuration from BPI address
0x000000. Alternatively, set S2.6 to ON to select initial configuration from BPI address 0x800000.
details.
19. VITA 57.1 FMC HPC Connector
The ML605 implements both the High Pin Count (HPC, J64) and Low Pin Count (LPC, J63)
connector options of VITA 57.1.1 FMC specification. This section discusses the FMC HPC
J64 connector.
The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low
Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector
form factor is used for both versions. The HPC version is fully populated with 400 pins
present, and the LPC version is partially populated with 160 pins.
The 10 x 40 rows of a FMC HPC connector provides connectivity for:
•
•
•
•
•
160 single-ended or 80 differential user-defined signals
10 MGTs
2 MGT clocks
4 differential clocks
159 ground, 15 power connections
Of the above signal and clock connectivity capability, the ML605 implements the following
subset:
•
78 differential user defined pairs:
♦
♦
♦
34 LA pairs
24 HA pairs
20 HB pairs
•
•
•
8 MGTs
2 MGT clocks
4 differential clocks
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Chapter 1: ML605 Evaluation Board
Note: The ML605 board VADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed
at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The ML605 VITA 57.1 FMC interfaces
are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.
Table 1-28 shows the VITA 57.1 FMC HPC connections. The connector pinout is in
Any signal named FMC_HPC_xxxx that is wired between a U1 FPGA pin and some other
device does not appear in this table.
Table 1-28: VITA 57.1 FMC HPC Connections
J64 FMC
HPC Pin
U1 FPGA
Pin
J64 FMC
HPC Pin
U1 FPGA
Pin
Schematic Net Name
Schematic Net Name
A2
FMC_HPC_DP1_M2C_P
FMC_HPC_DP1_M2C_N
FMC_HPC_DP2_M2C_P
FMC_HPC_DP2_M2C_N
FMC_HPC_DP3_M2C_P
FMC_HPC_DP3_M2C_N
FMC_HPC_DP4_M2C_P
FMC_HPC_DP4_M2C_N
FMC_HPC_DP5_M2C_P
FMC_HPC_DP5_M2C_N
FMC_HPC_DP1_C2M_P
FMC_HPC_DP1_C2M_N
FMC_HPC_DP2_C2M_P
FMC_HPC_DP2_C2M_N
FMC_HPC_DP3_C2M_P
FMC_HPC_DP3_C2M_N
FMC_HPC_DP4_C2M_P
FMC_HPC_DP4_C2M_N
FMC_HPC_DP5_C2M_P
FMC_HPC_DP5_C2M_N
AE3
AE4
AF5
AF6
AG3
AG4
AJ3
B12
B13
B16
B17
B20
B21
B32
B33
B36
B37
FMC_HPC_DP7_M2C_P
FMC_HPC_DP7_M2C_N
FMC_HPC_DP6_M2C_P
FMC_HPC_DP6_M2C_N
FMC_HPC_GBTCLK1_M2C_P
FMC_HPC_GBTCLK1_M2C_N
FMC_HPC_DP7_C2M_P
FMC_HPC_DP7_C2M_N
FMC_HPC_DP6_C2M_P
FMC_HPC_DP6_C2M_N
AP5
AP6
AM5
AM6
AK6
AK5
AP1
AP2
AN3
AN4
A3
A6
A7
A10
A11
A14
A15
A18
A19
A22
A23
A26
A27
A30
A31
A34
A35
A38
A39
AJ4
AL3
AL4
AD1
AD2
AF1
AF2
AH1
AH2
AK1
AK2
AM1
AM2
C2
C3
FMC_HPC_DP0_C2M_P
FMC_HPC_DP0_C2M_N
FMC_HPC_DP0_M2C_P
FMC_HPC_DP0_M2C_N
FMC_HPC_LA06_P
AB1
AB2
D4
D5
FMC_HPC_GBTCLK0_M2C_P
FMC_HPC_GBTCLK0_M2C_N
FMC_HPC_LA01_CC_P
FMC_HPC_LA01_CC_N
FMC_HPC_LA05_P
AD6
AD5
C6
AC3
D8
AK19
AL19
AG22
AH22
C7
AC4
D9
C10
C11
AG20
AG21
D11
D12
FMC_HPC_LA06_N
FMC_HPC_LA05_N
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Detailed Description
U1 FPGA
Table 1-28: VITA 57.1 FMC HPC Connections (Cont’d)
J64 FMC
HPC Pin
U1 FPGA
Pin
J64 FMC
HPC Pin
Schematic Net Name
FMC_HPC_LA10_P
Schematic Net Name
Pin
C14
C15
C18
C19
C22
C23
C26
C27
C30
C31
AM20
AL20
AN19
AN20
AH25
AJ25
D14
D15
D17
D18
D20
D21
D23
D24
D26
D27
D29
D30
D31
D33
FMC_HPC_LA09_P
FMC_HPC_LA09_N
FMC_HPC_LA13_P
FMC_HPC_LA13_N
FMC_HPC_LA17_CC_P
FMC_HPC_LA17_CC_N
FMC_HPC_LA23_P
FMC_HPC_LA23_N
FMC_HPC_LA26_P
FMC_HPC_LA26_N
FMC_HPC_TCK_BUF(2)
FMC_TDI_BUF(2)
AM18
AL18
AP19
AN18
AN27
AM27
AL26
AM26
AM25
AL25
U88.15
J17.1
FMC_HPC_LA10_N
FMC_HPC_LA14_P
FMC_HPC_LA14_N
FMC_HPC_LA18_CC_P
FMC_HPC_LA18_CC_N
FMC_HPC_LA27_P
FMC_HPC_LA27_N
IIC_SCL_MAIN_LS(1)
IIC_SDA_MAIN_LS(1)
AP30
AP31
AK9
AE9
FMC_HPC_TDO(2)
FMC_TMS_BUF(2)
J17.3
U88.17
E2
E3
FMC_HPC_HA01_CC_P
FMC_HPC_HA01_CC_N
FMC_HPC_HA05_P
FMC_HPC_HA05_N
FMC_HPC_HA09_P
FMC_HPC_HA09_N
FMC_HPC_HA13_P
FMC_HPC_HA13_N
FMC_HPC_HA16_P
FMC_HPC_HA16_N
FMC_HPC_HA20_P
FMC_HPC_HA20_N
FMC_HPC_HB03_P
FMC_HPC_HB03_N
FMC_HPC_HB05_P
FMC_HPC_HB05_N
FMC_HPC_HB09_P
AD29
AC29
AB27
AC27
AB30
AB31
AE31
AD31
AC33
AB33
V32
F1
F4
FMC_HPC_PG_M2C_LS(1)
FMC_HPC_HA00_CC_P
FMC_HPC_HA00_CC_N
FMC_HPC_HA04_P
FMC_HPC_HA04_N
FMC_HPC_HA08_P
FMC_HPC_HA08_N
FMC_HPC_HA12_P
FMC_HPC_HA12_N
FMC_HPC_HA15_P
FMC_HPC_HA15_N
FMC_HPC_HA19_P
FMC_HPC_HA19_N
FMC_HPC_HB02_P
FMC_HPC_HB02_N
FMC_HPC_HB04_P
FMC_HPC_HB04_N
J27
AE33
AF33
AB28
AC28
AG31
AF31
AD32
AE32
AB32
AC32
U33
E6
F5
E7
F7
E9
F8
E10
E12
E13
E15
E16
E18
E19
E21
E22
E24
E25
E27
F10
F11
F13
F14
F16
F17
F19
F20
F22
F23
F25
F26
V33
AL30
AM31
AN33
AN34
AL34
U32
AP32
AP33
AM33
AL33
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Chapter 1: ML605 Evaluation Board
Table 1-28: VITA 57.1 FMC HPC Connections (Cont’d)
J64 FMC
HPC Pin
U1 FPGA
Pin
J64 FMC
HPC Pin
U1 FPGA
Pin
Schematic Net Name
FMC_HPC_HB09_N
Schematic Net Name
FMC_HPC_HB08_P
E28
E30
E31
E33
E34
AK34
AH33
AH32
AL31
AK31
F28
F29
F31
F32
F34
F35
AK33
AK32
AJ31
FMC_HPC_HB13_P
FMC_HPC_HB13_N
FMC_HPC_HB19_P
FMC_HPC_HB19_N
FMC_HPC_HB08_N
FMC_HPC_HB12_P
FMC_HPC_HB12_N
FMC_HPC_HB16_P
FMC_HPC_HB16_N
AJ32
AH29
AH30
G2
FMC_HPC_CLK1_M2C_P
FMC_HPC_CLK1_M2C_N
FMC_HPC_LA00_CC_P
FMC_HPC_LA00_CC_N
FMC_HPC_LA03_P
FMC_HPC_LA03_N
FMC_HPC_LA08_P
FMC_HPC_LA08_N
FMC_HPC_LA12_P
FMC_HPC_LA12_N
FMC_HPC_LA16_P
FMC_HPC_LA16_N
FMC_HPC_LA20_P
FMC_HPC_LA20_N
FMC_HPC_LA22_P
FMC_HPC_LA22_N
FMC_HPC_LA25_P
FMC_HPC_LA25_N
FMC_HPC_LA29_P
FMC_HPC_LA29_N
FMC_HPC_LA31_P
FMC_HPC_LA31_N
FMC_HPC_LA33_P
FMC_HPC_LA33_N
AP20
AP21
AF20
AF21
AC19
AD19
AK22
AJ22
H2
H4
FMC_HPC_PRSNT_M2C_L(1)
FMC_HPC_CLK0_M2C_P
FMC_HPC_CLK0_M2C_N
FMC_HPC_LA02_P
FMC_HPC_LA02_N
FMC_HPC_LA04_P
FMC_HPC_LA04_N
FMC_HPC_LA07_P
FMC_HPC_LA07_N
FMC_HPC_LA11_P
FMC_HPC_LA11_N
FMC_HPC_LA15_P
FMC_HPC_LA15_N
FMC_HPC_LA19_P
FMC_HPC_LA19_N
FMC_HPC_LA21_P
FMC_HPC_LA21_N
FMC_HPC_LA24_P
FMC_HPC_LA24_N
FMC_HPC_LA28_P
FMC_HPC_LA28_N
FMC_HPC_LA30_P
FMC_HPC_LA30_N
FMC_HPC_LA32_P
FMC_HPC_LA32_N
AP25
K24
G3
G6
H5
K23
G7
H7
AC20
AD20
AF19
AE19
AK21
AJ21
G9
H8
G10
G12
G13
G15
G16
G18
G19
G21
G22
G24
G25
G27
G28
G30
G31
G33
G34
G36
G37
H10
H11
H13
H14
H16
H17
H19
H20
H22
H23
H25
H26
H28
H29
H31
H32
H34
H35
H37
H38
AM21
AL21
AP22
AN23
AK23
AL24
AP27
AP26
AN28
AM28
AL28
AK28
AL29
AK29
AH23
AH24
AM22
AN22
AM23
AL23
AN25
AN24
AN29
AP29
AN30
AM30
AK27
AJ27
AJ24
AK24
AG25
AG26
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Detailed Description
U1 FPGA
Table 1-28: VITA 57.1 FMC HPC Connections (Cont’d)
J64 FMC
HPC Pin
U1 FPGA
Pin
J64 FMC
HPC Pin
Schematic Net Name
Schematic Net Name
Pin
J2
FMC_HPC_CLK3_M2C_P(2)
FMC_HPC_CLK3_M2C_N(2)
FMC_HPC_HA03_P
FMC_HPC_HA03_N
FMC_HPC_HA07_P
FMC_HPC_HA07_N
FMC_HPC_HA11_P
FMC_HPC_HA11_N
FMC_HPC_HA14_P
FMC_HPC_HA14_N
FMC_HPC_HA18_P
FMC_HPC_HA18_N
FMC_HPC_HA22_P
FMC_HPC_HA22_N
FMC_HPC_HB01_P
FMC_HPC_HB01_N
FMC_HPC_HB07_P
FMC_HPC_HB07_N
FMC_HPC_HB11_P
FMC_HPC_HB11_N
FMC_HPC_HB15_P
FMC_HPC_HB15_N
FMC_HPC_HB18_P
FMC_HPC_HB18_N
U84.6
U84.7
AA25
Y26
K4
FMC_HPC_CLK2_M2C_P(2)
FMC_HPC_CLK2_M2C_N(2)
FMC_HPC_HA02_P
U83.6
U83.7
AB25
AC25
AA28
AA29
AD34
AC34
V30
J3
K5
J6
K7
J7
K8
FMC_HPC_HA02_N
FMC_HPC_HA06_P
J9
AA26
AB26
AG33
AG32
AA30
AA31
T33
K10
K11
K13
K14
K16
K17
K19
K20
K22
K23
K25
K26
K28
K29
K31
K32
K34
K35
K37
K38
J10
J12
J13
J15
J16
J18
J19
J21
J22
J24
J25
J27
J28
J30
J31
J33
J34
J36
J37
FMC_HPC_HA06_N
FMC_HPC_HA10_P
FMC_HPC_HA10_N
FMC_HPC_HA17_CC_P
FMC_HPC_HA17_CC_N
FMC_HPC_HA21_P
W30
U31
T34
FMC_HPC_HA21_N
FMC_HPC_HA23_P
U30
U28
U26
V29
FMC_HPC_HA23_N
FMC_HPC_HB00_CC_P
FMC_HPC_HB00_CC_N
FMC_HPC_HB06_CC_P
FMC_HPC_HB06_CC_N
FMC_HPC_HB10_P
U27
AN32
AM32
AJ34
AH34
AJ29
AJ30
AE28
AE29
AD25
AD26
AF30
AG30
AF26
AE26
AF28
AF29
AE27
AD27
AG27
AG28
FMC_HPC_HB10_N
FMC_HPC_HB14_P
FMC_HPC_HB14_N
FMC_HPC_HB17_CC_P
FMC_HPC_HB17_CC_N
Notes:
1. Signals ending with _LS are not directly connected to the FMC HPC connector. _LS signals are connected between the listed U1
FPGA pin and a level shifter device. The signal connected between the shifted side of said device and the FMC HPC pin listed has
the same signal name, without the _LS on the end.
2. These signals do not connect to U1 FPGA pins. The pin numbers in the right-hand column identify the device and pin these signals
are connected to (U88.17 = U88 pin 17, and so on).
ML605 Hardware User Guide
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Chapter 1: ML605 Evaluation Board
Table 1-29: Power Supply Voltages for HPC Connector
Allowable
Voltage Range
Max Capacitive
Load
Voltage Supply
No Pins Max Amps Tolerance
VADJ
Fixed 2.5V
0-VADJ
0-VADJ
0-VIO_B_M2C
3.3V
4
2
1
1
1
4
2
4
1.15
1 mA
1 mA
20 mA
3
+/- 5%
+/- 5%
+/- 2%
+/- 2%
+/- 5%
+/- 5%
+/- 5%
1000 uF
500 uF
10 uF
VIO_B_M2C
VREF_A_M2C
VREF_B_M2C
3P3VAUX
3P3V
10 uF
150 uF
1000 uF
1000 uF
3.3V
12P0V
12V
1
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Detailed Description
20. VITA 57.1 FMC LPC Connector
The ML605 implements both the High Pin Count (HPC, J64) and Low Pin Count (LPC, J63)
connector options of VITA 57.1.1 FMC specification. This section discusses the FMC LPC
J63 connector.
The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low
Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector
form factor is used for both versions. The HPC version is fully populated with 400 pins
present, and the LPC version is partially populated with 160 pins.
The 10 x 40 rows of a FMC LPC connector provides connectivity for:
•
•
•
•
•
68 single-ended or 34 differential user defined signals
1 MGT
1 MGT clock
2 differential clocks
61 ground, 10 power connections
Of the above signal and clock connectivity capability, the ML605 implements the full set:
•
34 differential user-defined pairs:
34 LA pairs
♦
•
•
•
1 MGT
1 MGT clock
2 differential clocks
Signaling Speed Ratings:
•
•
Single-ended: 9 GHz / 18 Gb/s
Differential
♦
♦
♦
Optimal Vertical: 9 GHz / 18 Gb/s
Optimal Horizontal: 16 GHz / 32 Gb/s
High Density Vertical 7 GHz / 15 Gb/s
Mechanical specifications:
•
•
Samtec SEAM/SEAF Series
1.27mm x 1.27mm (0.050" x 0.050") pitch
The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on
a -3 dB insertion loss point within a two-level signaling environment.
Note: The ML605 board VADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed
at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The ML605 VITA 57.1 FMC interfaces
are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.
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Chapter 1: ML605 Evaluation Board
Table 1-30 shows the VITA 57.1 FMC LPC connections. The connector pinout is in
Any signal named FMC_LPC_xxxx that is wired between a U1 FPGA pin and some other
device does not appear in this table..
Table 1-30: VITA 57.1 FMC LPC Connections
J63 FMC
LPC Pin
U1 FPGA
Pin
J63 FMC
LPC Pin
U1 FPGA
Pin
Schematic Net Name
Schematic Net Name
C2
C3
FMC_LPC_DP0_C2M_P
FMC_LPC_DP0_C2M_N
FMC_LPC_DP0_M2C_P
FMC_LPC_DP0_M2C_N
FMC_LPC_LA06_P
D1
D2
D4
D5
FMC_LPC_GBTCLK0_M2C_P
FMC_LPC_GBTCLK0_M2C_N
FMC_LPC_LA01_CC_P
FMC_LPC_LA01_CC_N
FMC_LPC_LA05_P
M6
M5
C6
G3
D8
F31
E31
H34
H33
L25
L26
D34
C34
N28
N29
R28
R27
L33
M32
C7
G4
D9
C10
C11
C14
C15
C18
C19
C22
C23
C26
C27
K33
J34
D11
D12
D14
D15
D17
D18
D20
D21
D23
D24
D26
D27
FMC_LPC_LA06_N
FMC_LPC_LA10_P
FMC_LPC_LA05_N
F30
G30
C33
B34
L29
L30
R31
R32
FMC_LPC_LA09_P
FMC_LPC_LA10_N
FMC_LPC_LA14_P
FMC_LPC_LA09_N
FMC_LPC_LA13_P
FMC_LPC_LA14_N
FMC_LPC_LA18_CC_P
FMC_LPC_LA18_CC_N
FMC_LPC_LA27_P
FMC_LPC_LA13_N
FMC_LPC_LA17_CC_P
FMC_LPC_LA17_CC_N
FMC_LPC_LA23_P
FMC_LPC_LA27_N
FMC_LPC_LA23_N
FMC_LPC_LA26_P
FMC_LPC_LA26_N
G2
G3
FMC_LPC_CLK1_M2C_P
FMC_LPC_CLK1_M2C_N
FMC_LPC_LA00_CC_P
FMC_LPC_LA00_CC_N
FMC_LPC_LA03_P
F33
G33
K26
K27
J31
H2
H4
FMC_LPC_PRSNT_M2C_L
FMC_LPC_CLK0_M2C_P
FMC_LPC_CLK0_M2C_N
FMC_LPC_LA02_P
FMC_LPC_LA02_N
FMC_LPC_LA04_P
FMC_LPC_LA04_N
FMC_LPC_LA07_P
FMC_LPC_LA07_N
FMC_LPC_LA11_P
AD9
A10
B10
G31
H30
K28
J29
G6
H5
G7
H7
G9
H8
G10
G12
G13
G15
G16
G18
G19
FMC_LPC_LA03_N
FMC_LPC_LA08_P
J32
H10
H11
H13
H14
H16
H17
H19
J30
FMC_LPC_LA08_N
FMC_LPC_LA12_P
K29
E32
E33
A33
B33
G32
H32
D31
D32
C32
FMC_LPC_LA12_N
FMC_LPC_LA16_P
FMC_LPC_LA11_N
FMC_LPC_LA15_P
FMC_LPC_LA16_N
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Detailed Description
U1 FPGA
Table 1-30: VITA 57.1 FMC LPC Connections (Cont’d)
J63 FMC
LPC Pin
U1 FPGA
Pin
J63 FMC
LPC Pin
Schematic Net Name
Schematic Net Name
Pin
G21
G22
G24
G25
G27
G28
G30
G31
G33
G34
G36
G37
FMC_LPC_LA20_P
FMC_LPC_LA20_N
FMC_LPC_LA22_P
FMC_LPC_LA22_N
FMC_LPC_LA25_P
FMC_LPC_LA25_N
FMC_LPC_LA29_P
FMC_LPC_LA29_N
FMC_LPC_LA31_P
FMC_LPC_LA31_N
FMC_LPC_LA33_P
FMC_LPC_LA33_N
P29
R29
N27
P27
P31
P30
N34
P34
M31
L31
K32
K31
H20
H22
H23
H25
H26
H28
H29
H31
H32
H34
H35
H37
H38
FMC_LPC_LA15_N
FMC_LPC_LA19_P
FMC_LPC_LA19_N
FMC_LPC_LA21_P
FMC_LPC_LA21_N
FMC_LPC_LA24_P
FMC_LPC_LA24_N
FMC_LPC_LA28_P
FMC_LPC_LA28_N
FMC_LPC_LA30_P
FMC_LPC_LA30_N
FMC_LPC_LA32_P
FMC_LPC_LA32_N
B32
M30
N30
R26
T26
N32
P32
N33
M33
M26
M27
N25
M25
References
See the data sheet for the ROHS compliant FMC HPC Samtec SEARAY connector (carrier
side socket ASP-134486-01; module side plug ASP-134488-01), and the high-speed
characterization report for this connector system on the Samtec website. [Ref 32]
21. Power Management
AC Adapter and Input Power Jack/Switch
The ML605 is powered from a 12V source that is connected through a 6-pin (2X3) right-
angle Mini-Fit type connector J60. The AC-to-DC power supply included in the kit has a
mating 6-pin plug.
When the ML605 is installed into a table top or tower PC's PCIe slot, the ML605 is typically
powered from the PC ATX power supply. One of the ATX hard disk type 4-pin power
connectors is plugged into ML605 connector J25. The ML605 can be powered with the AC
power adapter even when plugged into a PC PCIe motherboard slot; however, users are
cautioned not to also connect an ATX 4-pin power connector to J25. See the caution notes
Caution! DO NOT plug a PC ATX power supply 6-pin connector into ML605 connector J60.
The ATX 6-pin connector has a different pinout than ML605 J60, and connecting the ATX 6-pin
connector will damage the ML605 and void the board warranty.
Caution! DO NOT apply power to J60 and the 4-pin ATX disk drive connector J25 at the same
The ML605 power can be turned on or off through the board mounted slide switch SW2.
When the switch is in the on position, a green LED (DS25) is illuminated.
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Chapter 1: ML605 Evaluation Board
Onboard Power Regulation
Figure 1-28 shows the ML605 onboard power supply architecture. The ML605 uses power
solutions from Texas Instruments.
X-Ref Target Figure 1-28
-
12V
PWR Jack
J25/J60
Power Supply
Linear Regulator TL1963
VCC5
U8
Power Controller 1
UCD9240PFC
U24
VCCINT
Switching Module PTD08A020W
1.00V@20A max U42
VCCAUX
Switching Module PTD08A010W
2.50V@10A max U91
VCC2V5, FPGA_VCC2V5
Switching Module PTD08A020W
2.5V@20A max U43
Linear Regulator TL1963A
1.8V@500mA max U79
VCC1V8
Power Controller 2
UCD9240PFC
U25
Switching Regulator UCD7230RG
1.00V@6A max U35
MGT_AVCC
MGT_AVTT
Switching Regulator UCD7230RG
1.20V@6A max U36
Switching Module PTD08A010W
VCC1V5, FPGA_VCC1V5
1.5V@10A max
U20
Switching Module PTD08A010W
VCC3V3
3.3V@10A max
U21
Sink/Source DDR Regulator
Linear Regulator TPS51200
0.75V@3A max
VTTDDR
U17
UG534_28_012010
Figure 1-28: ML605 Onboard Power Regulators
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Detailed Description
Power Rail Schematic
Table 1-31: Onboard Power System Devices
Reference
Designator
Power Rail
Net Name
Device Type
Description
PMBus Controller - Core (Addr = 52)
Voltage
Page
UCD9240PFC
PTD08A020W
PTD08A020W
PTD08A010W
U24
35
U42
20A 0.6V - 3.6V Adj. Switching Regulator VCCINT_FPGA
20A 0.6V - 3.6V Adj. Switching Regulator VCC2V5_FPGA
1.00V
2.50V
2.50V
36
U43
37
U91
10A 0.6V - 3.6V Adj. Switching Regulator
VCCAUX
38
UCD9240PFC
UCD7230RGWR
UCD7230RGWR
PTD08A010W
PTD08A010W
U25
U35
U36
U20
U21
PMBus Controller - Aux (Addr = 53)
6A 0.6V - 3.6V Adj. Switching Regulator
6A 0.6V - 3.6V Adj. Switching Regulator
10A 0.6V - 3.6V Adj. Switching Regulator
10A 0.6V - 3.6V Adj. Switching Regulator
40
41
42
43
44
MGT_AVCC
MGT_AVTT
VCC_1V5
1.00V
1.20V
1.50V
3.30V
VCC_3V3
TPS79518DCQR
TPS512300DRCT
U79
U17
500mA Fixed Linear Regulator
VCC_1V8
VTTDDR
1.80V
0.75V
45
45
3A DDR3 VTERM Tracking Linear
Regulator
TPS512300DRCT
TL1963
U17
U8
10mA Tracking Reference output
1.5A Fixed Linear Regulator
VTTVREF
VCC5
0.75V
5.00V
45
35
Voltage and current monitoring and control are available for selected power rails through
Texas Instruments’ Fusion Digital Power™ graphical user interface (GUI). Both onboard
TI power controllers are wired to the same PMBus. The PMBus connector, J3, is provided
for use with the TI USB Interface Adapter PMBus pod and associated TI GUI.
References
For more detailed information about this technology and the various power management
controllers and regulator modules offered by Texas Instruments, visit
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Chapter 1: ML605 Evaluation Board
22. System Monitor
The System Monitor provides information regarding the FPGA on-chip temperature and
power supply conditions via JTAG and an internal FPGA interface. The System Monitor
can also be used to monitor external analog signals via 17 external analog input channels.
For more information regarding this functionality, which is featured on every Virtex-6
This section provides a brief overview of the System Monitor related functionality that is
supported on the ML605.
Reference and Power Supply
The System Monitor has dedicated analog power supply pins and supports the use of an
external 1.25V reference IC (U23) for the analog-to-digital conversion process. An option
(using jumper J19) to select an on-chip reference is also provided; however, the highest
accuracy over a temperature range of -40°C to +125°C is obtained using an external
reference. Figure 1-29 illustrates the power supply and reference options on the ML605.
For a more detailed discussion of these requirements, see the Virtex-6 FPGA System Monitor
X-Ref Target Figure 1-29
-
VCC2V5
Analog Supply Filter
SYSMON_AVDD
C78
X5R
10V
C190
X5R
6.3V
1UF
J19
0.1UF
3
2
1
SYSMON_VREFP
VCC5
AGND
U23
REF3012
C383
X5R
10V
0.1UF
REF3012AIDBZT
1.25V
1
2
OUT
IN
GND
3
C79
X5R
10V
C191
X5R
6.3V
1UF
AGND
Ferrie Bead
0.1UF
Jumper on pins 1-2
Default Setting:
1-2 Select External Reference
2-3 Select On-Chip Reference
AGND
GND
UG534_29_081209
Figure 1-29: System Monitor External Reference
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Detailed Description
System Monitor Header (J35)
Figure 1-30 shows the pinout for the System Monitor 12-pin header. The header provides
user access to the analog power supply (A ) and the 1.25V reference shown in
Vdd
Figure 1-29, page 68. Access to the FPGA thermal diode and dedicated analog input
channel (Vp/Vn) is also provided on this header. The header can be used to connect user
specific analog signals and sensors to the system monitor.
The kelvin points for a 5 milliohm current sensing shunt in the FPGA 1V V
core supply
ccint
are also available on this header. By connecting header pins 9 to 11 and 10 to 12 using
jumpers, the system monitor can be used to monitor the FPGA core current and power
consumption. This can be used to collect useful power information about a particular
design or implementation.
X-Ref Target Figure 1-30
-
FPGA
Thermal Diode
access
System Monitor
Header
J35
FPGA_DX_P
1
3
2
NC
NC
FPGA_DX_N
4
5
6
SYSMON_AVDD
1.25V Reference
Vccint_shunt_N
7
8
9
10
12
Anti-alias Filter
Vccint_shunt_P
11
SYSMON_VN
SYSMON_VP
C169
X7R
16V
AGND
0.01UF
To Measure VCCINT Current:
Jumper on 9-11, 10-12
Dedicated Analog Inputs
Connect Vccint shunt to Vp,Vn
UG534_37 _081209
Figure 1-30: System Monitor Header (J35)
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Chapter 1: ML605 Evaluation Board
ML605 Board Power Monitor
In addition to monitoring the FPGA core supply power consumption, two auxiliary analog
input channels (of the 16 that are available) are used to implement a power monitor for the
entire ML605 board. The board power is monitored at the 12V power input connector.
Figure 1-31 shows how the power monitor is implemented and connected to the System
Monitor auxiliary input channels 12 and 13. A simple resistor divider is used to monitor
the 12V supply voltage and to provide a reference voltage to an instrumentation amplifier
(InAmp). The voltage on the auxiliary channel 12 is equal to supply voltage divided by 24
(~ 0.5V).
The InAmp is used to amplify (by a factor of 50) the voltage dropped across a 2 milliohm
current sense shunt. The voltage at the output of the InAmp is proportional to the current.
The voltage on auxiliary channel 13 = Current (amps) x 0.002 x 50. (e.g., 5A = 0.5V).
X-Ref Target Figure 1-31
-
2mΩ 1%
12V Supply Monitor
R1
R2
K1
K2
100nF
IN+
IN-
11.5kΩ 0.5%
499Ω 0.5%
~0.5V
V+
INA213
~470Ω
1kΩ
OUT
SC70-6
Package
50V/V
V
AUXP[13]
REF
10nF
Current Channel
10nF
GND
V
AUXN[13]
1kΩ
1kΩ
10nF
~470Ω
V
AUXP[12]
10nF
Voltage Channel
V
AUXN[12]
1kΩ
UG534_38 _081209
Figure 1-31: ML605 12V Power Monitor
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Detailed Description
Fan Controller
In highly demanding situations, active thermal management in the form of a heat sink and
fan may be required. In order to support this, drive circuitry for an external fan has been
provided on the ML605. A fan with tach output can be connect at header J59 as shown in
Figure 1-32. The fan PWM signal is generated by the FPGA and the tach input can be used
to close the control loop and regulate the fan speed. Alternatively, the FPGA temperature
as recorded by the System Monitor can be used to close the PWM control loop for the fan.
X-Ref Target Figure 1-32
-
VCC12_P
R367
J59
10.0K
1%
1/16W
1
2
3
GND
12V
SM_FAN_TACH
Tach
VCC2V5
R358
4.75K
1%
R369
10.0K
1%
1/16W
2
4
Q24
0
NDT3055L
3
1
SM_FAN_PWM
UG534_39 _081209
Figure 1-32: ML605 Fan Driver
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Chapter 1: ML605 Evaluation Board
FPGA Power Supply Margining
The PMBus (IIC), which provides access to the 2 x UDC9240 power controllers, can also be
accessed via FPGA I/O in addition to a dedicated header (J3), see Figure 1-33. A full
description of the UDC9240 functionality is outside the scope of this user guide. However,
this useful feature can be used, for example, to margin the FPGA and board power
supplies when evaluating a design. The System Monitor provides accurate measurements
of the on-chip supply voltages as the FPGA supplies are margined. The PMBus (and fan)
connections are shown in Figure 1-33.
X-Ref Target Figure 1-33
-
TI_V3P3
PMBus Connector
R301
100K
R299
R300
UDC9240
100K
100K
J3
5%
5%
5%
NC
NC
NC
1
3
5
7
9
2
4
6
8
NC
NC
PMBUS_ALERT 35
PMBUS_DATA 20
10
PMBUS_CLK
19
PMBUS_CTRL 36
DGND1
9240
R335
1.0M
5%
BANK 34
6vlx240tff1156
AGND1
AJ9
AH9
AB10
AC10
M10
PMBUS_CTRL_LS
IO_L11N_SRCC_34_AJ9
IO_L11P_SRCC_34_AH9
IO_L10N_MRCC_34_AB10
IO_L10P_MRCC_34_AC10
IO_L9N_MRCC_34_M10
IO_L9P_MRCC_34_L10
PMBUS_ALERT_LS
PMBUS_DATA_LS
PMBUS_CLK_LS
SM_FAN_TACH
L10
SM_FAN_PWM
UG534_35_081209
Figure 1-33: UDC9240 PMBus Access
System Monitor ML605 Demonstration Design
The various features described in this section are easily evaluated using a MicroBlaze™
based reference designed provided with the ML605 Evaluation Board. This reference
design supports a UART based interface using a terminal program such as Hyperterminal
to provide information on the FPGA power supplies, temperature, and power
consumption. In addition, the UART interface can be used to margin the FPGA supplies
over the PMBus.
The System Monitor functionality can also be accessed at any time via JTAG using the
ChipScope Pro Analyzer tool without design modifications or cores inserted into a user
design. The ChipScope Pro Analyzer tool automatically connects to the System Monitor
via a JTAG cable after a connection is established.
References
For more information on using the System Monitor and an overview of the tool support for
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Configuration Options
Configuration Options
The FPGA on the ML605 Evaluation Board can be configured by the following methods:
•
•
•
•
For more information, see the Virtex-6 FPGA Configuration User Guide at
Table 1-32: Mode Switch S2 Settings
Mode Pins (M2,M1,M0)
Configuration Mode
Slave SelectMAP
BPI Mode
110
010
101
JTAG
With the mode set to JTAG 101, the ML605 will not attempt to boot or load a bitstream
from either of the Flash devices. If a CompactFlash (CF) card is installed in the CF socket
U73, System ACE CF will attempt to load a bitstream from the CF card image address
pointed to by the image select switch S1. With no CF card present, the ML605 can be
configured via the onboard JTAG controller and USB download cable as described above.
With the mode set to either Slave SelectMAP 110, or BPI Mode 010, the FPGA will attempt
to configure itself from the selected Flash device as described in “3. 128 Mb Platform Flash
Note: S1 switch 4 is the System ACE controller enable switch. When ON, this switch allows the
System ACE to boot at power-on if it finds a CF card present. In order to boot from BPI Flash U4 or
Xilinx Platform Flash (U27) without System ACE contention, S1 switch 4 must be OFF.
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Appendix A
Default Switch and Jumper Settings
Table A-1: Default Switch Settings
REFDES
Function/Type
Default
SW2
Board power slide-switch
off
User GPIO 8-pole DIP switch
8
7
6
5
4
3
2
1
off
off
off
off
off
off
off
off
SW1
System ACE CF configuration and image select 4-pole DIP switch
(1)
4
3
2
1
SysACE Mode = 1
off
off
off
off
SysAce CFGAddr 2 = 0
SysAce CFGAddr 1 = 0
SysAce CFGAddr 0 = 0
S1
FPGA mode, boot PROM select and FPGA CCLK select 6-pole DIP
switch
6
5
FLASH_A23 = 0
M2 = 0
off
off
S2
M1 = 1
4
on
M[2:0] = 010 = Master BPI-Up
3
2
1
M0 = 0
off
on
off
CS_SEL = 1 = boot from BPI Flash
EXT_CCLK = 0
Notes:
1. S1 position 4 is the System ACE controller enable switch. When ON, this switch allows the System
ACE to boot at power on if it finds a CF card present. In order to boot from BPI Flash or Xilinx Platform
Flash without System ACE contention, S1 switch 4 must be OFF.
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Appendix A: Default Switch and Jumper Settings
Table A-2: Default Jumper Settings
Jumper REFDES
Function
Default
J69
System ACE CF Error LED Enable
Jump 1-2
GMII:
pins 1-2: GMII/MII to Cu
pins 2-3: SGMII to Cu, no clk
J66
J67
Jump 1 - 2
pins 1-2: GMII/MII to Cu
pins 2-3: SGMII to Cu, no clk
Jump 1 - 2
no jumper
J68
J66 pins 1-2, J68 ON: RGMII, modified MII in Cu
FMC Bypass:
J18
exclude FMC LPC connector
exclude FMC LPC connector
Jump 1 - 2
Jump 1 - 2
J17
System Monitor:
J19
Test_mon_vrefp sourced by U23, REF3012
measure voltage on R-kelvin on 12V rail
Jump 1 - 2
Jump 9 - 11,
Jump 10 - 12
J35
SFP Module:
J54
Full BW
Jump 1 - 2
Jump 1 - 2
J65
PCIe Lane Size:
J42
SFP Enable
1 lane
Jump 1 - 2
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Appendix B
VITA 57.1 FMC LPC (J63) and HPC (J64)
Connector Pinout
Figure B-1 shows the pinout of the FMC LPC connector. Pins marked NC are not
connected.
X-Ref Target Figure B-1
-
K
J
H
G
F
E
D
C
B
A
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VR EF_A_M2C
PR SNT_M2C_L
GND
CLK0_M2C_P
CLK0_M2C_N
GND
GND
CLK1_M2C_P
CLK1_M2C_N
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PG_C2M
GND
GND
DP0_C2M_P
DP0_C2M_N
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
3
NC
GND
4
NC
NC GBTCLK0_M2C_P
NC GBTCLK0_M2C_N
5
NC
GND
GND
6
NC
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
LA13_N
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
DP0_M2C_P
DP0_M2C_N
GND
7
NC
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
LA21_N
GND
LA24_P
LA24_N
GND
8
NC
9
NC
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA26_P
LA26_N
GND
LA27_P
LA27_N
GND
TCK
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
TDI
S CL
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
TDO
S DA
3P3VAUX
TMS
GND
GND
TR ST_L
GA1
GA0
12P0V
GND
3P3V
LA32_P
LA32_N
GND
GND
12P0V
GND
3P3V
GND
3P3V
VADJ
GND
GND
VADJ
3P3V
Figure B-1: FMC LPC Connector Pinout
ML605 Hardware User Guide
77
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Appendix B: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout
Figure B-2 shows the pinout of the FMC HPC connector.
X-Ref Target Figure B-2
-
Figure B-2: FMC HPC Connector Pinout
78
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Appendix C
ML605 Master UCF
The UCF template is provided for designs that target the ML605. Net names provided in
the constraints below correlate with net names on the ML605 Rev. D schematic. On
identifying the appropriate pins, the net names below should be replaced with net names
Users can refer to the UCF files generated by tools such as MIG (Memory Interface
Generator for memory interfaces) and BSB (Base System Builder) for more detailed
information concerning the I/O standards required for each particular interface. The FMC
connectors J63 and J64 are connected to 2.5V V banks. Because each user’s FMC card
cco
implements customer-specific circuitry, the FMC bank I/O standards must be uniquely
defined by each customer.
NET "CLK_33MHZ_SYSACE"
NET "CPU_RESET"
##
LOC = "AE16";
LOC = "H10";
## 93 on U19
## 2
on SW10 pushbutton (active-High)
NET "DDR3_A0"
NET "DDR3_A1"
NET "DDR3_A2"
NET "DDR3_A3"
NET "DDR3_A4"
NET "DDR3_A5"
NET "DDR3_A6"
NET "DDR3_A7"
NET "DDR3_A8"
NET "DDR3_A9"
NET "DDR3_A10"
NET "DDR3_A11"
NET "DDR3_A12"
NET "DDR3_A13"
NET "DDR3_A14"
NET "DDR3_A15"
NET "DDR3_BA0"
NET "DDR3_BA1"
NET "DDR3_BA2"
NET "DDR3_CAS_B"
NET "DDR3_CKE0"
NET "DDR3_CKE1"
NET "DDR3_CLK0_N"
NET "DDR3_CLK0_P"
NET "DDR3_CLK1_N"
NET "DDR3_CLK1_P"
NET "DDR3_D0"
NET "DDR3_D1"
NET "DDR3_D2"
NET "DDR3_D3"
NET "DDR3_D4"
NET "DDR3_D5"
NET "DDR3_D6"
NET "DDR3_D7"
LOC = "L14";
LOC = "A16";
LOC = "B16";
LOC = "E16";
LOC = "D16";
LOC = "J17";
LOC = "A15";
LOC = "B15";
LOC = "G15";
LOC = "F15";
LOC = "M16";
LOC = "M15";
LOC = "H15";
LOC = "J15";
LOC = "D15";
LOC = "C15";
LOC = "K19";
LOC = "J19";
LOC = "L15";
LOC = "C17";
LOC = "M18";
LOC = "M17";
LOC = "H18";
LOC = "G18";
LOC = "L16";
LOC = "K16";
LOC = "J11";
LOC = "E13";
LOC = "F13";
LOC = "K11";
LOC = "L11";
LOC = "K13";
LOC = "K12";
LOC = "D11";
## 98 on J1
## 97 on J1
## 96 on J1
## 95 on J1
## 92 on J1
## 91 on J1
## 90 on J1
## 86 on J1
## 89 on J1
## 85 on J1
## 107 on J1
## 84 on J1
## 83 on J1
## 119 on J1
## 80 on J1
## 78 on J1
## 109 on J1
## 108 on J1
## 79 on J1
## 115 on J1
## 73 on J1
## 74 on J1
## 103 on J1
## 101 on J1
## 104 on J1
## 102 on J1
## 5
## 7
on J1
on J1
## 15 on J1
## 17 on J1
## 4
## 6
on J1
on J1
## 16 on J1
## 18 on J1
ML605 Hardware User Guide
79
UG534 (v1.2.1) January 21, 2010
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Appendix C: ML605 Master UCF
NET "DDR3_D8"
NET "DDR3_D9"
NET "DDR3_D10"
NET "DDR3_D11"
NET "DDR3_D12"
NET "DDR3_D13"
NET "DDR3_D14"
NET "DDR3_D15"
NET "DDR3_D16"
NET "DDR3_D17"
NET "DDR3_D18"
NET "DDR3_D19"
NET "DDR3_D20"
NET "DDR3_D21"
NET "DDR3_D22"
NET "DDR3_D23"
NET "DDR3_D24"
NET "DDR3_D25"
NET "DDR3_D26"
NET "DDR3_D27"
NET "DDR3_D28"
NET "DDR3_D29"
NET "DDR3_D30"
NET "DDR3_D31"
NET "DDR3_D32"
NET "DDR3_D33"
NET "DDR3_D34"
NET "DDR3_D35"
NET "DDR3_D36"
NET "DDR3_D37"
NET "DDR3_D38"
NET "DDR3_D39"
NET "DDR3_D40"
NET "DDR3_D41"
NET "DDR3_D42"
NET "DDR3_D43"
NET "DDR3_D44"
NET "DDR3_D45"
NET "DDR3_D46"
NET "DDR3_D47"
NET "DDR3_D48"
NET "DDR3_D49"
NET "DDR3_D50"
NET "DDR3_D51"
NET "DDR3_D52"
NET "DDR3_D53"
NET "DDR3_D54"
NET "DDR3_D55"
NET "DDR3_D56"
NET "DDR3_D57"
NET "DDR3_D58"
NET "DDR3_D59"
NET "DDR3_D60"
NET "DDR3_D61"
NET "DDR3_D62"
NET "DDR3_D63"
NET "DDR3_DM0"
NET "DDR3_DM1"
NET "DDR3_DM2"
NET "DDR3_DM3"
NET "DDR3_DM4"
NET "DDR3_DM5"
NET "DDR3_DM6"
NET "DDR3_DM7"
NET "DDR3_DQS0_N"
LOC = "M13";
LOC = "J14";
LOC = "B13";
LOC = "B12";
LOC = "G10";
LOC = "M11";
LOC = "C12";
LOC = "A11";
LOC = "G11";
LOC = "F11";
LOC = "D14";
LOC = "C14";
LOC = "G12";
LOC = "G13";
LOC = "F14";
LOC = "H14";
LOC = "C19";
LOC = "G20";
LOC = "E19";
LOC = "F20";
LOC = "A20";
LOC = "A21";
LOC = "E22";
LOC = "E23";
LOC = "G21";
LOC = "B21";
LOC = "A23";
LOC = "A24";
LOC = "C20";
LOC = "D20";
LOC = "J20";
LOC = "G22";
LOC = "D26";
LOC = "F26";
LOC = "B26";
LOC = "E26";
LOC = "C24";
LOC = "D25";
LOC = "D27";
LOC = "C25";
LOC = "C27";
LOC = "B28";
LOC = "D29";
LOC = "B27";
LOC = "G27";
LOC = "A28";
LOC = "E24";
LOC = "G25";
LOC = "F28";
LOC = "B31";
LOC = "H29";
LOC = "H28";
LOC = "B30";
LOC = "A30";
LOC = "E29";
LOC = "F29";
LOC = "E11";
LOC = "B11";
LOC = "E14";
LOC = "D19";
LOC = "B22";
LOC = "A26";
LOC = "A29";
LOC = "A31";
LOC = "E12";
## 21 on J1
## 23 on J1
## 33 on J1
## 35 on J1
## 22 on J1
## 24 on J1
## 34 on J1
## 36 on J1
## 39 on J1
## 41 on J1
## 51 on J1
## 53 on J1
## 40 on J1
## 42 on J1
## 50 on J1
## 52 on J1
## 57 on J1
## 59 on J1
## 67 on J1
## 69 on J1
## 56 on J1
## 58 on J1
## 68 on J1
## 70 on J1
## 129 on J1
## 131 on J1
## 141 on J1
## 143 on J1
## 130 on J1
## 132 on J1
## 140 on J1
## 142 on J1
## 147 on J1
## 149 on J1
## 157 on J1
## 159 on J1
## 146 on J1
## 148 on J1
## 158 on J1
## 160 on J1
## 163 on J1
## 165 on J1
## 175 on J1
## 177 on J1
## 164 on J1
## 166 on J1
## 174 on J1
## 176 on J1
## 181 on J1
## 183 on J1
## 191 on J1
## 193 on J1
## 180 on J1
## 182 on J1
## 192 on J1
## 194 on J1
## 11 on J1
## 28 on J1
## 46 on J1
## 63 on J1
## 136 on J1
## 153 on J1
## 170 on J1
## 187 on J1
## 10 on J1
80
ML605 Hardware User Guide
UG534 (v1.2.1) January 21, 2010
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NET "DDR3_DQS0_P"
NET "DDR3_DQS1_N"
NET "DDR3_DQS1_P"
NET "DDR3_DQS2_N"
NET "DDR3_DQS2_P"
NET "DDR3_DQS3_N"
NET "DDR3_DQS3_P"
NET "DDR3_DQS4_N"
NET "DDR3_DQS4_P"
NET "DDR3_DQS5_N"
NET "DDR3_DQS5_P"
NET "DDR3_DQS6_N"
NET "DDR3_DQS6_P"
NET "DDR3_DQS7_N"
NET "DDR3_DQS7_P"
NET "DDR3_ODT0"
NET "DDR3_ODT1"
NET "DDR3_RAS_B"
NET "DDR3_RESET_B"
NET "DDR3_S0_B"
NET "DDR3_S1_B"
NET "DDR3_TEMP_EVENT"
NET "DDR3_WE_B"
##
LOC = "D12";
LOC = "J12";
LOC = "H12";
LOC = "A14";
LOC = "A13";
LOC = "H20";
LOC = "H19";
LOC = "C23";
LOC = "B23";
LOC = "A25";
LOC = "B25";
LOC = "G28";
LOC = "H27";
LOC = "D30";
LOC = "C30";
LOC = "F18";
LOC = "E17";
LOC = "L19";
LOC = "E18";
LOC = "K18";
LOC = "K17";
LOC = "D17";
LOC = "B17";
## 12 on J1
## 27 on J1
## 29 on J1
## 45 on J1
## 47 on J1
## 62 on J1
## 64 on J1
## 135 on J1
## 137 on J1
## 152 on J1
## 154 on J1
## 169 on J1
## 171 on J1
## 186 on J1
## 188 on J1
## 116 on J1
## 120 on J1
## 110 on J1
## 30 on J1
## 114 on J1
## 121 on J1
## 198 on J1
## 113 on J1
NET "DVI_D0"
NET "DVI_D1"
NET "DVI_D2"
NET "DVI_D3"
NET "DVI_D4"
NET "DVI_D5"
NET "DVI_D6"
NET "DVI_D7"
NET "DVI_D8"
NET "DVI_D9"
NET "DVI_D10"
NET "DVI_D11"
NET "DVI_DE"
NET "DVI_GPIO1_FMC_C2M_PG_LS"
NET "DVI_H"
NET "DVI_RESET_B_LS"
NET "DVI_V"
NET "DVI_XCLK_N"
NET "DVI_XCLK_P"
##
LOC = "AJ19";
LOC = "AH19";
LOC = "AM17";
LOC = "AM16";
LOC = "AD17";
LOC = "AE17";
LOC = "AK18";
LOC = "AK17";
LOC = "AE18";
LOC = "AF18";
LOC = "AL16";
LOC = "AK16";
LOC = "AD16";
LOC = "K9";
## 63 on U38 (thru series R111 47.5 ohm)
## 62 on U38 (thru series R110 47.5 ohm)
## 61 on U38 (thru series R109 47.5 ohm)
## 60 on U38 (thru series R108 47.5 ohm)
## 59 on U38 (thru series R107 47.5 ohm)
## 58 on U38 (thru series R106 47.5 ohm)
## 55 on U38 (thru series R105 47.5 ohm)
## 54 on U38 (thru series R104 47.5 ohm)
## 53 on U38 (thru series R103 47.5 ohm)
## 52 on U38 (thru series R102 47.5 ohm)
## 51 on U38 (thru series R101 47.5 ohm)
## 50 on U38 (thru series R100 47.5 ohm)
## 2 on U38 (thru series R112 47.5 ohm)
## 18 on U32 (not wired to U38)
LOC = "AN17";
LOC = "AP17";
LOC = "AD15";
LOC = "AC17";
LOC = "AC18";
## 4 on U38 (thru series R113 47.5 ohm)
## 2 on U32 (DVI_RESET_B pin 13 on U38)
## 5 on U38 (thru series R114 47.5 ohm)
## 56 on U38
## 57 on U38
NET "FLASH_A0"
NET "FLASH_A1"
NET "FLASH_A2"
NET "FLASH_A3"
NET "FLASH_A4"
NET "FLASH_A5"
NET "FLASH_A6"
NET "FLASH_A7"
NET "FLASH_A8"
NET "FLASH_A9"
NET "FLASH_A10"
NET "FLASH_A11"
NET "FLASH_A12"
NET "FLASH_A13"
NET "FLASH_A14"
NET "FLASH_A15"
NET "FLASH_A16"
NET "FLASH_A17"
NET "FLASH_A18"
NET "FLASH_A19"
NET "FLASH_A20"
LOC = "AL8";
LOC = "AK8";
LOC = "AC9";
LOC = "AD10";
LOC = "C8";
LOC = "B8";
LOC = "E9";
LOC = "E8";
LOC = "A8";
LOC = "A9";
LOC = "D9";
LOC = "C9";
LOC = "D10";
LOC = "C10";
LOC = "F10";
LOC = "F9";
LOC = "AH8";
LOC = "AG8";
LOC = "AP9";
LOC = "AN9";
LOC = "AF10";
## 29 on U4, A1 on U27
## 25 on U4, B1 on U27
## 24 on U4, C1 on U27
## 23 on U4, D1 on U27
## 22 on U4, D2 on U27
## 21 on U4, A2 on U27
## 20 on U4, C2 on U27
## 19 on U4, A3 on U27
## 8 on U4, B3 on U27
## 7 on U4, C3 on U27
## 6 on U4, D3 on U27
## 5 on U4, C4 on U27
## 4 on U4, A5 on U27
## 3 on U4, B5 on U27
## 2 on U4, C5 on U27
## 1 on U4, D7 on U27
## 55 on U4, D8 on U27
## 18 on U4, A7 on U27
## 17 on U4, B7 on U27
## 16 on U4, C7 on U27
## 11 on U4, C8 on U27
ML605 Hardware User Guide
81
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Appendix C: ML605 Master UCF
NET "FLASH_A21"
NET "FLASH_A22"
NET "FLASH_A23"
NET "FLASH_D0"
NET "FLASH_D1"
NET "FLASH_D2"
NET "FLASH_D3"
NET "FLASH_D4"
NET "FLASH_D5"
NET "FLASH_D6"
NET "FLASH_D7"
NET "FLASH_D8"
NET "FLASH_D9"
NET "FLASH_D10"
NET "FLASH_D11"
NET "FLASH_D12"
NET "FLASH_D13"
NET "FLASH_D14"
NET "FLASH_D15"
NET "FLASH_WAIT"
NET "FPGA_FWE_B"
NET "FPGA_FOE_B"
NET "FPGA_CCLK"
NET "PLATFLASH_L_B"
NET "FPGA_FCS_B"
LOC = "AF9";
LOC = "AL9";
LOC = "AA23";
LOC = "AF24";
LOC = "AF25";
LOC = "W24";
LOC = "V24";
LOC = "H24";
LOC = "H25";
LOC = "P24";
LOC = "R24";
LOC = "G23";
LOC = "H23";
LOC = "N24";
LOC = "N23";
LOC = "F23";
LOC = "F24";
LOC = "L24";
LOC = "M23";
LOC = "J26";
LOC = "AF23";
LOC = "AA24";
LOC = "K8";
## 10 on U4, A8 on U27
## 9 on U4, G1 on U27
## 26 on U4
## 34 on U4 (thru series R215 100 ohm), F2 on U27
## 36 on U4 (thru series R216 100 ohm), E2 on U27
## 39 on U4 (thru series R217 100 ohm), G3 on U27
## 41 on U4 (thru series R218 100 ohm), E4 on U27
## 47 on U4 (thru series R219 100 ohm), E5 on U27
## 49 on U4 (thru series R220 100 ohm), G5 on U27
## 51 on U4 (thru series R221 100 ohm), G6 on U27
## 53 on U4 (thru series R222 100 ohm), H7 on U27
## 35 on U4 (thru series R223 100 ohm), E1 on U27
## 37 on U4 (thru series R224 100 ohm), E3 on U27
## 40 on U4 (thru series R225 100 ohm), F3 on U27
## 42 on U4 (thru series R226 100 ohm), F4 on U27
## 48 on U4 (thru series R227 100 ohm), F5 on U27
## 50 on U4 (thru series R228 100 ohm), H5 on U27
## 52 on U4 (thru series R229 100 ohm), G7 on U27
## 54 on U4 (thru series R230 100 ohm), E7 on U27
## 56 on U4
## 14 on U4, G8 on U27
## 32 on U4, F8 on U27
##
##
F1 on U27
H1 on U27
LOC = "AC23";
LOC = "Y24";
## 30 on U4, B4 on U27 (U10 and switch S2.2 setting
select either U4 or U27)
##
##
NET "FMC_HPC_CLK0_M2C_N"
NET "FMC_HPC_CLK0_M2C_P"
NET "FMC_HPC_CLK1_M2C_N"
NET "FMC_HPC_CLK1_M2C_P"
NET "FMC_HPC_CLK2_M2C_IO_N"
NET "FMC_HPC_CLK2_M2C_IO_P"
NET "FMC_HPC_CLK2_M2C_MGT_C_N"
NET "FMC_HPC_CLK2_M2C_MGT_C_P"
NET "FMC_HPC_CLK3_M2C_IO_N"
NET "FMC_HPC_CLK3_M2C_IO_P"
NET "FMC_HPC_CLK3_M2C_MGT_C_N"
NET "FMC_HPC_CLK3_M2C_MGT_C_P"
NET "FMC_HPC_DP0_C2M_N"
NET "FMC_HPC_DP0_C2M_P"
NET "FMC_HPC_DP0_M2C_N"
NET "FMC_HPC_DP0_M2C_P"
NET "FMC_HPC_DP1_C2M_N"
NET "FMC_HPC_DP1_C2M_P"
NET "FMC_HPC_DP1_M2C_N"
NET "FMC_HPC_DP1_M2C_P"
NET "FMC_HPC_DP2_C2M_N"
NET "FMC_HPC_DP2_C2M_P"
NET "FMC_HPC_DP2_M2C_N"
NET "FMC_HPC_DP2_M2C_P"
NET "FMC_HPC_DP3_C2M_N"
NET "FMC_HPC_DP3_C2M_P"
NET "FMC_HPC_DP3_M2C_N"
NET "FMC_HPC_DP3_M2C_P"
NET "FMC_HPC_DP4_C2M_N"
NET "FMC_HPC_DP4_C2M_P"
NET "FMC_HPC_DP4_M2C_N"
NET "FMC_HPC_DP4_M2C_P"
NET "FMC_HPC_DP5_C2M_N"
NET "FMC_HPC_DP5_C2M_P"
NET "FMC_HPC_DP5_M2C_N"
NET "FMC_HPC_DP5_M2C_P"
NET "FMC_HPC_DP6_C2M_N"
NET "FMC_HPC_DP6_C2M_P"
LOC = "K23";
LOC = "K24";
LOC = "AP21";
LOC = "AP20";
LOC = "AC30";
LOC = "AD30";
LOC = "AB5";
LOC = "AB6";
LOC = "AF34";
LOC = "AE34";
LOC = "AH5";
LOC = "AH6";
LOC = "AB2";
LOC = "AB1";
LOC = "AC4";
LOC = "AC3";
LOC = "AD2";
LOC = "AD1";
LOC = "AE4";
LOC = "AE3";
LOC = "AF2";
LOC = "AF1";
LOC = "AF6";
LOC = "AF5";
LOC = "AH2";
LOC = "AH1";
LOC = "AG4";
LOC = "AG3";
LOC = "AK2";
LOC = "AK1";
LOC = "AJ4";
LOC = "AJ3";
LOC = "AM2";
LOC = "AM1";
LOC = "AL4";
LOC = "AL3";
LOC = "AN4";
LOC = "AN3";
## H5 on J64
## H4 on J64
## G3 on J64
## G2 on J64
## 15 on U83
## 16 on U83
## 2
## 2
on series C399 0.1uF
on series C398 0.1uF
## J3 on J64
## J2 on J64
## 2
## 2
on series C397 0.1uF
on series C396 0.1uF
## C3 on J64
## C2 on J64
## C7 on J64
## C6 on J64
## A23 on J64
## A22 on J64
## A3 on J64
## A2 on J64
## A27 on J64
## A26 on J64
## A7 on J64
## A6 on J64
## A31 on J64
## A30 on J64
## A11 on J64
## A10 on J64
## A35 on J64
## A34 on J64
## A15 on J64
## A14 on J64
## A39 on J64
## A38 on J64
## A19 on J64
## A18 on J64
## B37 on J64
## B36 on J64
82
ML605 Hardware User Guide
UG534 (v1.2.1) January 21, 2010
Download from Www.Somanuals.com. All Manuals Search And Download.
NET "FMC_HPC_DP6_M2C_N"
NET "FMC_HPC_DP6_M2C_P"
NET "FMC_HPC_DP7_C2M_N"
NET "FMC_HPC_DP7_C2M_P"
NET "FMC_HPC_DP7_M2C_N"
NET "FMC_HPC_DP7_M2C_P"
NET "FMC_HPC_GBTCLK0_M2C_N"
NET "FMC_HPC_GBTCLK0_M2C_P"
NET "FMC_HPC_GBTCLK1_M2C_N"
NET "FMC_HPC_GBTCLK1_M2C_P"
NET "FMC_HPC_HA00_CC_N"
NET "FMC_HPC_HA00_CC_P"
NET "FMC_HPC_HA01_CC_N"
NET "FMC_HPC_HA01_CC_P"
NET "FMC_HPC_HA02_N"
NET "FMC_HPC_HA02_P"
NET "FMC_HPC_HA03_N"
NET "FMC_HPC_HA03_P"
NET "FMC_HPC_HA04_N"
NET "FMC_HPC_HA04_P"
NET "FMC_HPC_HA05_N"
NET "FMC_HPC_HA05_P"
NET "FMC_HPC_HA06_N"
NET "FMC_HPC_HA06_P"
NET "FMC_HPC_HA07_N"
NET "FMC_HPC_HA07_P"
NET "FMC_HPC_HA08_N"
NET "FMC_HPC_HA08_P"
NET "FMC_HPC_HA09_N"
NET "FMC_HPC_HA09_P"
NET "FMC_HPC_HA10_N"
NET "FMC_HPC_HA10_P"
NET "FMC_HPC_HA11_N"
NET "FMC_HPC_HA11_P"
NET "FMC_HPC_HA12_N"
NET "FMC_HPC_HA12_P"
NET "FMC_HPC_HA13_N"
NET "FMC_HPC_HA13_P"
NET "FMC_HPC_HA14_N"
NET "FMC_HPC_HA14_P"
NET "FMC_HPC_HA15_N"
NET "FMC_HPC_HA15_P"
NET "FMC_HPC_HA16_N"
NET "FMC_HPC_HA16_P"
NET "FMC_HPC_HA17_CC_N"
NET "FMC_HPC_HA17_CC_P"
NET "FMC_HPC_HA18_N"
NET "FMC_HPC_HA18_P"
NET "FMC_HPC_HA19_N"
NET "FMC_HPC_HA19_P"
NET "FMC_HPC_HA20_N"
NET "FMC_HPC_HA20_P"
NET "FMC_HPC_HA21_N"
NET "FMC_HPC_HA21_P"
NET "FMC_HPC_HA22_N"
NET "FMC_HPC_HA22_P"
NET "FMC_HPC_HA23_N"
NET "FMC_HPC_HA23_P"
NET "FMC_HPC_HB00_CC_N"
NET "FMC_HPC_HB00_CC_P"
NET "FMC_HPC_HB01_N"
NET "FMC_HPC_HB01_P"
NET "FMC_HPC_HB02_N"
NET "FMC_HPC_HB02_P"
NET "FMC_HPC_HB03_N"
LOC = "AM6";
LOC = "AM5";
LOC = "AP2";
LOC = "AP1";
LOC = "AP6";
LOC = "AP5";
LOC = "AD5";
LOC = "AD6";
LOC = "AK5";
LOC = "AK6";
LOC = "AF33";
LOC = "AE33";
LOC = "AC29";
LOC = "AD29";
LOC = "AC25";
LOC = "AB25";
LOC = "Y26";
LOC = "AA25";
LOC = "AC28";
LOC = "AB28";
LOC = "AC27";
LOC = "AB27";
LOC = "AA29";
LOC = "AA28";
LOC = "AB26";
LOC = "AA26";
LOC = "AF31";
LOC = "AG31";
LOC = "AB31";
LOC = "AB30";
LOC = "AC34";
LOC = "AD34";
LOC = "AG32";
LOC = "AG33";
LOC = "AE32";
LOC = "AD32";
LOC = "AD31";
LOC = "AE31";
LOC = "AA31";
LOC = "AA30";
LOC = "AC32";
LOC = "AB32";
LOC = "AB33";
LOC = "AC33";
LOC = "W30";
LOC = "V30";
LOC = "T34";
LOC = "T33";
LOC = "U32";
LOC = "U33";
LOC = "V33";
LOC = "V32";
LOC = "U30";
LOC = "U31";
LOC = "V29";
LOC = "U28";
LOC = "U27";
LOC = "U26";
LOC = "AG30";
LOC = "AF30";
LOC = "AM32";
LOC = "AN32";
LOC = "AP33";
LOC = "AP32";
LOC = "AM31";
## B17 on J64
## B16 on J64
## B33 on J64
## B32 on J64
## B13 on J64
## B12 on J64
## D5 on J64
## D4 on J64
## B21 on J64
## B20 on J64
## F5 on J64
## F4 on J64
## E3 on J64
## E2 on J64
## K8 on J64
## K7 on J64
## J7 on J64
## J6 on J64
## F8 on J64
## F7 on J64
## E7 on J64
## E6 on J64
## K11 on J64
## K10 on J64
## J10 on J64
## J9 on J64
## F11 on J64
## F10 on J64
## E10 on J64
## E9 on J64
## K14 on J64
## K13 on J64
## J13 on J64
## J12 on J64
## F14 on J64
## F13 on J64
## E13 on J64
## E12 on J64
## J16 on J64
## J15 on J64
## F17 on J64
## F16 on J64
## E16 on J64
## E15 on J64
## K17 on J64
## K16 on J64
## J19 on J64
## J18 on J64
## F20 on J64
## F19 on J64
## E19 on J64
## E18 on J64
## K20 on J64
## K19 on J64
## J22 on J64
## J21 on J64
## K23 on J64
## K22 on J64
## K26 on J64
## K25 on J64
## J25 on J64
## J24 on J64
## F23 on J64
## F22 on J64
## E22 on J64
ML605 Hardware User Guide
83
UG534 (v1.2.1) January 21, 2010
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix C: ML605 Master UCF
NET "FMC_HPC_HB03_P"
NET "FMC_HPC_HB04_N"
NET "FMC_HPC_HB04_P"
NET "FMC_HPC_HB05_N"
NET "FMC_HPC_HB05_P"
NET "FMC_HPC_HB06_CC_N"
NET "FMC_HPC_HB06_CC_P"
NET "FMC_HPC_HB07_N"
NET "FMC_HPC_HB07_P"
NET "FMC_HPC_HB08_N"
NET "FMC_HPC_HB08_P"
NET "FMC_HPC_HB09_N"
NET "FMC_HPC_HB09_P"
NET "FMC_HPC_HB10_N"
NET "FMC_HPC_HB10_P"
NET "FMC_HPC_HB11_N"
NET "FMC_HPC_HB11_P"
NET "FMC_HPC_HB12_N"
NET "FMC_HPC_HB12_P"
NET "FMC_HPC_HB13_N"
NET "FMC_HPC_HB13_P"
NET "FMC_HPC_HB14_N"
NET "FMC_HPC_HB14_P"
NET "FMC_HPC_HB15_N"
NET "FMC_HPC_HB15_P"
NET "FMC_HPC_HB16_N"
NET "FMC_HPC_HB16_P"
NET "FMC_HPC_HB17_CC_N"
NET "FMC_HPC_HB17_CC_P"
NET "FMC_HPC_HB18_N"
NET "FMC_HPC_HB18_P"
NET "FMC_HPC_HB19_N"
NET "FMC_HPC_HB19_P"
NET "FMC_HPC_LA00_CC_N"
NET "FMC_HPC_LA00_CC_P"
NET "FMC_HPC_LA01_CC_N"
NET "FMC_HPC_LA01_CC_P"
NET "FMC_HPC_LA02_N"
NET "FMC_HPC_LA02_P"
NET "FMC_HPC_LA03_N"
NET "FMC_HPC_LA03_P"
NET "FMC_HPC_LA04_N"
NET "FMC_HPC_LA04_P"
NET "FMC_HPC_LA05_N"
NET "FMC_HPC_LA05_P"
NET "FMC_HPC_LA06_N"
NET "FMC_HPC_LA06_P"
NET "FMC_HPC_LA07_N"
NET "FMC_HPC_LA07_P"
NET "FMC_HPC_LA08_N"
NET "FMC_HPC_LA08_P"
NET "FMC_HPC_LA09_N"
NET "FMC_HPC_LA09_P"
NET "FMC_HPC_LA10_N"
NET "FMC_HPC_LA10_P"
NET "FMC_HPC_LA11_N"
NET "FMC_HPC_LA11_P"
NET "FMC_HPC_LA12_N"
NET "FMC_HPC_LA12_P"
NET "FMC_HPC_LA13_N"
NET "FMC_HPC_LA13_P"
NET "FMC_HPC_LA14_N"
NET "FMC_HPC_LA14_P"
NET "FMC_HPC_LA15_N"
NET "FMC_HPC_LA15_P"
LOC = "AL30";
LOC = "AL33";
LOC = "AM33";
LOC = "AN34";
LOC = "AN33";
LOC = "AE26";
LOC = "AF26";
LOC = "AH34";
LOC = "AJ34";
LOC = "AK32";
LOC = "AK33";
LOC = "AK34";
LOC = "AL34";
LOC = "AF29";
LOC = "AF28";
LOC = "AJ30";
LOC = "AJ29";
LOC = "AJ32";
LOC = "AJ31";
LOC = "AH32";
LOC = "AH33";
LOC = "AD27";
LOC = "AE27";
LOC = "AE29";
LOC = "AE28";
LOC = "AH30";
LOC = "AH29";
LOC = "AG28";
LOC = "AG27";
LOC = "AD26";
LOC = "AD25";
LOC = "AK31";
LOC = "AL31";
LOC = "AF21";
LOC = "AF20";
LOC = "AL19";
LOC = "AK19";
LOC = "AD20";
LOC = "AC20";
LOC = "AD19";
LOC = "AC19";
LOC = "AE19";
LOC = "AF19";
LOC = "AH22";
LOC = "AG22";
LOC = "AG21";
LOC = "AG20";
LOC = "AJ21";
LOC = "AK21";
LOC = "AJ22";
LOC = "AK22";
LOC = "AL18";
LOC = "AM18";
LOC = "AL20";
LOC = "AM20";
LOC = "AN22";
LOC = "AM22";
LOC = "AL21";
LOC = "AM21";
LOC = "AN18";
LOC = "AP19";
LOC = "AN20";
LOC = "AN19";
LOC = "AL23";
LOC = "AM23";
## E21 on J64
## F26 on J64
## F25 on J64
## E25 on J64
## E24 on J64
## K29 on J64
## K28 on J64
## J28 on J64
## J27 on J64
## F29 on J64
## F28 on J64
## E28 on J64
## E27 on J64
## K32 on J64
## K31 on J64
## J31 on J64
## J30 on J64
## F32 on J64
## F31 on J64
## E31 on J64
## E30 on J64
## K35 on J64
## K34 on J64
## J34 on J64
## J33 on J64
## F35 on J64
## F34 on J64
## K38 on J64
## K37 on J64
## J37 on J64
## J36 on J64
## E34 on J64
## E33 on J64
## G7 on J64
## G6 on J64
## D9 on J64
## D8 on J64
## H8 on J64
## H7 on J64
## G10 on J64
## G9 on J64
## H11 on J64
## H10 on J64
## D12 on J64
## D11 on J64
## C11 on J64
## C10 on J64
## H14 on J64
## H13 on J64
## G13 on J64
## G12 on J64
## D15 on J64
## D14 on J64
## C15 on J64
## C14 on J64
## H17 on J64
## H16 on J64
## G16 on J64
## G15 on J64
## D18 on J64
## D17 on J64
## C19 on J64
## C18 on J64
## H20 on J64
## H19 on J64
84
ML605 Hardware User Guide
UG534 (v1.2.1) January 21, 2010
Download from Www.Somanuals.com. All Manuals Search And Download.
NET "FMC_HPC_LA16_N"
NET "FMC_HPC_LA16_P"
NET "FMC_HPC_LA17_CC_N"
NET "FMC_HPC_LA17_CC_P"
NET "FMC_HPC_LA18_CC_N"
NET "FMC_HPC_LA18_CC_P"
NET "FMC_HPC_LA19_N"
NET "FMC_HPC_LA19_P"
NET "FMC_HPC_LA20_N"
NET "FMC_HPC_LA20_P"
NET "FMC_HPC_LA21_N"
NET "FMC_HPC_LA21_P"
NET "FMC_HPC_LA22_N"
NET "FMC_HPC_LA22_P"
NET "FMC_HPC_LA23_N"
NET "FMC_HPC_LA23_P"
NET "FMC_HPC_LA24_N"
NET "FMC_HPC_LA24_P"
NET "FMC_HPC_LA25_N"
NET "FMC_HPC_LA25_P"
NET "FMC_HPC_LA26_N"
NET "FMC_HPC_LA26_P"
NET "FMC_HPC_LA27_N"
NET "FMC_HPC_LA27_P"
NET "FMC_HPC_LA28_N"
NET "FMC_HPC_LA28_P"
NET "FMC_HPC_LA29_N"
NET "FMC_HPC_LA29_P"
NET "FMC_HPC_LA30_N"
NET "FMC_HPC_LA30_P"
NET "FMC_HPC_LA31_N"
NET "FMC_HPC_LA31_P"
NET "FMC_HPC_LA32_N"
NET "FMC_HPC_LA32_P"
NET "FMC_HPC_LA33_N"
NET "FMC_HPC_LA33_P"
NET "FMC_HPC_PG_M2C_LS"
NET "FMC_HPC_PRSNT_M2C_L"
##
LOC = "AN23";
LOC = "AP22";
LOC = "AM27";
LOC = "AN27";
LOC = "AJ25";
LOC = "AH25";
LOC = "AN24";
LOC = "AN25";
LOC = "AL24";
LOC = "AK23";
LOC = "AP29";
LOC = "AN29";
LOC = "AP26";
LOC = "AP27";
LOC = "AM26";
LOC = "AL26";
LOC = "AM30";
LOC = "AN30";
LOC = "AM28";
LOC = "AN28";
LOC = "AL25";
LOC = "AM25";
LOC = "AP31";
LOC = "AP30";
LOC = "AJ27";
LOC = "AK27";
LOC = "AK28";
LOC = "AL28";
LOC = "AK24";
LOC = "AJ24";
LOC = "AK29";
LOC = "AL29";
LOC = "AG26";
LOC = "AG25";
LOC = "AH24";
LOC = "AH23";
LOC = "J27";
LOC = "AP25";
## G19 on J64
## G18 on J64
## D21 on J64
## D20 on J64
## C23 on J64
## C22 on J64
## H23 on J64
## H22 on J64
## G22 on J64
## G21 on J64
## H26 on J64
## H25 on J64
## G25 on J64
## G24 on J64
## D24 on J64
## D23 on J64
## H29 on J64
## H28 on J64
## G28 on J64
## G27 on J64
## D27 on J64
## D26 on J64
## C27 on J64
## C26 on J64
## H32 on J64
## H31 on J64
## G31 on J64
## G30 on J64
## H35 on J64
## H34 on J64
## G34 on J64
## G33 on J64
## H38 on J64
## H37 on J64
## G37 on J64
## G36 on J64
## F1 on J64
## H2 on J64
NET "FMC_LPC_CLK0_M2C_N"
NET "FMC_LPC_CLK0_M2C_P"
NET "FMC_LPC_CLK1_M2C_N"
NET "FMC_LPC_CLK1_M2C_P"
NET "FMC_LPC_DP0_C2M_N"
NET "FMC_LPC_DP0_C2M_P"
NET "FMC_LPC_DP0_M2C_N"
NET "FMC_LPC_DP0_M2C_P"
NET "FMC_LPC_GBTCLK0_M2C_N"
NET "FMC_LPC_GBTCLK0_M2C_P"
NET "FMC_LPC_IIC_SCL_LS"
NET "FMC_LPC_IIC_SDA_LS"
NET "FMC_LPC_LA00_CC_N"
NET "FMC_LPC_LA00_CC_P"
NET "FMC_LPC_LA01_CC_N"
NET "FMC_LPC_LA01_CC_P"
NET "FMC_LPC_LA02_N"
NET "FMC_LPC_LA02_P"
NET "FMC_LPC_LA03_N"
NET "FMC_LPC_LA03_P"
NET "FMC_LPC_LA04_N"
NET "FMC_LPC_LA04_P"
NET "FMC_LPC_LA05_N"
NET "FMC_LPC_LA05_P"
NET "FMC_LPC_LA06_N"
NET "FMC_LPC_LA06_P"
LOC = "B10";
LOC = "A10";
LOC = "G33";
LOC = "F33";
LOC = "D2";
LOC = "D1";
LOC = "G4";
LOC = "G3";
LOC = "M5";
LOC = "M6";
LOC = "AF13";
LOC = "AG13";
LOC = "K27";
LOC = "K26";
LOC = "E31";
LOC = "F31";
LOC = "H30";
LOC = "G31";
LOC = "J32";
LOC = "J31";
LOC = "J29";
LOC = "K28";
LOC = "H33";
LOC = "H34";
LOC = "J34";
LOC = "K33";
## H5 on J63
## H4 on J63
## G3 on J63
## G2 on J63
## C3 on J63
## C2 on J63
## C7 on J63
## C6 on J63
## D5 on J63
## D4 on J63
## 2
## 2
of Q26
of Q27
## G7 on J63
## G6 on J63
## D9 on J63
## D8 on J63
## H8 on J63
## H7 on J63
## G10 on J63
## G9 on J63
## H11 on J63
## H10 on J63
## D12 on J63
## D11 on J63
## C11 on J63
## C10 on J63
ML605 Hardware User Guide
85
UG534 (v1.2.1) January 21, 2010
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix C: ML605 Master UCF
NET "FMC_LPC_LA07_N"
NET "FMC_LPC_LA07_P"
NET "FMC_LPC_LA08_N"
NET "FMC_LPC_LA08_P"
NET "FMC_LPC_LA09_N"
NET "FMC_LPC_LA09_P"
NET "FMC_LPC_LA10_N"
NET "FMC_LPC_LA10_P"
NET "FMC_LPC_LA11_N"
NET "FMC_LPC_LA11_P"
NET "FMC_LPC_LA12_N"
NET "FMC_LPC_LA12_P"
NET "FMC_LPC_LA13_N"
NET "FMC_LPC_LA13_P"
NET "FMC_LPC_LA14_N"
NET "FMC_LPC_LA14_P"
NET "FMC_LPC_LA15_N"
NET "FMC_LPC_LA15_P"
NET "FMC_LPC_LA16_N"
NET "FMC_LPC_LA16_P"
NET "FMC_LPC_LA17_CC_N"
NET "FMC_LPC_LA17_CC_P"
NET "FMC_LPC_LA18_CC_N"
NET "FMC_LPC_LA18_CC_P"
NET "FMC_LPC_LA19_N"
NET "FMC_LPC_LA19_P"
NET "FMC_LPC_LA20_N"
NET "FMC_LPC_LA20_P"
NET "FMC_LPC_LA21_N"
NET "FMC_LPC_LA21_P"
NET "FMC_LPC_LA22_N"
NET "FMC_LPC_LA22_P"
NET "FMC_LPC_LA23_N"
NET "FMC_LPC_LA23_P"
NET "FMC_LPC_LA24_N"
NET "FMC_LPC_LA24_P"
NET "FMC_LPC_LA25_N"
NET "FMC_LPC_LA25_P"
NET "FMC_LPC_LA26_N"
NET "FMC_LPC_LA26_P"
NET "FMC_LPC_LA27_N"
NET "FMC_LPC_LA27_P"
NET "FMC_LPC_LA28_N"
NET "FMC_LPC_LA28_P"
NET "FMC_LPC_LA29_N"
NET "FMC_LPC_LA29_P"
NET "FMC_LPC_LA30_N"
NET "FMC_LPC_LA30_P"
NET "FMC_LPC_LA31_N"
NET "FMC_LPC_LA31_P"
NET "FMC_LPC_LA32_N"
NET "FMC_LPC_LA32_P"
NET "FMC_LPC_LA33_N"
NET "FMC_LPC_LA33_P"
NET "FMC_LPC_PRSNT_M2C_L"
##
LOC = "H32";
LOC = "G32";
LOC = "K29";
LOC = "J30";
LOC = "L26";
LOC = "L25";
LOC = "G30";
LOC = "F30";
LOC = "D32";
LOC = "D31";
LOC = "E33";
LOC = "E32";
LOC = "C34";
LOC = "D34";
LOC = "B34";
LOC = "C33";
LOC = "B32";
LOC = "C32";
LOC = "B33";
LOC = "A33";
LOC = "N29";
LOC = "N28";
LOC = "L30";
LOC = "L29";
LOC = "N30";
LOC = "M30";
LOC = "R29";
LOC = "P29";
LOC = "T26";
LOC = "R26";
LOC = "P27";
LOC = "N27";
LOC = "R27";
LOC = "R28";
LOC = "P32";
LOC = "N32";
LOC = "P30";
LOC = "P31";
LOC = "M32";
LOC = "L33";
LOC = "R32";
LOC = "R31";
LOC = "M33";
LOC = "N33";
LOC = "P34";
LOC = "N34";
LOC = "M27";
LOC = "M26";
LOC = "L31";
LOC = "M31";
LOC = "M25";
LOC = "N25";
LOC = "K31";
LOC = "K32";
LOC = "AD9";
## H14 on J63
## H13 on J63
## G13 on J63
## G12 on J63
## D15 on J63
## D14 on J63
## C15 on J63
## C14 on J63
## H17 on J63
## H16 on J63
## G16 on J63
## G15 on J63
## D18 on J63
## D17 on J63
## C19 on J63
## C18 on J63
## H20 on J63
## H19 on J63
## G19 on J63
## G18 on J63
## D21 on J63
## D20 on J63
## C23 on J63
## C22 on J63
## H23 on J63
## H22 on J63
## G22 on J63
## G21 on J63
## H26 on J63
## H25 on J63
## G25 on J63
## G24 on J63
## D24 on J63
## D23 on J63
## H29 on J63
## H28 on J63
## G28 on J63
## G27 on J63
## D27 on J63
## D26 on J63
## C27 on J63
## C26 on J63
## H32 on J63
## H31 on J63
## G31 on J63
## G30 on J63
## H35 on J63
## H34 on J63
## G34 on J63
## G33 on J63
## H38 on J63
## H37 on J63
## G37 on J63
## G36 on J63
## H2 on J63
## NET "FPGA_CCLK"
NET "FPGA_DONE"
NET "FPGA_DX_N"
LOC = "K8";
LOC = "R8";
LOC = "W17";
LOC = "W18";
LOC = "Y24";
LOC = "AA24";
LOC = "AF23";
## SEE NET "FLASH_NN" GROUP
## 2
## 4
## 2
on "DONE" LED DS13
on J35
on J35
NET "FPGA_DX_P"
## NET "FPGA_FCS_B"
## NET "FPGA_FOE_B"
## NET "FPGA_FWE_B"
##
## SEE NET "FLASH_NN" GROUP
## SEE NET "FLASH_NN" GROUP
## SEE NET "FLASH_NN" GROUP
NET "FPGA_INIT_B"
LOC = "P8";
## 1
on Q14 ("INIT" LED DS31 driver)
86
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NET "FPGA_M0"
NET "FPGA_M1"
NET "FPGA_M2"
NET "FPGA_PROG_B"
NET "FPGA_TCK"
NET "FPGA_TDI"
NET "FPGA_TMS"
NET "FPGA_VBATT"
##
LOC = "U8";
LOC = "W8";
LOC = "V8";
LOC = "L8";
LOC = "AE8";
LOC = "AD8";
LOC = "AF8";
LOC = "N8";
## 3
## 4
## 4
## 1
## 80 on U19
## 82 on U19
## 85 on U19
on S2 DIP switch (active-High)
on S2 DIP switch (active-High)
on S2 DIP switch (active-High)
on SW4 pushbutton (active-Low)
## 1
on B1 (battery + terminal)
NET "GPIO_DIP_SW1"
NET "GPIO_DIP_SW2"
NET "GPIO_DIP_SW3"
NET "GPIO_DIP_SW4"
NET "GPIO_DIP_SW5"
NET "GPIO_DIP_SW6"
NET "GPIO_DIP_SW7"
NET "GPIO_DIP_SW8"
##
LOC = "D22";
LOC = "C22";
LOC = "L21";
LOC = "L20";
LOC = "C18";
LOC = "B18";
LOC = "K22";
LOC = "K21";
## 1
## 2
## 3
## 4
## 5
## 6
## 7
## 8
on SW1 DIP switch (active-High)
on SW1 DIP switch (active-High)
on SW1 DIP switch (active-High)
on SW1 DIP switch (active-High)
on SW1 DIP switch (active-High)
on SW1 DIP switch (active-High)
on SW1 DIP switch (active-High)
on SW1 DIP switch (active-High)
NET "GPIO_LED_0"
NET "GPIO_LED_1"
NET "GPIO_LED_2"
NET "GPIO_LED_3"
NET "GPIO_LED_4"
NET "GPIO_LED_5"
NET "GPIO_LED_6"
NET "GPIO_LED_7"
##
LOC = "AC22";
LOC = "AC24";
LOC = "AE22";
LOC = "AE23";
LOC = "AB23";
LOC = "AG23";
LOC = "AE24";
LOC = "AD24";
## 2
## 2
## 2
## 2
## 2
## 2
## 2
## 2
on LED DS12, 1 on J62
on LED DS11, 2 on J62
on LED DS9, 3 on J62
on LED DS10, 4 on J62
on LED DS15, 5 on J62
on LED DS14, 6 on J62
on LED DS22, 7 on J62
on LED DS21, 8 on J62
NET "GPIO_LED_C"
NET "GPIO_LED_E"
NET "GPIO_LED_N"
NET "GPIO_LED_S"
NET "GPIO_LED_W"
##
LOC = "AP24";
LOC = "AE21";
LOC = "AH27";
LOC = "AH28";
LOC = "AD21";
## 2
## 2
## 2
## 2
## 2
on LED DS16
on LED DS19
on LED DS20
on LED DS18
on LED DS17
NET "GPIO_SW_C"
NET "GPIO_SW_E"
NET "GPIO_SW_N"
NET "GPIO_SW_S"
NET "GPIO_SW_W"
##
LOC = "G26";
LOC = "G17";
LOC = "A19";
LOC = "A18";
LOC = "H17";
## 2
## 2
## 2
## 2
## 2
on SW9 pushbutton (active-High)
on SW7 pushbutton (active-High)
on SW5 pushbutton (active-High)
on SW6 pushbutton (active-High)
on SW8 pushbutton (active-High)
NET "IIC_SCL_DVI"
NET "IIC_SCL_MAIN_LS"
NET "IIC_SCL_SFP"
NET "IIC_SDA_DVI"
NET "IIC_SDA_MAIN_LS"
NET "IIC_SDA_SFP"
##
LOC = "AN10";
LOC = "AK9";
LOC = "AA34";
LOC = "AP10";
LOC = "AE9";
LOC = "AA33";
## 2
## 2
## 2
## 2
## 2
## 2
on Q5, 15 on U38
on Q19
on Q23
on Q6, 14 on U38
on Q20
on Q21
NET "LCD_DB4_LS"
NET "LCD_DB5_LS"
NET "LCD_DB6_LS"
NET "LCD_DB7_LS"
NET "LCD_E_LS"
NET "LCD_RS_LS"
NET "LCD_RW_LS"
##
LOC = "AD14";
LOC = "AK11";
LOC = "AJ11";
LOC = "AE12";
LOC = "AK12";
LOC = "T28";
LOC = "AC14";
## 4
## 3
## 2
## 1
## 9
on J41
on J41
on J41
on J41
on J41
## 11 on J41
## 10 on J41
NET "P30_CS_SEL"
##
LOC = "AJ12";
## 2
on S2 DIP switch (active-High),1 on U10
NET "PCIE_100M_MGT0_N"
NET "PCIE_100M_MGT0_P"
NET "PCIE_250M_MGT1_N"
NET "PCIE_250M_MGT1_P"
NET "PCIE_PERST_B_LS"
NET "PCIE_RX0_N"
NET "PCIE_RX0_P"
NET "PCIE_RX1_N"
NET "PCIE_RX1_P"
LOC = "P5";
LOC = "P6";
LOC = "V5";
LOC = "V6";
LOC = "AE13";
LOC = "J4";
LOC = "J3";
LOC = "K6";
LOC = "K5";
## 15 on U14
## 16 on U14
## 18 on U9
## 17 on U9
## 4
on U32
## B15 on P1
## B14 on P1
## B20 on P1
## B19 on P1
ML605 Hardware User Guide
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Appendix C: ML605 Master UCF
NET "PCIE_RX2_N"
NET "PCIE_RX2_P"
NET "PCIE_RX3_N"
NET "PCIE_RX3_P"
NET "PCIE_RX4_N"
NET "PCIE_RX4_P"
NET "PCIE_RX5_N"
NET "PCIE_RX5_P"
NET "PCIE_RX6_N"
NET "PCIE_RX6_P"
NET "PCIE_RX7_N"
NET "PCIE_RX7_P"
NET "PCIE_TX0_N"
NET "PCIE_TX0_P"
NET "PCIE_TX1_N"
NET "PCIE_TX1_P"
NET "PCIE_TX2_N"
NET "PCIE_TX2_P"
NET "PCIE_TX3_N"
NET "PCIE_TX3_P"
NET "PCIE_TX4_N"
NET "PCIE_TX4_P"
NET "PCIE_TX5_N"
NET "PCIE_TX5_P"
NET "PCIE_TX6_N"
NET "PCIE_TX6_P"
NET "PCIE_TX7_N"
NET "PCIE_TX7_P"
NET "PCIE_WAKE_B_LS"
##
LOC = "L4";
LOC = "L3";
LOC = "N4";
LOC = "N3";
LOC = "R4";
LOC = "R3";
LOC = "U4";
LOC = "U3";
LOC = "W4";
LOC = "W3";
LOC = "AA4";
LOC = "AA3";
LOC = "F2";
LOC = "F1";
LOC = "H2";
LOC = "H1";
LOC = "K2";
LOC = "K1";
LOC = "M2";
LOC = "M1";
LOC = "P2";
LOC = "P1";
LOC = "T2";
LOC = "T1";
LOC = "V2";
LOC = "V1";
LOC = "Y2";
LOC = "Y1";
LOC = "AD22";
## B24 on P1
## B23 on P1
## B28 on P1
## B27 on P1
## B34 on P1
## B33 on P1
## B38 on P1
## B37 on P1
## B42 on P1
## B41 on P1
## B46 on P1
## B45 on P1
## A17 on P1
## A16 on P1
## A22 on P1
## A21 on P1
## A26 on P1
## A25 on P1
## A30 on P1
## A29 on P1
## A36 on P1
## A35 on P1
## A40 on P1
## A39 on P1
## A44 on P1
## A43 on P1
## A48 on P1
## A47 on P1
## B11 on P1
NET "PHY_COL"
NET "PHY_CRS"
NET "PHY_INT"
NET "PHY_MDC"
LOC = "AK13";
LOC = "AL13";
LOC = "AH14";
LOC = "AP14";
LOC = "AN14";
LOC = "AH13";
LOC = "AP11";
LOC = "AM13";
LOC = "AN13";
LOC = "AF14";
LOC = "AE14";
LOC = "AN12";
LOC = "AM12";
LOC = "AD11";
LOC = "AC12";
LOC = "AC13";
LOC = "AG12";
LOC = "AD12";
LOC = "AJ10";
LOC = "AH12";
LOC = "AM11";
LOC = "AL11";
LOC = "AG10";
LOC = "AG11";
LOC = "AL10";
LOC = "AM10";
LOC = "AE11";
LOC = "AF11";
LOC = "AH10";
## 114 on U80
## 115 on U80
## 32 on U80
## 35 on U80
## 33 on U80
## 36 on U80
NET "PHY_MDIO"
NET "PHY_RESET"
NET "PHY_RXCLK"
NET "PHY_RXCTL_RXDV"
NET "PHY_RXD0"
NET "PHY_RXD1"
NET "PHY_RXD2"
NET "PHY_RXD3"
NET "PHY_RXD4"
NET "PHY_RXD5"
NET "PHY_RXD6"
NET "PHY_RXD7"
NET "PHY_RXER"
NET "PHY_TXCLK"
NET "PHY_TXCTL_TXEN"
NET "PHY_TXC_GTXCLK"
NET "PHY_TXD0"
NET "PHY_TXD1"
NET "PHY_TXD2"
NET "PHY_TXD3"
NET "PHY_TXD4"
NET "PHY_TXD5"
NET "PHY_TXD6"
NET "PHY_TXD7"
NET "PHY_TXER"
##
## 7
## 4
## 3
on U80
on U80
on U80
## 128 on U80
## 126 on U80
## 125 on U80
## 124 on U80
## 123 on U80
## 121 on U80
## 120 on U80
## 9
on U80
## 10 on U80
## 16 on U80
## 14 on U80
## 18 on U80
## 19 on U80
## 20 on U80
## 24 on U80
## 25 on U80
## 26 on U80
## 28 on U80
## 29 on U80
## 13 on U80
## NET "PLATFLASH_L_B"
##
LOC = "AC23";
## SEE NET "FLASH_NN" GROUP
NET "PMBUS_ALERT_LS"
NET "PMBUS_CLK_LS"
NET "PMBUS_CTRL_LS"
LOC = "AH9";
LOC = "AC10";
LOC = "AJ9";
## 2
## 2
## 2
on Q15
on Q18
on Q16
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NET "PMBUS_DATA_LS"
##
NET "SFP_LOS"
NET "SFP_RX_N"
NET "SFP_RX_P"
NET "SFP_TX_DISABLE_FPGA"
NET "SFP_TX_N"
NET "SFP_TX_P"
##
LOC = "AB10";
## 2
## 8
## 12 on P4
## 13 on P4
## 1
## 19 on P4
## 18 on P4
on Q17
on P4
LOC = "V23";
LOC = "E4";
LOC = "E3";
LOC = "AP12";
LOC = "C4";
LOC = "C3";
on Q22
NET "SGMIICLK_QO_N"
NET "SGMIICLK_QO_P"
NET "SGMII_RX_N"
NET "SGMII_RX_P"
NET "SGMII_TX_N"
NET "SGMII_TX_P"
##
LOC = "H5";
LOC = "H6";
LOC = "B6";
LOC = "B5";
LOC = "A4";
LOC = "A3";
## 2
## 2
## 1
## 1
## 1
## 1
on series C55 0.1uF
on series C56 0.1uF
on series C163 0.01uF
on series C162 0.01uF
on series C164 0.01uF
on series C165 0.01uF
NET "SMA_REFCLK_N"
NET "SMA_REFCLK_P"
NET "SMA_RX_N"
NET "SMA_RX_P"
NET "SMA_TX_N"
NET "SMA_TX_P"
##
LOC = "F5";
LOC = "F6";
LOC = "D6";
LOC = "D5";
LOC = "B2";
LOC = "B1";
## 1
## 1
## 1
## 1
## 1
## 1
on series C61 0.1uF
on series C62 0.1uF
on series C57 0.1uF
on series C58 0.1uF
on J27 SMA
on J26 SMA
NET "SM_FAN_PWM"
NET "SM_FAN_TACH"
##
LOC = "L10";
LOC = "M10";
## 1
## 2
on Q24
on R368
NET "SYSACE_CFGTDI"
NET "SYSACE_D0"
NET "SYSACE_D1"
NET "SYSACE_D2"
NET "SYSACE_D3"
NET "SYSACE_D4"
NET "SYSACE_D5"
NET "SYSACE_D6"
NET "SYSACE_D7"
NET "SYSACE_MPA00"
NET "SYSACE_MPA01"
NET "SYSACE_MPA02"
NET "SYSACE_MPA03"
NET "SYSACE_MPA04"
NET "SYSACE_MPA05"
NET "SYSACE_MPA06"
NET "SYSACE_MPBRDY"
NET "SYSACE_MPCE"
NET "SYSACE_MPIRQ"
NET "SYSACE_MPOE"
NET "SYSACE_MPWE"
##
LOC = "AC8";
LOC = "AM15";
LOC = "AJ17";
LOC = "AJ16";
LOC = "AP16";
LOC = "AG16";
LOC = "AH15";
LOC = "AF16";
LOC = "AN15";
LOC = "AC15";
LOC = "AP15";
LOC = "AG17";
LOC = "AH17";
LOC = "AG15";
LOC = "AF15";
LOC = "AK14";
LOC = "AJ15";
LOC = "AJ14";
LOC = "L9";
## 81 on U19
## 66 on U19
## 65 on U19
## 63 on U19
## 62 on U19
## 61 on U19
## 60 on U19
## 59 on U19
## 58 on U19
## 70 on U19
## 69 on U19
## 68 on U19
## 67 on U19
## 45 on U19
## 44 on U19
## 43 on U19
## 39 on U19
## 42 on U19
## 41 on U19
## 77 on U19
## 76 on U19
LOC = "AL15";
LOC = "AL14";
NET "SYSCLK_N"
NET "SYSCLK_P"
##
LOC = "H9";
LOC = "J9";
## 5
## 4
on U11, 5 on U89 (DNP)
on U11, 4 on U89 (DNP)
NET "USB_1_CTS"
NET "USB_1_RTS"
NET "USB_1_RX"
NET "USB_1_TX"
##
LOC = "T24";
LOC = "T23";
LOC = "J25";
LOC = "J24";
## 22 on U34
## 23 on U34
## 24 on U34
## 25 on U34
NET "USB_A0_LS"
NET "USB_A1_LS"
NET "USB_CS_B_LS"
NET "USB_D0_LS"
NET "USB_D1_LS"
NET "USB_D2_LS"
NET "USB_D3_LS"
NET "USB_D4_LS"
NET "USB_D5_LS"
LOC = "Y32";
LOC = "W26";
LOC = "W27";
LOC = "R33";
LOC = "R34";
LOC = "T30";
LOC = "T31";
LOC = "T29";
LOC = "V28";
## 14 on U30
## 2
## 18 on U29
## 8 on U31
## 14 on U31
## 6 on U31
## 16 on U31
## 4 on U31
## 18 on U31
on U29
ML605 Hardware User Guide
89
UG534 (v1.2.1) January 21, 2010
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Appendix C: ML605 Master UCF
NET "USB_D6_LS"
NET "USB_D7_LS"
NET "USB_D8_LS"
NET "USB_D9_LS"
NET "USB_D10_LS"
NET "USB_D11_LS"
NET "USB_D12_LS"
NET "USB_D13_LS"
NET "USB_D14_LS"
NET "USB_D15_LS"
NET "USB_INT_LS"
NET "USB_RD_B_LS"
NET "USB_RESET_B_LS"
NET "USB_WR_B_LS"
##
LOC = "V27";
LOC = "U25";
LOC = "Y28";
LOC = "W32";
LOC = "W31";
LOC = "Y29";
LOC = "W29";
LOC = "Y34";
LOC = "Y33";
LOC = "Y31";
LOC = "Y27";
LOC = "W25";
LOC = "T25";
LOC = "V25";
## 2
## 12 on U30
## 14 on U29
## 8
## 12 on U29
## 2 on U30
## 18 on U30
## 4 on U30
## 16 on U30
## 6
## 6
## 16 on U29
## 8
## 4
on U31
on U29
on U30
on U29
on U30
on U29
NET "USER_CLOCK"
NET "USER_SMA_CLOCK_N"
NET "USER_SMA_CLOCK_P"
NET "USER_SMA_GPIO_N"
NET "USER_SMA_GPIO_P"
##
LOC = "U23";
LOC = "M22";
LOC = "L23";
LOC = "W34";
LOC = "V34";
## 5
## 1
## 1
## 1
## 1
on X5
on J55 SMA
on J58 SMA
on J56 SMA
on J57 SMA
NET "VAUX_CURR_N"
NET "VAUX_CURR_P"
NET "VAUX_VOLT_N"
NET "VAUX_VOLT_P"
LOC = "P26";
LOC = "P25";
LOC = "M28";
LOC = "L28";
## 1
## 1
## 1
## 1
on series R373 1.00K
on series R370 1.00K
on series R371 1.00K
on series R372 1.00K
90
ML605 Hardware User Guide
UG534 (v1.2.1) January 21, 2010
Download from Www.Somanuals.com. All Manuals Search And Download.
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