Virtex-5 FPGA ML561
Memory Interfaces
Development Board
User Guide
UG199 (v1.2) April 19, 2008
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Table of Contents
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Documentation and Reference Design CD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Initial Board Check Before Applying Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Applying Power to the Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Hardware Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DDR400 SDRAM Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DDR2 DIMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DDR2 SDRAM Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
QDRII SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
RLDRAM II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Memory Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DDR400 and DDR2 Component Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DDR2 SDRAM DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
QDRII and RLDRAM II Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
RS-232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
200 MHz LVPECL Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SMA Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
33 MHz Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
33 MHz System ACE Controller Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
GTP Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
User I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
General-Purpose Headers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Seven-Segment Displays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Light Emitting Diodes (LEDs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power On or Off Slide Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Soft Touch Probe Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power Measurement Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Liquid Crystal Display Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Voltage Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Board Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FPGA Internal Power Budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Termination and Transmission Line Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
JTAG Chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Parallel IV Cable Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
System ACE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Signal Integrity Correlation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DDR2 Component Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DDR2 Component Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DDR2 DIMM Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DDR2 DIMM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
QDRII Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
QDRII Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Summary and Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
How to Generate a User-Specific FPGA IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . 93
FPGA #1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
FPGA #2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
FPGA #3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Display Hardware Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Peripheral Device KS0713 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Controller – Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Controller – LCD Panel Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Controller – Power Supply Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Operation Example of the 64128EFCBC-3LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Read/Write Characteristics (6800 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
LCD Panel Used in Full Graphics Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
LCD Panel Used in Character Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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Preface
About This Guide
®
This user guide describes the Virtex -5 FPGA ML561 Memory Interfaces Development
Board. Complete and up-to-date documentation of the Virtex-5 family of FPGAs is
Guide Contents
This manual contains the following chapters:
•
•
•
•
•
•
•
•
•
•
Additional Documentation
The following documents are also available for download at
•
Virtex-5 Family Overview
The features and product selection of the Virtex-5 family are outlined in this overview.
•
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 family.
•
Virtex-5 FPGA User Guide
Chapters in this guide cover the following topics:
-
-
-
-
Clocking Resources
Clock Management Technology (CMT)
Phase-Locked Loops (PLLs)
Block RAM
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Preface: About This Guide
-
-
-
-
Configurable Logic Blocks (CLBs)
SelectIO™ Resources
SelectIO Logic Resources
Advanced SelectIO Logic Resources
•
•
•
•
•
•
•
Virtex-5 FPGA RocketIO GTP Transceiver User Guide
This guide describes the RocketIO™ GTP transceivers available in the Virtex-5 LXT
and SXT platforms.
Virtex-5 FPGA RocketIO GTX Transceiver User Guide
This guide describes the RocketIO GTX transceivers available in the Virtex-5 FXT
platform.
®
Virtex-5 FPGA Embedded Processor Block for PowerPC 440 Designs
This reference guide is a description of the embedded processor block available in the
Virtex-5 FXT platform.
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in the Virtex-5 LXT, SXT, and FXT platforms.
Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs
This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, and FXT
®
platforms used for PCI Express designs.
Virtex-5 FPGA XtremeDSP Design Considerations User Guide
This guide describes the XtremeDSP™ slice and includes reference designs for using
the DSP48E.
Virtex-5 FPGA Configuration Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
•
•
Virtex-5 FPGA System Monitor User Guide
The System Monitor functionality available in all the Virtex-5 devices is outlined in
this guide.
Virtex-5 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
•
Virtex-5 FPGA PCB Designer’s Guide
This guide provides information on PCB design for Virtex-5 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
Additional Support Resources
To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
8
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Conventions
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
This document uses the following typographical conventions. An example illustrates each
convention.
Convention
Meaning or Use
Example
See the Virtex-5 Configuration Guide
for more information.
References to other documents
Italic font
The address (F) is asserted after
clock event 2.
Emphasis in text
Underlined Text
Indicates a link to a web page.
Online Document
The following conventions are used in this document:
Convention
Meaning or Use
Example
See the section “Additional
Documentation” for details.
Cross-reference link to a location
in the current document
Blue text
Refer to “Clock Management
Technology (CMT)” in
Chapter 2 for details.
Cross-reference link to a location See Figure 5 in the Virtex-5 FPGA
Red text
in another document
Data Sheet
Go to http://www.xilinx.com
for the latest documentation.
Blue, underlined text
Hyperlink to a website (URL)
Terminology
This section defines terms used in Chapter 7, “ML561 Hardware-Simulation Correlation,”
of this document.
DVW is the data valid window opening measured by the VIH and VIL masks. The
Data Valid Window (DVW)
smaller of the two values are listed as absolute time as well as in terms of the percentage
of UI (Unit Interval), or bit time.
The ultimate goal of a design is to ascertain quality of signal at the receiver I/O Buffer
(IOB). This measurement can only be simulated. When the hardware measurements are
correlated with the simulation at the probe point, the extra probe capacitance is
removed from the IBIS schematics, and the simulation is repeated at two extreme
corners (slow-weak and fast-strong). Removal of probe capacitance is important to
represent the actual hardware. If the SI characteristics of these simulations are proved
to be within the acceptable range with sufficient margin, then the performance
requirements for data signal interface of the corresponding memory operation at the
target clock frequency are proved to have been met.
Extrapolation
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Preface: About This Guide
These measurements are the actual real-time measurements of an eye diagram and a
segment of the test pattern (PRBS6) waveform captured on ML561 hardware at the
designated probe point using an Agilent scope.
Hardware Measurements
As the frequency of operation increases, the signal delay is affected by the data pattern
that precedes the current data bit. This is called the inter-symbol interference (ISI) effect.
All testing is performed with a pseudo-random bitstream (PRBS) of order 6, that is,
PRBS6. ISI is the jitter represented by the eye at all four voltage thresholds. The worst
of the following two sum values are listed in this table:
Inter-Symbol Interference
(ISI)
• Sum of ISI at VIH(ac)-min and VIH(dc)-min
• Sum of ISI at VIL(ac)-max and VIL(dc)-max
This is the noise margin available at the receiver. Measurements are taken at the AC
voltage levels as the minimum vertical opening of the eye in the vicinity of the center
of the bit period. Ideally, the input voltage needs to remain above the DC voltage
specifications. However, by considering the AC voltage specifications for the nominal
voltage level for VREF, these measurements are more conservative values that also
include the effects of VREF variations.
Noise Margin
• VIH margin: Difference between the top of the eye opening and VIH(ac)-min
• VIL margin: Difference between VIL(ac)-max and the bottom of the eye opening
These measurements are performed in stand-alone fashion for the signal under test.
Thus no consideration of crosstalk or Simultaneously Switching Output (SSO) effects
are accounted for.
Overshoot margin is the difference between the maximum allowable VIH per JEDEC
specification and the maximum amplitude of the measured eye. Similarly, undershoot
margin is the difference between the minimum amplitude of the measured eye and the
minimum allowable VIL value per JEDEC specification. For both SSTL18 and 1.8V
HSTL specifications:
Overshoot / Undershoot
Margin
• VIH(max) < (VDDQ + 300 mV) = (1.8 + 0.3)V = 2.1V
• VIL(min) > -300 mV = 0.3V
The BoardSim utility of the HyperLynx simulator is used to extract the IBIS schematics
of the same signal net for which hardware measurements are made. To replicate the
hardware measurement probe set up at the probe point, a 0.5 pF probe capacitance is
added based on Agilent probe loading specifications to the extracted IBIS schematics of
the memory signal. For the FPGA devices soldered on the ML561 board under test, the
process corner (slow, typical, or fast) is not known. Thus simulation is performed for all
three corners (slow-weak, typical, and fast-strong), and the results of the case that best
fits with hardware measurement is selected for tabulation.
Simulation Correlation
This term is the minimum input level at which the receiver must recognize input logic
High.
VIH(ac)-min
VIH(dc)-min
VIL(ac)-max
VIL(dc)-max
When the input signal reaches VIH(ac)-min, the receiver continues to interpret the
input as a logic High as long as the signal remains above this voltage. (This parameter
is basically the hysteresis for a logic ‘1’.)
This term is the maximum input level at which the receiver must recognize input logic
Low.
When the input signal reaches VIL(ac)-max, the receiver continues to interpret the input
as a logic Low as long as the signal remains below this voltage. (This parameter is
basically the hysteresis for logic ‘0’.)
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Chapter 1
Introduction
®
This chapter introduces the Virtex -5 FPGA ML561 reference design. It contains the
following sections:
•
•
About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit
The Virtex-5 FPGA ML561 Memory Interfaces Tool Kit provides a complete development
platform to interface with external memory devices for designing and verifying
applications based on the Virtex-5 LXT FPGA platform. This kit allows designers to
implement high-speed applications with extreme flexibility using IP cores and customized
modules. The Virtex-5 LXT FPGA, with its column-based architecture, makes it possible to
develop highly flexible memory interface applications.
The Virtex-5 FPGA ML561 Memory Interfaces Tool Kit includes the following:
•
Virtex-5 FPGA ML561 Memory Interfaces Development Board (XC5VLX50T-FFG1136
FPGA)
•
•
•
•
5V/6.5 A DC power supply
Country-specific power supply line cord
RS-232 serial cable, DB9-F to DB9-F
Documentation and reference design CD-ROM
Optional items that also support development efforts include:
®
®
•
•
•
Xilinx ISE software
JTAG cable
Xilinx Parallel IV cable
For assistance with any of these items, contact your local Xilinx distributor or visit the
The heart of the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit is the Virtex-5 FPGA
ML561 Development Board. This manual provides comprehensive information on Rev A3
and later revisions of this board.
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Chapter 1: Introduction
Virtex-5 FPGA ML561 Memory Interfaces Development Board
A high-level functional block diagram of the Virtex-5 FPGA ML561 Memory Interfaces
External Interfaces:
System ACE Controller,
USB, RS-232, LCD
SSTL18/SSTL2
FPGA #1
XC5VLX50T/
FFG1136
SSTL18
HSTL
FPGA #3
XC5VLX50T/
FFG1136
FPGA #2
XC5VLX50T/
FFG1136
WIDE
UG191_c1_01_020807
DEEP
Figure 1-1: Virtex-5 FPGA ML561 Development Board Block Diagram
The Virtex-5 FPGA ML561 Development Board includes the following major functional
blocks:
•
•
DDR SDRAM Controller Using Virtex-5 FPGA Devices.
•
DDR2 DIMM: Five PC2-5300 DIMM sockets for up to 2 GB (128M x 144 bits). See
•
•
DDR2-667 components: 64 MB (16M x 32 bits) at 333 MHz clock speed
QDR II SRAM Interface for Virtex-5 Devices.
•
RLDRAM II memory: 64 MB (16M x 36 bits) at up to 300 MHz clock speed. See
•
•
One DB9-M RS-232 port and one USB 2.0 port
A System ACE™ CompactFlash (CF) Configuration Controller that allows storing
and downloading of up to eight FPGA configuration image files
•
On-board power regulators with 5% output margin test capabilities
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Virtex-5 FPGA ML561 Memory Interfaces Development Board
Figure 1-2 shows the Virtex-5 FPGA ML561 Development Board and indicates the
locations of the resident memory devices.
32-bit
DDR400
SDRAM
144 bits wide
DDR2
SDRAM
DIMM
32-bit
DDR2
SDRAM
72 bits wide,
up to 4 deep
72-bit
QDRII
SRAM
36-bit
RLDRAM II
UG199_c1_02_050106
Figure 1-2: Virtex-5 FPGA ML561 Development Board
Virtex-5 FPGA ML561 User Guide
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Chapter 1: Introduction
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Chapter 2
Getting Started
This chapter describes the items needed to configure the Virtex-5 FPGA ML561 Memory
Interfaces Development Board. The Virtex-5 FPGA ML561 Development Board is tested at
the factory after assembly and should be received in working condition. It is set up to load
a bitstream from the CompactFlash card at socket J27 through the System ACE controller
(U45).
This chapter contains the following sections:
•
•
•
Documentation and Reference Design CD
The CD included in the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit contains the
design files for the Virtex-5 FPGA ML561 Development Board, including schematics,
board layout, and reference design files. Open the ReadMe.rtffile on the CD to review
the list of contents.
Initial Board Check Before Applying Power
Perform these steps before applying board power:
1. Set up the Configuration Mode jumpers (P27, P46, and P112) for JTAG configuration.
ML561 Development Board.
2. Confirm that the JTAG chain jumpers P38, P44, and P109 are connecting pins 1 to 2 and
pins 3 to 4. This way, all three devices are in the chain. Otherwise, the ISE iMPACT
software will not find all three devices to configure. For more information see “JTAG
3. Make sure that no inhibit jumpers are present on any of the power supply regulator
4. The Virtex-5 FPGA ML561 Development Board has a 200 MHz on-board oscillator,
which provides a copy of a differential LVPECL clock to each of the three FPGAs
through a differential clock buffer (ICS853006). There is also a connection to a pair of
SMA connectors (J19, J20) to provide a differential LVDS clock from an off-board signal
generator. Another differential clock buffer (ICS853006) provides a copy of this clock to
each of the three FPGAs. These clocks are available after configuration for the design to
use for various system clocks.
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Chapter 2: Getting Started
5. Insert the CompactFlash card included in the kit into socket J27 on the Virtex-5 FPGA
ML561 Development Board. To select the startup file, check that SW8 is set to position
0.
Applying Power to the Board
The Virtex-5 FPGA ML561 Development Board is now ready to power on. The Virtex-5
FPGA ML561 Development Board is shipped with a country-specific AC line cord for the
universal input 5V desktop power supply. Follow these steps to power up the Virtex-5
FPGA ML561 Development Board:
1. Confirm that the ON-OFF switch, SW5, is in the OFF position.
2. Plug the 5V desktop power supply into the 5V DC input barrel jack J28 on the Virtex-5
FPGA ML561 Development Board. Plug the desktop power supply AC line cord into
an electrical outlet supplying the appropriate voltage.
3. Turn SW5 to the ON position. The power indicators for all regulator modules should
come on, indicating output from the regulators. The System ACE status LED D37
comes on when the System ACE controller (U45) extracts the BIT configuration file
from the CompactFlash card to the FPGA. If no CompactFlash card is installed in the
card socket J27 on the Virtex-5 FPGA ML561 Development Board, the red System ACE
error LED D38 flashes.
4. If a CompactFlash card is not installed in socket J27, a JTAG cable must be used to
configure the FPGAs. To use a Parallel IV cable or other JTAG pod, download the
FPGA configuration bitstream into each FPGA. After the DONE LED (D28) comes on,
the FPGAs are configured and ready to use.
5. Push the reset button SW4.
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Chapter 3
Hardware Description
This chapter describes the major hardware blocks on the Virtex-5 FPGA ML561
Development Board and provides useful design consideration. It contains the following
sections:
•
•
•
•
•
Hardware Overview
The ML561 Development/Evaluation system reference design is implemented with three
XC5VLX50T-FFG1136 devices from the Virtex-5 FPGA family to demonstrate high-speed
external memory application interfaces. The memory technologies supported by the
Virtex-5 FPGA ML561 Development Board are DDR2 SDRAM, DDR400 SDRAM, QDRII
SRAM, and RLDRAM II SDRAM.
Figure 3-1 provides a view of all the major components on ML561 board. It shows the
placement of the three Virtex-5 FPGAs, and the position of the associated major interfaces
for each FPGA.
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Chapter 3: Hardware Description
SSTL18
MGT Connections
FPGA #1
LEDs
SSTL2
& V
SPY
A1
V
TT
REF
DDR
FPGA #2
FPGA #1
DDR
SPY
FPGA #1
LEDs
Test Header 1
A1
FPGA #2
Test Header 2
SSTL18
LEDs
MGT
CLK
DDR2
DDR2
AVC
CPLL
Config1
V
& V
TT
REF
Config2
VVTTR
XC
AVTTX
AVTRX
DIP1
FBD
VCC
12V Banana
Jacks
Clocks &
Buffers
7SEG2
DIP2
External
CLK
ON
V
CCINT
SSTL2
RS-232
Driver
A1
OFF
7SEG1
SPY
HSTL
12V -> 5V
3.3V
Serial Header
QDRII
QDRII
V
/
12V Input
Jack
CCAUX
CCO
RLDRAM II
V
RESET
FPGA #3
HSTL
5V Banana
Jacks
RLDRAM II
SPY
V
& V
TT
REF
System ACE
Test Header 3
ON
Controller
JTAG Test Header
Config3
FPGA #3 LEDs
OFF
5V Input
Jack
7SEG3
DIP3
HSTL
Pwr Measure Header
USB
LCD Connector
PROG
JTAG
UG199_c3_01_050106
Figure 3-1: ML561 XC5VLX50T-FFG1136 Board Placement Diagram
FPGA
The ML561 uses three Virtex-5 XC5VLX50T-FFG1136 devices, each in a 1136-pin,
components on the Virtex-5 FPGA ML561 Development Board, including their reference
designators and links to their corresponding data sheets.
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Hardware Overview
Memories
Table 3-1 lists the types of memories that the ML561 board supports.
Table 3-1: Summary of ML561 Memory Interfaces
Data/Strobe
Ratios
Memory Type
Maximum Speed
Data Rate
Data Width
I/O Standard
DDR400 SDRAM
DDR2 DIMM
DDR2 SDRAM
QDRII SRAM
RLDRAM II
200 MHz
333 MHz
333 MHz
300 MHz
300 MHz
400 Mbps
667 Mbps
667 Mbps
1.2 Gbps
600 Mbps
32
144
32
SSTL2
SSTL18
SSTL18
HSTL18
HSTL18
8:1
8:1
8:1
72
18:1, 36:1
9:1, 18:1
36
When a larger data/strobe ratio is implemented, for example, a x36 QDRII device, the
smaller configurations can also be demonstrated by programming the FPGA for a smaller
data width, such as a 9:1 data/strobe ratio for the QDRII device.
DDR400 SDRAM Components
The Virtex-5 FPGA ML561 Development Board has two 200 MHz Micron
MT46V32M16BN-5B (16-bit) DDR400 SDRAM components that provide a 32-bit interface.
Each 16-bit device is packaged in a 60-ball FBGA package, with a common address and
control bus and separate clocks and DQS/DQ signals.
DDR2 DIMM
The Virtex-5 FPGA ML561 Development Board contains five PC-5300 240-pin DIMM
sockets for a maximum data width of 144 bits or a maximum depth of four DIMMs. The
sockets are arranged in a row leading away from the FPGA so they can share common
address and control signals. DIMM1 through DIMM4 share DQ/DQS signals to form a
deep 72-bit memory interface, while DIMM5 has separate DQ/DQS signals.
For the deep DDR2 interface, the sockets are to be populated starting at socket DIMM4.
Table 3-2 illustrates how the sockets should be populated based on the interface wanted.
Table 3-2: Populating DDR2 DIMM Sockets
DIMM Sockets
Populated
DIMM Interface
Interface Width
One Deep
Two Deep
Three Deep
Four Deep
Two Wide
5 or 4
72-bit
72-bit
72-bit
72-bit
144-bit
4 and 3
4, 3, and 2
4, 3, 2, and 1
5 and 4
Populating the DIMMs in this order is necessary due to the placement of the termination
on the signals being shared. More detail on termination is given in “Board Design
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Chapter 3: Hardware Description
Wide
Deep
DQ and DQS
BY0-BY7, CB0_7
DQ and DQS
BY8-BY15, CB8_15
Address and Commands
DIMM1 Control
DIMM2 Control
DIMM3 Control
DIMM4 Control
DIMM5 Control
UG199_c3_02_050106
Figure 3-2: DDR2 Deep and Wide DIMM Sockets
DDR2 SDRAM Components
The ML561 board contains two 333 MHz Micron MT47H32M16CC-3 (16-bit) DDR2
SDRAM components that provide a 32-bit interface to FPGA #1. Each 16-bit device is
packaged in an 84-ball FBGA package, with a common address and control bus and
separate clocks and DQS/DQ signals.
QDRII SRAM
The ML561 board contains a 300 MHz QDRII SRAM interface with a 72-bit Read interface
and a 72-bit Write interface using two Samsung K7R643684M-FC30 components (x36).
They are packaged in a 165-ball FBGA package with a body size of 15 x 17 mm. These two
components share the same address/control signals but have separate clock and data
signals.
RLDRAM II Devices
The ML561 contains a 300 MHz 36-bit RLDRAM II interface using two Micron
MT49H16M18BM-25 devices (x18) packaged in a 144-ball PBGA package. They share a
common address and control bus but have separate clocks and DQS/DQ signals.
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Memory Details
Memory Details
DDR400 and DDR2 Component Memories
The FPGA #1 device on the Virtex-5 FPGA ML561 Development Board is connected to
Figure 3-3 summarizes the distribution of DDR and DDR2 discrete component interface
signals among the different banks of the FPGA #1 device.
GTP I/O
BANK 25 (40)
BANK 6 (20)
BANK 126
BANK 21 (40)
BANK 17 (40)
BANK 4 (20)
BANK 22 (40)
BANK 122
Global Clock Inputs
BANK 2 (20)
BANK 18 (40)
BANK 118
Voltage Control
BANK 13 (40)
DDR Components
DQ 0, 1, 2
BANK 114
BANK 112
(Configuration)
BANK 0
BANK 11 (40)
DDR Components
DQ 3 & Controls
BANK 12 (40)
USB Controls
BANK 15 (40)
BANK 1 (20)
BANK 116
BANK 120
DDR2 Component
DDR2 Component
DQ 0, 1
Address
BANK 19 (40)
BANK 3 (20)
BANK 20 (40)
RS232
DDR2 Component
DQ 2, 3
DDR2 Component
Controls
Inter-FPGA MII Links
BANK 23 (40)
BANK 5 (20)
BANK 124
UG199_c3_03_050106
Figure 3-3: FPGA #1 Banks for DDR400 and DDR2 Component (Top View)
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Chapter 3: Hardware Description
Table 3-3 describes all signals associated with DDR400 Component memories.
Table 3-3: DDR400 Component Signal Summary
Board Signal Name(s)
DDR1_A[13:0]
Bits
14
4
Description
DDR400 Component Address
DDR400 Component Differential Clock
DDR400 Component Control Signals
DDR1_CK[2:1]_[P,N]
DDR1_[RAS,CAS,WE]_N, DDR1_CKE,
DDR1_BA[1:0], DDR1_BY[0_1,2_3]_CS_N,
DDR1_DM_BY[3:0]
12
DDR1_DQ_BY0_B[7:0], DDR1_DQS_BY0_P
DDR1_DQ_BY1_B[7:0], DDR1_DQS_BY1_P
DDR1_DQ_BY2_B[7:0], DDR1_DQS_BY2_P
DDR1_DQ_BY3_B[7:0], DDR1_DQS_BY3_P
9
9
9
9
DDR400 Data and Strobe: Byte 0
DDR400 Data and Strobe: Byte 1
DDR400 Data and Strobe: Byte 2
DDR400 Data and Strobe: Byte 3
Notes:
1. DDR1_CKE signal has a weak 4.7KΩpull-down resistor to meet the memory power-up requirements.
Table 3-4 describes all signals associated with DDR2 Component memories. For a complete
list of FPGA #1 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”
Table 3-4: DDR2 Component Signal Summary
Board Signal Name(s)
DDR2_A[12:0]
Bits
13
Description
DDR2 Component Address
DDR2_CK[1:0]_[P,N]
4
DDR2 Component Differential
Clock
DDR2_ODT[1:0], DDR2_[RAS,CAS,WE]_N,
DDR2_CKE, DDR2_BA[1:0], DDR2_CS[1:0]_N,
DDR2_DM_BY[3:0]
14
DDR2 Component Control Signals
DDR2_DQ_BY0_B[7:0], DDR2_DQS_BY0_[P,N]
DDR2_DQ_BY1_B[7:0], DDR2_DQS_BY1_[P,N]
DDR2_DQ_BY2_B[7:0], DDR2_DQS_BY2_[P,N]
DDR2_DQ_BY3_B[7:0], DDR2_DQS_BY3_[P,N]
10
10
10
10
DDR2 Data and Strobe: Byte 0
DDR2 Data and Strobe: Byte 1
DDR2 Data and Strobe: Byte 2
DDR2 Data and Strobe: Byte 3
Notes:
1. DDR2_CKE and DDR2_ODT[1:0] signals have a weak 4.7KΩpull-down resistor to meet the memory
power-up requirements.
Performance DDR2 SDRAM Interface in Virtex-5 Devices, and the corresponding demos are
included on the CD shipped with the ML561 Tool Kit. For a complete list of FPGA #1
signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”
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Memory Details
DDR2 SDRAM DIMM
The FPGA #2 device on the Virtex-5 FPGA ML561 Development Board is connected to
DDR2 memories. The DDR2 memory interface includes a 144-bit wide DIMM connection
to up to five 240-pin DDR2 DIMM sockets.
For the 144-bit wide DIMM datapath, the data bytes are spread across multiple banks of
signals among the different banks of the FPGA #2 device.
BANK 124
TX 0, 1
BANK 5 (20)
BANK 23 (40)
BANK 120
BANK 20 (40)
DDR2 DIMM
DQ 8, 9, 10
BANK 3 (20)
BANK 19 (40)
DDR2 DIMM
General I/O
RX 0, 1
Controls & DIMM1 Cntl
BANK 116
BANK 1 (20)
BANK 15 (40)
General I/O
DDR2 DIMM
DQ 0, 1, 2
GTP CLK
BANK 112
BANK 12 (40)
DDR2 DIMM
BANK 11 (40)
DDR2 DIMM
(Configuration)
DQ 11, 12, CB8_15
DQ 6, 3 CB0_7
BANK 114
BANK 0
BANK 13 (40)
DDR2 DIMM
DQ 5, 7, 4
BANK 118
BANK 18 (40)
BANK 2 (20)
BANK 17 (40)
DDR2 DIMM
DDR2 DIMM
Inter-FPGA MII Links
DQ 14, 15, 13
BANK 22 (40)
Common Controls
BANK 122
BANK 126
BANK 4 (20)
BANK 21 (40)
DDR2 DIMM
Global Clock Inputs
DDR2 DIMM
DIMM 4 & 5 Cntl
DIMM 1, 2, 3 Cntl
BANK 6 (20)
BANK 25 (40)
UG199_c3_04_050106
Figure 3-4: FPGA #2 Banks for DDR2 DIMM (SSTL18) Interfaces (Top View)
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Chapter 3: Hardware Description
Table 3-5 describes all the signals associated with DDR2 DIMM component memories. For
the Deep DIMM interface to four DIMMs, the individual dedicated control signals are
Table 3-5: DDR2 DIMM Signal Summary
Board Signal Name(s)
DDR2_DIMM_A[15:0]
Bits
Description
16 DDR2 DIMM Address
DDR2_DIMM[5:1]_CK[2:0]_[P,N]
30 DDR2 DIMM Differential Clocks: Three copies per
DIMM
DDR2_DIMM_[RAS,CAS,WE,RESET]_N,
DDR2_DIMM[5:1]_CKE[1:0], DDR2_DIMM_BA[2:0],
DDR2_DIMM[5:1]_CS[1:0]_N,
37 DDR2 DIMM Common Control Signals
20 DDR2 DIMM Dedicated Control Signals
DDR2_DIMM[5:1]_ODT[1:0]
DDR2_DIMM[1:5]_CS[1:0]_N,
DDR2_DIMM[1:5]_CKE[1:0],
DDR2_DIMM[1:5]_ODT[1:0]
DDR2_DIMM_LB_BK[11,13,15]_[IN,OUT]
6
3
Deep DIMMs (DIMM1 through DIMM4) Loopback
Signals
DDR2_DIMM_LB_BK[12,18,20]
Wide DIMM (DIMM5) Loopback Signals (Total of six
FPGA pins)
DDR2_DIMM[1:5]_CNTL_PAR,
DDR2_DIMM[1:5]_CNTL_PAR_ERR,
20 Miscellaneous Place Holder Signals to the Five
DIMMs
DDR2_DIMM[1:5]_NC_019, DDR2_DIMM[1:5]_NC_102
DDR2_DIMM_DQ_BY[0:15]_B[7:0],
DDR2_DIMM_DQS_BY[0:15]_L_[P,N],
DDR2_DIMM_DM_BY[0:15]
176 DDR2 DIMM Data, Strobes, and Data Mask: Bytes 0
through 15
DDR2_DIMM_DQ_CB0_7_B[7:0],
DDR2_DIMM_DQS_CB0_7_L_[P,N],
DDR2_DIMM_DM_CB0_7
11 DDR2 DIMM Data, Strobes, and Data Mask: Check
Byte 0
DDR2_DIMM_DQ_CB8_15_B[7:0],
DDR2_DIMM_DQS_CB8_15_L_[P,N],
DDR2_DIMM_DM_CB8_15
11 DDR2 DIMM Data, Strobes, and Data Mask: Check
Byte 1
DDR2_DIMM[1:5]_SA[2:0]
DDR2_DIMM_[SCL,SDA]"
15 Serial PROM Address
2
Serial PROM interface CLK and Data
Notes:
1. DDR2_DIMM_CKE and DDR2_DIMM_ODT signals are connected to a 4.7KΩpull-down resistor to meet the memory power-up
requirements.
corresponding demo are included on the CD shipped with the ML561 Tool Kit.
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Memory Details
QDRII and RLDRAM II Memories
Figure 3-5 summarizes the distribution of QDRII and RLDRAM II component interface
signals among the different banks of the FPGA #3 device.
BANK 124
BANK 5 (20)
BANK 23 (40)
BANK 120
BANK 116
BANK 20 (40)
RLDII Data
BANK 3 (20)
BANK 19 (40)
QDRII Data
Q1, 3 & D1
General I/O
DQ 0, 1 & D0
BANK 1 (20)
BANK 15 (40)
QDRII Data
D7, 2, 3, 0
System ACE Controls
BANK 112
BANK 114
BANK 12 (40)
RLDII Data
BANK 11 (40)
QDRII Data
Q0, 2 & D6
(Configuration)
DQ 2, 3 & D1
BANK 0
BANK 13 (40)
QDRII Data
Q4, 5, 6
BANK 118
BANK 18 (40)
RLDII Data
BANK 2 (20)
BANK 17 (40)
QDRII Data
Inter-FPGA MII Links
D 2, 3
Q7 & D4, 5
BANK 122
BANK 22 (40)
BANK 4 (20)
BANK 21 (40)
RLDII Address
and Control
QDRII Address
and Control
Global Clock Inputs
BANK 126
BANK 6 (20)
BANK 25 (40)
UG199_c3_05_050106
Figure 3-5: FPGA #3 Banks for QDRII SRAM and RLDRAM II Interfaces (Top View)
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Chapter 3: Hardware Description
Table 3-6 describes all the signals associated with QDRII component memories.
Table 3-6: QDRII Component Signal Summary
Board Signal Name(s)
Bits
19
Description
QDR2_SA[18:0]
QDRII Address
QDR2_CK_BY0_3_[P,N],
QDR2_CK_BY4_7_[P,N]
4
QDRII Differential Clock
QDR2_[R,W,DLL_OFF]_N
3
QDRII Control Signals
QDR2_D_BY[3:0]_B[8:0],
QDR2_K_BY0_3_[P,N],
QDR2_BW_BY[3:0]
42
QDRII Write Data, Strobes, and Byte Write: Bytes 3:0
QDR2_Q_BY[3:0]_B[8:0],
QDR2_CQ_BY0_3_[P,N]
38
42
QDRII Read Data and Strobes: Bytes 3:0
QDR2_D_BY[7:4]_B[8:0],
QDR2_K_BY4_7_[P,N],
QDR2_BW_BY[3:0]
QDRII Write Data, Strobes, and Byte Write: Bytes 7:4
QDR2_Q_BY[7:4]_B[8:0],
QDR2_CQ_BY4_7_[P,N]
38
QDRII Read Data and Strobes: Bytes 7:4
Notes:
1. QDR2_SA[18] is incorrectly labeled QDR2_NC_A3 in the ML561 schematics and layout file.
included on the CD shipped with the ML561 Tool Kit.
For a complete list of FPGA #3 signals and their pin locations, refer to Appendix A, “FPGA
Table 3-7 describes all signals associated with RLDRAM II devices.
Table 3-7: RLDRAM II Component Signal Summary
Board Signal Name(s)
Bits
23
2
Description
RLDRAM II Address
RLD2_A[19:0], RLD2_BA[2:0]
RLD2_CK_BY0_1 _[P,N]
RLD2_CK_BY2_3 _[P,N]
RLDRAM II Differential Clock
RLDRAM II Differential Clock
RLDRAM II Control Signals
2
RLD2_CS_BY[0_1,2_3]_N, RLD2_[REF,WE]_N,
8
RLD2_DM_BY[0_1,2_3]_N, RLD2_QVLD_BY[0_1,2_3]
RLD2_DQ_BY[1:0]_B[8:0], RLD2_DK_BY0_1_[P,N],
RLD2_QK_BY[1:0]_[P,N]
24
24
RLDRAM II Data and Strobes: Bytes 1:0
RLDRAM II Data and Strobes: Bytes 3:2
RLD2_DQ_BY[3:2]_B[8:0], RLD2_DK_BY0_1_[P,N],
RLD2_QK_BY[3:2]_[P,N]
included on the CD shipped with the ML561 Tool Kit.
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External Interfaces
External Interfaces
The external interfaces of the Virtex-5 FPGA ML561 Development Board are described in
this section.
RS-232
The ML561 board provides an RS-232 serial interface using a Maxim MAX3316ECUP
device. The maximum speed of this device is 460 Kbps.
Hooks are provided to connect and disconnect FPGAs to the RS-232 serial interface, by
placing jumpers on headers based on the FPGA involved in the communication. Only one
FPGA is allowed in the communication, and others must be disconnected before operation.
The ML561 toolkit CD contains code to implement a UART core in one FPGA for
interfacing with a host PC.
The RS-232 interface is accessible through a male DB-9 serial connector (P73).
Table 3-8: RS-232 Jumper Settings
To Connect FPGA # to
TX
RX
DB-9 (P73)
FPGA #1
FPGA #2
FPGA #3
P52 Pin 2 -> P52 Pin 1
P52 Pin 2 -> P51 Pin 1
P52 Pin 2 -> P52 Pin 3
P53 Pin 2 -> P53 Pin 1
P53 Pin 2 -> P54 Pin 1
P53 Pin 2 -> P53 Pin 3
USB
Full-speed (12 Mbps) USB functionality is proved using a Silicon Laboratories CP2102-GM
USB to RS-232 Bridge. RS-232 and USB signals are converted between one another so a
RS-232 core needs to be implemented in the FPGA for communication. A level translator is
used to convert between the 2.5V I/O of the FPGA and the 3.3V I/O the CP2102 uses.
Hooks are provided to connect and disconnect FPGAs to the USB connection, by placing
jumpers on headers based on the FPGA involved in the communication. Only one FPGA is
allowed in the communication, and others must be disconnected before operation.
The USB interface is accessible through a female ‘A’ USB connector (J29).
Table 3-9: USB Jumper Settings
To Connect FPGA # to DB-9
TX
RX
(J29)
FPGA #1
FPGA #2
FPGA #3
P36 Pin 2 -> P36 Pin 1
P36 Pin 2 -> P35 Pin 1
P36 Pin 2 -> P36 Pin 3
P22 Pin2 -> P22 Pin 1
P22 Pin2 -> P23 Pin 1
P22 Pin2 -> P22 Pin 3
Clocks
The ML561 board contains a 200 MHz LVPECL clock oscillator and connectors for external
clock inputs for use as system clocks (J19 and J20). The GTP transceivers use their own
clock source that can be provided through SMA connectors on the board (J16 and J21).
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Chapter 3: Hardware Description
200 MHz LVPECL Clock
The 200 MHz LVPECL clock source is an Epson EG-2121CA200M-PCHS oscillator (Y1)
with a differential output. The oscillator runs at 200 MHz 100 PPM with an operating
voltage of 2.5V 5%. This output is fed into an ICS853006 LVPECL buffer for generating a
separate differential copy for each FPGA as well as a test point (P59).
Table 3-10: FPGA 200 MHz IDELAY Reference Clock Source
FPGA #
Signal Name
1
1
2
2
3
3
DIRECT_CLK_TO_FPGA1_P
DIRECT_CLK_TO_FPGA1_N
DIRECT_CLK_TO_FPGA2_P
DIRECT_CLK_TO_FPGA2_N
DIRECT_CLK_TO_FPGA3_P
DIRECT_CLK_TO_FPGA3_N
SMA Clock
Two SMA connectors are provided for the input of an off-board differential clock (J19 and
J20). A differential clock buffer (ICS853006) is used on the board (U17 and U18) to generate
four LVPECL copies of the differential clock signal, one for each FPGA along with a probe
point (P40) for testing. The traces from the buffer are routed as a differential pair to each
FPGA where they are terminated with 100Ωdifferential termination.
Table 3-11: FPGA External Clock Sources
FPGA #
Signal Name
1
1
2
2
3
3
EXT_CLK_TO_FPGA1_P
EXT_CLK_TO_FPGA1_N
EXT_CLK_TO_FPGA2_P
EXT_CLK_TO_FPGA2_N
EXT_CLK_TO_FPGA3_P
EXT_CLK_TO_FPGA3_N
33 MHz Clock
A single-ended 33 MHz Epson SG-8002CA oscillator is provided on the board (Y2) for
testing purposes. Four copies of this clock are generated using a clock buffer (ICS8304) on
the board, one per FPGA along with a probe point for testing (P41).
The application using this clock source as an input to the PLL on the Virtex-5 device has
not yet been fully verified.
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External Interfaces
Table 3-12: FPGA Slow Clock Sources
FPGA
Signal Name
1
2
3
FPGA1_LOW_FREQ_CLK
FPGA2_LOW_FREQ_CLK
FPGA3_LOW_FREQ_CLK
33 MHz System ACE Controller Oscillator
A single-ended 33 MHz Epson SG-8002CA oscillator is provided on the board (Y3) as a
clock source for System ACE functionality.
GTP Clocks
Two SMA connectors are provided for the input of an off-board differential clock (J16 and
J21). A differential clock buffer (ICS8543BG) is used on the board (U20) to generate four
LVDS copies of the differential clock signal, two for FPGA #1, one for FPGA #2, and one for
FPGA #3.
A header is used to select between a clock forwarded by the GTP or from the external clock
source used to provide a clock to the FPGA logic.
User I/Os
This subsection describes the devices that connect to the User I/Os of the ML561 board.
These I/Os are provided to ease hardware development using the ML561.
General-Purpose Headers
The 16-pin test headers are surface mounted, one per FPGA. Of the two bytes of test
signals, traces are matched for signals within a byte.
Table 3-13: Test Headers
Header Signal Description
Location
Header Pin #
FPGA1_TEST_HDR_BY0_B[0:7]
FPGA1_TEST_HDR_BY1_B[0:7]
FPGA2_TEST_HDR_BY0_B[0:7]
FPGA2_TEST_HDR_BY1_B[0:7]
FPGA3_TEST_HDR_BY0_B[0:7]
FPGA3_TEST_HDR_BY1_B[0:7]
P20 (TEST1)
P20 (TEST1)
P21 (TEST2)
P21 (TEST2)
P93 (TEST3)
P93 (TEST3)
Odd pins: 1, 3, 5, 7, 9, 11, 13, 15
Even pins: 2, 4, 6, 8, 10, 12, 14, 16
Odd pins: 1, 3, 5, 7, 9, 11, 13, 15
Even pins: 2, 4, 6, 8, 10, 12, 14, 16
Odd pins: 1, 3, 5, 7, 9, 11, 13, 15
Even pins: 2, 4, 6, 8, 10, 12, 14, 16
DIP Switch
One four-position DIP switch per FPGA (for a total of three) is available to externally pull
up or pull down a signal on the FPGA. This can be used to manually set values used by the
design running on the FPGA.
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Chapter 3: Hardware Description
Seven-Segment Displays
One seven-segment display per FPGA (for a total of three) is available for use. The red
Stanley-Electric NAR131SB displays are active Low, using seven inputs to display a
character or number plus another input for a decimal point.
7SEG_0_N
7SEG_5_N
7SEG_4_N
7SEG_1_N
7SEG_2_N
7SEG_6_N
7SEG_3_N
7SEG_DP_N
UG199_c3_06_050106
Figure 3-6: Seven-Segment Display Signal Mapping
Light Emitting Diodes (LEDs)
Each FPGA is able to control four active-high green LEDs. The green is used to distinguish
the User LEDs from the blue system LEDs on the Virtex-5 FPGA ML561 Development
Board.
Pushbuttons
The ML561 board contains two momentary pushbuttons. Their functions and locations are
Table 3-14: User Pushbuttons
Button
Description
Pin Connection
SW7
SW4
PROG_B: Configure FPGA
System ACE Controller: Pin 33
RESET_N: Reset the FPGA designs FPGA #1: AH14
FPGA #2: AH14
FPGA #3: AH14
The Reset signal goes to a buffer (U32) that provides a separate copy of Reset to each
FPGA.
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External Interfaces
Power On or Off Slide Switch
The power on or off slide switch is a DPST slide switch used to apply input power to the
board. While the board contains two such switches, the 5V switch is primarily used to
supply 5V power to the board, whereas the 12V switch is available for testing only.
Soft Touch Probe Points
Soft Touch E5396A Probeless connection points are provided for monitoring FPGA #2 and
FPGA #3 test signals with a compatible Agilent logic analyzer. FPGA #2 uses separate test
signals for soft touch pins, while FPGA #3 shares the general-purpose test header signals
with soft touch pins due to lack of available I/O pins.
Power Measurement Header
The ML561 comes with a 3M Pak 100 power measurement header to enable easy
measurement of the power being consumed by the devices on the ML561. Each power
regulator uses an Isotek Kelvin current sense resistor (SMV-R010-0.5) in the path from the
output of the regulator to the power plane. The power can be computed by measuring the
voltage drop across each of these resistors.
R
= 10 mΩ
KELVIN
CCXXPR
MARGIN+ MARGIN-
+5V or +12V
V
V
CCX
V
To FPGA or
Other Device
V
V
OUT
IN
Voltage
Regulator
1KΩ
Mon
To
CCXX
V
Sense-
Monitor
Cable
CCXX
R
SET
V
Sense+
CCXX
UG199_c3_07_050106
Figure 3-7: Virtex-5 FPGA ML561 Development Board Power Measurement System
Table 3-15: Power Measurement Header Pins (P102)
Header Signal
Power Header Pin #
VCC1V0_SENSE+
VCC1V0_SENSE-
VCC1V0_MON
VCC2V5_SENSE+
VCC2V5_SENSE-
VCC2V5_MON
VCC3V3_SENSE+
VCC3V3_SENSE-
VCC3V3_MON
1
2
3
5
6
7
9
10
11
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Chapter 3: Hardware Description
Table 3-15: Power Measurement Header Pins (P102) (Continued)
Header Signal
Power Header Pin #
VCC1V8_SENSE+
VCC1V8_SENSE-
VCC1V8_MON
VCC1V5_SENSE+
VCC1V5_SENSE-
VCC1V5_MON
VCC2V6_SENSE+
VCC2V6_SENSE-
VCC2V6_MON
VCC5_SENSE+
VCC5_SENSE-
VCC5_MON
VCC5
13
14
15
17
18
19
21
22
23
25
26
24
20
4
GND
GND
8
GND
12
16
GND
Liquid Crystal Display Connector
Previous memory boards such as the ML461 had a DisplaytechQ 64128E-FC-BC-3LP
64x128 LCD panel. This display was removed from the ML561, but the connection is still
available for use with embedded systems if the user connects the display to connector
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Power Regulation
RS232
Driver
A1
OFF
7SEG1
SPY
HSTL
Serial Header
QDRII
QDRII
V
/
12V Input
Jack
CCAUX
CCO
RLDRAM II
V
RESET
FPGA3
12V -> 5V
HSTL
5V Banana
Jacks
RLDRAM II
SPY
V
& V
TT
REF
System ACE
Test Header 3
ON
Controller
JTAG Test Header
3.3V
Config3
FPGA3 LEDs
OFF
5V Input
Jack
7SEG3
DIP3
HSTL
Pwr Measure Header
LCD Connector
USB
PROG
JTAG
UG199_c3_08_050106
Figure 3-8: LCD Panel Connector for Possible LCD Support
The product specification at
Power Regulation
This section describes the devices that supply power to the Virtex-5 FPGA ML561
Development Board. For electrical requirements and power consumption, see Chapter 4,
Power Distribution
general overview of the power distribution system.
Board Power
To Devices
+5V
3.3V
Slide
Switch
MGT
Power
MGT Power
FPGA Power
12V -> 5V
+12V
To All FPGAs
V
or V
/V
CCINT
CCAUX CCO
Slide
Switch
FPGA Power
SSTL18, HSTL, or SSTL2
To FPGAs
To Memories
Memory Power
SSTL18, HSTL, or SSTL2
V
V
TT
TT
V
V
REF
REF
UG199_c3_09_050106
Figure 3-9: Virtex-5 FPGA ML561 Development Board Power Distribution System
The Virtex-5 FPGA ML561 Development Board is powered through the +5V input jack
(J28) from the power supply included in the ML561 Tool Kit. Alternatively, the +5V can
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Chapter 3: Hardware Description
also be supplied from a bench supply using the two banana jacks: J25 (RED) for +5V and
J24 (BLACK) for GND.
The Rev-A assembly of the Virtex-5 FPGA ML561 Development Board does not support
the +12V input via jack J23 or via banana jacks J18 (RED) for +12V and J17 (BLACK) for
GND.
The memory and FPGAs use separate power supplies for SSTL18, HSTL, and SSTL2,
respectively. Thus the power being consumed can be easily measured for each using the
power measurement header provided on the ML561.
Voltage Regulators
The +5V voltage source is supplied as input to nine on-board regulator modules. Six of
those modules (TI PTH05010-WAZ) are used to generate the +1.0V, +2.5V, and +1.8V for
SSTL18 at FPGA #1 and FPGA #2, +1.8V for HSTL18 at FPGA #3, +2.6V for SSTL2 at
FPGA #1, and +3.3V voltages for the GTP power supplies, LEDs, etc. The remaining three
modules (TI PTH05000-ADJ) are used to generate +1.8V for SSTL18 at the memories, +1.8V
for HSTL at the memories, and +2.6V for SSTL2 at the memories.
An additional three bulk voltage regulators (Fairchild FN6555) are used to generate
termination (V ) and reference (V ) voltages each for the SSTL2, SSTL18, and HSTL
TT
REF
power levels. By design, these voltage levels are half of the input reference voltage being
supplied by the memory power supplies.
The TI PTH05010-WAZ and TI PTH05000-ADJ regulator modules require a fixed 5V input.
The output is adjustable over a range of 0.9V to 3.6V by changing the resistor tied between
pin 4 and GND. The difference between these two modules is that the PTH05010-WAZ
output voltage can be margined up to+ 5% of the nominal value by driving pin 10 to GND
(or digital Low), or margined down to -5% of the nominal value by driving pin 9 Low. The
PTH05010-WAZ also has a tracking feature that can be used to track another voltage
source.
TRACK
VMARGIN_DN_xxxx_N
VMARGIN_UP_xxxx_N
10
9
8
1
2
MRGNUP MRGNDN TRACK
GND
VIN
GND
VOUT
7
6
PTH05010
Voltage Regulator
5V
VO_ADJ VO_SENSE
INHIBIT
3
4
5
COUT
+
+
CIN
470 μF
330 μF
(optional)
Inhibit
Jumper
RSET
UG199_c3_10_050106
Figure 3-10: PTH05010 Voltage Regulator
There are two ways to apply the digital controls to the margin input pins of the PTH05010:
either from FPGA #1 or manually with jumpers.
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Power Regulation
The FPGA can drive VMARGIN_DN_xxxx_N and VMARGIN_UP_xxxx_N signals, where
xxxx indicates one of the six main power regulators: SSTL2, HSTL, SSTL18, VCC1V0,
VCC2V5, and VCC3V3.
Table 3-16: Manual Voltage Margining
VMARGIN_UP_N
VMARGIN_DN_N
Output Voltage
High
High
Low
Low
High
Low
High
Low
Nominal
-5%
+5%
Not Applicable
If both voltage-margining inputs to the power regulator are pulled Low, the output voltage
is close to nominal but has the possibility of a slightly higher error in the output voltage.
The power modules use a low-leakage open-drain control signal to control the voltage
margining. In the FPGA, this can be approximated by using a control signal that drives the
output Low when active and does not drive the signal at all when inactive (high-
impedance output).
Three-pin headers are available for performing manual voltage margining, using jumpers
Table 3-17: FPGA #1 Signals and On-Board Jumpers for Voltage Margining
Power Regulator
Signal Name
Jumper Setting
VCCINT (VR6)
VMARGIN_UP_VCC1V0_N
VMARGIN_DN_VCC1V0_N
VMARGIN_UP_SSTL18_N
VMARGIN_DN_SSTL18_N
VMARGIN_UP_SSTL2_N
VMARGIN_DN_SSTL2_N
VMARGIN_UP_HSTL_N
VMARGIN_DN_HSTL_N
VMARGIN_UP_VCC2V5_N
VMARGIN_DN_VCC2V5_N
P48: 1 -> 2
P48: 3 -> 2
P4: 1 -> 2
SSTL18 (VR1)
SSTL2 (VR9)
P4: 3 -> 2
P450 1 -> 2
P50: 3 -> 2
P58: 1 -> 2
P58: 3 -> 2
P69: 1 -> 2
P69: 3 -> 2
HSTL (VR10)
VCCAUX (VR12)
The TI PTH05010-WAZ and TI PTH05000-ADJ regulator outputs can be enabled or
inhibited through the use of on-board two-pin jumpers. The inhibit jumpers use the
following conventions:
•
•
Jumper OFF = Enabled
Jumper ON = Inhibited
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Chapter 3: Hardware Description
Table 3-18 summarizes the inhibit headers.
Table 3-18: Headers for Voltage Regulator Inhibition
Power Regulator
CCINT (VR6)
Inhibit Header
V
P63
P11
P32
P68
P5
SSTL18 (VR1)
SSTL18_M (VR4)
SSTL2 (VR9)
SSTL2_M (VR2)
HSTL (VR10)
P74
P105
P79
P101
HSTL_M (VR14)
VCCAUX (VR12)
VCC3V3 (VR13)
Board Design Considerations
and guidelines to be followed for designing a board for a MIG reference design.
The Virtex-5 FPGA ML561 Development Board design allows implementation of DCI
termination scheme at the FPGA for each of the memory interfaces on the board. A
preliminary analysis of the Weighted Average Simultaneously Switching Outputs
(WASSO) for all three Virtex-5 devices indicates that the SSO guidelines are met for the
current pinout. The following factors helped to reduce the SSO noise as compared to the
Virtex-4 FPGA ML461 board implementation:
•
•
•
SparseChevron pinout resulting in larger number of Power/GND pin pairs per bank
A revised higher SSO allowance per Power/GND pair for SparseChevron packages
Reduced thickness of the board (74 mils vs. 98 mils) resulting in reduced via
inductance
External terminations at both the memory and FPGA are provided for data signals for
most of the memory interfaces on the Virtex-5 FPGA ML561 Development Board layout.
The external V termination is implemented with a single 50Ω termination to the V
TT
REF
and guidelines for terminations.
These are V end terminations to the respective voltage levels for SSTL2, SSTL18, and
TT
HSTL signals. There are two topologies of end terminations for data signals:
1. Fly-by termination: The parallel termination is placed after the receiver pin.
2. Non-fly-by termination: The parallel termination is placed between the driver and the
receiver along the trace as close to the receiver pin as possible. Also the stub from
signal trace to the termination resistor is kept very short, within 0.1 inch.
For Read data, terminations at the FPGA have non-fly-by termination topology. These
terminations can be selectively depopulated on the ML561 board when DCI termination is
implemented inside FPGA for received data. Due to non-fly-by termination topology, the
result is a minimal stub for the signal, thus preserving good signal integrity for read data.
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Board Design Considerations
For Write data and terminations at the memory, if the trace length from the receiver pin to
the termination resistor can be guaranteed to be within 0.3 inches, then the fly-by
termination scheme is implemented. Otherwise, the non-fly-by termination topology is
implemented for Write data at the memory end.
The physical dimensions of the raw PCB are 12.75 inches x 11.75 inches. With the
overhangs due to edge connectors, the actual size of the fully assembled board is
approximately 13 inches x 12 inches, with 1.5 inches height allowance for the DIMM
modules. This 14-layer board has 6 signal layers, 4 GND layers, and 4 power planes and
diagram of the ML561 Revision A PCB.
using Virtex-5 devices.
1.0 oz, TOP, Z = 50Ω, width = 6 mils
0
3.8 mils, Er = 4.4
1.0 oz, 02_GND1
4 mils, Er = 4.4
0.5 oz, 03_INR1, Z = 50Ω, width = 4.5 mils
0
5.3 mils, Er = 4.4
1.0 oz, 04_PWR1
8 mils, Er = 4.4
0.5 oz, 05_INR2, Z = 50Ω, width = 4.5 mils
0
3.2 mils, Er = 4.4
1.0 oz, 06_GND2
3 mils, Er = 4.4
1.0 oz, 07_PWR2
3.3 mils, Er = 4.4
1.0 oz, 08_PWR3
3 mils, Er = 4.4
73.90 7 mils
1.0 oz, 09_GND3
3.2 mils, Er = 4.4
0.5 oz, 10_INR5, Z = 50Ω, width = 4.5 mils
0
8 mils, Er = 4.4
1.0 oz, 11_PWR4
5.3 mils, Er = 4.4
0.5 oz, 12_INR6, Z = 50Ω, width = 4.5 mils
0
4 mils, Er = 4.4
1.0 oz, 13_GND4
3.8 mils, Er = 4.4
1.0 oz, BOTTOM, Z = 50Ω, width = 6 mils
0
UG199_c3_11_102407
Figure 3-11: ML561 Revision A PCB Stack-Up
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Chapter 3: Hardware Description
Table 3-19 shows the details of the dielectric material and construction for each layer and
the controlled impedance values for the signal layers.
Table 3-19: ML561 Revision A PCB Controlled Impedance
Cu
Substrate
Test
Width
(mils)
Layer
Name
Z0
(ohms)
Seq #
Type
Usage
Weight Thickness
(oz.)
Er
Comment
(mils)
3.8
4
1
TOP
Metal
Dielectric
Metal
Signal
Substrate
Plane
1.0
<Auto>
4.4
6
50
50
50
5
5
5
Microstrip Signal Top
2
3
02_GND1
03_INR1
04_PWR1
05_INR2
06_GND2
07_PWR2
08_PWR3
09_GND3
10_INR5
11_PWR4
12_INR6
13_GND4
BOTTOM
1.0
0.5
1.0
0.5
1.0
1.0
1.0
1.0
0.5
1.0
0.5
1.0
1.0
<Auto>
4.4
Ground Plane #1
Stripline Signal - Inner #1
Split Power Plane #1
Stripline Signal - Inner #2
Ground Plane #2
4
Dielectric
Metal
Substrate
Signal
5
<Auto>
4.4
4.5
4.5
6
Dielectric
Metal
Substrate
Plane
5.3
8
7
<Auto>
4.4
8
Dielectric
Metal
Substrate
Signal
9
<Auto>
4.4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Dielectric
Metal
Substrate
Plane
3.2
3
<Auto>
4.4
Dielectric
Metal
Substrate
Plane
<Auto>
4.4
Split Power Plane #2
Split Power Plane #3
Ground Plane #3
Dielectric
Metal
Substrate
Plane
3.3
3
<Auto>
4.4
Dielectric
Metal
Substrate
Plane
<Auto>
4.4
Dielectric
Metal
Substrate
Signal
3.2
8
<Auto>
4.4
4.5
4.5
6
50
50
50
5
5
5
Stripline Signal - Inner #3
Split Power Plane #4
Stripline Signal - Inner #4
Ground Plane #4
Dielectric
Metal
Substrate
Plane
<Auto>
4.4
Dielectric
Metal
Substrate
Signal
5.3
4
<Auto>
4.4
Dielectric
Metal
Substrate
Plane
<Auto>
4.4
Dielectric
Metal
Substrate
Signal
3.8
<Auto>
Microstrip Signal Bottom
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Chapter 4
Electrical Requirements
This chapter provides the electrical requirements for the Virtex-5 FPGA ML561
Development Board. It contains the following sections:
•
•
Power Consumption
Table 4-1 lists the operating voltages, maximum currents, and power consumption used by
the ML561 board devices. The Virtex-5 FPGA ML561 Development Board has provisions
for two power inputs: a 5V power supply and a 12V power supply. The maximum rating of
a commercially available 5V power supply is limited to 8A, or a 40W maximum capacity.
This power supply is similar to the 5V brick used for previous memory tool kits, for
example, ML461. This tool kit expects the Virtex-5 FPGA ML561 Development Board to
exercise only one external memory interface at a time. In this case, the total power
consumption of the board stays within the 40W limit.
activated simultaneously, then the total power consumption is approximately 57W, which
exceeds the 40W capacity of the 5V power brick. So an alternate 12V power input jack (J23)
is provided on the Virtex-5 FPGA ML561 Development Board to hook up a 12V power
brick, for example, CUI DTS120500U with a 60W capacity. The 12V is converted to 5V
using the TI PTH12010WAS power module (VR11), which can supply up to 12A of current
at 5V, or a 60W capacity.
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Chapter 4: Electrical Requirements
Table 4-1: ML561 Power Consumption
Current Power
Device Description
Total Available Power
Quantity Voltage (V)
Source
(mA)
(W)
5V Power Supply
1
1
5.0
8000
5000
40.0 Bellus Power SPD-050-5
60.0 CUI DTS120500U
12V Power Supply
12.0
Power Consumed
DDR400 Component Interface
XC5VLX50T-FFG1136:
FPGA #1 (DDR400)
3.7
1
1.0, 2.5, 2.6 1887
DDR x16 Memory
2
2.6
1.2
210
16
1.1 Micron DDR Component Data Sheet
1.2 All signals. 608 mV swing around VTT
DDR Comp VTT Termination
DDR2 Component Interface
60
XC5VLX50T-FFG1136:
FPGA #1 (DDR2)
1.0, 1.8[S],
2.5
3.1
1
1991
DDR2 x16 Memory
2
1.8
1.2
250
16
0.9 Micron DDR2 Component Data Sheet
DDR2 Comp VTT Termination
DDR2 DIMM Interface
25
0.5 Addr/Cntl: 603 mV swing around VTT
XC5VLX50T-FFG1136:
FPGA #2 (DDR2)
1.0, 1.8[S],
2.5
10.2
1
6420
DDR2 DIMM
2
1.8
1.2
1755
16
6.3 Micron DDR2 DIMM Data Sheet
DDR2 DIMM VTT Termination
QDRII Memory Interface
160
3.1 All signals: 603 mV swing around VTT
XC5VLX50T-FFG1136:
FPGA #3 (QDRII)
1.0, 1.8[H],
1.8[S], 2.5
6.3
1
3917
QDRII Memory [H]
2
1.8
1.0
950
16
3.4 Samsung QDRII Data Sheet
QDRII VTT Termination
RLDRAM II Memory Interface
175
2.8 All signals. 500 mV swing around VTT
XC5VLX50T-FFG1136:
FPGA #3 (RLDRAM II)
1.0, 1.8[H],
2.5
4.5
1
3069
RLDRAM II Memory
RLDRAM II VTT Termination
Miscellaneous Circuit
Clock Buffer
2
1.8
1.0
920
16
3.3 Micron RLDRAM II Data Sheet
60
1.0 All signals. 500 mV swing around VTT
1
2
1
1
2
3.3
3.3
3.3
2.5
3.3
23
115
200
30
0.1 ICS8304 Data Sheet
Differential Clock Buffer
System ACE Controller
200 MHz Oscillator
0.8 ICS853006 Data Sheet
0.1 Epson EG2121CA Data Sheet
0.3 Epson SG-8002CA Data Sheet
53.2
33 MHz Oscillator
45
Total Power Consumed
40
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Power Consumption
Table 4-1: ML561 Power Consumption (Continued)
Current Power
Device Description
Quantity Voltage (V)
Source
(mA)
(W)
Power Modules Capacity
VCCINT Power Plane (1.0V)
HSTL FPGA Power Plane (1.8V)
HSTL Memory Power Plane (1.8V)
HSTL _VREF Power Plane (0.9V)
SSTL18 FPGA Power Plane (1.8V)
SSTL18 Memory Power Plane (1.8V)
SSTL18 _VREF Power Plane (0.9V)
SSTL2 FPGA Power Plane (2.6V)
SSTL2 Memory Power Plane (2.6V)
SSTL2 _VREF Power Plane (1.3V)
2.5V Power Plane
1
1
1
1
1
1
1
1
1
1
1
1
1
1.00
1.80
1.80
0.90
1.80
1.80
0.90
2.60
2.60
1.30
2.50
3.30
5.00
15000 15.0 TI PTH05010 15A Module Data Sheet
15000 27.0
6000
3000
10.8 TI PTH05000 6A Module Data Sheet
2.7 Fairchild FN6555 Data Sheet
15000 27.0 TI PTH05010 15A Module Data Sheet
6000
3000
10.8 TI PTH05000 6A Module Data Sheet
2.7 Fairchild FN6555 Data Sheet
15000 39.0 TI PTH05010 15A Module Data Sheet
6000
3000
15.6 TI PTH05000 6A Module Data Sheet
3.9 Fairchild FN6555 Data Sheet
15000 37.5 TI PTH05010 15A Module Data Sheet
15000 49.5
3.3V Power Plane
12V-to-5V Converter
12000 60.0 TI PTH12010 12A Module Data Sheet
Notes:
1. [S] = 1.8V power for SSTL18 plane.
2. [H] = 1.8V power for HSTL18 plane.
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Chapter 4: Electrical Requirements
Table 4-2 lists the 12 different power planes on the Virtex-5 FPGA ML561 Development
Board. For the SSTL2, SSTL18, and HSTL power, separate power modules are
implemented for V to FPGA, and V to memory, allowing for ease of power
CCO
DD
measurement for the FPGAs. The power modules for V
inputs are implemented with
CCO
TI PTH05010 modules, which have provisions for 5% voltage margining pins.
Table 4-2: Power Planes
Stack-Up
Layer
Voltage Regulator Module (VRM) Part
Power Plane
VRM REFDES
VCCINT Power Plane (1.0V)
VR6
VR1
Layer 4
Layer 7
Layer 8
Layer 11
Layer 8
Layer 11
Layer 7
Layer 8
Layer 8
Layer 8
Layer 8
Layer 7
Layer 7
Layer 7
Layer 7
SSTL18 FPGA Power Plane (1.8V)
HSTL FPGA Power Plane (1.8V)
VCCAUX Power Plane (2.5V)
VR10
VR12
VR9
TI PTH05010 15A Modules
SSTL2 FPGA Power Plane (2.6V)
TTL Power Plane (3.3V)
VR13
VR4
SSTL18 Memory Power Plane (1.8V)
HSTL Memory Power Plane (1.8V)
SSTL2 Memory Power Plane (2.6V)
SSTL18_VREF Power Plane (0.9V)
SSTL18_VTT Power Plane (0.9V)
HSTL_VREF Power Plane (0.9V)
HSTL_VTT Power Plane (0.9V)
SSTL2_VREF Power Plane (1.3V)
SSTL2_VTT Power Plane (1.3V)
TI PTH05000 6A Modules
VR14
VR2
U14
U42
U2
Fairchild FN6555 3A Bus Term Regulators
(Separate outputs for VTT and VREF
)
Each of the three Fairchild FN6555 Bus Terminator Regulators has two voltage outputs:
one each for V and V . The FN6555 regulator is a push-pull device rated at 3A for the
REF
TT
V
output and 3 mA for the V
output.
TT
REF
Because the V
voltage is used by the FPGA and memory devices only as reference, the
REF
power supply does not source any real current. Thus the 3 mA capacity for the V
is considered sufficient.
output
REF
The V voltage is guaranteed to within 20 mV of the V
regulator. The minimum driver output voltage swing around V
SSTL18, SSTL2, and HSTL I/O standards as:
output by the FN6555
REF
TT
is specified for the
REF
•
•
•
SSTL2: 608 mV
SSTL18: 603 mV
HSTL: 500 mV (for HSTL18)
For a given memory interface, the maximum number of single-ended (non-differential)
signals that might need to be pulled up or down at a time for QDRII is 144 data bits and
approximately 30 address and control signals. The differential pair signals offset for the
sink and source of current. With a continuous current capacity of 3A for the FN6555
regulator, the regulator can supply up to (3000 / 175) = 17 mA of current per signal. The
maximum drive strength for a driver is specified at 16 mA. For a 50ΩV termination, this
TT
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Power Consumption
current can support a voltage swing of up to (16 mA * 50Ω) = 800 mV, which is sufficient to
meet the output voltage specifications for SSTL18, SSTL2, and HSTL18 I/O standards.
nine TI power modules for the first set of nine power planes and the three Fairchild
regulators for the V power planes. The positive values in the Excess Power column of
TT
Table 4-3 show that each of the 14 modules can supply the necessary power for the
corresponding power plane.
Table 4-3: ML561 Power Plane Capacities
Device Description Quantity
Total Available Power
Excess
Power
(W)
Voltage Current Power
Source
(V)
(mA)
(W)
5V Power Supply
1
1
5.0
8000
5000
40.0
60.0
Bellus Power SPD-050-5
CUI DTS120500U
12V Power Supply
12.0
Power Consumed by Power Plane
XC5VLX50T-FFG1136: FPGA #1
(DDR400, DDR2)
1
1
1
1
1.0
1.0
1.0
1.0
2289
1945
2675
15000
2.3
1.9
XC5VLX50T-FFG1136: FPGA #2
(DDR2 DIMM)
XC5VLX50T-FFG1136: FPGA #3
(QDRII and RLDRAM II)
2.7
VCCINT Power Plane (1.0V) Capacity
TI PTH05010 15A Module Data
Sheet
15.0
8.1
XC5VLX50T-FFG1136: FPGA #3
(QDRII and RLDRAM II)
1
1
1.8
1.8
3876
7.0
HSTL FPGA Power Plane (1.8V)
Capacity
TI PTH05010 15A Module Data
Sheet
15000
27.0
20.0
QDRII Memory [H]
RLDRAM II Memory
2
2
1.8
1.8
950
920
3.4
3.3
Samsung QDRII Data Sheet
Micron RLDRAM II Data Sheet
HSTL_Mem Power Plane (1.8V)
Capacity
TI PTH05000 6A Module Data
Sheet
1
1.8
1.0
6000
16
10.8
2.8
4.1
QDRII VTT Termination
All signals. 500 mV swing
175
around VTT
.
RLDRAM II VTT Termination
HSTL _VREF Power Plane (0.9V)
All signals. 500 mV swing
60
1
1.0
0.9
16
1.0
2.7
around VTT
.
3000
-0.1 Fairchild FN6555 Data Sheet
XC5VLX50T-FFG1136:
FPGA #1 (DDR2)
1
1
1.8
1.8
1011
4258
1.8
7.7
XC5VLX50T-FFG1136:
FPGA #2 (DDR2 DIMM)
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Chapter 4: Electrical Requirements
Table 4-3: ML561 Power Plane Capacities (Continued)
Excess
Power
(W)
Voltage Current Power
Device Description
Quantity
Source
(V)
(mA)
(W)
SSTL18 FPGA Power Plane (1.8V)
Capacity
TI PTH05010 15A Module Data
Sheet
1
1.8
15000
27.0
17.5
DDR2 x16 Memory
Micron DDR2 Component Data
Sheet
2
2
1
1.8
1.8
1.8
250
1755
6000
0.9
6.3
DDR2 DIMM
Micron DDR2 DIMM Data Sheet
SSTL18_Mem Power Plane (1.8V)
Capacity
TI PTH05010 15A Module Data
Sheet
10.8
3.6
DDR2 Comp VTT Termination
DDR2 DIMM VTT Termination
SSTL18 _VREF Power Plane (0.9V)
Addr/Cntl: 603 mV swing
around VTT
25
1.2
16
0.5
All signals: 603 mV swing
around VTT
160
1
1.2
0.9
16
3.1
2.7
3000
-0.9 Fairchild FN6555 Data Sheet
XC5VLX50T-FFG1136: FPGA #1
(DDR400, DDR2)
1
1
1
2.5
2.5
2.5
609
218
435
1.5
0.5
1.1
XC5VLX50T-FFG1136: FPGA #2
(DDR2 DIMM)
XC5VLX50T-FFG1136: FPGA #3
(QDRII and RLDRAM II)
Differential Clock Buffer
200 MHz Osc
2
1
2.5
2.5
115
30
0.8
0.1
ICS853006 Data Sheet
Epson EG2121CA Data Sheet
2.5V Power Plane Capacity
TI PTH05010 15A Module Data
Sheet
1
2.5
15000
37.5
34.1
XC5VLX50T-FFG1136: FPGA #1
(DDR400)
1
1
2.6
2.6
950
2.5
SSTL2_FPGA Power Plane (2.6V)
Capacity
TI PTH05010 15A Module Data
Sheet
15000
39.0
36.5
DDR x16 Memory
Micron DDR Component Data
Sheet
2
1
2.6
2.6
210
1.1
SSTL2_Mem Power Plane (2.6V)
Capacity
TI PTH05010 15A Module Data
Sheet
6000
15.6
14.5
DDR Comp VTT Termination
All signals. 608 mV swing
around VTT
60
1
1.2
1.3
3.3
16
3000
23
1.2
3.9
0.1
SSTL2 _VREF Power Plane (1.3V)
Clock Buffer
2.7
Fairchild FN6555 Data Sheet
1
ICS8304 Data Sheet
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Power Consumption
Table 4-3: ML561 Power Plane Capacities (Continued)
Excess
Power
(W)
Voltage Current Power
Device Description
System ACE Controller
Quantity
Source
(V)
(mA)
(W)
1
2
1
3.3
3.3
3.3
200
45
0.7
0.3
CompactFlash Solution
33 MHz Oscillator
Epson SG-8002CA Data Sheet
3.3V Power Plane Capacity
TI PTH05010 15A Module Data
Sheet
15000
49.5
47.8
6.8
Total Power Consumed
53.2
12V-to-5V Power Module Capacity
TI PTH12010 12A Module Data
Sheet
1
5.0
12000
60.0
Notes:
1. [S] = 1.8V power for SSTL18 plane.
2. [H] = 1.8V power for HSTL18 plane.
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Chapter 4: Electrical Requirements
FPGA Internal Power Budget
Table 4-4 summarizes power consumption estimates by each of the three
XC5VLX50T-FFG1136 FPGAs on the Virtex-5 FPGA ML561 Development Board. This
estimate derives the FPGA utilization information from the respective map report of a fully
configured reference design.
Table 4-4: ML561 FPGA Power Estimate Summary
FPGA #
FPGA #1
FPGA #2(1)
FPGA #3
DDR400 Comp DDR2 Comp
DDR2 DIMM
(DCI)
RLDRAM II
Interface
QDRII (DCI)
(DCI)
(DCI)
(DCI)
HSTL_18
4.5
I/O Standard
SSTL_18
HSTL_18
Total Power (W)
3.7
3.1
10.2
6.3
VCCINT (1.0V) mW
763
435
763
544
1945
544
1160
544
1515
544
VCCAUX (2.5V) mW
SSTL_18 VCCO (1.8V) mW
SSTL_2 VCCO (2.6V) mW
HSTL_18 VCCO (1.8V) mW
1819
7664
2469
4571
2406
I/O Frequency (MHz)
200
200
400
200
400
200
400
200
400
200
Fabric Frequency (MHz)
Number of Slices
1500
2000
50
1500
2000
50
5910
7352
143
2750
2000
750
1951
1800
400
Number of Flip-flops
Number of Shift Register LUTs
Number of Block RAMs
Number of DCMs
5
2
5
2
17
2
14
2
21
2
Inputs
10
50
36
10
50
40
10
90
90
160
0
13
52
36
Outputs
Bidirectionals
192
Ambient Temperature (°C)
Airflow (LFM)
25
0
25
0
25
250
5
25
250
5
25
0
Heat Sink (Theta-J)
n/a
n/a
n/a
Junction Temperature (°C)
67
60
78
58
76
Notes:
1. For DDR2 DIMMs as well as QDRII memory interfaces with DCI, an MD35E-10B heat sink is needed. A heat sink with Theta-J = 5.0
should be okay without airflow. See http://www.alphanovatech.com/c_md35e.html for the heat sink profile. A heat sink with
Theta-J = 5.0 might need airflow of 250 LFM.
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Chapter 5
Signal Integrity Recommendations
Termination and Transmission Line Summaries
The following are common recommendations for the signal termination scheme to all
external memories implemented on the Virtex-5 FPGA ML561 Development Board:
•
Single-ended signals: Simulation indicates that for a single-ended signal, there is no
significant performance difference for a signal with split termination of 100Ω+ 100Ω
between V and GND versus the V termination of 50Ωto the V voltage.
DD
TT
REF
Because the power consumption for the split termination is considerably higher than
the V termination for the SSTL2, SSTL18, and HSTL I/O standards, V termination
TT
TT
is recommended for single-ended signals on the board, such as data, address, and
control. For bidirectional single-ended signals (for example, DDR2 DQ), the V
TT
termination is provided at both ends of the signal at the FPGA as well as at the
memory.
•
•
Differential signals: For differential pair signals, a 100Ωdifferential termination is
provided between the two legs of the differential pair. This termination is placed
closest to the load. For bidirectional differential signals (for example, DDR2 DQS), the
differential SelectIO™ primitives in Virtex-5 FPGAs (for example,
DIFF_SSTL_II_18_DCI), account for the differential termination within the IOB. So
external differential termination is required only at the memory.
Multiload signals: Address and control signals are driven by the FPGA, and they
have multiple loads. The termination is placed at the end of the trace after the last
load.
Virtex-5 FPGA ML561 Development Board for the following five different memory
interfaces. For each signal category, these tables include reference to the preliminary IBIS
(1)
simulation results
.
1. Virtex-4 device IBIS models were used during the development of the ML561 board to understand the
expected signal integrity of the memory interface signals. When the Virtex-5 device IBIS models are available,
the results of post-layout IBIS simulations and characterization results will be reported.
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Chapter 5: Signal Integrity Recommendations
Table 5-1: DDR400 SDRAM Component Terminations
Signal
FPGA Driver
SSTL2_II_DCI
SSTL2_II_DCI
SSTL2_II
Termination at FPGA
No termination
Termination at Memory
50Ωpull-up to 1.3V
Data (DQ)
Data Strobe (DQS)
Clock (CK, CK)
No termination
50Ωpull-up to 1.3V
No termination
100Ωdifferential termination
between pair
Address (A, BA)
SSTL2_II
SSTL2_II
No termination
No termination
50Ωpull-up to 1.3V after the last
component
Control (RAS, CAS, WE, CS, DM, and
CKE)
50Ωpull-up to 1.3V after the last
component
Table 5-2: DDR2 SDRAM DIMM Terminations
Signal
Data (DQ)
FPGA Driver
SSTL18_II_DCI
DIFF_SSTL18_II_DCI
SSTL18_II
Termination at FPGA
Termination at Memory
No termination
No termination
No termination
No termination
No termination (use 75ΩODT(1)
)
Data Strobe (DQS, DQS)
Data Mask (DM)
No termination (use 75ΩODT)
No termination (use 75ΩODT)
No termination(2)
6 Pairs of Clocks (CK, CK),
3 each per DIMM
SSTL18_II
Address (A, BA)
SSTL18_II
SSTL18_II
No termination
No termination
50Ωpull-up to 0.9V after the second
DIMM
Control (RAS, CAS, WE,
CS, CKE, and others)
50Ωpull-up to 0.9V after the second
DIMM
Notes:
1. Due to use of DCI I/O for DQ and DQS, these signals have parallel termination at the source during Write operations. Simulation
results show that use of a weaker 75ΩODT instead of a matching 50ΩODT setting gives better noise margin at the memory.
2. The DIMM already contains 120Ωdifferential termination. A 5 pF capacitive termination is provided on the board as per Micron
Table 5-3: DDR2 SDRAM Component Terminations
Signal
FPGA Driver
SSTL18_II_DCI
DIFF_SSTL18_II_DCI
SSTL18_II
Termination at FPGA
No termination
No termination
No termination
No termination
Termination at Memory
No termination (use 75ΩODT)
No termination (use 75ΩODT)
No termination (use 75ΩODT)
Data (DQ)
Data Strobe (DQS, DQS)
Data Mask (DM)
Clock (CK, CK)
SSTL18_II
100Ωdifferential termination between
pair
Address (A, BA)
SSTL18_II
SSTL18_II
No termination
No termination
50Ωpull-up to 0.9V after the last
component
Control (RAS, CAS, WE, CS,
and CKE)
50Ωpull-up to 0.9V after the last
component
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Termination and Transmission Line Summaries
Table 5-4: QDRII SRAM Terminations
Signal
Write Data (D)
FPGA Driver
Termination at FPGA
Termination at Memory
50Ωpull-up to 0.9V
HSTL_I_18
HSTL_I_DCI_18
HSTL_I_18
No termination
No termination
No termination
No termination
No termination
Read Data (Q)
No termination
50Ωpull-up to 0.9V
No termination
Write Strobe (K, K)
Read Strobe (CQ, CQ)
Clock (CK, CK)
HSTL_I_DCI_18
HSTL_I_18
100Ωdifferential termination
between pair
Address (A, BA)
HSTL_I_18
HSTL_I_18
No termination
No termination
50Ωpull-up to 0.9V after the last
component
Control (RAS, CAS, WE,
CS, CKE, and BW)
50Ωpull-up to 0.9V after the last
component
Table 5-5: RLDRAM II Terminations
Signal
FPGA Driver
Termination at FPGA
No termination
No termination
No termination
No termination
Termination at Memory
50Ωpull-up to 0.9V
No termination
Data (DQ for CIO)
Data (Q for SIO)
HSTL_II_DCI_18
HSTL_I_DCI_18
HSTL_I_18
Write Data (D for SIO)
Write Strobe (DK, DK)
50Ωpull-up to 0.9V
DIFF_HSTL_I_18
100Ωdifferential termination
between pair
Read Strobe (QK, QK)
Data Valid (QVLD)
Clock (CK, CK)
DIFF_HSTL_II_DCI_18 (for CIO)
DIFF_HSTL_I_DCI_18 (for SIO)
No termination
No termination
No termination
No termination
No termination
No termination
No termination
HSTL_II_DCI_18 (for CIO)
HSTL_I_DCI_18 (for SIO)
DIFF_HSTL_I_18
100Ωdifferential termination
between pair
Address (A, BA)
HSTL_I_18
50Ωpull-up to 0.9V after the last
component
Control (RAS, CAS, WE,
CS, and CKE)
HSTL_I_18
50Ωpull-up to 0.9V after the last
component
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Chapter 5: Signal Integrity Recommendations
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Chapter 6
Configuration
This chapter provides a brief description of the FPGA configuration methods used on the
Virtex-5 FPGA ML561 Development Board. This chapter contains the following sections:
•
•
•
•
•
Configuration Modes
The Virtex-5 FPGA ML561 Memory Interfaces Development Board includes several
options to configure the Virtex-5 FPGAs. The configuration modes are:
•
•
System ACE mode
JTAG mode
Table 6-1 shows the Virtex-5 FPGA configuration modes. The Master and Slave (Parallel)
SelectMAP configuration modes are not supported on the Virtex-5 FPGA ML561
Development Board. A separate 6-pin 3x2 header is provide for each FPGA to control the
Mode bits setting. The three headers are P27, P46, and P112 for FPGA #1, FPGA #2, and
FPGA #3, respectively. The even pins (# 2, 4, and 6) of the headers are tied to GND, and the
odd pins (# 1, 3, and 5) are connected to the respective Mode bit FPGA inputs (M0, M1, and
M2, respectively). A weak (4.7KΩ) pull-up is applied to each of these pins to set a logic '1'
by default.
Table 6-1: Configuration Modes
Mode Jumpers(3,4)
XCONFIG
P72
JTAG
P114
Mode
5 -> 6
(M2)
3 -> 4
(M1)
1 -> 2
(M0)
(2)
Master Serial
X(1)
X
—
0
1
0
1
1
0
1
1
1
0
0
1
1
0
1
Slave Serial
—
—
—
X
Master SelectMAP
Slave SelectMAP
JTAG
—
—
—
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Chapter 6: Configuration
Table 6-1: Configuration Modes (Continued)
Mode Jumpers(3,4)
XCONFIG
P72
JTAG
P114
Mode
5 -> 6
3 -> 4
(M1)
1 -> 2
(M2)
(M0)
System ACE CF Card
—
—
1
1
1
Notes:
1. X = Supported.
2. — = Not applicable.
3. Corresponding jumper position is Closed.
4. Corresponding jumper position is Open.
JTAG Chain
Four devices (the System ACE chip and three XC5VLX50T-FFG1136 FPGAs) are connected
via a JTAG chain on the Virtex-5 FPGA ML561 Development Board. The order of the four
devices in the JTAG chain is System ACE chip (U45), FPGA #1 (U7), FPGA #2 (U5), and
FPGA #3 (U34). The DONE pin of the FPGAs in the chain are tied together to a single LED
(D28). Each FPGA in the JTAG chain must be programmed for the board to be configured
properly. To program FPGAs in the JTAG chain that do not need functionality, a blank
design with no logic implementation can be used to compile to generate the corresponding
configuration bitstream.
Three different sources can be used to drive this JTAG chain:
•
•
•
JTAG Port
Xilinx Parallel IV Cable
System ACE Controller
JTAG Port
The Virtex-5 FPGA ML561 Development Board provides a JTAG connector (P114) that can
be used to program the Virtex-5 FPGAs, and program and/or configure other JTAG
devices in the chain.
Parallel IV Cable Port
The Virtex-5 FPGA ML561 Development Board provides a Parallel IV Cable connector
(P64) to configure the Virtex-5 FPGAs and program JTAG devices located in the JTAG
chain.
System ACE Interface
The Virtex-5 FPGA ML561 Development Board provides a System ACE interface to
configure the Virtex-5 FPGA. The interface also gives software designers the ability to run
code (for soft processor IP within the FPGA) from removable CompactFlash cards.
System ACE compatible ACE files, formatting the CompactFlash card, and storing
multiple design images.
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System ACE Interface
Table 6-2 shows the System ACE interface signal names, descriptions, and pin
assignments.
Table 6-2: System ACE Interface Signal Descriptions
System ACE Pin Number
Signal Name
70
69
68
67
45
44
43
66
65
63
62
61
60
59
58
77
76
42
41
39
93
SYSACE_MPA0
SYSACE_MPA1
SYSACE_MPA2
SYSACE_MPA3
SYSACE_MPA4
SYSACE_MPA5
SYSACE_MPA6
SYSACE_MPD0
SYSACE_MPD1
SYSACE_MPD2
SYSACE_MPD3
SYSACE_MPD4
SYSACE_MPD5
SYSACE_MPD6
SYSACE_MPD7
SYSACE_CTRL0/MPOE
SYSACE_CTRL1/MPWE
SYSACE_CTRL2/MPCE
SYSACE_CTRL3/MPIRQ
SYSACE_CTRL4/MPBRDY
SYSACE_CLK
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Chapter 6: Configuration
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Chapter 7
ML561 Hardware-Simulation
Correlation
This chapter contains the following sections:
•
•
•
•
•
Introduction
Signal integrity (SI) simulation is a very powerful tool that predicts the quality of signal at
the receiver. The quality of signal at the I/O buffer of the receiver device is most important
to the system designer. The observation point is buried within the IC device and is not
accessible for attaching a physical probe. This signal can only be simulated. It cannot be
measured on the hardware with an oscilloscope.
Signals can only be measured on hardware at the via probe points of a printed circuit board
(PCB) near the receiver device. For a high level of confidence in the SI simulation results, it
is necessary to develop and validate the simulation model to get a good correlation with
the hardware measurements at the probe points. When the correlation is obtained, the
same simulation model is used to extrapolate and accurately predict the signal quality at
the I/O buffer of the receiver device for the two significant corner driver conditions: slow-
weak and fast-strong.
The Virtex-5 FPGA ML561 Development Board implements five different memory
interfaces:
•
•
•
•
•
32-bit DDR2 component
144-bit DDR2 DIMM
72-bit QDRII SRAM
32-bit DDR component
36-bit RLDRAM II
Each of these interfaces consists address, control, clock, data, and strobe signals. The
ML561 board has over 500 unique signals.
DDR2 SDRAMs and QDRII SRAM represent the large majority of Virtex-5 FPGA memory
applications. The dual data rate (DDR) data bits are the most critical signals to analyze.
This chapter presents SI analysis for only six representative data bit signals. The procedure
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Chapter 7: ML561 Hardware-Simulation Correlation
illustrated here for these signals can be easily adopted to perform SI analysis for any other
memory interface signal on the ML561 board.
This chapter presents the SI results for the following six data bit signals:
•
•
•
•
•
•
DDR2 component DQ bit (DDR2_DQ_BY2_B3) for write operations
DDR2 component DQ bit (DDR2_DQ_BY2_B3) for read operations
DDR2 DIMM DQ bit (DDR2_DIMM_DQ_BY2_B3) for write operations
DDR2 DIMM DQ bit (DDR2_DIMM_DQ_BY2_B3) for read operations
QDRII D bit (QDR2_D_BY0_B5) for write operations
QDRII Q bit (QDR2_Q_BY0_B5) for read operations
Test Setup
Hardware measurements were performed for the six specific signal nets, and then signal
integrity (SI) simulations were performed for correlation and extrapolation. The test setup
consisted of the following hardware equipment, simulation software tools, the stimulus
test pattern, and test criteria for determining the quality of signals. The test bench is
designed so that the test pattern is applied only to the signal under test, and all other data
bits to the same memory interface are kept in a quiet Low state. This setup ensures that the
hardware measurement is not altered due to any simultaneous switching output (SSO)
effect.
•
Hardware measurement equipment
♦
♦
♦
Agilent DSO80604B 6 GHz oscilloscope
Agilent 1131A 3.5 GHz Infiniimax probe amplifier
Agilent E2675A (Differential browser) or E2677A (Differential solder-in probe) or
N5425A (ZIF probe)
♦
♦
Virtex-5 FPGA ML561, Rev B2 board: S/N 103
SRS Model CG635 Synthesized Clock Generator for low jitter clock source
•
Simulation software
♦
Mentor Graphics HyperLynx EXT, Version 7.5 with LineSim and BoardSim
features
♦
Xilinx Virtex-5 FPGA IBIS package file: ff1136_5vlx50t.pkg, Rev 1.0 dated
June 12, 2006
♦
♦
♦
♦
♦
♦
ML561, Rev B layout file: ML561_B_041706.hyp
Micron DDR2-667 IBIS model for output and ODT input
Micron PC2-5300 RDIMM IBIS model
Molex DDR2 DIMM socket specification (P/N 087705-1041)
Samsung QDRII HSTL 1.8V IBIS model
IBISWriter Utility of ISE software suite to create customized IBIS model of the
FPGA1 (U7) and FPGA3 (U34) devices on the ML561 board: Model files
User-Specific FPGA IBIS Model,” page 93 for steps on how to create a customized
IBIS model of Virtex-5 FPGA for your design.)
•
Stimulus
Pseudo Random Bit Stream (PRBS) is accepted as the most effective test pattern to
measure the quality of data signals because, unlike the periodic signals like clock and
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Test Setup
strobe, a random value can be applied to data bits from one cycle to another. A 63-bit
(1)
PRBS6 (PRBS of order 6) test pattern stimulus is used for this analysis. The value of
this PRBS6 string is 63’h03F5_66ED_2717_9461, that is:
63’b000001111110101011001101110110100100111000101111001010001100001.
The HyperLynx stimulus setup is for: a 2-sequence repeat, 10 bits skipped, 1 eye, and
0% jitter.
•
Test criteria
Quality of a signal is measured in terms of the opening of the signal eye at the receiver
input for both the amplitude and the width. DDR2 SDRAM (Component and DIMM)
interfaces utilize the SSTL_18 I/O standard, and the QDRII SRAM interface utilizes
the HSTL 1.8V I/O standard. For each of these two I/O standards, the eye mask is
defined by the trapezoid enclosed by the following four voltage thresholds at the
receiver input:
♦
♦
♦
♦
VIH(ac)-min at the rising edge
VIH(dc)-min at the falling edge
VIL(dc)-max at the rising edge
VIL(ac)-max at the falling edge
Because the HyperLynx SI simulation software does not support a trapezoidal mask
definition, two separate triangular masks for VIH and VIL are defined, as shown in
Figure 7-2, such that the third vertex of triangle falls on the VREF axis.
VDDQ
VOH(dc)
VOH(ac)
VIH(ac)
VIH(dc)
VREF
VIL(dc)
VIL(ac)
VOL(ac)
VOL(dc)
VSS
UG199_c7_01_062707
Figure 7-1: Single Trapezoid Eye Mask Definition
1. A maximal-length PRBS test sequence of order n generates all (2n – 1), n-bit combinations of test sequences
(except all 0s). Thus the test sequence contains one n-bit long consecutive string of 1s and two (n-1)-bit long
consecutive strings of 0s. With the PRBS6 test pattern, at the highest test frequency of 333 MHz (that is, the bit
time is 1.5 ns), measurements in this setup result in a maximum settling time of (1.5 ns * 5) = 7.5 ns for a logic
Low, and a maximum settling time of (1.5 ns * 6) = 9 ns for a logic High. 7.5 ns is sufficient time for the test
signal to reach a steady state before the next transition. Thus a PRBS test pattern of higher order, such as 7 or
9, does not change the eye pattern, as proven by sample simulation of one test signal with PRBS6, PRBS7, and
PRBS9 stimuli.
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Chapter 7: ML561 Hardware-Simulation Correlation
VDDQ
VOH(dc)
VOH(ac)
VIH(ac)
VIL(ac)
VIH(dc)
VIL(dc)
VREF
VOL(ac)
VOL(dc)
VSS
UG199_c7_02_062707
Figure 7-2: Two Triangular Eye Mask Definitions for VIH and VIL
♦
♦
DDR2 mask (for nominal VDDQ = 1.8V and VREF = 0.9V):
-
-
-
-
VIH(ac)-min = VREF + 200 mV = 1.1V
VIH(dc)-min = VREF + 125 mV = 1.025V
VIL(ac)-max = VREF – 200 mV = 0.7V
VIL(dc)-max = VREF – 125 mV = 0.775V
QDRII mask (for nominal values of VDDQ = 1.8V and VREF = 0.9V):
-
-
-
-
VIH(ac)-min = VREF + 200 mV = 1.1V
VIH(dc)-min = VREF + 100 mV = 1.0V
VIL(ac)-max = VREF – 200 mV = 0.7V
VIL(dc)-max = VREF – 100 mV = 0.8V
Signal Integrity Correlation Results
This section presents SI results for each of the six chosen memory signals on the ML561
board. The following information is presented for each memory signal:
•
•
•
A post-layout IBIS schematics of the signal under test
(1)
A description of the major circuit elements of this signal
A summary of four SI results: hardware measurement, correlation simulation, slow-
weak corner driver simulation extrapolation, and fast-strong corner driver simulation
extrapolation
•
A set of eight figures showing eye and waveform scope shots for each of the four SI
results mentioned in the bulleted list in the previous section
For an explanation of the different terms used to present these results, refer to
1. With regard to transmission line impedance, Table 3-19 in the “Board Design Considerations” section lists
controlled impedance values of all routing layers. The design goal for the ML561 board is to keep the
characteristic impedance for all routing layers as close to 50Ωas possible. Manufacturing tolerance is usually
10%. The characteristic impedance of DIMM PCB is derived from the Micron DIMM layout file.
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Signal Integrity Correlation Results
DDR2 Component Write Operation
This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from FPGA1 (U7)
to the DDR2 memory component (U12) measured at 333 MHz (667 Mb/s), where the unit
interval (UI) = 1.5 ns.
49.1 ohms
47.132 ps
0.302 in
DDR2_DQ_BY2_B3
49.1 ohms
445.560 ps
2.852 in
DDR2_DQ_BY2_B3
28.5 ohms
4.473 ps
0.028 in
DDR2_DQ_BY2_B3
49.0 ohms
24.721 ps
0.164 in
DDR2_DQ_BY2_B3
28.5 ohms
3.579 ps
0.022 in
58.3 ohms
25.244 ps
AutoPadstk_19
21.2 ohms
1.000 ps
AutoPadstk_3
71.0 ohms
27.482 ps
U12.D3
U7.P25
DDR2_DQ_BY2_B3 AutoPadstk_3
TL2
TL3
TL4
TL8
TL9
TL6
TL5
TL1
Virtex-5 FPGA
MT47H32M16CC_…
DQ11
DDR2_DQ_BY2_B3
DDR2_D…
DDR2_D…
DDR2_D…
DDR2_D…
DDR2_D…
C9
C7
DDR2_D…
22.9 fF
58.1 fF
140.8 fF
22.9 fF
22.9 fF
500.0 fF
365.6 fF
500.0 fF
UG199_c7_03_071907
Figure 7-3: Post-Layout IBIS Schematics of DDR2 Component Write Data Bit (DDR2_DQ_BY2_B3)
Table 7-1: Circuit Elements of DDR2 Component Write Data Bit
(DDR2_DQ_BY2_B3)
Element
Designation
U7.P25
Description
FPGA SSTL18_II_DCI_O
Driver
Receiver
U12.D3
C9
DDR2 Memory, 75 ΩODT
Via under the memory device
ODT75 at load
Probe Point
PCB Termination
Trace Length
None
TL 2, 4, 9, 6, 1
3.37 inches
Table 7-2: DDR2 Component Write Operation Correlation Results
Noise Margin
(VIH, + VIL) = Total
(% of VREF)
Overshoot / Undershoot
Margin
DVW(1)
(%UI)
ISI
(% UI)
Measurement
(% of VREF)
(80 + 80) = 160 ps
(10.7%)
(274 + 384) = 658 mV
(73.1%)
(550 + 470) = 1020 mV
(113.3%)
Hardware at probe
point
1.18 ns
(78.7%)
(77 + 36) = 113 ps
(7.5%)
(294 + 266) = 560 mV
(62.2%)
(461 + 490) = 951 mV
(105.7%)
Simulation correlation
slow-weak corner
1.22 ns
(81.3%)
40 ps
47 ps
98 mV
69 mV
(7.6%)
Correlation Delta:
HW vs. Simulation
(2.6%)
(3.2%)
(10.9%)
(91 + 36) = 127 ps
(8.5%)
(300 + 270) = 570 mV
(63.3%)
(469 + 501) = 970 mV
(107.8%)
Extrapolation at IOB
slow-weak corner
1.27 ns
(84%)
(34 + 20) = 54 ps
(3.7%)
(406 + 351) = 757 mV
(84.1%)
(304 + 381) = 685 mV
(76.1%)
Extrapolation at IOB
fast-strong corner
1.39 ns
(92%)
Notes:
1. DVW = Data Valid Window, ISI = Inter-Symbol Interference
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Chapter 7: ML561 Hardware-Simulation Correlation
DDR2 DQ is a bidirectional signal. To perform hardware measurements for a Write
operation that is not interrupted by a Read response or a Refresh operation, the testbench
Table 7-3: DIP[1:2] Settings
Setting
2’b00or 2’b11
Description
Normal alternating Write/Read sequence
Write only, Refresh disabled
2’b01
2’b10
Write once, then Read only, Refresh disabled
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Signal Integrity Correlation Results
UG199_c7_04_071107
Figure 7-4: DDR2 Component Write HW Measurement - Eye Scope Shot at Probe Point (DDR2 Memory Via)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 3:C9.1 (at pin)
-200.0
0.000
400.0
800.0
1200.0
1600.0
Time (ps)
UG199_c7_05_070907
♦ 333 MHz, Slow, PRBS6, 81.5% UI
♦ Cursor 1: 1.1028V, 123.6 ps
♦ Cursor 2: 1.0253V, 1.3458 ns
♦ Delta Voltage = 77.5 mV, Delta Time = 1.2222 ns (81.5% UI)
Figure 7-5: DDR2 Component Write Correlation - Eye Scope Shot at Probe Point (Slow Corner)
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Chapter 7: ML561 Hardware-Simulation Correlation
UG199_c7_06_071107
Figure 7-6: DDR2 Component Write HW Measurement - Waveform Scope Shot at Probe Point
(DDR2 Memory Via)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 3:C9.1 (at pin)
-200.0
65.000
75.000
85.000
95.000
105.000
Time (ns)
Figure 7-7: DDR2 Component Write Correlation - Waveform Scope Shot at Probe Point (Slow Corner)
UG199_c7_07_070907
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Signal Integrity Correlation Results
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
Probe 1:U12.D3 (at die)
0.000
-200.0
-200.0
200.0
600.0
1000.0
1400.0
1800.0
Time (ps)
UG199_c7_08_071007
♦ 333 MHz, Slow, PRBS6, 84.5% UI
♦ Cursor 1: 1.1007V, 123.7 ps
♦ Cursor 2: 1.0253V, 1.3921 ns
♦ Delta Voltage = 75.4 mV, Delta Time = 1.2684 ns (84.5% UI)
Figure 7-8: DDR2 Component Write Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
Probe 1:U12.D3 (at die)
0.000
-200.0
65.000
75.000
85.000
95.000
105.000
Time (ns)
UG199_c7_09_071007
Figure 7-9: DDR2 Component Write Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
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Chapter 7: ML561 Hardware-Simulation Correlation
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
Probe 1:U12.D3 (at die)
1200.0 1600.0
-100.0
800.0
2000.0
2400.0
2800.0
Time (ps)
UG199_c7_10_071007
♦ 333 MHz, Fast, PRBS6, 92.5% UI
♦ Cursor 1: 701.2 mV, 1.0026 ns
♦ Cursor 2: 774.6 mV, 2.3908 ns
♦ Delta Voltage = 73.4 mV, Delta Time = 1.3883 ns (92.5% UI)
Figure 7-10: DDR2 Component Write Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
Probe 1:U12.D3 (at die)
-100.0
65.000
75.000
85.000
95.000
105.000
Time (ns)
UG199_c7_11_071007
Figure 7-11: DDR2 Component Write Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
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Signal Integrity Correlation Results
DDR2 Component Read Operation
This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from the DDR2
memory component (U12) to FPGA1 (U7) measured at 333 MHz (667 Mb/s), where the
unit interval (UI) = 1.5 ns.
U7.P25
U12.D3
TL2
TL3
TL4
TL8
TL9
TL6
TL5
TL1
49.1 ohms
47.132 ps
0.302 in
49.1 ohms
445.560 ps
2.852 in
28.5 ohms
28.5 ohms
49.0 ohms
21.2 ohms
1.000 ps
AutoPadstk_3
58.3 ohms
71.0 ohms
27.482 ps
AutoPadstk_3
Virtex-5 FPGA
DDR2_DQ_BY2_B3
4.473 ps
3.579 ps
24.721 ps
25.244 ps
MT47H64M8CB-3
DQ3
0.028 in
DDR2_DQ_BY2_B3
0.022 in
DDR2_DQ_BY2_B3
0.164 in
DDR2_DQ_BY2_B3
AutoPadstk_19
DDR2_DQ_BY2_B3 DDR2_DQ_BY2_B3
DDR2_D…
DDR2_D…
58.1 fF
DDR2_D…
DDR2_D…
DDR2_D…
DDR2_D…
C9
C7
500.0 fF
22.9 fF
140.8 fF
22.9 fF
22.9 fF
500.0 fF
365.6 fF
UG199_c7_12_071907
Figure 7-12: Post-Layout IBIS Schematics of the DDR2 Component Read Data Bit (DDR2_DQ_BY2_B3)
Table 7-4: Circuit Elements of DDR2 Component Read Data Bit
(DDR2_DQ_BY2_B3)
Element
Designation
U12.D3
Description
DDR2 Memory
Driver
Receiver
U7.P25
C7
FPGA SSTL18_II_DCI_I
Via under FPGA1
DCI at receiver
Probe Point
PCB Termination
Trace Length
None
TL 2, 4, 9, 6, 1
3.37 inches
Table 7-5: DDR2 Component Read Operation Correlation Results
Noise Margin
(VIH + VIL) = Total
(% of VREF)
Overshoot /
Undershoot Margin
(% of VREF)
ISI
(% UI)
Measurement
DVW (% UI)
(70 + 110) = 180 ps
(12%)
(423 + 416) = 839 mV
(83.1%)
(400 +400) = 800 mV
(79.1%)
1.28 ns
(85%)
Hardware at probe point
(132 + 91) = 223 ps
(14.9%)
(406 +439) = 845 mV
(83.8%)
(279 +277) = 556 mV
(61.9%)
Simulation correlation
slow-weak corner
1.28 ns
(85%)
0 ps
43 ps
6 mV
244 mV
(17.2%)
Correlation Delta:
HW vs. Simulation
(0.0%)
(2.9%)
(0.7%)
(96 + 82) = 178 ps
(11.9%)
(418 + 449) = 867 mV
(96.3%)
(304 +265) = 569 mV
(63.1%)
Extrapolation at IOB
slow-weak corner
1.29 ns
(86%)
(29 + 67) = 96 ps
(6.7%)
(455 +435) = 890 mV
(98.9%)
(167 +182) = 349 mV
(38.9%)
Extrapolation at IOB
fast-strong corner
1.32 ns
(88%)
To perform hardware measurements for a Read operation that is not interrupted by a Write
or a Refresh operation, the testbench on FPGA1 is controlled by the following DIP switch
(SW2) setting:
•
DIP[1:2] = 2’b10– Write once, then Read only, Refresh disabled
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Chapter 7: ML561 Hardware-Simulation Correlation
UG199_c7_13_071107
Figure 7-13: DDR2 Component Read HW Measurement - Eye Scope Shot at Probe Point (FPGA1 Via)
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
Probe 3:C7.1 (at pin)
-100.0
800.0
1200.0
1600.0
2000.0
2400.0
2800.0
Time (ns)
UG199_c7_14_071107
♦ 333 MHz, Slow, PRBS6, 85.9% UI
♦ Cursor 1: 697.1 mV, 1.2345 ns
♦ Cursor 2: 774.6 mV, 2.5191 ns
♦ Delta Voltage = 77.5 mV, Delta Time = 1.2846 ns (85.9% UI)
Figure 7-14: DDR2 Component Read Correlation - Eye Scope Shot at Probe Point (Slow Corner)
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Signal Integrity Correlation Results
UG199_c7_15_071107
Figure 7-15: DDR2 Component Read HW Measurement - Waveform Scope Shot at Probe Point (FPGA1
Via)
1900.0
Probe 3:C7.1 (at pin)
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
-100.0
65.000
75.000
85.000
95.000
105.000
Time (ns)
UG199_c7_16_071007
Figure 7-16: DDR2 Component Read Correlation - Waveform Scope Shot at Probe Point (Slow Corner)
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Chapter 7: ML561 Hardware-Simulation Correlation
1900.0
Probe 1:U7.P25 (at die)
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
-100.0
800.0
1200.0
1600.0
2000.0
2400.0
2800.0
Time (ps)
UG199_c7_17_071007
♦ 333 MHz, Slow, PRBS6, 85.5% UI
♦ Cursor 1: 1.0988V, 1.2170 ns
♦ Cursor 2: 1.0254V, 2.5029 ns
♦ Delta Voltage = 73.4 mV, Delta Time = 1.2859 ns (85.5% UI)
Figure 7-17: DDR2 Component Read Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 1:U7.P25 (at die)
-200.0
65.000
75.000
85.000
95.000
105.000
Time (ns)
UG199_c7_18_071007
Figure 7-18: DDR2 Component Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
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Signal Integrity Correlation Results
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
Probe 1:U7.P25 (at die)
700.0
500.0
300.0
100.0
-100.0
800.0
1200.0
1600.0
2000.0
2400.0
2800.0
Time (ps)
UG199_c7_19_071007
♦ 333 MHz, Fast, PRBS6, 88% UI
♦ Cursor 1: 701.2 mV, 1.0772 ns
♦ Cursor 2: 774.6 mV, 2.3980 ns
♦ Delta Voltage = 73.4 mV, Delta Time = 1.3208 ns (88% UI)
Figure 7-19: DDR2 Component Read Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
Probe 1:U7.P25 (at die)
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
-100.0
65.000
75.000
85.000
95.000
105.000
Time (ns)
UG199_c7_20_071007
Figure 7-20: DDR2 Component Read Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
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Chapter 7: ML561 Hardware-Simulation Correlation
DDR2 DIMM Write Operation
This subsection shows the test results for the DDR2_DIMM_DQ_BY2_B3 signal from
FPGA2 (U5) to the DDR2 DIMM (XP2) measured at 333 MHz (667 Mb/s), where the unit
interval (UI) = 1.5 ns.
49.8 ohms
94.605 ps
0.606 in
DDR2_DIMM_DQ_...
49.8 ohms
90.340 ps
0.578 in
DDR2_DIMM_DQ_...
28.5 ohms
4.473 ps
0.028 in
DDR2_DIMM_DQ_...
49.8 ohms
90.955 ps
0.582 in
DDR2_DIMM_DQ_...
49.1 ohms
78.216 ps
0.501 in
49.1 ohms
41.316 ps
0.264 in
49.8 ohms
864.365 ps
5.533 in
DDR2_DIMM_DQ_...
71.6 ohms
22.319 ps
59.1 ohms
12.486 ps
AutoPadstk_12_B...
U5_B00.H29
AutoPadstk_3_B00
DDR2_DIMM_DQ_... DDR2_DIMM_DQ_...
59.8 ohms
3.590 ps
0.022 in
59.8 ohms
31.503 ps
0.195 in
59.8 ohms
78.962 ps
0.490 in
59.8 ohms
10.373 ps
0.064 in
J1_B01.31
U3_B01.J1
MDQ19_B01 MDQ19_B01 MDQ19_B01
DQ19_B01
RN6_B01
22.0 ohms
TL15
TL16
TL17
TL18
TL19
TL20
TL7
TL6
TL3
Virtex-5 FPGA
DDR2_DQ_BY2_B3
XP2_B00.31
XP3_B00.31
XP4_B00.31
XP5_B00.31
TL1
TL5
TL11
TL12
MT47H64M8CB_C...
DQ6
????
DDR2_DI...
22.9 fF
DDR2_DI...
96.3 fF
DDR2_DI...
253.0 fF
DDR2_DI...
46.4 fF
C8
TL14
????
TL27
????
TL23
????
TL25
????
MDQ19_...
17.3 fF
C13
500.0 fF
50.3 ohms
23.650 ps
DDR2_D...
50.3 ohms
23.650 ps
DDR2_D...
50.3 ohms
23.650 ps
DDR2_D...
50.3 ohms
23.650 ps
DDR2_D...
500.0 fF
R_00179...
0.0 milliohms
R7
R5
R6
0.0 milliohms
0.0 milliohms
0.0 milliohms
TL13
TL26
TL22
TL24
50.3 ohms
23.650 ps
DQ19_B...
50.3 ohms
23.650 ps
DQ19_B...
50.3 ohms
23.650 ps
DQ19_B...
50.3 ohms
23.650 ps
DQ19_B...
UG199_c7_21_071907
Figure 7-21: Post-Layout IBIS Schematics of DDR2 DIMM Write Data Bit (DDR2_DIMM_DQ_BY2_B3)
Table 7-6: Circuit Elements of DDR2 DIMM Write Data Bit
(DDR2_DIMM_DQ_BY2_B3)
Element
Designation
U5.H29
Description
FPGA SSTL18_II_DCI_O
DDR2 DIMM, 75 ΩODT
Via under memory on DIMM
ODT at load
Driver
Receiver
XP2-U3.J1
C13
Probe Point
PCB Termination
Trace Length
None
Multiple TLs
8.975 inches
The IBIS schematics for DDR2 DIMM interface is extracted from a multi-board project
definition of the two-board combination, which includes the ML561 motherboard and the
DDR2 DIMM at the XP2 connector of the motherboard. The impedance characteristics of
the Molex socket pin (XP2, pin 31) is also included in the IBIS model as a (TL13,
R_00179_CONN_0001, TL14) combination.
The ML561 board under test (S/N 103) is assembled with DDR2 sockets XP3, XP4, and
the three socket pins at the XP3, XP4, and XP5 connectors.
The DDR2 DIMM used for this correlation testing is a single-rank DIMM part (Micron part
number MT9HTF6472xx-667). Thus for hardware measurements closest to the load, a
probe point via on the DIMM for pin U3.J1 is available.
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Signal Integrity Correlation Results
Table 7-7: DDR2 DIMM Write Operation Correlation Results
Noise Margin
(VIH + VIL) = Total
(% of VREF)
Overshoot / Undershoot
Margin
DVW
(%UI)
ISI
(% UI)
Measurement
(% of VREF)
(300 + 200) = 500 ps
(33.3%)
(110 + 100) = 210 mV
(23.3%)
(620 + 620) = 1240 mV
(137.7%)
Hardware at Probe
Point
942 ps
(62.8%)
Simulation correlation
at memory via (C13)
slow-weak corner
(80 + 54) = 134 ps
(8.9%)
(172 + 150) = 322 mV
(35.9%)
(606 + 636) =1242 mV
(138%)
1.16 ns
(77.3%)
Correlation Delta:
HW vs. Simulation
218 ps
366 ps
112 mV
(12.6%)
2 mV
(14.5%)
(24.4%)
(0.3%)
(85 + 32) = 117 ps
(7.8%)
(178 + 137) = 315 mV
(35.0%)
(604 + 632) = 1236 mV
(137.3%)
Extrapolation at IOB
slow-weak corner
1.23 ns
(82%)
(54 + 46) = 100 ps
(6.7%)
(146 + 107) = 253 mV
(28.1%)
(457 + 524) = 981 mV
(109.0%)
Extrapolation at IOB
fast-strong corner
1.32 ns
(88%)
DDR2 DQ is a bidirectional signal. To perform hardware measurements for a Write
operation that is not interrupted by a Read response or a Refresh operation, the testbench
Table 7-8: DIP[1:2] Settings
Setting
2’b00or 2’b11
Description
Normal alternating Write/Read sequence
Write only, Refresh disabled
2’b01
2’b10
Write once, then Read only, Refresh disabled
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Chapter 7: ML561 Hardware-Simulation Correlation
UG199_c7_22_071107
Figure 7-22: DDR2 DIMM Write HW Measurement - Eye Scope Shot at Probe Point #1 (DDR2 Memory Via)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 3:C13.1 (at pin)
-200.0
800.0
1200.0
1600.0
2000.0
2400.0
2800.0
Time (ps)
UG199_c7_23_070907
♦ 333 MHz, Slow, PRBS6, 77% UI
♦ Cursor 1: 1.1004V, 1.2553 ns
♦ Cursor 2: 1.0253V, 2.4105 ns
♦ Delta Voltage = 75.2 mV, Delta Time = 1.1582 ns (77% UI)
Figure 7-23: DDR2 DIMM Write Correlation - Eye Scope Shot at Probe Point #1 (Slow Corner)
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Signal Integrity Correlation Results
UG199_c7_24_071107
Figure 7-24: DDR2 DIMM Write HW Measurement - Waveform Scope Shot at Probe Point #1 (DDR2 Memory
Via)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 3:C13.1 (at pin)
-200.0
95.000
105.000
115.000
125.000
135.000
145.000
Time (ns)
UG199_c7_23_071007
Figure 7-25: DDR2 DIMM Write Correlation - Waveform Scope Shot at Probe Point #1 (Slow Corner)
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Chapter 7: ML561 Hardware-Simulation Correlation
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 6:U3_B01.J1 (at die)
-200.0
1000.0
1400.0
1800.0
2200.0
2600.0
Time (ps)
UG199_c7_26_071007
♦ 333 MHz, Slow, PRBS6, 82% UI
♦ Cursor 1: 1.1028V, 1.2399 ns
♦ Cursor 2: 1.0253V, 2.4671 ns
♦ Delta Voltage = 77.5 mV, Delta Time = 1.2272 ns (82% UI)
Figure 7-26: DDR2 DIMM Write Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 6:U3_B01.J1 (at die)
-200.0
95.000
105.000
115.000
125.000
135.000
145.000
Time (ns)
UG199_c7_27_071007
Figure 7-27: DDR2 DIMM Write Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
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Signal Integrity Correlation Results
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 6:U3_B01.J1 (at die)
-200.0
400.0
800.0
1200.0
1600.0
2000.0
2400.0
Time (ps)
UG199_c7_28_071007
♦ 333 MHz, Fast, PRBS6, 88% UI
♦ Cursor 1: 1.1004V, 646.3 ps
♦ Cursor 2: 1.0273V, 1.9659 ns
♦ Delta Voltage = 73.1 mV, Delta Time = 1.3196 ns (88% UI)
Figure 7-28: DDR2 DIMM Write Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 6:U3_B01.J1 (at die)
95.000
105.000
115.000
125.000
135.000
145.000
Time (ns)
UG199_c7_29_071007
Figure 7-29: DDR2 DIMM Write Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
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Chapter 7: ML561 Hardware-Simulation Correlation
DDR2 DIMM Read Operation
This subsection shows the test results for the DDR2_DIMM_DQ_BY2_B3 signal from the
DDR2 DIMM (XP2) to FPGA2 (U5) measured at 333 MHz (667 Mb/s), where the unit
interval (UI) = 1.5 ns.
49.8 ohms
94.605 ps
0.606 in
DDR2_DIMM_DQ_...
49.8 ohms
90.340 ps
0.578 in
DDR2_DIMM_DQ_...
28.5 ohms
4.473 ps
0.028 in
49.8 ohms
90.955 ps
0.582 in
DDR2_DIMM_DQ_...
49.1 ohms
78.216 ps
0.501 in
49.1 ohms
41.316 ps
0.264 in
49.8 ohms
864.365 ps
5.533 in
DDR2_DIMM_DQ_...
71.6 ohms
22.319 ps
59.1 ohms
12.486 ps
AutoPadstk_12_B...
U5_B00.H29
AutoPadstk_3_B00 DDR2_DIMM_DQ_...
DDR2_DIMM_DQ_... DDR2_DIMM_DQ_...
59.8 ohms
3.590 ps
59.8 ohms
10.373 ps
0.064 in
59.8 ohms
31.503 ps
0.195 in
59.8 ohms
78.962 ps
0.490 in
0.022 in
U3_B01.J1
J1_B01.31
MDQ19_B01
DQ19_B01
MDQ19_B01 MDQ19_B01
TL15
TL16
TL17
TL18
TL19
TL20
TL7
TL6
TL3
RN6_B01
22.0 ohms
Virtex-5 FPGA
DIMM_DQ_BY2_B3
XP2_B00.31
XP3_B00.31
XP4_B00.31
XP5_B00.31
TL12
TL1
TL5
TL11
MT47H64M8CB_C...
DQ6
????
DDR2_DI...
22.9 fF
DDR2_DI...
96.3 fF
DDR2_DI...
253.0 fF
DDR2_DI...
46.4 fF
C8
TL14
TL27
TL23
TL25
????
50.3 ohms
23.650 ps
DDR2_D...
MDQ19_...
17.3 fF
????
C13
????
50.3 ohms
23.650 ps
DDR2_D...
????
50.3 ohms
23.650 ps
DDR2_D...
50.3 ohms
23.650 ps
DDR2_D...
500.0 fF
500.0 fF
R_00179...
0.0 milliohms
R7
R5
R6
0.0 milliohms
0.0 milliohms
0.0 milliohms
TL13
TL26
TL22
TL24
50.3 ohms
23.650 ps
DQ19_B...
50.3 ohms
23.650 ps
DQ19_B...
50.3 ohms
23.650 ps
DQ19_B...
50.3 ohms
23.650 ps
DQ19_B...
UG199_c7_30_071907
Figure 7-30: Post-Layout IBIS Schematics of the DDR2 DIMM Read Data Bit (DDR2_DIMM_DQ_B)
Table 7-9: Circuit Elements of DDR2 DIMM Read Data Bit
(DDR2_DIMM_DQ_BY2_B3)
Element
Designation
XP2-U3.J1
Description
Driver
DDR2 DIMM
Receiver
U5.H29
C8
FPGA SSTL18_II_DCI_I
Via under FPGA2 (U5.H29)
DCI at load
Probe Point
PCB Termination
Trace Length
None
Multiple TLs
8.975 inches
Table 7-10: DDR2 DIMM Read Operation Correlation Results
Noise Margin
(VIH + VIL) = Total
(% of VREF)
Overshoot / Undershoot
Margin
DVW (%
UI)
ISI
(% UI)
Measurement
(% of VREF)
904 ps
(60%)
Hardware at probe
point
(107 + 62) = 169 ps
(11.2%)
(623 + 613) = 1236 mV
(137.3%)
(242 + 258) = 500 mV
865 ps
(59%)
Simulation correlation
slow-weak corner
(130 + 83) = 213 ps
(14.2%)
(524 + 504) = 1028 mV
(114.2%)
(+292 + 298) = 590 mV
90 mV (10%)
Correlation Delta:
HW vs. Simulation
39 ps
(2.6%)
44 ps (2.9%)
208 mV (23.1%)
(243 + 303) = 546 mV
(60.7%)
(594 + 544) = 1138 mV
(116.5%)
Extrapolation at IOB
slow-weak corner
1.23 ns
(82%)
(139 + 75) = 224 ps
(14.9%)
Extrapolation at IOB
fast-strong corner
1.24 ns
(83%)
(131 + 60) = 191 ps
(12.7%)
(288 + 282) = 570 mV
(63.3%)
(+481 + 508) = 989 mV
(109.9%)
To perform hardware measurements for a Read operation that is not interrupted by a Write
or a Refresh operation, the testbench on FPGA1 is controlled by the following DIP switch
(SW1) setting:
•
DIP[1:2] = 2’b10– Write once, then Read only, Refresh disabled
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Signal Integrity Correlation Results
UG199_c7_31_071107
Figure 7-31: DDR2 DIMM Read HW Measurement - Eye Scope Shot at Probe Point (FPGA1 Via)
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
Probe 3:C8.1 (at pin)
-100.0
2000.0
2400.0
2800.0
3200.0
3600.0
Time (ps)
UG199_c7_32_071107
♦ 333 MHz, Slow, PRBS6, 59% UI
♦ Cursor 1: 1.0988V, 2.5207 ns
♦ Cursor 2: 1.0254V, 3.3859 ns
♦ Delta Voltage = 73.4 mV, Delta Time = 865.2 ps (59% UI)
Figure 7-32: DDR2 DIMM Read Correlation - Eye Scope Shot at Probe Point (Slow Corner)
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Chapter 7: ML561 Hardware-Simulation Correlation
UG199_c7_33_071107
Figure 7-33: DDR2 DIMM Read HW Measurement - Waveform Scope Shot at Probe Point (FPGA1 Via)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
Probe 3:C8.1 (at pin)
45.000
0.000
-200.0
25.000
35.000
55.000
65.000
75.000
Time (ns)
UG199_c7_34_071007
Figure 7-34: DDR2 DIMM Read Correlation - Waveform Scope Shot at Probe Point (Slow Corner)
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Signal Integrity Correlation Results
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
Probe 6:U5_B00.H29 (at die)
0.000
-200.0
2000.0
2400.0
2800.0
3200.0
3600.0
4000.0
Time (ps)
UG199_c7_35_071007
♦ 333 MHz, Slow, PRBS6, 82% UI
♦ Cursor 1: 1.1007V, 2.3997 ns
♦ Cursor 2: 1.0232V, 3.6257 ns
♦ Delta Voltage = 77.5 mV, Delta Time = 1.2260 ns (82% UI)
Figure 7-35: DDR2 DIMM Read Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 6:U5_B00.H29 (at die)
-200.0
30.000
40.000
50.000
60.000
70.000
Time (ns)
UG199_c7_36_071007
Figure 7-36: DDR2 DIMM Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
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1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
Probe 6:U5_B00.H29 (at die)
0.000
-200.0
400.0
800.0
1200.0
1600.0
2000.0
2400.0
Time (ps)
UG199_c7_37_071007
♦ 333 MHz, Fast, PRBS6, 83% UI
♦ Cursor 1: 697.0 mV, 763.0 ps
♦ Cursor 2: 776.6 mV, 2.0052 ns
♦ Delta Voltage = 79.5 mV, Delta Time = 1.2422 ns (83% UI)
Figure 7-37: DDR2 DIMM Read Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 6:U5_B00.H29 (at die)
-200.0
30.000
40.000
50.000
60.000
70.000
Time (ns)
UG199_c7_38_071007
Figure 7-38: DDR2 DIMM Read Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
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Signal Integrity Correlation Results
QDRII Write Operation
This subsection shows the test results for the QDR2_D_BY0_B5 signal from FPGA3 (U34)
to QDRII memory (U35) measured at 300 MHz (600 Mb/s), where the unit interval
(UI) = 167 ns.
49.0 ohms
5.283 ps
0.035 in
VCC0V7…
0.9V
QDR2_D_BY0_B5
R1586
49.9 ohms
TL6
49.8 ohms
28.5 ohms
4.473 ps
28.5 ohms
4.404 ps
0.027 in
49.0 ohms
45.1 ohms
7.862 ps
AutoPadstk_19
70.8 ohms
16.339 ps
AutoPadstk_3
520.665 ps
3.333 in
71.0 ohms
27.482 ps
11.902 ps
U34.M31
0.028 in
0.079 in
QDR2_D_BY0_B5
U35.G11
QDR2_D_BY0_B5
QDR2_D_BY0_B5
QDR2_D_BY0_B5 AutoPadstk_3
TL2
TL4
TL5
TL7
TL8
TL3
TL1
Virtex-5 FPGA
QDR2_D_BY0_B5
K7R323684M_1.8V
D5
QDR2_D...
C7
QDR2_D...
QDR2_D...
22.9 fF
QDR2_D...
22.9 fF
QDR2_D...
QDR2_D...
22.9 fF
177.3 fF
399.1 fF
500.0 fF
58.1 fF
UG199_c7_39_070907
Figure 7-39: Post-Layout IBIS Schematics of QDRII Write Data Bit (QDR2_D_BY0_B5)
Table 7-11: Circuit Elements of QDRII Write Data bit (QDR2_D_BY0_B5)
Element
Designation
U34.M31
Description
FPGA HSTL_I_18
Driver
Receiver
U35.G11
C7
QDRII memory
Probe Point
PCB Termination
Trace Length
Via under Memory
External termination at memory
3.46 inches
R1586
TL 2, 5, 8, 1
Table 7-12: QDRII Write Operation Correlation Results
Noise Margin
(VIH + VIL) = Total
(% of VREF)
Overshoot / Undershoot
Margin
DVW
(% UI)
ISI
(% UI)
Measurement
(% of VREF)
Hardware at probe
point
1.40 ns
(84.1%)
(340 + 400) = 740 mV
(82.2%)
(450 + 400) = 850 mV
(94.5%)
(50 + 70) = 120 ps (7.2%)
(136 + 91) = 227 ps (13.6%)
107 ps (6.4%)
Simulation correlation
slow-weak corner
1.39 ns
(83.5%)
(344 + 398) = 742 mV
(82.5%)
(483 + 452) = 935 mV
(103.9%)
Correlation Delta:
HW vs. Simulation
10 ps
(0.6%)
2 mV (0.3%)
85 mV (9.4%)
1.38 ns
(83%)
(172 + 141) = 313 ps
(18.8%)
Extrapolation at IOB
slow-weak corner
(329 + 358) = 687 mV
(76.3%)
(400 + 361) = 761 mV
(84.5%)
1.49 ns
(89%)
Extrapolation at IOB
fast-strong corner
(353 + 376) = 729 mV
(81.0%)
(156 + 30) = 186 mV
(20.7%)
(126 + 91) = 217 ps (13.0%)
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UG199_c7_40_071107
Figure 7-40: QDRII Write HW Measurement - Eye Scope Shot at Probe Point (QDRII Memory Via)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
Probe 3:C7.1 (at pin)
0.000
-200.0
0.000
400.0
800.0
1200.0
1600.0
Time (ps)
UG199_c7_41_070907
♦ 300 MHz, Slow, PRBS6, 83.5% UI
♦ Cursor 1: 699.1 mV, 90.0 ps
♦ Cursor 2: 801.0 mV, 1.4770 ns
♦ Delta Voltage = 101.9 mV, Delta Time = 1.3870 ns (83.5% UI)
Figure 7-41: QDRII Write Correlation - Eye Scope Shot at Probe Point (Slow Corner)
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Signal Integrity Correlation Results
UG199_c7_42_071107
Figure 7-42: QDRII Write HW Measurement - Waveform Scope Shot at Probe Point (QDRII Memory Via)
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
Probe 3:C7.1 (at pin)
-100.0
110.000
120.000
130.000
140.000
150.000
160.000
Time (ns)
UG199_c7_43_071007
Figure 7-43: QDRII Write Correlation - Waveform Scope Shot at Probe Point (Slow Corner)
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Chapter 7: ML561 Hardware-Simulation Correlation
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 6:U35.G11 (at die)
-200.0
0.000
400.0
800.0
1200.0
1600.0
Time (ps)
UG199_c7_44_070907
♦ 300 MHz, Slow, PRBS6, 83% UI
♦ Cursor 1: 699.1 mV, 61.3 ps
♦ Cursor 2: 801.0 mV, 1.4433 ns
♦ Delta Voltage = 101.9 mV, Delta Time = 1.3820 ns (83% UI)
Figure 7-44: QDRII Write Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
Probe 6:U35.G11 (at die)
-100.0
110.000
120.000
130.000
140.000
150.000
160.000
Time (ns)
UG199_c7_45_071007
Figure 7-45: QDRII Write Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
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Signal Integrity Correlation Results
3100.0
2600.0
2100.0
1600.0
1100.0
600.0
100.0
-400.0
-900.0
-1400.0
-1900.0
Probe 6:U35.G11 (at die)
800.0
1200.0
1600.0
2000.0
2400.0
2800.0
Time (ps)
UG199_c7_46_070907
♦ 300 MHz, Fast, PRBS6, 89% UI
♦ Cursor 1: 699.1 mV, 1.1440 ns
♦ Cursor 2: 801.0 mV, 2.6334 ns
♦ Delta Voltage = 101.9 mV, Delta Time = 1.4894 ns (89% UI)
Figure 7-46: QDRII Write Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
3400.0
2900.0
2400.0
1900.0
1400.0
900.0
400.0
-100.0
-600.0
-1100.0
Probe 6:U35.G11 (at die)
-1600.0
110.000
120.000
130.000
140.000
150.000
160.000
Time (ns)
UG199_c7_47_070907
Figure 7-47: QDRII Write Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
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Chapter 7: ML561 Hardware-Simulation Correlation
QDRII Read Operation
This subsection shows the test results for the QDR2_Q_BY0_B5 signal from QDRII
memory (U35) to FPGA3 (U34) measured at 300 MHz (600 Mb/s), where the unit interval
(UI) = 1.67 ns.
49.1 ohms
28.5 ohms
4.473 ps
49.1 ohms
28.5 ohms
4.404 ps
71.8 ohms
22.319 ps
AutoPad...
427.654 ps
2.737 in
71.6 ohms
22.319 ps
AutoPadstk_3
95.834 ps
0.028 in
0.613 in
QDR2_Q_BY0_B5
0.027 in
U35.F11
U34.G33
QDR2_Q_BY0_B5
QDR2_Q_BY0_B5
QDR2_Q_BY0_B5
TL3
TL6
TL7
TL8
TL1
TL2
K7R323684M_1.8V
C5
Virtex-5 FPGA
QDR2_Q_BY0_B5
QDR2_Q...
513.2 fF
QDR2_Q...
QDR2_Q...
22.9 fF
QDR2_Q...
96.3 fF
C7
QDR2_Q...
22.9 fF
96.3 fF
500.0 fF
UG199_c7_48_071907
Figure 7-48: Post-Layout IBIS Schematics of QDRII Read Data Bit (QDR2_Q_BY0_B5)
Table 7-13: Circuit Elements of QDRII Read Data Bit (QDR2_Q_BY0_B5)
Element
Designation
U36.F11
Description
QDRII memory
Driver
Receiver
U34.G33
C7
FPGA HSTL_I_DCI_18
Via under FPGA3 (U34)
DCI at FPGA
Probe Point
PCB Termination
Trace Length
None
TL 1, 3, 6, 8
3.41 inches
Table 7-14: QDRII Read Operation Correlation Results
Noise Margin
(VIH + VIL) = Total
(% of VREF)
Overshoot / Undershoot
Margin
DVW
(% UI)
ISI
(% UI)
Measurement
(% of VREF)
1.09 ns
(65.4%)
(400 + 400) = 800 mV
(88.9%)
(500 + 500) = 1000 mV
(111.1%)
Hardware at probe point
(70 + 50) = 120 ps (7.2%)
(72 + 75) = 147 ps (8.8%)
27 ps (1.6%)
984 ps
Simulation correlation
slow-weak corner
(250 + 264) = 514 mV
(57.1%)
(532 + 518) = 1050 mV
(105.5%)
(59.0%)
Correlation Delta:
HW vs. Simulation
106 ps
(6.4%)
386 mV (31.8%)
50 mV (5.6%)
1.46 ns
(88%)
Extrapolation at IOB
slow-weak corner
(237 + 272) = 509 mV
(56.5%)
(608 + 575) = 1183 mV
(131.5%)
(49 + 36) = 85 ps (5.1%)
1.45 ns
(87%)
Extrapolation at IOB
fast-strong corner
(341 +201) = 542 mV
(60.3%)
(532 + 661) = 1193 mV
(132.6%)
(27 + 39) = 66 ps (4.0%)
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Signal Integrity Correlation Results
UG199_c7_49_071107
Figure 7-49: QDRII Read HW Measurement - Eye Diagram Scope Shot at Probe Point (FPGA3 Via)
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
Probe 3:C7.1 (at pin)
0.000
-200.0
800.0
1200.0
1600.0
2000.0
2400.0
Time (ps)
UG199_c7_50_070907
♦ 300 MHz, Slow, PRBS6, 59% UI
♦ Cursor 1: 1.1007V, 1.4881 ns
♦ Cursor 2: 1.0029V, 2.4719 ns
♦ Delta Voltage = 97.9 mV, Delta Time = 983.8 ps (59% UI)
Figure 7-50: QDRII Read Correlation - Eye Diagram Scope Shot at Probe Point (Slow Corner)
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Chapter 7: ML561 Hardware-Simulation Correlation
UG199_c7_51_071107
Figure 7-51: QDRII Read HW Measurement - Waveform Scope Shot at Probe Point (FPGA3 Via)
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
Probe 3:C7.1 (at pin)
100.0
-100.0
20.000
30.000
40.000
50.000
60.000
70.000
Time (ns)
UG199_c7_52_071007
Figure 7-52: QDRII Read Correlation - Waveform Scope Shot at Probe Point (Slow Corner)
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Signal Integrity Correlation Results
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
Probe 6:U34.G33 (at die)
0.000
-200.0
1000.0
1400.0
1800.0
2200.0
2600.0
Time (ps)
UG199_c7_53_070907
♦ 300 MHz, Slow, PRBS6, 88% UI
♦ Cursor 1: 1.1008V, 1.2758 ns
♦ Cursor 2: 998.9 mV, 2.7352 ns
♦ Delta Voltage = 101.9 mV, Delta Time = 1.4594 ns (88% UI)
Figure 7-53: QDRII Read Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
Probe 6:U34.G33 (at die)
-100.0
30.000
40.000
50.000
60.000
70.000
Time (ns)
UG199_c7_54_071007
Figure 7-54: QDRII Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner
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Chapter 7: ML561 Hardware-Simulation Correlation
1800.0
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
200.0
0.000
Probe 6:U34.G33 (at die)
-200.0
1200.0
1600.0
2000.0
2400.0
2800.0
Time (ps)
UG199_c7_55_070907
♦ 300 MHz, Fast, PRBS6, 87% UI
♦ Cursor 1: 801 mV, 2.7263 ns
♦ Cursor 2: 697.0 mV, 1.2744 ns
♦ Delta Voltage = 104.0 mV, Delta Time = 1.4519 ns (87% UI)
Figure 7-55: QDRII Read Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
1900.0
1700.0
1500.0
1300.0
1100.0
900.0
700.0
500.0
300.0
100.0
Probe 6:U34.G33 (at die)
-100.0
25.000
35.000
45.000
55.000
65.000
75.000
Time (ns)
UG199_c7_56_071007
Figure 7-56: QDRII Read Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
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Summary and Recommendations
Summary and Recommendations
The first objective of this exercise is to establish correlation between hardware
measurements and the simulation at the probe point. The intention was to validate the
simulation model for the targeted signal. The degree of correlation achieved is looked at in
terms of absolute difference as well as relative percentage. The relative percentage
differences are presented in terms of unit interval (UI) for timing characteristics and in
terms of VREF voltage for the voltage margin characteristics.
Correlation simulation is performed under ideal conditions, that is, the stimulus is
generated without any jitter. On the other hand, the hardware measurements are subject to
jitter (which tends to increase ISI), board-level power fluctuation (which can affect the eye
amplitude), and stability of the probing station. Thus some correlation differences are
expected. The user ultimately uses his or her own judgment to account for these
differences, and adjusts the values extrapolated for quality of signal at the receiver IOB.
Table 7-15 contains this information for all six test signals.
Table 7-15: Summary of Correlation Differences: Hardware vs. Simulation
Overshoot /
Undershoot Margin
(% VREF)
ΔDVW
ΔISI
(% UI)
Noise Margin
(% VREF)
Operation
(% UI(1)
)
98 mV
69 mV
(7.6%)
40 ps
(2.6%)
47 ps
(3.2%)
DDR2 Component Write
DDR2 Component Read
DDR2 DIMM Write
DDR2 DIMM Read
QDRII Write
(10.9%)
0 ps
6 mV
244 mV
(17.2%)
43 ps
(2.9%)
(0%)
(0.7%)
112 mV
(12.6%)
2 mV
218 ps
(14.5%)
366 ps
(24.5%)
(0.3%)
90 mV
208 mV
(23.1%)
39 ps
(2.6%)
44 ps
(2.9%)
(10.0%)
2 mV
85 mV
(9.4%)
10 ps
(0.6%)
107 ps
(6.4%)
(0.3%)
386 mV
(31.8%)
50 mV
(5.6%)
106 ps
(6.4%)
27 ps
(1.6%)
QDRII Read
Notes:
1. Unit Interval (UI): 1.5 ns for DDR2 and 1.67 ns for QDRII. VREF = 0.9V for DDR2 and QDRII.
There are varying degrees of correlation differences among the six test signals. In general,
there is a good match between hardware measurements and the correlation simulation,
except for some yet-to-be analyzed differences, for example, DDR2 DIMM Write DVW and
QDRII read noise margin.
The remainder of this section summarizes the extrapolation results of the data bit interface
for all six memory operations on the ML561 board. The measure of SI characteristics of
each signal is determined by the worst-case extrapolation measurement from among the
simulations with drivers at slow-weak and fast-strong corners. The values chosen between
these two corner cases are:
•
•
Minimum of DVW, noise margin, and overshoot/undershoot margin
Maximum of ISI
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Chapter 7: ML561 Hardware-Simulation Correlation
Table 7-16 summarizes the extrapolated SI characteristics of all six test signals.
Table 7-16: Summary of Worst-Case SI Characteristics
Overshoot /
Undershoot Margin
(% VREF)
ΔDVW
(% UI)
ΔISI
(% UI)
Noise Margin
(% VREF)
Operation
127 ps
(8.5%)
570 mV
(63.3%)
685 mV
(76.1%)
1.27 ns
(84%)
DDR2 Component Write
DDR2 Component Read
DDR2 DIMM Write
DDR2 DIMM Read
QDRII Write
178 ps
867 mV
(96.3%)
349 mV
(38.9%)
1.29 ns
(86%)
(11.9%)
117 ps
(7.8%)
253 mV
(28.1%)
981 mV
1.23 ns
(82%)
(109.0%)
224 ps
546 mV
(60.7%)
989 mV
1.23 ns
(82%)
(14.9%)
(109.9%)
313 ps
687 mV
(76.3%)
186 mV
(20.7%)
1.38 ns
(83%)
(18.8%)
85 ps
509 mV
(56.5%)
1183 mV
(131.5%)
1.45 ns
(87%)
QDRII Read
(5.1%)
Here are some observations about extrapolated SI characteristics among these test signals:
•
•
The Data Valid Window (DVW) values already account for the degradation caused by
ISI due to the PRBS6 test pattern. For timing analysis, two values need to be taken into
consideration appropriately. For a PRBS6 test pattern, the worst-case DVW value
(after discounting for ISI) is 82% UI for DDR2 DIMM operations.
DDR2 write operations, as compared to QDRII write operations, have a lower noise
margin due to the always on nature of the DCI termination on the DQ signal for the
SSTL18_II_DCI I/O standard at the FPGA. Consequently, the overshoot/undershoot
margin for DDR2 write operations is higher than for QDRII write operations. The
DDR2 DIMM write operation has the lowest VIL noise margin of 107 mV.
•
•
For read operations, the sum of VIH and VIL noise margins beyond the AC value
specifications is at least 509 mV (56.6% of VREF). QDRII read operations have the
lowest VIL noise margin of 201 mV.
All six signals have positive values for overshoot and undershoot margins. QDRII
write operations have the lowest undershoot margin value of 30 mV.
except for a clarification for DDR2 ODT as “75 ohm ODT”.)
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How to Generate a User-Specific FPGA IBIS Model
How to Generate a User-Specific FPGA IBIS Model
The following steps indicate how to generate an IBIS model:
1. Under ISE, open your fully compiled project.
2. Go to the Tcl Shell tab, and issue an ibiswritercommand as:
ibiswriter –allmodels <your top level project design file>.ncd <name up
to 24 lowercase characters>.ibs ;
For example, ibiswriter –allmodels mem_interface_top.ncd
ml561_fpga3_u34.ibs
(under the “Device Models” sidebar link). Then unzip the ZIP file containing the
device package files and extract a package file for your device, for example,
ff1136_5vlx50t.pkg. Place this file in the same directory as the FPGA IBIS file (for
example, ml561_fpga3_u34.ibs).
4. Open the ml561_fpga3_u34.ibsfile generated by ibiswriter in HyperLynx Visual
IBIS Editor. Check the file for correctness by clicking on the check (9) button in the top
toolbar. Warnings are okay.
5. Open the ff1136_5vlx50t.pkgfile using a text editor and locate the [Define
Package Model]line. Copy and paste this line into the ml561_fpga3_u34.ibsfile
just above the line with the [Package]declaration. Edit the copied line to change
[Define Package Model]to [Package Model].
6. Again, check the file for correctness by clicking on the check (9) button in the top
toolbar. Multiple errors will appear. The package model file defines I/O definitions for
all usable pins, but now ibiswriter only declares pins defined under the UCF. Thus
errors are displayed for all the undefined pins, for example:
ERROR - Pin 'AK9' found in Package_Model 'ff1136_xc5vlx50t_fga0106_dc' Pin_Numbers
list not found in Component 'VIRTEX-5' Pin list.
7. Copy all these errors into a text file with a .txtfile type.
♦
Open this text file with Excel and provide the delimiter as (‘), which puts all the
unused pin names in one column. Delete all other columns before and after the
one with the pin names.
♦
♦
In column 2, fill in Unused_IOfor all pins.
In column 3, fill in the name of one of the I/O standards defined under the
[Model] section of the ml561_fpga3_u34.ibsfile, for example,
LVCMOS25_S_12. Choose a name that is not an output only standard, because it
might conflict with other outputs in the same bank.
♦
♦
Right-justify the indentation for all three columns and make sure that each
column is wider by a few spaces than the longest string in that column.
Save this file with the Save As command in Excel using the Formatted Text (space
delimited) (*.prn) option to create a text file with text columns separated by
spaces. (The IBIS checker gives a warning if the .ibsfile contains tabs.)
8. Open the .prnfile with a text editor and copy all these lines to the .ibsfile at the end
of the [Pin]definitions section (just above the [Diff Pin]declarations).
9. Check (9) the .ibsfile again. There should not be any errors. Again, warnings are
okay.
10. The result is an accurate custom-made IBIS model of a Virtex-5 device specific to your
design.
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Chapter 7: ML561 Hardware-Simulation Correlation
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Appendix A
FPGA Pinouts
This appendix provides the pinouts for the three FPGAs on the Virtex-5 FPGA ML561
Development Board. The toolkit CD shipped with every ML561 contains sample UCFs for
each memory interface. These UCFs are for pinout reference only and do not include other
constraints, like I/O standards.
FPGA #1 Pinout
Table A-1 lists the connections for FPGA #1 (U7).
Table A-1: FPGA #1 Pinout
Signal Name
Pin
Signal Name
Pin
DDR400 Component Interface
DDR1_A0
DDR1_A1
M32
L33
E33
E32
E34
DDR1_CK1_N
DDR1_CK1_P
DDR1_CK2_N
DDR1_CK2_P
DDR1_CKE
AJ34
AH34
AE34
AF34
AC34
N32
DDR1_A10
DDR1_A11
DDR1_A12
DDR1_A13
DDR1_A2
F33
K32
DDR1_LB_BK11
DDR1_LB_BK11
DDR1_LB_BK13
DDR1_LB_BK13
DDR1_RAS_N
P32
DDR1_A3
K34
AJ32
AK32
AB32
AD34
AG32
Y32
DDR1_A4
L34
DDR1_A5
J34
DDR1_A6
H34
H33
F34
DDR1_WE_N
DDR1_A7
DDR1_DM_BY0
DDR1_DM_BY1
DDR1_DM_BY2
DDR1_DM_BY3
DDR1_DQ_BY0_B0
DDR1_DQ_BY0_B1
DDR1_DQ_BY0_B2
DDR1_DQ_BY0_B3
DDR1_A8
DDR1_A9
G33
P34
DDR1_BA0
DDR1_BA1
DDR1_BY0_1_CS_N
DDR1_BY2_3_CS_N
DDR1_CAS_N
AK33
AK34
AB33
AC33
AC32
G32
AP32
AN32
AN33
AN34
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Appendix A: FPGA Pinouts
Table A-1: FPGA #1 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
DDR400 Component Interface (cont.)
DDR1_DQ_BY0_B4
DDR1_DQ_BY0_B5
DDR1_DQ_BY0_B6
DDR1_DQ_BY0_B7
DDR1_DQ_BY1_B0
DDR1_DQ_BY1_B1
DDR1_DQ_BY1_B2
DDR1_DQ_BY1_B3
DDR1_DQ_BY1_B4
DDR1_DQ_BY1_B5
DDR1_DQ_BY1_B6
DDR1_DQ_BY1_B7
DDR1_DQ_BY2_B0
DDR1_DQ_BY2_B1
DDR1_DQ_BY2_B2
DDR1_DQ_BY2_B3
AM32
AM33
AL33
AL34
Y34
DDR1_DQ_BY2_B4
R32
R33
R34
T33
DDR1_DQ_BY2_B5
DDR1_DQ_BY2_B6
DDR1_DQ_BY2_B7
DDR1_DQ_BY3_B0
DDR1_DQ_BY3_B1
DDR1_DQ_BY3_B2
DDR1_DQ_BY3_B3
DDR1_DQ_BY3_B4
DDR1_DQ_BY3_B5
DDR1_DQ_BY3_B6
DDR1_DQ_BY3_B7
DDR1_DQS_BY0_P
DDR1_DQS_BY1_P
DDR1_DQS_BY2_P
DDR1_DQS_BY3_P
D34
C34
D32
C32
C33
B33
AA34
AA33
Y33
V34
W34
V33
A33
B32
V32
U31
AD32
AF33
K33
J32
U32
T34
U33
DDR2 Component Interface
DDR2_A0
DDR2_A1
DDR2_A10
DDR2_A11
DDR2_A12
DDR2_A2
DDR2_A3
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
DDR2_A8
DDR2_A9
DDR2_BA0
DDR2_BA1
K12
K13
G22
J15
DDR2_CAS_N
DDR2_CK0_N
DDR2_CK0_P
DDR2_CK1_N
DDR2_CK1_P
DDR2_CKE
J14
K19
L19
J19
K16
H23
G23
H12
J12
K18
K17
H20
H19
T28
T29
M28
N28
H18
H17
H13
DDR2_CS0_N
DDR2_CS1_N
DDR2_LB_BK15
DDR2_LB_BK15
DDR2_LB_BK19
DDR2_LB_BK19
DDR2_ODT0
K22
K23
K14
L14
K21
J22
DDR2_ODT1
DDR2_RAS_N
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FPGA #1 Pinout
Table A-1: FPGA #1 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
DDR2 Component Interface (cont.)
DDR2_WE_N
DDR2_DM_BY0
J21
U30
L29
K27
J27
DDR2_DQ_BY2_B2
N25
P25
P24
N24
P27
P26
M26
M25
J25
DDR2_DQ_BY2_B3
DDR2_DQ_BY2_B4
DDR2_DQ_BY2_B5
DDR2_DQ_BY2_B6
DDR2_DQ_BY2_B7
DDR2_DQ_BY3_B0
DDR2_DQ_BY3_B1
DDR2_DQ_BY3_B2
DDR2_DQ_BY3_B3
DDR2_DQ_BY3_B4
DDR2_DQ_BY3_B5
DDR2_DQ_BY3_B6
DDR2_DQ_BY3_B7
DDR2_DQS_BY0_N
DDR2_DQS_BY0_P
DDR2_DQS_BY1_N
DDR2_DQS_BY1_P
DDR2_DQS_BY2_N
DDR2_DQS_BY2_P
DDR2_DQS_BY3_N
DDR2_DQS_BY3_P
DDR2_DM_BY1
DDR2_DM_BY2
DDR2_DM_BY3
DDR2_DQ_BY0_B0
DDR2_DQ_BY0_B1
DDR2_DQ_BY0_B2
DDR2_DQ_BY0_B3
DDR2_DQ_BY0_B4
DDR2_DQ_BY0_B5
DDR2_DQ_BY0_B6
DDR2_DQ_BY0_B7
DDR2_DQ_BY1_B0
DDR2_DQ_BY1_B1
DDR2_DQ_BY1_B2
DDR2_DQ_BY1_B3
DDR2_DQ_BY1_B4
DDR2_DQ_BY1_B5
DDR2_DQ_BY1_B6
DDR2_DQ_BY1_B7
DDR2_DQ_BY2_B0
DDR2_DQ_BY2_B1 23
T25
U25
T26
U26
R27
R26
U28
U27
E31
F31
J29
J24
L26
L25
L24
K24
N30
M31
P29
N29
E27
E26
H27
G27
H29
F30
G30
F29
E29
T24
R24
FPGA #1 Clock and Reset Signals
CLK_TO_FPGA1_MGT_116_N
CLK_TO_FPGA1_MGT_116_P
CLK_TO_FPGA1_MGT_118_N
CLK_TO_FPGA1_MGT_118_P
DIRECT_CLK_TO_FPGA1_N
H3
H4
DIRECT_CLK_TO_FPGA1_P
AG22
AG13
AH12
AH20
AH14
EXT_CLK_TO_FPGA1_N
EXT_CLK_TO_FPGA1_P
FPGA1_LOW_FREQ_CLK
FPGA1_RESET_N
AF3
AF4
AH22
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Appendix A: FPGA Pinouts
Table A-1: FPGA #1 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
FPGA #1 MII Link Interface
FPGA2_TO_FPGA1_MII_TX_CLK
FPGA2_TO_FPGA1_MII_TX_DATA0
FPGA2_TO_FPGA1_MII_TX_DATA1
FPGA2_TO_FPGA1_MII_TX_DATA2
FPGA2_TO_FPGA1_MII_TX_DATA3
FPGA2_TO_FPGA1_MII_TX_EN
FPGA2_TO_FPGA1_MII_TX_ERR
FPGA2_TO_FPGA1_MII_TX_SPARE
J10
C13
B13
K9
FPGA3_TO_FPGA1_MII_TX_CLK
FPGA3_TO_FPGA1_MII_TX_DATA0
FPGA3_TO_FPGA1_MII_TX_DATA1
FPGA3_TO_FPGA1_MII_TX_DATA2
FPGA3_TO_FPGA1_MII_TX_DATA3
FPGA3_TO_FPGA1_MII_TX_EN
FPGA3_TO_FPGA1_MII_TX_ERR
FPGA3_TO_FPGA1_MII_TX_SPARE
D10
H10
C12
D12
J11
K8
L11
L10
J9
A13
H9
K11
FPGA #1 Configuration Signals
FPGA_INIT
FPGA_PROGB
FPGA_TMS
N14
M22
FPGA1_D_IN
P15
M15
FPGA1_DONE
FPGA1_DOUT_B
FPGA1_HSWAPEN
FPGA1_TCK
AC14
L23
AD15
M23
FPGA_VBATT
FPGA1_CCLK
N15
AB15
AC15
AD14
FPGA1_CNFG_M0
FPGA1_CNFG_M1
FPGA1_CNFG_M2
AD21
AC22
AD22
FPGA1_TDI_IN
FPGA1_TDO 15
FPGA #1 Test and Debug Signals
FPGA1_DIP0
AG18
AG15
AH15
AG20
AF26
H8
FPGA1_TEST_HDR_BY0_B6
E8
E9
FPGA1_DIP1
FPGA1_TEST_HDR_BY0_B7
FPGA1_TEST_HDR_BY1_B0
FPGA1_TEST_HDR_BY1_B1
FPGA1_TEST_HDR_BY1_B2
FPGA1_TEST_HDR_BY1_B3
FPGA1_TEST_HDR_BY1_B4
FPGA1_TEST_HDR_BY1_B5
FPGA1_TEST_HDR_BY1_B6
FPGA1_TEST_HDR_BY1_B7
FPGA1_DIP2
E12
L9
FPGA1_DIP3
FPGA1_SPYHOLE_BK21
FPGA1_TEST_HDR_BY0_B0
FPGA1_TEST_HDR_BY0_B1
FPGA1_TEST_HDR_BY0_B2
FPGA1_TEST_HDR_BY0_B3
FPGA1_TEST_HDR_BY0_B4
FPGA1_TEST_HDR_BY0_B5
M10
E11
F11
L8
G8
G10
F10
M8
G12
F8
F9
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FPGA #1 Pinout
Table A-1: FPGA #1 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
FPGA #1 Test Display Signals
FPGA1_7SEG_0_N
FPGA1_7SEG_1_N
FPGA1_7SEG_2_N
FPGA1_7SEG_3_N
FPGA1_7SEG_4_N
FPGA1_7SEG_5_N
AG17
AH18
AE18
AF18
AG16
AH17
FPGA1_7SEG_6_N
FPGA1_7SEG_DP_N
FPGA1_LED0
AF19
AG21
AD19
AE19
AE17
AF16
FPGA1_LED1
FPGA1_LED2
FPGA1_LED3
FPGA #1 External Interfaces
FPGA1_LCD_BL_ON
FPGA1_LCD_CSB
FPGA1_LCD_DB0
FPGA1_LCD_DB1
FPGA1_LCD_DB2
FPGA1_LCD_DB3
FPGA1_LCD_DB4
FPGA1_LCD_DB5
FPGA1_LCD_DB6
FPGA1_LCD_DB7
FPGA1_USB_CTS_N
FPGA1_USB_DSR_N
FPGA1_USB_DTR_N
FPGA1_USB_RST_N
M6
FPGA1_LCD_E
M5
N8
L6
M7
K6
K7
P6
FPGA1_LCD_R_WB
FPGA1_LCD_RESET_N
FPGA1_LCD_RS
N7
R11
G5
P9
FPGA1_RS232_CTS
FPGA1_RS232_RTS
FPGA1_RS232_RX
FPGA1_RS232_TX
FPGA1_TXN0_BK124
FPGA1_TXP0_BK124
FPGA1_USB_RTS_N
FPGA1_USB_RX
P7
L5
L4
H5
B9
P5
N5
G6
E6
B10
G7
T9
E7
FPGA1_USB_SUSPEND
FPGA1_USB_TX
T11
U10
T10
FPGA #1 Voltage Margining Interface
VMARGIN_DN_3V3_N
VMARGIN_DN_HSTL_N
VMARGIN_DN_SSTL18_N
VMARGIN_DN_SSTL2_N
VMARGIN_DN_VCC1V0_N
VMARGIN_DN_VCC2V5_N
AE22
AE13
AF13
AF23
AF20
AE14
VMARGIN_UP_3V3_N
AE23
AE12
AG12
AG23
AF21
AF14
VMARGIN_UP_HSTL_N
VMARGIN_UP_SSTL18_N
VMARGIN_UP_SSTL2_N
VMARGIN_UP_VCC1V0_N
VMARGIN_UP_VCC2V5_N
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Appendix A: FPGA Pinouts
FPGA #2 Pinout
Table A-2 lists the connections for FPGA #2 (U5).
Table A-2: FPGA #2 Pinout
Signal Name
Pin
Signal Name
Pin
DDR2 DIMM Deep Interface
DDR2_DIMM_A0
DDR2_DIMM_A1
AG30
AH29
AF31
AC29
AD30
AA30
AA29
AC30
AH30
AJ30
AF30
AF29
AK31
AJ31
AD29
AE29
AB30
AA31
AB31
V29
DDR2_DIMM1_CK0_N
DDR2_DIMM1_CK0_P
DDR2_DIMM1_CK1_N
DDR2_DIMM1_CK1_P
DDR2_DIMM1_CK2_N
DDR2_DIMM1_CK2_P
DDR2_DIMM1_CKE0
DDR2_DIMM1_CKE1
DDR2_DIMM1_CS0_N
DDR2_DIMM1_CS1_N
DDR2_DIMM1_ODT0
DDR2_DIMM1_ODT1
DDR2_DIMM2_CK0_N
DDR2_DIMM2_CK0_P
DDR2_DIMM2_CK1_N
DDR2_DIMM2_CK1_P
DDR2_DIMM2_CK2_N
DDR2_DIMM2_CK2_P
DDR2_DIMM2_CKE0
DDR2_DIMM2_CKE1
DDR2_DIMM2_CS0_N
DDR2_DIMM2_CS1_N
DDR2_DIMM2_ODT0
DDR2_DIMM2_ODT1
DDR2_DIMM3_CK0_N
DDR2_DIMM3_CK0_P
DDR2_DIMM3_CK1_N
DDR2_DIMM3_CK1_P
DDR2_DIMM3_CK2_N
M26
M25
J25
DDR2_DIMM_A10
DDR2_DIMM_A11
J24
DDR2_DIMM_A12
L26
DDR2_DIMM_A13
L25
DDR2_DIMM_A14
G28
DDR2_DIMM_A15
H28
DDR2_DIMM_A2
V27
DDR2_DIMM_A3
V28
DDR2_DIMM_A4
H24
DDR2_DIMM_A5
H25
DDR2_DIMM_A6
AF26
AF25
AG25
AF24
AJ26
AH27
AE24
AD24
W27
Y27
DDR2_DIMM_A7
DDR2_DIMM_A8
DDR2_DIMM_A9
DDR2_DIMM_BA0
DDR2_DIMM_BA1
DDR2_DIMM_BA2
DDR2_DIMM_CAS_N
DDR2_DIMM_LB_BK11_IN
DDR2_DIMM_LB_BK11_OUT
DDR2_DIMM_LB_BK13_IN
DDR2_DIMM_LB_BK13_OUT
DDR2_DIMM_LB_BK15_IN
DDR2_DIMM_LB_BK15_OUT
DDR2_DIMM_RAS_N
DDR2_DIMM_RESET_N
DDR2_DIMM_WE_N
P32
H33
AJ32
AK32
T28
AE26
AE27
AA24
Y24
T29
Y28
AC27
AB27
AA26
Y29
W29
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FPGA #2 Pinout
Table A-2: FPGA #2 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
DDR2 DIMM Deep Interface (cont.)
DDR2_DIMM3_CK2_P
DDR2_DIMM3_CKE0
DDR2_DIMM3_CKE1
DDR2_DIMM3_CS0_N
DDR2_DIMM3_CS1_N
DDR2_DIMM3_ODT0
DDR2_DIMM3_ODT1
DDR2_DIMM4_CK0_N
DDR2_DIMM4_CK0_P
DDR2_DIMM4_CK1_N
DDR2_DIMM4_CK1_P
DDR2_DIMM4_CK2_N
DDR2_DIMM4_CK2_P
DDR2_DIMM4_CKE0
DDR2_DIMM4_CKE1
DDR2_DIMM4_CS0_N
DDR2_DIMM4_CS1_N
DDR2_DIMM4_ODT0
DDR2_DIMM4_ODT1
DDR2_DIMM_DM_BY0
DDR2_DIMM_DM_BY1
DDR2_DIMM_DM_BY2
DDR2_DIMM_DM_BY3
DDR2_DIMM_DM_BY4
DDR2_DIMM_DM_BY5
DDR2_DIMM_DM_BY6
DDR2_DIMM_DM_BY7
DDR2_DIMM_DM_CB0_7
DDR2_DIMM_DQ_BY0_B0
DDR2_DIMM_DQ_BY0_B1
DDR2_DIMM_DQ_BY0_B2
DDR2_DIMM_DQ_BY0_B3
AA25
AE28
AH28
W25
V25
DDR2_DIMM_DQ_BY0_B4
R27
R26
U28
U27
N29
M30
L30
J31
DDR2_DIMM_DQ_BY0_B5
DDR2_DIMM_DQ_BY0_B6
DDR2_DIMM_DQ_BY0_B7
DDR2_DIMM_DQ_BY1_B0
DDR2_DIMM_DQ_BY1_B1
DDR2_DIMM_DQ_BY1_B2
DDR2_DIMM_DQ_BY1_B3
DDR2_DIMM_DQ_BY1_B4
DDR2_DIMM_DQ_BY1_B5
DDR2_DIMM_DQ_BY1_B6
DDR2_DIMM_DQ_BY1_B7
DDR2_DIMM_DQ_BY2_B0
DDR2_DIMM_DQ_BY2_B1
DDR2_DIMM_DQ_BY2_B2
DDR2_DIMM_DQ_BY2_B3
DDR2_DIMM_DQ_BY2_B4
DDR2_DIMM_DQ_BY2_B5
DDR2_DIMM_DQ_BY2_B6
DDR2_DIMM_DQ_BY2_B7
DDR2_DIMM_DQ_BY3_B0
DDR2_DIMM_DQ_BY3_B1
DDR2_DIMM_DQ_BY3_B2
DDR2_DIMM_DQ_BY3_B3
DDR2_DIMM_DQ_BY3_B4
DDR2_DIMM_DQ_BY3_B5
DDR2_DIMM_DQ_BY3_B6
DDR2_DIMM_DQ_BY3_B7
DDR2_DIMM_DQ_BY4_B0
DDR2_DIMM_DQ_BY4_B1
DDR2_DIMM_DQ_BY4_B2
DDR2_DIMM_DQ_BY4_B3
AB26
AB25
AK9
AK8
AJ11
AK11
AD11
AD10
AG11
AG10
W26
Y26
J30
G31
H30
L29
E31
F31
J29
H29
F30
G30
F29
E29
J32
AE11
AF11
U30
R31
T31
F34
G33
E33
E32
E34
F33
G32
Y34
AA34
AA33
Y33
L33
AK34
AG32
P34
AK33
M32
T25
U25
T26
U26
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Appendix A: FPGA Pinouts
Table A-2: FPGA #2 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
DDR2 DIMM Deep Interface (cont.)
DDR2_DIMM_DQ_BY4_B4
DDR2_DIMM_DQ_BY4_B5
DDR2_DIMM_DQ_BY4_B6
DDR2_DIMM_DQ_BY4_B7
DDR2_DIMM_DQ_BY5_B0
DDR2_DIMM_DQ_BY5_B1
DDR2_DIMM_DQ_BY5_B2
DDR2_DIMM_DQ_BY5_B3
DDR2_DIMM_DQ_BY5_B4
DDR2_DIMM_DQ_BY5_B5
DDR2_DIMM_DQ_BY5_B6
DDR2_DIMM_DQ_BY5_B7
DDR2_DIMM_DQ_BY6_B0
DDR2_DIMM_DQ_BY6_B1
DDR2_DIMM_DQ_BY6_B2
DDR2_DIMM_DQ_BY6_B3
DDR2_DIMM_DQ_BY6_B4
DDR2_DIMM_DQ_BY6_B5
DDR2_DIMM_DQ_BY6_B6
DDR2_DIMM_DQ_BY6_B7
DDR2_DIMM_DQ_BY7_B0
DDR2_DIMM_DQ_BY7_B1
DDR2_DIMM_DQ_BY7_B2
DDR2_DIMM_DQ_BY7_B3
DDR2_DIMM_DQ_BY7_B4
DDR2_DIMM_DQ_BY7_B5
DDR2_DIMM_DQ_BY7_B6
V34
W34
V33
DDR2_DIMM_DQ_BY7_B7
Y32
D34
C34
D32
C32
C33
B33
DDR2_DIMM_DQ_CB0_7_B0
DDR2_DIMM_DQ_CB0_7_B1
DDR2_DIMM_DQ_CB0_7_B2
DDR2_DIMM_DQ_CB0_7_B3
DDR2_DIMM_DQ_CB0_7_B4
DDR2_DIMM_DQ_CB0_7_B5
DDR2_DIMM_DQ_CB0_7_B6
DDR2_DIMM_DQ_CB0_7_B7
DDR2_DIMM_DQS_BY0_L_N
DDR2_DIMM_DQS_BY0_L_P
DDR2_DIMM_DQS_BY1_L_N
DDR2_DIMM_DQS_BY1_L_P
DDR2_DIMM_DQS_BY2_L_N
DDR2_DIMM_DQS_BY2_L_P
DDR2_DIMM_DQS_BY3_L_N
DDR2_DIMM_DQS_BY3_L_P
DDR2_DIMM_DQS_BY4_L_N
DDR2_DIMM_DQS_BY4_L_P
DDR2_DIMM_DQS_BY5_L_N
DDR2_DIMM_DQS_BY5_L_P
DDR2_DIMM_DQS_BY6_L_N
DDR2_DIMM_DQS_BY6_L_P
DDR2_DIMM_DQS_BY7_L_N
DDR2_DIMM_DQS_BY7_L_P
DDR2_DIMM_DQS_CB0_7_L_N
DDR2_DIMM_DQS_CB0_7_L_P
V32
AP32
AN32
AN33
AN34
AM32
AM33
AL33
AL34
U31
A33
B32
N30
M31
P30
P31
U32
L31
T34
K31
J34
U33
R32
H34
AE34
AF34
AE32
AD32
K32
K33
AJ34
AH34
K34
L34
R33
R34
T33
AF33
AB33
AC33
AB32
AC32
AD34
AC34
DDR2 DIMM Wide Interface
DDR2_DIMM5_CK0_N
DDR2_DIMM5_CK0_P
DDR2_DIMM5_CK1_N
DDR2_DIMM5_CK1_P
AM13
AN13
AA10
AB10
DDR2_DIMM5_CK2_N
AP14
AN14
AC10
AM11
DDR2_DIMM5_CK2_P
DDR2_DIMM5_CKE0
DDR2_DIMM5_CKE1
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FPGA #2 Pinout
Table A-2: FPGA #2 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
DDR2 DIMM Wide Interface (cont.)
DDR2_DIMM5_CS0_N
DDR2_DIMM5_CS1_N
V24
W24
AA9
AA8
F5
DDR2_DIMM_DQ_BY11_B5
G6
T11
T10
J6
DDR2_DIMM_DQ_BY11_B6
DDR2_DIMM_DQ_BY11_B7
DDR2_DIMM_DQ_BY12_B0
DDR2_DIMM_DQ_BY12_B1
DDR2_DIMM_DQ_BY12_B2
DDR2_DIMM_DQ_BY12_B3
DDR2_DIMM_DQ_BY12_B4
DDR2_DIMM_DQ_BY12_B5
DDR2_DIMM_DQ_BY12_B6
DDR2_DIMM_DQ_BY12_B7
DDR2_DIMM_DQ_BY13_B0
DDR2_DIMM_DQ_BY13_B1
DDR2_DIMM_DQ_BY13_B2
DDR2_DIMM_DQ_BY13_B3
DDR2_DIMM_DQ_BY13_B4
DDR2_DIMM_DQ_BY13_B5
DDR2_DIMM_DQ_BY13_B6
DDR2_DIMM_DQ_BY13_B7
DDR2_DIMM_DQ_BY14_B0
DDR2_DIMM_DQ_BY14_B1
DDR2_DIMM_DQ_BY14_B2
DDR2_DIMM_DQ_BY14_B3
DDR2_DIMM_DQ_BY14_B4
DDR2_DIMM_DQ_BY14_B5
DDR2_DIMM_DQ_BY14_B6
DDR2_DIMM_DQ_BY14_B7
DDR2_DIMM_DQ_BY15_B0
DDR2_DIMM_DQ_BY15_B1
DDR2_DIMM_DQ_BY15_B2
DDR2_DIMM_DQ_BY15_B3
DDR2_DIMM_DQ_BY15_B4
DDR2_DIMM5_ODT0
DDR2_DIMM5_ODT1
DDR2_DIMM_LB_BK12
DDR2_DIMM_LB_BK12
DDR2_DIMM_LB_BK18
DDR2_DIMM_LB_BK18
DDR2_DIMM_LB_BK20
DDR2_DIMM_LB_BK20
DDR2_DIMM_DM_BY10
DDR2_DIMM_DM_BY11
DDR2_DIMM_DM_BY12
DDR2_DIMM_DM_BY13
DDR2_DIMM_DM_BY14
DDR2_DIMM_DM_BY15
DDR2_DIMM_DM_BY8
DDR2_DIMM_DM_BY9
DDR2_DIMM_DM_CB8_15
DDR2_DIMM_DQ_BY10_B0
DDR2_DIMM_DQ_BY10_B1
DDR2_DIMM_DQ_BY10_B2
DDR2_DIMM_DQ_BY10_B3
DDR2_DIMM_DQ_BY10_B4
DDR2_DIMM_DQ_BY10_B5
DDR2_DIMM_DQ_BY10_B6
DDR2_DIMM_DQ_BY10_B7
DDR2_DIMM_DQ_BY11_B0
DDR2_DIMM_DQ_BY11_B1
DDR2_DIMM_DQ_BY11_B2
DDR2_DIMM_DQ_BY11_B3
DDR2_DIMM_DQ_BY11_B4
T6
F6
R6
W10
Y6
K6
K7
E11
F11
G11
R11
G5
P6
P7
L4
AD7
AC7
AB5
AA5
AB7
AB6
AC5
AC4
V9
Y11
AH7
W11
M8
G12
H5
H8
G8
V10
AK6
AK7
U8
G10
F10
F8
F9
V8
E8
AJ6
AJ7
W6
AE6
AD6
Y7
E9
E7
E6
U10
T9
G7
AA6
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Appendix A: FPGA Pinouts
Table A-2: FPGA #2 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
DDR2 DIMM Wide Interface (cont.)
DDR2_DIMM_DQ_BY15_B5
DDR2_DIMM_DQ_BY15_B6
DDR2_DIMM_DQ_BY15_B7
DDR2_DIMM_DQ_BY8_B0
DDR2_DIMM_DQ_BY8_B1
DDR2_DIMM_DQ_BY8_B2
DDR2_DIMM_DQ_BY8_B3
DDR2_DIMM_DQ_BY8_B4
DDR2_DIMM_DQ_BY8_B5
DDR2_DIMM_DQ_BY8_B6
DDR2_DIMM_DQ_BY8_B7
DDR2_DIMM_DQ_BY9_B0
DDR2_DIMM_DQ_BY9_B1
DDR2_DIMM_DQ_BY9_B2
DDR2_DIMM_DQ_BY9_B3
DDR2_DIMM_DQ_BY9_B4
DDR2_DIMM_DQ_BY9_B5
DDR2_DIMM_DQ_BY9_B6
DDR2_DIMM_DQ_BY9_B7
DDR2_DIMM_DQ_CB8_15_B0 20
DDR2_DIMM_DQ_CB8_15_B1
DDR2_DIMM_DQ_CB8_15_B2
DDR2_DIMM_DQ_CB8_15_B3
AD5
AD4
Y8
DDR2_DIMM_DQ_CB8_15_B4
N7
N8
M5
M6
J9
DDR2_DIMM_DQ_CB8_15_B5
DDR2_DIMM_DQ_CB8_15_B6
DDR2_DIMM_DQ_CB8_15_B7
DDR2_DIMM_DQS_BY10_L_N
DDR2_DIMM_DQS_BY10_L_P
DDR2_DIMM_DQS_BY11_L_N
DDR2_DIMM_DQS_BY11_L_P
DDR2_DIMM_DQS_BY12_L_N
DDR2_DIMM_DQS_BY12_L_P
DDR2_DIMM_DQS_BY13_L_N
DDR2_DIMM_DQS_BY13_L_P
DDR2_DIMM_DQS_BY14_L_N
DDR2_DIMM_DQS_BY14_L_P
DDR2_DIMM_DQS_BY15_L_N
DDR2_DIMM_DQS_BY15_L_P
DDR2_DIMM_DQS_BY8_L_N
DDR2_DIMM_DQS_BY8_L_P
DDR2_DIMM_DQS_BY9_L_N
DDR2_DIMM_DQS_BY9_L_P
DDR2_DIMM_DQS_CB8_15_L_N
DDR2_DIMM_DQS_CB8_15_L_P
G13
F13
N9
J10
J7
N10
E13
E12
L9
H7
U7
T8
M10
A13
H9
AF6
AE7
V7
H10
C12
D12
J11
W7
AF5
AG5
C13
B13
K9
K11
D11
P5
K8
N5
R8
L6
R7
M7
DDR2 DIMM Miscellaneous Signals
DDR2_DIMM1_CNTL_PAR
DDR2_DIMM1_CNTL_PAR_ERR
DDR2_DIMM1_NC_019
G27
H27
DDR2_DIMM3_CNTL_PAR
AA28
AG28
AK29
AJ29
AG8
DDR2_DIMM3_CNTL_PAR_ERR
DDR2_DIMM3_NC_019
K24
DDR2_DIMM1_NC_102
L24
DDR2_DIMM3_NC_102
DDR2_DIMM2_CNTL_PAR
DDR2_DIMM2_CNTL_PAR_ERR
DDR2_DIMM2_NC_019
AD26
AD25
AK28
AK27
DDR2_DIMM4_CNTL_PAR
DDR2_DIMM4_CNTL_PAR_ERR
DDR2_DIMM4_NC_019
AH8
AL10
AE8
DDR2_DIMM2_NC_102
DDR2_DIMM4_NC_102
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FPGA #2 Pinout
Table A-2: FPGA #2 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
DDR2 DIMM Miscellaneous Signals (cont.)
DDR2_DIMM5_CNTL_PAR
DDR2_DIMM5_CNTL_PAR_ERR
DDR2_DIMM5_NC_019
DDR2_DIMM5_NC_102
DDR2_DIMM_SCL
AB8
AM12
AC9
AL11
W31
Y31
DDR2_DIMM2_SA2
N24
P27
P26
N28
K27
L28
K28
E26
F28
E28
DDR2_DIMM3_SA0
DDR2_DIMM3_SA1
DDR2_DIMM3_SA2
DDR2_DIMM4_SA0
DDR2_DIMM4_SA1
DDR2_DIMM4_SA2
DDR2_DIMM5_SA0
DDR2_DIMM5_SA1
DDR2_DIMM5_SA2
DDR2_DIMM_SDA
DDR2_DIMM1_SA0
T24
DDR2_DIMM1_SA1
R24
DDR2_DIMM1_SA2
N25
P25
DDR2_DIMM2_SA0
DDR2_DIMM2_SA1
P24
FPGA #2 Clock and Reset Signals
CLK_TO_FPGA2_MGT_N
CLK_TO_FPGA2_MGT_P
DIRECT_CLK_TO_FPGA2_N
DIRECT_CLK_TO_FPGA2_P
H3
H4
EXT_CLK_TO_FPGA2_N
AG13
AH12
AH20
AH14
EXT_CLK_TO_FPGA2_P
FPGA2_LOW_FREQ_CLK
FPGA2_RESET_N_IN
AH22
AG22
FPGA #2 MII Link Interface
FPGA1_TO_FPGA2_MII_TX_CLK
FPGA1_TO_FPGA2_MII_TX_DATA0
FPGA1_TO_FPGA2_MII_TX_DATA1
FPGA1_TO_FPGA2_MII_TX_DATA2
AE14
AE16
AF15
AF21
FPGA1_TO_FPGA2_MII_TX_DATA3
AF20
AD20
AE21
AF14
FPGA1_TO_FPGA2_MII_TX_EN
FPGA1_TO_FPGA2_MII_TX_ERR
FPGA1_TO_FPGA2_MII_TX_SPARE
FPGA #2 Configuration Signals
FPGA_INIT
FPGA_PROGB
FPGA_TMS
N14
M22
FPGA2_D_IN
P15
M15
FPGA2_DONE
FPGA2_DOUT_B
FPGA2_HSWAPEN
FPGA2_TCK
AC14
L23
AD15
M23
FPGA_VBATT
FPGA2_CCLK
N15
AB15
AC15
AD14
FPGA2_CNFG_M0
FPGA2_CNFG_M1
FPGA2_CNFG_M2
AD21
AC22
AD22
FPGA2_TDI_IN
FPGA2_TDO
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Appendix A: FPGA Pinouts
Table A-2: FPGA #2 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
FPGA #2 Test and Debug Signals
FPGA2_DIP0
AG18
AG15
AH15
AG20
H20
H19
H13
J14
FPGA2_SOFTTOUCH_BY1_B7
H17
P29
FPGA2_DIP1
FPGA2_SPYHOLE_BK15
FPGA2_SPYHOLE_BK18
FPGA2_DIP2
W9
FPGA2_DIP3
FPGA2_TEST_HDR_BY0_B0
FPGA2_TEST_HDR_BY0_B1
FPGA2_TEST_HDR_BY0_B2
FPGA2_TEST_HDR_BY0_B3
FPGA2_TEST_HDR_BY0_B4
FPGA2_TEST_HDR_BY0_B5
FPGA2_TEST_HDR_BY0_B6
FPGA2_TEST_HDR_BY0_B7
FPGA2_TEST_HDR_BY1_B0
FPGA2_TEST_HDR_BY1_B1
FPGA2_TEST_HDR_BY1_B2
FPGA2_TEST_HDR_BY1_B3
FPGA2_TEST_HDR_BY1_B4
FPGA2_TEST_HDR_BY1_B5
FPGA2_TEST_HDR_BY1_B6
FPGA2_TEST_HDR_BY1_B7
AE23
AE22
AG12
AF13
AG23
AF23
AE12
AE13
K12
FPGA2_SOFTTOUCH_BY0_B0
FPGA2_SOFTTOUCH_BY0_B1
FPGA2_SOFTTOUCH_BY0_B2
FPGA2_SOFTTOUCH_BY0_B3
FPGA2_SOFTTOUCH_BY0_B4
FPGA2_SOFTTOUCH_BY0_B5
FPGA2_SOFTTOUCH_BY0_B6
FPGA2_SOFTTOUCH_BY0_B7
FPGA2_SOFTTOUCH_BY1_B0
FPGA2_SOFTTOUCH_BY1_B1
FPGA2_SOFTTOUCH_BY1_B2
FPGA2_SOFTTOUCH_BY1_B3
FPGA2_SOFTTOUCH_BY1_B4
FPGA2_SOFTTOUCH_BY1_B5
FPGA2_SOFTTOUCH_BY1_B6
J21
J20
H15
H14
J19
K13
K18
G16
G15
L18
H23
G23
H12
J12
K17
H18
K22
K23
FPGA #2 Test Display Signals
FPGA2_7SEG_0_N
FPGA2_7SEG_1_N
FPGA2_7SEG_2_N
FPGA2_7SEG_3_N
FPGA2_7SEG_4_N
FPGA2_7SEG_5_N
AG17
AH18
AE18
AF18
AG16
AH17
FPGA2_7SEG_6_N
AF19
AG21
AD19
AE19
AE17
AF16
FPGA2_7SEG_DP_N
FPGA2_LED0
FPGA2_LED1
FPGA2_LED2
FPGA2_LED3
FPGA #2 External Interfaces
FPGA2_116_TX0_N
FPGA2_116_TX0_P
FPGA2_120_RX0_N
FPGA2_120_RX0_P
FPGA2_120_RX1_N
G2
F2
FPGA2_120_RX1_P
D1
B10
B9
FPGA2_124_TX0_N
FPGA2_124_TX0_P
FPGA2_124_TX1_N
FPGA2_124_TX1_P
A2
A3
C1
B6
B5
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FPGA #2 Pinout
Table A-2: FPGA #2 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
FPGA #2 External Interfaces (cont.)
FPGA2_TXN0_BK120
FPGA2_TXN1_BK120
FPGA2_TXP0_BK120
FPGA2_TXP1_BK120
FPGA2_RS232_CTS
FPGA2_RS232_RTS
FPGA2_RS232_RX
FPGA2_RS232_TX
B3
D2
FPGA2_USB_CTS_N
L15
K16
J15
FPGA2_USB_DSR_N
FPGA2_USB_DTR_N
FPGA2_USB_RST_N
FPGA2_USB_RTS_N
FPGA2_USB_RX
B4
E2
L21
L16
J22
K14
L14
G22
H22
FPGA2_USB_SUSPEND
FPGA2_USB_TX
L20
K21
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Appendix A: FPGA Pinouts
FPGA #3 Pinout
Table A-3 lists the connections for FPGA #3 (U34).
Table A-3: FPGA #3 Pinout
Signal Name
Pin
Signal Name
Pin
QDRII Memory Interface
QDR2_CK_BY0_3_N
QDR2_CK_BY0_3_P
QDR2_CK_BY0_3_P
QDR2_CK_BY4_7_N
QDR2_CK_BY4_7_P
QDR2_CK_BY4_7_P
QDR2_CQ_BY0_3_N
QDR2_CQ_BY0_3_P
QDR2_CQ_BY4_7_N
QDR2_CQ_BY4_7_P
QDR2_DLL_OFF_N
QDR2_K_BY0_3_N
QDR2_K_BY0_3_P
QDR2_K_BY4_7_N
QDR2_K_BY4_7_P
QDR2_LB_BK11
QDR2_LB_BK11
QDR2_LB_BK13
QDR2_LB_BK13
QDR2_LB_BK17
QDR2_LB_BK17
QDR2_LB_BK19
QDR2_LB_BK19
QDR2_NC_A3
K34
G28
QDR2_SA11
QDR2_SA12
QDR2_SA13
QDR2_SA14
QDR2_SA15
QDR2_SA16
QDR2_SA17
QDR2_SA2
QDR2_SA3
QDR2_SA4
QDR2_SA5
QDR2_SA6
QDR2_SA7
QDR2_SA8
QDR2_SA9
QDR2_W_N
AB26
AB25
AA24
Y24
L34
AJ34
AA31
AH34
E26
AC27
AB27
AA26
AJ27
AK26
AF28
AE28
AH28
AG28
AA28
AB28
AH27
M32
K33
AA29
AD32
AK27
F28
E28
AC30
AB30
P32
P34
AE34
AJ32
AE29
AF31
K27
QDR2_BW_BY0_N
QDR2_BW_BY1_N
QDR2_BW_BY2_N
QDR2_BW_BY3_N
QDR2_BW_BY4_N
QDR2_BW_BY5_N
QDR2_BW_BY6_N
QDR2_BW_BY7_N
QDR2_D_BY0_B0
QDR2_D_BY0_B1
QDR2_D_BY0_B2
QDR2_D_BY0_B3
QDR2_D_BY0_B4
L33
L28
K28
AK33
AK34
AC29
AD30
T28
M28
AG25
AF24
AJ26
AJ29
AK29
AC28
QDR2_NC_C6
QDR2_R_N
U30
QDR2_SA0
R31
QDR2_SA1
T31
QDR2_SA10
N30
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FPGA #3 Pinout
Table A-3: FPGA #3 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
QDRII Memory Interface (cont.)
QDR2_D_BY0_B5
QDR2_D_BY0_B6
QDR2_D_BY0_B7
QDR2_D_BY0_B8
QDR2_D_BY1_B0
QDR2_D_BY1_B1
QDR2_D_BY1_B2
QDR2_D_BY1_B3
QDR2_D_BY1_B4
QDR2_D_BY1_B5
QDR2_D_BY1_B6
QDR2_D_BY1_B7
QDR2_D_BY1_B8
QDR2_D_BY2_B0
QDR2_D_BY2_B1
QDR2_D_BY2_B2
QDR2_D_BY2_B3
QDR2_D_BY2_B4
QDR2_D_BY2_B5
QDR2_D_BY2_B6
QDR2_D_BY2_B7
QDR2_D_BY2_B8
QDR2_D_BY3_B0
QDR2_D_BY3_B1
QDR2_D_BY3_B2
QDR2_D_BY3_B3
QDR2_D_BY3_B4
QDR2_D_BY3_B5
QDR2_D_BY3_B6
QDR2_D_BY3_B7
QDR2_D_BY3_B8
QDR2_D_BY4_B0
M31
P30
P31
L31
J27
QDR2_D_BY4_B1
AH29
AH30
AJ30
AF30
AF29
AK31
AJ31
AD29
V30
QDR2_D_BY4_B2
QDR2_D_BY4_B3
QDR2_D_BY4_B4
QDR2_D_BY4_B5
QDR2_D_BY4_B6
QDR2_D_BY4_B7
QDR2_D_BY4_B8
QDR2_D_BY5_B0
QDR2_D_BY5_B1
QDR2_D_BY5_B2
QDR2_D_BY5_B3
QDR2_D_BY5_B4
QDR2_D_BY5_B5
QDR2_D_BY5_B6
QDR2_D_BY5_B7
QDR2_D_BY5_B8
QDR2_D_BY6_B0
QDR2_D_BY6_B1
QDR2_D_BY6_B2
QDR2_D_BY6_B3
QDR2_D_BY6_B4
QDR2_D_BY6_B5
QDR2_D_BY6_B6
QDR2_D_BY6_B7
QDR2_D_BY6_B8
QDR2_D_BY7_B0
QDR2_D_BY7_B1
QDR2_D_BY7_B2
QDR2_D_BY7_B3
QDR2_D_BY7_B4
QDR2_D_BY7_B5
M26
M25
J25
J24
L26
L25
L24
K24
L29
E31
F31
J29
W27
Y27
W25
V25
W26
Y26
V24
W24
U31
U32
T34
H29
F30
G30
F29
E29
K31
P29
N29
M30
L30
J31
U33
R32
R33
R34
T33
N32
T25
U25
T26
J30
G31
H30
AG30
U26
R27
R26
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Appendix A: FPGA Pinouts
Table A-3: FPGA #3 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
QDRII Memory Interface (cont.)
QDR2_D_BY7_B6
QDR2_D_BY7_B7
QDR2_D_BY7_B8
QDR2_Q_BY0_B0
QDR2_Q_BY0_B1
QDR2_Q_BY0_B2
QDR2_Q_BY0_B3
QDR2_Q_BY0_B4
QDR2_Q_BY0_B5
QDR2_Q_BY0_B6
QDR2_Q_BY0_B7
QDR2_Q_BY0_B8
QDR2_Q_BY1_B0
QDR2_Q_BY1_B1
QDR2_Q_BY1_B2
QDR2_Q_BY1_B3
QDR2_Q_BY1_B4
QDR2_Q_BY1_B5
QDR2_Q_BY1_B6
QDR2_Q_BY1_B7
QDR2_Q_BY1_B8
QDR2_Q_BY2_B0
QDR2_Q_BY2_B1
QDR2_Q_BY2_B2
QDR2_Q_BY2_B3
QDR2_Q_BY2_B4
QDR2_Q_BY2_B5
QDR2_Q_BY2_B6
QDR2_Q_BY2_B7
QDR2_Q_BY2_B8
QDR2_Q_BY3_B0
QDR2_Q_BY3_B1
U28
U27
T29
J34
QDR2_Q_BY3_B2
G27
F26
QDR2_Q_BY3_B3
QDR2_Q_BY3_B4
QDR2_Q_BY3_B5
QDR2_Q_BY3_B6
QDR2_Q_BY3_B7
QDR2_Q_BY3_B8
QDR2_Q_BY4_B0
QDR2_Q_BY4_B1
QDR2_Q_BY4_B2
QDR2_Q_BY4_B3
QDR2_Q_BY4_B4
QDR2_Q_BY4_B5
QDR2_Q_BY4_B6
QDR2_Q_BY4_B7
QDR2_Q_BY4_B8
QDR2_Q_BY5_B0
QDR2_Q_BY5_B1
QDR2_Q_BY5_B2
QDR2_Q_BY5_B3
QDR2_Q_BY5_B4
QDR2_Q_BY5_B5
QDR2_Q_BY5_B6
QDR2_Q_BY5_B7
QDR2_Q_BY5_B8
QDR2_Q_BY6_B0
QDR2_Q_BY6_B1
QDR2_Q_BY6_B2
QDR2_Q_BY6_B3
QDR2_Q_BY6_B4
QDR2_Q_BY6_B5
QDR2_Q_BY6_B6
F25
H24
H34
H33
J32
H25
G26
G25
F34
G33
E33
E32
E34
T24
R24
N25
P25
P24
N24
P27
P26
N28
G32
D34
C34
D32
C32
C33
B33
A33
B32
H28
H27
AP32
AN32
AN33
AN34
AM32
AM33
AL33
AL34
AK32
AF34
AE33
AF33
AB33
AC33
AB32
AC32
AD34
AC34
Y32
Y34
AA34
AA33
Y33
V34
W34
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FPGA #3 Pinout
Table A-3: FPGA #3 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
QDRII Memory Interface (cont.)
QDR2_Q_BY6_B7
QDR2_Q_BY6_B8
QDR2_Q_BY7_B0
QDR2_Q_BY7_B1
QDR2_Q_BY7_B2
QDR2_Q_BY7_B3
V33
V32
AB31
Y29
QDR2_Q_BY7_B4
W29
Y31
W31
V27
V28
QDR2_Q_BY7_B5
QDR2_Q_BY7_B6
QDR2_Q_BY7_B7
QDR2_Q_BY7_B8
Y28
V29
RLDRAM II Memory Interface
RLD2_A0
RLD2_A1
AD10
AD9
RLD2_CK_BY2_3_N
AE11
AF11
AK9
AK8
AH8
AG8
AH10
AH9
C13
B13
K9
RLD2_CK_BY2_3_P
RLD2_CS_BY0_1_N
RLD2_CS_BY2_3_N
RLD2_DK_BY0_1_N
RLD2_DK_BY0_1_P
RLD2_DK_BY2_3_N
RLD2_DK_BY2_3_P
RLD2_QK_BY0_N
RLD2_QK_BY0_P
RLD2_QK_BY1_N
RLD2_QK_BY1_P
RLD2_QK_BY2_N
RLD2_QK_BY2_P
RLD2_QK_BY3_N
RLD2_QK_BY3_P
RLD2_QVLD_BY0_1
RLD2_QVLD_BY2_3
RLD2_REF_N
RLD2_A10
RLD2_A11
RLD2_A12
RLD2_A13
RLD2_A14
RLD2_A15
RLD2_A16
RLD2_A17
RLD2_A18
RLD2_A19
RLD2_A2
AC8
AP12
AA9
AA8
AM13
AN13
AA10
AB10
AP14
AN14
AE8
K8
J7
RLD2_A3
AL10
AL11
AC9
H7
RLD2_A4
U7
RLD2_A5
T8
RLD2_A6
AC10
AM11
AM12
AB8
F11
RLD2_A7
U10
AJ9
AF9
D11
H8
RLD2_A8
RLD2_A9
RLD2_WE_N
RLD2_BA0
RLD2_BA1
RLD2_BA2
RLD2_CK_BY0_1_N
RLD2_CK_BY0_1_P
AJ11
RLD2_D_BY0_B0
RLD2_D_BY0_B1
RLD2_D_BY0_B2
RLD2_D_BY0_B3
RLD2_D_BY0_B4
AK11
AD11
AG11
AG10
G8
G10
F10
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Appendix A: FPGA Pinouts
Table A-3: FPGA #3 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
RLDRAM II Memory Interface (cont.)
RLD2_D_BY0_B5
RLD2_D_BY0_B6
RLD2_D_BY0_B7
RLD2_D_BY0_B8
RLD2_D_BY1_B0
RLD2_D_BY1_B1
RLD2_D_BY1_B2
RLD2_D_BY1_B3
RLD2_D_BY1_B4
RLD2_D_BY1_B5
RLD2_D_BY1_B6
RLD2_D_BY1_B7
RLD2_D_BY1_B8
RLD2_D_BY2_B0
RLD2_D_BY2_B1
RLD2_D_BY2_B2
RLD2_D_BY2_B3
RLD2_D_BY2_B4
RLD2_D_BY2_B5
RLD2_D_BY2_B6
RLD2_D_BY2_B7
RLD2_D_BY2_B8
RLD2_D_BY3_B0
RLD2_D_BY3_B1
RLD2_D_BY3_B2
RLD2_D_BY3_B3
RLD2_D_BY3_B4
RLD2_D_BY3_B5
RLD2_D_BY3_B6
RLD2_D_BY3_B7
RLD2_D_BY3_B8
RLD2_DM_BY0_1_N
F8
F9
RLD2_DM_BY2_3_N
T9
G13
F13
N9
N10
E13
E12
L9
RLD2_DQ_BY0_B0
RLD2_DQ_BY0_B1
RLD2_DQ_BY0_B2
RLD2_DQ_BY0_B3
RLD2_DQ_BY0_B4
RLD2_DQ_BY0_B5
RLD2_DQ_BY0_B6
RLD2_DQ_BY0_B7
RLD2_DQ_BY0_B8
RLD2_DQ_BY1_B0
RLD2_DQ_BY1_B1
RLD2_DQ_BY1_B2
RLD2_DQ_BY1_B3
RLD2_DQ_BY1_B4
RLD2_DQ_BY1_B5
RLD2_DQ_BY1_B6
RLD2_DQ_BY1_B7
RLD2_DQ_BY1_B8
RLD2_DQ_BY2_B0
RLD2_DQ_BY2_B1
RLD2_DQ_BY2_B2
RLD2_DQ_BY2_B3
RLD2_DQ_BY2_B4
RLD2_DQ_BY2_B5
RLD2_DQ_BY2_B6
RLD2_DQ_BY2_B7
RLD2_DQ_BY2_B8
RLD2_DQ_BY3_B0
RLD2_DQ_BY3_B1
RLD2_DQ_BY3_B2
RLD2_DQ_BY3_B3
E8
E9
R11
R7
J6
T6
R6
M10
E11
J10
B12
A13
H9
H10
C12
D12
J11
K6
K7
P6
P7
V9
V10
AK6
AK7
U8
V8
K11
E7
AJ6
AJ7
W9
Y8
E6
G7
G6
AD7
AC7
AB5
AA5
AB7
AB6
AC5
AC4
G12
F6
F5
J5
G5
H5
L4
P5
N5
L6
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FPGA #3 Pinout
Table A-3: FPGA #3 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
RLDRAM II Memory Interface (cont.)
RLD2_DQ_BY3_B4
RLD2_DQ_BY3_B5
RLD2_DQ_BY3_B6
M7
N7
N8
RLD2_DQ_BY3_B7
RLD2_DQ_BY3_B8
M5
M6
FPGA #3 Clock and Reset Signals
CLK_TO_FPGA3_MGT_N
CLK_TO_FPGA3_MGT_P
DIRECT_CLK_TO_FPGA3_N
DIRECT_CLK_TO_FPGA3_P
D4
E4
EXT_CLK_TO_FPGA3_N
AG13
AH12
AH20
AH14
EXT_CLK_TO_FPGA3_P
FPGA3_LOW_FREQ_CLK
FPGA3_RESET_N_IN
AH22
AG22
FPGA #3 MII Link Interface
FPGA1_TO_FPGA3_MII_TX_CLK
FPGA1_TO_FPGA3_MII_TX_DATA0
FPGA1_TO_FPGA3_MII_TX_DATA1
FPGA1_TO_FPGA3_MII_TX_DATA2
AE14
AE16
AF15
AF21
FPGA1_TO_FPGA3_MII_TX_DATA3
AF20
AD20
AE21
AF14
FPGA1_TO_FPGA3_MII_TX_EN
FPGA1_TO_FPGA3_MII_TX_ERR
FPGA1_TO_FPGA3_MII_TX_SPARE
FPGA #3 Configuration Signals
FPGA_INIT
FPGA_PROGB
FPGA_TMS
N14
M22
FPGA3_D_IN
P15
M15
FPGA3_DONE
FPGA3_DOUT_B
FPGA3_HSWAPEN
FPGA3_TCK
AC14
L23
AD15
M23
FPGA_VBATT
FPGA3_CCLK
N15
AB15
AC15
AD14
FPGA3_CNFG_M0
FPGA3_CNFG_M1
FPGA3_CNFG_M2
AD21
AC22
AD22
FPGA3_TDI_IN
FPGA3_TDO
FPGA #3 Test and Debug Signals
FPGA3_DIP0
FPGA3_DIP1
AG18
AG15
AH15
AG20
R8
FPGA3_TEST_HDR_BY0_B3
AF13
AG23
AF23
AE12
AE13
AE24
AD24
AD25
AD26
FPGA3_TEST_HDR_BY0_B4
FPGA3_TEST_HDR_BY0_B5
FPGA3_TEST_HDR_BY0_B6
FPGA3_TEST_HDR_BY0_B7
FPGA3_TEST_HDR_BY1_B0
FPGA3_TEST_HDR_BY1_B1
FPGA3_TEST_HDR_BY1_B2
FPGA3_TEST_HDR_BY1_B3
FPGA3_DIP2
FPGA3_DIP3
FPGA3_SPYHOLE_BK12
FPGA3_SPYHOLE_BK13
FPGA3_TEST_HDR_BY0_B0
FPGA3_TEST_HDR_BY0_B1
FPGA3_TEST_HDR_BY0_B2
AG32
AE23
AE22
AG12
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Appendix A: FPGA Pinouts
Table A-3: FPGA #3 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin
FPGA #3 Test and Debug Signals (cont.)
FPGA3_TEST_HDR_BY1_B4
FPGA3_TEST_HDR_BY1_B5
AC24
AC25
FPGA3_TEST_HDR_BY1_B6
FPGA3_TEST_HDR_BY1_B7
AE26
AE27
FPGA #3 Test Display Signals
FPGA3_7SEG_0_N
FPGA3_7SEG_1_N
FPGA3_7SEG_2_N
FPGA3_7SEG_3_N
FPGA3_7SEG_4_N
FPGA3_7SEG_5_N
AG17
AH18
AE18
AF18
AG16
AH17
FPGA3_7SEG_6_N
AF19
AG21
AD19
AE19
AE17
AF16
FPGA3_7SEG_DP_N
FPGA3_LED0
FPGA3_LED1
FPGA3_LED2
FPGA3_LED3
FPGA #3 External Interfaces
FPGA3_RS232_CTS
FPGA3_RS232_RTS
FPGA3_RS232_RX
FPGA3_RS232_TX
FPGA3_USB_CTS_N
FPGA3_USB_DSR_N
G15
L18
H18
K17
H14
J14
FPGA3_USB_DTR_N
H13
L19
H15
J20
FPGA3_USB_RST_N
FPGA3_USB_RTS_N
FPGA3_USB_RX
FPGA3_USB_SUSPEND
FPGA3_USB_TX
K19
J21
FPGA #3 System ACE Control Signals
SYSACE_CTRL0
SYSACE_CTRL1
SYSACE_CTRL2
SYSACE_CTRL3
SYSACE_CTRL4
SYSACE_MPA0
SYSACE_MPA1
SYSACE_MPA2
SYSACE_MPA3
SYSACE_MPA4
H12
G23
H23
K13
K12
G22
H22
L14
K14
K23
SYSACE_MPA5
K22
J12
SYSACE_MPA6
SYSACE_MPD0
SYSACE_MPD1
SYSACE_MPD2
SYSACE_MPD3
SYSACE_MPD4
SYSACE_MPD5
SYSACE_MPD6
SYSACE_MPD7
L21
L20
L15
L16
J22
K21
K16
J15
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Appendix B
Bill of Materials
This appendix lists the bill of materials (BOM) for many of the components used for the
assembly of the Virtex-5 FPGA ML561 Development Board, Revision A. Wherever feasible
and practical, the associated reference designators are also listed for each part. The
component part number in the “Mfr. Part Number” column includes a link to the
corresponding manufacturer or supplier’s web page. Check with the manufacturer for
current information regarding the location and status of component data sheets.
Table B-1: Bill of Materials
Category
Description
Manufacturer
Mfr. Part Number
Reference Designators
FPGA
Virtex-5 FPGA
Xilinx
XC5VLX50T-FFG1136 -2 speed grade
U5, U7, U34
XP1, XP2, XP3, XP4, XP5
(DIMM)
DDR2 Registered DIMM
DDR2 Unbuffered DIMM
Micron
Micron
XP1, XP2, XP3, XP4, XP5
(DIMM)
DDR400 SDRAM
DDR2 SDRAM
QDRII
Micron
Micron
U6, U9
Memory
U11, U12
U35, U41
U25, U33
Samsung
Micron
RLDRAM II
XP1, XP2, XP3, XP4, XP5
(Socket)
DIMM Socket
SMP Technology
33 MHz Oscillator
200 MHz Oscillator
System ACE Controller
JTAG Port
Epson
Epson
Xilinx
Molex
Y2, Y3
Y1
Clock
U45
Configuration
P114
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Appendix B: Bill of Materials
Table B-1: Bill of Materials (Continued)
Category
Description
Manufacturer
Mfr. Part Number
Reference Designators
VR1, VR6, VR9, VR10,
VR12, VR13
15A Power Module
Texas Instruments
6A Power Module
4A LDO
Texas Instruments
Maxim
VR2, VR4, VR14
VR3, VR5, VR7, VR8
U15
1.5A VLDO Regulator
Linear Technology
DDR Bus Termination
Regulator
Fairchild
Semiconductor
Power
U1, U2, U14, U42
Power Measurement Header
500 mA VLDO Regulator
5A LDO
3M
P102
U16, U22
U23
Linear Technology
Texas Instruments
R63, R724, R764, R777,
R874, R885, R954
Power Sensing Resistor
Isotek Corp.
USB to RS-232 Bridge
Schmitt Inverter
Silicon Labs
Toshiba
U43
U32
Glue Logic
Level Translator
Maxim
U10
RS-232 Compatible Transceiver
CMOS Octal Buffer
Maxim
U31
ON Semiconductor
U37, U38
Integrated Device
Technology
LVCMOS, 1-to-4
U19
U30, U44
U17, U18
U20
Integrated Device
Technology
LVCMOS, 1-to-4, 5V Tolerant
Differential LVPECL, 1-to-6
Diff. LVPECL-to-LVDS, 1-to-4
Diff. HCSL, 1-to-4
Integrated Device
Technology
Clock Buffer
Integrated Device
Technology
Integrated Device
Technology
U24
Display
7-Segment LED
Banana Jack (Red)
Banana Jack (Black)
RS232 DB-9 Port
Stanley Electric
Hirschmann
Hirschmann
Tyco Electronics
KYCON
D17, D23, D35
J18, J25
J17, J24
P73
USB Port
J29
Test Headers (2x8)
CompactFlash Holder
CompactFlash Ejector
5V Power Input Jack
Power Fuse
Tyco Electronics
Molex
P20, P21, P93
J27
Socket/
Connector
Molex
CUI Inc.
J28
Digikey
F1, F2
SMA for Ext Clock Inputs
AMPHENOL-RF
J16, J19, J20, J21
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Table B-1: Bill of Materials (Continued)
Category
Description
DIP (Test Inputs)
System Reset (Black)
Configuration Reset (Red)
Power Input (12V and 5V)
Rotary 8-position
0402 (Assorted Values)
0603 (Assorted Values)
0805 (Assorted Values)
Tantalum C
Manufacturer
ITT_INDUSTRIES
Panasonic
Panasonic
APEM
Mfr. Part Number
Reference Designators
SW1, SW2, SW6
SW4
Switch
SW7
SW3, SW5
SW8
Digikey
Panasonic
Panasonic
Panasonic
Kemet
MLC_CAP_0402
MLC_CAP_0603
MLC_CAP_0805
TANT_CAP_C
TANT_CAP_D
TANT_CAP_E
Lxx
Capacitor
Inductor
Tantalum D
Kemet
Tantalum E
Kemet
DO3316
Coilcraft
TDK
Ferrite Bead
FBxx
0805 (assorted values)
0402 (assorted values)
0603 (assorted values)
0805 (assorted values)
MOSFET
Digikey
Lxx
Panasonic
Panasonic
Panasonic
Diodes
Rxxx
Resistor
Rxxx
Rxxx
Transistor
Qxx
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Appendix B: Bill of Materials
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Appendix C
LCD Interface
This appendix describes the LCD interface for the Virtex-5 FPGA ML561 Development
Board.
General
The Virtex-5 FPGA ML561 Development Board has a full graphical LCD panel. This
display was chosen because of its possible use in embedded systems. A character-type
display also can be connected because the graphical LCD has the same interface as the
character-type LCD panels.
A hardware character generator must be designed to display characters on the screen.
Display Hardware Design
The FPGA (I/O functioning at 2.5V) is connected to the graphic LCD panel through a set of
voltage-level converting devices. These switches translate the 2.5 I/O voltage to a 3.3V
voltage for the LCD panel.
A graphics-based LCD panel from DisplayTech (64128EFCBC-XLP) is used on the Virtex-5
FPGA ML561 Development Board. The control for this LCD panel is based on the KS0713
controller from Samsung. The KS0713 is a 65-column, 132-segment driver-controller device
for graphic dot matrix LCD systems. The chip accepts serial or parallel display data. The
8-bit parallel interface is compatible with most LCD panel manufacturers. The serial
connection mode is write only.
Extra features added to the interface in addition to the normal parallel signals are:
•
•
•
Intel or Motorola compatible interface
External reset of the chip
External chip select
The interface also contains the following built-in options for the display and controller:
•
•
•
On-chip oscillator circuitry
On-chip voltage converter (x2, x3, x4, and x5)
A 64-step electronic contrast control function
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Appendix C: LCD Interface
Table C-1 summarizes the controller specifications.
Table C-1: Display Controller Specifications
Parameter
Specification
Supply Voltage
2.4V to 3.6V (VDD
)
LCD Driving Voltage
Power Consumption
4V to 15V (VLCD = V0 - VDD)
70 μA typical (VDD = 3V, x4 boost, V0 = 11V,
internal supply = ON)
Sleep Mode
2 μA
Standby Mode
10 μA
The on-chip RAM size is 65 x 132 = 8580 bits.
Hardware Schematic Diagram
LCD-BUS
LED
Rst
MI
-
+
Vcc Gnd
LCD_D[7:0]
IC19
3.3V
ENA, R/W, RSEL, CS1B
3.3V
3.3V
IC22
IC23
68xx
3.3V
DIP1_4
68xx
Default = 68xx
Default =
Resistor to Gnd
Backlight ON/OFF
UG199_C_01_050106
Figure C-1: Display Schematic Diagram
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Hardware Schematic Diagram
Peripheral Device KS0713
Figure C-2 is a block diagram of the Samsung KS0713.
VDD
33 Common
Driver
132 Segment
Driver
33 Common
Driver
Circuits
Circuits
Circuits
VSS
Segment Controller
Common Controller
V/F
Circuit
Page
Address
Circuit
I/O
Buffer
Display Data RAM
65 x132 =
Line
Address
Circuit
Display
Timing
Generator
Circuit
8580 Bits
V/R
Circuit
Column Address
Circuit
Oscillator
V/C
Circuit
Instruction Register
Instruction Decoder
Status Register
Bus Holder
MPU Interface (Parallel & Serial)
KS0713 Samsung
UG199_C_02_050106
Figure C-2: KS0713 Block Diagram
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Appendix C: LCD Interface
Figure C-3 shows only the signals of interest for the LCD controller. The data sheet from
the Samsung web pages provides a complete signal listing.
1
2
3
4
5
6
7
8
9
VSS
VDD
MI
DB7
DB6
DB5
DB4
DB3
DB2
Jumper J3
Parallel or Serial Selection.
Default is Parallel.
S128
10 DB1
11 DB0
12 E
13 R/W
14 RS
C64
LCD Panel
15 RST
16 CS1B
17 LED+
18 LED-
LED Backlight
UG199_C_03_050106
Figure C-3: 64128EFCBC-XLP Block Diagram
Figure C-4 shows the dimensions for the 64128EFCBC-XLP LCD panel.
74.00
69.00
56.00
J2
J1
17 18
LED
128 x 64 DOTS
1
2
30
1
2.50
2.54
Dimensions in mm
8.00 Max
UG199_C_04_050106
Figure C-4: 64128EFCBC-XLP Dimensions
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Hardware Schematic Diagram
Controller – Operation
The pixels for the LCD panel are stored in the controller data RAM. This RAM is a 65-row
by 132-column array. Each display pixel is represented by a single bit in the RAM array.
The interface to the RAM array goes through the 8-bit (DB0 – DB7) LCD interface.
Therefore, the 65-bit rows are split into eight pages of eight lines. The ninth page is a single
line page (DB0 only).
Interface designs can read from or write to the RAM array.
The display page is changed through the 4-bit page address register.
The column address (line address) is set with a two-byte register access. The line address
corresponds to the first line that is going to be displayed on the LCD panel. This address is
located in a 6-bit address register.
The RAM array is configured such that there are two characters per row (page), where each
address lines, ADC control, and LCD outputs (segments).
Table C-2: LCD Panel
Line
Address
DB3 DB2 DB1 DB0 Data
DB0
DB1
DB2
DB3
00H
01H
02H
03H
0
0
0
0
Page 0
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
04H
05H
06H
07H
08H
09H
0AH
0BH
0
0
0
1
Page 1
0CH
0DH
0EH
0FH
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Appendix C: LCD Interface
Table C-2: LCD Panel (Continued)
Line
DB3 DB2 DB1 DB0 Data
Address
10H
11H
DB0
DB1
DB2
DB3
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
Page 2
Page 3
Page 4
Page 5
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
0
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Hardware Schematic Diagram
Table C-2: LCD Panel (Continued)
Line
Address
DB3 DB2 DB1 DB0 Data
DB0
DB1
DB2
DB3
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
0
1
1
0
Page 6
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
0
1
1
0
1
0
1
0
Page 7
Page 8
ADC = 0
ADC = 1
0
1
2
3
4
5
6
7
8
9
A
B
7E 7F 80 81 82 83
Column
Address
83 82 81 80 7F
7
E
7
D
7
C
7
B
7
A
79 78
5
4
3
2
1
0
LCD Output
When a page is addressed, all the bits representing dots on the LCD panel can be accessed
in that page. An array of 8x132 bits is available. The line address dictates what line of the
RAM is going to be displayed on the first line of the glass panel.
Controller – LCD Panel Connections
The controller die, KS0713, connects to the LCD glass panel and user connection pins via a
small PCB. Other necessary pins have default connections on the PCB.
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Appendix C: LCD Interface
Controller – Power Supply Circuits
Figure C-5 shows the power supply circuits. The power supply is used in the five times
boost mode, where VDD is 3.3V and VOUT is 16.5V. VOUT is the operating voltage of the
operational amplifier delivering the operating voltage, V0, for the LCD panel.
DUTY1
DUTY2
BSTS
VOUT
VR
5 x VDD
MS
INTRS
2
VDD
17 VDD
18 VOUT
25
26
27
VDD
28
29
1
VSS
30 VSS1
16 VSS
DCDC5B
VSS
UG199_C_05_050106
Figure C-5: Power Supply Circuits
The LCD operating voltage, V0, is set with two resistors R and R . INTRS is driven Low
A
B
when the resistors are external. INTRS is driven High when the resistors are internal. For
the Virtex-5 FPGA ML561 Development Board, internal resistors are selected.
The LCD operating voltage (V0) and the Electronic Volume Voltage (V ) can be calculated
EV
RB
⎛
⎞
V0 = 1 + ------ × VEV
Equation C-1
Equation C-2
⎝
⎠
RA
63 – α
⎛
⎞
VEV = 1 – -------------- × VREF
⎝
⎠
300
is equal to 2.0V at 25 °C.
REF
The values of the reference voltage parameter, α, and the ratio R /R are determined with
A
B
bit settings in the LCD controller’s instruction registers. Thus, it is possible to change
physical operating parameters of the LCD through register bit settings, controlling the
operating voltage, and the electronic volume level.
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Hardware Schematic Diagram
The voltage and contrast settings must be configured before the LCD panel is ready for
controller.
Setup Instruction Flow
Power ON
Board Power Supply Start
RESETB Pin is Kept LOW
Start FPGA Configuration
RESETB Pin is Kept LOW
FPGA Configured and Application Running
RESETB Pin is Taken HIGH
ADC Select
- ADC = 0 SEG1 --> SEG132
- ADC = 1 SEG132 --> SEG1
LCD Bias
ADC Select
SHL Select
LCD Bias Select
DUTY0, 1 is "11".
LCD Bias 0 = 1/7
LCD Bias 1 = 1/9
SHL Select
- SHL = 0 COM1 --> COM64
- SHL = 1 COM64 --> COM1
Voltage Converter ON
Voltage Regulator ON
Voltage Follower ON
Wait longer than 1 ms between
each instruction to let the voltages stabilize.
The on-chip resistors are used.
Therefore, the selection MUST be
set to 101.
Regulator Resistor Select
Set Reference Voltage
Setting Reference Voltage
is a two-pass instruction:
End Initialization
- Set Reference Voltage Mode
- Set Reference Voltage Register
UG199_C_06_050106
Figure C-6: LCD Controller Initialization Flow
Operation Example of the 64128EFCBC-3LP
The KS0713 LCD controller has several default settings of operation on the LCD panel
PCB. Some settings are forced through direct bonding on the chip. The default settings are:
•
•
•
•
•
•
•
•
Master mode
Parallel mode
Internal oscillator
Duty cycle ratio is set to 1/65
Voltage converter input is between 2.4V ≤VDD ≤3.6V, where VDD connects to 3.3V
Internal voltage divider resistors
Temperature coefficient is set to -0.05%/°C
Normal power mode is set
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Appendix C: LCD Interface
•
The voltage follower and voltage regulator are set to:
♦
♦
Five times boost mode
The V4, V3, V2, V1, and V0 outputs depend on the bias settings of 1/9 or 1/7.
Because of these default settings, the following display controller connections are not used:
•
•
•
•
DISP: Turns into an output when Master mode is selected
FRS: Static driver segment output
M: Used in Master/Slave display configurations
CL: Clock pin used in Master/Slave display configurations
Table C-3: Display Controller Initialization (RESETB is Low)
Parameter
Initial Value
Display
OFF
OFF
OFF
OFF
Entire Display
ADC Select
Reverse Display
Power Control
0,0,0 (VC, VR, VF)
LCD Bias
1/7
Read-Modify-Write
SHL Select
OFF
OFF
Static Indicator Mode
Static Indicator Register
Display Start
OFF
0,0 (S1, S0)
0 (First line)
Column Address
Page Address
0
0
Regulator Select
Reference Voltage
Reference Voltage Register
0,0,0 (R2, R1, R0)
OFF
1,0,0,0,0,0 (SV5, SV4, SV3, SV2, SV1, SV0)
When RESETB is High, the display must be initialized. The first steps to be taken to
guarantee correct operation of the display and the controller are:
•
Configure the ADC bit. This bit determines the scanning direction of the segments.
♦
When the RESETB signal is active, ADC is reset to 0, meaning that the segments
are scanned from SEG1 up to SEG132.
♦
When ADC is set to 1, the segments are scanned in opposite direction.
•
Configure the SHL bit. This bit sets the scanning direction of the COM lines.
♦
When the RESETB signal is active, SHL is reset to 0, meaning that the segments
are scanned from COM1 up to COM64.
♦
When SHL is set to 1, the common lines are scanned in opposite direction.
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Hardware Schematic Diagram
After the SHL bit is configured, these settings normally are not changed.
Select the LCD bias settings.
•
♦
The duty cycle is selected as 1/65 by hardwiring the controller IC pads on the
display PCB.
♦
The LCD bias is set to:
-
-
1/7: when the BIAS bit is 0
1/9: when the BIAS bit is 1
The following steps are performed next:
•
•
•
Start the onboard converter, regulator, and follower
Table C-4: Resistor Value Settings
3-Bit Data Settings (R2 R1 R0)
000
001
010
011
100
101
110
111
1+(Rb/Ra)
1.90
2.19
2.55
3.02
3.61
4.35
5.29
6.48
Table C-5: Reference Voltage Parameters
SV5
SV4
SV3
SV2
SV1
SV0
Reference Voltage Parameter (α)
0
0
0
0
0
0
0
0
0
0
0
1
0
1
..
..
..
..
…
..
..
..
..
..
..
..
..
..
1
1
1
1
1
1
1
1
1
1
0
1
62
63
At startup of the LCD controller (after RESETB operation), the resistor and reference
voltage values are:
•
•
Resistor selection is: 0,0,0
Reference voltage is: 1,0,0,0,0,0
The resistor selection value MUST be set to 101b when using this LCD panel.
After the display is brought to operational mode, it is best to wait at least 1 ms to ensure the
stabilization of power supply levels. After this time, all other necessary display
initializations can be performed.
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Appendix C: LCD Interface
Instruction Set
Table C-6 shows the instruction set for the LCD panel.
Table C-6: Display Instructions
Instruction
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read display data
1
1
Read Data
8-bit data specified by the column and page address can be read from the Display Data RAM. The column address is increased automatically,
thus data can be read continuously from the addressed page.
Write display data
1
0
Write Data
8-bit data can be written into a RAM location specified by the column and page address. The column address is increased automatically, thus
data can be written continuously to the addressed page.
Read status
0
1
BUSY
ADC
ONOFF
RESETB
0
0
0
0
BUSY: Device is BUSY when internal operation or reset. (0=active, 1 =busy).
ADC: Indicates the relationship between RAM column address and segment driver.
ONOFF: Indicates display ON or OFF status.
RESETB: Indicates if initialization is in progress.
Display ON/OFF
Turn display ON or OFF. (1=ON, 0 = OFF)
Initial display line
0
0
0
1
0
0
1
1
0
1
1
1
DON
ST0
0
ST5
ST4
ST3
ST2
ST1
Sets the line address of the display RAM to determine the initial line of the LCD panel.
ST5
0
ST4
0
ST3
0
ST2
0
ST1
0
ST0
0
Line address 0
Line address 1
..
0
0
0
0
0
1
..
..
..
..
..
..
1
1
1
1
1
0
Line address 62
Line address 63
1
1
1
1
1
1
Set reference voltage mode
Set reference voltage register
0
0
0
0
1
x
0
x
0
0
0
0
0
1
SV5
SV4
SV3
SV2
SV1
SV0
This is a two-byte instruction. The first instruction sets the reference voltage mode. The second instruction sets the reference voltage parameter.
SV5
SV4
SV3
SV2
SV1
SV0
0
0
..
1
1
0
0
..
1
1
0
0
..
1
1
0
0
..
1
1
0
0
..
1
1
0
1
..
0
1
0
1
..
62
63
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Hardware Schematic Diagram
Table C-6: Display Instructions (Continued)
Instruction
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Set page address
0
0
1
0
1
1
P3
P2
P1
P0
This instruction sets the address of the display data page. Any RAM data bit can be accessed when its page address and column address are
specified. Changing the Page Address does not affect the display status.
P3
0
P2
0
P1
0
P0
0
page 0
page 1
...
0
0
0
1
..
..
..
..
0
1
1
1
page 7
page 8
1
0
0
0
Set column address MSB
Set column address LSB
0
0
0
0
0
0
0
0
0
0
1
0
Y7
Y3
Y6
Y2
Y5
Y1
Y4
Y0
This instruction sets the address of the display data RAM. When a read or write to or from the display data RAM occurs, the addresses are
automatically increased.
Y7
0
Y6
0
Y5
0
Y4
0
Y3
0
Y2
0
Y1
0
Y0
0
Col
Addr 0
Col
Addr 1
0
..
0
..
0
..
0
..
0
..
0
..
0
..
1
..
...
Col
Addr
130
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Col
Addr
131
ADC select
0
0
1
0
1
0
0
0
0
ADC
This instruction changes the relationship between RAM column address and segment driver.
ADC = 0, SEG1 --> SEG132 default mode
ADC = 1, SEG132 --> SEG1
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Appendix C: LCD Interface
Table C-6: Display Instructions (Continued)
Instruction
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Reverse display ON/OFF
0
0
1
0
1
0
0
1
1
REV
REV
RAM bit data = '1'
Pixel ON
RAM bit data = '0'
Pixel OFF
0
1
Pixel OFF
Pixel ON
Entire display ON/OFF
0
0
1
0
1
0
0
1
0
EON
This instruction forces the display to be turned on regardless the contents of the display data RAM. The contents of the display data RAM are
saved. This instruction has priority over reverse display.
LCD bias select
0
0
1
0
1
0
0
0
1
BIAS
This instruction selects the LCD bias.
Duty
ratio
Bias = 0
1/7
Bias = 1
1/9
1/65
Set modify-read
0
0
1
1
1
0
0
0
0
0
This instruction stops the automatic incrementing of the column address by a read operation. The automatic increment is still done with a
write operation.
Reset modify-read
This instruction resets the changed modify-read to the normal.
Reset
0
0
1
1
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
0
This instruction resets the LCD controller registers to the default values. The instruction CANNOT initialize the LCD power supply initialized
with RESETB.
SHL select
0
0
1
1
0
0
SHL
x
x
x
This instruction sets the COM output scanning direction.
SHL = 0, COM1 ----> COM64 (default)
SHL = 1, COM64 ----> COM1
Power Control
0
0
0
0
1
0
1
VC
VR
VF
This instruction selects one of the eight power circuit functions. In the case of the DisplayTech 64128EFCBC display, these must be kept at "000"
Regulator resistor select
0
0
0
0
1
0
0
R2
R1
R0
This instruction selects the resistor ratio Rb/Ra.
Set static indicator mode
Set static indicator register
0
0
0
0
1
x
0
x
1
x
0
x
1
x
1
x
0
SM
S0
S1
This is a two-byte instruction. The first instruction enables the second instruction. The second instruction update the contents of the static
indicator register.
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Hardware Schematic Diagram
Read/Write Characteristics (6800 Mode)
Table C-7 list the read and write timing parameters in 6800 mode. The associated
Table C-7: Read/Write Characteristics in 6800 Mode
Parameter
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Signal
Symbol
TAS
Min
13
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
RS
TAH
17
-
-
TDS
35
-
-
-
-
DB7 to DB0
TDH
13
Access Time
TACC
TOD
-
-
125
90
-
Output Disable Time
System Cycle Time
10
-
RS
TCYC
400
TPWR
TPWW
-
125
55
-
Enable Pulse Width
Read/Write
E_RD
-
RS
RW
T
AS
T
AH
CS1B
T
CYC
T
PWR
T
PWW
E
T
DS
T
DH
WRITE
DB0-DB7
T
ACC
T
OD
READ
UG199_C_07_050106
Figure C-7: Read/Write Timing Waveforms (6800 Mode)
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Appendix C: LCD Interface
Design Examples
LCD Panel Used in Full Graphics Mode
The LCD controller RAM has eight 132-byte pages (in fact, there are nine pages; page 9 is
special). Each page is one byte wide. If all the pages are put in one memory block, the
needed space is 8 pages x 8 bits x 132 pixels or 8448 bits (1056 bytes).
One Virtex-5 FPGA block RAM can be configured as 8+1 by 2048.
One block RAM can be used to store one complete pixel view of the LCD panel. There is
enough space left for commands.
The ninth bit in the block RAM indicates whether the data in the block RAM is real data to
be displayed or is a command for the controller.
The interface to the LCD panel is slow. The E signal can be used as the controller clock
signal. This signal has a minimum cycle time of 400 ns for displaying 8 bits (equal to 8 dots)
on the LCD. One full page of the display takes up to 132 x 400 ns = 52.8 μs. Updating the
full display takes 52.8μs x 8 = 423μs.
If using the dual port and data width capabilities of the block RAM, then writes to the
block RAM can be 32 bits (+4 control bits), and reads from the block RAM on the LCD side
can be 8 bits (1 control bit). An entire LCD page is updated in 33 write operations.
The interface on the LCD panel side sequentially reads the block RAM, and thus, updates
the screen contiguously (like a television screen). The controller (microcontroller or other)
side of the block RAM can be written at any time.
The write operation happens on the rising edge of the clock and the read (LCD update)
happens on the falling edge of the clock. Normally write and read operations at the same
address give corrupt read data when the read and write clock edges do not respect the
clock-to-clock setup timing. This problem is solved by using both edges of the clock.
A state machine provides correct timing of the signals on the LCD panel side. The panel
can be used in write-only mode or in read/write mode. Most of the time, LCD panels
operate in write-only mode.
At first, the block RAM must be initialized with some data (instructions to the LCD) to
panel in full graphics mode.
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Hardware Schematic Diagram
RData (8+gnd)
DataIn (8)
DB (8)
DataOut (8)
IorD = '1' Instruction
'0' Data
WData (32+4)
Address
Write
IorD (bit 9)
Addr
CS1B
read
RS
Enable
ena
RW
Clock
Clock
E
Clock
Block RAM
Reset
E
Clock
TC
State
Machine
Clock
Reset
Design for Full Graphics Interface, Attached to CoreConnect Bus
UG199_C_08_050106
Figure C-8: General Block Diagram of LCD Panel in Full Graphics Mode
LCD Panel Used in Character Mode
This design example requires a byte representing a command or data to be displayed as
input.
•
•
•
When the Enable signal is Low, nothing happens. The display interface design is
locked.
When the Enable signal is High and the data_or_command control signal is Low, the
byte written is a display command.
When the Enable signal and the data_or_command control signal are High, the byte
written is the ASCII character code of the character to be put on the display.
Display Command Byte
When the LCD interface is enabled for the first time, a set of command bytes is sent to the
LCD. This command set provides the basic initialization of the LCD controller. When this
initialization is done, the normal LCD interface is freed for normal use. Command bytes
from the valid command set can be sent to the display (controller).
The Toplevel.vhd.txtfile provides a detailed description of the LCD controller
interface.
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Appendix C: LCD Interface
Display Data Byte
The supplied byte must be a valid ASCII representation of a character as shown in
UG199_C_09_050106
Figure C-9: ASCII Character Representations
The character set is stored in block RAM (used as ROM). The CharacterSet.xlsfile
organized as small arrays of eight bytes, which is easy for address calculation.
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Hardware Schematic Diagram
Data[7:0]
2047
F0 - FF
E0 - EF
D0 - DF
C0 - CF
B0 - BF
A0 - AF
Not Used
Not Used
70 - 7F
60 - 6F
50 - 5F
40 - 4F
30 - 3F
20 - 2F
10 - 1F
Not Used
The RAM array is divided in
pages of eight bytes by 16,
forming an array of 128 bytes.
This array represents one
column of standard ASCII table.
A character is stored as:
1280
1279
Addr[10:0]
N-x
1024
1023
N
N-1
Shift
Direction
Addr
256
255
0
RAMB16_S9
0
0 1 2 3 4 5 6 7 Data
UG199_C_10_050106
Figure C-10: Block RAM Organization
When presenting byte value 30 hex, character 0 must be displayed. Shifting the value
00110000b (30h) up three positions gives the value 180h or 348d.
Because each character uses eight byte locations, character 0 in the character set starts from
memory location 348 decimal.
For example, character X has byte value 58h or 01011000b. Shifting this value three
positions gives the value 2C0h or 704d.
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Appendix C: LCD Interface
Figure C-11 shows a block diagram of the LCD character generator controller. Character
data is latched and then shifted left three positions. This shifted value is the start byte for a
counter that outputs an address to the block RAM. The result is a stream of bytes
representing a character for the display.
A small second counter determines when a new character is loaded into the block RAM
address counter.
Position
Register
Page
8
Data
0
1
DesRst
Counter A
DI
8
8
11
11
DataIn
Ena
DO
Addr
8
Ena
E
E
L
3
Rst
DesRst Ssr
RAMB16_S9
Display
Register
Clk
Clk
We
Clk
DesRst
DesRst
Clk
E
TC
Load
LUT-ROM
Display
Counter B
Initialization
DesRst
Count to 8.
Clk
Stop both counters at TC.
Send character position and
line to the LCD.
Load new value in counter A.
Switch to character ROM.
Enable counters.
RS
Rst
DesRst
RW
E
Ena
State Machine
Clk
UG199_C_11_050106
Figure C-11: LCD Character Generator Controller
A state machine manages the processing order.
A minimum cycle time of 400 ns on the E signal used as a reference. The 200 MHz system
clock frequency is used as reference system clock. One E cycle uses at least 80 system clock
cycles when the design is running at 200 MHz. The E pulse is part of the state machine, and
the design only depends on the system clock. Timing is met as long as the system clock
does not exceed 200 MHz.
This design can be adapted easily to fit the MicroBlaze™ or PPC405 CoreConnect bus
system.
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Hardware Schematic Diagram
Array Connector Numbering
Figure C-12 shows the LCD connections for Bank 0.
Bank 0
Connector Pin
A
B
C
D
E
F
G
H
I
D9
LCD_D0
D7
D5
D3
LCD_D4
LCD_D5
LCD_D6
10
9
8
D1
LCD_D7
7
6
E10
LCD_RST
E8
E6
E4
E2
F5
LCD_D1
LCD_D2
LCD_D3
LCD_ENA
LCD_R/W
5
4
3
2
1
F3
F1
LCD_RSEL
LCD_CS1B
Connector J32
UG199_C_12_050106
Figure C-12: LCD Connections (Bank 0)
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Appendix C: LCD Interface
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