User's Guide
SLAU189–September 2006
ADS8364/65MEVM
This user's guide describes the characteristics, operation, and use of the
ADS8364/65MEVM 16-bit, parallel analog-to-digital converter evaluation module
(EVM). A complete circuit description, a schematic diagram, and bill of materials is
included.
Contents
1
2
3
4
5
6
7
8
EVM Overview ...................................................................................... 1
Introduction .......................................................................................... 2
Analog Interface .................................................................................... 2
Digital Interface ..................................................................................... 4
Power Supplies ..................................................................................... 6
EVM Operation...................................................................................... 6
List of Figures
1
2
3
Channel A0 Input Circuit........................................................................... 3
Channel A1 Input Circuit........................................................................... 4
List of Tables
1
2
3
4
5
6
J1 Pinout and Functions ........................................................................... 6
JP1 Pinout ........................................................................................... 6
1
EVM Overview
1.1 Features
•
Full-featured evaluation board for the ADS8364 and ADS8365 250-kHz, 16-bit, 6-channel,
simultaneous-sampling, analog-to-digital converter
•
•
Analog inputs can be configured as single-ended or differential
Modular design allows direct connection to various DSP platforms through the 5-6K and HPA-MCU
Interface Boards
•
•
Built-in reference
High-speed parallel interface
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Analog Interface
NOTE: Components marked NI are NOT INSTALLED.
Figure 1. Channel A0 Input Circuit
This configuration allows single-ended signals of ±2.5 V (+5 Vpp) to be applied to either input of channel
A0 (J2 pin 1 or 3 referenced to pin 2). The input also can be applied to connector J4 (not shown) pins 2 or
4, referenced to analog ground.
3.2 Bipolar Input to Channel A0
By changing components and setting the appropriate jumper, it is possible to configure the input buffer to
accept bipolar input voltages. Table 1 is related to the schematic presented in Figure 1 and represents just
a few of the possible input configurations.
Table 1. Typical Analog Input Buffer Circuit Values
Input Voltage
R3
R28
R2
R25
R1
R24
R4
R29
W2
W1
Default
0 – +5
open
5kΩ
5kΩ
5 kΩ
1–2
0 – 2.5
– 2.5 – +2.5
– 5 – +5
5 kΩ
20 kΩ
20 kΩ
20 kΩ
5 kΩ
4 kΩ
4 kΩ
4 kΩ
open
20 kΩ
10 kΩ
5 kΩ
5 kΩ
4 kΩ
2 kΩ
1 kΩ
2–3
2–3
2–3
2–3
– 10 – +10
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Digital Interface
The output from the buffer stage in each case applies 0-5 V to the CHA0(+) input when the applied signal
is connected to J2 pin 1 or J4 pin 2. The applied signal is directed to the CHA0(-) input when connected
via J2 pin 3 or J4 pin 4.
When operating the ADS836x with single-ended signals, it is important to keep the unused ADC input
biased to +2.5 V. This is easily accomplished on the EVM by changing the components associated with
either the inverting or noninverting input only, leaving the default component values shown in Table 1 on
the unused input. For example, to achieve a bipolar input range of ±10 V on CHA0(+), use the component
values shown for R1–R4 and move the shunt on W2 position 2-3. Components R24, R25, R28, and R29
3.3 Analog Input – Channel A1
The analog input to the ADS8364/65MEVM board for channel A1 is composed of the INA159 difference
amplifier and the associated circuitry as shown in Figure 2. The INA159 is powered from the +5-V analog
supply, and arranged as a noninverting amplifier with a gain of 0.2. The internal +2.5-V reference voltage
of the ADS836x is applied to both REF1 and REF2 pins of the INA159 to provide a direct ±10-V interface
with built-in level translation to the noninverting input of channel A1.
Figure 2. Channel A1 Input Circuit
3.4 Analog Inputs –Channels B0/B1 and C0/C1
The analog inputs to the remaining ADS836x input channels are routed to connector J3 and configured
with simple R/C filters only. This configuration allows the EVM user to apply any customized input circuit to
the data converter. Connector J3 is composed of a male/female pass-through combination of pin header
and socket with industry standard 0.1-inch centers.
When the ADS8364/65MEVM is used in combination with the 5-6K Interface Board or HPA-MCU Interface
Board, the DAP Signal Conditioning Board (SLAU105) can be used to drive the remaining input channels.
4
Digital Interface
The ADS8364/65MEVM is designed for easy interfacing to multiple control platforms. Jumper options are
provided on the EVM to allow control over the state of Chip Select pin (CS) as well as the operating mode
pins (A0–A2), the Reset pin (RST), and the Conversion Start strobes (HOLD A, HOLDB, and HOLDC).
4
ADS8364/65MEVM
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Digital Interface
Jumpers W4 and W6 control the signals applied to A0, A1, A2, and CS. In the factory default mode, W6 is
closed by means of a shunt jumper. The Ax and CS pins are controlled by the signals applied to J5 (top or
bottom side). When used with either the 5-6K or HPA-MCU Interface Boards, these control signals are
associated with the host processors address bus.
By removing the shunt jumper located at W6, the A0, A1, and A2 pins are controlled by shunt jumpers
placed on W4. The CS pin is routed to J5.1, which requires the application of an active-low Chip Select
signal. A simple shunt jumper placed across J5 pins 1-2 can be used to force the CS pin to ground if
desired.
4.1 Parallel Control
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin,
dual-row, header/socket combination at J5 (Table 2). This header/socket provides access to the digital
connector options.
Table 2. Header/Socket Combinations at J5
Pin Number
J5.1
Signal
Description
DC_CSa
DC_AWE
DC_ARE
EVM_A0
EVM_A1
EVM_A2
EVM_A3
EVM_A4
DC_TOUT
DC_INTa
Daughter Card Chip Select – active-low signal used to access the EVM
Write Strobe – signal not used on the ADS8364/65M EVM
Read Strobe – active-low signal used to access parallel data
EVM Address line 0 – used with U3 to control A0
EVM Address line 1 – used with U3 to control A1
EVM Address line 2 – used with U3 to control A2
EVM Address line 3 – used with U3 and U6 to control CS
EVM Address line 4 – not used
J5.3
J5.5
J5.7
J5.9
J5.11
J5.13
J5.15
J5.17
J5.19
Timer Input – optional CLK input used with W8
Interrupt Output to Host Processor – connects to the ADC EOC pin
4.2 Parallel Data
The ADS8364/65MEVM uses Samtec part numbers SSW-116-22-F-D-VS-K and TSM-116-01-T-DV-P to
provide a convenient 16-pin, dual-row header/socket combination at J6. This header/socket combination
provides access to the parallel data pins of the ADS7864. Data line D0 is connected to J6 pin 1. Data
lines 1–15 are located on pins 3–31, respectively. Even pin numbers 2–32 are connected to digital ground.
4.3 GPIO/Control Options
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a 10-pin, dual-row,
header/socket combination at J1 to facilitate general-purpose input/output (GPIO) control options to the
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Power Supplies
Table 3. J1 Pinout and Functions
Pin Number
Signal
NAP
Description
J1.1
Controls power-down options on the ADS8365 (only) using the NAP input pin
Controls read options, when HI, address information can be read from the chip
Active-low signal HOLDC used to start a conversion on ADC channel pair C
Active-low signal HOLDB used to start a conversion on ADC channel pair B
Active-low signal HOLDA used to start a conversion on ADC channel pair A
Active-low signal RESET used to place the ADS7864’s FIFO in reset state
Unused on the ADS8364/65MEVM
J1.3
ADD
J1.5
HOLD_C#
HOLD_B#
HOLD_A#
RESET#
NA
J1.7
J1.9
J1.11
J1.13
J1.15
J1.17
J1.19
NA
Unused on the ADS8364/65MEVM
DC_TOUTa Used with W10 to allow host processor timer control of HOLDx
NA Unused on the ADS8364/65MEVM
5
Power Supplies
The ADS8364/65MEVM board requires +5 VDC for the both the analog and digital section of the ADC.
The supply (+Va and +Vd) can range from +4.75 VDC to +5.25 VDC. . The internal buffer can be powered
through the BVdd input voltage and can range from 2.7 VDC to 5.5 VDC. Because the EVM is designed to
work with the 5-6K and HPA-MCU Interface Boards, JP1 provides direct connection to the common power
bus described in SLAU104.
Table 4. JP1 Pinout
Signal
+VA (positive input buffer supply)
+5VA (+Va to the ADS8364)
DGND
Pin Number
Signal
-VA (negative input buffer supply)
-5VA (Unused)
1
3
5
7
9
2
4
6
AGND
+1.8VD (Unused)
8
+VD1 (Unused)
+3.3VD (used with W5 for support circuitry)
10
+5VD (+5V to pin 22 of the ADS8364 and pin 22 of the
ADS8365)
Alternate power sources can be applied via various test points located on the EVM. See the schematic at
the end of this document for details. Note – while filters are provided for all power supply inputs, optimal
performance of the EVM requires a clean, well-regulated power source.
5.1 Reference Voltages
The ADS8364/65MEVM is configured to use its internal reference through jumper W3 (see schematic for
details). If an external reference is desired, the shunt jumper on W3 should be moved to cover pins 1-2;
the external reference source can be applied to the test point labeled TP10 referenced to TP12. The
internal +2.5-V reference is still connected to the input buffer U1 in this case to ensure proper mid-point
biasing to channel A1.
6
EVM Operation
The analog input swing is 5 Vpp, centered on a +2.5-V internal or external reference. The installed device
accepts bipolar input ranges when a level shift circuit is used in the analog front-end circuitry. For
information on various circuit configurations, see section 3.2 of this document or section 12 of Op-Amps
for Everyone (SLOD006) .
Once power is applied to the EVM, the analog input source can be connected directly to J3 or J4 (top or
bottom side) or through optional amplifier and signal-conditioning modules using the 5-6K and HPA-MCU
Interface Boards. The analog input level should not exceed 5 Vp-p. The analog input range is from ±Vref
(typically 2.5 VDC) centered at +2.5 V.
6
ADS8364/65MEVM
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EVM Bill of Materials, Assembly Drawing, and Schematic
The digital control signals can be applied directly to J1 and J5 (top or bottom side). The
ADS8364/65MEVM can also be connected directly to the 5-6K Interface Board for use with a variety of
C5000™ and C6000™ series DSP Starter Kits (DSK), or the HPA-MCU Interface Board for use with
C2000™ Series DSPs and TMS470™ Series controllers. The Control and Data connectors are designed
to allow pattern generators and/or logic analyzers to be connected to the EVM using standard ribbon-type
cables on 0.1-inch centers.
The BYTE signal, which controls the output of the ADS836x when used with 8-bit controllers, can be
manipulated with jumper W7. By default, W7 is closed and the BYTE pin is held low, providing data in
16-bit format. Removing the shunt at W7 asserts BYTE high by means of pullup resistor R23.
The conversion clock can be applied to J7, a BNC connector with a 50-Ω terminator, or J5 as mentioned
previously. Jumper W8 allows the EVM user to select the clock source. In normal operation (factory
default) the shunt on jumper W8 is covering pins 2-3. To use a clock source applied to the BNC connector
J7, move the shunt at jumper W8 to cover pins 1-2. In either case, the conversion clock can be monitored
at TP21.
6.1 Default Jumper Locations
Table 5. ADS8364/65MEVM Jumpers
Jumper
W1
Shunt Position Jumper Description
Pins 1-2
Pins 1-2
Pins 2-3
OPEN
Controls CHA1(+) input source selection
W2
Controls CHA1(–) input source selection
Controls reference source (default is internal)
3x2 Jumper to control A0, A1, A2
Controls BVdd Selection
W3
W4
W5
Pins 1-2
Closed
W6
Controls application of A0, A1 and A2 signals as well as the chip select input. Used in conjunction
with W4.
W7
W8
W9
W10
Closed
Pins 2-3
NA
Controls BYTE input, opening W7 forces BYTE high via R23
Controls application of conversion clock source via J5 or J7
W9 pins 2-3 are wired short on the PWB
TIMER
3×3 Jumper to control HOLDx signals – timer or GPIO options available
7
EVM Bill of Materials, Assembly Drawing, and Schematic
7.1 Bill of Materials
Table 6. ADS8364/65MEVM Bill of Materials
Designators
Description
Manufacturer
Mfg. Part Number
C2 C3 C7 C10–C12 0.1uF, 0603, Ceramic, X7R, 25V, 10%
TDK Corp.
C1608X7R1E104K
C18 C37–C39 C41
C45–C49 C52
C35 C36 C42–C44
C53
1nF, 0603, Ceramic, COG, 50V, 5%
TDK Corp.
C1608C0G1H102J
EMK212BJ106KG-T
C5 C6 C8 C9 C13
C15
10µF, 0805, Ceramic, X5R, 16V, 10%
Taiyo Yuden
C1 C19
33pF, 0805, Ceramic, COG, 50V, 5%
0.01µF, 0603, Ceramic, COG, 25V, 5%
100pF, 0603, Ceramic, COG, 50V, 5%
1µF, 0603, Ceramic, X7R, 16V, 10%
TDK Corp.
TDK Corp.
TDK Corp.
TDK Corp.
C1608C0G1H330J
C1608C0G1E103J
C1608C0G1H101J
C1608X7R1C105K
C22 C24
C16 C14 C25–C34
C50
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EVM Bill of Materials, Assembly Drawing, and Schematic
Table 6. ADS8364/65MEVM Bill of Materials (continued)
Designators
D1 D2
Description
Manufacturer
Chicago Miniature
Samtec
Mfg. Part Number
CMD15-21VGC/TR8
SSW-110-22-S-D-VS
Green LED
10 Pin, Dual Row, SMT Socket (20 Pos.)
J1 J3–J5(Bottom
Side)
J1 J3–J5 (Top Side) 10 Pin, Dual Row, SMT Header (20 Pos.)
Samtec
TSM-110-01-T-D-V-P
ED555/3DS
J2
3 Terminal Screw Connector
On-Shore Tech.
Samtec
J6 (Bottom Side)
J6 (Top Side)
J7
16 Pin, Dual Row, SMT Socket (32 Pos.)
16 Pin, Dual Row, SMT Header (32 Pos.)
PCB Mount BNC
SSW-116-22-S-D-VS
TSM-116-01-T-D-V-P
31-5329
Samtec
Amphenol
Samtec
JP1(Bottom Side)
JP1 (Top Side)
FB1–FB5
5 Pin, Dual Row, SMT Socket (10 Pos.)
5 Pin, Dual Row, SMT Header (10 Pos.)
0805 size Ferrite Bead
SSW-105-22-S-D-VS
TSM-105-01-T-D-V-P
MMZ2012D121B
9C08052A4991FKHFT
Samtec
TDK Corp.
Yageo Corp.
R1 R2 R4 R24 R25 4.99kΩ, 1%, 0805, .1W Resistor
R29
R5–R14 R20 R21
R31 R36
49.9 Ω, 0603, 1%, 0.1W Resistor
Yageo Corp.
Yageo Corp.
RC0603FR-0749R9L
RC0603JR-0710KL
R16–R19 R22 R23
R34 R35
10kΩ, 0603, 5%, 0.1W Resistor
R26 R27
R15 R32
2kΩ, 0805, 0.1W Resistor
0 Ω, 0603, 0.1W Resistor
Red Test Point Loop
Yageo Corp.
Yageo Corp.
Keystone
9C08052A2001JLHFT
RC0603JR-070RL
5000
TP1–TP3 TP8 Tp9
TP10 TP20
AGND DGND TP12 Black Test Point Loop
Keystone
Keystone
5001
5015
TP11 TP13–TP17
TP21–TP24
SMT Test Point Loop – Shown on Silkscreen as: A0,
A1, A2, RST, RD, WR, CS, CLOCK, FD, EOC
OPA2132, SOIC
OPA2340; DGK package
ADS8364
U1
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Samtec
OPA2132UA
U2
OPA2340EA
U4
ADS8364Y/250
INA159AIDGKR
SN74CBT3257PWR
SN74AHC1G04DBVT
SN74AHC125PW
TSW-103-07-L-S
TSW-102-07-L-S
TSW-103-07-L-D
TSM-103-07-L-T
U5
INA159; DGK package
SN74CBT3257PW
SN74AHC1G04
U3
U6
U7
SN74AHC125
W1–W3 W5 W8
W6 W7
W4
3 Pin Header
2 Pin Header
Samtec
2×3 Header
Samtec
W10
3×3 Header
Samtec
C4 C17 C20 C21
C23 C51 R3 R28
R33 W9
Not Installed
8
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EVM Bill of Materials, Assembly Drawing, and Schematic
7.2 Assembly Drawing
designator found on the PWB. Complete Gerber files are available on request.
Figure 3. ADS8364/654MEVM Assembly Drawing
7.3 Circuit Schematics
The entire circuit schematic for the ADS8364/65MEVM appears on the following page.
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1
2
3
4
5
6
Revision History
REV
ECN Number
Approved
Note:
Components marked "NI"
are NOT installed!
C1
33pF
W1
TP7
R2
R4
4.99K
4.99K
-Vin
D
C
B
A
D
C
B
A
Op Amp Bypass
+Vin
U1A
J2
2
3
R8
R14
49.9
R12
49.9
A0In
1
C0+
A0+
B0+
R3
NI
49.9
1
C24
0.01uF
C23
NI
C26
100pF
OPA2132
C31
100pF
C29
100pF
C4
2
3
NI
+Vin
R1
C22
0.01uF
C21
NI
Vref
4.99K
C19
C42
1nF
C43
1nF
-Vin
C44
1nF
33pF
W2
TP6
R25
R29
4.99K
4.99K
U1B
6
5
R7
49.9
R13
49.9
R11
49.9
7
C0-
A0-
B0-
R28
NI
C25
100pF
OPA2132
C30
100pF
C34
100pF
C20
NI
J4
AVdd
R24
4.99K
Vref
1
3
5
7
9
2
4
6
8
10
C17
NI
R33
NI
Vref
11 12
13 14
15 16
17 18
19 20
U5
REF1
1
2
8
5
REF2
W9
Wire Short
SENSE
Analog Input
IN-
R21
49.9
6
OUT
A1+
3
4
IN+
AVdd
C16
100pF
C51
NI
R9
49.9
R5
49.9
7
V-
V+
B1+
C1+
INA159
C53
1nF
C18
0.1uF
C27
100pF
C32
100pF
R20
49.9
A1-
C50
1uF
C14
100pF
C36
1nF
C35
1nF
R10
49.9
R6
49.9
B1-
C1-
J3
C28
100pF
C33
100pF
1
3
5
7
9
2
4
6
8
10
11 12
13 14
15 16
17 18
19 20
ti
A
12500 TI Boulevard. Dallas, Texas 75243
Analog Input
Title:
ADS8364/65 Modular Evaluation Module
Tom Hendrick
Tom Hendrick
Engineer:
Drawn By:
FILE:
B
SIZE:
DATE:
REV:
14-Jul-2006
SHEET:
OF:
1
3
mADS8364_2_SH1.Sch
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2
3
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1
2
3
4
5
6
ADC Bypass
DVdd AVdd
J5
BVdd
DC_CSa
DC_AWE
DC_ARE#
A0
A1
A2
BVdd
1
3
5
7
9
2
4
6
C12
C48
0.1uF
C47
0.1uF
C46
0.1uF
C40
0.1uF
C39
C38
C37
0.1uF
8
AVdd
DVdd
BVdd
0.1uF
0.1uF
0.1uF
10
U3
1B1
11 12
13 14
15 16
17 18
19 20
A3
4
7
2
3
BA0
BA1
BA2
CS#
EVM_A0
EVM_A1
EVM_A2
1A
2A
3A
4A
D
C
B
A
D
C
B
A
1B2
DC_TOUT
DC_INTa
BGND
TP17
TP13
5
6
2B1
2B2
TP21
Parallel Control
TP15
28
9
11
10
CLK
CLK
3B1
3B2
BVdd
C52
J7
TP14
M_A0
M_A1
M_A2
0.1uF
63
64
51
52
12
14
13
RESET#
ADD
DC_TOUT
A0+
A0-
A0+
A0-
RESET#
ADD
4B1
4B2
U7
W8
1
2
4
5
10
9
13
12
R31
49.9
TP22
BVdd
1OE
1
2
53
54
55
BA2
BA1
BA0
BVdd
EVM_A0 3
A0
A1
A3
A2
A1-
A1+
A1-
A1+
A2
A1
A0
R19
10K
1Y
1A
2OE
2A
3OE
3A
4OE
4A
1
15
S
/OE
U6
6
8
EVM_A1
EVM_A3
R22
10K
2Y
3Y
4Y
5
A_REF
4
2
EVM_A3
56
57
58
HOLD_A#
HOLD_B#
HOLD_C#
HOLD_A#
HOLD_B#
HOLD_C#
SN74CBT3257PWR
SN74X1G04
DC_CSa
6
7
11
EVM_A2
B0+
B0-
B0+
B0-
TP11
TP24
SN74AHC125
26
27
FD
DC_INTa
FD
EOC#
BVdd
W6
11
12
B1-
B1+
B1-
B1+
TP16
29
30
DC_ARE#
DC_AWE
RD#
WR#
10
U4
ADS8364/65
B_REF
J6
BVdd
BVdd
TP23
DC_D0
DC_D1
DC_D2
DC_D3
DC_D4
DC_D5
DC_D6
DC_D7
DC_D8
DC_D9
DC_D10
DC_D11
DC_D12
DC_D13
DC_D14
DC_D15
R16
10K
R17
10K
R18
10K
31
CS#
1
2
4
6
8
10
CS#
16
17
3
5
7
9
C0+
C0-
C0+
C0-
R35
10K
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R34
10K
DC_D0
DC_D1
DC_D2
DC_D3
DC_D4
DC_D5
DC_D6
DC_D7
DC_D8
DC_D9
DC_D10
DC_D11
DC_D12
DC_D13
DC_D14
DC_D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
M_A0
M_A1
M_A2
J1
18
19
C1-
C1+
C1-
C1+
/NAP
ADD
GP(CLKR)
GP(FSX)
GP(FSR)
RESET#
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
1
2
4
6
8
10
11 12
13 14
15 16
17 18
19 20
3
5
7
9
15
C_REF
W4
TP8
62
61
W10
REFIN
D9
GP(CLKR)
GP(FSX)
GP(FSR)
D10
D11
D12
D13
D14
D15
DC_TOUTa
REFOUT
ADC Control
HOLD_A#
HOLD_B#
HOLD_C#
ADC Data Bus
McBSP 1 Setup
23
BYTE
BVdd
ADD = CLKX1 (GP OUT)
HOLD A# = CLKR1 (GP OUT)
HOLD B# = FSX1 (GP OUT)
HOLD C# = FSR1 (GP OUT)
RESET# = DX1 (GP OUT)
FD = DR1 (GP IN)
R23
10K
W7
R15
0 ohm
BGND
+3.3VD +1.8VD +5VA +VA
-VA -5VA +VD1 +5VD
JP1
W3
EXT. REF.
TP10
1
2
4
6
3
5
7
9
C8
10uF
C7
0.1uF
8
10
AVdd
C45
TP12
R36
49.9
DGND
+5VD
AGND
+VIN
DVdd
+VA
AVdd
+5VA
TP9
TP2
0.1uF
FB1
C49
FB3
R26
U2B
5
TP3
U2A
2K
FB5
C15
3
2
7
C6
10uF
D2
Green
C3
0.1uF
1
6
10uF
Vref
0.1uF
C9
10uF
C10
0.1uF
C41
0.1uF
OPA2340
OPA2340
+5VD
+3.3VD
-VIN
-VA
W5
TP1
BVdd
FB4
R27
TP20
2K
C5
FB2
ti
DATE:
D1
Green
C2
0.1uF
12500 TI Boulevard. Dallas, Texas 75243
10uF
C13
Title:
C11
10uF
R32
0 ohm
0.1uF
ADS8364/65 Modular Evaluation Module
Tom Hendrick
Tom Hendrick
Engineer:
Drawn By:
FILE:
SIZE:
REV:
B
14-Jul-2006
A
BGND
2
SHEET:
OF:
3
1
2
3
4
5
6
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Related Documentation From Texas Instruments
8
Related Documentation From Texas Instruments
1. ADS8364, 250kHz, 16-Bit, 6-Channel Simultaneous Sampling Analog-to-Digital Converters data sheet
(SBAS219)
2. ADS8365, 250kHz, 16-Bit, 6-Channel Simultaneous Sampling Analog-to-Digital Converter data sheet
(SBAS362)
3. OPA2132, High-Speed FET-Input Operational Amplifiers data sheet (SBOS054)
4. INA159, Precision Gain of 0.2 Level Translation Difference Amplifier data sheet (SBOS333)
5. 5-6K Interface Board User's Guide (SLAU104)
6. DAP Signal Conditioning Board User's Guide (SLAU105)
7. ×HPA-MCU Interface Board User's Guide (SLAU106)
8. Designing Modular EVMs for Data Acquisition Products application report (SLAA185)
9. Data Converters for Industrial Power Management application report (SBAA117)
10. Op-Amps for Everyone application report (SLOD006)
10
ADS8364/65MEVM
SLAU189–September 2006
Submit Documentation Feedback
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