6,4 mm X 9,7 mm
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
4-V TO 6-V INPUT, 8-A OUTPUT SYNCHRONOUS BUCK PWM
SWITCHER WITH INTEGRATED FETS (SWIFT™)
FEATURES
DESCRIPTION
D
D
D
D
D
30-mΩ MOSFET Switches for High Efficiency
at 8-A Continuous Output
0.9-V to 3.3-V Adjustable Output Voltage
Range With 1% Accuracy
Externally Compensated
Fast Transient Response
As a member of the SWIFT™ family of dc/dc regulators,
the TPS54810 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance under transient conditions and flexibility in
choosing the output filter L and C components; an
under-voltage-lockout circuit to prevent start-up until
the input voltage reaches 3.8 V; an internally or
externally set slow-start circuit to limit in-rush currents;
and a power good output useful for processor/logic
reset, fault signaling, and supply sequencing.
Wide PWM Frequency:
Fixed 350 kHz, 550 kHz or
Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
D
D
The TPS54810 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT™ designer software tool to aid
in quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
APPLICATIONS
D
D
Low-Voltage, High-Density Systems With
Power Distributed at 5 V
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
D
D
Broadband, Networking, and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
EFFICIENCY AT 700 HZ
SIMPLIFIED SCHEMATIC
Input
100
V = 5 V
I
Output
95
90
85
80
75
70
65
60
55
50
V
= 3.3 V
O
VIN
PH
TPS54810
BOOT
PGND
VBIAS
AGND
COMP
VSENSE
0
1
2
3
4
5
6
7
8
9
10
Compensation Network
I
− Load Current − A
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright © 2002, Texas Instruments Incorporated
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
T = −40°C to 125°C, V = 4 V to 6 V unless otherwise noted
J
I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
4.0
6.0
V
f = 350 kHz, SYNC ≤ 0.8 V, RT open,
PH pin open
s
11
15.8
f = 550 kHz, SYNC ≥ 2.5 V, RT open,
PH pin open
I
Quiescent current
mA
s
(Q)
16
23.5
1.4
Shutdown, SS/ENA = 0 V
1.0
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
Rising and falling edge deglitch, UVLO
BIAS VOLTAGE
3.8
3.50
0.16
2.5
3.85
V
V
3.40
0.14
V
(1)
µs
Output voltage, VBIAS
I
= 0
2.70
2.80
2.90
100
V
(VBIAS)
(2)
Output current, VBIAS
µA
CUMULATIVE REFERENCE
V
ref
Accuracy
0.882 0.891 0.900
V
REGULATION
I = 4 A, f = 350 kHz, T = 85°C
0.04
0.04
0.03
0.03
L
s
J
(1) (3)
(1) (3)
Line regulation
%/V
%/A
I = 4 A, f = 550 kHz, T = 85°C
L
s
J
I = 0 A to 8 A, f = 350 kHz, T = 85°C
L
s
J
Load regulation
OSCILLATOR
I = 0 A to 8 A, f = 550 kHz, T = 85°C
L
s
J
SYNC ≤ 0.8 V, RT open
280
440
252
460
663
2.5
350
550
280
500
700
420
660
308
540
762
Internally set—free running frequency range
kHz
kHz
SYNC ≥ 2.5 V, RT open
RT = 180 kΩ (1% resistor to AGND)
RT = 100 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND)
Externally set—free running frequency range
High level threshold, SYNC
V
V
Low level threshold, SYNC
0.8
(1)
Pulse duration, external sychronization, SYNC
50
ns
kHz
V
(1)
Frequency range, SYNC
330
700
(1)
Ramp valley
0.75
1
(1)
Ramp amplitude (peak-to-peak)
V
(1)
Minimum controllable on time
200
ns
(1)
Maximum duty cycle
90%
(1)
(2)
(3)
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 9
3
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS CONTINUED
T = −40°C to 125°C, V = 4 V to 6 V unless otherwise noted
J
I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
(1)
Error amplifier open loop voltage gain
Error amplifier unity gain bandwidth
1 kΩ COMP to AGND
90
110
dB
(1)
Parallel 10 kΩ, 160 pF COMP to AGND
3
5
MHz
Error amplifier common mode input voltage
range
(1)
Powered by internal LDO
0
VBIAS
250
V
Input bias current, VSENSE
VSENSE = V
60
nA
ref
Output voltage slew rate (symmetric), COMP
1.0
1.4
V/µs
PWM COMPARATOR
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding dead-
time)
(1)
10-mV overdrive
70
85
ns
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
Enable hysteresis voltage, SS/ENA
0.82
1.20
0.03
2.5
3.35
5
1.40
V
V
(1)
(1)
Falling edge deglitch, SS/ENA
µs
ms
µA
mA
Internal slow-start time
2.6
3
4.1
8
Charge current, SS/ENA
Discharge current, SS/ENA
SS/ENA = 0V
SS/ENA = 1.3 V, V = 1.5 V
1.5
2.3
4.0
I
POWER GOOD
Power good threshold voltage
Power good hysteresis voltage
VSENSE falling
90
3
%V
ref
(1)
(1)
%V
ref
Power good falling edge deglitch
35
µs
V
Output saturation voltage, PWRGD
Leakage current, PWRGD
I
= 2.5 mA
0.18
0.3
1
(sink)
V = 3.6 V
I
µA
CURRENT LIMIT
(1)
V = 4.5 V , output shorted
9
11
12
I
Current limit
A
(1)
V = 6 V , output shorted
10
I
Current limit leading edge blanking time
Current limit total response time
100
200
ns
ns
THERMAL SHUTDOWN
Thermal shutdown trip point
(1)
(1)
135
150
10
165
_C
Thermal shutdown hysteresis
OUTPUT POWER MOSFETS
_C
(2)
V = 6 V
26
30
47
60
I
r
Power MOSFET switches
mΩ
DS(on)
(2)
V = 4.5 V
I
(1)
(2)
Specified by design
Matched MOSFETs, low-side r
production tested, high-side r
production tested.
DS(on)
DS(on)
4
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
PWP PACKAGE
(TOP VIEW)
1
2
3
28
AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
27
26
25
24
23
22
21
20
19
18
17
16
15
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
4
5
6
7
8
9
PH
PH
PH
PH
PH
PH
PH
PH
THERMAL
PAD
VIN
VIN
10
11
12
13
14
PGND
PGND
PGND
PGND
PGND
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and
SYNC pin. Connect PowerPAD to AGND.
BOOT
5
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
PGND
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors. A single point
connection to AGND is recommended.
PH
6−14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High-Z when VSENSE ≥ 90% V , otherwise PWRGD is low. Note that output is low
ref
when SS/ENA is low or the internal shutdown signal is active.
RT
28
26
27
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the
SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
SS/ENA
SYNC
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select
between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
VIN
device package with a high quality, low-ESR 10-µF ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
5
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
FUNCTIONAL BLOCK DIAGRAM
VBIAS
AGND
VBIAS
VIN
Enable
Comparator
SS/ENA
REG
Falling
Edge
SHUTDOWN
VIN
ILIM
Comparator
1.2 V
3 − 6 V
Deglitch
Thermal
Hysteresis: 0.03 V
Leading
Edge
Blanking
Shutdown
2.5 µs
150°C
VIN UVLO
Comparator
Falling
100 ns
and
Rising
Edge
VIN
BOOT
3.8 V
Deglitch
Hysteresis: 0.16 V
30 mΩ
2.5 µs
SS_DIS
SHUTDOWN
L
OUT
V
O
PH
Internal/External
Slow-Start
(Internal Slow-Start Time = 3.35 ms)
+
C
O
Adaptive Dead-Time
and
Control Logic
R
S
Q
−
Error
Amplifier
PWM
Comparator
Reference
VIN
VREF = 0.891 V
30 mΩ
OSC
PGND
Powergood
Comparator
PWRGD
VSENSE
0.90 V
Falling
Edge
Deglitch
ref
TPS54810
Hysteresis: 0.03 Vref
SHUTDOWN
35 µs
SYNC
VSENSE
COMP
RT
RELATED DC/DC PRODUCTS
D
D
TPS56300—dc/dc controller
PT6600 series—9-A plugin modules
6
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
60
50
40
30
20
750
650
550
V = 5 V,
I
I
= 8 A
O
SYNC ≥ 2.5 V
450
SYNC ≤ 0.8 V
350
250
10
0
−40 −15 10
35
60
85
110 135
−40
0
25
85
125
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 1
Figure 2
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
DEVICE POWER LOSSES
vs
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
LOAD CURRENT
JUNCTION TEMPERATURE
5
0.895
0.893
0.891
0.889
800
700
600
T
J
= 125°C
4.5
f
= 700 kHz
s
4
RT = 68 k
RT = 100 k
RT = 180 k
3.5
3
2.5
2
500
400
300
200
1.5
1
V = 5 V
I
0.887
0.885
0.5
0
0
1
2
3
4
5
6
7
8
−40
0
25
85
125
−40
0
25
85
125
I
− Load Current − A
L
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 5
Figure 3
Figure 4
OUTPUT VOLTAGE REGULATION
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
ERROR AMPLIFIER
OPEN LOOP RESPONSE
vs
INPUT VOLTAGE
0.895
0.893
0
140
3.80
R
C
T
= 10 kΩ,
= 160 pF,
= 25°C
L
L
−20
−40
−60
−80
120
100
80
3.65
3.50
A
Phase
Gain
0.891
0.889
3.35
−100
−120
−140
−160
−180
−200
60
3.20
3.05
40
20
0.887
0.885
2.90
2.75
0
−20
4.5
4.8
5.1
5.4
5.7
6
1
10 100 1 k 10 k 100 k 1 M 10 M
−40
0
25
85
125
V − Input Voltage − V
I
f − Frequency − Hz
T
J
− Junction Temperature − °C
Figure 6
Figure 7
Figure 8
7
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
APPLICATION INFORMATION
TPS54810 application. The TPS54810 (U1) can provide
up to 8 A of output current at a nominal output voltage of
1.8 V. For proper thermal performance, the PowerPAD
underneath the integrated circuit TPS54810 needs to be
soldered well to the printed-circuit board.
V
I
C10
C12
U1
10 µF
10 µF
TPS54810PWP
R6
71.5 kΩ
27
28
24
23
22
21
RT
VIN
VIN
VIN
VIN
VIN
PH
PH
PH
PH
PH
PH
PH
PH
R5
10 kΩ
SYNC
SS/ENA
26
25
20
14
13
C6
0.047 µF
C3
VBIAS
PWRGD
COMP
12
1 µF
4
3
11
L1
10
9
0.65 µH
C1
C4
R2
R3
10 kΩ
V
O
8
7
6
301 Ω
C8
22 µF
C7
22 µF
C5
22 µF
1000 pF
R1
3300 pF
C2
PH
BOOT
PGND
PGND
C9
150 pF
2
1
5
VSENSE
10 kΩ
19
18
17
16
15
0.047 µF
R7
2.4 Ω
R4
9.76 kΩ
PGND
PGND
PGND
AGND
C11
3300 pF
PWRPAD
Analog and Power Grounds are Tied at the Pad Under the Package of IC
Figure 9. Application Circuit
at 1.8 V. R1, along with R2, R3, C1, C2, and C4 forms the
loop compensation network for the circuit. For this design,
a Type 3 topology is used.
COMPONENT SELECTION
The values for the components used in this design
example were selected for low output ripple voltage and
small PCB area. Additional design information is available
OPERATING FREQUENCY
In the application circuit, RT is grounded through a 71.5 kΩ
resistor to select the operating frequency of 700 kHz. To
set a different frequency, place a 68 kΩ to 180 kΩ resistor
between RT (pin 28) and analog ground or leave RT
floating to select the default of 350 kHz. The resistance can
be approximated using the following equation:
INPUT FILTER
The input voltage is a nominal 5 VDC. The input filter C10
is a 10-µF ceramic capacitor (Taiyo Yuden). C12, also a
10-µF ceramic capacitor (Taiyo Yuden) provides high
frequency decoupling of the TPS54810 from the input
supply and must be located as close as possible to the
device. Ripple current is carried in both C10 and C12, and
the return path to PGND should avoid the current
circulating in the output capacitors C5, C7, and C8.
500 kHz
Switching Frequency
R +
100 [kW]
(1)
OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor and
3 x 22-µF capacitor. The inductor is a low dc resistance
(0.017 Ω) type, Pulse Engineering PA0277. The
capacitors used are 22-µF, 6.3 V ceramic types with X5R
dielectric. The feedback loop is compensated so that the
unity gain frequency is approximately 75 kHz.
FEEDBACK CIRCUIT
The values for these components have been selected to
provide low output ripple voltage. The resistor divider
network of R1 and R4 sets the output voltage for the circuit
8
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
capacitors, the input voltage decoupling capacitor, and the
PGND pins of the TPS54810. Use a separate wide trace
for the analog ground signal path. The analog ground is
used for the voltage set point divider, timing resistor RT,
slow-start capacitor and bias capacitor grounds. Connect
this trace directly to AGND (Pin 1).
PCB LAYOUT
Figure 10 shows a generalized PCB layout guide for the
TPS54810
The VIN pins are connected together on the printed-circuit
board (PCB) and bypassed with
a
low-ESR
ceramic-bypass capacitor. Care should be taken to
minimize the loop area formed by the bypass capacitor
connections, the VIN pins, and the TPS54810 ground
pins. The minimum recommended bypass capacitance is
10-µF ceramic capacitor with a X5R or X7R dielectric and
the optimum placement is closest to the VIN pins and the
PGND pins.
The PH pins are tied together and routed to the output
inductor. Since the PH connection is the switching node,
the inductor is located close to the PH pins. The area of the
PCB conductor is minimized to prevent excessive
capacitive coupling.
Connect the boot capacitor between the phase node and
the BOOT pin as shown Keep the boot capacitor close to
the IC and minimize the conductor trace lengths.
The TPS54810 has two internal grounds (analog and
power). Inside the TPS54810, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. Noise injected between the
two grounds can degrade the performance of the
TPS54810, particularly at higher output currents. Ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground traces are
recommended. There is an area of ground on the top layer
directly under the IC, with an exposed area for connection
to the PowerPAD. Use vias to connect this ground area to
any internal ground planes. Additional vias are also used
at the ground side of the input and output filter capacitors.
The AGND and PGND pins are tied to the PCB ground by
connecting them to the ground area under the device as
shown. The only components that tie directly to the power
ground plane are the input capacitors, the output
Connect the output filter capacitor(s) as shown between
the VOUT trace and PGND. It is important to keep the loop
formed by the PH pins, L , C
OUT OUT
and PGND as small as
practical.
Place the compensation components from the VOUT trace
to the VSENSE and COMP pins. Do not place these
components too close to the PH trace. Due to the size of
the IC package and the device pin-out, they must be routed
close, but maintain as much separation as possible while
still keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to analog
ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC
pin is used to select 350-kHz operating frequency, connect
them to this trace.
9
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
ANALOG GROUND TRACE
AGND
FREQUENCY SET RESISTOR
RT
SLOW ST ART
CAPACITOR
SYNC
SS/ENA
VBIAS
VSENSE
COMP
COMPENSA TION
NETWORK
BIAS CAP ACITOR
PWRGD
BOOT
BOOT
CAPACITOR
VIN
VIN
EXPOSED
POWERP AD
AREA
PH
PH
PH
PH
VOUT
VIN
VIN
VIN
PH
VIN
PGND
PGND
PGND
PGND
PGND
PH
PH
PH
PH
PH
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
TOPSIDE GROUND AREA
VIAto Ground Plane
Figure 10. PCB Layout
10
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
any area available should be used when 8 A or greater
operation is desired. Connection from the exposes area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the twelve recommended
that enhance thermal performance should be included in
areas not under the device package.
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Ø0.0130
8 PL
4 PL Ø0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0150
0.06
0.0339
0.0650
0.0500
0.3820 0.3478
0.2090
0.0256
0.0500
0.0500
0.0650
0.0339
Minimum Recommended Exposed
Copper Area for Powerpad. 5-mil
Stencils May Require 10 Percent
0.1700
Larger Area
0.1340
0.0630
0.0400
Minimum Recommended Top
Side Analog Ground Area
Figure 11. Recommended Land Pattern for the 28−Pin PWP PowerPAD
11
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
PERFORMANCE GRAPHS (FROM APPLICATION CIRCUIT SHOWN IN FIGURE 9)
EFFICIENCY
vs
LOAD REGULATION
vs
LINE REGULATION
vs
OUTPUT CURRENT
OUTPUT CURRENT
INPUT VOLTAGE
100
95
90
85
80
75
70
65
60
55
50
1.001
1.0008
1.0006
1.0004
1.0002
1.003
1.002
1.001
1
V = 5 V
I
V = 5 V
V = 5 V
I
I
V
= 1.8 V
O
V
T
= 1.8 V
= 25°C
V
T
= 1.8 V
= 25°C
O
O
8 A
f
= 700 kHz
s
A
A
f
= 700 kHz
f
= 700 kHz
s
s
1
0.9998
0.9996
0.9994
4 A
0 A
0.999
0.998
0.997
0.9992
0.999
0
2
4
6
8
10
0
2
4
6
8
10
4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9
− Input Voltage − V
I
− Output Current − A
O
I
− Output Current − A
V
I
O
Figure 13
Figure 14
Figure 12
AMBIENT TEMPERATURE
vs
(1)
OUTPUT CURRENT
OUTPUT RIPPLE VOLTAGE
TRANSIENT RESPONSE
125
T
f
= 25°C
= 700 kHz
V = 5 V
I
V = 5 V
I
J
115
105
95
V
I
= 1.8 V
= 6 A
s
O
O
f
= 700 kHz
V = 5 V
I
s
85
75
65
55
45
35
25
2 A to 6.5 A
t − Time − 20 µs/div
t − Time − 1 µs/div
0
1
2
3
4
5
6
7
8
I
− Output Current − A
O
Figure 16
Figure 17
Figure 15
SLOW-START TIMING
V = 5 V,
I
0.04 µF
Slow-start Cap
4.0 ms/div
Figure 18
(1)
Safe operating area is applicable to the test board conditions in the Dissipation Ratings
12
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND.
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
The TPS54810 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 3.80 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
3.5 V. Hysteresis in the UVLO comparator, and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
Voltage Reference
The voltage reference system produces a precise V
ref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54810, since it cancels
offset errors in the scale and error amplifier circuits.
Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions. First, the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is
required for the application, the oscillator frequency can be
externally adjusted from 280 to 700 kHz by connecting a
resistor between the RT pin and AGND and floating the
SYNC pin. The switching frequency is approximated by
the following equation, where R is the resistance from RT
to AGND:
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and
AGND.
Adding a capacitor to the SS/ENA pin has two effects on
start-up. First, a delay occurs between release of the
SS/ENA pin and start up of the output. The delay is
proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
100 kW
Switching Frequency +
500 [kHz]
R
(4)
External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a
resistor from RT to AGND. Choose an RT resistor which
sets the free running frequency to 80% of the
synchronization signal. The following table summarizes
the frequency selection configurations:
1.2 V
5 mA
t + C
d
(SS)
(2)
Second, as the output becomes active, a brief ramp-up at
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
ramp-up time set by the capacitor is approximately:
SWITCHING FRE-
QUENCY
SYNC PIN
RT PIN
350 kHz, internally set
550 kHz, internally set
Float or AGND
=2.5 V
Float
Float
Externally set 280 kHz Float
to 700 kHz
R = 68 k to 180 k
0.7 V
5 mA
t
+ C
(d)
(SS)
Externally synchro-
nized frequency
Synchronization R = RT value for 85%
signal
(3)
of external synchro-
nization frequency
The actual ramp-up time is likely to be less than the above
approximation due to the brief ramp-up at the internal rate.
Error Amplifier
VBIAS Regulator (VBIAS)
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54810 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
13
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
particular application needs. Type 2 or type 3 compensa-
tion can be employed using external compensation
components.
FET is below 2 V. While the low-side driver does not turn
on until the voltage at the gate of the high-side MOSFET
is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
PWM Control
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is reset, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
Overcurrent Protection
The cycle by cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold.
The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100 ns leading edge
blanking circuit prevents false tripping of the current limit
when the high side switch is turning on. Current limit
detection occurs only when current flows from VIN to PH
when sourcing current to the output filter. Load protection
during current sink operation is provided by thermal
shutdown.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54810 is capable of sinking current continuously
until the output reaches the regulation set-point.
Thermal Shutdown
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point,
and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
starting up by control of the soft-start circuit, heating up due
to the fault condition, and then shutting down upon
reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
Power Good (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or SS/ENA is low. When
VIN ≥ UVLO threshold, SS/ENA ≥ enable threshold, and
Dead-Time Control and MOSFET Drivers
VSENSE > 90% of V , the open drain output of the
ref
PWRGD pin is high. A hysteresis voltage equal to 3% of
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the voltage at the gate of the low-side
V
ref
and a 35 µs falling edge deglitch circuit prevent
tripping of the power good comparator due to high
frequency noise.
14
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PACKAGE OPTION ADDENDUM
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
TPS54810PWP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
PWP
28
28
28
28
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS54810PWPG4
TPS54810PWPR
TPS54810PWPRG4
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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PACKAGE MATERIALS INFORMATION
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS54810PWPR
HTSSOP PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
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PACKAGE MATERIALS INFORMATION
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TPS54810PWPR
2000
Pack Materials-Page 2
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