TMS320DM357 DMSoC Universal Serial Bus
(USB) Controller
User's Guide
Literature Number: SPRUGH3
November 2008
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Contents
Preface....................................................................................................................................... 11
1
Introduction....................................................................................................................... 14
1.1
1.2
1.3
1.4
1.5
1.6
Purpose of the Peripheral .............................................................................................. 14
Features .................................................................................................................. 14
Features Not Supported ................................................................................................ 14
Functional Block Diagram .............................................................................................. 15
Supported Use Case Examples ....................................................................................... 16
Industry Standard(s) Compliance Statement ........................................................................ 22
2
3
Peripheral Architecture ....................................................................................................... 23
2.1
2.2
2.3
2.4
2.5
Clock Control............................................................................................................. 23
Signal Descriptions ...................................................................................................... 23
Indexed and Non-Indexed Registers.................................................................................. 23
USB PHY Initialization .................................................................................................. 24
Dynamic FIFO Sizing ................................................................................................... 24
USB Controller Host and Peripheral Modes Operation ............................................................ 24
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
USB Controller Peripheral Mode Operation.......................................................................... 26
USB Controller Host Mode Operation ................................................................................ 44
DMA Operation .......................................................................................................... 57
Interrupt Handling........................................................................................................ 68
Test Modes............................................................................................................... 70
Reset Considerations ................................................................................................... 74
Interrupt Support......................................................................................................... 74
EDMA Event Support ................................................................................................... 74
Power Management..................................................................................................... 74
4
Registers........................................................................................................................... 75
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Control Register (CTRLR) .............................................................................................. 82
Status Register (STATR) ............................................................................................... 83
RNDIS Register (RNDISR)............................................................................................. 83
Auto Request Register (AUTOREQ).................................................................................. 84
USB Interrupt Source Register (INTSRCR).......................................................................... 85
USB Interrupt Source Set Register (INTSETR) ..................................................................... 86
USB Interrupt Source Clear Register (INTCLRR)................................................................... 87
USB Interrupt Mask Register (INTMSKR)............................................................................ 88
USB Interrupt Mask Set Register (INTMSKSETR).................................................................. 89
4.10 USB Interrupt Mask Clear Register (INTMSKCLRR) ............................................................... 90
4.11 USB Interrupt Source Masked Register (INTMASKEDR).......................................................... 91
4.12 USB End of Interrupt Register (EOIR) ................................................................................ 92
4.13 USB Interrupt Vector Register (INTVECTR) ......................................................................... 92
4.14 Transmit CPPI Control Register (TCPPICR)......................................................................... 93
4.15 Transmit CPPI Teardown Register (TCPPITDR).................................................................... 93
4.16 CPPI DMA End of Interrupt Register (CPPIEOIR) .................................................................. 94
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4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR).......................................................... 95
4.18 Transmit CPPI Raw Status Register (TCPPIRAWSR) ............................................................. 95
4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) ................................................. 96
4.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR)............................................... 96
4.21 Receive CPPI Control Register (RCPPICR) ......................................................................... 97
4.22 Receive CPPI Masked Status Register (RCPPIMSKSR) .......................................................... 97
4.23 Receive CPPI Raw Status Register (RCPPIRAWSR).............................................................. 98
4.24 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR)................................................... 98
4.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) ............................................... 99
4.26 Receive Buffer Count 0 Register (RBUFCNT0) ..................................................................... 99
4.27 Receive Buffer Count 1 Register (RBUFCNT1).................................................................... 100
4.28 Receive Buffer Count 2 Register (RBUFCNT2).................................................................... 100
4.29 Receive Buffer Count 3 Register (RBUFCNT3).................................................................... 101
4.30 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) ..................................................... 101
4.31 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) ..................................................... 102
4.32 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) ..................................................... 102
4.33 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) ..................................................... 103
4.34 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) ..................................................... 103
4.35 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) ..................................................... 104
4.36 Transmit CPPI Completion Pointer (TCPPICOMPPTR) .......................................................... 104
4.37 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0)...................................................... 105
4.38 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1)...................................................... 105
4.39 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2)...................................................... 107
4.40 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3)...................................................... 107
4.41 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4)...................................................... 109
4.42 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5)...................................................... 109
4.43 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6)...................................................... 110
4.44 Receive CPPI Completion Pointer (RCPPICOMPPTR)........................................................... 110
4.45 Function Address Register (FADDR)................................................................................ 111
4.46 Power Management Register (POWER)............................................................................ 111
4.47 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)................................... 112
4.48 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ....................................................... 112
4.49 Interrupt Enable Register for INTRTX (INTRTXE)................................................................. 113
4.50 Interrupt Enable Register for INTRRX (INTRRXE) ................................................................ 113
4.51 Interrupt Register for Common USB Interrupts (INTRUSB) ...................................................... 115
4.52 Interrupt Enable Register for INTRUSB (INTRUSBE)............................................................. 116
4.53 Frame Number Register (FRAME) .................................................................................. 117
4.54 Index Register for Selecting the Endpoint Status and Control Registers (INDEX)............................ 117
4.55 Register to Enable the USB 2.0 Test Modes (TESTMODE) ..................................................... 118
4.56 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ..................................... 119
4.57 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)..................................... 120
4.58 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ......................................... 121
4.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) .................................... 122
4.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ......................................... 123
4.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ..................................... 124
4.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)..................................... 125
4.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ......................................... 126
4.64 Count 0 Register (COUNT0).......................................................................................... 128
4.65 Receive Count Register (RXCOUNT) ............................................................................... 128
4
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4.66 Type Register (Host mode only) (HOST_TYPE0) ................................................................ 129
4.67 Transmit Type Register (Host mode only) (HOST_TXTYPE) ................................................... 129
4.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) .................................................... 130
4.69 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) .......................................... 130
4.70 Receive Type Register (Host mode only) (HOST_RXTYPE) ................................................... 131
4.71 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) .......................................... 131
4.72 Configuration Data Register (CONFIGDATA)...................................................................... 132
4.73 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) ................................................... 134
4.74 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ................................................... 135
4.75 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) ................................................... 135
4.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ................................................... 136
4.77 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) ................................................... 136
4.78 OTG Device Control Register (DEVCTL) ........................................................................... 137
4.79 Transmit Endpoint FIFO Size (TXFIFOSZ) ......................................................................... 138
4.80 Receive Endpoint FIFO Size (RXFIFOSZ) ......................................................................... 138
4.81 Transmit Endpoint FIFO Address (TXFIFOADDR) ................................................................ 139
4.82 Receive Endpoint FIFO Address (RXFIFOADDR)................................................................. 139
4.83 Transmit Function Address (TXFUNCADDR) ...................................................................... 140
4.84 Transmit Hub Address (TXHUBADDR) ............................................................................. 140
4.85 Transmit Hub Port (TXHUBPORT) .................................................................................. 140
4.86 Receive Function Address (RXFUNCADDR) ...................................................................... 141
4.87 Receive Hub Address (RXHUBADDR).............................................................................. 141
4.88 Receive Hub Port (RXHUBPORT)................................................................................... 141
Appendix A Revision History ..................................................................................................... 143
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List of Figures
1
Functional Block Diagram................................................................................................. 15
Interrupt Service Routine Flow Chart.................................................................................... 25
CPU Actions at Transfer Phases......................................................................................... 29
Sequence of Transfer...................................................................................................... 30
Service Endpoint 0 Flow Chart ........................................................................................... 32
IDLE Mode Flow Chart .................................................................................................... 33
TX Mode Flow Chart....................................................................................................... 34
RX Mode Flow Chart....................................................................................................... 35
Setup Phase of a Control Transaction Flow Chart..................................................................... 45
IN Data Phase Flow Chart ................................................................................................ 47
OUT Data Phase Flow Chart ............................................................................................. 48
Completion of SETUP or OUT Data Phase Flow Chart............................................................... 49
Completion of IN Data Phase Flow Chart............................................................................... 51
Tx Queue Flow Chart ...................................................................................................... 60
Rx Queue Flow Chart...................................................................................................... 65
Control Register (CTRLR)................................................................................................. 82
Status Register (STATR).................................................................................................. 83
RNDIS Register (RNDISR)................................................................................................ 83
Auto Request Register (AUTOREQ)..................................................................................... 84
USB Interrupt Source Register (INTSRCR)............................................................................. 85
USB Interrupt Source Set Register (INTSETR) ........................................................................ 86
USB Interrupt Source Clear Register (INTCLRR)...................................................................... 87
USB Interrupt Mask Register (INTMSKR)............................................................................... 88
USB Interrupt Mask Set Register (INTMSKSETR) .................................................................... 89
USB Interrupt Mask Clear Register (INTMSKCLRR).................................................................. 90
USB Interrupt Source Masked Register (INTMASKEDR)............................................................. 91
USB End of Interrupt Register (EOIR)................................................................................... 92
USB Interrupt Vector Register (INTVECTR)............................................................................ 92
Transmit CPPI Control Register (TCPPICR) ........................................................................... 93
Transmit CPPI Teardown Register (TCPPITDR) ...................................................................... 93
CPPI DMA End of Interrupt Register (CPPIEOIR)..................................................................... 94
Transmit CPPI Masked Status Register (TCPPIMSKSR) ............................................................ 95
Transmit CPPI Raw Status Register (TCPPIRAWSR) ................................................................ 95
Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) .................................................... 96
Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR).................................................. 96
Receive CPPI Control Register (RCPPICR)............................................................................ 97
Receive CPPI Masked Status Register (RCPPIMSKSR)............................................................. 97
Receive CPPI Raw Status Register (RCPPIRAWSR)................................................................. 98
Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) ..................................................... 98
Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) .................................................. 99
Receive Buffer Count 0 Register (RBUFCNT0)........................................................................ 99
Receive Buffer Count 1 Register (RBUFCNT1) ...................................................................... 100
Receive Buffer Count 2 Register (RBUFCNT2) ...................................................................... 100
Receive Buffer Count 3 Register (RBUFCNT3) ...................................................................... 101
Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0)........................................................ 101
Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1)........................................................ 102
Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2)........................................................ 102
Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3)........................................................ 103
Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4)........................................................ 103
Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5)........................................................ 104
Transmit CPPI Completion Pointer (TCPPICOMPPTR)............................................................. 104
Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) ........................................................ 105
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6
List of Figures
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53
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98
99
Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) ........................................................ 106
Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) ........................................................ 107
Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) ........................................................ 107
Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) ........................................................ 109
Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) ........................................................ 109
Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) ........................................................ 110
Receive CPPI Completion Pointer (RCPPICOMPPTR) ............................................................. 110
Function Address Register (FADDR) .................................................................................. 111
Power Management Register (POWER) .............................................................................. 111
Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX) ............................................. 112
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX).......................................................... 113
Interrupt Enable Register for INTRTX (INTRTXE).................................................................... 113
Interrupt Enable Register for INTRRX (INTRRXE)................................................................... 114
Interrupt Register for Common USB Interrupts (INTRUSB)......................................................... 115
Interrupt Enable Register for INTRUSB (INTRUSBE) ............................................................... 116
Frame Number Register (FRAME) ..................................................................................... 117
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)............................... 117
Register to Enable the USB 2.0 Test Modes (TESTMODE) ........................................................ 118
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)........................................ 119
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ....................................... 120
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0)............................................. 121
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)....................................... 122
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ............................................ 123
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ........................................ 124
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ....................................... 125
Control Status Register for Host Receive Endpoint (HOST_RXCSR)............................................. 126
Count 0 Register (COUNT0) ............................................................................................ 128
Receive Count Register (RXCOUNT).................................................................................. 128
Type Register (Host mode only) (HOST_TYPE0).................................................................... 129
Transmit Type Register (Host mode only) (HOST_TXTYPE)....................................................... 129
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0)........................................................ 130
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL).............................................. 130
Receive Type Register (Host mode only) (HOST_RXTYPE) ....................................................... 131
Receive Interval Register (Host mode only) (HOST_RXINTERVAL) .............................................. 131
Configuration Data Register (CONFIGDATA)......................................................................... 132
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) ...................................................... 134
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ...................................................... 135
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) ...................................................... 135
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ...................................................... 136
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) ...................................................... 136
OTG Device Control Register (DEVCTL).............................................................................. 137
Transmit Endpoint FIFO Size (TXFIFOSZ)............................................................................ 138
Receive Endpoint FIFO Size (RXFIFOSZ) ............................................................................ 138
Transmit Endpoint FIFO Address (TXFIFOADDR)................................................................... 139
Receive Endpoint FIFO Address (RXFIFOADDR) ................................................................... 139
Transmit Function Address (TXFUNCADDR)......................................................................... 140
Transmit Hub Address (TXHUBADDR)................................................................................ 140
100 Transmit Hub Port (TXHUBPORT) ..................................................................................... 140
101 Receive Function Address (RXFUNCADDR) ......................................................................... 141
102 Receive Hub Address (RXHUBADDR) ................................................................................ 141
103 Receive Hub Port (RXHUBPORT) ..................................................................................... 141
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List of Tables
1
USB Pins .................................................................................................................... 23
PERI_TXCSR Register Bit Configuration for Bulk IN Transactions ................................................. 37
PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions .............................................. 39
PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions ........................................ 41
PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions..................................... 43
Transmit Buffer Descriptor Word 0....................................................................................... 58
Transmit Buffer Descriptor Word 1....................................................................................... 58
Transmit Buffer Descriptor Word 2....................................................................................... 58
Transmit Buffer Descriptor Word 3....................................................................................... 58
Receive Buffer Descriptor Word 0 ....................................................................................... 63
Receive Buffer Descriptor Word 1 ....................................................................................... 63
Receive Buffer Descriptor Word 2 ....................................................................................... 63
Receive Buffer Descriptor Word 3 ....................................................................................... 64
Interrupts Generated by the USB Controller............................................................................ 68
USB Interrupt Conditions.................................................................................................. 68
Universal Serial Bus (USB) Registers ................................................................................... 75
Control Register (CTRLR) Field Descriptions .......................................................................... 82
Status Register (STATR) Field Descriptions............................................................................ 83
RNDIS Register (RNDISR) Field Descriptions ......................................................................... 83
Auto Request Register (AUTOREQ) Field Descriptions .............................................................. 84
USB Interrupt Source Register (INTSRCR) Field Descriptions ...................................................... 85
USB Interrupt Source Set Register (INTSETR) Field Descriptions.................................................. 86
USB Interrupt Source Clear Register (INTCLRR) Field Descriptions ............................................... 87
USB Interrupt Mask Register (INTMSKR) Field Descriptions ........................................................ 88
USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions .............................................. 89
USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions............................................ 90
USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions ...................................... 91
USB End of Interrupt Register (EOIR) Field Descriptions ............................................................ 92
USB Interrupt Vector Register (INTVECTR) Field Descriptions...................................................... 92
Transmit CPPI Control Register (TCPPICR) Field Descriptions ..................................................... 93
Transmit CPPI Teardown Register (TCPPITDR) Field Descriptions ................................................ 93
CPPI DMA End of Interrupt Register (CPPIEOIR) Field Descriptions .............................................. 94
Transmit CPPI Masked Status Register (TCPPIMSKSR) Field Descriptions ...................................... 95
Transmit CPPI Raw Status Register (TCPPIRAWSR) Field Descriptions.......................................... 95
Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) Field Descriptions.............................. 96
Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) Field Descriptions ........................... 96
Receive CPPI Control Register (RCPPICR) Field Descriptions...................................................... 97
Receive CPPI Masked Status Register (RCPPIMSKSR) Field Descriptions....................................... 97
Receive CPPI Raw Status Register (RCPPIRAWSR) Field Descriptions .......................................... 98
Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) Field Descriptions ............................... 98
Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) Field Descriptions............................ 99
Receive Buffer Count 0 Register (RBUFCNT0) Field Descriptions.................................................. 99
Receive Buffer Count 1 Register (RBUFCNT1) Field Descriptions ................................................ 100
Receive Buffer Count 2 Register (RBUFCNT2) Field Descriptions ................................................ 100
Receive Buffer Count 3 Register (RBUFCNT3) Field Descriptions ................................................ 101
Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) Field Descriptions.................................. 101
Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) Field Descriptions.................................. 102
Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Field Descriptions.................................. 102
Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) Field Descriptions.................................. 103
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8
List of Tables
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50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
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81
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86
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92
93
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95
96
97
98
99
100
Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions.................................. 103
Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) Field Descriptions.................................. 104
Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions....................................... 105
Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) Field Descriptions .................................. 105
Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) Field Descriptions .................................. 106
Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) Field Descriptions .................................. 107
Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) Field Descriptions .................................. 107
Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) Field Descriptions .................................. 109
Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) Field Descriptions .................................. 109
Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) Field Descriptions .................................. 110
Receive CPPI Completion Pointer (RCPPICOMPPTR) Field Descriptions ....................................... 110
Function Address Register (FADDR) Field Descriptions ............................................................ 111
Power Management Register (POWER) Field Descriptions ........................................................ 111
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) Field Descriptions ............... 112
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions ................................... 113
Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions ............................................. 113
Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions............................................. 114
Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions .................................. 115
Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions ......................................... 116
Frame Number Register (FRAME) Field Descriptions............................................................... 117
Index Register for Selecting the Endpoint Status and Control Registers (INDEX) Field Descriptions ........ 117
Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions.................................. 118
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions ................. 119
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions ................. 120
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions....................... 121
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions................. 122
Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions ...................... 123
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions.................. 124
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions ................. 125
Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions....................... 126
Count 0 Register (COUNT0) Field Descriptions...................................................................... 128
Receive Count Register (RXCOUNT) Field Descriptions ........................................................... 128
Type Register (Host mode only) (HOST_TYPE0) Field Descriptions ............................................. 129
Transmit Type Register (Host mode only) (HOST_TXTYPE) Field Descriptions ................................ 129
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Field Descriptions ................................. 130
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Field Descriptions ....................... 130
Receive Type Register (Host mode only) (HOST_RXTYPE) Field Descriptions................................. 131
Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions........................ 132
Configuration Data Register (CONFIGDATA) Field Descriptions .................................................. 132
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions................................ 134
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions................................ 135
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions................................ 135
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions................................ 136
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions................................ 136
OTG Device Control Register (DEVCTL) Field Descriptions ....................................................... 137
Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions ..................................................... 138
Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions...................................................... 138
Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions............................................. 139
Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions ............................................. 139
Transmit Function Address (TXFUNCADDR) Field Descriptions .................................................. 140
Transmit Hub Address (TXHUBADDR) Field Descriptions.......................................................... 140
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List of Tables
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101
102
103
104
A-1
Transmit Hub Port (TXHUBPORT) Field Descriptions............................................................... 140
Receive Function Address (RXFUNCADDR) Field Descriptions................................................... 141
Receive Hub Address (RXHUBADDR) Field Descriptions .......................................................... 141
Receive Hub Port (RXHUBPORT) Field Descriptions ............................................................... 141
Document Revision History.............................................................................................. 143
10
List of Tables
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Preface
SPRUGH3–November 2008
Read This First
About This Manual
This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media
System-on-Chip (DMSoC).
Notational Conventions
This document uses the following conventions.
•
Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
•
Registers in this document are shown in figures and described in tables.
–
Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
–
Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM357 Digital Media System-on-Chip (DMSoC). Copies of
these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the
search box provided at www.ti.com.
SPRUG06 — TMS320DM357 DMSoC Video Processing Back End (VPBE) User's Guide. Describes
the video processing back end (VPBE) in the TMS320DM357 Digital Media System-on-Chip
(DMSoC) video processing subsystem. Included in the VPBE is the video encoder, on-screen
display, and digital LCD controller.
SPRUG25 — TMS320DM357 DMSoC ARM Subsystem Reference Guide. Describes the ARM
subsystem in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The ARM subsystem is
designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is
responsible for configuration and control of the device; including the video processing subsystem,
and a majority of the peripherals and external memories.
SPRUG26 —TMS320DM357 DMSoC Universal Asynchronous Receiver/Transmitter (UART) User's
Guide. This document describes the universal asynchronous receiver/transmitter (UART) peripheral
in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The UART peripheral performs
serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial
conversion on data received from the CPU.
SPRUG27 — TMS320DM357 DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide.
Describes the inter-integrated circuit (I2C) peripheral in the TMS320DM357 Digital Media
System-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and other
devices compliant with the I2C-bus specification and connected by way of an I2C-bus. External
components attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and
from the DMSoC through the I2C peripheral. This document assumes the reader is familiar with the
I2C-bus specification.
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Preface
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Notational Conventions
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SPRUG28 — TMS320DM357 DMSoC 64-Bit Timer User's Guide. Describes the operation of the
software-programmable 64-bit timer in the TMS320DM357 Digital Media System-on-Chip (DMSoC).
Timer 0 and Timer 1 are used as general-purpose (GP) timers and can be programmed in 64-bit
mode, dual 32-bit unchained mode, or dual 32-bit chained mode; Timer 2 is used only as a
watchdog timer. The GP timer modes can be used to generate periodic interrupts or enhanced
direct memory access (EDMA) synchronization events. The watchdog timer mode is used to
provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting
code loop.
SPRUG29 — TMS320DM357 DMSoC Serial Peripheral Interface (SPI) User's Guide. Describes the
serial peripheral interface (SPI) in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The
SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed
bit-transfer rate. The SPI is normally used for communication between the DMSoC and external
peripherals. Typical applications include an interface to external I/O or peripheral expansion via
devices such as shift registers, display drivers, SPI EPROMs and analog-to-digital converters.
SPRUG30 — TMS320DM357 DMSoC Host Port Interface (HPI) Reference Guide. This document
describes the host port interface in the TMS320DM357 Digital Media System-on-Chip (DMSoC).
The HPI provides a parallel port interface through which an external host processor can directly
access the TMS320DM357 DMSoC processor's resources (configuration and program/data
memories).
SPRUG31 — TMS320DM357 DMSoC General-Purpose Input/Output (GPIO) User's Guide. Describes
the general-purpose input/output (GPIO) peripheral in the TMS320DM357 Digital Media
System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose pins that can
be configured as either inputs or outputs. When configured as an input, you can detect the state of
the input by reading the state of an internal register. When configured as an output, you can write
to an internal register to control the state driven on the output pin.
SPRUG32 — TMS320DM357 DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller
User's Guide. Describes the multimedia card (MMC)/secure digital (SD) card controller in the
TMS320DM357 Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number of
applications to provide removable data storage. The MMC/SD controller provides an interface to
external MMC and SD cards. The communication between the MMC/SD controller and MMC/SD
card(s) is performed by the MMC/SD protocol.
SPRUG33 — TMS320DM357 DMSoC Asynchronous External Memory Interface (EMIF) User's
Guide. Describes the asynchronous external memory interface (EMIF) in the TMS320DM357
Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of
external devices.
SPRUG34 — TMS320DM357 DMSoC Enhanced Direct Memory Access (EDMA) Controller User's
Guide. Describes the operation of the enhanced direct memory access (EDMA3) controller in the
TMS320DM357 Digital Media System-on-Chip (DMSoC). The EDMA3 controller’s primary purpose
is to service user-programmed data transfers between two memory-mapped slave endpoints on the
DMSoC.
SPRUG35 — TMS320DM357 DMSoC Audio Serial Port (ASP) User's Guide. Describes the operation
of the audio serial port (ASP) audio interface in the TMS320DM357 Digital Media System-on-Chip
(DMSoC). The primary audio modes that are supported by the ASP are the AC97 and IIS modes. In
addition to the primary audio modes, the ASP supports general serial port receive and transmit
operation, but is not intended to be used as a high-speed interface.
SPRUG36 — TMS320DM357 DMSoC Ethernet Media Access Controller (EMAC)/Management Data
Input/Output (MDIO) Module User's Guide. Discusses the ethernet media access controller
(EMAC) and physical layer (PHY) device management data input/output (MDIO) module in the
TMS320DM357 Digital Media System-on-Chip (DMSoC). The EMAC controls the flow of packet
data from the DMSoC to the PHY. The MDIO module controls PHY configuration and status
monitoring.
12
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Notational Conventions
SPRUG37 — TMS320DM357 DMSoC Pulse-Width Modulator (PWM) Peripheral User's Guide.
Describes the pulse-width modulator (PWM) peripheral in the TMS320DM357 Digital Media
System-on-Chip (DMSoC).
SPRUG38 — TMS320DM357 DMSoC DDR2 Memory Controller User's Guide. Describes the DDR2
memory controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The DDR2
memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM
devices.
SPRUG39 — TMS320DM357 DMSoC Video Processing Front End (VPFE) User's Guide. Describes
the video processing front end (VPFE) in the TMS320DM357 Digital Media System-on-Chip
(DMSoC) video processing subsystem. Included in the VPFE is the preview engine, CCD controller,
resizer, histogram, and hardware 3A (H3A) statistic generator.
SPRUGH2 —TMS320DM357 DMSoC Peripherals Overview Reference Guide. This document provides
an overview of the peripherals in the TMS320DM357 Digital Media System-on-Chip (DMSoC).
SPRUGH3 —TMS320DM357 DMSoC Universal Serial Bus Controller User's Guide. This document
describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media
System-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. It
provides a mechanism for data transfer between USB devices and also supports host negotiation.
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User's Guide
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Universal Serial Bus (USB) Controller
1
Introduction
This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media
System-on-Chip (DMSoC). The controller supports high-speed USB peripheral mode and high-speed
limited host-mode operations. The USB controller can be operated by ARM through the memory-mapped
registers.
Note: The High-Speed USB OTG Controller is an instantiation of the MUSBMHDRC from Mentor
Graphics Corporation.
This document contains materials that are ©2003-2007 Mentor Graphics Corporation.
Mentor Graphics is a registered trademark of Mentor Graphics Corporation or its affiliated
companies in the United States and other countries.
1.1 Purpose of the Peripheral
The USB controller supports data throughput rates up to 480 Mbps. It provides a mechanism for data
transfer between USB devices and also supports host negotiation.
1.2 Features
The USB has the following features:
•
•
•
•
•
•
•
•
•
•
Supports USB 2.0 peripheral at High Speed (480 Mbps) and Full Speed (12 Mbps)
Supports USB 2.0 host at High Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps)
Supports USB 2.0 OTG
Supports four simultaneous RX and TX endpoints, more can be supported by dynamically switching
Each endpoint can support all transfer types (control, bulk, interrupt, and isochronous)
Supports USB extensions for Session Request (SRP) and Host Negotiation (HNP)
Includes a 4K endpoint FIFO RAM, and supports programmable FIFO sizes
External 5V power supply for VBUS can be controlled through I2C
Includes a DMA controller that supports four TX and four RX DMA channels
Includes RNDIS mode of DMA for accelerating RNDIS type protocols using short packet termination
over USB
1.3 Features Not Supported
The following features are not supported:
•
•
•
High Bandwidth Isochronous Transfer.
High Bandwidth Interrupt Transfer.
Automatic Amalgamation of Bulk Packets (CPPI DMA will indirectly handle this feature and is not
supported at the core level).
•
Automatic Splitting of Bulk Packets (CPPI DMA will indirectly handle this feature and is not supported
at the core level).
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Introduction
1.4 Functional Block Diagram
Figure 1. Functional Block Diagram
Internal
bus
CPPI
DMA
engine
Packet
encode/
decode
USB
2.0
PHY
FIFO
USB
24 MHz
crystal
oscillator
Registers, interrupts, endpoint control,
and packet scheduling
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1.5 Supported Use Case Examples
The USB supports the following user cases:
Detailed information about the architecture and operation of the USB controller follows in Section 2.
Programming examples are also provided for each of the operational modes of the controller.
User Case 1: An example of how to initialize the USB controller
Example 1. Initializing the USB Controller
// Routine to initialize USB controller
void usb_init()
{
// local loop variable
int I;
// VBUS must be controlled externally. The following routine
// should perform whatever actions are required (if any) to
// turn off VBUS in the system.
vbus_off();
// Reset the USB controller
usbRegs->CTRLR = 0x00000001;
// Power on PHY and oscillator by clearing bits 2, 1, and 0 of USBPHY_CTL
sysRegs->USB_PHY_CTRL = 0x000000D0;
//Clear all pending interrupts
usbRegs->INTCLRR = usbRegs->INTSRCR;
// Initialize CPPI DMA
usbRegs->RCPPICR = 0;
usbRegs->TCPPICR = 0;
//Disable the RX DMA
//Disable the TX DMA
// Initialize CPPI DMA state
for(I = 0; i<4; I++) {
usbRegs->CHANNEL[i].TCPPIDMASTATEW0 = 0;
usbRegs->CHANNEL[i].TCPPIDMASTATEW1 = 0;
usbRegs->CHANNEL[i].TCPPIDMASTATEW2 = 0;
usbRegs->CHANNEL[i].TCPPIDMASTATEW3 = 0;
usbRegs->CHANNEL[i].TCPPIDMASTATEW4 = 0;
usbRegs->CHANNEL[i].TCPPIDMASTATEW5 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW0 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW1 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW2 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW3 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW4 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW5 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW6 = 0;
}
}
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User Case 2: An example of how to program the USB Endpoints in peripheral mode
Example 2. Programming the USB Endpoints in Peripheral Mode
// DMA channel number. Valid values are 0, 1, 2, or 3.
int CHAN_NUM = 0;
// Fifo sizes: uncomment the desired size.
// This example uses 64-byte fifo.
// int fifosize = 0;
// int fifosize = 1;
// int fifosize = 2;
int fifosize = 3;
// int fifosize = 4;
// int fifosize = 5;
// int fifosize = 6;
// int fifosize = 7;
// int fifosize = 8;
// int fifosize = 9;
// 8 bytes
// 16 bytes
// 32 bytes
// 64 bytes
// 128 bytes
// 256 bytes
// 512 bytes
// 1024 bytes
// 2048 bytes
// 4096 bytes
// FIFO address. Leave 64-bytes for endpoint 0.
int fifo_start_address = 8;
// Uncomment the desired buffering. If double-buffer is selected, actual
// FIFO space will be twice the value listed above for fifosize.
// This example uses single buffer.
int double_buffer = 0; // Single-buffer
// int double_buffer = 1; // Double-buffer
// For maximum packet size this formula will usually work, but it can also be
// set to another value if needed. If non power of 2 value is needed (such as
// 1023) set it explicitly.
#define FIFO_MAXP 8*(1<<fifosize);
// Set the following variable to the device address.
int device_address = 0;
// The following code should be run after receiving a USB reset from the host.
// Initialize the endpoint FIFO. RX and TX will be allocated the same sizes.
usbRegs->INDEX = CHAN_NUM+1;
usbRegs->RXFIFOSZ = fifosize | ((double_buffer & 1)<<4);
usbRegs->RXFIFOADDR = fifo_start_address;
usbRegs->TXFIFOSZ =
fifosize | ((double_buffer & 1)<<4);
usbRegs->TXFIFOADDR = fifo_start_address + (1<<(fifosize+double_buffer));
usbRegs->RXMAXP = FIFO_MAXP;
usbRegs->TXMAXP = FIFO_MAXP;
// Force Data Toggle is optional for interrupt traffic. Uncomment if needed.
// CSL_FINS(usbRegs->PERI_TXCSR,USB_PERI_TXCSR_FRCDATATOG,1);
// Uncomment below to configure the endpoint for ISO and not respond with a
// handshake packet.
// CSL_FINS(usbRegs->PERI_RXCSR,USB_PERI_RXCSR_ISO,1);
// CSL_FINS(usbRegs->PERI_TXCSR,USB_PERI_TXCSR_ISO,1);
// After receiving a successful set-address command, set the following register
// to the specified address immediately following the status stage.
usbRegs->FADDR = device_address;
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User Case 3: An example of how to program the USB endpoints in host mode
Example 3. Programming the USB Endpoints in Host Mode
// DMA channel number. Valid values are 0, 1, 2, or 3.
int CHAN_NUM = 0;
// Fifo sizes: uncomment the desired size.
// This example uses 64-byte fifo.
// int fifosize = 0;
// int fifosize = 1;
// int fifosize = 2;
int fifosize = 3;
// int fifosize = 4;
// int fifosize = 5;
// int fifosize = 6;
// int fifosize = 7;
// int fifosize = 8;
// int fifosize = 9;
// 8 bytes
// 16 bytes
// 32 bytes
// 64 bytes
// 128 bytes
// 256 bytes
// 512 bytes
// 1024 bytes
// 2048 bytes
// 4096 bytes
// FIFO address. Leave 64-bytes for endpoint 0.
int fifo_start_address = 8;
// Uncomment the desired buffering. If double-buffer is selected, actual
// FIFO space will be twice the value listed above for fifosize.
// This example uses single buffer.
int double_buffer = 0; // Single-buffer
// int double_buffer = 1; // Double-buffer
// Set the following variable to the device endpoint type: CONTROL ISO BULK or IN
int device_protocol = BULK;
//int device_protocol = ISO;
//int device_protocol = INT;
// USB speeds
#define LOW_SPEED 0
#define FULL_SPEED 1
#define HIGH_SPEED 2
// TXTYPE protocol
#define CONTROL 0
#define ISO 1
#define BULK 2
#define INT 3
// For maximum packet size this formula will usually work, but it can also be
// set to another value if needed. If non power of 2 value is needed (such as
// 1023) set it explicitly.
#define FIFO_MAXP 8*(1<<fifosize);
// Set the following variable to the device address.
int device_address = 1;
// Set the following variable to the device endpoint number.
int device_ep = 1;
// Variable used for endpoint configuration
Uint8 type = 0;
// Variable to keep track of errors
int error = 0;
// The following code should be run after resetting the attached device
// Initialize the endpoint FIFO. RX and TX will be allocated the same sizes.
usbRegs->INDEX = CHAN_NUM+1;
usbRegs->RXFIFOSZ = fifosize | ((double_buffer & 1)<<4);
usbRegs->RXFIFOADDR = fifo_start_address;
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Introduction
Example 3. Programming the USB Endpoints in Host Mode (continued)
usbRegs->TXFIFOSZ =
fifosize | ((double_buffer & 1)<<4);
usbRegs->TXFIFOADDR = fifo_start_address + (1<<(fifosize+double_buffer));
usbRegs->RXMAXP = FIFO_MAXP;
usbRegs->TXMAXP = FIFO_MAXP;
//Configure the endpoint
switch (device_speed) {
case LOW_SPEED : type = (3<<6) | ((device_protocol & 3) << 4) | (device_ep & 0xf); break;
case FULL_SPEED: type = (2<<6) | ((device_protocol & 3) << 4) | (device_ep & 0xf); break;
case HIGH_SPEED: type = (1<<6) | ((device_protocol & 3) << 4) | (device_ep & 0xf); break;
default:error++;
}
usbRegs->EPCSR[CHAN_NUM+1].HOST_TYPE0 = type; // TXTYPE
usbRegs->EPCSR[CHAN_NUM+1].HOST_RXTYPE = type;
// Set NAK limit / Polling interval (Interrupt & Iso protocols)
if ((device_protocol == INT) || (device_protocol == ISO)) {
usbRegs->EPCSR[CHAN_NUM+1].HOST_NAKLIMIT0 = TXINTERVAL;
usbRegs->EPCSR[CHAN_NUM+1].HOST_RXINTERVAL = RXINTERVAL;
} else {
// TX Polling interval
// RX Polling interval
usbRegs->EPCSR[CHAN_NUM+1].HOST_NAKLIMIT0 = 2;
usbRegs->EPCSR[CHAN_NUM+1].HOST_RXINTERVAL = 2;
// Frames to timeout from NAKs
// Frames to timeout from NAKs
}
//Set the address for transactions after SET ADDRESS successfully completed
usbRegs->EPTRG[CHAN_NUM+1].TXFUNCADDR = device_address;
usbRegs->EPTRG[CHAN_NUM+1].RXFUNCADDR = device_address;
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User Case 4: An example of how to do host negotiation to support USB
If the HOSTREQ bit in the DEVCTL register is set, host negotiation is performed by the hardware when
the device enters suspend mode. The bit is cleared when host negotiation is complete.
User Case 5: An example of how to program the USB DMA controller
Example 4. Programming the USB DMA Controller
// Number of DMA channels
#define NUM_CHANNEL 4
// Number of DMA buffers to allocate
#define RX_BUFFERS 32
#define TX_BUFFERS 32
// Memory region to place DMA buffers and descriptors
#define MEMORY_TARGET ".DDREMIF_0_BUF"
// DMA defines
#define SOP
#define EOP
#define OWNER
#define EOQ
#define ZERO_BYTE
#define RX_ABORT
(Uint32) (1<<31)
(Uint32) (1<<30)
(Uint32) (1<<29)
(Uint32) (1<<28)
(Uint32) (1<<23)
(Uint32) (1<<19)
// DMA channel configuration
#define CH0 0
#define CH1 1
#define CH2 2
#define CH3 3
// Loop variable
int I;
// Variable to keep track of errors
int error = 0;
// Variable to keep track of the number of descriptors built
int tx_desc[NUM_CHANNEL];
int rx_desc[NUM_CHANNEL];
// Current TX Buffer descriptor[channel number]
// Current RX Buffer descriptor[channel number]
// Separate data section for bufferDesc. NOTE: CPPI buffers MUST be aligned to 16-byte
boundaries.
#pragma DATA_SECTION(rx_bufferDesc, MEMORY_TARGET)
Uint32 rx_bufferDesc[NUM_CHANNEL][RX_BUFFERS];
#pragma DATA_SECTION(tx_bufferDesc, MEMORY_TARGET)
Uint32 tx_bufferDesc[NUM_CHANNEL][TX_BUFFERS];
// Initialize CPPI DMA. This code is also included in the controller initialization.
usbRegs->RCPPICR = 0;
usbRegs->TCPPICR = 0;
//Disable the RX DMA
//Disable the TX DMA
for(I = 0; i<NUM_CHANNEL;i++) { // Initialize CPPI DMA state
usbRegs->CHANNEL[i].TCPPIDMASTATEW0 = 0;
usbRegs->CHANNEL[i].TCPPIDMASTATEW1 = 0;
usbRegs->CHANNEL[i].TCPPIDMASTATEW2 = 0;
usbRegs->CHANNEL[i].TCPPIDMASTATEW3 = 0;
usbRegs->CHANNEL[i].TCPPIDMASTATEW4 = 0;
usbRegs->CHANNEL[i].TCPPIDMASTATEW5 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW0 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW1 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW2 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW3 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW4 = 0;
usbRegs->CHANNEL[i].RCPPIDMASTATEW5 = 0;
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Example 4. Programming the USB DMA Controller (continued)
usbRegs->CHANNEL[i].RCPPIDMASTATEW6 = 0;
tx_desc[i] = 0;
rx_desc[i] = 0;
}
// Routine to flush TX fifo.
// Must call this routine twice for double-buffered FIFO
void flush_tx_fifo(int ep) {
int index_save;
int status;
index_save = usbRegs->INDEX;
usbRegs->INDEX = ep;
// Save the index to restore later
// Set the index to the desired endpoint
status = usbRegs->PERI_TXCSR & 3;
if (!(status)) {
usbRegs->PERI_TXCSR |= 1;
packet already in FIFO
}
// Isolate the TxPktRdy and FIFONotEmpty bits
// Nothing showing in FIFO
// Set TxPktRdy in case there is a partial
usbRegs->PERI_TXCSR = ((usbRegs->PERI_TXCSR & 0xFFFC) | 8);
bit set, FIFONotEmpty=0, and TxPktRdy=0.
// Write TXCSR with flush
while (usbRegs->PERI_TXCSR & 8);
// Keep looping until the flush bit clears
usbRegs->INDEX = index_save;
// Restore the index to previous value
}
// Routine to start the TX DMA for a given channel
void start_tx_dma(int ch) {
// Must have at least one descriptor before turning on TX DMA
if (rx_desc[ch] < 1) {error++;} else {
//Flush FIFO (2 times in case it is double-buffered)
flush_tx_fifo(ch+1);
flush_tx_fifo(ch+1);
// Start the DMA
usbRegs->TCPPICR = 1; //Enable Tx CPPI DMA
usbRegs->CHANNEL[ch].TCPPIDMASTATEW0 = (Uint32)(&tx_bufferDesc[ch][0]);
CSL_FINS(usbRegs->PERI_TXCSR,USB_PERI_TXCSR_DMAEN,1); // TXCSR, bit DMAReqEnab
}
}
// Routine to add a TX descriptor
void add_tx_descriptor(int ch, unsigned char * inBuf, int bytes) {
if ((bytes < 0) || (bytes >65535)) {bytes = 64; error++;}
// Link previous buffer to this one if this is not the first descriptor of the channel
if (tx_desc[ch] > 0) tx_bufferDesc[ch][4*(tx_desc[ch]-1)] =
(Uint32)(&tx_bufferDesc[ch][4*tx_desc[ch]]);
// Set up DMA buffer descriptors
tx_bufferDesc[ch][4*tx_desc[ch]+0] = (Uint32)(0x00000000);
tx_bufferDesc[ch][4*tx_desc[ch]+1] = (Uint32)inBuf;
tx_bufferDesc[ch][4*tx_desc[ch]+2] = (0x0000 << 16) | bytes;
[15:0] Buffer length
// Next Descriptor pointer
// Buffer pointer
// [31:16] Buffer offset
if (bytes == 0) bytes = ZERO_BYTE | 1;
tx_bufferDesc[ch][4*tx_desc[ch]+3] = SOP | EOP | OWNER | bytes;
// Set the ZERO_BYTE bit and size 1 byte
// [31]=SOP, [30]=EOP,
[29]=owner, [28]=EOQ, [23]=zero-byte, [19] = rxabort, [15:0]=packet length
// If DMA already enabled and has stopped, write this to the TX Queue head pointer
if ((usbRegs->TCPPICR == 1) && (usbRegs->CHANNEL[ch].TCPPIDMASTATEW0 == 0))
usbRegs->CHANNEL[ch].TCPPIDMASTATEW0 = (Uint32)(&tx_bufferDesc[ch][4*tx_desc[ch]+0]);
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Example 4. Programming the USB DMA Controller (continued)
// Increment descriptor counter
tx_desc[ch]++;
}
// Routine to start the RX DMA for a given channel
void start_rx_dma(int ch) {
int index_save;
index_save = usbRegs->INDEX;
// Save the index to restore later
// Must have at least 3 descriptors to receive anything
if (rx_desc[ch] < 2) {error++;} else {
usbRegs->INDEX = ch+1;
usbRegs->RCPPICR = 1; //Enable Rx CPPI DMA
usbRegs->CHANNEL[ch].RCPPIDMASTATEW1 = (Uint32)(&rx_bufferDesc[ch][0]);
CSL_FINS(usbRegs->PERI_RXCSR,USB_PERI_RXCSR_DMAEN,1);
// Update the buffer count register. This ADDS to the existing value, does not
overwrite.
switch (ch) {
case 0: usbRegs->RBUFCNT0 = rx_desc[ch]; break;
case 1: usbRegs->RBUFCNT1 = rx_desc[ch]; break;
case 2: usbRegs->RBUFCNT2 = rx_desc[ch]; break;
case 3: usbRegs->RBUFCNT3 = rx_desc[ch]; break;
}
}
usbRegs->INDEX = index_save;
// Restore the index to previous value
}
//Function to build Rx DMA descriptors
void add_rx_descriptor(int ch, unsigned char * outBuf, int bytes) {
int index_save;
index_save = usbRegs->INDEX;
// Save the index to restore later
if (bytes < 1) {bytes = 64; error++;}
usbRegs->INDEX = ch+1;
// Link previous buffer to this one if this is not the first descriptor of the channel
if (rx_desc[ch] > 0) rx_bufferDesc[ch][4*(rx_desc[ch]-1)] =
(Uint32)(&rx_bufferDesc[ch][4*rx_desc[ch]]);
rx_bufferDesc[ch][4*rx_desc[ch]+0] = (Uint32)(0x00000000);
rx_bufferDesc[ch][4*rx_desc[ch]+1] = (Uint32)outBuf;
rx_bufferDesc[ch][4*rx_desc[ch]+2] = (0x0000 << 16) | bytes;
rx_bufferDesc[ch][4*rx_desc[ch]+3] = OWNER | 0;
rx_desc[ch]++;
// Next descriptor
// Buffer address
// Rx buffer size in bytes
// OWNER
usbRegs->INDEX = index_save;
// Restore the index to previous value
}
1.6 Industry Standard(s) Compliance Statement
This device conforms to USB 2.0 Specification and On-The-Go Supplement to the USB 2.0 Specification
Rev 1.0a.
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Peripheral Architecture
2
Peripheral Architecture
2.1 Clock Control
Information related to clock generation and control for the USB peripheral will be added in a future revision
of this document. Clocks for USB are generated based on a crystal oscillator on the M24XI and M24XO
pins. The oscillator is enabled by bit OSCPDWN of the USBPHY_CTL register in the system module.
2.2 Signal Descriptions
mode.
Table 1. USB Pins
Pin
Type(1)
Function
M24XI
I
Crystal input for M24 oscillator (24 MHZ for USB)
Crystal output for M24 oscillator
1.8V power supply for M24 oscillator
Ground for M24 oscillator
M24X0
O
S
M24VDD
M24VSS
PLLVDD18
USB_VBUS
GND
I/O
1.8 Volt power supply for PLLs (system and USB)
5V input that signifies that VBUS is connected. The OTG section of the PHY can also pull up or
down on this signal for HNP and SRP.
USB_ID
USB_DP
USB_DM
I/O
I/O
I/O
USB_ID is an input that is open or pulled to ground depending on OTG connector configuration.
The state determines if controller starts in HOST or PERIPHERAL mode.
USB bi-directional Data Differential signal pair [positive/negative]. Input/output DP signal of the
differential signal pair.
USB bi-directional Data Differential signal pair [positive/negative]. Input/output DM signal of the
differential signal pair.
USB_R1
I/O
GND
S
Reference current output. This must be connected via a 10 kΩ 1% resistor to USB_VSSREF
Ground for reference current
.
USB_VSSREF
USB_VDDA3P3
USB_VSSA3P3
USB_VDD1P83
USB_VSS1P8
USB_VDDA1P2LDO
Analog 3.3 V power supply for USB phy
Analog ground for USB phy
GND
S
1.8 V I/O power supply for USB phy
GND
S
I/O Ground for USB phy
Core Power supply LDO output for USB phy. This must be connected via 1 µF capacitor to
USB_VSSA1P2LDO. Do not connect this to other supply pins.
USB_VSSA1P2LDO GND
Core Ground for USB phy. This must be connected via 1 µF capacitor to USB_VDDA1P2LDO.
(1)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
2.3 Indexed and Non-Indexed Registers
USB controller provides two mechanism of accessing the endpoint control and status registers:
•
Indexed Endpoint Control/Status Registers – These registers are memory-mapped at offset 410h to
41Fh. The endpoint is selected by programming the INDEX register of the controller.
•
Non-indexed Endpoint Control/Status Registers – These registers are memory-mapped at offset 500h
to 54Fh. Registers at offset 500h-50Fh map to Endpoint 0; offset 510h-51Fh map to Endpoint 1, and
so on.
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2.4 USB PHY Initialization
The following bits in USBPHY_CTL must be cleared to enable the USB controller: OSCPDWN and
PHYPDWN. The following bits in USBPHY_CTL must be set to enable the level comparators: VBDTCTEN
and VBUSENS. After this configuration is in place, wait until the PLL clock is good prior to continuing, i.e.,
wait until USBPHY_CTL.PHYCLKGD bit is set.
2.5 Dynamic FIFO Sizing
The USB controller supports a total of 4K RAM to dynamically allocate FIFO to all endpoints. The
allocation of FIFO space to the different endpoints requires the specification for each Tx and Rx endpoint
of:
•
•
•
The start address of the FIFO within the RAM block
The maximum size of packet to be supported
Whether double-buffering is required.
These details are specified through four registers, which are added to the indexed area of the memory
map. That is, the registers for the desired endpoint are accessed after programming the INDEX register
with the desired endpoint value. Section 4.79, Section 4.80, Section 4.81, and Section 4.82 provide details
of these registers.
Note: The option of setting FIFO sizes dynamically only applies to Endpoints 1 … 4. Endpoint 0
FIFO has a fixed size (64 bytes) and a fixed location (start address 0).
It is the responsibility of the firmware to ensure that all the Tx and Rx endpoints that are
active in the current USB configuration have a block of RAM assigned exclusively to that
endpoint that is at least as large as the maximum packet size set for that endpoint.
3
USB Controller Host and Peripheral Modes Operation
The USB controller can be used in a range of different environments. It can be used as either a
high-speed or a full-speed USB peripheral device attached to a conventional USB host (such as a PC). It
can be used as either host or peripheral device in point-to-point data transfers with another peripheral
device - or, if the other device also contains a Dual-Role Controller, the two devices can switch roles as
required. (This second device may be either a high-speed, full-speed or low-speed USB function.) Or the
controller can be used as the host to a range of such peripheral devices in a multi-point setup.
Whether the controller expects to behave as a host or as a peripheral device depends on the way the
devices are cabled together. Each USB cable has an A end and a B end. If the A end of the cable is
plugged into the controller, it will take the role of the Host device and go into host mode. If the B end of
the cable is plugged in, the controller will go instead into peripheral mode.
The USB controller interrupts the ARM on completion of the data transfer on any of the endpoints or on
detecting reset, resume, suspend, connect, disconnect, or SOF on the bus.
When the ARM is interrupted with a USB interrupt, it needs to read the interrupt status register to
determine the endpoints that have caused the interrupt and jump to the appropriate routine. If multiple
endpoints have caused the interrupt, endpoint 0 should be serviced first, followed by the other endpoints.
The suspend interrupt should be serviced last.
The following sections describe the programming of USB controller in Peripheral mode and Host mode.
DMA Operations and Interrupt Handler mechanisms are common to both peripheral and host mode
operations and are discussed after the programming in Peripheral and Host Mode.
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Figure 2. Interrupt Service Routine Flow Chart
Read interrupt
status register
Yes
Resume
interrupt
?
Resume routine
No
A
A device
B device
device or
B device
?
Yes
Yes
SESSREQ
interrupt
?
Session req
routine
No
Vbus
error interrupt
?
Vbus error
routine
Host
Host
or peripheral
?
Peripheral
Connect
interrupt
?
EP0
interrupt
?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Connect
routine
Peripheral
EP0 routine
No
No
Babble
interrupt
?
Receive
interrupt
?
Babble
routine
Peripheral
Rx routine
No
No
EP0
interrupt
?
Transmit
interrupt
?
Host EP0
routine
Peripheral
Tx routine
No
Receive
interrupt
?
Host Rx
routine
No
Transmit
interrupt
?
Host Tx
routine
No
SOF
interrupt
?
Yes
Yes
Yes
Resume
routine
Disconn
interrupt
?
Disconnect
routine
Suspend
interrupt
?
Suspend
routine
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3.1 USB Controller Peripheral Mode Operation
•
Soft connect - After a reset, the SOFTCONN bit of POWER register (bit 6) is cleared to 0. The
controller will therefore appear disconnected until the software has set the SOFTCONN bit to 1. The
application software can then choose when to set the PHY into its normal mode. Systems with a
lengthy initialization procedure may use this to ensure that initialization is complete and the system is
ready to perform enumeration before connecting to the USB.
Once the SOFTCONN bit has been set, the software can also simulate a disconnect by clearing this bit
to 0.
•
Entry into suspend mode
When operating as a peripheral device, the controller monitors activity on the bus and when no activity
has occurred for 3 ms, it goes into Suspend mode. If the Suspend interrupt has been enabled, an
interrupt will be generated at this time.
At this point, the controller can then be left active (and hence able to detect when Resume signaling
occurs on the USB), or the application may arrange to disable the controller by stopping its clock.
However, the controller will not then be able to detect Resume signaling on the USB. As a result, some
external hardware will be needed to detect Resume signaling (by monitoring the DM and DP signals),
so that the clock to the controller can be restarted.
•
•
Resume Signaling - When resume signaling occurs on the bus, first the clock to the controller must be
restarted if necessary. Then the controller will automatically exit Suspend mode. If the Resume
interrupt is enabled, an interrupt will be generated.
Initiating a remote wakeup - If the software wants to initiate a remote wakeup while the controller is in
Suspend mode, it should write to the Power register to set the RESUME bit to 1. The software should
leave then this bit set for approximately 10 ms (minimum of 2 ms, a maximum of 15 ms) before
resetting it to 0.
Note: No resume interrupt will be generated when the software initiates a remote wakeup.
•
Reset Signaling - When reset signaling occurs on the bus, the controller will perform the following
actions:
–
–
–
–
–
Sets FADDR register to 0
Sets INDEX register to 0
Flushes all endpoint FIFOs
Clears all control/status registers
Generates a reset interrupt.
If the HSENA bit in the POWER register (bit 5) was set, the controller also tries to negotiate for
high-speed operation.
Whether high-speed operation is selected is indicated by HSMODE bit of POWER register (bit 4).
When the application software receives a reset interrupt, it should close any open pipes and wait for
bus enumeration to begin.
3.1.1
Peripheral Mode: Control Transactions
Endpoint 0 is the main control endpoint of the core. The software is required to handle all the standard
device requests that may be sent or received via endpoint 0. These are described in Universal Serial Bus
Specification, Revision 2.0, Chapter 9. The protocol for these device requests involves different numbers
and types of transactions per transfer. To accommodate this, the software needs to take a state machine
approach to command decoding and handling.
The Standard Device Requests received by a USB peripheral device can be divided into three categories:
Zero Data Requests (in which all the information is included in the command), Write Requests (in which
the command will be followed by additional data), and Read Requests (in which the device is required to
send data back to the host).
This section looks at the sequence of actions that the software must perform to process these different
types of device request.
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Note: The Setup packet associated with any standard device request should include an 8-byte
command. Any setup packet containing a command field of anything other than 8 bytes will
be automatically rejected by the controller.
3.1.1.1
Zero Data Requests
Zero data requests have all their information included in the 8-byte command and require no additional
data to be transferred. Examples of Zero Data standard device requests are:
•
•
•
•
•
SET_FEATURE
CLEAR_FEATURE
SET_ADDRESS
SET_CONFIGURATION
SET_INTERFACE
The sequence of events will begin, as with all requests, when the software receives an endpoint 0
interrupt. The RXPKTRDY bit of PERI_CSR0 (bit 0) will also have been set. The 8-byte command should
then be read from the endpoint 0 FIFO, decoded and the appropriate action taken.
For example, if the command is SET_ADDRESS, the 7-bit address value contained in the command
should be written to the FADDR register. The PERI_CSR0 register should then be written to set the
SERV_RXPKTRDY bit (bit 6) (indicating that the command has been read from the FIFO) and to set the
DATAEND bit (bit 3) (indicating that no further data is expected for this request). The interval between
setting SERV_RXPKTRDY bit and DATAEND bit should be very small to avoid getting a SetupEnd error
condition.
When the host moves to the status stage of the request, a second endpoint 0 interrupt will be generated to
indicate that the request has completed. No further action is required from the software. The second
interrupt is just a confirmation that the request completed successfully. For SET_ADDRESS command,
the address should be set in FADDR register only after the status stage interrupt is received.
If the command is an unrecognized command, or for some other reason cannot be executed, then when it
has been decoded, the PERI_CSR0 register should be written to set the SERV_RXPKTRDY bit (bit 6) and
to set the SENDSTALL bit (bit 5). When the host moves to the status stage of the request, the controller
will send a STALL to tell the host that the request was not executed. A second endpoint 0 interrupt will be
generated and the SENTSTALL bit (bit 2 of PERI_CSR0) will be set.
If the host sends more data after the DATAEND bit has been set, then the controller will send a STALL.
An endpoint 0 interrupt will be generated and the SENTSTALL bit (bit 2 of PERI_CSR0) will be set.
Note: DMA is not supported for endpoint 0, so the command should be read by accessing the
endpoint 0 FIFO register.
3.1.1.2
Write Requests
Write requests involve an additional packet (or packets) of data being sent from the host after the 8-byte
command. An example of a Write standard device request is: SET_DESCRIPTOR.
The sequence of events will begin, as with all requests, when the software receives an endpoint 0
interrupt. The RXPKTRDY bit of PERI_CSR0 will also have been set. The 8-byte command should then
be read from the Endpoint 0 FIFO and decoded.
As with a zero data request, the PERI_CSR0 register should then be written to set the SERV_RXPKTRDY
bit (bit 6) (indicating that the command has been read from the FIFO) but in this case the DATAEND bit
(bit 3) should not be set (indicating that more data is expected).
When a second endpoint 0 interrupt is received, the PERI_CSR0 register should be read to check the
endpoint status. The RXPKTRDY bit of PERI_CSR0 should be set to indicate that a data packet has been
received. The COUNT0 register should then be read to determine the size of this data packet. The data
packet can then be read from the endpoint 0 FIFO.
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If the length of the data associated with the request (indicated by the wLength field in the command) is
greater than the maximum packet size for endpoint 0, further data packets will be sent. In this case,
PERI_CSR0 should be written to set the SERV_RXPKTRDY bit, but the DATAEND bit should not be set.
When all the expected data packets have been received, the PERI_CSR0 register should be written to set
the SERV_RXPKTRDY bit and to set the DATAEND bit (indicating that no more data is expected).
When the host moves to the status stage of the request, another endpoint 0 interrupt will be generated to
indicate that the request has completed. No further action is required from the software, the interrupt is
just a confirmation that the request completed successfully.
If the command is an unrecognized command, or for some other reason cannot be executed, then when it
has been decoded, the PERI_CSR0 register should be written to set the SERV_RXPKTRDY bit (bit 6) and
to set the SENDSTALL bit (bit 5). When the host sends more data, the controller will send a STALL to tell
the host that the request was not executed. An endpoint 0 interrupt will be generated and the SENTSTALL
bit of PERI_CSR0 (bit 2) will be set.
If the host sends more data after the DATAEND has been set, then the controller will send a STALL. An
endpoint 0 interrupt will be generated and the SENTSTALL bit of PERI_CSR0 (bit 2) will be set.
3.1.1.3
Read Requests
Read requests have a packet (or packets) of data sent from the function to the host after the 8-byte
command. Examples of Read Standard Device Requests are:
•
GET_CONFIGURATION
GET_INTERFACE
GET_DESCRIPTOR
GET_STATUS
•
•
•
•
SYNCH_FRAME
The sequence of events will begin, as with all requests, when the software receives an endpoint 0
interrupt. The RXPKTRDY bit of PERI_CSR0 (bit 0) will also have been set. The 8-byte command should
then be read from the endpoint 0 FIFO and decoded. The PERI_CSR0 register should then be written to
set the SERV_RXPKTRDY bit (bit 6) (indicating that the command has read from the FIFO).
The data to be sent to the host should then be written to the endpoint 0 FIFO. If the data to be sent is
greater than the maximum packet size for endpoint 0, only the maximum packet size should be written to
the FIFO. The PERI_CSR0 register should then be written to set the TXPKTRDY bit (bit 1) (indicating that
there is a packet in the FIFO to be sent). When the packet has been sent to the host, another endpoint 0
interrupt will be generated and the next data packet can be written to the FIFO.
When the last data packet has been written to the FIFO, the PERI_CSR0 register should be written to set
the TXPKTRDY bit and to set the DATAEND bit (bit 3) (indicating that there is no more data after this
packet).
When the host moves to the status stage of the request, another endpoint 0 interrupt will be generated to
indicate that the request has completed. No further action is required from the software: the interrupt is
just a confirmation that the request completed successfully.
If the command is an unrecognized command, or for some other reason cannot be executed, then when it
has been decoded, the PERI_CSR0 register should be written to set the SERV_RXPKTRDY bit (bit 6) and
to set the SENDSTALL bit (bit 5). When the host requests data, the controller will send a STALL to tell the
host that the request was not executed. An endpoint 0 interrupt will be generated and the SENTSTALL bit
of PERI_CSR0 (bit 2) will be set.
If the host requests more data after DATAEND (bit 3) has been set, then the controller will send a STALL.
An endpoint 0 interrupt will be generated and the SENTSTALL bit of PERI_CSR0 (bit 2) will be set.
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3.1.1.4
Endpoint 0 States
When the USB controller is operating as a peripheral device, the endpoint 0 control needs three modes –
IDLE, TX and RX – corresponding to the different phases of the control transfer and the states endpoint 0
enters for the different phases of the transfer (described in later sections).
The default mode on power-up or reset should be IDLE. RXPKTRDY bit of PERI_CSR0 (bit 0) becoming
set when endpoint 0 is in IDLE state indicates a new device request. Once the device request is unloaded
from the FIFO, the controller decodes the descriptor to find whether there is a data phase and, if so, the
direction of the data phase of the control transfer (in order to set the FIFO direction).See Figure 3.
Depending on the direction of the data phase, endpoint 0 goes into either TX state or RX state. If there is
no Data phase, endpoint 0 remains in IDLE state to accept the next device request.
The actions that the CPU needs to take at the different phases of the possible transfers (e.g., loading the
Note: The controller changes the FIFO direction, depending on the direction of the data phase
independently of the CPU.
Figure 3. CPU Actions at Transfer Phases
Sequence #3
Idle
Sequence #1
Sequence #2
Tx state
Rx state
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Figure 4. Sequence of Transfer
Idle
TX state
Idle
Status phase
(OUT)
IN data
phase
IN data
phase
IN data
phase
Sequence #1
Setup
Int
Int
Int
Int
Int
Unload device
req. and clear
RxPktRdy
Load FIFO
and set
TxPktRdy
Load FIFO
and set
TxPktRdy
Load FIFO and
set TxPktRdy
and set DataEnd
CPU actions
Idle
RX state
Idle
OUT data
phase
OUT data
phase
OUT data
Int
Status phase
(IN)
Sequence #2
CPU actions
Setup
Int
Int
Int
Int
phase
Unload
Unload FIFO
and clear
RxPktRdy
Unload FIFO
and clear
RxPktRdy
Unload FIFO and
clear RxPktRdy
and set DataEnd
device req.
and clear
RxPktRdy
No data phase
Status phase
(IN)
Sequence #3
CPU actions
Setup
Int
Int
Idle
Unload device req and
clear RxPktRdy and set
DataEnd
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3.1.1.5
Endpoint 0 Service Routine
An Endpoint 0 interrupt is generated when:
•
•
•
•
The controller sets the RXPKTRDY bit of PERI_CSR0 (bit 0) after a valid token has been received and
data has been written to the FIFO.
The controller clears the TXPKTRDY bit of PERI_CSR0 (bit 1) after the packet of data in the FIFO has
been successfully transmitted to the host.
The controller sets the SENTSTALL bit of PERI_CSR0 (bit 2) after a control transaction is ended due
to a protocol violation.
The controller sets the SETUPEND bit of PERI_CSR0 (bit 4) because a control transfer has ended
before DATAEND (bit 3 of PERI_CSR0) is set.
Whenever the endpoint 0 service routine is entered, the software must first check to see if the current
control transfer has been ended due to either a STALL condition or a premature end of control transfer. If
the control transfer ends due to a STALL condition, the SENTSTALL bit would be set. If the control
transfer ends due to a premature end of control transfer, the SETUPEND bit would be set. In either case,
the software should abort processing the current control transfer and set the state to IDLE.
Once the software has determined that the interrupt was not generated by an illegal bus state, the next
If endpoint 0 is in IDLE state, the only valid reason an interrupt can be generated is as a result of the
controller receiving data from the bus. The service routine must check for this by testing the RXPKTRDY
bit of PERI_CSR0 (bit 0). If this bit is set, then the controller has received a SETUP packet. This must be
unloaded from the FIFO and decoded to determine the action the controller must take. Depending on the
command contained within the SETUP packet, endpoint 0 will enter one of three states:
•
If the command is a single packet transaction (SET_ADDRESS, SET_INTERFACE etc.) without any
data phase, the endpoint will remain in IDLE state.
•
•
If the command has an OUT data phase (SET_DESCRIPTOR etc.), the endpoint will enter RX state.
If the command has an IN data phase ( GET_DESCRIPTOR etc.), the endpoint will enter TX state.
If the endpoint 0 is in TX state, the interrupt indicates that the core has received an IN token and data
from the FIFO has been sent. The software must respond to this either by placing more data in the FIFO if
the host is still expecting more data or by setting the DATAEND bit to indicate that the data phase is
complete. Once the data phase of the transaction has been completed, endpoint 0 should be returned to
IDLE state to await the next control transaction.
Note: All command transactions include a field that indicates the amount of data the host expects
to receive or is going to send.
If the endpoint is in RX state, the interrupt indicates that a data packet has been received. The software
must respond by unloading the received data from the FIFO. The software must then determine whether it
has received all of the expected data. If it has, the software should set the DATAEND bit and return
endpoint 0 to IDLE state. If more data is expected, the firmware should set the SERV_RXPKTRDY bit of
PERI_CSR0 (bit 6) to indicate that it has read the data in the FIFO and leave the endpoint in RX state.
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Figure 5. Service Endpoint 0 Flow Chart
Service
endpoint 0
Read endpoint 0 CSR
Sent
stall
?
Yes
Yes
Yes
Yes
Yes
Clear SentStall bit
state −> IDLE
No
Setup
end
?
Set ServicedSetupEnd
state −> IDLE
No
State
= IDLE
?
IDLE mode
TX mode
RX mode
No
State
= TX
?
No
State
= RX*
?
* By default
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3.1.1.5.1 IDLE Mode
IDLE mode is the mode the endpoint 0 control must select at power-on or reset and is the mode to which
the endpoint 0 control should return when the RX and TX modes are terminated. It is also the mode in
Figure 6. IDLE Mode Flow Chart
IDLE mode
No
RxPktRdy
Return
set?
Yes
Unload FIFO
Decode command
Command
No
Process command
has data
phase
?
Set ServicedRxPktRdy
Set DataEnd
Yes
Set
ServiceRxPktRdy
Return
Data
phase = IN
?
Yes
State −> TX
Return
No
State −> RX
Return
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3.1.1.5.2 TX Mode
When the endpoint is in TX state all arriving IN tokens need to be treated as part of a data phase until the
required amount of data has been sent to the host. If either a SETUP or an OUT token is received while
the endpoint is in the TX state, this will cause a SetupEnd condition to occur as the core expects only IN
Three events can cause TX mode to be terminated before the expected amount of data has been sent:
1. The host sends an invalid token causing a SETUPEND condition (bit 4 of PERI_CSR0 set).
2. The software sends a packet containing less than the maximum packet size for endpoint 0.
3. The software sends an empty data packet.
Until the transaction is terminated, the software simply needs to load the FIFO when it receives an
interrupt that indicates a packet has been sent from the FIFO. (An interrupt is generated when
TXPKTRDY is cleared.)
When the software forces the termination of a transfer (by sending a short or empty data packet), it should
set the DATAEND bit of PERI_CSR0 (bit 3) to indicate to the core that the data phase is complete and
that the core should next receive an acknowledge packet.
Figure 7. TX Mode Flow Chart
TX mode
Write
ꢀ MaxP bytes
to FIFO
Last
packet
?
No
Set
TxPktRdy
Yes
Set TxPktRdy
and set DataEnd
state −> IDLE
Return
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3.1.1.5.3 RX Mode
In RX mode, all arriving data should be treated as part of a data phase until the expected amount of data
has been received. If either a SETUP or an IN token is received while the endpoint is in RX state, a
SetupEnd condition will occur as the controller expects only OUT tokens.
Three events can cause RX mode to be terminated before the expected amount of data has been
1. The host sends an invalid token causing a SETUPEND condition (setting bit 4 of PERI_CSR0).
2. The host sends a packet which contains less than the maximum packet size for endpoint 0.
3. The host sends an empty data packet.
Until the transaction is terminated, the software unloads the FIFO when it receives an interrupt that
indicates new data has arrived (setting RXPKTRDY bit of PERI_CSR0) and to clear RXPKTRDY by
setting the SERV_RXPKTRDY bit of PERI_CSR0 (bit 6).
When the software detects the termination of a transfer (by receiving either the expected amount of data
or an empty data packet), it should set the DATAEND bit (bit 3 of PERI_CSR0) to indicate to the controller
that the data phase is complete and that the core should receive an acknowledge packet next.
Figure 8. RX Mode Flow Chart
RX mode
No
RxPktRdy
set
Return
?
Yes
Read Count0
register (n)
Unload n bytes
from FIFO
No
Last
packet
?
Set
ServicedRxPktRdy
Yes
Set
ServicedRxPktRdy
and DataEnd
state->IDLE
Return
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3.1.1.5.4 Error Handling
A control transfer may be aborted due to a protocol error on the USB, the host prematurely ending the
transfer, or if the software wishes to abort the transfer (e.g., because it cannot process the command).
The controller automatically detects protocol errors and sends a STALL packet to the host under the
following conditions:
•
The host sends more data during the OUT Data phase of a write request than was specified in the
command. This condition is detected when the host sends an OUT token after the DATAEND bit (bit 3
of PERI_CSR0) has been set.
•
The host requests more data during the IN Data phase of a read request than was specified in the
command. This condition is detected when the host sends an IN token after the DATAEND bit in the
PERI_CSR0 register has been set.
•
•
The host sends more than Max Packet Size data bytes in an OUT data packet.
The host sends a non-zero length DATA1 packet during the STATUS phase of a read request.
When the controller has sent the STALL packet, it sets the SENTSTALL bit (bit 2 of PERI_CSR0) and
generates an interrupt. When the software receives an endpoint 0 interrupt with the SENTSTALL bit set, it
should abort the current transfer, clear the SENTSTALL bit, and return to the IDLE state.
If the host prematurely ends a transfer by entering the STATUS phase before all the data for the request
has been transferred, or by sending a new SETUP packet before completing the current transfer, then the
SETUPEND bit (bit 4 of PERI_CSR0) will be set and an endpoint 0 interrupt generated. When the
software receives an endpoint 0 interrupt with the SETUPEND bit set, it should abort the current transfer,
set the SERV_SETUPEND bit (bit 7 of PERI_CSR0), and return to the IDLE state. If the RXPKTRDY bit
(bit 0 of PERI_CSR0) is set this indicates that the host has sent another SETUP packet and the software
should then process this command.
If the software wants to abort the current transfer, because it cannot process the command or has some
other internal error, then it should set the SENDSTALL bit (bit 5 of PERI_CSR0). The controller will then
send a STALL packet to the host, set the SENTSTALL bit (bit 2 of PERI_CSR0) and generate an endpoint
0 interrupt.
3.1.1.5.5 Additional Conditions
When working as a peripheral device, the controller automatically responds to certain conditions on the
USB bus or actions by the host. The details are given below:
•
Stall Issued to Control Transfers
–
The host sends more data during an OUT Data phase of a Control transfer than was specified in
the device request during the SETUP phase. This condition is detected by the controller when the
host sends an OUT token (instead of an IN token) after the software has unloaded the last OUT
packet and set DataEnd.
–
The host requests more data during an IN data phase of a Control transfer than was specified in
the device request during the SETUP phase. This condition is detected by the controller when the
host sends an IN token (instead of an OUT token) after the software has cleared TXPKTRDY and
set DataEnd in response to the ACK issued by the host to what should have been the last packet.
–
–
–
The host sends more than MaxPktSize data with an OUT data token.
The host sends the wrong PID for the OUT Status phase of a Control transfer.
The host sends more than a zero length data packet for the OUT Status phase.
•
Zero Length Out Data Packets In Control Transfer
–
A zero length OUT data packet is used to indicate the end of a Control transfer. In normal
operation, such packets should only be received after the entire length of the device request has
been transferred (i.e., after the software has set DataEnd). If, however, the host sends a zero
length OUT data packet before the entire length of device request has been transferred, this signals
the premature end of the transfer. In this case, the controller will automatically flush any IN token
loaded by software ready for the Data phase from the FIFO and set SETUPEND bit (bit 4 of
PERI_CSR0).
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3.1.2
Bulk Transactions
3.1.2.1
Peripheral Mode: Bulk In Transactions
A Bulk IN transaction is used to transfer non-periodic data from the USB peripheral device to the host.
The following optional features are available for use with a Tx endpoint used in peripheral mode for Bulk
IN transactions:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting
transmission to the host. Double packet buffering is enabled by setting the DPB bit of TXFIFOSZ
register (bit 4).
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint is
able to accept another packet in its FIFO. This feature allows the DMA controller to load packets into
the FIFO without processor intervention.
When DMA is enabled and DMAMODE bit of PERI_TXCSR is set, an endpoint interrupt is not
generated for completion of the packet transfer. An endpoint interrupt is generated only in the error
conditions.
3.1.2.1.1 Setup
In configuring a TX endpoint for bulk transactions, the TXMAXP register must be written with the
maximum packet size (in bytes) for the endpoint. This value should be the same as the wMaxPacketSize
field of the Standard Endpoint Descriptor for the endpoint and the PERI_TXCSR register should be set as
Table 2. PERI_TXCSR Register Bit Configuration for Bulk IN Transactions
Bit Position
Bit 14
Bit Field Name Configuration
ISO
Cleared to 0 for bulk mode operation
Bit 13
MODE
Set to 1 to make sure the FIFO is enabled (only necessary if the FIFO is shared with an RX
endpoint)
Bit 12
Bit 11
Bit 10
DMAEN
Set to 1 if DMA requests must be enabled
FRCDATATOG Cleared to 0 to allow normal data toggle operations
DMAMODE Set to 1 when DMA is enabled and EP interrupt is not needed for each packet transmission
When the endpoint is first configured (following a SET_CONFIGURATION or SET_INTERFACE command
on Endpoint 0), the lower byte of PERI_TXCSR should be written to set the CLRDATATOG bit (bit 6). This
will ensure that the data toggle (which is handled automatically by the controller) starts in the correct state.
Also if there are any data packets in the FIFO (indicated by the FIFONOTEMPTY bit (bit 1 of
PERI_TXCSR) being set), they should be flushed by setting the FLUSHFIFO bit (bit 3 of PERI_TXCSR).
Note: It may be necessary to set this bit twice in succession if double buffering is enabled.
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3.1.2.1.2 Operation
When data is to be transferred over a Bulk IN pipe, a data packet needs to be loaded into the FIFO and
the PERI_TXCSR register written to set the TXPKTRDY bit (bit 0). When the packet has been sent, the
TXPKTRDY bit will be cleared by the USB controller and an interrupt generated so that the next packet
can be loaded into the FIFO. If double packet buffering is enabled, then after the first packet has been
loaded and the TXPKTRDY bit set, the TXPKTRDY bit will immediately be cleared by the USB controller
and an interrupt generated so that a second packet can be loaded into the FIFO. The software should
operate in the same way, loading a packet when it receives an interrupt, regardless of whether double
packet buffering is enabled or not.
In the general case, the packet size must not exceed the size specified by the lower 11 bits of the
TXMAXP register. This part of the register defines the payload (packet size) for transfers over the USB
and is required by the USB Specification to be either 8, 16, 32, 64 (Full-Speed or High-Speed) or 512
bytes (High-Speed only).
The host may determine that all the data for a transfer has been sent by knowing the total amount of data
that is expected. Alternatively it may infer that all the data has been sent when it receives a packet which
is smaller than the stated payload (TXMAXP [bit 10 : bit 0]). In the latter case, if the total size of the data
block is a multiple of this payload, it will be necessary for the function to send a null packet after all the
data has been sent. This is done by setting TXPKTRDY when the next interrupt is received, without
loading any data into the FIFO.
If large blocks of data are being transferred, then the overhead of calling an interrupt service routine to
load each packet can be avoided by using DMA.
3.1.2.1.3 Error Handling
If the software wants to shut down the Bulk IN pipe, it should set the SENDSTALL bit (bit 4 of
PERI_TXCSR). When the controller receives the next IN token, it will send a STALL to the host, set the
SENTSTALL bit (bit 5 of PERI_TXCSR) and generate an interrupt.
When the software receives an interrupt with the SENTSTALL bit (bit 5 of PERI_TXCSR) set, it should
clear the SENTSTALL bit. It should however leave the SENDSTALL bit set until it is ready to re-enable the
Bulk IN pipe.
Note: If the host failed to receive the STALL packet for some reason, it will send another IN token,
so it is advisable to leave the SENDSTALL bit set until the software is ready to re-enable the
Bulk IN pipe. When a pipe is re-enabled, the data toggle sequence should be restarted by
setting the CLRDATATOG bit in the PERI_TXCSR register (bit 6).
3.1.2.2
Peripheral Mode: Bulk OUT Transactions
A Bulk OUT transaction is used to transfer non-periodic data from the host to the function controller.
The following optional features are available for use with an Rx endpoint used in peripheral mode for Bulk
OUT transactions:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception
from the host. Double packet buffering is enabled by setting the DPB bit of the RXFIFOSZ register (bit
4).
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint has
a packet in its FIFO. This feature can be used to allow the DMA controller to unload packets from the
FIFO without processor intervention.
When DMA is enabled, endpoint interrupt will not be generated for completion of packet reception.
Endpoint interrupt will be generated only in the error conditions.
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3.1.2.2.1 Setup
In configuring an Rx endpoint for Bulk OUT transactions, the RXMAXP register must be written with the
maximum packet size (in bytes) for the endpoint. This value should be the same as the wMaxPacketSize
field of the Standard Endpoint Descriptor for the endpoint. In addition, the relevant interrupt enable bit in
the INTRRXE register should be set (if an interrupt is required for this endpoint) and the PERI_RXCSR
Table 3. PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions
Bit Position
Bit 14
Bit Field Name Configuration
ISO
Cleared to 0 to enable Bulk protocol
Bit 13
DMAEN
DISNYET
DMAMODE
Set to 1 if a DMA request is required for this endpoint
Cleared to 0 to allow normal PING flow control. This will affect only high speed transactions.
Always set this bit to 0
Bit 12
Bit 11
When the endpoint is first configured (following a SET_CONFIGURATION or SET_INTERFACE command
on Endpoint 0), the lower byte of PERI_RXCSR should be written to set the CLRDATATOG bit (bit 7).
This will ensure that the data toggle (which is handled automatically by the USB controller) starts in the
correct state.
Also if there are any data packets in the FIFO (indicated by the RXPKTRDY bit (bit 0 of PERI_RXCSR)
being set), they should be flushed by setting the FLUSHFIFO bit (bit 4 of PERI_RXCSR).
Note: It may be necessary to set this bit twice in succession if double buffering is enabled.
3.1.2.2.2 Operation
When a data packet is received by a Bulk Rx endpoint, the RXPKTRDY bit (bit 0 of PERI_RXCSR) is set
and an interrupt is generated. The software should read the RXCOUNT register for the endpoint to
determine the size of the data packet. The data packet should be read from the FIFO, then the
RXPKTRDY bit should be cleared.
The packets received should not exceed the size specified in the RXMAXP register (as this should be the
value set in the wMaxPacketSize field of the endpoint descriptor sent to the host). When a block of data
larger than wMaxPacketSize needs to be sent to the function, it will be sent as multiple packets. All the
packets will be wMaxPacketSize in size, except the last packet which will contain the residue. The
software may use an application specific method of determining the total size of the block and hence when
the last packet has been received. Alternatively it may infer that the entire block has been received when it
receives a packet which is less than wMaxPacketSize in size. (If the total size of the data block is a
multiple of wMaxPacketSize, a null data packet will be sent after the data to signify that the transfer is
complete.)
In the general case, the application software will need to read each packet from the FIFO individually. If
large blocks of data are being transferred, the overhead of calling an interrupt service routine to unload
each packet can be avoided by using DMA.
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3.1.2.2.3 Error Handling
If the software wants to shut down the Bulk OUT pipe, it should set the SENDSTALL bit (bit 5 of
PERI_RXCSR). When the controller receives the next packet it will send a STALL to the host, set the
SENTSTALL bit (bit 6 of PERI_RXCSR) and generate an interrupt.
When the software receives an interrupt with the SENTSTALL bit (bit 6 of PERI_RXCSR) set, it should
clear this bit. It should however leave the SENDSTALL bit set until it is ready to re-enable the Bulk OUT
pipe.
Note: If the host failed to receive the STALL packet for some reason, it will send another packet, so
it is advisable to leave the SENDSTALL bit set until the software is ready to re-enable the
Bulk OUT pipe. When a Bulk OUT pipe is re-enabled, the data toggle sequence should be
restarted by setting the CLRDATATOG bit (bit 7) in the PERI_RXCSR register.
3.1.3
Interrupt Transactions
An Interrupt IN transaction uses the same protocol as a Bulk IN transaction and can be used the same
way. Similarly, an Interrupt OUT transaction uses almost the same protocol as a Bulk OUT transaction
and can be used the same way.
Tx endpoints in the USB controller have one feature for Interrupt IN transactions that they do not support
in Bulk IN transactions. In Interrupt IN transactions, the endpoints support continuous toggle of the data
toggle bit.
This feature is enabled by setting the FRCDATATOG bit in the PERI_TXCSR register (bit 11). When this
bit is set, the controller will consider the packet as having been successfully sent and toggle the data bit
for the endpoint, regardless of whether an ACK was received from the host.
Another difference is that interrupt endpoints do not support PING flow control. This means that the
controller should never respond with a NYET handshake, only ACK/NAK/STALL. To ensure this, the
DISNYET bit in the PERI_RXCSR register (bit 12) should be set to disable the transmission of NYET
handshakes in high-speed mode.
Though DMA can be used with an interrupt OUT endpoint, it generally offers little benefit as interrupt
endpoints are usually expected to transfer all their data in a single packet.
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3.1.4
Isochronous Transactions
3.1.4.1
Isochronous IN Transactions
An Isochronous IN transaction is used to transfer periodic data from the function controller to the host.
The following optional features are available for use with a Tx endpoint used in Peripheral mode for
Isochronous IN transactions:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting
transmission to the host. Double packet buffering is enabled by setting the DPB bit of TXFIFOSZ
register (bit 4).
Note: Double packet buffering is generally advisable for Isochronous transactions in order to avoid
Underrun errors as described in later section.
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint is
able to accept another packet in its FIFO. This feature allows the DMA controller to load packets into
the FIFO without processor intervention.
However, this feature is not particularly useful with Isochronous endpoints because the packets
transferred are often not maximum packet size and the PERI_TXCSR register needs to be accessed
following every packet to check for Underrun errors.
When DMA is enabled and DMAMODE bit of PERI_TXCSR is set, endpoint interrupt will not be
generated for completion of packet transfer. Endpoint interrupt will be generated only in the error
conditions.
3.1.4.1.1 Setup
In configuring a Tx endpoint for Isochronous IN transactions, the TXMAXP register must be written with
the maximum packet size (in bytes) for the endpoint. This value should be the same as the
wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint. In addition, the relevant
interrupt enable bit in the INTRTXE register should be set (if an interrupt is required for this endpoint) and
Table 4. PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions
Bit Position
Bit 14
Bit Field Name Configuration
ISO
Set to 1 to enable Isochronous transfer protocol
Bit 13
MODE
Set to 1 to ensure the FIFO is enabled (only necessary if the FIFO is shared with an Rx
endpoint).
Bit 12
Bit 11
Bit 10
DMAEN
Set to 1 if DMA Requests have to be enabled
FRCDATATOG Ignored in Isochronous mode
DMAMODE Set it to 1, when DMA is enabled and EP interrupt is not needed for each packet transmission
3.1.4.1.2 Operation
An Isochronous endpoint does not support data retries, so if data underrun is to be avoided, the data to be
sent to the host must be loaded into the FIFO before the IN token is received. The host will send one IN
token per frame (or microframe in High-speed mode), however the timing within the frame (or microframe)
can vary. If an IN token is received near the end of one frame and then at the start of the next frame,
there will be little time to reload the FIFO. For this reason, double buffering of the endpoint is usually
necessary.
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An interrupt is generated whenever a packet is sent to the host and the software may use this interrupt to
load the next packet into the FIFO and set the TXPKTRDY bit in the PERI_TXCSR register (bit 0) in the
same way as for a Bulk Tx endpoint. As the interrupt could occur almost any time within a
frame(/microframe), depending on when the host has scheduled the transaction, this may result in
irregular timing of FIFO load requests. If the data source for the endpoint is coming from some external
hardware, it may be more convenient to wait until the end of each frame(/microframe) before loading the
FIFO as this will minimize the requirement for additional buffering. This can be done by using either the
SOF interrupt or the external SOF_PULSE signal from the controller to trigger the loading of the next data
packet. The SOF_PULSE is generated once per frame(/microframe) when a SOF packet is received. (The
controller also maintains an external frame(/microframe) counter so it can still generate a SOF_PULSE
when the SOF packet has been lost.) The interrupts may still be used to set the TXPKTRDY bit in
PERI_TXCSR (bit 0) and to check for data overruns/underruns.
Starting up a double-buffered Isochronous IN pipe can be a source of problems. Double buffering requires
that a data packet is not transmitted until the frame(/microframe) after it is loaded. There is no problem if
the function loads the first data packet at least a frame(/microframe) before the host sets up the pipe (and
therefore starts sending IN tokens). But if the host has already started sending IN tokens by the time the
first packet is loaded, the packet may be transmitted in the same frame(/microframe) as it is loaded,
depending on whether it is loaded before, or after, the IN token is received. This potential problem can be
avoided by setting the ISOUPDATE bit in the POWER register (bit 7). When this bit is set, any data packet
loaded into an Isochronous Tx endpoint FIFO will not be transmitted until after the next SOF packet has
been received, thereby ensuring that the data packet is not sent too early.
3.1.4.1.3 Error Handling
If the endpoint has no data in its FIFO when an IN token is received, it will send a null data packet to the
host and set the UNDERRUN bit in the PERI_TXCSR register (bit 2). This is an indication that the
software is not supplying data fast enough for the host. It is up to the application to determine how this
error condition is handled.
If the software is loading one packet per frame(/microframe) and it finds that the TXPKTRDY bit in the
PERI_TXCSR register (bit 0) is set when it wants to load the next packet, this indicates that a data packet
has not been sent (perhaps because an IN token from the host was corrupted). It is up to the application
how it handles this condition: it may choose to flush the unsent packet by setting the FLUSHFIFO bit in
the PERI_TXCSR register (bit 3), or it may choose to skip the current packet.
3.1.4.2
Isochronous OUT Transactions
An Isochronous OUT transaction is used to transfer periodic data from the host to the function controller.
Following optional features are available for use with an Rx endpoint used in Peripheral mode for
Isochronous OUT transactions:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception
from the host. Double packet buffering is enabled by setting the DPB bit of RXFIFOSZ register (bit 4).
Note: Double packet buffering is generally advisable for Isochronous transactions in order to avoid
Overrun errors.
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint has
a packet in its FIFO. This feature can be used to allow the DMA controller to unload packets from the
FIFO without processor intervention.
However, this feature is not particularly useful with Isochronous endpoints because the packets
transferred are often not maximum packet size and the PERI_RXCSR register needs to be accessed
following every packet to check for Overrun or CRC errors.
When DMA is enabled, endpoint interrupt will not be generated for completion of packet reception.
Endpoint interrupt will be generated only in the error conditions.
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3.1.4.2.1 Setup
In configuring an Rx endpoint for Isochronous OUT transactions, the RXMAXP register must be written
with the maximum packet size (in bytes) for the endpoint. This value should be the same as the
wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint. In addition, the relevant
interrupt enable bit in the INTRRXE register should be set (if an interrupt is required for this endpoint) and
Table 5. PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions
Bit Position
Bit 14
Bit Field Name Configuration
ISO
Set to 1 to enable isochronous protocol
Bit 13
DMAEN
DISNYET
DMAMODE
Set to 1 if a DMA request is required for this endpoint
Ignored in isochronous transfers
Bit 12
Bit 11
Always set this bit to 0
3.1.4.2.2 Operation
An Isochronous endpoint does not support data retries so, if a data overrun is to be avoided, there must
be space in the FIFO to accept a packet when it is received. The host will send one packet per frame (or
microframe in High-speed mode); however, the time within the frame can vary. If a packet is received near
the end of one frame(/microframe) and another arrives at the start of the next frame, there will be little time
to unload the FIFO. For this reason, double buffering of the endpoint is usually necessary.
An interrupt is generated whenever a packet is received from the host and the software may use this
interrupt to unload the packet from the FIFO and clear the RXPKTRDY bit in the PERI_RXCSR register
(bit 0) in the same way as for a Bulk Rx endpoint. As the interrupt could occur almost any time within a
frame(/microframe), depending on when the host has scheduled the transaction, the timing of FIFO unload
requests will probably be irregular. If the data sink for the endpoint is going to some external hardware, it
may be better to minimize the requirement for additional buffering by waiting until the end of each
frame(/microframe) before unloading the FIFO. This can be done by using either the SOF interrupt or the
external SOF_PULSE signal from the controller to trigger the unloading of the data packet. The
SOF_PULSE is generated once per frame(/microframe) when a SOF packet is received. (The controller
also maintains an external frame(/microframe) counter so it can still generate a SOF_PULSE when the
SOF packet has been lost.) The interrupts may still be used to clear the RXPKTRDY bit in PERI_RXCSR
and to check for data overruns/underruns.
3.1.4.2.3 Error Handling
If there is no space in the FIFO to store a packet when it is received from the host, the OVERRUN bit in
the PERI_RXCSR register (bit 2) will be set. This is an indication that the software is not unloading data
fast enough for the host. It is up to the application to determine how this error condition is handled.
If the controller finds that a received packet has a CRC error, it will still store the packet in the FIFO and
set the RXPKTRDY bit (bit 0 of PERI_RXCSR) and the DATAERROR bit (bit 3 of PERI_RXCSR). It is left
up to the application how this error condition is handled.
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3.2 USB Controller Host Mode Operation
•
•
•
•
Entry into Suspend mode. When operating as a host, the controller can be prompted to enter Suspend
mode by setting the SUSPENDM bit in the POWER register. When this bit is set, the controller will
complete the current transaction then stop the transaction scheduler and frame counter. No further
transactions will be started and no SOF packets will be generated. If the ENSUSPM bit (bit 0 of
POWER register) is set, PHY will go into low-power mode when the controller enters Suspend mode.
Sending Resume Signaling. When the application requires the controller to leave Suspend mode, it
must clear the SUSPENDM bit in the POWER register (bit 1), set the RESUME bit (bit 2) and leave it
set for 20ms. While the RESUME bit is high, the controller will generate Resume signaling on the bus.
After 20 ms, the application should clear the Resume bit, at which point the frame counter and
transaction scheduler will be started.
Responding to Remote Wake-up. If Resume signaling is detected from the target while the controller is
in Suspend mode, the PHY will be brought out of low-power mode. The controller will then exit
Suspend mode and automatically set the RESUME bit in the POWER register (bit 2) to take over
generating the Resume signaling from the target. If the Resume interrupt is enabled, an interrupt will
be generated.
Reset Signaling. If the RESET bit in the POWER register (bit 3) is set while the controller is in Host
mode, it will generate Reset signaling on the bus. If the HSENAB bit in the POWER register (bit 5) was
set, it will also try to negotiate for high-speed operation. The software should keep the RESET bit set
for at least 20 ms to ensure correct resetting of the target device. After the software has cleared the bit,
the controller will start its frame counter and transaction scheduler. Whether high-speed operation is
selected will be indicated by HSMODE bit of POWER register (bit 4).
3.2.1
Host Mode: Control Transactions
Host Control Transactions are conducted through Endpoint 0 and the software is required to handle all the
Standard Device Requests that may be sent or received via Endpoint 0 (as described in Universal Serial
Bus Specification, Revision 2.0, Chapter 9).
As for a USB peripheral device, there are three categories of Standard Device Requests to be handled:
Zero Data Requests (in which all the information is included in the command), Write Requests (in which
the command will be followed by additional data), and Read Requests (in which the device is required to
send data back to the host).
1. Zero Data Requests consist of a SETUP command followed by an IN Status Phase
2. Write Requests consist of a SETUP command, followed by an OUT Data Phase which is in turn
followed by an IN Status Phase
3. Read Requests consist of a SETUP command, followed by an IN Data Phase which is in turn followed
by an OUT Status Phase
A timeout may be set to limit the length of time for which the controller will retry a transaction which is
continually NAKed by the target. This limit can be between 2 and 215 frames/ microframes and is set
through the HOST_NAKLIMIT0 register. The following sections describe the CPU actions required for
these different types of requests by examining the steps to take in the different Control Transaction
phases.
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3.2.1.1
Setup Phase
For the SETUP Phase of a control transaction (Figure 9), the software driving the US host device needs
to:
1. Load the 8 bytes of the required Device request command into the Endpoint 0 FIFO.
2. Set SETUPPKT and TXPKTRDY (bits 3 and 1 of HOST_CSR0, respectively).
Note: These bits must be set together.
The controller then proceeds to send a SETUP token followed by the 8-byte command to Endpoint 0 of
the addressed device, retrying as necessary. (On errors, controller retries the transaction three times.)
Figure 9. Setup Phase of a Control Transaction Flow Chart
Transaction
scheduled
TxPktRdy
and SetupPkt
No
both set
?
Yes
SETUP token sent
DATA0 oacket sent
Command not
supported by
target
RxStall set
Stall
received
?
Yes
Yes
TxPktRdy cleared
Error Count cleared
interrupt generated
No
ACK
received
?
TxPktRdy cleared
Error Count cleared
Interrupt generated
No
Transaction
complete
NAK limit
reached
?
NAK
received
?
No
Yes
Error count
cleared
No
Yes
Error count
incremented
NAK Timeout set
Endpoint halted
Interrupt generated
Implies problem
at peripheral end
of connection.
Error bit set
Error
count=3
?
No
Yes
TxPktRdy cleared
Error Count cleared
interrupt generated
Transaction deemed
complete
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3. At the end of the attempt to send the data, the controller will generate an Endpoint 0 interrupt. The
software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit
(bit 4) or the NAK_TIMEOUT bit (bit 7) has been set.
If RXSTALL is set, it indicates that the target did not accept the command (e.g., because it is not
supported by the target device) and so has issued a STALL response.
If ERROR is set, it means that the controller has tried to send the SETUP Packet and the following
data packet three times without getting any response.
If NAK_TIMEOUT is set, it means that the controller has received a NAK response to each attempt to
send the SETUP packet, for longer than the time set in HOST_NAKLIMIT0. The controller can then be
directed either to continue trying this transaction (until it times out again) by clearing the
NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT
bit.
4. If none of RXSTALL, ERROR or NAK_TIMEOUT is set, the SETUP Phase has been correctly ACKed
and the software should proceed to the following IN Data Phase, OUT Data Phase or IN Status Phase
specified for the particular Standard Device Request.
3.2.1.2
IN Data Phase
For the IN Data Phase of a control transaction (Figure 10), the software driving the USB host device
needs to:
1. Set REQPKT bit of HOST_CSR0 (bit 5).
2. Wait while the controller sends the IN token and receives the required data back.
3. When the controller generates the Endpoint 0 interrupt, read HOST_CSR0 to establish whether the
RXSTALL bit (bit 2), the ERROR bit (bit 4), the NAK_TIMEOUT bit (bit 7) or RXPKTRDY bit (bit 0) has
been set.
If RXSTALL is set, it indicates that the target has issued a STALL response.
If ERROR is set, it means that the controller has tried to send the required IN token three times without
getting any response.
If NAK_TIMEOUT bit is set, it means that the controller has received a NAK response to each attempt
to send the IN token, for longer than the time set in HOST_NAKLIMIT0. The controller can then be
directed either to continue trying this transaction (until it times out again) by clearing the
NAK_TIMEOUT bit or to abort the transaction by clearing REQPKT before clearing the NAK_TIMEOUT
bit.
4. If RXPKTRDY has been set, the software should read the data from the Endpoint 0 FIFO, then clear
RXPKTRDY.
5. If further data is expected, the software should repeat Steps 1-4.
When all the data has been successfully received, the CPU should proceed to the OUT Status Phase of
the Control Transaction.
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Figure 10. IN Data Phase Flow Chart
For each IN packet
requested in SETUP phase
ReqPkt
No
set
?
Yes
IN token sent
Problem in
data sent
RxStall set
ReqPkt cleared
Error Count cleared
Interrupt generated
STALL
received
?
Yes
No
NAK limit
reached
?
NAK
received
?
No
Yes
Error count
cleared
No
Yes
NAK Timeout set
Endpoint halted
Interrupt generated
Data0/1
received
?
ACK sent
RxPktRdy
set
ReqPkt cleared
Error Count cleared
Interrupt generated
Yes
No
Error count
incremented
Transaction
complete
Implies problem
at peripheral end
of connection.
Error bit set
Error
count=3
?
No
Yes
ReqPkt cleared
Error Count cleared
Interrupt generated
Transaction deemed
complete
3.2.1.3
OUT Data Phase
For the OUT Data Phase of a control transaction (Figure 11), the software driving the USB host device
needs to:
1. Load the data to be sent into the endpoint 0 FIFO.
2. Set the TXPKTRDY bit of HOST_CSR0 (bit 1). The controller then proceeds to send an OUT token
followed by the data from the FIFO to Endpoint 0 of the addressed device, retrying as necessary.
3. At the end of the attempt to send the data, the controller will generate an Endpoint 0 interrupt. The
software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit
(bit 4) or the NAK_TIMEOUT bit (bit 7) has been set.
If RXSTALL bit is set, it indicates that the target has issued a STALL response.
If ERROR bit is set, it means that the controller has tried to send the OUT token and the following data
packet three times without getting any response.
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If NAK_TIMEOUT is set, it means that the controller has received a NAK response to each attempt to
send the OUT token, for longer than the time set in the HOST_NAKLIMIT0 register. The controller can
then be directed either to continue trying this transaction (until it times out again) by clearing the
NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT
bit.
If none of RXSTALL, ERROR or NAKLIMIT is set, the OUT data has been correctly ACKed.
4. If further data needs to be sent, the software should repeat Steps 1-3.
When all the data has been successfully sent, the software should proceed to the IN Status Phase of
the Control Transaction.
Figure 11. OUT Data Phase Flow Chart
For each OUT packet
specified in SETUP phase
TxPktRdy
No
set
?
Yes
OUT token sent
DATA0/1 packet sent
Command could
not be completed
RxStall set
Stall
received
?
Yes
Yes
TxPktRdy cleared
Error Count cleared
interrupt generated
No
ACK
received
?
TxPktRdy cleared
Error Count cleared
Interrupt generated
No
Transaction
complete
NAK limit
reached
?
NAK
received
?
No
Yes
Error count
cleared
No
Yes
Error count
incremented
NAK Timeout set
Endpoint halted
Interrupt generated
Implies problem
at peripheral end
of connection.
Error bit set
Error
count=3
?
No
Yes
TxPktRdy cleared
Error Count cleared
interrupt generated
Transaction deemed
complete
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3.2.1.4
IN Status Phase (following SETUP Phase or OUT Data Phase)
For the IN Status Phase of a Control Transaction (Figure 12), the software driving the USB Host device
needs to:
1. Set the STATUSPKT and REQPKT bits of HOST_CSR0 (bit 6 and bit 5, respectively).
2. Wait while the controller sends an IN token and receives a response from the USB peripheral device.
Figure 12. Completion of SETUP or OUT Data Phase Flow Chart
Completion of either SETUP
phase or OUT data phase
ReqPkt
and StatusPkt
No
both set
?
Yes
IN token sent
Command could
RxStall set
ReqPkt cleared
Error Count cleared
Interrupt generated
STALL
received
?
not be completed
Yes
No
NAK limit
reached
?
NAK
received
?
No
Yes
Error count
cleared
No
Yes
NAK Timeout set
Endpoint halted
Interrupt generated
Data1
received
?
ACK sent
RxPktRdy
set
ReqPkt cleared
Error Count cleared
Interrupt generated
Yes
No
Error count
incremented
Transaction
complete
Implies problem
at peripheral end
of connection.
Error bit set
Error
count=3
?
No
Yes
ReqPkt cleared
Error Count cleared
Interrupt generated
Transaction deemed
complete
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3. When the controller generates the Endpoint 0 interrupt, read HOST_CSR0 to establish whether the
RXSTALL bit (bit 2), the ERROR bit (bit 4), the NAK_TIMEOUT bit (bit 7) or RXPKTRDY bit (bit 0) has
been set.
If RXSTALL bit is set, it indicates that the target could not complete the command and so has issued a
STALL response.
If ERROR bit is set, it means that the controller has tried to send the required IN token three times
without getting any response.
If NAK_TIMEOUT bit is set, it means that the controller has received a NAK response to each attempt
to send the IN token, for longer than the time set in the HOST_NAKLIMIT0 register. The controller can
then be directed either to continue trying this transaction (until it times out again) by clearing the
NAK_TIMEOUT bit or to abort the transaction by clearing REQPKT bit and STATUSPKT bit before
clearing the NAK_TIMEOUT bit.
4. If RxPktRdy has been set, the CPU should simply clear RxPktRdy.
3.2.1.5
OUT Status Phase (following IN Data Phase)
For the OUT Status Phase of a control transaction (Figure 13), the CPU driving the host device needs to:
1. Set STATUSPKT and TXPKTRDY bits of HOST_CSR0 (bit 6 and bit 1, respectively).
Note: These bits need to be set together.
2. Wait while the controller sends the OUT token and a zero-length DATA1 packet.
3. At the end of the attempt to send the data, the controller will generate an Endpoint 0 interrupt. The
software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit
(bit 4) or the NAK_TIMEOUT bit (bit 7) has been set.
If RXSTALL bit is set, it indicates that the target could not complete the command and so has issued a
STALL response.
If ERROR bit is set, it means that the controller has tried to send the STATUS Packet and the following
data packet three times without getting any response.
If NAK_TIMEOUT bit is set, it means that the controller has received a NAK response to each attempt
to send the IN token, for longer than the time set in the HOST_NAKLIMIT0 register. The controller can
then be directed either to continue trying this transaction (until it times out again) by clearing the
NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT
bit.
4. If none of RXSTALL, ERROR or NAK_TIMEOUT bits is set, the STATUS Phase has been correctly
ACKed.
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Figure 13. Completion of IN Data Phase Flow Chart
Completion of
IN data phase
TxPktRdy
and StatusPkt
both set
?
No
Yes
OUT token sent
Zero−length
DATA1 packet sent
Command could
not be completed
RxStall set
Stall
received
?
Yes
Yes
TxPktRdy cleared
Error Count cleared
interrupt generated
No
ACK
received
?
TxPktRdy cleared
Error Count cleared
Interrupt generated
No
Transaction
complete
NAK limit
reached
?
NAK
received
?
No
Yes
Error count
cleared
No
Yes
Error count
incremented
NAK Timeout set
Endpoint halted
Interrupt generated
Implies problem
at peripheral end
of connection.
Error bit set
Error
count=3
?
No
Yes
TxPktRdy cleared
Error Count cleared
interrupt generated
Transaction deemed
complete
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3.2.2
Bulk Transactions
3.2.2.1
Host Mode: Bulk IN Transactions
A Bulk IN transaction may be used to transfer non-periodic data from the external USB peripheral to the
host.
The following optional features are available for use with an Rx endpoint used in host mode to receive the
data:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception
from the host. This allows that one packet can be received while another is being read. Double packet
buffering is enabled by setting the DPB bit of RXFIFOSZ register (bit 4).
•
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint has
a packet in its FIFO. This feature can be used to allow the DMA controller to unload packets from the
FIFO without processor intervention.
When DMA is enabled, endpoint interrupt will not be generated for completion of packet reception.
Endpoint interrupt will be generated only in the error conditions.
AutoRequest: When the AutoRequest feature is enabled, the REQPKT bit of HOST_RXCSR (bit 5) will
be automatically set when the RXPKTRDY bit is cleared.
This feature is applicable only when DMA is enabled. To enable AutoRequest feature, set the
AUTOREQ register for the DMA channel associated for the endpoint.
3.2.2.1.1 Setup
Before initiating any Bulk IN Transactions in Host mode:
•
The target function address needs to be set in the RXFUNCADDR register for the selected controller
endpoint. (RXFUNCADDR register is available for all endpoints from EP0 to EP4.)
•
The HOST_RXTYPE register for the endpoint that is to be used needs to be programmed as follows:
–
–
–
Operating speed in the SPEED bit field (bits 7 and 6).
Set 10 (binary value) in the PROT field for bulk transfer.
Endpoint Number of the target device in RENDPN field. This is the endpoint number contained in
the Rx endpoint descriptor returned by the target device during enumeration.
•
The RXMAXP register for the controller endpoint must be written with the maximum packet size (in
bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard
Endpoint Descriptor for the target endpoint.
•
•
•
The HOST_RXINTERVAL register needs to be written with the required value for the NAK limit (2 - 215
frames/microframes), or cleared to 0 if the NAK timeout feature is not required.
The relevant interrupt enable bit in the INTRRXE register should be set (if an interrupt is required for
this endpoint).
The following bits of HOST_RXCSR register should be set as shown below:
–
–
Set DMAEN (bit 13) to 1 if a DMA request is required for this endpoint.
Clear DSINYET (bit 12) to 0 to allow normal PING flow control. This will affect only High Speed
transactions.
–
Always clear DMAMODE (bit 11) to 0.
•
If DMA is enabled, the AUTOREQ register can be set for generating IN tokens automatically after
receiving the data. Set the bit field RXn_AUTOREQ (where n is the endpoint number) with binary value
01 or 11.
When the endpoint is first configured, the endpoint data toggle should be cleared to 0 either by using the
DATATOGWREN and DATATOG bits of HOST_RXCSR (bit 10 and bit 9) to toggle the current setting or
by setting the CLRDATATOG bit of HOST_RXCSR (bit 7). This will ensure that the data toggle (which is
handled automatically by the controller) starts in the correct state. Also if there are any data packets in the
FIFO (indicated by the RXPKTRDY bit (bit 0 of HOST_RXCSR) being set), they should be flushed by
setting the FLUSHFIFO bit of HOST_RXCSR (bit 4).
Note: It may be necessary to set this bit twice in succession if double buffering is enabled.
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3.2.2.1.2 Operation
When Bulk data is required from the USB peripheral device, the software should set the REQPKT bit in
the corresponding HOST_RXCSR register (bit 5). The controller will then send an IN token to the selected
peripheral endpoint and waits for data to be returned.
If data is correctly received, RXPKTRDY bit of HOST_RXCSR (bit 0) is set. If the USB peripheral device
responds with a STALL, RXSTALL bit (bit 6 of HOST_RXCSR) is set. If a NAK is received, the controller
tries again and continues to try until either the transaction is successful or the POLINTVL_NAKLIMIT set
in the HOST_RXINTERVAL register is reached. If no response at all is received, two further attempts are
made before the controller reports an error by setting the ERROR bit of HOST_RXCSR (bit 2).
The controller then generates the appropriate endpoint interrupt, whereupon the software should read the
corresponding HOST_RXCSR register to determine whether the RXPKTRDY, RXSTALL, ERROR or
DATAERR_NAKTIMEOUT bit is set and act accordingly. If the DATAERR_NAKTIMEOUT bit is set, the
controller can be directed either to continue trying this transaction (until it times out again) by clearing the
DATAERR_NAKTIMEOUT bit or to abort the transaction by clearing REQPKT bit before clearing the
DATAERR_NAKTIMEOUT bit.
The packets received should not exceed the size specified in the RXMAXP register (as this should be the
value set in the wMaxPacketSize field of the endpoint descriptor sent to the host).
In the general case, the application software will need to read each packet from the FIFO individually. If
large blocks of data are being transferred, the overhead of calling an interrupt service routine to unload
each packet can be avoided by using DMA.
3.2.2.1.3 Error Handling
If the target wants to shut down the Bulk IN pipe, it will send a STALL response to the IN token. This will
result in the RXSTALL bit of HOST_RXCSR (bit 6) being set.
3.2.2.2
Bulk OUT Transactions
A Bulk OUT transaction may be used to transfer non-periodic data from the host to the USB peripheral.
Following optional features are available for use with a Tx endpoint used in Host mode to transmit this
data:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting
transmission to the peripheral device. Double packet buffering is enabled by setting the DPB bit of
TXFIFOSZ register (bit 4).
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint is
able to accept another packet in its FIFO. This feature can be used to allow the DMA controller to load
packets into the FIFO without processor intervention.
When DMA is enabled and DMAMODE bit in HOST_TXCSR register is set, an endpoint interrupt will
not be generated for completion of packet reception. An endpoint interrupt will be generated only in the
error conditions.
3.2.2.2.1 Setup
Before initiating any bulk OUT transactions:
•
The target function address needs to be set in the TXFUNCADDR register for the selected controller
endpoint. (TXFUNCADDR register is available for all endpoints from EP0 to EP4.)
•
The HOST_TXTYPE register for the endpoint that is to be used needs to be programmed as follows:
–
–
–
Operating speed in the SPEED bit field (bits 7 and 6).
Set 10b in the PROT field for bulk transfer.
Endpoint Number of the target device in TENDPN field. This is the endpoint number contained in
the OUT(Tx) endpoint descriptor returned by the target device during enumeration.
•
The TXMAXP register for the controller endpoint must be written with the maximum packet size (in
bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard
Endpoint Descriptor for the target endpoint.
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•
•
•
The HOST_TXINTERVAL register needs to be written with the required value for the NAK limit (2 - 215
frames/microframes), or cleared to 0 if the NAK timeout feature is not required.
The relevant interrupt enable bit in the INTRTXE register should be set (if an interrupt is required for
this endpoint).
The following bits of HOST_TXCSR register should be set as shown below:
–
Set the MODE bit (bit 13) to 1 to ensure the FIFO is enabled (only necessary if the FIFO is shared
with an Rx endpoint).
–
–
–
Set the DMAEN bit (bit 12) to 1 if a DMA request is required for this endpoint.
Clear the FRCDATATOG bit (bit 11) to 0 to allow normal data toggle operations.
Set the DMAMODE bit (bit 10) to 1 when DMA is enabled and the endpoint interrupt is not needed
for each packet transmission.
When the endpoint is first configured, the endpoint data toggle should be cleared to 0 either by using the
DATATOGWREN bit and DATATOG bit of HOST_TXCSR (bit 9 and bit 8) to toggle the current setting or
by setting the CLRDATATOG bit of HOST_TXCSR (bit 6). This will ensure that the data toggle (which is
handled automatically by the controller) starts in the correct state. Also, if there are any data packets in
the FIFO (indicated by the FIFONOTEMPTY bit of HOST_TXCSR register (bit 1) being set), they should
be flushed by setting the FLUSHFIFO bit (bit 3 of HOST_TXCSR).
Note: It may be necessary to set this bit twice in succession if double buffering is enabled.
3.2.2.2.2 Operation
When Bulk data is required to be sent to the USB peripheral device, the software should write the first
packet of the data to the FIFO (or two packets if double-buffered) and set the TXPKTRDY bit in the
corresponding HOST_TXCSR register (bit 0). The controller will then send an OUT token to the selected
peripheral endpoint, followed by the first data packet from the FIFO.
If data is correctly received by the peripheral device, an ACK should be received whereupon the controller
will clear TXPKTRDY bit of HOST_TXCSR (bit 0). If the USB peripheral device responds with a STALL,
the RXSTALL bit (bit 5) of HOST_TXCSR is set. If a NAK is received, the controller tries again and
continues to try until either the transaction is successful or the NAK limit set in the HOST_TXINTERVAL
register is reached. If no response at all is received, two further attempts are made before the controller
reports an error by setting ERROR bit in HOST_TXCSR (bit 2).
The controller then generates the appropriate endpoint interrupt, whereupon the software should read the
corresponding HOST_TXCSR register to determine whether the RXSTALL (bit 5), ERROR (bit 2) or
NAK_TIMEOUT (bit 7) bit is set and act accordingly. If the NAK_TIMEOUT bit is set, the controller can be
directed either to continue trying this transaction (until it times out again) by clearing the NAK_TIMEOUT
bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT bit.
If large blocks of data are being transferred, then the overhead of calling an interrupt service routine to
load each packet can be avoided by using DMA.
3.2.2.2.3 Error Handling
If the target wants to shut down the Bulk OUT pipe, it will send a STALL response. This is indicated by the
RXSTALL bit of HOST_TXCSR register (bit 5) being set.
3.2.3
Host Mode: Interrupt Transactions
When the controller is operating as the host, interactions with an Interrupt endpoint on the USB peripheral
device are handled in very much the same way as the equivalent Bulk transactions (described in previous
sections).
The principal difference as far as operational steps are concerned is that PROT field of HOST_RXTYPE
and HOST_TXTYPE (bits 5:4) need to be set (binary value) to represent an Interrupt transaction.
The required polling interval also needs to be set in the HOST_RXINTERVAL and HOST_TXINTERVAL
registers.
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3.2.4
Isochronous Transactions
3.2.4.1
Host Mode: Isochronous IN Transactions
An Isochronous IN transaction is used to transfer periodic data from the USB peripheral to the host.
The following optional features are available for use with an Rx endpoint used in Host mode to receive this
data:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception
from the host. This allows that one packet can be received while another is being read. Double packet
buffering is enabled by setting the DPB bit of RXFIFOSZ register (bit 4).
•
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint has
a packet in its FIFO. This feature can be used to allow the DMA controller to unload packets from the
FIFO without processor intervention. However, this feature is not particularly useful with isochronous
endpoints because the packets transferred are often not maximum packet size.
When DMA is enabled, endpoint interrupt will not be generated for completion of packet reception.
Endpoint interrupt will be generated only in the error conditions.
AutoRequest: When the AutoRequest feature is enabled, the REQPKT bit of HOST_RXCSR (bit 5) will
be automatically set when the RXPKTRDY bit is cleared.
This feature is applicable only when DMA is enabled. To enable AutoRequest feature, set the
AUTOREQ register for the DMA channel associated for the endpoint.
3.2.4.1.1 Setup
Before initiating an Isochronous IN Transactions in Host mode:
•
The target function address needs to be set in the RXFUNCADDR register for the selected controller
endpoint (RXFUNCADDR register is available for all endpoints from EP0 to EP4).
•
The HOST_RXTYPE register for the endpoint that is to be used needs to be programmed as follows:
–
–
–
Operating speed in the SPEED bit field (bits 7 and 6).
Set 01 (binary value) in the PROT field for isochronous transfer.
Endpoint Number of the target device in RENDPN field. This is the endpoint number contained in
the Rx endpoint descriptor returned by the target device during enumeration.
•
The RXMAXP register for the controller endpoint must be written with the maximum packet size (in
bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard
Endpoint Descriptor for the target endpoint.
•
•
•
The HOST_RXINTERVAL register needs to be written with the required transaction interval (usually
one transaction per frame/microframe).
The relevant interrupt enable bit in the INTRRXE register should be set (if an interrupt is required for
this endpoint).
The following bits of HOST_RXCSR register should be set as shown below:
–
–
Set the DMAEN bit ( bit 13) to 1 if a DMA request is required for this endpoint.
Clear the DISNYET it (bit 12) to 0 to allow normal PING flow control. This will only affect High
Speed transactions.
–
Always clear the DMAMODE bit (bit 11) to 0.
•
If DMA is enabled, AUTOREQ register can be set for generating IN tokens automatically after receiving
the data. Set the bit field RXn_AUTOREQ (where n is the endpoint number) with binary value 01 or 11.
3.2.4.1.2 Operation
The operation starts with the software setting REQPKT bit of HOST_RXCSR (bit 5). This causes the
controller to send an IN token to the target.
When a packet is received, an interrupt is generated which the software may use to unload the packet
from the FIFO and clear the RXPKTRDY bit in the HOST_RXCSR register (bit 0) in the same way as for a
Bulk Rx endpoint. As the interrupt could occur almost any time within a frame(/microframe), the timing of
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FIFO unload requests will probably be irregular. If the data sink for the endpoint is going to some external
hardware, it may be better to minimize the requirement for additional buffering by waiting until the end of
each frame before unloading the FIFO. This can be done by using the SOF_PULSE signal from the
controller to trigger the unloading of the data packet. The SOF_PULSE is generated once per
frame(/microframe). The interrupts may still be used to clear the RXPKTRDY bit in HOST_RXCSR.
3.2.4.1.3 Error Handling
If a CRC or bit-stuff error occurs during the reception of a packet, the packet will still be stored in the FIFO
but the DATAERR_NAKTIMEOUT bit of HOST_RXCSR (bit 3) is set to indicate that the data may be
corrupt.
3.2.4.2
Host Mode: Isochronous Out Transactions
An Isochronous OUT transaction may be used to transfer periodic data from the host to the USB
peripheral.
Following optional features are available for use with a Tx endpoint used in Host mode to transmit this
data:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting
transmission to the peripheral device. Double packet buffering is enabled by setting the DPB bit of
TXFIFOSZ register (bit 4).
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint is
able to accept another packet in its FIFO. This feature can be used to allow the DMA controller to load
packets into the FIFO without processor intervention.
However, this feature is not particularly useful with isochronous endpoints because the packets
transferred are often not maximum packet size.
When DMA is enabled and DMAMODE bit in HOST_TXCSR register is set, endpoint interrupt will not
be generated for completion of packet reception. Endpoint interrupt will be generated only in the error
conditions.
3.2.4.2.1 Setup
Before initiating any Isochronous OUT transactions:
•
The target function address needs to be set in the TXFUNCADDR register for the selected controller
endpoint (TXFUNCADDR register is available for all endpoints from EP0 to EP4).
•
The HOST_TXTYPE register for the endpoint that is to be used needs to be programmed as follows:
–
–
–
Operating speed in the SPEED bit field (bits 7 and 6).
Set 01 (binary value) in the PROT field for isochronous transfer.
Endpoint Number of the target device in TENDPN field. This is the endpoint number contained in
the OUT(Tx) endpoint descriptor returned by the target device during enumeration.
•
The TXMAXP register for the controller endpoint must be written with the maximum packet size (in
bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard
Endpoint Descriptor for the target endpoint.
•
•
•
The HOST_TXINTERVAL register needs to be written with the required transaction interval (usually
one transaction per frame/microframe).
The relevant interrupt enable bit in the INTRTXE register should be set (if an interrupt is required for
this endpoint).
The following bits of HOST_TXCSR register should be set as shown below:
–
Set the MODE bit (bit 13) to 1 to ensure the FIFO is enabled (only necessary if the FIFO is shared
with an Rx endpoint).
–
–
–
Set the DMAEN bit ( bit 12) to 1 if a DMA request is required for this endpoint.
The FRCDATATOG bit (bit 12) is ignored for isochronous transactions.
Set the DMAMODE bit (bit 10) to 1 when DMA is enabled and the endpoint interrupt is not needed
for each packet transmission.
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3.2.4.2.2 Operation
The operation starts when the software writes to the FIFO and sets TXPKTRDY bit of HOST_TXCSR
(bit 0). This triggers the controller to send an OUT token followed by the first data packet from the FIFO.
An interrupt is generated whenever a packet is sent and the software may use this interrupt to load the
next packet into the FIFO and set the TXPKTRDY bit in the HOST_TXCSR register (bit 0) in the same
way as for a Bulk Tx endpoint. As the interrupt could occur almost any time within a frame, depending on
when the host has scheduled the transaction, this may result in irregular timing of FIFO load requests. If
the data source for the endpoint is coming from some external hardware, it may be more convenient to
wait until the end of each frame before loading the FIFO as this will minimize the requirement for
additional buffering. This can be done by using the SOF_PULSE signal from the controller to trigger the
loading of the next data packet. The SOF_PULSE is generated once per frame(/microframe). The
interrupts may still be used to set the TXPKTRDY bit in HOST_TXCSR.
3.3 DMA Operation
The DMA controller sub-module is a common 4 dual-channel DMA controller. It supports 4 TX and 4 RX
channels, and each channel attaches to the associated endpoint in the controller. Channel 0 maps to
Endpoint 1 up to Channel 3 mapping to Endpoint 4, while endpoint 0 cannot utilize the DMA. The DMA is
programmed through parameters stored in the DMA registers, and implements DMAs through the buffer
descriptor chains stored in main memory. The DMA utilizes incrementing addressing mode, and can burst
up to 64 bytes. When a DMA is initiated, the DMA controller reads the current parameters for that channel
from the DMA registers, reads the CPPI buffer descriptor pointed to by the parameters, and performs the
DMA using the data buffer in the descriptor. The DMA controller updates and saves the DMA parameters
when the data is completed. The software can access the current parameters at any time by accessing
the DMA registers.
The DMA controller has a concept of DMA packets which is different from the USB packets. A DMA
packet can be (but not necessarily) of the same size as USB packet. Each DMA packet can comprise of
one or multiple data buffers. Each DMA channel can process one or multiple chains of these DMA
packets.
The controller supports two modes of DMA: transparent mode and RNDIS mode. Transparent mode will
interrupt the CPU for every USB data packet, while RNDIS mode can service multiple USB packets with
only a single CPU interrupt.
3.3.1
DMA Transmit Operation
For transmit operation, the software has to program the DMA channel with a chain of transmit buffers.
3.3.1.1
Transmit Buffer
A Transmit buffer is a contiguous block of memory used to store data for transmission. Each Tx buffer has
a corresponding Tx buffer descriptor. Each Tx buffer can be linked together with other Tx buffers to make
a DMA packet or a queue of DMA packets.
Transmit buffers are byte aligned structures located in processor’s main memory. Tx buffer size may vary
from 1 to 65,535 bytes.
3.3.1.2
CPPI Transmit Buffer Descriptor
Tx buffer descriptors provide information about a single corresponding Tx data buffer. Every Tx buffer has
a single Tx buffer descriptor that stores the following information:
•
Pointer to the data buffer
•
•
•
•
•
Pointer to the next buffer descriptor in the queue
Buffer length and offset to the first valid byte of buffer data
Start of DMA packet (SOP) indicator
End of DMA packet (EOP) indicator
Ownership (only valid with SOP)
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•
•
End of queue (EOQ) (only valid on EOP)
Packet Length (only valid with SOP)
Transmit buffer descriptors contain 16 bytes (4 words) and must begin on 16-byte aligned addresses.
Transmit buffer descriptors may be linked together to form packets. Buffer descriptor SOP and EOP bits
are used to delimit packets. Packets in turn may be linked together to form transmit queue. Each queue
consists of a chain of buffer descriptors linked together by Next Descriptor Pointers. The last buffer
descriptor in a queue has a zero Next Descriptor Pointer. Each descriptor points to a data buffer yielding a
queue of buffers.
Four Words of Transmit Buffer Descriptor are described below.
Table 6. Transmit Buffer Descriptor Word 0
Bits
Name
Description
31:0
Next Descriptor
Pointer
The 32-bit word aligned memory address of the next buffer descriptor in the Tx queue. This is the
mechanism used to reference the next buffer descriptor from the current buffer descriptor. If the
value of this pointer is zero then the current buffer is the last buffer in the queue. The software sets
the Next Descriptor Pointer.
Table 7. Transmit Buffer Descriptor Word 1
Bits
Name
Description
31:0
Buffer Pointer
The Buffer Pointer is the byte aligned memory address of the buffer associated with the buffer
descriptor. The software sets the Buffer Pointer.
Table 8. Transmit Buffer Descriptor Word 2
Bits
Name
Description
31:16
Buffer Offset
The Buffer Offset indicates how many unused bytes are at the start of the buffer (SOP buffers only).
A value of zero indicates that there are no unused bytes at the start of the buffer and that valid data
begins on the first byte of the buffer. A value of 000Fh (decimal 15) indicates that the first 15 bytes
of the buffer are to be ignored by the DMA controller while transmitting and that valid buffer data
starts on byte 16 of the buffer. The Buffer Offset is valid only on Start Of Packet buffer descriptors
and must be zero otherwise. The software sets the Buffer Offset. The Buffer Offset must be less
than the Buffer Length.
15:0
Buffer Length
The Buffer Length field indicates how many valid data bytes are in the buffer. Unused or protocol
specific bytes at the beginning of the buffer are not counted in the Buffer Length field. The software
sets the Buffer Length.
Table 9. Transmit Buffer Descriptor Word 3
Bits
Name
Value Description
31
SOP
Start of Packet: SOP Indicates that the descriptor buffer is the first buffer in the packet. The
software sets the SOP bit.
0
1
Not start of packet buffer
Start of packet buffer
30
29
EOP
End of Packet: EOP Indicates that the descriptor buffer is the last buffer in the packet. The
software sets the EOP bit. It is valid to set both SOP and EOP in the same descriptor.
0
1
Not end of packet buffer
End of packet buffer
Ownership
The Ownership bit indicates ownership of the DMA packet and is valid only on SOP. This bit
is set by the software and cleared by the DMA controller when the packet has been
transmitted. The software can use this bit to reclaim buffers.
0
1
The packet is owned by the host processor
The packet is owned by the DMA controller
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Table 9. Transmit Buffer Descriptor Word 3 (continued)
Bits
Name
Value Description
28
EOQ
End of Queue: The End of Queue bit is set by the DMA controller to indicate that all packets
in the queue have been transmitted and the Tx queue is empty. This bit is valid only on when
EOP is set.
0
1
The Tx queue has more packets to transfer
The DMA controller took this descriptor buffer as the last buffer descriptor in the last packet in
the queue
27:24
23
Reserved
Zero Byte
Reserved
Zero Byte Packet Identifier. This bit is set by the software when a zero byte USB packet
needs to be transmitted. This bit tells the DMA controller that no data transfer needs to be
done for transmitting this zero byte data buffer. Set the Packet Length to 1 when setting this
bit.
22:16
15:0
Reserved
Reserved
Packet Length
The length of the DMA packet in bytes. This field is valid only on SOP and is written by the
software. If the Packet Length is less than the sum of the buffer lengths, then the packet data
will be truncated. A Packet Length greater than the sum of the buffers is a software error.
Packet Length must be nonzero. Set to one when setting the Zero Byte bit.
Four different cases are possible for the number of buffers in a DMA packet:
1. Buffer Descriptor contains Start of Packet field and End of Packet field (1 buffer in DMA packet).
2. Buffer Descriptor contains Start of Packet field only (2+ buffers in DMA packet).
3. Buffer Descriptor contains End of Packet field only (2+ buffers in DMA packet).
4. Buffer Descriptor does not contain either of Start of Packet field and End of Packet field (3+ buffers in
packet).
3.3.1.3
Transmit DMA State
The DMA controller stores and maintains state information for each transmit channel. The state
information is referred to as the Tx DMA State. The Tx DMA State is a combination of control fields and
DMA controller specific scratchpad space used to manipulate data structures and transmit DMA packets.
The Tx DMA State is stored in registers TCPPIDMASTATEW0, TCPPIDMASTATEW1,
TCPPIDMASTATEW2, TCPPIDMASTATEW3, TCPPIDMASTATEW4, TCPPIDMASTATEW5 and
TCPPICOMPPTR for each channel.
Each channel has one queue. The queue has one head descriptor pointer and one completion pointer.
The following information is stored in the Tx DMA State:
•
TCPPIDMASTATEW0: Tx Queue Head Descriptor Pointer(s)
TCPPICOMPPTR: Tx Completion Pointer(s)
TCPPIDMASTATEW1: Start of Packet Buffer Descriptor Pointer
TCPPIDMASTATEW2: Current Buffer Descriptor Pointer
TCPPIDMASTATEW3: Current Buffer Pointer
•
•
•
•
•
TCPPIDMASTATEW5: Remaining DMA Packet Length and Actual DMA Packet Length
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3.3.1.4
Transmit Queue
Figure 14 shows a Tx queue. Tx queue provide a logical queue of DMA packets for transmission through
a channel. Each channel has one dedicated Tx queues. The queue has one associated Tx Queue Head
Descriptor Pointer and one associated Tx Completion Pointer container in the channel Tx DMA state. The
Tx queue is linked lists of Tx buffer descriptors that constitute one or more packets queued for
transmission. Packets are added to the tail of the list by the software and packets are freed from the head
of the list by the DMA controller as each packet transmission is completed.
Figure 14. Tx Queue Flow Chart
SOP descriptor
Descriptor
Buffer
Buffer
Buffer
EOP descriptor
Tx queue head descriptor pointer
3.3.1.5
Operation
•
After reset the software must write zeroes to all Tx DMA State registers (TCPPIDMASTATEW0,
TCPPIDMASTATEW1, TCPPIDMASTATEW2, TCPPIDMASTATEW3, TCPPIDMASTATEW4,
TCPPIDMASTATEW5).
•
•
•
•
•
The software constructs transmit queues in memory (one or more DMA packets for transmission)
Enable DMA for the endpoint in the PERI_TXCSR or HOST_TXCSR by setting the DMAEN bit.
Enable the DMA ports by setting TCPPI_ENABLE bit of TCPPICR register.
Write the head of the queue descriptor pointer to the TCPPIDMASTATEW0 register to start the DMA.
The USB controller will start transmitting data. Interrupt associated with the DMA channel is asserted,
after each DMA packet is transmitted.
For each buffer added to a transmit queue, the software must initialize the Tx buffer descriptor values as
follows:
•
Write the Next Descriptor Pointer with the 32-bit aligned address of the next descriptor in the queue
(zero if last descriptor)
•
•
•
•
•
Write the Buffer Pointer with the byte aligned address of the buffer data
Write the Buffer Length with the number of bytes in the buffer
Write the Buffer Offset with the number of bytes in the offset to the data (nonzero with SOP only)
Set the SOP, EOP, and Ownership bits as appropriate
Clear the End Of Queue bit
The DMA controller begins Tx DMA packet transmission on a given channel when the host writes the
channel’s Tx queue head descriptor pointer with the address of the first buffer descriptor in the queue
(nonzero value). Each channel has one queue and a head descriptor pointer. The first buffer descriptor for
each Tx DMA packet must have the Start of Packet (SOP) bit and the Ownership bit set to one by the
software. The last buffer descriptor for each Tx DMA packet must have the End of Packet (EOP) bit set to
one by the software. The DMA controller will transmit DMA packets until all queued packets have been
transmitted and the queue is empty. When each packet transmission is complete, the DMA controller will
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clear the Ownership bit in the DMA packet’s SOP buffer descriptor and issue an interrupt to the processor
by writing the DMA packet’s last buffer descriptor address to the queue’s Tx DMA State Completion
Pointer (TCPPICOMPPTR register). When the last packet in a queue has been transmitted, the DMA
controller sets the End Of Queue bit in the EOP buffer descriptor, clears the Ownership bit in the SOP
Descriptor, zeroes the appropriate DMA state head descriptor pointer, and then issues a Tx interrupt to
the host by writing address of the last buffer descriptor processed by the DMA controller to the queue’s
associated Tx completion pointer (TCPPICOMPPTR register).
On interrupt from the port, the software can process the buffer queue, detecting transmitted packets by the
status of the Ownership bit in the SOP buffer descriptor. If the Ownership bit is cleared to zero, then the
packet has been transmitted and the software may reclaim the buffers associated with the packet. The
software continues queue processing until the end of the queue or until a SOP buffer descriptor is read
that contains a set Ownership bit indicating that the packet transmission is not complete. The software
determines that all packets in the queue have been transmitted when the last packet in the queue has a
cleared Ownership bit in the SOP buffer descriptor, the End of Queue bit is set in the last packet EOP
buffer descriptor, and the Next Descriptor Pointer of the last packet EOP buffer descriptor is zero.
The software acknowledges an interrupt by writing the address of the last buffer descriptor to the queue’s
associated Tx Completion Pointer (TCPPICOMPPTR register).
If the software written buffer address value in TCCPICOMPPTR register is different from the buffer
address written by the DMA controller after Tx completion, then the interrupt for the Tx Channel remains
asserted. If the software-written buffer address value matches with the buffer address written by the DMA
controller, the Tx Channel interrupt gets deasserted.
A misqueued packet condition may occur when the software adds a packet to a queue for transmission as
the DMA controller finishes transmitting the previous last packet in the queue. The misqueued packet is
detected by the software when queue processing detects a cleared Ownership bit in the SOP buffer
descriptor, a set End of Queue bit in the EOP buffer descriptor, and a nonzero Next Descriptor Pointer in
the EOP buffer descriptor. A misqueued packet means that the DMA controller read the last EOP buffer
descriptor before the host added the new last packet to the queue, so the DMA controller determined
queue empty just before the last packet was added. The host software corrects the misqueued packet
condition by initiating a new packet transfer for the misqueued packet by writing the misqueued packet’s
SOP buffer descriptor address to the head descriptor pointer in TCCPIDMASTATEW0 register.
3.3.1.6
Transparent Mode and RNDIS Mode Transmit DMA Operation
Transparent Mode DMA operation is the default DMA mode (as described in previous section) where an
interrupt is generated whenever a DMA packet is transmitted. In the transparent mode, DMA packet size
cannot be greater than USB MaxPktSize and FIFO size for the endpoint. This means, for transmitting say
‘n’ USB packets, the DMA controller should be programmed with a queue of ‘n’ DMA packets. Transparent
mode must be used whenever USB MaxPktSize for the endpoint is not a multiple of 64 bytes.
RNDIS mode DMA is used to transmit DMA packets which are larger than USB MaxPktSize. This is
accomplished by breaking the larger packet into smaller packets, not larger than USB MaxPktSize. This
implies that the data to be transmitted will be sent over USB in multiple packets of MaxPktSize and the Tx
DMA interrupt for the channel is generated after the transmission of complete DMA packet. This mode of
DMA is used for RNDIS type transfers over USB. The protocol defines the end of the complete transfer by
sending a short USB packet (smaller than USB MaxPktSize as mentioned in USB specification 2.0). If the
DMA packet size is an exact multiple of USB MaxPktSize, the DMA controller sends a zero byte packet at
the end of complete transfer to signify the completion of the transfer.
RNDIS Mode DMA is supported only when USB MaxPktSize and the associated FIFO size is an integral
multiple of 64 bytes.
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RNDIS Mode Setup
The setup of RNDIS mode DMA is similar to the default Transparent Mode as mentioned in the previous
section. The following steps need to be taken for setting up RNDIS mode Tx DMA:
•
After reset the software must write zeroes to all Tx DMA State registers (TCPPIDMASTATEW0,
TCPPIDMASTATEW1,
TCPPIDMASTATEW5).
TCPPIDMASTATEW2,
TCPPIDMASTATEW3,
TCPPIDMASTATEW4,
•
•
•
•
The software constructs transmit queue in memory (one or more DMA Packets in for transmission).
Enable DMA for the endpoint in the PERI_TXCSR or HOST_TXCSR by setting the DMAEN bit.
Enable the DMA ports by setting TCPPI_ENABLE bit of TCPPICR register.
Set RNDIS bit of CTRLR register for enabling RNDIS mode for all channels or set TXnEN bit of
RNDISR register for specific DMA channel n.
•
•
•
Write the head of the queue descriptor pointer to the TCPPIDMASTATEW0 register to start the DMA.
The USB controller will start transmitting data.
If the DMA packet size is exact multiple of USB MaxPktSize, a zero byte packet is transmitted and
interrupt associated with the DMA channel is asserted.
•
If the DMA packet size is not exact multiple of USB MaxPktSize, the last USB packet transmitted is a
short packet and interrupt associated with the DMA channel is asserted.
Transparent Mode Setup
Transparent DMA configuration is identical to RNDIS DMA configuration with the exception of the
followings: Each packet is defined by a single buffer descriptor with SOP and EOP bit fields set. Packet
size is not bounded to be a multiple of 64 byte but by max packet size. CTRLR.RNDIS bit field should be
cleared to zero.
3.3.1.7
DMA Channel TearDown
The DMA also supports a teardown operation on TX channels. Teardown allows software to terminate the
current Tx queue by notifying the DMA. The DMA will stop the current Tx DMA for that channel, and
update the channel parameters to remove all Tx descriptors from that queue. Then the software is free to
reclaim the buffers without worry of interrupting the DMA in progress.
Teardown of Tx channels is done using the TCPPITDR register. If the READY bit of TCPPITDR register is
set, it signifies that the Tx channel can be torn down. The channel number should be written in the
CHANNEL field of TCPPITDR register to teardown the channel.
Note that the software must also teardown the core after the DMA. Software should specify that the
following steps are all completed before assuming teardown has completed successfully.
1. After tearing down the channel, DMA interrupt should be generated and the TCPPICOMPPTR register
will be FFFF FFFCh. This indicates that the DMA has completed the teardown and all the data buffers
can be reclaimed.
2. The software must set the FLUSHFIFO bit of the PERI_TXCSR or HOST_TXCSR register for the
endpoint to be torn down.
After both the DMA and the core are torn down, the DMA channel and endpoint can be restarted cleanly.
A failure to perform either of these steps could result in data loss or spurious data upon restart.
3.3.2
DMA Receive Operation
For receive operation, the software has to program the DMA channel with a chain of receive buffers.
3.3.2.1
Receive Buffer
A receive buffer is a contiguous block of memory used to store received data. Each Rx buffer has a
corresponding Rx buffer descriptor. Each Rx buffer can be linked together with other Rx buffers to make a
DMA packet or a queue of DMA packets.
Receive buffers are byte aligned structures located in processor’s main memory. Rx buffer size may vary
from 1 to 65,535 bytes.
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3.3.2.2
CPPI Receive Buffer Descriptor
Rx buffer descriptors provide information about a single corresponding Rx data buffer. Every Rx buffer has
a single Rx buffer descriptor that stores the following information:
•
•
•
•
•
•
•
•
Pointer to the data buffer
Pointer to the next buffer descriptor in the queue
Buffer length and offset to the first valid byte of buffer data
Start of DMA packet (SOP) indicator
End of DMA packet (EOP) indicator
Ownership (only valid with SOP)
End of queue (EOQ) (only valid on EOP)
Packet Length (only valid with SOP)
Receive buffer descriptors contain 16 bytes (4 words) and must begin on 16-byte aligned addresses.
Receive buffer descriptors may be linked together to form packets. Buffer descriptor SOP and EOP bits
are used to delimit packets. Packets in turn may be linked together to form receive queue. Each queue
consists of a chain of buffer descriptors linked together by Next Descriptor Pointers. The last buffer
descriptor in a queue has a zero Next Descriptor Pointer. Each descriptor points to a data buffer yielding a
queue of buffers.
Table 10. Receive Buffer Descriptor Word 0
Bits
Name
Description
31:0
Next Descriptor
Pointer
The 32-bit word aligned memory address of the next buffer descriptor in the Rx queue. This is the
mechanism used to reference the next buffer descriptor from the current buffer descriptor. If the
value of this pointer is zero then the current buffer is the last buffer in the queue. The software sets
the Next Descriptor Pointer.
Table 11. Receive Buffer Descriptor Word 1
Bits
Name
Description
31:0
Buffer Pointer
The Buffer Pointer is the byte aligned memory address of the buffer associated with the buffer
descriptor. The software sets the Buffer Pointer.
Table 12. Receive Buffer Descriptor Word 2
Bits
Name
Description
31:16
Buffer Offset
The Buffer Offset indicates how many unused bytes are at the start of the buffer (SOP buffers only).
A value of zero indicates that there are no unused bytes at the start of the buffer and that valid data
begins on the first byte of the buffer. A value of 000Fh (decimal 15) indicates that the first 15 bytes
of the buffer are to be ignored by the DMA controller while transmitting and that valid buffer data
starts on byte 16 of the buffer. The software sets the buffer offset to zero on buffer initialization and
the DMA controller overwrites the zero value on SOP packets with the Rx DMA State buffer offset
value.
15:0
Buffer Length
The Buffer Length field indicates how many valid data bytes are in the buffer. Unused or protocol
specific bytes at the beginning of the buffer are not counted in the Buffer Length field. The software
sets the buffer length on buffer initialization. The DMA controller will overwrite the software initialized
value on an EOP buffer when the number of received data bytes is less than the host initiated value.
The DMA controller will overwrite the host initialized value on SOP when the Buffer Offset is greater
than zero, or the Packet Length is less than the buffer length.
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Table 13. Receive Buffer Descriptor Word 3
Bit
Field
Value Description
31
SOP
Start of Packet: SOP Indicates that the descriptor buffer is the first buffer in the packet. Software
should clear the SOP bit when setting up the descriptor.
0
1
Not start of packet buffer
Start of packet buffer
30
29
EOP
End of Packet: EOP Indicates that the descriptor buffer is the last buffer in the packet. Software
should clear the EOP bit when setting up the descriptor.
0
1
Not end of packet buffer
End of packet buffer
Ownership
The Ownership bit indicates ownership of the DMA packet and is valid only on SOP. This bit is
set by the software and cleared by the DMA controller when the packet has been transmitted.
The software can use this bit to reclaim buffers.
0
1
The packet is owned by the host processor.
The packet is owned by the DMA controller.
28
EOQ
End of Queue: The End of Queue bit is set by the DMA controller to indicate that all packets in
the queue have been transmitted and the Tx queue is empty. This bit is valid only on when EOP
is set. Software should clear this bit when setting up the descriptor.
0
1
The Tx queue has more packets to transfer.
The DMA controller took this descriptor buffer as the last buffer descriptor in the last packet in
the queue.
27:24 Reserved
23 Zero Byte
Reserved
Zero Byte Packet Identifier. This bit is set by the DMA controller when a zero byte USB packet
has been received. Software should ignore the Packet Length when this bit is set.
22:16 Reserved
Reserved
15:0 Packet Length
The length of the DMA packet in bytes. This field is valid only on SOP and is written by the DMA
controller. If the Packet Length is less than the sum of the buffer lengths, then the packet data
will be truncated. Software should ignore the Packet Length when Zero Byte is set.
Four different cases are possible for the number of buffers in a DMA packet:
1. Buffer Descriptor contains Start of Packet field and End of Packet field (1 buffer in DMA packet)
2. Buffer Descriptor contains Start of Packet field only (2+ buffers in DMA packet)
3. Buffer Descriptor contains End of Packet field only (2+ buffers in DMA packet)
4. Buffer Descriptor does not contain either of Start of Packet field and End of Packet field (3+ buffers in
packet)
3.3.2.3
Receive DMA State
The DMA controller stores and maintains state information for each receive channel. The state information
is referred to as the Rx DMA State. The Rx DMA State is a combination of control fields and DMA
controller specific scratchpad space used to manipulate data structures and receive DMA packets. The Rx
DMA State is stored in registers RCPPIDMASTATEW0, RCPPIDMASTATEW1, RCPPIDMASTATEW2,
RCPPIDMASTATEW3, RCPPIDMASTATEW4, RCPPIDMASTATEW5, RCPPIDMASTATEW6 and
RCPPICOMPPTR for each channel.
Each channel has one receive queue that has a head descriptor pointer and one completion pointer.
The following information is stored in the Tx DMA State:
•
RCPPIDMASTATEW0: Rx Queue Head Descriptor Pointer
RCPPICOMPPTR: Rx Completion Pointer
RCPPIDMASTATEW2: Start of Packet Buffer Descriptor Pointer
RCPPIDMASTATEW3: Current Buffer Descriptor Pointer
RCPPIDMASTATEW4: Current Buffer Pointer
•
•
•
•
•
RCPPIDMASTATEW5: Remaining DMA Packet Length and Actual DMA Packet Length
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3.3.2.4
Receive Queue
packets to be received from DMA controller channel. Each channel has single Rx queue. There are no
multiple queue as in transmit channels. Each queue has one associated Rx Queue Head Descriptor
Pointer and one associated Rx Completion Pointer contained in the channel Rx DMA State. The Rx queue
are linked lists of Rx buffer descriptors that constitute processor memory space for one or more packets to
be received. Packet space is added to the tail of the list by the software and received packets are freed
from the list by the DMA controller as each packet is received.
Figure 15. Rx Queue Flow Chart
SOP descriptor
Descriptor
Buffer
Buffer
Buffer
Buffer
Buffer
Descriptor
Descriptor
EOP descriptor
Rx queue head descriptor pointer
3.3.2.5
Operation
•
After reset the software must write zeroes to all Rx DMA State registers (RCPPIDMASTATEW0,
RCPPIDMASTATEW1, RCPPIDMASTATEW2, RCPPIDMASTATEW3, RCPPIDMASTATEW4,
RCPPIDMASTATEW5 and RCPPIDMASTATEW6).
•
•
•
•
The software constructs receive queue in memory.
Enable DMA for the endpoint in the PERI_RXCSR or HOST_RXCSR by setting the DMAEN bit.
Enable the DMA ports by setting RCPPI_ENABLE bit of RCPPICR register.
Set the value in RBUFCNTn register (where n is the channel number) for the number of buffers
available in the Rx queue. The hardware requires at least 3 available buffers to start the DMA. A new
transfer will not be started if the buffer count is below 3. The value in RBUFCNTn decrements as DMA
controller consumes the buffers for reception.
•
•
Write the head of the queue descriptor pointer to the RCPPIDMASTATEW1 register to start the DMA.
The USB controller will send IN token and wait for the data on the bus. Once data is received, DMA
controller will transfer the data in the Rx queue from the endpoint FIFO. Once a complete DMA packet
is received, interrupt associated with the DMA channel is asserted.
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The software enables packet reception on a given channel by writing the address of the first buffer
descriptor in the queue (nonzero value) to the channel’s head descriptor pointer (RCCPIDMASTATEW1)
in the channel’s Rx DMA state. When packet reception begins on a given channel, the DMA controller fills
each Rx buffer with data in order starting with the first buffer and proceeding through the Rx queue. If the
Buffer Offset in the Rx DMA State is nonzero, then the controller will begin writing data after the offset
number of bytes in the SOP buffer. The DMA controller performs the following operations at the end of
each packet reception:
•
Overwrite the buffer length in the packet’s EOP buffer descriptor with the number of bytes actually
received in the packet’s last buffer. The software initialized value is the buffer size. The overwritten
value will be less than or equal to the software initialized value.
•
•
Set the EOP bit in the packet’s EOP buffer descriptor.
Set the EOQ bit in the packet’s EOP buffer descriptor if the current packet is the last packet in the
queue.
•
•
Overwrite the packet’s SOP buffer descriptor Buffer Offset with the Rx DMA state value (the software
initialized the buffer descriptor Buffer Offset value to zero). All non SOP buffer descriptors must have a
zero Buffer Offset initialized by the host.
Overwrite the packet’s SOP buffer descriptor buffer length with the number of valid data bytes in the
buffer. If the buffer is filled up, the buffer length will be the buffer size minus buffer offset.
•
•
•
•
Set the SOP bit in the packet’s SOP buffer descriptor.
Write the SOP buffer descriptor Packet Length field.
Clear the Ownership bit in the packet’s SOP buffer descriptor.
Issue an Rx DMA interrupt to the host processor by writing the address of the packet’s last buffer
descriptor to the queue’s Rx DMA State Completion Pointer (RCPPICOMPPTR register).
On interrupt the software processes the Rx buffer queue detecting received packets by the status of
the Ownership bit in each packet’s SOP buffer descriptor. If the Ownership bit is cleared then the
packet has been completely received and is available to be processed by the software. The software
may continue Rx queue processing until the end of the queue or until a buffer descriptor is read that
contains a set Ownership bit indicating that the next packet’s reception is not complete. The software
determines that the Rx queue is empty when the last packet in the queue has a cleared Ownership bit
in the SOP buffer descriptor, a set End of Queue bit in the EOP buffer descriptor, and the Next
Descriptor Pointer in the EOP buffer descriptor is zero.
The software acknowledges an interrupt by writing the address of the last buffer descriptor to the
queue’s associated Rx Completion Pointer (RCPPICOMPPTR register).
If the software written buffer address value in RCCPICOMPPTR register is different from the buffer
address written by the DMA controller after Rx completion, then the interrupt for the Rx Channel
remains asserted. If the software written buffer address value matches with the buffer address written
by the DMA controller, the Rx Channel interrupt gets deasserted.
A misqueued buffer may occur when the software adds buffers to a queue as the DMA controller
finishes the reception of the previous last packet in the queue. The misqueued buffer is detected by the
software when queue processing detects a cleared Ownership bit in the SOP buffer descriptor, a set
End of Queue bit in the EOP buffer descriptor, and a nonzero Next Descriptor Pointer in the EOP
buffer descriptor. A misqueued buffer means that the DMA controller read the last EOP buffer
descriptor before the software added buffer descriptor(s) to the queue, so the DMA controller
determined queue empty just before the software added more buffer descriptor(s). Receive overrun
condition may occur in the misqueued buffer case. If a new packet reception is begun during the time
that the DMA controller has determined the end of queue condition, then the received packet will
overrun (start of packet overrun). If the misqueued buffer occurs during the middle of a packet
reception then middle of packet overrun may occur. If the misqueued buffer occurs after the last packet
has completed, and is corrected before the next packet reception begins, then overrun will not occur.
The software acts on the misqueued buffer condition by writing the added buffer descriptor address to
the appropriate Rx DMA State Head Descriptor Pointer in RCPPIDMASTATEW1 register.
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3.3.2.6
Receive Abort Handling
The DMA controller sets ‘Rx Abort’ bit used to identify Rx packets which were aborted due to lack of
buffers. Software must take care to inspect any Rx SOP packet for this bit and ignore all the buffers in that
packet as the packet is incomplete. Also, for aborted packets, the packet length may not match the data
size in the buffers.
3.3.2.7
RNDIS Mode and Transparent Mode Receive DMA Operation
Transparent Mode DMA operation is the default DMA mode (as described in previous section) where an
interrupt is generated whenever a DMA packet is received. In the transparent mode, DMA packet size
cannot be greater than USB MaxPktSize for the endpoint. This means, for receiving say n USB packets,
the DMA controller should be programmed with a queue of minimum n DMA packets. RBUFCNTn register
also needs to be written with value n. The number n should be greater than 3 as the RBUFCNTn register
should have at least 3 packets for the Rx DMA to receive packets from the endpoint FIFO.
RNDIS mode DMA is used to receive DMA packets which are larger than USB MaxPktSize. This is
accomplished by breaking the larger packet into smaller packets, not larger than USB MaxPktSize. This
implies that multiple USB packets of MaxPktSize will be received and transferred together as a single
large DMA packet and the DMA interrupt is generated only at the end of the complete reception of DMA
packet. This mode of DMA is used for RNDIS type transfers over USB. The protocol defines the end of the
complete transfer by receiving a short USB packet (smaller than USB MaxPktSize as mentioned in USB
specification 2.0). If the DMA packet size is an exact multiple of USB MaxPktSize, the DMA controller
waits for a zero byte packet at the end of complete transfer to signify the completion of the transfer.
RNDIS Mode DMA is supported only when USB MaxPktSize is an integral multiple of 64 bytes.
RNDIS Mode Setup
The setup of RNDIS mode DMA is similar to the default Transparent Mode as mentioned in the previous
section. The following steps need to be taken for setting up RNDIS mode Rx DMA:
•
RNDIS mode requires that the associated MaxPkt Size and FIFO size must be integral multiples of
64 bytes.
•
After reset the software must write zeroes to all Rx DMA State registers (RCPPIDMASTATEW0,
RCPPIDMASTATEW1,
RCPPIDMASTATEW2,
RCPPIDMASTATEW3,
RCPPIDMASTATEW4,
RCPPIDMASTATEW5 and RCPPIDMASTATEW6).
•
•
•
•
The software constructs receive queue in memory.
Enable DMA for the endpoint in the PERI_RXCSR or HOST_RXCSR by setting the DMAEN bit.
Enable the DMA ports by setting RCPPI_ENABLE bit of RCPPICR register.
Set RNDIS bit of CTRLR register for enabling RNDIS mode for all channels or set TXnEN bit of
RNDISR register for specific DMA channel n.
•
Set the value in RBUFCNTn register (where n is the channel number) for the number of buffers
available in the Rx queue. The minimum value should be 3 for the Rx DMA to start operation. The
value in RBUFCNTn decrements as DMA controller consumes the buffers for reception.
•
•
Write the head of the queue descriptor pointer to the RCPPIDMASTATEW1 register to start the DMA.
The USB controller will send IN token and wait for the data on the bus. Once data is received, DMA
controller will transfer the data in the Rx queue from the endpoint FIFO. Once a complete DMA packet
is received, the interrupt associated with the DMA channel is asserted.
•
•
If the DMA packet size is exact multiple of USB MaxPktSize, a zero byte packet is expected and
interrupt associated with the DMA channel is asserted when that zero byte packet is received.
If the DMA packet size is not exact multiple of USB MaxPktSize, the last USB packet received is a
short packet and interrupt associated with the DMA channel is asserted.
An additional feature of automatically generating IN tokens is available. This feature is used in USB Host
mode operation of the USB controller. This feature is functional in RNDIS mode DMA only. To
automatically generate the IN tokens while receiving data, set the field RXn_AUTOREQ (where n is the
channel number) of AUTOREQ register with binary 01. In this case, IN tokens will be generated and sent
to the target USB peripheral device after every successfully received packet. No IN token will be
generated after the End Of DMA Packet is reached. Rx DMA interrupt is generated after the complete
reception.
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If RXn_AUTOREQ (where n is the channel number) of AUTOREQ register is set with binary 11, IN tokens
will be generated and sent to the target USB peripheral device even after the End Of DMA Packet is
reached. This feature is useful to keep data reception operational across multiple DMA packets in a Rx
queue. The host processor does not have to restart sending IN tokens for every DMA packet in the Rx
queue.
Transparent Mode Setup
Transparent receive DMA configuration is identical to RNDIS DMA configuration with the exception of the
following:
•
•
•
•
Each packet is defined by a single buffer descriptor with SOP and EOP bit fields set.
Packet size is not bounded to be a multiple of 64 byte but by max packet size.
CTRLR.RNDIS bit field should be cleared to zero.
RXn:AUTOREQ register field is programmed with the value of 0, which is programmed for no Auto
Request.
3.3.2.8
DMA Teardown Procedure
In order to Teardown a TX channel, the endpoint FIFO must be flushed after the DMA Teardown
completes. Teardown is not complete until the following steps are successfully completed.
•
Write the TX Teardown register in the CPPI DMA with the channel to teardown. The DMA will interrupt
after the teardown is complete and the TX Completion Pointer will be FFFF FFFCh. This indicates that
the DMA has completed the teardown and all of the associated CPPI buffers can be reclaimed.
•
Call the flush_tx_fifo routine (code provided in Example 4) once if the FIFO is set up for single-buffer or
twice for double-buffer.
3.4 Interrupt Handling
Table 14. Interrupts Generated by the USB Controller
Interrupt
Description
Tx Endpoint [4:0]
Rx Endpoint [4:1]
Tx endpoint ready or error condition. For endpoints 4 to 0. (Rx and Tx for endpoint 0)
Rx endpoint ready or error condition. For endpoints 4 to 1. (Endpoint 0 has interrupt status in
Tx interrupt)
USB Core[8:0]
Interrupts for 9 USB conditions
DMA Tx Completion [3:0]
DMA Rx Completion [3:0]
Tx DMA completion interrupt for channel 3 to 0
Rx DMA completion interrupt for channel 3 to 0
Whenever any of these interrupt conditions are generated, the host processor is interrupted. The software
needs to read the different interrupt status registers (discussed in later section) to determine the source of
the interrupt.
Table 15. USB Interrupt Conditions
Interrupt
USB[8]
USB[7]
USB[6]
USB[5]
USB[4]
Description
DRVVBUS level change
VBus voltage < VBus Valid Threshold (VBus error)
SRP detected
Device Disconnected (Valid in Host Mode)
Device Connected (Valid in Host Mode)
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Table 15. USB Interrupt Conditions (continued)
Interrupt
USB[3]
USB[2]
Description
SOF started
Reset Signaling detected (In Peripheral Mode)
Babble detected (In Host Mode)
USB[1]
USB[0]
Resume signaling detected
Suspend Signaling detected
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3.4.1
USB Core Interrupts
There are two methods available for software to access USB core interrupts, selectable by the UINT bit of
CTRLR. The UINT bit cleared to 0 selects the PDR 2.0 compliant register set (INTSRCR, INTSETR,
INTCLRR, INTMSKR, INTMSKSETR, INTMSKCLRR, INTMASKEDR). This is the default, and should be
used for most systems. The DRVVBUS level change interrupt is only available in the PDR compliant
register. UINT set to one selects direct access to the USB core interrupt registers (INTRUSB, INTRUSBE,
INTRTX, INTRRX). Software should select a single method for interrupts and use its corresponding
registers exclusively.
Interrupt status can be determined using the INTSRCR (interrupt source) register. This register is
non-masked. To clear the interrupt source, set the corresponding interrupt bit in INTCLRR register. For
debugging purposes, interrupt can be set manually through INTSETR register.
The interrupt controller provides the option of masking the interrupts. A mask can be set using
INTMSKSETR register and can be cleared by setting the corresponding bit in the INTMSKCLRR register.
The mask can be read from INTMSKR register. The masked interrupt status is determined using the
INTMASKEDR register.
Software should write all zeros to the End Of Interrupt Register (EOIR) to acknowledge the completion of
the USB core interrupt.
Note: If the EOIR is not written, the interrupt output to the CPU will not be pulsed again for the next
interrupt.
3.4.2
DMA Interrupts
Interrupt status for the DMA interrupts is determined by TCCPIRAWSR and RCPPIRAWSR registers.
These are the raw interrupt status registers for DMA interrupts.
Tx DMA interrupts mask is set using TCPPIENSETR register and cleared using TCPPIIENCLRR register.
The masked status is read using TCPPIMSKSR register.
Rx DMA interrupts mask is set using RCPPIENSETR register and cleared using RCPPIIENCLRR register.
The masked status is read using RCPPIMSKSR register.
Like USB core interrupts, the CPPIEOIR register needs to be written by the host processor software to
acknowledge the completion of the interrupt.
Upon receipt of a DMA interrupt, software should check TCPPIRAWSR/RCPPIRAWSR to determine
which DMA channel(s) to service. Check the CPPI buffer descriptor ownership field for the completed
channel for error conditions and add or update buffer descriptors as needed. Write the RCPPICOMPPTR
or TCPPICOMPPTR completion pointer with the address of the buffer descriptor serviced in order to clear
the interrupt. Finally, write the DMA End Of Interrupt register CPPIEOIR with all zeros to enable future (or
current unserviced) interrupts to pulse the interrupt output to the CPU.
When using DMA with a TX endpoint, set the TXCSR register DMAMODE bit to one in order to receive
only error (not packet completion) interrupts. For DMA with an RX endpoint, the DMAMODE bit in RXCSR
should be cleared to 0.
3.5 Test Modes
The controller supports the four USB 2.0 test modes defined for High-speed functions. It also supports an
additional “FIFO access” test mode that can be used to test the operation of the CPU interface, the DMA
controller (if configured) and the RAM block.
The test modes are entered by writing to the TestMode register (offset address 0x40F). At test mode is
usually requested by the host sending a SET_FEATURE request to Endpoint 0. When the software
receives the request, it should wait until the Endpoint 0 transfer has completed (when it receives the
Endpoint 0 interrupt indicating the status phase has completed) then write to the TestMode register.
Note: These test modes have no purpose in normal operation.
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3.5.1
TEST_SE0_NAK
To enter the Test_SE0_NAK test mode, the software should set the Test_SE0-NAK bit by writing 0x01 to
the TestMode register. The controller will then go into a mode in which it responds to any valid IN token
with a NAK.
3.5.2
3.5.3
TEST_J
To enter the Test_J test mode, the software should set the Test_J bit by writing 0x02 to the TestMode
register. The controller will then go into a mode in which it transmits a continuous J on the bus.
TEST_K
To enter the Test_K test mode, the software should set the Test_K bit by writing 0x04 to the TestMode
register. The controller will go into a mode in which it transmits a continuous K on the bus.
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3.5.4
TEST_PACKET
To execute the Test_Packet, the software should:
1. Start a session (if the core is being used in Host mode).
2. Write the standard test packet (shown below) to the Endpoint 0 FIFO.
3. Write 0x8 to the TestMode register to enter Test_Packet test mode.
4. Set the TxPktRdy bit in the CSR0 register (D1).
The 53 by test packet to load is as follows (all bytes in hex). The test packet only has to be loaded once;
the controller will keep re-sending the test packet without any further intervention from the software.
00
00
00
AA
EE
FE
FF
F7
F7
00
AA
EE
FF
FF
FB
FB
00
AA
EE
FF
FF
FD
FD
00
AA
EE
FF
FF
FC
7E
00
AA
EE
FF
7F
7E
00
AA
EE
FF
BF
BF
00
AA
EE
FF
DF
DF
AA
EE
FF
EF
EF
This data sequence is defined in Universal Serial Bus Specification Revision 2.0, Section 7.1.20. The
controller will add the DATAA0 PID to the head of the data sequence and the CRC to the end.
3.5.5
FIFO_ACCESS
The FIFO Access test mode allows the user to test the operation of CPU Interface, the DMA controller (if
configured) and the RAM block by loading a packet of up to 64 bytes into the Endpoint 0 FIFO and then
reading it back out again. Endpoint 0 is used because it is a bi-directional endpoint that uses the same
area of RAM for its Tx and Rx FIFOs.
Note: The core does not need to be connected to the USB bus to run this test. If it is connected,
then no session should be in progress when the test is run.
The test procedure is as follows:
1. Load a packet of up to 64 bytes into the Endpoint 0 Tx FIFO.
2. Set CSR0.TxPktRdy.
3. Write 0x40 to the Testmode register.
4. Unload the packet from the Endpoint Rx FIFO, again.
5. Set CSR0.ServicedRxPktRdy
Writing 0x40 to the Testmode register causes the following sequence of events:
1. The Endpoint 0 CPU pointer (which records the number of bytes to be transmitted) is copied to the
Endpoint 0 USB pointer (which records the number of bytes received).
2. The Endpoint 0 CPU pointer is reset.
3. CSR0.TxPktRdy is cleared.
4. CSR0.RxPktRdy is set.
5. An Endpoint 0 interrupt is generated (if enabled).,
The effect of these steps is to make the Endpoint 0 controller act as if the packet loaded into the Tx FIFO
has flushed and the same packet received over the USB. The data that was loaded in the Tx FIFO can
now be read out of the Rx FIFO.
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3.5.6
FORCE_HOST
The Force Host test mode enables the user to instruct the core to operate in Host mode, regardless of
whether it is actually connected to any peripheral, i.e., the state of the CID input and the LINESTATE and
HOSTDISCON signals are ignored. (While in this mode, the state of the HOSTDISCON signal can be read
from bit 7 of the DevCtl register.)
This mode, which is selected by setting bit 7 within the Testmode register, allows implementation of the
USB Test_Force_Enable (7.1.20). It can also be used for debugging PHY problems in hardware.
While the Force_Host bit remains set, the core will enter Host mode when the Session bit is set and
remain in Host mode until the Session bit is cleared even if a connected device is disconnected during the
session. The operating speed while in this mode is determined for the sitting of the Force_HS and
Force_FS bits of the Testmode register.
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3.6 Reset Considerations
The USB controller has two reset sources: hardware reset and the soft reset (RESET bit in CTRLR
register).
3.6.1
Software Reset Considerations
When the RESET bit in CTRLR is set, all the USB controller registers and DMA operations are reset. The
bit is cleared automatically.
A software reset on the ARM or DSP CPUs does not affect the register values and operation of the USB
controller.
3.6.2
3.6.3
Hardware Reset Considerations
When a hardware reset is asserted, all the registers are set to their default values.
USB Reset Considerations
When operating in peripheral mode, a USB reset received from the host causes some internal registers to
be reset. The USB controller setup operations (for example FIFO sizing) in peripheral mode should be
performed after receiving the USB reset, and again on each subsequent USB reset. There are some
conditions where multiple USB reset interrupts may be received in rapid succession. Good interrupt
handling practices must be observed to assure that the setup is performed (again) after the final USB
reset interrupt.
3.7 Interrupt Support
The USB peripheral presents a single interrupt to the ARM interrupt controller (AINTC). For information on
the mapping of interrupts, refer to the device-specific data manual.
3.8 EDMA Event Support
The USB is an internal bus master peripheral and therefore does not utilize any EDMA events. The
registers support only individual access. Bursting data to or from the USB register space through EDMA is
not supported.
3.9 Power Management
The USB controller can be placed in reduced power modes to conserve power during periods of low
activity. The power management of the peripheral is controlled by the processor Power and Sleep
Controller (PSC). The PSC acts as a master controller for power management for all of the peripherals on
the device. For detailed information on power management procedures using the PSC, see the
TMS320DMxxx DMSoC ARM Subsystem Reference Guide (spru856).
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Registers
4
Registers
Table 16 lists the memory-mapped registers for the universal serial bus (USB). See the device-specific
data manual for the memory address of these registers. The base address is 01C6 4000h.
Note: In some cases, a single register address can have different names or meanings depending
on the mode (host/peripheral) or the setting of the index register. The meaning of some bit
fields varies with the mode.
Table 16. Universal Serial Bus (USB) Registers
Offset
4h
Acronym
Register Description
Section
CTRLR
Control Register
Section 4.1
Section 4.2
Section 4.3
Section 4.4
Section 4.5
Section 4.6
Section 4.7
Section 4.8
Section 4.9
Section 4.10
Section 4.11
Section 4.12
Section 4.13
Section 4.14
Section 4.15
Section 4.16
Section 4.17
Section 4.18
Section 4.19
Section 4.20
Section 4.21
Section 4.22
Section 4.23
Section 4.24
Section 4.25
Section 4.26
Section 4.27
Section 4.28
Section 4.29
8h
STATR
Status Register
10h
14h
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
80h
84h
88h
90h
94h
98h
9Ch
C0h
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
RNDISR
RNDIS Register
AUTOREQ
INTSRCR
Autorequest Register
USB Interrupt Source Register
USB Interrupt Source Set Register
USB Interrupt Source Clear Register
USB Interrupt Mask Register
INTSETR
INTCLRR
INTMSKR
INTMSKSETR
INTMSKCLRR
INTMASKEDR
EOIR
USB Interrupt Mask Set Register
USB Interrupt Mask Clear Register
USB Interrupt Source Masked Register
USB End of Interrupt Register
INTVECTR
TCPPICR
USB Interrupt Vector Register
Transmit CPPI Control Register
Transmit CPPI Teardown Register
CPPI DMA End of Interrupt Register
Transmit CPPI Masked Status Register
Transmit CPPI Raw Status Register
Transmit CPPI Interrupt Enable Set Register
Transmit CPPI Interrupt Enable Clear Register
Receive CPPI Control Register
Receive CPPI Masked Status Register
Receive CPPI Raw Status Register
Receive CPPI Interrupt Enable Set Register
Receive CPPI Interrupt Enable Clear Register
Receive Buffer Count 0 Register
Receive Buffer Count 1 Register
Receive Buffer Count 2 Register
Receive Buffer Count 3 Register
Transmit/Receive CPPI Channel 0 State Block
Transmit CPPI DMA State Word 0
Transmit CPPI DMA State Word 1
Transmit CPPI DMA State Word 2
Transmit CPPI DMA State Word 3
Transmit CPPI DMA State Word 4
Transmit CPPI DMA State Word 5
Transmit CPPI Completion Pointer
Receive CPPI DMA State Word 0
TCPPITDR
CPPIEOIR
TCPPIMSKSR
TCPPIRAWSR
TCPPIIENSETR
TCPPIIENCLRR
RCPPICR
RCPPIMSKSR
RCPPIRAWSR
RCPPIENSETR
RCPPIIENCLRR
RBUFCNT0
RBUFCNT1
RBUFCNT2
RBUFCNT3
100h
104h
108h
10Ch
110h
114h
11Ch
120h
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
TCPPICOMPPTR
Section 4.30
Section 4.31
Section 4.32
Section 4.33
Section 4.34
Section 4.35
Section 4.36
Section 4.37
RCPPIDMASTATEW0
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Table 16. Universal Serial Bus (USB) Registers (continued)
Offset
124h
128h
12Ch
130h
134h
138h
13Ch
Acronym
Register Description
Section
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
Receive CPPI DMA State Word 1
Receive CPPI DMA State Word 2
Receive CPPI DMA State Word 3
Receive CPPI DMA State Word 4
Receive CPPI DMA State Word 5
Receive CPPI DMA State Word 6
Receive CPPI Completion Pointer
Transmit/Receive CPPI Channel 1 State Block
Transmit CPPI DMA State Word 0
Transmit CPPI DMA State Word 1
Transmit CPPI DMA State Word 2
Transmit CPPI DMA State Word 3
Transmit CPPI DMA State Word 4
Transmit CPPI DMA State Word 5
Transmit CPPI Completion Pointer
Receive CPPI DMA State Word 0
Receive CPPI DMA State Word 1
Receive CPPI DMA State Word 2
Receive CPPI DMA State Word 3
Receive CPPI DMA State Word 4
Receive CPPI DMA State Word 5
Receive CPPI DMA State Word 6
Receive CPPI Completion Pointer
Transmit/Receive CPPI Channel 2 State Block
Transmit CPPI DMA State Word 0
Transmit CPPI DMA State Word 1
Transmit CPPI DMA State Word 2
Transmit CPPI DMA State Word 3
Transmit CPPI DMA State Word 4
Transmit CPPI DMA State Word 5
Transmit CPPI Completion Pointer
Receive CPPI DMA State Word 0
Receive CPPI DMA State Word 1
Receive CPPI DMA State Word 2
Receive CPPI DMA State Word 3
Receive CPPI DMA State Word 4
Receive CPPI DMA State Word 5
Receive CPPI DMA State Word 6
Receive CPPI Completion Pointer
Transmit/Receive CPPI Channel 3 State Block
Transmit CPPI DMA State Word 0
Transmit CPPI DMA State Word 1
Transmit CPPI DMA State Word 2
Transmit CPPI DMA State Word 3
Transmit CPPI DMA State Word 4
Transmit CPPI DMA State Word 5
Section 4.38
Section 4.39
Section 4.40
Section 4.41
Section 4.42
Section 4.43
Section 4.44
140h
144h
148h
14Ch
150h
154h
15Ch
160h
164h
168h
16Ch
170h
174h
178h
17Ch
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
TCPPICOMPPTR
Section 4.30
Section 4.31
Section 4.32
Section 4.33
Section 4.34
Section 4.35
Section 4.36
Section 4.37
Section 4.38
Section 4.39
Section 4.40
Section 4.41
Section 4.42
Section 4.43
Section 4.44
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
180h
184h
188h
18Ch
190h
194h
19Ch
1A0h
1A4h
1A8h
1ACh
1B0h
1B4h
1B8h
1BCh
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
TCPPICOMPPTR
Section 4.30
Section 4.31
Section 4.32
Section 4.33
Section 4.34
Section 4.35
Section 4.36
Section 4.37
Section 4.38
Section 4.39
Section 4.40
Section 4.41
Section 4.42
Section 4.43
Section 4.44
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
Section 4.30
Section 4.31
Section 4.32
Section 4.33
Section 4.34
Section 4.35
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Registers
Table 16. Universal Serial Bus (USB) Registers (continued)
Offset
1DCh
1E0h
1E4h
1E8h
1ECh
1F0h
1F4h
1F8h
1FCh
Acronym
Register Description
Section
TCPPICOMPPTR
Transmit CPPI Completion Pointer
Receive CPPI DMA State Word 0
Receive CPPI DMA State Word 1
Receive CPPI DMA State Word 2
Receive CPPI DMA State Word 3
Receive CPPI DMA State Word 4
Receive CPPI DMA State Word 5
Receive CPPI DMA State Word 6
Receive CPPI Completion Pointer
Common USB Registers
Section 4.36
Section 4.37
Section 4.38
Section 4.39
Section 4.40
Section 4.41
Section 4.42
Section 4.43
Section 4.44
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
400h
401h
402h
FADDR
POWER
INTRTX
Function Address Register
Section 4.45
Section 4.46
Section 4.47
Power Management Register
Interrupt Register for Endpoint 0 and for Transmit
Endpoints 1 to 4
404h
406h
408h
40Ah
40Bh
40Ch
40Eh
INTRRX
INTRTXE
INTRRXE
INTRUSB
INTRUSBE
FRAME
Interrupt Register for Receive Endpoints 1 to 4
Interrupt enable register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts
Interrupt Enable Register for INTRUSB
Frame Number Register
Section 4.48
Section 4.49
Section 4.50
Section 4.51
Section 4.52
Section 4.53
Section 4.54
INDEX
Index Register for Selecting the Endpoint Status and Control
Registers
40Fh
TESTMODE
Register to Enable the USB 2.0 Test Modes
Section 4.55
Indexed Registers (These registers operate on the endpoint selected by the INDEX register)
410h
412h
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
(Index register set to select Endpoints 1-4)
Section 4.56
Section 4.57
Section 4.58
Section 4.59
Section 4.60
Section 4.61
Section 4.62
Section 4.63
Section 4.64
Section 4.65
PERI_CSR0
HOST_CSR0
PERI_TXCSR
HOST_TXCSR
RXMAXP
Control Status Register for Endpoint 0 in Peripheral Mode.
(Index register set to select Endpoint 0)
Control Status Register for Endpoint 0 in Host Mode
(Index register set to select Endpoint 0)
Control Status Register for Peripheral Transmit Endpoint.
(Index register set to select Endpoints 1-4)
Control Status Register for Host Transmit Endpoint
(Index register set to select Endpoints 1-4)
414h
416h
Maximum Packet Size for Peripheral/Host Receive Endpoint
(Index register set to select Endpoints 1-4)
PERI_RXCSR
HOST_RXCSR
COUNT0
Control Status Register for Peripheral Receive Endpoint.
(Index register set to select Endpoints 1-4)
Control Status Register for Host Receive Endpoint
(Index register set to select Endpoints 1-4)
418h
41Ah
Number of Received Bytes in Endpoint 0 FIFO
(Index register set to select Endpoint 0)
RXCOUNT
Number of Bytes in Host Receive Endpoint FIFO
(Index register set to select Endpoints 1- 4)
HOST_TYPE0
Defines the speed of Endpoint 0
Section 4.66
Section 4.67
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral
endpoint number for the host Transmit endpoint.
(Index register set to select Endpoints 1-4)
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Table 16. Universal Serial Bus (USB) Registers (continued)
Offset
Acronym
Register Description
Section
41Bh
HOST_NAKLIMIT0
Sets the NAK response timeout on Endpoint 0
(Index register set to select Endpoint 0)
Section 4.68
HOST_TXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the
NAK response timeout on Bulk transactions for host Transmit
endpoint. (Index register set to select Endpoints 1-4)
Section 4.69
41Ch
41Dh
41Fh
HOST_RXTYPE
HOST_RXINTERVAL
CONFIGDATA
Sets the operating speed, transaction protocol and peripheral
endpoint number for the host Receive endpoint.
(Index register set to select Endpoints 1-4)
Section 4.70
Section 4.71
Section 4.72
Sets the polling interval for Interrupt/ISOC transactions or the
NAK response timeout on Bulk transactions for host Receive
endpoint. (Index register set to select Endpoints 1-4)
Returns details of core configuration. (Index register set to
select Endpoint 0)
FIFOn
420h
424h
428h
42Ch
430h
FIFO0
FIFO1
FIFO2
FIFO3
FIFO4
Transmit and Receive FIFO Register for Endpoint 0
Transmit and Receive FIFO Register for Endpoint 1
Transmit and Receive FIFO Register for Endpoint 2
Transmit and Receive FIFO Register for Endpoint 3
Transmit and Receive FIFO Register for Endpoint 4
OTG Device Control
Section 4.73
Section 4.74
Section 4.75
Section 4.76
Section 4.77
460h
DEVCTL
OTG Device Control Register
Section 4.78
Dynamic FIFO Control
462h
463h
464h
466h
TXFIFOSZ
Transmit Endpoint FIFO Size
(Index register set to select Endpoints 1-4)
Section 4.79
Section 4.80
Section 4.81
Section 4.82
RXFIFOSZ
Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4)
TXFIFOADDR
RXFIFOADDR
Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4)
Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4)
Target Endpoint 0 Control Registers, Valid Only in Host Mode
480h
482h
TXFUNCADDR
TXHUBADDR
Address of the target function that has to be accessed
through the associated Transmit Endpoint.
Section 4.83
Section 4.84
Address of the hub that has to be accessed through the
associated Transmit Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
483h
TXHUBPORT
Port of the hub that has to be accessed through the
associated Transmit Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.85
484h
486h
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed
through the associated Receive Endpoint.
Section 4.86
Section 4.87
Address of the hub that has to be accessed through the
associated Receive Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
487h
RXHUBPORT
Port of the hub that has to be accessed through the
associated Receive Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.88
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Registers
Table 16. Universal Serial Bus (USB) Registers (continued)
Offset
Acronym
Register Description
Section
Target Endpoint 1 Control Registers, Valid Only in Host Mode
488h
48Ah
TXFUNCADDR
TXHUBADDR
Address of the target function that has to be accessed
through the associated Transmit Endpoint.
Section 4.83
Section 4.84
Address of the hub that has to be accessed through the
associated Transmit Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
48Bh
TXHUBPORT
Port of the hub that has to be accessed through the
associated Transmit Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.85
48Ch
48Eh
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed
through the associated Receive Endpoint.
Section 4.86
Section 4.87
Address of the hub that has to be accessed through the
associated Receive Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
48Fh
RXHUBPORT
Port of the hub that has to be accessed through the
associated Receive Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.88
Target Endpoint 2 Control Registers, Valid Only in Host Mode
490h
492h
TXFUNCADDR
TXHUBADDR
Address of the target function that has to be accessed
through the associated Transmit Endpoint.
Section 4.83
Section 4.84
Address of the hub that has to be accessed through the
associated Transmit Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
493h
TXHUBPORT
Port of the hub that has to be accessed through the
associated Transmit Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.85
494h
496h
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed
through the associated Receive Endpoint.
Section 4.86
Section 4.87
Address of the hub that has to be accessed through the
associated Receive Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
497h
RXHUBPORT
Port of the hub that has to be accessed through the
associated Receive Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.88
Target Endpoint 3 Control Registers, Valid Only in Host Mode
498h
49Ah
TXFUNCADDR
TXHUBADDR
Address of the target function that has to be accessed
through the associated Transmit Endpoint.
Section 4.83
Section 4.84
Address of the hub that has to be accessed through the
associated Transmit Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
49Bh
49Ch
TXHUBPORT
Port of the hub that has to be accessed through the
associated Transmit Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.85
Section 4.86
RXFUNCADDR
Address of the target function that has to be accessed
through the associated Receive Endpoint.
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Table 16. Universal Serial Bus (USB) Registers (continued)
Offset
Acronym
Register Description
Section
49Eh
RXHUBADDR
Address of the hub that has to be accessed through the
associated Receive Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.87
49Fh
RXHUBPORT
Port of the hub that has to be accessed through the
associated Receive Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.88
Target Endpoint 4 Control Registers, Valid Only in Host Mode
4A0h
4A2h
TXFUNCADDR
TXHUBADDR
Address of the target function that has to be accessed
through the associated Transmit Endpoint.
Section 4.83
Section 4.84
Address of the hub that has to be accessed through the
associated Transmit Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
4A3h
TXHUBPORT
Port of the hub that has to be accessed through the
associated Transmit Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.85
4A4h
4A6h
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed
through the associated Receive Endpoint.
Section 4.86
Section 4.87
Address of the hub that has to be accessed through the
associated Receive Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
4A7h
RXHUBPORT
Port of the hub that has to be accessed through the
associated Receive Endpoint. This is used only when full
speed or low speed device is connected via a USB2.0
high-speed hub.
Section 4.88
Control and Status Register for Endpoint 0
Control Status Register for Endpoint 0 in Peripheral Mode
Control Status Register for Endpoint 0 in Host Mode
Number of Received Bytes in Endpoint 0 FIFO
Defines the Speed of Endpoint 0
502h
PERI_CSR0
HOST_CSR0
COUNT0
Section 4.57
Section 4.58
Section 4.64
Section 4.66
Section 4.68
Section 4.72
508h
50Ah
50Bh
50Fh
HOST_TYPE0
HOST_NAKLIMIT0
CONFIGDATA
Sets the NAK Response Timeout on Endpoint 0
Returns details of core configuration.
Control and Status Register for Endpoint 1
Maximum Packet Size for Peripheral/Host Transmit Endpoint
510h
512h
TXMAXP
Section 4.56
Section 4.59
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
Section 4.60
514h
516h
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
Section 4.61
Section 4.62
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
Section 4.63
518h
51Ah
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
Section 4.65
Section 4.67
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral
endpoint number for the host Transmit endpoint.
51Bh
51Ch
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the
NAK response timeout on Bulk transactions for host Transmit
endpoint.
Section 4.69
Section 4.70
Sets the operating speed, transaction protocol and peripheral
endpoint number for the host Receive endpoint.
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Registers
Table 16. Universal Serial Bus (USB) Registers (continued)
Offset
Acronym
Register Description
Section
51Dh
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the
NAK response timeout on Bulk transactions for host Receive
endpoint.
Section 4.71
Control and Status Register for Endpoint 2
520h
522h
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Section 4.56
Section 4.59
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
Section 4.60
524h
526h
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
Section 4.61
Section 4.62
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
Section 4.63
528h
52Ah
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
Section 4.65
Section 4.67
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral
endpoint number for the host Transmit endpoint.
52Bh
HOST_TXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the
NAK response timeout on Bulk transactions for host Transmit
endpoint.
Section 4.69
52Ch
52Dh
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral
endpoint number for the host Receive endpoint.
Section 4.70
Section 4.71
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the
NAK response timeout on Bulk transactions for host Receive
endpoint.
Control and Status Register for Endpoint 3
530h
532h
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Section 4.56
Section 4.59
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
Section 4.60
534h
536h
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
Section 4.61
Section 4.62
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
Section 4.63
538h
53Ah
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
Section 4.65
Section 4.67
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral
endpoint number for the host Transmit endpoint.
53Bh
HOST_TXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the
NAK response timeout on Bulk transactions for host Transmit
endpoint.
Section 4.69
53Ch
53Dh
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral
endpoint number for the host Receive endpoint.
Section 4.70
Section 4.71
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the
NAK response timeout on Bulk transactions for host Receive
endpoint.
Control and Status Register for Endpoint 4
540h
542h
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Section 4.56
Section 4.59
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR
RXMAXP
Control Status Register for Host Transmit Endpoint
(host mode)
Section 4.60
Section 4.61
544h
Maximum Packet Size for Peripheral/Host Receive Endpoint
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Table 16. Universal Serial Bus (USB) Registers (continued)
Offset
Acronym
Register Description
Section
546h
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
Section 4.62
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
Section 4.63
548h
54Ah
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
Section 4.65
Section 4.67
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral
endpoint number for the host Transmit endpoint.
54Bh
HOST_TXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the
NAK response timeout on Bulk transactions for host Transmit
endpoint.
Section 4.69
54Ch
54Dh
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral
endpoint number for the host Receive endpoint.
Section 4.70
Section 4.71
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the
NAK response timeout on Bulk transactions for host Receive
endpoint.
4.1 Control Register (CTRLR)
Figure 16. Control Register (CTRLR)
31
15
16
Reserved
R-0
5
4
3
2
1
0
Reserved
R-0
RNDIS
R/W-0
UINT
R/W-0
Reserved
R-0
CLKFACK
R/W-0
RESET
W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. Control Register (CTRLR) Field Descriptions
Bit
31-5
4
Field
Value Description
Reserved
RNDIS
0
Reserved
0-1
0-1
0
RNDIS mode enable.
USB non-PDR interrupt enable.
Reserved
3
UINT
2
Reserved
CLKFACK
RESET
1
0-1
Clock stop fast ACK enable.
Soft reset.
0
0
1
Writing a 1 starts a module reset.
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Registers
4.2 Status Register (STATR)
Figure 17. Status Register (STATR)
31
16
Reserved
R-0
15
1
0
Reserved
R-0
DRVVBUS
R-0
LEGEND: R = Read only; -n = value after reset
Table 18. Status Register (STATR) Field Descriptions
Bit
31-1
0
Field
Value Description
Reserved
DRVVBUS
0
Reserved
Current DRVVBUS value.
DRVVBUS value is logic 0
DRVVBUS value is logic 1
0
1
4.3 RNDIS Register (RNDISR)
Figure 18. RNDIS Register (RNDISR)
31
15
20
19
18
17
16
Reserved
R-0
RX4EN RX3EN RX2EN RX1EN
R/W-0
R/W-0
R/W-0
R/W-0
4
3
2
1
0
Reserved
R-0
TX4EN TX3EN TX2EN TX1EN
R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. RNDIS Register (RNDISR) Field Descriptions
Bit
Field
Value Description
31-20 Reserved
0
Reserved
19
18
17
16
15-4
3
RX4EN
RX3EN
RX2EN
RX1EN
Reserved
TX4EN
TX3EN
TX2EN
TX1EN
0-1
0-1
0-1
0-1
0
Receive Endpoint 4 RNDIS mode enable.
Receive Endpoint 3 RNDIS mode enable.
Receive Endpoint 2 RNDIS mode enable.
Receive Endpoint 1 RNDIS mode enable.
Reserved
0-1
0-1
0-1
0-1
Transmit Endpoint 4 RNDIS mode enable.
Transmit Endpoint 3 RNDIS mode enable.
Transmit Endpoint 2 RNDIS mode enable.
Transmit Endpoint 1 RNDIS mode enable.
2
1
0
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4.4 Auto Request Register (AUTOREQ)
Figure 19. Auto Request Register (AUTOREQ)
31
16
Reserved
R-0
15
8
7
6
5
4
3
2
1
0
Rx1
Reserved
R-0
Rx4
Rx3
Rx2
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. Auto Request Register (AUTOREQ) Field Descriptions
Bit
31-8
7-6
Field
Value Description
Reserved
Rx4
0
0-3h
0
Reserved
RX endpoint 4 Auto Req enable.
No auto req
1h
2h
3h
0-3h
0
Auto req on all but EOP
Reserved
Auto req always
5-4
3-2
1-0
Rx3
Rx2
Rx1
RX endpoint 3 Auto Req enable.
No auto req
1h
2h
3h
0-3h
0
Auto req on all but EOP
Reserved
Auto req always
RX endpoint 2 Auto Req enable.
No auto req
1h
2h
3h
0-3h
0
Auto req on all but EOP
Reserved
Auto req always
RX endpoint 1 Auto Req enable.
No auto req
1h
2h
3h
Auto req on all but EOP
Reserved
Auto req always
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Registers
4.5 USB Interrupt Source Register (INTSRCR)
Figure 20. USB Interrupt Source Register (INTSRCR)
31
15
25
8
24
16
0
Reserved
R-0
USB
R-0
13
12
7
5
4
Reserved
R-0
RX
Reserved
R-0
TX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 21. USB Interrupt Source Register (INTSRCR) Field Descriptions
Bit
Field
Value Description
31-25 Reserved
24-16 USB
0
Reserved
0-1FFh USB interrupt sources
Generated by the USB core (not the DMA)
Reserved
15-13 Reserved
0
12-8
RX
0-1Fh Receive endpoint interrupt sources
Generated by the USB core (not the DMA)
7-5
4-0
Reserved
TX
0
Reserved
0-Fh
Transmit endpoint interrupt sources
Generated by the USB core (not the DMA)
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4.6 USB Interrupt Source Set Register (INTSETR)
Figure 21. USB Interrupt Source Set Register (INTSETR)
31
15
25
8
24
16
0
Reserved
R-0
USB
W-0
13
12
7
5
4
Reserved
R-0
RX
Reserved
R-0
TX
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 22. USB Interrupt Source Set Register (INTSETR) Field Descriptions
Bit
Field
Value Description
31-25 Reserved
24-16 USB
0
Reserved
0-1FFh Write a 1 to set equivalent USB interrupt source
Allows the USB interrupt sources to be manually triggered
15-13 Reserved
0
Reserved
12-8
RX
0-1Fh Write a 1 to set equivalent Receive endpoint interrupt source
Allows the USB interrupt sources to be manually triggered
7-5
4-0
Reserved
TX
0
Reserved
0-Fh
Write a 1 to set equivalent Transmit endpoint interrupt source
Allows the USB interrupt sources to be manually triggered
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Registers
4.7 USB Interrupt Source Clear Register (INTCLRR)
Figure 22. USB Interrupt Source Clear Register (INTCLRR)
31
15
25
8
24
7
16
0
Reserved
R-0
USB
W-0
13
12
5
4
Reserved
R-0
RX
Reserved
R-0
TX
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 23. USB Interrupt Source Clear Register (INTCLRR) Field Descriptions
Bit
Field
Value Description
31-25 Reserved
24-16 USB
0
Reserved
0-1FFh Write a 1 to clear equivalent USB interrupt source
Allows the CPU to acknowledge an interrupt source and turn it off
15-13 Reserved
0
Reserved
12-8
RX
0-1Fh Write a 1 to clear equivalent Receive endpoint interrupt source
Allows the CPU to acknowledge an interrupt source and turn it off
7-5
4-0
Reserved
TX
0
Reserved
0-Fh
Write a 1 to clear equivalent Transmit endpoint interrupt source
Allows the CPU to acknowledge an interrupt source and turn it off
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4.8 USB Interrupt Mask Register (INTMSKR)
Figure 23. USB Interrupt Mask Register (INTMSKR)
31
15
25
8
24
16
0
Reserved
R-0
USB
R-0
13
12
7
5
4
Reserved
R-0
RX
Reserved
R-0
TX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 24. USB Interrupt Mask Register (INTMSKR) Field Descriptions
Bit
Field
Value Description
31-25 Reserved
24-16 USB
0
Reserved
0-1FFh USB interrupt source masks
Contains the masks of the interrupt sources generated by the USB core (not the DMA). These masks
are used to enable or disable interrupt sources appearing as masked interrupts
15-13 Reserved
0
Reserved
12-8
RX
1Fh
Receive endpoint interrupt source masks
Contains the masks of the interrupt sources generated by the USB core (not the DMA). These masks
are used to enable or disable interrupt sources appearing as masked interrupts.
7-5
4-0
Reserved
TX
0
Reserved
0-Fh
Transmit endpoint interrupt source masks
Contains the masks of the interrupt sources generated by the USB core (not the DMA). These masks
are used to enable or disable interrupt sources appearing as masked interrupts.
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Registers
4.9 USB Interrupt Mask Set Register (INTMSKSETR)
Figure 24. USB Interrupt Mask Set Register (INTMSKSETR)
31
15
25
8
24
7
16
0
Reserved
R-0
USB
W-0
13
12
5
4
Reserved
R-0
RX
Reserved
R-0
TX
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 25. USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions
Bit
Field
Value Description
31-25 Reserved
24-16 USB
0
Reserved
0-1FFh Write a 1 to set equivalent USB interrupt mask
Allows the USB interrupt masks to be individually enabled
15-13 Reserved
0
Reserved
12-8
RX
0-1Fh Write a 1 to set equivalent Receive endpoint interrupt mask
Allows the USB interrupt masks to be individually enabled
7-5
4-0
Reserved
TX
0
Reserved
0-Fh
Write a 1 to set equivalent Transmit endpoint interrupt mask
Allows the USB interrupt masks to be individually enabled
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4.10 USB Interrupt Mask Clear Register (INTMSKCLRR)
Figure 25. USB Interrupt Mask Clear Register (INTMSKCLRR)
31
15
25
8
24
7
16
0
Reserved
R-0
USB
W-0
13
12
5
4
Reserved
R-0
RX
Reserved
R-0
TX
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 26. USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions
Bit
Field
Value Description
31-25 Reserved
24-16 USB
0
Reserved
0-1FFh Write a 1 to clear equivalent USB interrupt mask
Allows the USB interrupt masks to be individually disabled
15-13 Reserved
0
Reserved
12-8
RX
0-1Fh Write a 1 to clear equivalent Receive endpoint interrupt mask
Allows the USB interrupt masks to be individually disabled
7-5
4-0
Reserved
TX
0
Reserved
0-Fh
Write a 1 to clear equivalent Transmit endpoint interrupt mask
Allows the USB interrupt masks to be individually disabled
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Registers
4.11 USB Interrupt Source Masked Register (INTMASKEDR)
Figure 26. USB Interrupt Source Masked Register (INTMASKEDR)
31
15
25
24
16
0
Reserved
R-0
USB
R-0
13
12
8
7
5
4
Reserved
R-0
RX
Reserved
R-0
TX
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 27. USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions
Bit
Field
Value Description
31-25 Reserved
24-16 USB
0
Reserved
0-1FFh USB interrupt sources masked
Contains the status of the interrupt sources generated by the USB core masked by the USB Interrupt
Mask Register values
15-13 Reserved
0
Reserved
12-8
RX
0-1Fh Receive endpoint interrupt sources masked
Contains the status of the interrupt sources generated by the USB core masked by the USB Interrupt
Mask Register values.
7-5
4-0
Reserved
TX
0
Reserved
0-Fh
Transmit endpoint interrupt sources masked
Contains the status of the interrupt sources generated by the USB core masked by the USB Interrupt
Mask Register values.
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4.12 USB End of Interrupt Register (EOIR)
Figure 27. USB End of Interrupt Register (EOIR)
31
16
0
Reserved
R-0
15
8
7
Reserved
R-0
VECTOR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. USB End of Interrupt Register (EOIR) Field Descriptions
Bit
31-8
7-0
Field
Value Description
Reserved
VECTOR
0
Reserved
0-FFh EOI Vector
Allows the CPU to acknowledge completion of an interrupt by writing to the EOI. An eoi_write signal will
be generated, the EOI vector will be updated to the written value, and another interrupt will be triggered
if interrupt sources remain. Software should always write zeros for the EOI vector value.
4.13 USB Interrupt Vector Register (INTVECTR)
Figure 28. USB Interrupt Vector Register (INTVECTR)
31
0
VECTOR
R-0
LEGEND: R = Read only; -n = value after reset
Table 29. USB Interrupt Vector Register (INTVECTR) Field Descriptions
Bit
Field
Value
0-FFFF FFFFh Input Interrupt Vector
Recycles the Interrupt Vector input to be read by the CPU
Description
31-0
VECTOR
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Registers
4.14 Transmit CPPI Control Register (TCPPICR)
Figure 29. Transmit CPPI Control Register (TCPPICR)
31
16
Reserved
R-0
15
1
0
Reserved
R-0
TCPPI_ENABLE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. Transmit CPPI Control Register (TCPPICR) Field Descriptions
Bit
31-1
0
Field
Value Description
Reserved
TCPPI_ENABLE
0
Reserved
Transmit CPPI Enable Controls if the Transmit CPPI DMA controller is enabled. Be sure to program
the CPPI chain and set the DMA state words before enabling the DMA. Failure to initialize the DMA
before enabling could result in spurious transfers and memory corruption.
0
1
Transmit CPPI DMA is disabled
Transmit CPPI DMA is enabled
4.15 Transmit CPPI Teardown Register (TCPPITDR)
Figure 30. Transmit CPPI Teardown Register (TCPPITDR)
31
READY
R-1
30
16
0
Reserved
R-0
15
2
1
Reserved
R-0
CHANNEL
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. Transmit CPPI Teardown Register (TCPPITDR) Field Descriptions
Bit
31
Field
Value Description
READY
Reserved
CHANNEL
0-1
0
Indicates if the Teardown register can be written
Reserved
30-2
1-0
0-3h
Teardown Channel
Indicates the channel that is to be torn down
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4.16 CPPI DMA End of Interrupt Register (CPPIEOIR)
Note: This register was previously named TCPPIEOIR, and that name will continue to exist in the
CSL for backward compatibility.
Figure 31. CPPI DMA End of Interrupt Register (CPPIEOIR)
31
15
16
Reserved
R-0
8
7
0
Reserved
R-0
VECTOR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. CPPI DMA End of Interrupt Register (CPPIEOIR) Field Descriptions
Bit
31-8
7-0
Field
Value Description
Reserved
VECTOR
0
Reserved
0-FFh End of Interrupt Vector
This is an application specific register which is essentially a general purpose output from the LCSAR.
One cycle after this register is written, the eoi_vector[7:0] value will appear on the eoi_vector output port
from the LCSAR and the eoi_write output port will be asserted for 1 clock cycle. This register is used to
convert level sensitive interrupts to pulsed, non-redundant interrupts. Software should write all zeros for
the vector value.
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Registers
4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR)
Figure 32. Transmit CPPI Masked Status Register (TCPPIMSKSR)
31
16
0
Reserved
R-0
15
4
3
Reserved
R-0
MASKED COMP_PENDING
R-0
LEGEND: R = Read only; -n = value after reset
Table 33. Transmit CPPI Masked Status Register (TCPPIMSKSR) Field Descriptions
Bit
31-4 Reserved
3-0 MASKED COMP_PENDING
Field
Value Description
0
Reserved
0-Fh Masked High Priority Transmit Completion Pending
Indicators for channels 3 to 0 Raw Transmit high priority completion indicators bitwise
anded with Transmit high priority completion mask bits
4.18 Transmit CPPI Raw Status Register (TCPPIRAWSR)
Figure 33. Transmit CPPI Raw Status Register (TCPPIRAWSR)
31
16
0
Reserved
R-0
15
4
3
Reserved
R-0
COMP_PENDING
R-0
LEGEND: R = Read only; -n = value after reset
Table 34. Transmit CPPI Raw Status Register (TCPPIRAWSR) Field Descriptions
Bit
31-4
3-0
Field
Value Description
Reserved
0
Reserved
COMP_PENDING
0-Fh
Raw High Priority Transmit Completion Pending
Indicators for channels 3 to 0 Active high flags which indicate that a packet has completed
transmission on the high priority queue
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4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR)
Figure 34. Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR)
31
15
16
Reserved
R-0
4
3
0
Reserved
R-0
COMP_PENDING_INTR_EN
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35. Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) Field Descriptions
Bit
31-4 Reserved
3-0 COMP_PENDING_INTR_EN
Field
Value Description
0
Reserved
0-Fh Transmit CPPI High Priority Interrupt Enables
These are active high interrupt enables corresponding to the Transmit CPPI High
Priority Completion Pending status bits.
4.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR)
Figure 35. Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR)
31
16
0
Reserved
R-0
15
4
3
Reserved
R-0
COMP_PENDING_INTR_EN
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 36. Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) Field Descriptions
Bit
Field
Value Description
Reserved
31-4 Reserved
0
3-0
COMP_PENDING_INTR_EN
0-Fh Writing a 1 to any of the bits in the Transmit CPPI Interrupt Enable Clear Register will
result in clearing of the corresponding bit in the Transmit CPPI High Priority Interrupt
Enable Register.
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Registers
4.21 Receive CPPI Control Register (RCPPICR)
Figure 36. Receive CPPI Control Register (RCPPICR)
31
16
Reserved
R-0
15
1
0
Reserved
R-0
RCPPI_ENABLE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 37. Receive CPPI Control Register (RCPPICR) Field Descriptions
Bit
31-1
0
Field
Value Description
Reserved
0
Reserved
RCPPI_ENABLE
Receive CPPI Enable Controls if the Receive CPPI DMA controller is enabled. Be sure to program
the CPPI chain and set the DMA state words before enabling the DMA. Failure to initialize the DMA
before enabling could result in spurious transfers and memory corruption.
0
1
Receive CPPI DMA is disabled.
Receive CPPI DMA is enabled.
4.22 Receive CPPI Masked Status Register (RCPPIMSKSR)
Figure 37. Receive CPPI Masked Status Register (RCPPIMSKSR)
31
16
0
Reserved
R-0
15
4
3
Reserved
R-0
MASKED_COMP_PENDING
R-0
LEGEND: R = Read only; -n = value after reset
Table 38. Receive CPPI Masked Status Register (RCPPIMSKSR) Field Descriptions
Bit
31-4
3-0
Field
Value Description
Reserved
0
Reserved
MASKED_COMP_PENDING
0-Fh
Masked Receive Completion Pending
Indicators for channels 3 to 0 Raw Receive completion indicators bitwise ANDed with
Receive completion mask bits
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4.23 Receive CPPI Raw Status Register (RCPPIRAWSR)
Figure 38. Receive CPPI Raw Status Register (RCPPIRAWSR)
31
16
0
Reserved
R-0
15
4
3
Reserved
R-0
COMP_PENDING
R-0
LEGEND: R = Read only; -n = value after reset
Table 39. Receive CPPI Raw Status Register (RCPPIRAWSR) Field Descriptions
Bit
31-4
3-0
Field
Value
0
Description
Reserved
Reserved
COMP_PENDING
0-Fh
Raw Receive Completion Pending
Indicators for channels 3 to 0 Active high flags which indicate that a packet has completed
reception
4.24 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR)
Figure 39. Receive CPPI Interrupt Enable Set Register (RCPPIENSETR)
31
15
16
Reserved
R-0
4
3
0
Reserved
R-0
COMP_PENDING_INTR_EN
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 40. Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) Field Descriptions
Bit
31-4 Reserved
3-0 COMP_PENDING_INTR_EN
Field
Value Description
0
Reserved
0-Fh
Receive CPPI Interrupt Enables
These are active high interrupt enables corresponding to the Receive CPPI Completion
Pending status bits. Writing a 1 to any of the bits in the Receive CPPI Interrupt Enable
Set Register will result in setting of the corresponding bit in the Receive CPPI Interrupt
Enable Register.
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Registers
4.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR)
Figure 40. Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR)
31
15
16
Reserved
R-0
4
3
0
Reserved
R-0
COMP_PENDING_INTR_EN
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 41. Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) Field Descriptions
Bit
31-4
3-0
Field
Value
0
Description
Reserved
Reserved
COMP_PENDING_INTR_EN
0-Fh
Receive CPPI Interrupt Enables
These are active high interrupt enables corresponding to the Receive CPPI
Completion Pending status bits. Writing a 1 to any of the bits in the Receive CPPI
Interrupt Enable Clear Register will result in clearing of the corresponding bit in the
Receive CPPI Interrupt Enable Register.
4.26 Receive Buffer Count 0 Register (RBUFCNT0)
Figure 41. Receive Buffer Count 0 Register (RBUFCNT0)
31
16
0
Reserved
R-0
15
BUFCNT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 42. Receive Buffer Count 0 Register (RBUFCNT0) Field Descriptions
Bit
31-16 Reserved
15-0 BUFCNT
Field
Value
0
Description
Reserved
0-FFFFh
Receive CPPI Buffer Count
The current count of CPPI buffers in Receive channel 0 queue. Writes add to current value (not
overwrite). The DMA requires a minimum of 3 RX buffers to operate.
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4.27 Receive Buffer Count 1 Register (RBUFCNT1)
Figure 42. Receive Buffer Count 1 Register (RBUFCNT1)
31
15
16
0
Reserved
R-0
BUFCNT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 43. Receive Buffer Count 1 Register (RBUFCNT1) Field Descriptions
Bit
31-16 Reserved
15-0 BUFCNT
Field
Value
Description
Reserved
Receive CPPI Buffer Count
0
0-FFFFh
The current count of CPPI buffers in Receive channel 1 queue. Writes add to current value (not
overwrite). The DMA requires a minimum of 3 RX buffers to operate.
4.28 Receive Buffer Count 2 Register (RBUFCNT2)
Figure 43. Receive Buffer Count 2 Register (RBUFCNT2)
31
16
0
Reserved
R-0
15
BUFCNT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 44. Receive Buffer Count 2 Register (RBUFCNT2) Field Descriptions
Bit
31-16 Reserved
15-0 BUFCNT
Field
Value
0
Description
Reserved
0-FFFFh
Receive CPPI Buffer Count
The current count of CPPI buffers in Receive channel 2 queue. Writes add to current value (not
overwrite). The DMA requires a minimum of 3 RX buffers to operate.
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Registers
4.29 Receive Buffer Count 3 Register (RBUFCNT3)
Figure 44. Receive Buffer Count 3 Register (RBUFCNT3)
31
15
16
0
Reserved
R-0
BUFCNT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 45. Receive Buffer Count 3 Register (RBUFCNT3) Field Descriptions
Bit
31-16 Reserved
15-0 BUFCNT
Field
Value
Description
Reserved
Receive CPPI Buffer Count 0
0
0-FFFFh
The current count of CPPI buffers in Receive channel 3 queue. Writes add to current value (not
overwrite). The DMA requires a minimum of 3 RX buffers to operate.
4.30 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0)
Figure 45. Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0)
31
15
16
TXQ_HEAD_PTR
R/W-0
2
1
0
TXQ_HEAD_PTR
R/W-0
Reserved
R-0
IN_PACKET
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 46. Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) Field Descriptions
Bit
Field
Value
0-3FFF FFFFh TX Queue Head Pointer
30-bit pointer to 32-bit aligned descriptor at the head of the high priority TX queue
Reserved
Description
31-2 TXQ_HEAD_PTR
1
0
Reserved
0
IN_PACKET
Flag indicating the DMA is in the middle of processing a packet
Not currently in packet
0
1
Currently in packet
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4.31 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1)
Figure 46. Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1)
31
15
16
SOP_DESCRIPTOR_PTR
R/W-0
2
1
0
SOP_DESCRIPTOR_PTR
R/W-0
Reserved
R-0
IN_PACKET
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 47. Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) Field Descriptions
Bit
Field
Value
0-3FFF FFFFh Start of Packet Buffer Descriptor Pointer
30-bit pointer to 32-bit aligned descriptor which is the first descriptor for the
Description
31-2 SOP_DESCRIPTOR_PTR
current packet
1
0
Reserved
0
Reserved
IN_PACKET
Flag indicating the DMA is in the middle of processing a packet
Not currently in packet
0
1
Currently in packet
4.32 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2)
Figure 47. Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2)
31
15
16
CURR_DESCRIPTOR_PTR
R/W-0
2
1
0
CURR_DESCRIPTOR_PTR
R/W-0
TRUNCATED_NON_EOP
R/W-0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 48. Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Field Descriptions
Bit
Field
Value
0-3FFF FFFFh Current Buffer Descriptor Pointer
30-bit pointer to 32-bit aligned descriptor for buffer from which data is currently
Description
31-2 CURR_DESCRIPTOR_PTR
being transmitted
1
TRUNCATED_NON_EOP
Flag indicating that packet truncation has occurred on the current packet within a
buffer which was not designated as the end of packet buff
0
1
Truncation within non end of packet buffer has not occurred
Truncation within non end of packet has occurred
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Registers
Table 48. Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Field Descriptions (continued)
Bit
Field
Value
Description
0
Reserved
0
Reserved
4.33 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3)
Figure 48. Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3)
31
0
CURR_BUFFER_PTR
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 49. Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) Field Descriptions
Bit
Field
Value
0-FFFF FFFFh Current Buffer Pointer
32-bit absolute byte address in buffer from which data is currently being
transmitted
Description
31-0 CURR_BUFFER_PTR
4.34 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4)
Figure 49. Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4)
31
15
24
23
18
17
16
DESC_MSG
R/W-0
Reserved
R-0
CURR_BUFFER_EOP
R/W-0
CURR_BUFFER_SOP
R/W-0
0
CURR_BUFFER_LENGTH
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 50. Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions
Bit
Field
Value
Description
31-24 DESC_MSG
0-FFh
Descriptor Message
Byte which is passed from the SOP Tx Descriptor to the SOP Receive
descriptor. Used to tag packets.
23-18 Reserved
0
Reserved
17
16
CURR_BUFFER_EOP
0-1
Current Buffer is EOP
Flag indicating whether or not the current buffer that is being transmitted from is
the end of packet buffer
CURR_BUFFER_SOP
0-1
Current Buffer is SOP
Flag indicating whether or not the current buffer that is being transmitted from is
the start of packet buffer
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Table 50. Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions (continued)
Bit
Field
Value
Description
15-0 CURR_BUFFER_LENGTH
0-FFFFh
Current Buffer Length
Indicates how many valid bytes remain in the current buffer that is being
transmitted from
4.35 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5)
Figure 50. Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5)
31
16
REM_LENGTH
R/W-0
15
0
LENGTH
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 51. Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) Field Descriptions
Bit
Field
Value
Description
31-16 REM_LENGTH
0-FFFFh
Remaining Packet Length
Indicates how many bytes remain to be transmitted in the packet before truncation occurs
Packet Length
15-0
LENGTH
0-FFFFh
Indicates how many bytes are contained in the packet. This value is copied from the
packet-length field in Word 3 of the SOP Descriptor. This value is written into the AAL5 trailer
for the packet.
4.36 Transmit CPPI Completion Pointer (TCPPICOMPPTR)
Figure 51. Transmit CPPI Completion Pointer (TCPPICOMPPTR)
31
16
DESC_ADDR
R/W-0
15
2
1
0
DESC_ADDR
R/W-0
Reserved
R-0
WRBK_MODE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 52. Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions
Bit
Field
Value
0-3FFF FFFFh Descriptor Address
This field contains the 30-bit word aligned pointer of the end of packet descriptor that the
Description
31-2
DESC_ADDR
DMA has last processed
1
0
Reserved
0
Reserved
WRBK_MODE
Writeback/Compare Mode. This bit controls the action that is to be taken when this location
is written.
0
1
Compare Mode. Indicates that the value that is presented on bits 31:2 of the write data
should be compared against the value that is currently contained in bits 31:2 of this location.
If the two match, the interrupt bit corresponding to this Tx Queue should be deasserted.
Writeback Mode. Indicates that the value that is presented on bits 31:2 of the write data
should be written to this location and the interrupt for this Tx Queue should be asserted. This
bit is read as zero.
4.37 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0)
Figure 52. Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0)
31
15
16
Reserved
R-0
8
7
0
Reserved
R/W-0
SOP_BUFFER_OFFSET
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 53. Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) Field Descriptions
Bit
31-8 Reserved
7-0 SOP_BUFFER_OFFSET
Field
Value
0-7FFF FFh Reserved
0-FFh Start of Packet Buffer Offset
Description
Controls how many bytes the Receive DMA will skip at the beginning of the start
of packet buffer before beginning to fill the buffer with receive data. This field is
programmed by the Host software when the channel is set up to facilitate
addition of various protocol encapsulation headers for retransmission of received
packets.
4.38 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1)
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16
Figure 53. Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1)
31
RXQ_HEAD_PTR
R/W-0
15
2
1
0
RXQ_HEAD_PTR
R/W-0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 54. Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) Field Descriptions
Bit
Field
Value
0-1FFF FFFFh Receive Queue Head Pointer
30-bit pointer to 32-bit aligned descriptor at the head of the Receive queue
Reserved
Description
31-2 RXQ_HEAD_PTR
1-0
Reserved
0
106
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4.39 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2)
Figure 54. Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2)
31
15
16
SOP_DESCRIPTOR_PTR
R/W-0
2
1
0
SOP_DESCRIPTOR_PTR
R/W-0
Reserved
R-0
IN_PACKET
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 55. Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) Field Descriptions
Bit
Field
Value
0-1FFF FFFFh Start of Packet Buffer Descriptor Pointer
30-bit pointer to 32-bit aligned descriptor which is the first descriptor for the
Description
31-2 SOP_DESCRIPTOR_PTR
current packet
1
0
Reserved
0
Reserved
IN_PACKET
Flag indicating the DMA is in the middle of processing a packet 0: Not currently
in packet
0
1
Not currently in packet
Currently in packet
4.40 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3)
Figure 55. Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3)
31
15
16
CURR_DESCRIPTOR_PTR
R/W-0
1
0
CURR_DESCRIPTOR_PTR
R/W-0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 56. Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) Field Descriptions
Bit
Field
Value
0-3FFF FFFFh Current Buffer Descriptor Pointer
30-bit pointer to 32-bit aligned descriptor for buffer into which data is currently
Description
31-2 CURR_DESCRIPTOR_PTR
being received
1-0
Reserved
0
Reserved
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Registers
4.41 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4)
Figure 56. Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4)
31
0
CURR_BUFFER_PTR
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 57. Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) Field Descriptions
Bit
Field
Value
0-FFFF FFFFh Current Buffer Pointer
32-bit absolute byte address in buffer into which data is currently being received
Description
31-0 CURR_BUFFER_PTR
4.42 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5)
Figure 57. Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5)
31
16
PKT_LENGTH
R/W-0
15
0
CURR_BUFFER_LENGTH
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 58. Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) Field Descriptions
Bit
Field
Value
Description
31-16 PKT_LENGTH
0-FFFFh
Packet Length
Indicates how many bytes are contained in the packet. This value is written into
bits 15:0 of Word 3 of the SOP Descriptor during end of packet processing.
15-0 CURR_BUFFER_LENGTH
0-FFFFh
Current Buffer Length
Indicates how many free bytes remain in the current buffer that is being received
into
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4.43 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6)
Figure 58. Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6)
31
16
SOP_BUFFER_BYTECNT
R/W-0
15
0
CURR_BUFFER_BYTECNT
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 59. Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) Field Descriptions
Bit
Field
Value
Description
31-16 SOP_BUFFER_BYTECNT
0-FFFFh
Packet Length
Indicates how many bytes are contained in the packet. This value is written into
bits 15:0 of Word 3 of the SOP Descriptor during end of packet processing.
15-0 CURR_BUFFER_BYTECNT
0-FFFFh
Current Buffer Length
Indicates how many free bytes remain in the current buffer that is being received
into
4.44 Receive CPPI Completion Pointer (RCPPICOMPPTR)
Figure 59. Receive CPPI Completion Pointer (RCPPICOMPPTR)
31
16
DESC_ADDR
R/W-0
15
2
1
0
DESC_ADDR
R/W-0
Reserved
R-0
RDBK_MODE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 60. Receive CPPI Completion Pointer (RCPPICOMPPTR) Field Descriptions
Bit
Field
Value
0-7FFF FFFFh Descriptor Address
This field contains the 30-bit word aligned pointer of the end of packet descriptor that the
Description
31-2
DESC_ADDR
DMA has last processed.
1
Reserved
0
Reserved
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Table 60. Receive CPPI Completion Pointer (RCPPICOMPPTR) Field Descriptions (continued)
Bit
Field
Value
Description
0
RDBK_MODE
Readback / Compare Mode
0
Compare Mode. Indicates that the value that is presented on bits 31:2 of the read data
should be compared against the value that is currently contained in bits 31:2 of this location.
If the two match, the interrupt bit corresponding to this Receive Queue should be deasserted.
1
Readback Mode. Indicates that the value that is presented on bits 31:2 of the read data
should be read from this location and the interrupt for this Receive Queue should be
asserted. This bit is read as zero.
4.45 Function Address Register (FADDR)
Figure 60. Function Address Register (FADDR)
7
6
0
Reserved
R-0
FUNCADDR
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 61. Function Address Register (FADDR) Field Descriptions
Bit
7
Field
Value Description
Reserved
FUNCADDR
0
Reserved
6-0
0-7Fh 7-bit address of the peripheral part of the transaction
When used in Peripheral mode (DevCtl.D2=0), this register should be written with the address
received through a SET_ADDRESS command, which will then be used for decoding the function
address in subsequent token packets.
When used in Host mode (DevCtl.D2=1), this register should be set to the value sent in a
SET_ADDRESS command during device enumeration as the address for the peripheral device.
4.46 Power Management Register (POWER)
Figure 61. Power Management Register (POWER)
7
6
5
4
3
2
1
0
ISOUPDATE
R/W-0
SOFTCONN
R/W-0
HSEN
R/W-1
HSMODE
R-0
RESET
R/W-0
RESUME
R/W-0
SUSPENDM
R/W-0
ENSUSPM
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 62. Power Management Register (POWER) Field Descriptions
Bit
Field
Value Description
7
ISOUPDATE
0-1
When set, the USB controller will wait for an SOF token from the time TxPktRdy is set before
sending the packet. If an IN token is received before an SOF token, then a zero length data packet
will be sent. Note: This is only valid in Peripheral Mode. This bit only affects endpoints performing
Isochronous transfers.
6
5
4
SOFTCONN
HSEN
0-1
0-1
0-1
If Soft Connect/Disconnect feature is enabled, then the USB D+/D- lines are enabled when this bit
is set and tri-stated when this bit is cleared. Note: This is only valid in Peripheral Mode.
When set, the USB controller will negotiate for high-speed mode when the device is reset by the
hub. If not set, the device will only operate in full-speed mode.
HSMODE
This bit is set when the USB controller has successfully negotiated for high-speed mode.
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Table 62. Power Management Register (POWER) Field Descriptions (continued)
Bit
Field
Value Description
3
RESET
0-1
This bit is set when Reset signaling is present on the bus. Note: This bit is Read/Write in Host
Mode, but read-only in Peripheral Mode.
2
RESUME
0-1
Set to generate Resume signaling when the controller is in Suspend mode. The bit should be
cleared after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, this bit is also
automatically set when Resume signaling from the target is detected while the USB controller is
suspended.
1
0
SUSPENDM
ENSUSPM
0-1
0-1
In Host mode, this bit should be set to enter Suspend mode. In Peripheral mode, this bit is set on
entry into Suspend mode. It is cleared when the interrupt register is read, or the RESUME bit is set.
Set to enable the SUSPENDM output.
4.47 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)
The Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) is shown in Figure 62 and
Figure 62. Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX)
15
7
8
Reserved
R-0
5
4
3
2
1
0
Reserved
R-0
EP4TX
R-0
EP3TX
R-0
EP2TX
R-0
EP1TX
R-0
EP0
R-0
LEGEND: R = Read only; -n = value after reset
Table 63. Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)
Field Descriptions
Bit
15-5
4
Field
Value Description
Reserved
EP4TX
EP3TX
EP2TX
EP1TX
EP0
0
Reserved
0-1
0-1
0-1
0-1
0-1
Transmit Endpoint 4 interrupt active
Transmit Endpoint 3 interrupt active
Transmit Endpoint 2 interrupt active
Transmit Endpoint 1 interrupt active
Endpoint 0 interrupt active
3
2
1
0
4.48 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)
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Registers
Figure 63. Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)
16
Reserved
R-0
15
5
4
3
2
1
0
Reserved
R-0
EP4RX EP3RX EP2RX EP1RX
R-0 R-0 R-0 R-0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 64. Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions
Bit
15-5
4
Field
Value Description
Reserved
EP4RX
0
Reserved
0-1
0-1
0-1
0-1
0
Receive Endpoint 4 interrupt active
Receive Endpoint 3 interrupt active
Receive Endpoint 2 interrupt active
Receive Endpoint 1 interrupt active
Reserved
3
EP3RX
2
EP2RX
1
EP1RX
0
Reserved
4.49 Interrupt Enable Register for INTRTX (INTRTXE)
Figure 64. Interrupt Enable Register for INTRTX (INTRTXE)
15
7
8
Reserved
R-0
5
4
3
2
1
0
Reserved
R-0
EP4TX
R/W-1
EP3TX
R/W-1
EP2TX
R/W-1
EP1TX
R/W-1
EP0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 65. Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions
Bit
15-5
4
Field
Value Description
Reserved
EP4TX
EP3TX
EP2TX
EP1TX
EP0
0
Reserved
0-1
0-1
0-1
0-1
0-1
1/0 = Transmit Endpoint 4 interrupt enable/disable
1/0 = Transmit Endpoint 3 interrupt enable/disable
1/0 = Transmit Endpoint 2 interrupt enable/disable
1/0 = Transmit Endpoint 1 interrupt enable/disable
1/0 = Endpoint 0 interrupt enable/disable
3
2
1
0
4.50 Interrupt Enable Register for INTRRX (INTRRXE)
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Figure 65. Interrupt Enable Register for INTRRX (INTRRXE)
15
Reserved
R-0
7
5
4
3
2
1
0
Reserved
R-0
EP4RX
R/W-1
EP3RX
R/W-1
EP2RX
R/W-1
EP1RX
R/W-1
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 66. Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions
Bit
15-5
4
Field
Value Description
Reserved
EP4RX
EP3RX
EP2RX
EP1RX
Reserved
0
Reserved
0-1
0-1
0-1
0-1
0
1/0 = Receive Endpoint 4 interrupt enable/disable
1/0 = Receive Endpoint 3 interrupt enable/disable
1/0 = Receive Endpoint 2 interrupt enable/disable
1/0 = Receive Endpoint 1 interrupt enable/disable
Reserved
3
2
1
0
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4.51 Interrupt Register for Common USB Interrupts (INTRUSB)
Note: Unless the UINT bit of CTRLR is set, do not read or write this register directly. Use the
INTSRCR register instead.
Figure 66. Interrupt Register for Common USB Interrupts (INTRUSB)
7
6
5
4
3
2
RESET_BABBLE
R-0
1
0
VBUSERR
R-0
SESSREQ
R-0
DISCON
R-0
CONN
R-0
SOF
R-0
RESUME
R-0
SUSPEND
R-0
LEGEND: R = Read only; -n = value after reset
Table 67. Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions
Bit
Field
Value Description
7
VBUSERR
0-1
Set when VBus drops below the VBus valid threshold during a session. Only valid when the USB
controller is 'A' device. All active interrupts will be cleared when this register is read.
6
5
SESSREQ
DISCON
0-1
0-1
Set when session request signaling has been detected. Only valid when USB controller is 'A' device.
Set in host mode when a device disconnect is detected. Set in peripheral mode when a session
ends.
4
3
2
CONN
0-1
0-1
0-1
Set when a device connection is detected. Only valid in host mode.
Set when a new frame starts.
SOF
RESET_BABBLE
Set in peripheral mode when reset signaling is detected on the bus set in host mode when babble is
detected.
1
0
RESUME
0-1
0-1
Set when resume signaling is detected on the bus while the USB controller is in suspend mode.
Set when suspend signaling is detected on the bus only valid in peripheral mode.
SUSPEND
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4.52 Interrupt Enable Register for INTRUSB (INTRUSBE)
The Interrupt Enable Register for INTRUSB (INTRUSBE) is shown in Figure 67 and described in Table 68.
Note: Unless the UINT bit of CTRLR is set, do not read or write this register directly. Use the
INTMSKSETR/INTMSKCLRR registers instead.
Figure 67. Interrupt Enable Register for INTRUSB (INTRUSBE)
7
6
5
4
3
2
1
0
VBUSERR
R/W-0
SESSREQ
R/W-0
DISCON
R/W-0
CONN
R/W-0
SOF
R/W-0
RESET_BABBLE
R/W-1
RESUME
R/W-1
SUSPEND
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 68. Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions
Bit
7
Field
Value Description
VBUSERR
SESSREQ
DISCON
CONN
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
Vbus error interrupt enable
Session request interrupt enable
Disconnect interrupt enable
Connect interrupt enable
Start of frame interrupt enable
Reset interrupt enable
6
5
4
3
SOF
2
RESET_BABBLE
RESUME
SUSPEND
1
Resume interrupt enable
Suspend interrupt enable
0
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4.53 Frame Number Register (FRAME)
Figure 68. Frame Number Register (FRAME)
15
11
10
0
Reserved
R-0
FRAMENUMBER
R-0
LEGEND: R = Read only; -n = value after reset
Table 69. Frame Number Register (FRAME) Field Descriptions
Bit
15-11 Reserved
10-0 FRAMENUMBER
Field
Value Description
0
Reserved
0-7FFh Last received frame number
4.54 Index Register for Selecting the Endpoint Status and Control Registers (INDEX)
The Index Register for Selecting the Endpoint Status and Control Registers (INDEX) is shown in Figure 69
Figure 69. Index Register for Selecting the Endpoint Status and Control Registers (INDEX)
7
4
3
0
Reserved
R-0
EPSEL
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 70. Index Register for Selecting the Endpoint Status and Control Registers (INDEX)
Field Descriptions
Bit
7-4
3-0
Field
Value Description
Reserved
EPSEL
0
Reserved
0-Fh
Each transmit endpoint and each receive endpoint have their own set of control/status registers. EPSEL
determines which endpoint control/status registers are accessed.
Before accessing an endpoint's control/status registers, the endpoint number should be written to the
Index register to ensure that the correct control/status registers appear in the memory map.
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4.55 Register to Enable the USB 2.0 Test Modes (TESTMODE)
Figure 70. Register to Enable the USB 2.0 Test Modes (TESTMODE)
7
6
5
4
3
2
1
0
FORCE_HOST
R/W-0
FIFO_ACCESS
W-0
FORCE_FS FORCE_HS TEST_PACKET
R/W-0 R/W-0 R/W-0
TEST_K
R/W-0
TEST_J
R/W-0
TEST_SE0_NAK
R/W-0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 71. Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions
Bit
Field
Value
Description
7
FORCE_HOST
0-1
Set this bit to forcibly put the USB controller into Host mode when SESSION bit is set,
regardless of whether it is connected to any peripheral. The controller remains in Host mode
until the Session bit is cleared, even if a device is disconnected. And if the FORCE_HOST but
remains set, it will re-enter Host mode next time the SESSION bit is set. The operating speed is
determined using the FORCE_HS and FORCE_FS bits.
6
FIFO_ACCESS
0-1
Set this bit to transfer the packet in EP0 Tx FIFO to EP0 Receive FIFO. It is cleared
automatically.
5
4
3
FORCE_FS
0-1
0-1
0-1
Set this bit to force the USB controller into full-speed mode when it receives a USB reset.
Set this bit to force the USB controller into high-speed mode when it receives a USB reset.
FORCE_HS
TEST_PACKET
Set this bit to enter the Test_Packet test mode. In this mode, the USB controller repetitively
transmits a 53-byte test packet on the bus, the form of which is defined in the Universal Serial
Bus Specification Revision 2.0.
Note: The test packet has a fixed format and must be loaded into the Endpoint 0 FIFO before
the test mode is entered.
2
1
0
TEST_K
0-1
0-1
0-1
Set this bit to enter the Test_K test mode. In this mode, the USB controller transmits a
continuous K on the bus.
TEST_J
Set this bit to enter the Test_J test mode. In this mode, the USB controller transmits a
continuous J on the bus.
TEST_SE0_NAK
Set this bit to enter the Test_SE0_NAK test mode. In this mode, the USB controller remains in
high-speed mode, but responds to any valid IN token with a NAK.
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4.56 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)
Figure 71. Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)
15
11
10
0
Reserved
R-0
MAXPAYLOAD
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 72. Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)
Field Descriptions
Bit
Field
Value Description
15-11 Reserved
0
Reserved
10-0
MAXPAYLOAD
0-FFh The maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes,
but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt,
and Isochronous transfers in full-speed and high-speed operations. The value written to this register
should match the wMaxPacketSize field of the Standard Endpoint Descriptor for the associated
endpoint. A mismatch could cause unexpected results.
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4.57 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)
Figure 72. Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)
15
9
8
Reserved
R-0
FLUSHFIFO
W-0
7
6
5
4
3
2
1
0
SERV_SETUPEND SERV_RXPKTRDY
SENDSTALL
W-0
SETUPEND
DATAEND
W-0
SENTSTALL
R/W-0
TXPKTRDY
R/W-0
RXPKTRDY
R-0
W-0
W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 73. Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)
Field Descriptions
Bit
15-9
8
Field
Value Description
Reserved
FLUSHFIFO
0
Reserved
0-1
Set this bit to flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO
pointer is reset and the TXPKTRDY/RXPKTRDY bit is cleared.
Note: FLUSHFIFO has no effect unless TXPKTRDY/RXPKTRDY is set.
Set this bit to clear the SETUPEND bit. It is cleared automatically.
Set this bit to clear the RXPKTRDY bit. It is cleared automatically.
7
6
5
SERV_SETUPEND
SERV_RXPKTRDY
SENDSTALL
0-1
0-1
0-1
Set this bit to terminate the current transaction. The STALL handshake will be transmitted and
then this bit will be cleared automatically.
4
3
SETUPEND
DATAEND
0-1
0-1
This bit will be set when a control transaction ends before the DATAEND bit has been set. An
interrupt will be generated, and the FIFO will be flushed at this time. The bit is cleared by the
writing a 1 to the SERV_SETUPEND bit.
Set this bit to:
1 - When setting TXPKTRDY for the last data packet
2 - When clearing RXPKTRDY after unloading the last data packet
3 - When setting TXPKTRDY for a zero length data packet. It is cleared automatically.
This bit is set when a STALL handshake is transmitted. This bit should be cleared.
2
1
SENTSTALL
TXPKTRDY
0-1
0-1
Set this bit after loading a data packet into the FIFO. It is cleared automatically when the data
packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared.
0
RXPKTRDY
0-1
This bit is set when a data packet has been received. An interrupt is generated when this bit is set.
This bit is cleared by setting the SERV_RXPKTRDY bit.
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4.58 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0)
Figure 73. Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0)
15
11
10
DATATOGWREN
W-0
9
8
Reserved
R-0
DATATOG
R/W-0
FLUSHFIFO
W-0
7
6
5
4
3
2
1
0
NAK_TIMEOUT
W-0
STATUSPKT
R/W-0
REQPKT
R/W-0
ERROR
W-0
SETUPPKT
R/W-0
RXSTALL
R/W-0
TXPKTRDY
R/W-0
RXPKTRDY
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 74. Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions
Bit
Field
Value Description
15-11 Reserved
0
Reserved
10
9
DATATOGWREN
0-1
Set this bit to enable the DATATOG bit to be written. This bit is automatically cleared once the new
value is written to DATATOG.
DATATOG
0-1
0-1
When read, this bit indicates the current state of the EP0 data toggle. If DATATOGWREN is high,
this bit can be written with the required setting of the data toggle. If DATATOGWREN is low, any
value written to this bit is ignored.
8
FLUSHFIFO
Set this bit to flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO
pointer is reset and the TXPKTRDY/RXPKTRDY bit is cleared.
Note: FLUSHFIFO has no effect unless TXPKTRDY/RXPKTRDY is set.
7
6
NAK_TIMEOUT
STATUSPKT
0-1
0-1
This bit will be set when Endpoint 0 is halted following the receipt of NAK responses for longer than
the time set by the NAKLIMIT0 register. This bit should be cleared to allow the endpoint to
continue.
Set this bit at the same time as the TXPKTRDY or REQPKT bit is set, to perform a status stage
transaction. Setting this bit ensures that the data toggle is set so that a DATA1 packet is used for
the Status Stage transaction.
5
4
REQPKT
ERROR
0-1
0-1
Set this bit to request an IN transaction. It is cleared when RXPKTRDY is set.
This bit will be set when three attempts have been made to perform a transaction with no response
from the peripheral. You should clear this bit. An interrupt is generated when this bit is set.
3
SETUPPKT
0-1
Set this bit, at the same time as the TXPKTRDY bit is set, to send a SETUP token instead of an
OUT token for the transaction.
2
1
RXSTALL
0-1
0-1
This bit is set when a STALL handshake is received. You should clear this bit.
TXPKTRDY
Set this bit after loading a data packet into the FIFO. It is cleared automatically when the data
packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared.
0
RXPKTRDY
0-1
This bit is set when a data packet has been received. An interrupt is generated when this bit is set.
Clear this bit by setting the SERV_RXPKTRDY bit.
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4.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
Figure 74. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
15
Reserved
R-0
14
13
12
11
10
9
7
ISO
MODE
R/W-0
DMAEN
R/W-0
FRCDATATOG
R/W-0
DMAMODE
R/W-0
Reserved
R-0
R/W-0
6
5
4
3
2
1
0
CLRDATATOG
W-0
SENTSTALL
R/W-0
SENDSTALL
R/W-0
FLUSHFIFO
W-0
UNDERRUN
R/W-0
FIFONOTEMPTY
R/W-0
TXPKTRDY
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 75. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
Field Descriptions
Bit
15
14
Field
Value Description
Reserved
ISO
0
Reserved
0-1
Set this bit to enable the Tx endpoint for Isochronous transfers, and clear this bit to enable the Tx
endpoint for Bulk or Interrupt transfers.
13
MODE
0-1
Set this bit to enable the endpoint direction as Tx, and clear this bit to enable it as Rx.
Note: This bit has any effect only where the same endpoint FIFO is used for both Transmit and
Receive transactions.
12
11
DMAEN
0-1
0-1
Set this bit to enable the DMA request for the Tx endpoint.
FRCDATATOG
Set this bit to force the endpoint data toggle to switch and the data packet to be cleared from the
FIFO, regardless of whether an ACK was received. This can be used by Interrupt Tx endpoints
that are used to communicate rate feedback for Isochronous endpoints.
10
DMAMODE
0-1
When using DMA, clear this bit to receive an interrupt for each packet, or set this bit to only
receive error interrupts.
9-7
6
Reserved
0
Reserved
CLRDATATOG
SENTSTALL
0-1
0-1
Set this bit to reset the endpoint data toggle to 0.
5
This bit is set automatically when a STALL handshake is transmitted. The FIFO is flushed and the
TXPKTRDY bit is cleared. You should clear this bit.
4
3
SENDSTALL
FLUSHFIFO
0-1
0-1
Set this bit to issue a STALL handshake to an IN token. Clear this bit to terminate the stall
condition.
Note: This bit has no effect where the endpoint is being used for Isochronous transfers.
Set this bit to flush the next packet to be transmitted from the endpoint Tx FIFO. The FIFO pointer
is reset and the TXPKTRDY bit is cleared.
Note: FlushFIFO has no effect unless TXPKTRDY is set. Also note that, if the FIFO is
double-buffered, FlushFIFO may need to be set twice to completely clear the FIFO.
2
UNDERRUN
0-1
This bit is set automatically if an IN token is received when TXPKTRDY is not set. You should
clear this bit.
1
0
FIFONOTEMPTY
TXPKTRDY
0-1
0-1
This bit is set when there is at least 1 packet in the Tx FIFO. You should clear this bit.
Set this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet
has been transmitted. An interrupt is generated (if enabled) when the bit is cleared.
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4.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR)
Figure 75. Control Status Register for Host Transmit Endpoint (HOST_TXCSR)
15
14
13
12
11
10
9
8
Reserved
R-0
MODE
R/W-0
DMAEN
R/W-0
FRCDATATOG
R/W-0
DMAMODE
R/W-0
DATATOGWREN
W-0
DATATOG
R/W-0
7
6
5
4
3
2
1
0
NAK_TIMEOUT
R/W-0
CLRDATATOG
W-0
RXSTALL
R/W-0
SETUPPKT
R/W-0
FLUSHFIFO
W-0
ERROR
R/W-0
FIFONOTEMPTY
R/W-0
TXPKTRDY
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 76. Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions
Bit
Field
Value Description
15-14 Reserved
0
Reserved
13
MODE
0-1
Set this bit to enable the endpoint direction as Tx, and clear this bit to enable it as Rx.
Note: This bit has any effect only where the same endpoint FIFO is used for both Transmit and
Receive transactions.
12
11
DMAEN
0-1
0-1
Set this bit to enable the DMA request for the Tx endpoint.
FRCDATATOG
Set this bit to force the endpoint data toggle to switch and the data packet to be cleared from the
FIFO, regardless of whether an ACK was received. This can be used by Interrupt Tx endpoints that
are used to communicate rate feedback for Isochronous endpoints.
10
9
DMAMODE
0-1
0-1
0-1
When using DMA, clear this bit to receive an interrupt for each packet, or set this bit to only receive
error interrupts.
DATATOGWREN
DATATOG
Set this bit to enable the DATATOG bit to be written. This bit is automatically cleared once the new
value is written to DATATOG.
8
When read, this bit indicates the current state of the Tx EP data toggle. If DATATOGWREN is high,
this bit can be written with the required setting of the data toggle. If DATATOGWREN is low, any
value written to this bit is ignored.
7
NAK_TIMEOUT
0-1
This bit will be set when the Tx endpoint is halted following the receipt of NAK responses for longer
than the time set as the NAKLIMIT by the TXINTERVAL register. It should be cleared to allow the
endpoint to continue.
Note: This is valid only for Bulk endpoints.
6
5
CLRDATATOG
RXSTALL
0-1
0-1
Set this bit to reset the endpoint data toggle to 0.
This bit is set when a STALL handshake is received. The FIFO is flushed and the TXPKTRDY bit is
cleared. You should clear this bit.
4
3
SETUPPKT
FLUSHFIFO
0-1
0-1
Set this bit at the same time as TXPKTRDY is set, to send a SETUP token instead of an OUT
token for the transaction.
Note: Setting this bit also clears the DATATOG bit.
Set this bit to flush the next packet to be transmitted from the endpoint Tx FIFO. The FIFO pointer
is reset and the TXPKTRDY bit is cleared.
Note: FlushFIFO has no effect unless TXPKTRDY is set. Also note that, if the FIFO is
double-buffered, FLUSHFIFO may need to be set twice to completely clear the FIFO.
2
ERROR
0-1
The USB controller sets this bit when 3 attempts have been made to send a packet and no
handshake packet has been received. You should clear this bit. An interrupt is generated when the
bit is set. This is valid only when the endpoint is operating in Bulk or Interrupt mode.
1
0
FIFONOTEMPTY
TXPKTRDY
0-1
0-1
The USB controller sets this bit when there is at least 1 packet in the Tx FIFO.
Set this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet
has been transmitted. An interrupt is generated (if enabled) when the bit is cleared.
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4.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)
Figure 76. Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)
15
11
10
0
Reserved
R-0
MAXPAYLOAD
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 77. Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions
Bit
15-11 Reserved
10-0 MAXPAYLOAD
Field
Value Description
Reserved
0
0-FFh Defines the maximum amount of data that can be transferred through the selected Receive
endpoint in a single frame/microframe (high-speed transfers). The value set can be up to 1024
bytes, but is subject to the constraints placed by the USB Specification on packet sizes for Bulk,
Interrupt, and Isochronous transfers in full-speed and high-speed operations. The value written to
this register should match the wMaxPacketSize field of the Standard Endpoint Descriptor for the
associated endpoint. A mismatch could cause unexpected results.
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4.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)
Figure 77. Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)
15
Reserved
R-0
14
13
12
11
10
8
ISO
DMAEN
R/W-0
DISNYET
R/W-0
DMAMODE
R/W-0
Reserved
R-0
R/W-0
7
6
5
4
3
2
1
0
CLRDATATOG
W-0
SENTSTALL
R/W-0
SENDSTALL
R/W-0
FLUSHFIFO
W-0
DATAERROR
R-0
OVERRUN
R/W-0
FIFOFULL
R-0
RXPKTRDY
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 78. Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)
Field Descriptions
Bit
15
14
Field
Value Description
Reserved
ISO
0
Reserved
0-1
Set this bit to enable the Receive endpoint for Isochronous transfers, and clear this bit to enable the
Receive endpoint for Bulk/Interrupt transfers.
13
12
DMAEN
0-1
0-1
Set this bit to enable the DMA request for the Receive endpoints.
DISNYET
Set this bit to disable the sending of NYET handshakes. When set, all successfully received
Receive packets are ACKed, including at the point at which the FIFO becomes full.
Note: This bit only has any effect in high-speed mode, in which mode it should be set for all
Interrupt endpoints.
11
10-8
7
DMAMODE
Reserved
0
This bit should always be cleared to 0.
Reserved
0
CLRDATATOG
SENTSTALL
0-1
0-1
Set this bit to reset the endpoint data toggle to 0.
6
This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TXPKTRDY bit
is cleared. You should clear this bit.
5
4
SENDSTALL
FLUSHFIFO
0-1
0-1
Set this bit to issue a STALL handshake. Clear this bit to terminate the stall condition.
Note: This bit has no effect where the endpoint is being used for Isochronous transfers.
Set this bit to flush the next packet to be read from the endpoint Receive FIFO. The FIFO pointer is
reset and the RXPKTRDY bit is cleared.
Note: FLUSHFIFO has no effect unless RXPKTRDY is set. Also note that, if the FIFO is
double-buffered, FLUSHFIFO may need to be set twice to completely clear the FIFO.
3
2
DATAERROR
OVERRUN
0-1
0-1
This bit is set when RXPKTRDY is set if the data packet has a CRC or bit-stuff error. It is cleared
when RXPKTRDY is cleared.
Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always
returns zero.
This bit is set if an OUT packet cannot be loaded into the Receive FIFO. You should clear this bit.
Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always
returns zero.
1
0
FIFOFULL
0-1
0-1
This bit is set when no more packets can be loaded into the Receive FIFO.
RXPKTRDY
This bit is set when a data packet has been received. You should clear this bit when the packet has
been unloaded from the Receive FIFO. An interrupt is generated when the bit is set.
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4.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR)
Figure 78. Control Status Register for Host Receive Endpoint (HOST_RXCSR)
15
14
13
12
11
10
DATATOGWREN
W-0
9
8
Reserved
R-0
DMAEN
R/W-0
DISNYET
R/W-0
DMAMODE
R/W-0
DATATOG
R/W-0
Reserved
R-0
7
6
5
4
3
2
1
0
CLRDATATOG
W-0
RXSTALL
REQPKT
FLUSHFIFO
DATAERR_NAK
TIMEOUT
ERROR
FIFOFULL
RXPKTRDY
R/W-0
R/W-0
W-0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 79. Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions
Bit
Field
Value Description
15-14 Reserved
0
Reserved
13
12
DMAEN
0-1
0-1
Set this bit to enable the DMA request for the Receive endpoints.
DISNYET
Set this bit to disable the sending of NYET handshakes. When set, all successfully received
Receive packets are ACKED including at the point at which the FIFO becomes full.
Note: This bit only has any effect in high-speed mode, in which mode it should be set for all
Interrupt endpoints.
11
10
DMAMODE
0
This bit should always be cleared to 0.
DATATOGWREN
0-1
Set this bit to enable the DATATOG bit to be written. This bit is automatically cleared once
the new value is written to DATATOG.
9
DATATOG
0-1
When read, this bit indicates the current state of the Receive EP data toggle. If
DATATOGWREN is high, this bit can be written with the required setting of the data toggle.
If DATATOGWREN is low, any value written to this bit is ignored.
8
7
6
Reserved
0
Reserved
CLRDATATOG
RXSTALL
0-1
0-1
Set this bit to reset the endpoint data toggle to 0.
When a STALL handshake is received, this bit is set and an interrupt is generated. You
should clear this bit.
5
4
REQPKT
0-1
0-1
Set this bit to request an IN transaction. It is cleared when RXPKTRDY is set.
FLUSHFIFO
Set this bit to flush the next packet to be read from the endpoint Receive FIFO. The FIFO
pointer is reset and the RXPKTRDY bit is cleared.
Note: FLUSHFIFO has no effect unless RXPKTRDY is set. Also note that, if the FIFO is
double-buffered, FLUSHFIFO may need to be set twice to completely clear the FIFO.
3
2
DATAERR_NAKTIMEOUT
ERROR
0-1
0-1
When operating in ISO mode, this bit is set when RXPKTRDY is set if the data packet has
a CRC or bit-stuff error and cleared when RXPKTRDY is cleared. In Bulk mode, this bit will
be set when the Receive endpoint is halted following the receipt of NAK responses for
longer than the time set as the NAK Limit by the RXINTERVAL register. You should clear
this bit to allow the endpoint to continue.
The USB controller sets this bit when 3 attempts have been made to receive a packet and
no data packet has been received. You should clear this bit. An interrupt is generated when
the bit is set.
Note: This bit is only valid when the transmit endpoint is operating in Bulk or Interrupt
mode. In ISO mode, it always returns zero.
1
0
FIFOFULL
0-1
0-1
This bit is set when no more packets can be loaded into the Receive FIFO.
RXPKTRDY
This bit is set when a data packet has been received. You should clear this bit when the
packet has been unloaded from the Receive FIFO. An interrupt is generated when the bit is
set.
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4.64 Count 0 Register (COUNT0)
Figure 79. Count 0 Register (COUNT0)
15
7
6
0
Reserved
R-0
EP0RXCOUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 80. Count 0 Register (COUNT0) Field Descriptions
Bit
15-7
6-0
Field
Value Description
Reserved
Reserved
EP0RXCOUNT
0
0-7Fh Indicates the number of received data bytes in the Endpoint 0 FIFO. The value returned changes as
the contents of the FIFO change and is only valid while RXPKTRDY of PERI_CSR0 or
HOST_CSR0 is set.
4.65 Receive Count Register (RXCOUNT)
Figure 80. Receive Count Register (RXCOUNT)
15
13
12
0
Reserved
R-0
EPRXCOUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 81. Receive Count Register (RXCOUNT) Field Descriptions
Bit
15-13 Reserved
12-0 EPRXCOUNT
Field
Value
0
Description
Reserved
0-1FFFh
Holds the number of received data bytes in the packet in the Receive FIFO. The value
returned changes as the contents of the FIFO change and is only valid while RXPKTRDY of
PERI_RXCSR or HOST_RXCSR is set.
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4.66 Type Register (Host mode only) (HOST_TYPE0)
Figure 81. Type Register (Host mode only) (HOST_TYPE0)
7
6
5
0
SPEED
R/W-0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 82. Type Register (Host mode only) (HOST_TYPE0) Field Descriptions
Bit
Field
Value Description
7-6
SPEED
0-3h
0
Operating Speed of Target Device
Illegal
High
1h
2h
3h
0
Full
Low
5-0
Reserved
Reserved
4.67 Transmit Type Register (Host mode only) (HOST_TXTYPE)
Figure 82. Transmit Type Register (Host mode only) (HOST_TXTYPE)
7
6
5
4
3
0
SPEED
R/W-0
PROT
R/W-0
TENDPN
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 83. Transmit Type Register (Host mode only) (HOST_TXTYPE) Field Descriptions
Bit
Field
Value Description
7-6
SPEED
0-3h
0
Operating Speed of Target Device
Illegal
1h
High
2h
Full
3h
Low
5-4
3-0
PROT
0-3h
0
Set this to select the required protocol for the transmit endpoint
Control
1h
Isochronous
Bulk
2h
3h
Interrupt
TENDPN
0-Fh
Set this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB
controller during device enumeration.
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4.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0)
Figure 83. NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0)
7
5
4
0
Reserved
R-0
EP0NAKLIMIT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 84. NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Field Descriptions
Bit
7-5
4-0
Field
Value Description
Reserved
0
Reserved
EP0NAKLIMIT
0-1Fh Sets the number of frames/microframes (high-speed transfers) after which Endpoint 0 should time
out on receiving a stream of NAK responses. The number of frames/microframes selected is 2(—1)
(where m is the value set in the register, valid values 2-16). If the host receives NAK responses
from the target for more frames than the number represented by the Limit set in this register, the
endpoint will be halted.
Note: A value of 0 or 1 disables the NAK timeout function.
4.69 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL)
Figure 84. Transmit Interval Register (Host mode only) (HOST_TXINTERVAL)
7
0
POLINTVL_NAKLIMIT
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 85. Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Field Descriptions
Bit
Field
Value Description
7-0
POLINTVL_NAKLIMIT
0-FFh For Interrupt and Isochronous transfers, defines the polling interval for the
currently-selected transmit endpoint. For Bulk endpoints, this register sets the number of
frames/microframes after which the endpoint should timeout on receiving a stream of NAK
responses There is a transmit Interval register for each configured transmit endpoint
(except Endpoint 0). In each case the value that is set defines a number of
frames/microframes (High Speed transfers), as follows:
Transfer Type Speed Valid values (m) Interpretation
Interrupt Low Speed or Full Speed 1 - 255 Polling interval is m frames
High Speed 1 - 16 Polling interval is 2(—1) microframes
Isochronous Full Speed or High Speed 1 - 16 Polling interval is 2(—1) frames/microframes
Bulk Full Speed or High Speed 2 - 16 NAK Limit is 2(—1) frames/microframes
Note: A value of 0 or 1 disables the NAK timeout function.
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4.70 Receive Type Register (Host mode only) (HOST_RXTYPE)
Figure 85. Receive Type Register (Host mode only) (HOST_RXTYPE)
7
6
5
4
3
0
SPEED
R/W-0
PROT
R/W-0
RENDPN
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 86. Receive Type Register (Host mode only) (HOST_RXTYPE) Field Descriptions
Bit
Field
Value Description
7-6
SPEED
0-3h
0
Operating Speed of Target Device
Illegal
1h
High
2h
Full
3h
Low
5-4
3-0
PROT
0-3h
0
Set this to select the required protocol for the transmit endpoint
Control
1h
Isochronous
Bulk
2h
3h
Interrupt
RENDPN
0-Fh
Set this value to the endpoint number contained in the Receive endpoint descriptor returned to the USB
controller during device enumeration
4.71 Receive Interval Register (Host mode only) (HOST_RXINTERVAL)
Figure 86. Receive Interval Register (Host mode only) (HOST_RXINTERVAL)
7
0
POLINTVL_NAKLIMIT
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
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Table 87. Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions
Bit
Field
Value Description
7-0
POLINTVL_NAKLIMIT
0-FFh For Interrupt and Isochronous transfers, defines the polling interval for the
currently-selected transmit endpoint For Bulk endpoints, this register sets the number of
frames/microframes after which the endpoint should timeout on receiving a stream of NAK
responses. There is a transmit Interval register for each configured transmit endpoint
(except Endpoint 0). In each case the value that is set defines a number of
frames/microframes (High Speed transfers), as follows:
Transfer Type Speed Valid values (m) Interpretation
Interrupt Low Speed or Full Speed 1 - 255 Polling interval is m frames
High Speed 1 - 16 Polling interval is 2(—1) microframes
Isochronous Full Speed or High Speed 1 - 16 Polling interval is 2(—1) frames/microframes
Bulk Full Speed or High Speed 2 - 16 NAK Limit is 2(—1) frames/microframes
Note: A value of 0 or 1 disables the NAK timeout function
4.72 Configuration Data Register (CONFIGDATA)
Figure 87. Configuration Data Register (CONFIGDATA)
7
6
5
4
3
2
1
0
UTMIDATAWIDTH
R-0
MPRXE
R-0
MPTXE
R-0
BIGENDIAN
R-0
HBRXE
R-0
HBTXE
R-0
DYNFIFO
R-1
SOFTCONE
R-1
LEGEND: R = Read only; -n = value after reset
Table 88. Configuration Data Register (CONFIGDATA) Field Descriptions
Bit
Field
Value Description
7
MPRXE
Indicates automatic amalgamation of bulk packets.
0
1
Automatic amalgamation of bulk packets is not selected.
Automatic amalgamation of bulk packets is selected.
Indicates automatic splitting of bulk packets.
Automatic splitting of bulk packets is not selected.
Automatic splitting of bulk packets is selected.
Indicates endian ordering.
6
5
4
3
2
1
0
MPTXE
0
1
BIGENDIAN
HBRXE
0
1
Little-endian ordering is selected.
Big-endian ordering is selected.
Indicates high-bandwidth Rx ISO endpoint support.
High-bandwidth Rx ISO endpoint support is not selected.
High-bandwidth Rx ISO endpoint support is selected.
Indicates high-bandwidth Tx ISO endpoint support.
High-bandwidth Tx ISO endpoint support is not selected.
High-bandwidth Tx ISO endpoint support is selected.
Indicates dynamic FIFO sizing.
0
1
HBTXE
0
1
DYNFIFO
0
1
Dynamic FIFO sizing option is not selected.
Dynamic FIFO sizing option is selected.
Indicates soft connect/disconnect.
SOFTCONE
UTMIDATAWIDTH
0
1
Soft connect/disconnect option is not selected
Soft connect/disconnect option is selected
Indicates selected UTMI data width.
0
1
8 bits
16 bits
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4.73 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)
The Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) is shown in Figure 88 and described in
Figure 88. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)
31
0
DATA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 89. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions
Bit
Field
Value
Description
31-0
DATA
0-FFFF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint.
Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.
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4.74 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)
The Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) is shown in Figure 89 and described in
Figure 89. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)
31
0
DATA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 90. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions
Bit
Field
Value
Description
31-0
DATA
0-FFFF FFFF
Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint.
Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.
4.75 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)
The Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) is shown in Figure 90 and described in
Figure 90. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)
31
0
DATA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 91. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions
Bit
Field
Value
Description
31-0
DATA
0-FFFF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint.
Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.
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4.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)
The Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) is shown in Figure 91 and described in
Figure 91. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)
31
0
DATA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 92. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions
Bit
Field
Value
Description
31-0
DATA
0-FFFF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint.
Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.
4.77 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)
The Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) is shown in Figure 92 and described in
Figure 92. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)
31
0
DATA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 93. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions
Bit
Field
Value
Description
31-0
DATA
0-FFFF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint.
Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.
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4.78 OTG Device Control Register (DEVCTL)
Figure 93. OTG Device Control Register (DEVCTL)
7
6
5
4
3
2
1
0
BDEVICE
R-0
FSDEV
R-0
LSDEV
R-0
VBUS
R-0
HOSTMODE
R-0
HOSTREQ
R/W-0
SESSION
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 94. OTG Device Control Register (DEVCTL) Field Descriptions
Bit
Field
Value Description
7
BDEVICE
This read-only bit indicates whether the USB controller is operating as the 'A' device or the 'B'
device.
0
1
'A' device
'B' device
Only valid while a session is in progress.
6
FSDEV
0-1
0-1
This read-only bit is set when a full-speed or high-speed device has been detected being connected
to the port (high-speed devices are distinguished from full-speed by checking for high-speed chirps
when the device is reset). Only valid in Host mode.
5
LSDEV
VBUS
This read-only bit is set when a low-speed device has been detected being connected to the port.
Only valid in Host mode.
4-3
0-3h
0
These read-only bits encode the current VBus level as follows:
Below Session End
1h
Above Session End, below AValid
2h
Above AValid, below VBusValid
3h
Above VBusValid
2
1
HOSTMODE
HOSTREQ
0-1
0-1
This read-only bit is set when the USB controller is acting as a Host.
When set, the USB controller will initiate the Host Negotiation when Suspend mode is entered. It is
cleared when Host Negotiation is completed. ('B' device only)
0
SESSION
0-1
When operating as an 'A' device, you must set or clear this bit start or end a session. When
operating as a 'B' device, this bit is set/cleared by the USB controller when a session starts/ends.
You must also set this bit to initiate the Session Request Protocol. When the USB controller is in
Suspend mode, you may clear the bit to perform a software disconnect.
A special software routine is required to perform SRP. Details will be made available in a later
document version.
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4.79 Transmit Endpoint FIFO Size (TXFIFOSZ)
Figure 94. Transmit Endpoint FIFO Size (TXFIFOSZ)
7
5
4
3
0
Reserved
R-0
DPB
R/W-0
SZ
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 95. Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions
Bit
7-5
4
Field
Value Description
Reserved
DPB
0
Reserved
Double packet buffering enable
Single packet buffering is supported
Double packet buffering is enabled
0
1
3-0
SZ
0-Fh
Maximum packet size to be allowed (before any splitting within the FIFO of Bulk packets prior to
transmission). If m = SZ[3:0], the FIFO size is calculated as 2(m+3) for single packet buffering and 2(m+4)
for dual packet buffering.
4.80 Receive Endpoint FIFO Size (RXFIFOSZ)
Figure 95. Receive Endpoint FIFO Size (RXFIFOSZ)
7
5
4
3
0
Reserved
R-0
DPB
R/W-0
SZ
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 96. Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions
Bit
7-5
4
Field
Value Description
Reserved
DPB
0
Reserved
Double packet buffering enable
Single packet buffering is supported
Double packet buffering is enabled
0
1
3-0
SZ
0-Fh
Maximum packet size to be allowed (before any splitting within the FIFO of Bulk packets prior to
transmission). If m = SZ[3:0], the FIFO size is calculated as 2(m+3) for single packet buffering and 2(m+4)
for dual packet buffering.
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4.81 Transmit Endpoint FIFO Address (TXFIFOADDR)
Figure 96. Transmit Endpoint FIFO Address (TXFIFOADDR)
15
13
12
0
Reserved
R-0
ADDR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 97. Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions
Bit
15-13 Reserved
12-0 ADDR
Field
Value
0
Description
Reserved
0-1FFFh
Start Address of endpoint FIFO in units of 8 bytes
If m = ADDR[12:0] then the start address is 8*m
4.82 Receive Endpoint FIFO Address (RXFIFOADDR)
Figure 97. Receive Endpoint FIFO Address (RXFIFOADDR)
15
13
12
0
Reserved
R-0
ADDR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 98. Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions
Bit
15-13 Reserved
12-0 ADDR
Field
Value
0
Description
Reserved
0-1FFFh
Start Address of endpoint FIFO in units of 8 bytes
If m = ADDR[12:0], then the start address is 8*m
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4.83 Transmit Function Address (TXFUNCADDR)
Figure 98. Transmit Function Address (TXFUNCADDR)
7
6
0
Reserved
R-0
FUNCADDR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 99. Transmit Function Address (TXFUNCADDR) Field Descriptions
Bit
7
Field
Value Description
Reserved
FUNCADDR
0
Reserved
6-0
0-7Fh Address of target function
4.84 Transmit Hub Address (TXHUBADDR)
Figure 99. Transmit Hub Address (TXHUBADDR)
7
6
0
MULT_TRANS
R/W-0
HUBADDR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 100. Transmit Hub Address (TXHUBADDR) Field Descriptions
Bit
Field
Value Description
7
MULT_TRANS
0-1
Set to 1 if hub has multiple transaction translators. Cleared to 0 if only single transaction translator
is available.
6-0
HUBADDR
0-7Fh Address of hub
4.85 Transmit Hub Port (TXHUBPORT)
Figure 100. Transmit Hub Port (TXHUBPORT)
7
6
0
Reserved
R-0
HUBPORT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 101. Transmit Hub Port (TXHUBPORT) Field Descriptions
Bit
7
Field
Value Description
Reserved
HUBPORT
0
Reserved
6-0
0-7Fh Port number of the hub
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4.86 Receive Function Address (RXFUNCADDR)
Figure 101. Receive Function Address (RXFUNCADDR)
7
6
0
Reserved
R-0
FUNCADDR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 102. Receive Function Address (RXFUNCADDR) Field Descriptions
Bit
7
Field
Value Description
Reserved
FUNCADDR
0
Reserved
6-0
0-7Fh Address of target function
4.87 Receive Hub Address (RXHUBADDR)
Figure 102. Receive Hub Address (RXHUBADDR)
7
6
0
MULT_TRANS
R/W-0
HUBADDR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 103. Receive Hub Address (RXHUBADDR) Field Descriptions
Bit
Field
Value Description
7
MULT_TRANS
0-1
Set to 1 if hub has multiple transaction translators. Cleared to 0 if only single transaction translator
is available.
6-0
HUBADDR
0-7Fh Address of hub
4.88 Receive Hub Port (RXHUBPORT)
Figure 103. Receive Hub Port (RXHUBPORT)
7
6
0
Reserved
R-0
HUBPORT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 104. Receive Hub Port (RXHUBPORT) Field Descriptions
Bit
7
Field
Value Description
Reserved
HUBPORT
0
Reserved
6-0
0-7Fh Port number of hub
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Appendix A
Appendix A Revision History
Table A-1. Document Revision History
Reference
Section 1
Additions/Modifications/Deletions
Added note.
Section 1.3
Added section.
Section 2.4
Changed section.
Section 3.1.1
Section 3.1.2.1
Section 3.1.2.2
Section 3.2.1
Section 3.2.2.1
Section 3.2.3
Section 3.2.4.1
Section 3.2.4.2
Section 3.3.1.2
Section 3.3.1.3
Section 3.3.1.4
Section 3.3.1.4
Figure 14
Renamed section.
Renamed section.
Renamed section.
Renamed section.
Renamed section.
Renamed section.
Renamed section.
Renamed section.
Changed third sentence, second paragraph.
Changed second paragraph.
Renamed section.
Replaced first paragraph.
Changed figure.
Section 3.3.1.5
Section 3.3.1.5
Section 3.3.1.6
Section 3.3.2.7
Section 3.3.2.2
Section 3.3.2.4
Section 3.3.2.4
Figure 15
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Added "Transparent Mode Setup" and last paragraph.
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Renamed section.
Changed first paragraph.
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Section 3.3.2.5
Section 3.3.2.7
Section 3.3.2.8
Section 3.5
Changed second bullet.
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Added "Transparent Mode Setup" and last paragraph.
Added section and subsections.
Changed third sentence.
Changed bit descriptions.
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Section 4
Table 65
Table 66
SPRUGH3–November 2008
Revision History
143
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