TAS5508−5121K8EVM
Evaluation Module for the TAS5508B 8-Channel
Digital Audio PWM Processor and the TAS5121
Digital Amplifier Power Output Stage
User’s Guide
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EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:.
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR
EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end−product fit for general
consumer use. Persons handling the product(s) must have electronics training and observe good engineering
practice standards. As such, the goods being provided are not intended to be complete in terms of required
design−, marketing−, and/or manufacturing−related protective considerations, including product safety and
environmental measures typically found in end products that incorporate such semiconductor components or
circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding
electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore
may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be
returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE
EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES,
EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR
FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Due to the open construction of the
product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior
to handling the product. This notice contains important safety information about temperatures and voltages. For
additional information on TI’s environmental and/or safety programs, please contact the TI application engineer
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
FCC WARNING
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR
EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end−product fit for general
consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for
compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide
reasonable protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at his own expense will be required
to take whatever measures may be required to correct this interference.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright © 2006, Texas Instruments Incorporated
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0–29.5 V and the output
voltage range of 15–20 V for the system supply.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
75°C. The EVM is designed to operate properly with certain components above 75°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright © 2006, Texas Instruments Incorporated
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Preface
Read This First
About This Manual
This manual describes the operation of the TAS5508−5121K8EVM evaluation
module from Texas Instruments.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 — Overview
- Chapter 2 — System Interfaces
- Chapter 3 — Protection
Information About Cautions and Warnings
This manual may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
iii
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Related Documentation From Texas Instruments
The following table contains a list of data manuals that have detailed
descriptions of the integrated circuits used in the design of the
TAS5508−5121K8EVM. The data manuals can be obtained at the URL
Part Number
TAS5508B
Literature Number
SLES162
SLES086
SLOS351
SCES212
SCES217
SCES198
SCES218
SCLS393
SCAS290
SCES211
SLVS297
TAS5121
TLV272
SN74LVC1G00
SN74LVC1G08
SN74LVC2G08
SN74LVC1G14
SN74LV123A
SN74LVC125A
SN74LVC1G126A
LM317M
TPS3801K33
TPS76733
SLVS219
SLVS208
Additional Documentation
TAS5508−5121K8EVM Application Report (SLEA034A)
PC Configuration Tool for TAS5508B (TAS5508 GUI ver.2.1 or later)
General Application Notes
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademarks
Equibit, PowerPAD, and PurePath Digital are trademarks of Texas
Instruments.
iv
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Contents
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
TAS5508−5121K8EVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
PCB Key Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
Power Supply (PSU) Interface (J70, J71, and J73) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 PSU Control Interface (J72) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Loudspeaker Connectors (J100 . . . J800) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Line Out Connectors (J950 and J951) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Headphone Connector (J900) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Line Output Select (J50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Headphone Select (J32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Control Interface (J30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Digital Audio Interface (J40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
3.2
Short-Circuit Protection and Fault-Reporting Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Device Fault Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
v
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Figures
1−1
1−2
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
Integrated PurePath Digitalt Amplifier System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Physical Structure for the TAS5508−5121K8EVM (Rough Outline) . . . . . . . . . . . . . . . . . . . 1-3
Recommended Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
J71 and J70 Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
J73 Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
J72 Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
J100 . . . J800 Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
J950 and J951 Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
J900 Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
J50 Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
J32 Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Tables
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
Recommended Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
J71 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
J70 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
J73 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
J72 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
J100 . . . J800 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
J950 and J952 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
J900 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
J50 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2−10 J32 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2−11 J30 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2−12 J40 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
3−1
3−2
Channel Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
TAS5121 Warning/Error Signal Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
vi
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Chapter 1
Overview
The TAS5508−5121K8EVM PurePath Digital™ customer evaluation amplifier
module demonstrates two audio integrated circuits, TAS5508B and TAS5121,
from Texas Instruments (TI).
The TAS5508BPAG is a high-performance 32-bit (24-bit input) multichannel
PurePath Digital pulse width modulator (PWM) based on Equibit™ technology,
with a new fully symmetrical AD modulation scheme. It accepts an input
sample rate from 32 kHz to 192 kHz. The device also has digital audio
processing (DAP) that provides 48-bit signal processing, advanced
performance, and a high level of system integration. The device has interfaces
for headphone output and power supply volume control (PSVC).
The TAS5121DKD is a compact, high-power, digital amplifier power stage
designed to drive a 4-Ω loudspeaker up to 100 W (10% THD+N). The
TAS5121DKD contains integrated gate drivers, four matched and electrically
isolated enhancement-mode N-channel power DMOS transistors, and
protection/fault-reporting circuitry.
The DKD package has a PowerPAD™ on the top side for heat transfer through
a heatsink. The heatsink in this design is for evaluation purpose only.
This EVM, together with a TI input board, is a complete 8-channel digital audio
amplifier system, which includes digital input (S/PDIF), analog inputs,
interface to PC, and DAP features, such as digital volume control, input and
output mixers, auto mute, equalization, tone controls, loudness, dynamic
range compression, and PSVC output. There are configuration options for
stereo line level output, stereo headphone output, and power-stage failure
protection.
This 7.1 system is designed for home-theater applications, such as A/V
receivers, DVD minicomponent systems, home theater in a box (HTIB), DVD
receivers, or plasma display panels (PDPs).
Topic
Page
1.1 TAS5508−5121K8EVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 PCB Key Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-1
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TAS5508−5121K8EVM Features
1.1 TAS5508−5121K8EVM Features
- 8-channel PurePath Digital evaluation module
- Stereo channel line output
- Stereo headphone output
- Self-contained protection system (short circuit and thermal)
2
2
- Standard I S and I C control connector for TI input board
- Double-sided plated-through PCB layout
Figure 1−1. Integrated PurePath DigitalE Amplifier System
2 Channel
Headphone Output
2 Channel
Rec Line Output
6 Channel
Analog Input
TAS5508−5121K8EVM
Module
Control Interface
I2C Bus
8 Channel
Speaker Output
PC Interface
Optical
and
Coaxial
I2S Bus
S/PDIF Input
Example
Texas Instruments
Input−PC Board
Power Supply
1-2
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PCB Key Map
1.2 PCB Key Map
The physical structure for the TAS5508−5121K8EVM is illustrated in
Figure 1−2.
Figure 1−2. Physical Structure for TAS5508−5121K8EVM (Rough Outline)
PSU
Interface
(J70)
J600
J500
J800
J700
J400
J300
J200
J100
Left Line
Output
(J950)
Right Line
Output
(J951)
Speaker Outputs
Speaker Outputs
TAS5508B
Headphone
Output
(J900)
Control
Interface (J30)
Input Signal
Interface (J40)
Overview
1-3
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1-4
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Chapter 2
S
y
s
t
e
m
I
n
t
e
r
f
a
c
e
s
This chapter describes the TAS5508−5121K8EVM board in regards to
power supplies and system interfaces.
Topic
Page
2.1 Power Supply (PSU) Interface (J70, J71, and J73) . . . . . . . . . . . . . . . . 2-2
2.2 Loudspeaker Connectors (J100 . . . J800) . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3 Line Out Connectors (J950 and J951) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4 Headphone Connector (J900) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5 Line Output Select (J50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.6 Headphone Select (J32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.7 Control Interface (J30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.8 Digital Audio Interface (J40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-1
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Power Supply (PSU) Interface (J70, J71, and J73)
2.1 Power Supply (PSU) Interface (J70, J71, and J73)
The TAS5508−5121K8EVM module must be powered from external power
supplies. High-end audio performance requires a stabilized power supply with
low ripple voltage and low output impedance.
Note:
The length of the power supply cable must be minimized. Increasing length
of PSU cable is equal to increasing the distortion for the amplifier at high
output levels and low frequencies.
The maximum output-stage supply voltage depends of the speaker load
resistance. Check the recommended maximum supply voltage in the
TAS5121 data sheet (SLES086).
Table 2−1.Recommended Supply Voltages
Voltage Limitations
Current
(4-W load)
Recommendations
Description
System power supply
15 – 20 V
0 – 30.5 V
0.3 A
†
Output-stage power supply
6 A
†
The rated current corresponds to 2-channel full scale (80 W each), which most likely is adequate
for a standard 8-channel amplifier design.
The recommended TAS5121 power-up sequence is shown in Figure 2−1. For
proper TAS5121 operation, the RESET signal should be kept low during power
up. RESET is pulled low during power up for 200 ms by the onboard reset
generator (U73).
Figure 2−1. Recommended Power-Up Sequence
System power supply
Output stage power supply
RESET
> 1 ms
Figure 2−2. J71 and J70 Pin Numbers
4
System Power Supply
3
2
1
(PCB connector top view)
2-2
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Power Supply (PSU) Interface (J70, J71, and J73)
Table 2−2.J71 Pin Description
Pin No.
Net-Name at Schematics
Description
1
2
3
4
V-HBRIDGE
Output-stage power supply
System power supply
Ground
−
GND
GND
Ground
Table 2−3.J70 Pin Description
(Optional − Use to decrease of impedance to reach better performance)
Pin No.
Net-Name at Schematics
V-HBRIDGE
V-HBRIDGE
GND
Description
1
2
3
4
Extra output-stage power supply
Extra output-stage power supply
Extra ground
GND
Extra ground
Figure 2−3. J73 Pin Numbers
2
1
(PCB connector top view)
Table 2−4.J73 Pin Description
(Optional)
Pin No.
Net-Name at Schematics
V-HBRIDGE
Description
1
2
Extra output-stage power supply
Extra output-stage power supply
V-HBRIDGE
2.1.1 PSU Control Interface (J72)
This interface is used for onboard sensing of output supply voltage and for the
power supply volume control (PSVC) signal.
Figure 2−4. J72 Pin Numbers
5
4
3
2
1
(PCB connector top view)
System Interfaces
2-3
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Loudspeaker Connectors (J100 . . . J800)
Table 2−5.J72 Pin Description
Pin No.
Net-Name at Schematics
Description
1
2
3
4
5
—
Reserved for future use
Sense of output power supply
Ground
V-HBRIDGE
GND
RESET
PSVC
System reset (bidirectional)
Power-supply volume control signal
2.2 Loudspeaker Connectors (J100 . . . J800)
Both positive and negative speaker outputs are floating and may
not be connected to ground (e.g., through an oscilloscope).
Figure 2−5. J100 . . . J800 Pin Numbers
2
1
(PCB connector top view)
Table 2−6.J100 . . . J800 Pin Description
Pin No.
Net-Name at Schematics
Description
1
2
OUT−1
Speaker negative output
Speaker positive output
OUT−2
2.3 Line Out Connectors (J950 and J951)
Figure 2−6. J950 and J951 Pin Numbers
2
1
3
4
(PCB connector top view)
Table 2−7.J950 and J952 Pin Description
Pin No.
Net-Name at Schematics
Description
Ground
1
2
3
4
GND
OUT
OUT
OUT
Line out signal
Line out signal
Line out signal
2-4
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Headphone Connector (J900)
2.4 Headphone Connector (J900)
Figure 2−7. J900 Pin Numbers
1
3
2
4
(PCB connector top view)
Table 2−8.J900 Pin Description
Pin No.
Net-Name at Schematics
Description
1
2
3
4
OUT−L
GND
Left headphone output
Ground
—
For future use
OUT−R
Right headphone output
2.5 Line Output Select (J50)
Figure 2−8. J50 Pin Numbers
Table 2−9.J50 Pin Description
Pin No.
1−2
Description
Line outputs enabled
Line outputs disabled
2−3
2.6 Headphone Select (J32)
Figure 2−9. J32 Pin Numbers
Table 2−10.J32 Pin Description
Pin No.
1−2
Description
Headphone enabled
Headphone disabled
2−3
System Interfaces
2-5
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Control Interface (J30)
2.7 Control Interface (J30)
This interface connects the TAS5508−5121K8EVM board to a TI input board.
Table 2−11.J30 Pin Description
Pin Net-Name at
No. Schematics
Description
1
2
3
4
5
GND
Ground
PSVC−MCPU Power supply volume control from (mC) input board
GND
Ground
RESET
System reset (bidirectional). Activate MUTE before RESET for quiet reset.
2
BKND−ERR
Backend error (or soft reset) provides reduced click and pop reset, without resetting I C
volume register settings.
2
6
7
MUTE
Ramp volume from any setting to noiseless soft mute. Mute can also be activated by I C.
PDN
Power down. The TAS5508B goes to a power-down state when activated.
8
9
RESERVED
2
10 SDA
11 GND
12 SCL
I C data clock
Ground
2
I C bit clock
13 RESERVED
14
15 CONF−SEL
Configuration select. Channel 5 and 6 speaker outputs active and line outputs inactive
when high. Line outputs active and channel 5 and 6 speaker outputs inactive when low.
16 RESERVED
17 GND
Ground
18 RESERVED
19
20 SD1
Shutdown error reporting for front left, front right, and center channels. Activated if the
TAS5121 has high current or high temperature. See Chapter 3.
21 SD2
Shutdown error reporting for rear left, rear right, surround left, surround right, and
subwoofer channels. Activated if TAS5121 has high current or high temperature. See
Chapter 3.
22 OTW
Temperature warning. Activated if one or more TAS5121 has reached the temperature
warning level.
23 RESERVED
24 HP−SEL
Headphone select. Headphone is active when low and inactive when high.
Ground
25 GND
26
27 RESERVED
28
29
30
31 GND
32
Ground
33 +5V
34
5-V dc power supply (output)
2-6
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Digital Audio Interface (J40)
2.8 Digital Audio Interface (J40)
2
The digital audio interface contains digital audio signal data (I S), clocks, etc.
See the TAS5508B Data Manual (SLES162) for signal timing and details not
explained in this document.
Table 2−12.J40 Pin Description
Pin Net-Name at
No. Schematics
Description
1
2
GND
Ground
MCLK
Master clock input. Low-jitter system clock for PWM generation and reclocking.
Ground connection from source to the TAS5508B must be a low-impedance
connection.
3
4
5
6
7
8
9
GND
Ground
2
SDIN1
SDIN2
SDIN3
SDIN4
I S data 1, channel 1 and 2
2
I S data 2, channel 3 and 4
2
I S data 3, channel 5 and 6
2
I S data 4, channel 7 and 8
Reserved
Reserved
Ground
10 GND
11 SCLK
12 GND
13 LRCLK
14 GND
15
2
I S bit clock
Ground
2
I S left−right clock
Ground
Reserved
Ground
16 GND
System Interfaces
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Chapter 3
Protection
This chapter describes the short-circuit protection and fault-reporting circuitry
of the TAS5121 device.
Topic
Page
3.1 Short-Circuit Protection and Fault-Reporting Circuitry . . . . . . . . . . . 3-2
3.2 Device Fault Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3-1
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Short-Circuit Protection and Fault-Reporting Circuitry
3.1 Short-Circuit Protection and Fault-Reporting Circuitry
The TAS5121 is a self-protecting device that provides device fault reporting
(including high-temperature protection and short-circuit protection). The
TAS5121 is configured in back-end auto-recovery mode and, therefore, resets
automatically after all errors (M1, M2, and M3 is set low). This means that the
device restarts itself after an error occasion and reports shortly through SD1
and SD2 error signals.
The shutdown report signals are separated into two wires, SD1 and SD2. SD1
covers the primary information channels (front channels and center), where
the SD2 covers the secondary information channels (rear channels,
surround/line out channels, and subwoofer). Therefore, a microprocessor can
react differently on errors depending on primary or secondary channels faults,
e.g., lowering the output level or shutting down the secondary channels on
continues error reporting from one of those, where the primary channels
continue.
3-2
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Device Fault Reporting
3.2 Device Fault Reporting
The OTW and SD outputs from the TAS5121 indicate fault conditions. See the
TAS5121 data sheet (SLES086) for a description of these pins.
The temperature warning signals at the TAS5508−5121K8EVM board are
wired-OR to one temperature warning signal [OTW – pin 22 in control interface
connector (J30)].
Shutdown signals are wired-OR into two shutdown signals [SD1 and SD2 – pin
20 and pin 21 in control interface connector (J30)]. See Table 3−1 for channel
allocation.
Table 3−1.Channel Allocation
Description
Terminal
J100
J200
J300
J400
J500
J600
J700
J800
Shutdown Signal
Front left
SD1
SD1
SD2
SD2
SD2
SD2
SD1
SD2
Front right
Rear left
Rear right
Surround left (or line out left)
Surround right (or line out right)
Center
Subwoofer
The shutdown signals, together with the temperature warning signal, give chip
state information as described in Table 3−2. Device fault reporting outputs are
open-drain outputs.
Table 3−2.TAS5121 Warning/Error Signal Decoding
OTW
SDx Device Condition
High-temperature error and/or high-current error
0
0
0
1
1
1
0
1
High-temperature warning
Undervoltage lockout or high-current error
Normal operation, no errors/warnings
Protection
3-3
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3-4
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