DEMĆDAI3010
User’s Guide
April 2003
DAV Digital Audio/Speaker
SLEU036
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EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
oftheproduct, itistheuser’sresponsibilitytotakeanyandallappropriateprecautionswithregardtoelectrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’sGuidepriortohandlingtheproduct. Thisnoticecontainsimportantsafetyinformationabouttemperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of ±15 V and the output
voltage range of ±15 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applyingloadsoutsideofthespecifiedoutputrangemayresultinunintendedoperationand/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
55°C. The EVM is designed to operate properly with certain components above 55°C as long
as the input and output ranges are maintained. These components include but are not limited
tolinearregulators, switchingtransistors, passtransistors, andcurrentsenseresistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
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Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Use of the DEM-DAI3010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.1 Initial Settings of the DEM-DAI3010 (at shipping) . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.2 How to Connect Power Supplies to the DEM-DAI3010 . . . . . . . . . . . . . . . . . . . 1-3
Settings and Connections for Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Setting Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4.1 Function Setting Switches and Header Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4.2 Detailed Explanation of Function Setting Switches and Header Pins . . . . . . . . 1-6
1.3
1.4
2
Printed-Circuit Board and Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
2.2
DEM-DAI3010 Printed-Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
DEM-DAI3010 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Figures
1–1
2–1
2–2
2–3
2–4
2–5
2–6
DEM-DAI3010 Block DIagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
DEM-DAI3010 Silkscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
DEM-DAI3010—Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
DEM-DAI3010—Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
DEM-DAI3010 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
DEM-DAI3010 Regulator, Connector and Ext.-I/F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
DEM-DAI3010 Digital Section (Digital Audio Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Tables
1–1
1–2
1–3
Initial Settings of the DEM-DAI3010 at Shipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Power Supply Terminals and Supply Voltage (Depending on CN057 Setting) . . . . . . . . . . 1-3
Switches and Header Pins of the DEM-DAI3010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
v
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vi
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Chapter 1
Description
The DEM-DAI3010 is an evaluation board for the PCM3010 (24-bit, 96-kHz
ADC and 192-kHz DAC, stereo codec). This board includes not only the
PCM3010 but also analog I/O terminals, analog filter circuits, and an S/PDIF
digital I/O circuit that is useful for codec evaluation. S/PDIF I/O circuits consist
ofa24-bit/96-kHzdigitalaudiointerfacereceiver(DIR1703)andadigitalaudio
interface transmitter (DIT4096), and include optical (TOSLINK) and coaxial
S/PDIF digital I/O connectors. Removing shorting plugs from the pins of a
header breaks the connection between the S/PDIF I/O circuits and the
PCM3010for easier PCM3010 device evaluation.
Topic
Page
1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Use of the DEM-DAI3010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Settings and Connections for Basic Operation . . . . . . . . . . . . . . . . . . 1-4
1.4 Setting Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1-1
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Block Diagram
1.1 Block Diagram
Figure 1–1. DEM-DAI3010 Block DIagram
System Clock
X’tal Frequency
Data Format
Clock Mode
SW004
System Clock
SW003
JP001
DAC Output
L-ch Output
S/PDIF Input
OPT. IN
JP107
LPF
LPF
SW001
PCM3010
(Slave Only)
R-ch Output
DIR1703
COAX. IN
ADC Input
24.576 MHz
DIT4096
L-ch 1Vrms
JP105
JP106
L-ch 2Vrms
S/PDIF Output
OPT. OUT
LPF
LPF
SW051
R-ch 1Vrms
R-ch 2Vrms
COAX. OUT
74HCT244
SW005
SW006
SW101
System Clock
Data Format
Channel Status
System Clock
Data Format
Power Down
LPF Circuits
±15 V
5 V
PCM3010 V
PCM3010 V
and DIR1703, DIT4096, TOSLINK
CC
DD
CN057
3.3 V
3.3 V
1-2
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Use of the DEM-DAI3010
1.2 Use of the DEM-DAI3010
The DEM-DAI3010 is shipped with standard settings preset. Therefore,
connecting power supplies (15-V, –15-V and 5-V) is the only requirement to
prepare the board for use, unless nonstandard settings are desired.
1.2.1 Initial Settings of the DEM-DAI3010 (at shipping)
Table 1–1.Initial Settings of the DEM-DAI3010 at Shipping
Item
Initial Setting (at shipping)
Power supply voltage
15 V, –15 V, and 5 V (close CN57)
CN51–CN55 (open CN56)
Power supply terminals
Connection of PCM3010 and S/PDIF I/O
DIR1703 system clock (SCK)
DIR1703 output audio data format
DIR1703 crystal clock frequency
DIT4096 system clock (SCLK)
DIT4096 input audio data format
PCM3010 system clock
DIR1703 and DIT4096 connected with JP107
256 f
S
2
I S
24.576 MHz (load capacitance: 18 pF)
256 f
S
2
I S
Automatic selection (no setting required)
2
PCM3010 I/O audio data format
PCM3010 power-down function
PCM3010 de-emphasis function (DAC)
PCM3010 DAC cutoff frequency
PCM3010 ADC input terminal selection
I S
Disabled
Disabled
54 kHz (JP101–JP104 are closed)
CN101, CN102: 2-V rms input (with LPF)
1.2.2 How to Connect Power Supplies to the DEM-DAI3010
The DEM-DAI3010 requires 5-V, 15-V, and –15-V power supplies. Power is
supplied to this board by five binding posts (one each for V = +5 V, +AV
CC
CC
=+15V, –AV =–15V, andtwoforground)fromstabilizeddcpowersupplies.
CC
V
(3.3 V) for the PCM3010 is normally generated by an onboard
DD
voltage-regulator IC from V
(5 V), but it is possible to supply 3.3 V directly.
CC
To do so, open CN057, then supply 3.3 V to CN056 and 5 V to CN054. If 3.3
V is supplied externally, 5 V must still be provided to CN054 in order to supply
theanalogsectionofthePCM3010. Toavoidlatch-upofthePCM3010, ensure
that V
and V
are powered up simultaneously.
DD
CC
Table 1–2.Power Supply Terminals and Supply Voltage (Depending on CN057 Setting)
Power Terminal
CN051 (orange)
CN052 (green)
CN053 (blue)
CN054 (red)
CN057 Closed (Default)
CN057 Open
15 V
15 V
0 V (ground)
–15 V
0 V (ground)
–15 V
5 V
5 V
CN055 (black)
0 V (ground)
0 V (ground)
3.3 V
CN056 (2-pin connector) Open (no connection)
Description
1-3
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Settings and Connections for Basic Operation
1.3 Settings and Connections for Basic Operation
The PCM3010 is an LSI codec containing an ADC and a DAC. Connections
and settings depend on the evaluation object (ADC or DAC), and the setup
should be checked carefully. Following are example settings for three typical
evaluation situations. Note that when using S/PDIF I/O, the optical and coaxial
input corresponds to f = 96 kHz.
S
When the DAC section of PCM3010 is evaluated with S/PDIF input signal (the
PCM3010 operates as a slave of the DIR1703 PLL clock)
- Close all pins of JP107 with shorting plugs.
- Input an S/PDIF signal into the optical (U053) or coaxial (CN059)
connector.
- CN105 (L-ch) and CN106 (R-ch) are the analog signal outputs.
- Choose an S/PDIF input terminal (optical/coaxial) with the S/PDIF input
switch (SW051).
- Set the clock-mode switch (SW004) to PLL or Auto.
- The cutoff frequency of the LPF can be changed by JP101, JP102, JP103,
and JP104. All these jumpers are shorted at the time of shipment, which
sets the cutoff frequency to 20 kHz.
When the ADC section of PCM3010 is evaluated with S/PDIF output signal (the
PCM3010 operates as a slave of the DIR1703 crystal clock)
- Short all pins of JP107 with shorting plugs.
- Connect an analog signal to CN101/CN102 using an LPF, or to CN103/
CN104 using only a coupling capacitor without an LPF.
- Select the analog input terminal by changing by the settings of JP105 and
JP106. (Setup at the time of shipment is for CN101 and CN102.)
- A Toslink (U052) and a pin jack (CN058) are the S/PDIF digital output
terminals. Select the digital output connector by setting the S/PDIF output
switch (SW051). Simultaneous use of optical and coaxial outputs is
impossible.
- Set the clock mode switch (SW004) to X’tal. The X’tal mode of DIR1703
is used as a master clock for the ADC and DIT.
- Set up the channel status data using SW006.
- Because system clock frequency is 256 f , the ADC section operates at
S
f = 96 kHz. To operate the ADC section at a different f , the crystal (X001)
S
S
connected to DIR1703 must be changed. The system clock setup can be
changed if required. The load capacitance used with the crystal is
dependent on the crystal properties. Therefore, when the crystal is
changed, the capacitance of C006 and C007 must be selected to match
the crystal specification.
When S/PDIF I/O is not used (the PCM3010 is evaluated alone)
- Remove all shorting plugs attached to JP107.
1-4
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Setting Functions
- Data and a clock are supplied to the PCM3010 side of JP107.
- Set up FMT0 and FMT1 of SW101 according to the data format to be used.
- Set up DEMP0 and DEMP1 of SW101 for the desired de-emphasis of the
DAC section and PWDN for the power-down setting.
1.4 Setting Functions
All functions of the devices (PCM3010, DIR1703, DIT4096) on the
DEM-DAI3010 are controlled by DIP switches or header pins on this PCB.
Therefore, the DEM-DAI3010 does not require a microcontroller or software
to transmit data to internal function-setting registers. For specific information
on any device, see the data sheet for that device.
1.4.1 Function Setting Switches and Header Pins
Table 1–3.Switches and Header Pins of the DEM-DAI3010
SW/JP No. Item
Shape
SW001
SW002
SW003
SW004
SW005
SW006
SW051
SW101
JP001
JP107
JP101
JP102
JP103
JP104
JP105
JP106
CN057
S/PDIF input selection (optical/coax)
Toggle switch
Pushbutton switch
4-pole DIP switch
Toggle switch
4-pole DIP switch
10-pole DIP switch
Toggle switch
5-pole DIP switch
2×5 header
Reset of DIR1703 and DIT4096
Format and system clock setting of DIR1703
Output clock selection of DIR1703 (X’tal/Auto/PLL)
Format and system clock setting of DIT4096
Channel status data setting of DIT4096
S/PDIF output selection (optical/coax)
Setting of PCM3010 (format, de-emphasis, power down)
Crystal frequency and system clock setting of DIR1703
Connection of S/PDIF I/O circuit and PCM3010
Cutoff frequency setting of DAC output filter (L-ch)
Cutoff frequency setting of DAC output filter (R-ch)
Cutoff frequency setting of DAC output filter (L-ch)
Cutoff frequency setting of DAC output filter (R-ch)
Selection of L-ch ADC input terminal (CN101/CN103)
Selection of R-ch ADC input terminal (CN102/CN104)
2×7 header
2×2 header
2×2 header
2×1 header
2×1 header
2×2 header
2×2 header
The way of power supply of PCM3010 V
(3.3 V)
2×1 header
DD
Note: The relation between the DIP switch setting (ON/OFF) and the setting of the IC input port is printed on the PCB. The DIP
switch H position does not always set the IC input port level HIGH.
Toggle switch settings are printed on the PCB.
Description
1-5
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Setting Functions
1.4.2 Detailed Explanation of Function Setting Switches and Header Pins
SW001: Switch to select S/PDIF input connector (optical/coaxial). Selection of the
S/PDIF signal that is routed to the DIR1703 DIN port.
SW002: Reset switch for the DIR1703 and DIT4096. Pushing this switch resets the
DIR1703 and DIT4096 to the initial state. A reset circuit operates at the time of
power-supply connection, resetting the DIR1703 and DIT4096 automatically.
Therefore, it is not usually necessary to operate this switch.
SW003: Switch for setting the DIR1703 system clock and output data format
SCF1
SCF0
System Clock
128 f
L
L
S
L
H
L
256 f (initial stting)
S
H
H
384 f
512 f
S
S
H
FMT1
FMT0
Output Data Format
L
L
16-bit right-justified, MSB-first
24-bit right-justified, MSB-first
24-bit left-justified, MSB-first
L
H
L
H
H
2
H
24-bit, I S (initial setting)
SW004: Switch for setting the DIR1703 output clock source
Position
X’tal
Output Clock (SCK, BCK, LRCK)
Crystal clock
PLL
PLL clock
Auto
PLL (PLL locked) / crystal (PLL unlocked)
Note: When using the DIR1703 as a master clock for the ADC, this switch must be set to X’tal.
When inputting S/PDIF data demodulated by the DIR1703 into the DAC, set this switch to Auto or PLL.
SW005: Switch for setting the DIT4096 system clock and input data format
Note that the OFF state of this switch sets a HIGH level.
CLK1
CLK0
System Clock
L
L
Not used
L
H
L
256 f (initial setting)
S
H
H
384 f
512 f
S
S
H
1-6
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Setting Functions
FMT1
FMT0
Input Data Format
L
L
24-bit, left-justified, MSB-first
2
L
H
L
24-bit, I S (initial setting)
H
H
24-bit, right-justified, MSB-first
16-bit, right-justified, MSB-first
H
SW006: Switch for setting channel-status data of the DIT4096. Note that the OFF state
of this switch sets a HIGH level. Channel status data can set up if needed.
Moreover, it is also possible to connect a microcontroller to CN002 and to write
in channel-status data with the microcontroller. See the DIT4096 data sheet (TI
literature number SBOS225) for details about the contents of a setting.
SW051: Switch to select the S/PDIF output connector (optical/coaxial). An S/PDIF
output connector is chosen from optical (U052) and coaxial (CN058). The
optical and coaxial output terminals cannot be used simultaneously.
SW101: Switch for setting the functions of the PCM3010. All the functions of PCM3010
are set up with this switch. Functions that can be set are the audio serial data
I/O format, the DAC section de-emphasis, and power-down control.
FMT1
FMT0
DAC Input Data Format
ADC Output Data Format
24-bit, left-justified, MSB-first
24-bit, left-justified, MSB-first
24-bit, left-justified, MSB-first
L
L
24-bit, right-justified, MSB-first
16-bit, right-justified, MSB-first
24-bit, left-justified, MSB-first
L
H
L
H
H
2
2
H
24-bit, I S (initial setting)
24-bit, I S (initial setting)
DEMP1
DEMP0
DAC De-Emphasis
De-emphasis ON, 44.1-kHz
L
L
L
H
L
De-emphasis OFF (initial setting)
De-emphasis ON, 48-kHz
De-emphasis ON, 32-kHz
H
H
H
PDOWN
Power-Down Control
L
Power-down mode
H
Nomal operation (initial setting)
JP001:
Setup of the crystal frequency and system clock for the DIR1703. When the
system clock and the frequency of the crystal for the DIR1703 are changed, a
shorting plug is inserted in only one position of JP001 according to the following
tables. In order to avoid the loss of a shorting plug which is not being used, the
plug is put in the header pin position labeled as OPEN. Because 24.576 MHz
is used for a quartz crystal and the system clock is set as the 256 f output in
S
initial setting at the time of shipment, the shorting plug is attached in the CSBIT
position.
Description
1-7
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Setting Functions
JP001 setting table: DIR1703 system clock and crystal frequency
f in X’tal
S
Mode
128 f
256 f
384 f
512 f
S
BRSEL Jumper Position
S
S
S
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
4.096 MHz
5.6448 MHz
6.144 MHz
8.192 MHz
12.288 MHz
16.384 MHz
BFRAME
11.2896 MHz 16.9344 MHz 22.5792 MHz EMFLG
12.288 MHz 18.432 MHz 24.576 MHz OPEN (no jumper)
11.2896 MHz 22.5792 MHz 33.8688 MHz 45.1584 MHz URBIT
12.288 MHz 24.576 MHz 36.864 MHz 49.152 MHz CSBIT
Sample of a of JP001 setting
Target: system clock: 256 f and f = 48 kHz in the X’tal mode
S
S
In the preceding table, the frequency listed where the 256-f column
S
intersects the 48-kHz row is 12.288 MHz.
JP101–JP104: Cutoff frequency setting of DAC output post-LPF
The cutoff frequency of the LPF inserted in the DAC output is chosen by
these jumpers. The initial setting (all pins shorted) is 54 kHz at the time
of shipment. The cutoff frequency with all JP101–JP104 jumper pins open
is 108 kHz.
JP105–JP106: Selection of ADC input connectors (CN101 and CN102 or CN103 and
CN104)
There are two pairs of ADC input connectors. One pair is coupled to the
PCM3010 through capacitors (C121, C122). The other pair is connected
through a 103-kHz cutoff LPF and a –6 dB amplifier.
TheinputconnectorsarechosenbyJP105andJP106. Whenthejumpers
are on Direct-IN, then the left- and right-channel inputs on CN103 and
CN104, respectively, bypass the LPF.
When the jumpers are on –6 db/LPF, then the left- and right-channel
inputs on CN101 and CN102, respectively, go through the LPF to the
PCM3010.
ADC Full-Scale Input
L-ch 2 V rms
Connector No.
CN101
Details
L-ch ADC input with LPF
R-ch ADC input with LPF
L-ch ADC input without LPF
R-ch ADC input without LPF
R-ch 2 V rms
CN102
L-ch 1 V rms
CN103
R-ch 1 V rms
CN104
JP107: Connection of PCM3010 and S/PDIF I/O circuits
This is the header pin which connects the clock input and data I/O of the PCM3010
with an S/PDIF I/O circuit. All pin positions have shorting plugs installed at the time
of shipment.
ForevaluatingthePCM3010withotherDSPs, DIRs, andDITs, JP107jumpersare
removed. Connection to the alternative devices is made through the row of JP107
pins that is wired to the PCM3010.
1-8
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Setting Functions
CN057: V
supply selection for the PCM3010
CC
This jumper determines whether V
for the PCM3010 is supplied from a 3.3-V
CC
regulator on this board (U051), or via an external power supply terminal (CN056).
In the initial setting, V is supplied from the onboard regulator. When V for the
CC
CC
PCM3010 is to be provided by an external power supply, the jumper is removed
from CN057 and 3.3 V is supplied to CN056. If 3.3 V is supplied externally, 5 V
must still be provided to CN054 in order to supply the analog section of the
PCM3010.
To avoid latch-up of the PCM3010, ensure that V
simultaneously at start-up.
and V
are switched on
CC
DD
Description
1-9
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1-10
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Chapter 2
Printed-Circuit Board and Schematic
This chapter presents the DEM-DAI3010 printed-circuit board and
schematics.
Topic
Page
2.1 DEM-DAI3010 Printed-Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 DEM-DAI3010 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-1
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DEM-DAI3010 Printed-Circuit Board
2.1 DEM-DAI3010 Printed-Circuit Board
Figure 2–1. DEM-DAI3010 Silkscreen
2-2
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DEM-DAI3010 Printed-Circuit Board
Figure 2–2. DEM-DAI3010—Top View
Printed-Circuit Board and Schematic
2-3
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DEM-DAI3010 Printed-Circuit Board
Figure 2–3. DEM-DAI3010—Bottom View
2-4
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DEM-DAI3010 Schematics
2.2 DEM-DAI3010 Schematics
Figure 2–4. DEM-DAI3010 Analog Section
R113 1.2k
C119
100pF
C117 330pF
CN101
RCA
R117 4.7k
R111
3.3k
R109
2.4k
AV
+
pj
CC
C121
10uF
/16V
2
3
JP105
6
5
1
8
C 115
1800pF
FFC–4BMEP1
C113
7
C123
R115
4.7k
10uF
/16V
4
10uF/16V
U102
C125
U102
OPA2134PA
2/2
10uF/16V
OPA2134PA
1/2
CN103
RCA
pj
AV
AV
–
CC
R114 1.2k
C118 330pF
C120 100pF
R118 4.7k
CN102
RCA
R112
3.3k
R110
2.4k
+
CC
pj
C122
10uF
/16V
2
3
JP106
6
5
1
8
C116
1800pF
FFC–4BMEP1
C114
7
C124
R116
4.7k
10uF
/16V
4
10uF/16V
U103
U103
C126
OPA2134PA
1/2
OPA2134PA
2/2
10uF/16V
CN104
RCA
pj
AV
–
CC
V
CC
C138
U104
PCM3010
10uF
/16V
C137
0.1uF
C128
10uF
/16V
R105 15k
C101
10uF
/16V
C127
0.1uF
1
2
24
V
V
V
V
V
L
V
C109
JP103
IN
COM
JP101
2/2
23
22
21
20
19
18
17
16
15
14
13
R
IN
V
L
OUT
C135
0.1uF
3
120pF
C130
1
2
V
R
2
REF
REF
OUT
4
10uF/16V
R101
8.2k
C136
10uF/16V
V
CC
C129 0.1uF
R103
1k
5
C107 120pF
AGND2
DEMP0
DEMP1
PDWN
SCKI
1
CC
CN105
RCA
R107
100
6
2
3
C132
JP101
1/2
pj
AGND1
FMT0
FMT1
TEST
LRCK
BCK
10uF/16V
1
7
C131
0.1uF
8
C105
1200pF
U101
4
C103
1200pF
9
V
DD
OPA2134A
1/2
10
11
12
V
DD
AV
+
CC
DGND
DOUT
C111
10uF
/16V
C134
DIN
JP101/102: FFC–4BMEP1
C133
0.1uF
R121
0
R120
0
10uF /16V
JP103/104: FFC–2BMEP1
C102
10uF
/16V
C112
10uF
/16V
R106 15k
R119 220
C110
JP104
AV
–
CC
JP107
FFC–12BMEP1
JP102
2/2
5
4
FMT0
120pF
R102
8.2k
FMT1
GND
3
2
1
R104
1k
DEMP0
DEMP1
PDWN
C108 120pF
8
TX–DATA
SCLK
CN106
RCA
R108
100
6
5
pj
JP102
1/2
SW101
DSS105
7
BCK
C106
1200pF
U101
LRCK
C104
1200pF
OPA2134A
2/2
RX–DATA
Printed-Circuit Board and Schematic
2-5
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DEM-DAI3010 Schematics
Figure 2–5. DEM-DAI3010 Regulator, Connector and Ext.-I/F
CN056 B2P–VH
CN055
banana jack
(Black)
CN054
CN053
CN052
CN051
banana jack banana jack banana jack banana jack
V
DD
(Red)
(Blue)
(Green)
(Orange)
+
A V
CC
2
1
U051
REG1117–3.3
V
CC
CN057
FFC–2BMEP1
2
3
OUT IN
GND
C053
C052
10ouF
/16V
C054
100uF
/16V
C051
0.1uF
C055
0.1uF
1
C056
100uF
/16V
A V
–
CC
10uF/16V
CN060 57LE–40360–7700(D3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 33
34
35
36
C062
0.1uF
U054
74LVC244
[RESET]
[MDO]
1
20
19
18
RA051
Vcc
47k x 5
2
3
1
2
3
SW053
DSS104
U052
RESET
MDO
MDI
TOTX179P
[MDI]
4
5
17
16
15
14
13
12
11
3
4
[MC]
[ML]
6
MC
C057
1
2 4
5
7
0.1uF
C058
10uF
/16V
ML
8
9
CN05
8
10
GND
RCA pj
R052
374
6
5
4
2
1
SW051
R051
90.9
FT1D–2M
SW052
Optical
REC-out
FT1D–2M
3
REC–out
DIT–out
OPT-in
TR001
DIT/REC–out select
DA–02
C061
0.1uF
Coaxial
DIT–out
OPT/COAX–out
U053
TORX179P
COAX-in
select
1
C 05 9
0.1uF
C060
10uF
/16V
2
3 4
5
CN059 RCA
pj
R053
75
2-6
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DEM-DAI3010 Schematics
Figure 2–6. DEM-DAI3010 Digital Section (Digital Audio Interface)
RA001
47k x 5
1
FMT1
FMT0
CLK1
CLK0
MODE
MDAT
MONO
M/S
RA003
47k x 9
CN002
FFC
SW006
2
3
4
5
6
7
SW005
DSS109
DSS108
–9AMEP1
9
8
7
6
5
4
3
CSS
COPY/C
U
1
2
28
27
CSS
MODE
U
COPY/C
L
3
4
5
6
7
26
25
24
23
22
V
V
8
L
CLK1
CLK0
MCLK
BLS
AUDIO
EMPH
BLSM
EMPH
AUDIO
MONO
MDAT
C015
10 uF /16V
RA002
47k x 3
2
1
C018
0.1uF
Vcc
BLSM
BLS
V
DD
8
9
21
20
19
18
17
16
15
1
2
3
4
5
6
7
20
19
18
17
16
15
14
DGND
FMT0
FMT1
SCLK
SYNC
SDATA
M/S
C016
0.1uF
[SCLK]
C014
0.1uF
10
11
12
13
14
V
DD
C017
10 uF /16V
[BCK]
TX+
TX–
[LRCK]
DGND
RST
8
9
13
12
11
[TX–DATA]
U004 DIT4096
10
GND
U005
74HCT244
CN001
FFC–10AMEP1
[ADFLG]
[BRATE0]
[BRATE1]
ADFLG
BRATE0
BRATE1
UNLOCK/PE
BFRAME
EMFLG
SW003
DSS104
SW004
FT1E–2M
4
3
URBIT
CSBIT
Clock mode select
R003
47k
X’tal
CKTRNS
R004
470
2
1
GND
1
28
27
PLL
ADFLG
CKSEL
UNLOCK
FMT1
[BRSEL]
2
Auto
C010
D001
BRATE0
[CSBIT]
[URBIT]
[EMFLG]
[BFRAME]
3
4
5
6
7
26
25
24
23
22
1SS133
BRATE1
C011
10uF
10uF
/16V
C009
0.1 uF
C008
10uF
/16V
V
CC
SCKO[SCLK]
FMT0
SW002
V
V
CC
DD
FP1F–2M
R006
1.2k
JP001
C019
10uF
/16V
C005
DGND
XTO
AGND
FILT
RST
DIN
FFC10–
BMEP1
R005
1M
C012
0.068uF
10uF
/16V
8
9
21
20
19
18
17
16
15
XTI
C013
8200pF
X001
24.576MHz
(PX–1 x2pcs.)
CKTRNS
10
11
12
13
14
LRCKO[LRCK] BRSEL
BCKO[BCK] BFRAME
DOUT[RX-DATA] EMFLG
V
CC
C006
C007
18p
F
18p
F
C020
10uF
/16V
U003 REG1117–3.3
REC–out
DIT–out
IN
SCF0
SCF1
URBIT
CSBIT
2
OU T
GND
3
1
C0 04 0.1uF
U002 DIR1703
C001
0.1u
OPT–in
F
1
2
3
4
5
6
7
C002
0.1uF
14
13
12
11
10
9
C003
10uF/16V
COAX in
Vcc
RESET
MDO
MDI
MC
ML
R001
47k
CN004
XB–3–7–20
[TX–DATA ]
R002
2.2k
CN003
GND
TX–DATA
XB–3–7–20
[SCLK ]
8
SCLK
GND
SW001
FT1D–2M
U001
[BCK ]
[LRCK ]
[RX–DATA]
BCK
LRCK
RX–DATA
74HCU04
Printed-Circuit Board and Schematic
2-7
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