SM320F2812-HT
Digital Signal Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SGUS062A
June 2009–Revised April 2010
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SGUS062A–JUNE 2009–REVISED APRIL 2010
4
Peripherals ....................................................................................................................... 52
4.1
32-Bit CPU-Timers 0/1/2 ................................................................................................. 52
Event Manager Modules (EVA, EVB) ................................................................................... 55
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
General-Purpose (GP) Timers ................................................................................ 58
Full-Compare Units ............................................................................................. 58
Programmable Deadband Generator ........................................................................ 58
PWM Waveform Generation .................................................................................. 58
Double Update PWM Mode ................................................................................... 58
PWM Characteristics ........................................................................................... 59
Capture Unit ..................................................................................................... 59
Quadrature-Encoder Pulse (QEP) Circuit ................................................................... 59
External ADC Start-of-Conversion ........................................................................... 59
4.3
4.4
4.5
4.6
4.7
4.8
Enhanced Analog-to-Digital Converter (ADC) Module ............................................................... 60
Enhanced Controller Area Network (eCAN) Module .................................................................. 65
Multichannel Buffered Serial Port (McBSP) Module .................................................................. 69
Serial Communications Interface (SCI) Module ....................................................................... 73
Serial Peripheral Interface (SPI) Module ............................................................................... 76
GPIO MUX ................................................................................................................. 79
5
6
Development Support ........................................................................................................ 82
5.1
Device and Development Support Tool Nomenclature ............................................................... 82
Documentation Support ................................................................................................... 83
5.2
Electrical Specifications ..................................................................................................... 85
6.1
Absolute Maximum Ratings .............................................................................................. 85
Recommended Operating Conditions .................................................................................. 86
6.2
6.3
6.4
Electrical Characteristics ................................................................................................. 86
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During
Low-Power Modes at 150-MHz SYSCLKOUT ......................................................................... 88
6.5
6.6
6.7
6.8
6.9
Current Consumption Graphs ............................................................................................ 89
Reducing Current Consumption ......................................................................................... 90
Power Sequencing Requirements ....................................................................................... 90
Signal Transition Levels .................................................................................................. 91
Timing Parameter Symbology ........................................................................................... 92
6.10 General Notes on Timing Parameters .................................................................................. 93
6.11 Test Load Circuit .......................................................................................................... 93
6.12 Device Clock Table ........................................................................................................ 94
6.13 Clock Requirements and Characteristics ............................................................................... 94
6.13.1 Input Clock Requirements ..................................................................................... 94
6.13.2 Output Clock Characteristics .................................................................................. 95
6.14 Reset Timing ............................................................................................................... 96
6.15 Low-Power Mode Wakeup Timing ..................................................................................... 100
6.16 Event Manager Interface ................................................................................................ 104
6.16.1 PWM Timing ................................................................................................... 104
6.16.2 Interrupt Timing ................................................................................................ 106
6.17 General-Purpose Input/Output (GPIO) – Output Timing ............................................................ 107
6.18 General-Purpose Input/Output (GPIO) – Input Timing .............................................................. 108
6.19 SPI Master Mode Timing ................................................................................................ 109
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6.20 SPI Slave Mode Timing ................................................................................................. 113
6.21 External Interface (XINTF) Timing ..................................................................................... 117
6.22 XINTF Signal Alignment to XCLKOUT ................................................................................ 121
6.23 External Interface Read Timing ........................................................................................ 122
6.24 External Interface Write Timing ........................................................................................ 123
6.25 External Interface Ready-on-Read Timing With One External Wait State ....................................... 125
6.26 External Interface Ready-on-Write Timing With One External Wait State ........................................ 128
6.27 XHOLD and XHOLDA ................................................................................................... 131
6.28 XHOLD/XHOLDA Timing ............................................................................................... 132
6.29 On-Chip Analog-to-Digital Converter .................................................................................. 134
6.29.1 ADC Absolute Maximum Ratings ........................................................................... 134
6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions ........................... 135
6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ...................... 136
6.29.4 ADC Power-Up Control Bit Timing .......................................................................... 137
6.29.5 Detailed Description .......................................................................................... 138
6.29.5.1 Reference Voltage ................................................................................ 138
6.29.5.2 Analog Inputs ..................................................................................... 138
6.29.5.3 Converter .......................................................................................... 138
6.29.5.4 Conversion Modes ............................................................................... 138
6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0) ............................................ 138
6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 140
6.29.8 Definitions of Specifications and Terminology ............................................................. 141
6.29.8.1 Integral Nonlinearity .............................................................................. 141
6.29.8.2 Differential Nonlinearity .......................................................................... 141
6.29.8.3 Zero Offset ........................................................................................ 141
6.29.8.4 Gain Error ......................................................................................... 141
6.29.8.5 Signal-to-Noise Ratio + Distortion (SINAD) ................................................... 141
6.29.8.6 Effective Number of Bits (ENOB) ............................................................... 141
6.29.8.7 Total Harmonic Distortion (THD) ............................................................... 141
6.29.8.8 Spurious Free Dynamic Range (SFDR) ....................................................... 141
6.30 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 142
6.30.1 McBSP Transmit and Receive Timing ...................................................................... 142
6.30.2 McBSP as SPI Master or Slave Timing .................................................................... 145
6.31 Flash Timing .............................................................................................................. 149
6.31.1 Recommended Operating Conditions ...................................................................... 149
Mechanical Data .............................................................................................................. 151
7
4
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SGUS062A–JUNE 2009–REVISED APRIL 2010
List of Figures
2-1
SM320F2812 Die Layout........................................................................................................ 15
SM320F2812 172-Pin HFG CQFP (Top View)............................................................................... 16
Functional Block Diagram ....................................................................................................... 28
F2812 Memory Map (See Notes A. Through G.) ............................................................................ 28
External Interface Block Diagram .............................................................................................. 40
Interrupt Sources ................................................................................................................. 42
Multiplexing of Interrupts Using the PIE Block ............................................................................... 43
Clock and Reset Domains ...................................................................................................... 46
OSC and PLL Block.............................................................................................................. 48
Recommended Crystal/Clock Connection .................................................................................... 49
Watchdog Module ................................................................................................................ 50
CPU-Timers ....................................................................................................................... 52
CPU-Timer Interrupts Signals and Output Signal (See Notes A. and B.)................................................. 53
Event Manager A Functional Block Diagram (See Note A.)................................................................ 58
Block Diagram of the F2812 ADC Module .................................................................................... 61
ADC Pin Connections With Internal Reference (See Notes A and B)..................................................... 62
ADC Pin Connections With External Reference ............................................................................. 63
eCAN Block Diagram and Interface Circuit ................................................................................... 66
eCAN Memory Map .............................................................................................................. 67
McBSP Module With FIFO ...................................................................................................... 70
Serial Communications Interface (SCI) Module Block Diagram............................................................ 75
Serial Peripheral Interface Module Block Diagram (Slave Mode).......................................................... 78
GPIO/Peripheral Pin Multiplexing .............................................................................................. 81
28x Device Nomenclature....................................................................................................... 83
SM320F2812-HT Life Expectancy Curve ..................................................................................... 87
Typical Current Consumption Over Frequency............................................................................... 89
Typical Power Consumption Over Frequency................................................................................ 90
F2812 Typical Power-Up and Power-Down Sequence – Option 2 ........................................................ 91
Output Levels ..................................................................................................................... 92
Input Levels ....................................................................................................................... 92
3.3-V Test Load Circuit .......................................................................................................... 93
Clock Timing ...................................................................................................................... 96
Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)................................................... 98
Power-on Reset in Microprocessor Mode (XMP/MC = 1)................................................................... 99
Warm Reset in Microcomputer Mode.......................................................................................... 99
Effect of Writing Into PLLCR Register ......................................................................................... 99
IDLE Entry and Exit Timing.................................................................................................... 100
STANDBY Entry and Exit Timing ............................................................................................. 102
HALT Wakeup Using XNMI ................................................................................................... 104
PWM Output Timing............................................................................................................ 105
TDIRx Timing.................................................................................................................... 106
EVASOC Timing ................................................................................................................ 106
EVBSOC Timing ................................................................................................................ 106
External Interrupt Timing....................................................................................................... 107
General-Purpose Output Timing .............................................................................................. 108
GPIO Input Qualifier – Example Diagram for QUALPRD = 1............................................................. 108
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
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List of Figures
5
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6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
General-Purpose Input Timing ................................................................................................ 109
SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 110
SPI Master External Timing (Clock Phase = 1)............................................................................. 112
SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 114
SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 116
Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 120
Example Read Access ......................................................................................................... 122
Example Write Access ......................................................................................................... 124
Example Read With Synchronous XREADY Access ...................................................................... 126
Example Read With Asynchronous XREADY Access ..................................................................... 127
Write With Synchronous XREADY Access.................................................................................. 129
Write With Asynchronous XREADY Access ................................................................................ 130
External Interface Hold Waveform............................................................................................ 132
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 133
ADC Analog Input Impedance Model ........................................................................................ 137
ADC Power-Up Control Bit Timing ........................................................................................... 137
Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 139
Simultaneous Sampling Mode Timing ....................................................................................... 140
McBSP Receive Timing........................................................................................................ 144
McBSP Transmit Timing ....................................................................................................... 144
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 145
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 146
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 147
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 148
6
List of Figures
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SGUS062A–JUNE 2009–REVISED APRIL 2010
List of Tables
2-1
Hardware Features............................................................................................................... 14
Bare Die Information ............................................................................................................. 15
Signal Descriptions .............................................................................................................. 17
Addresses of Flash Sectors in F2812 ......................................................................................... 29
Wait States ........................................................................................................................ 30
Boot Mode Selection............................................................................................................. 33
Peripheral Frame 0 Registers .................................................................................................. 37
Peripheral Frame 1 Registers .................................................................................................. 37
Peripheral Frame 2 Registers .................................................................................................. 38
Device Emulation Registers..................................................................................................... 39
XINTF Configuration and Control Register Mappings ....................................................................... 41
XREVISION Register Bit Definitions........................................................................................... 41
PIE Peripheral Interrupts ....................................................................................................... 43
PIE Configuration and Control Registers ..................................................................................... 44
External Interrupts Registers ................................................................................................... 45
PLL, Clocking, Watchdog, and Low-Power Mode Registers .............................................................. 47
PLLCR Register Bit Definitions................................................................................................. 48
Possible PLL Configuration Modes ............................................................................................ 49
F2812 Low-Power Modes ....................................................................................................... 51
CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 54
Module and Signal Names for EVA and EVB ................................................................................ 55
EVA Registers ................................................................................................................... 56
ADC Registers ................................................................................................................... 64
3.3-V eCAN Transceivers for the SM320F2812 DSP ....................................................................... 66
CAN Registers Map ............................................................................................................. 68
McBSP Register Summary...................................................................................................... 71
SCI-A Registers .................................................................................................................. 74
SCI-B Registers .................................................................................................................. 74
SPI Registers .................................................................................................................... 77
GPIO Mux Registers ............................................................................................................ 79
GPIO Data Registers ............................................................................................................ 80
Typical Current Consumption by Various Peripherals (at 150 MHz) ..................................................... 90
Recommended Low-Dropout Regulators ..................................................................................... 91
Clock Table and Nomenclature................................................................................................. 94
Input Clock Frequency .......................................................................................................... 94
XCLKIN Timing Requirements – PLL Bypassed or Enabled .............................................................. 95
XCLKIN Timing Requirements – PLL Disabled .............................................................................. 95
Possible PLL Configuration Modes ........................................................................................... 95
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ....................................................... 95
Reset (XRS) Timing Requirements ........................................................................................... 96
IDLE Mode Switching Characteristics ....................................................................................... 100
STANDBY Mode Switching Characteristics ................................................................................ 101
HALT Mode Switching Characteristics ...................................................................................... 103
PWM Switching Characteristics .............................................................................................. 105
Timer and Capture Unit Timing Requirements ............................................................................. 105
External ADC Start-of-Conversion – EVA – Switching Characteristics ................................................. 106
2-2
2-3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
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6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-47
6-48
6-49
6-50
6-51
6-52
6-53
6-54
6-55
6-56
6-57
6-58
6-59
6-60
6-61
6-62
6-63
External ADC Start-of-Conversion – EVB – Switching Characteristics ................................................. 106
Interrupt Switching Characteristics ........................................................................................... 106
Interrupt Timing Requirements................................................................................................ 107
General-Purpose Output Switching Characteristics........................................................................ 107
General-Purpose Input Timing Requirements .............................................................................. 108
SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 109
SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 111
SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 113
SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 115
Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 117
XTIMING Register Configuration Restrictions .............................................................................. 117
Valid and Invalid Timing ....................................................................................................... 117
XTIMING Register Configuration Restrictions .............................................................................. 118
Valid and Invalid Timing when using Synchronous XREADY ............................................................ 118
XTIMING Register Configuration Restrictions .............................................................................. 118
XTIMING Register Configuration Restrictions .............................................................................. 119
Asynchronous XREADY ...................................................................................................... 119
XINTF Clock Configurations................................................................................................... 119
External Memory Interface Read Switching Characteristics ............................................................. 122
External Memory Interface Read Timing Requirements .................................................................. 122
External Memory Interface Write Switching Characteristics .............................................................. 123
External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ....................... 125
External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ............................ 125
Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 125
Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ...................................... 125
External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ........................ 128
Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 128
Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 128
XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 132
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 133
DC Specifications .............................................................................................................. 135
AC Specifications .............................................................................................................. 136
Current Consumption .......................................................................................................... 136
ADC Power-Up Delays ........................................................................................................ 137
Sequential Sampling Mode Timing .......................................................................................... 139
Simultaneous Sampling Mode Timing ....................................................................................... 140
McBSP Timing Requirements ................................................................................................ 142
McBSP Switching Characteristics ........................................................................................... 143
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ............................... 145
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ........................... 145
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ............................... 146
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ........................... 146
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ............................... 147
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ........................... 147
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ............................... 148
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 148
Flash Parameters at 150-MHz SYSCLKOUT .............................................................................. 149
Flash/OTP Access Timing .................................................................................................... 149
8
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6-64
Minimum Required Wait-States at Different Frequencies ................................................................ 149
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10
List of Tables
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SGUS062A–JUNE 2009–REVISED APRIL 2010
Digital Signal Processor
1
Features
12
• High-Performance Static CMOS Technology
– 150 MHz (6.67 ns Cycle Time)
• 128 Bit Security Key/Lock
– Protects Flash/ROM/OTP and L0/L1 SARAM
– Prevents Firmware Reverse Engineering
• Three 32 Bit CPU Timers
– Low Power (1.8 V Core at 135 MHz, 1.9 V,
Core at 150 MHz, 3.3 V I/O) Design
– 3.3 V Flash Voltage
• Motor Control Peripherals
• JTAG Boundary Scan Support(1)
• High-Performance 32 Bit CPU (TMS320C28x)
– 16 × 16 and 32 x 32 MAC Operations
– 16 × 16 Dual MAC
– Two Event Managers (EVA, EVB)
– Compatible to 240xA Devices
• Serial Port Peripherals
– Serial Peripheral Interface (SPI)
– Harvard Bus Architecture
– Atomic Operations
– Two Serial Communications Interfaces
(SCIs), Standard UART
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– 4M Linear Program Address Reach
– 4M Linear Data Address Reach
– Code-Efficient (in C/C++ and Assembly)
– Enhanced Controller Area Network (eCAN)
– Multichannel Buffered Serial Port (McBSP)
With SPI Mode
• 12 Bit ADC, 16 Channels
– 2 × 8 Channel Input Multiplexer
– Two Sample-and-Hold
– Single/Simultaneous Conversions
– Fast Conversion Rate: 80 ns/12.5 MSPS
– TMS320F24x/LF240x Processor Source Code
Compatible
• On-Chip Memory
– Flash Devices: Up to 128K × 16 Flash (Four
8K × 16 and Six 16K × 16 Sectors)
– ROM Devices: Up to 128K × 16 ROM
– 1K × 16 OTP ROM
– L0 and L1: 2 Blocks of 4K × 16 Each
Single-Access RAM (SARAM)
– H0: 1 Block of 8K × 16 SARAM
• Up to 56 Individually Programmable,
Multiplexed General-Purpose Input / Output
(GPIO) Pins
• Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware
• Development Tools Include
– M0 and M1: 2 Blocks of 1K × 16 Each
SARAM
• Boot ROM (4K × 16)
– With Software Boot Modes
– Standard Math Tables
• External Interface
– ANSI C/C++ Compiler/Assembler/Linker
– Supports TMS320C24x™/240x Instructions
– Code Composer Studio™ IDE
– DSP/BIOS™
– JTAG Scan Controllers [Texas Instruments
(TI) or Third-Party]
– Up to 1M Total Memory
– Evaluation Modules
– Programmable Wait States
– Programmable Read/Write Strobe Timing
– Three Individual Chip Selects
• Clock and System Control
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Watchdog Timer Module
• Three External Interrupts
• Peripheral Interrupt Expansion (PIE) Block That
Supports 45 Peripheral Interrupts
– Broad Third-Party Digital Motor Control
Support
• Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks
xxx
xxx
xxx
xxx
xxx
(1) IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port
1
TMS320C24x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TMS320C54x, TMS320C55x, TMS320C28x are trademarks of
Texas Instruments.
eZdsp is a trademark of Spectrum Digital Incorporated.
2
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Features
11
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xxx
1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS
•
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Extreme (–55°C/220°C) Temperature Range(2)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with
design and process enhancements to maximize performance over extended temperatures.
(2) Custom temperature ranges available
12
Features
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2
Introduction
This section provides a summary of the device features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
3
2.1 Description
The SM320F2812 device, member of the C28xE DSP generation, is a highly integrated, high-performance
solution for demanding control applications. The functional blocks and the memory maps are described in
Section 3, Functional Overview.
Throughout this document SM320F2812 is abbreviated as F2812.
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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2.2 Device Summary
Table 2-1 provides a summary of the device features.
Table 2-1. Hardware Features
FEATURE
F2812
6.67 ns
18K
128K
—
Instruction Cycle (at 150 MHz)
Single-Access RAM (SARAM) (16 bit word)
3.3 V On-Chip Flash (16 bit word)
On-Chip ROM (16-bit word)
Code Security for On-Chip Flash/SARAM/OTP/ROM
Boot ROM
Yes
Yes
OTP ROM (1K × 16)
External Memory Interface
Event Managers A and B (EVA and EVB)
• General-Purpose (GP) Timers
• Compare (CMP)/PWM
• Capture (CAP)/QEP Channels
Watchdog Timer
Yes
Yes
EVA, EVB
4
16
6/2
Yes
12 Bit ADC
Yes
• Channels
16
32 Bit CPU Timers
SPI
3
Yes
SCIA, SCIB
SCIA, SCIB
Yes
CAN
McBSP
Yes
Digital I/O Pins (Shared)
External Interrupts
Supply Voltage
56
3
1.8-V Core, (135 MHz) 1.9-V Core
(150 MHz), 3.3-V I/O
Temperature Options
S: –55°C to 220°C
Yes
14
Introduction
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2.3 Die Layout
function.
Figure 2-1. SM320F2812 Die Layout
Table 2-2. Bare Die Information
DIE PAD
COMPOSITI
ON
DIE PAD
COORDINATES
DIE
THICKNESS
BACKSIDE
FINISH
BACKSIDE
POTENTIAL
DIE SIZE
DIE PAD SIZE
219.4 x 207.0 (mils);
5572.0 x 5258.0 (mm)
Silicon with
backgrind
55.0 x 64.0 (mm)
See Table 2-3
11.0 mils
AlCu/TiN
Ground
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2.4 Pin Assignments
129
87
130
86
XZCS6AND7
TESTSEL
XZCS2
131
132
85
84
CANTXA
TRST
TCK
EMU0
V
SS
XA[3]
XWE
133
134
135
83
82
XA[12]
XD[14]
81
80
T4CTRIP/EVBSOC
XHOLDA
136
137
XF_XPLLDIS
XA[13]
79
78
V
DDIO
XA[2]
138
139
V
SS
DD
77
T3CTRIP_PDPINTB
V
V
140
141
76
75
SS
X1/XCLKIN
XA[14]
V
DDIO
142
143
74
73
X2
V
EMU1
XD[15]
XA[15]
DD
XD[11]
XD[10]
144
72
71
145
146
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
XA[16]
70
69
TCLKINB
TDIRB
147
148
68
67
V
DD3VFL
XD[9]
TEST1
149
150
V
66
65
DD
SCITXDA
XA[17]
151
152
TEST2
XD[8]
64
63
153
154
V
SCIRXDA
XA[18]
DDIO
C6TRIP
62
61
155
156
XHOLD
XRS
C5TRIP
60
59
C4TRIP
CAP6_QEPI2
CAP5_QEP4
157
158
XREADY
V
DD1
SS1
58
57
V
159
160
V
SS
CAP4_QEP3
ADCBGREFIN
V
56
55
161
162
V
SSA2
DDA2
DD
T4PWM_T4CMP
V
54
53
163
164
ADCINA7
ADCINA6
ADCINA5
XD[7]
T3PWM_T3CMP
52
165
166
V
51
50
SS
XR/W
PWM12
ADCINA4
ADCINA3
167
168
49
48
ADCINA2
ADCINA1
PWM11
PWM10
169
47
46
45
170
171
ADCINA0
ADCLO
PWM9
PWM8
PWM7
V
SSAIO
172
44
43
1
Figure 2-2. SM320F2812 172-Pin HFG CQFP (Top View)
16
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2.5 Signal Descriptions
Table 2-3 specifies the signals on the F2812 device. All digital inputs are TTL-compatible. All outputs are
3.3 V with CMOS levels. Inputs are not 5 V tolerant. A 100 mA (or 20 mA) pullup/pulldown is used.
Table 2-3. Signal Descriptions(1)
PIN NO.
DIE PAD
X-CENTER
(mm)
DIE PAD
Y-CENTER
(mm)
DIE PAD
NO.
NAME
I/O/Z(2) PU/PD(3)
DESCRIPTION
172-PIN
HFG
XINTF SIGNALS
XA[18]
154
152
149
145
141
138
135
129
127
122
118
116
109
106
101
83
173
171
167
163
157
154
151
145
143
138
134
131
124
121
116
96
42.6
42.6
2281.5
2485.3
2819.6
3182.9
3774.9
4029.4
4401.3
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
4471.5
3927.2
42.6
O/Z
O/Z
–
–
–
–
–
–
–
XA[17]
XA[16]
XA[15]
XA[14]
XA[13]
XA[12]
XA[11]
XA[10]
XA[9]
42.6
O/Z
42.6
O/Z
42.6
O/Z
42.6
O/Z
42.6
O/Z
255.7
474.4
996.5
1492.4
1825.2
2566.0
2937.9
3518.7
5361.5
5361.5
5024.5
2403.5
42.6
O/Z
O/Z
–
–
–
–
–
–
–
–
–
–
O/Z
19-bit XINTF Address Bus
XA[8]
O/Z
XA[7]
O/Z
XA[6]
O/Z
XA[5]
O/Z
XA[4]
O/Z
XA[3]
O/Z
XA[2]
78
91
O/Z
XA[1]
42
49
O/Z
XA[0]
18
24
42.6
O/Z
XD[15]
XD[14]
XD[13]
XD[12]
XD[11]
XD[10]
XD[9]
XD[8]
XD[7]
XD[6]
XD[5]
XD[4]
XD[3]
XD[2]
XD[1]
XD[0]
144
136
95
162
152
110
109
85
3306.9
4277.3
5057.5
5057.5
3382.2
3258.3
2608.4
2312.1
1045.9
42.6
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
42.6
4194.1
4318.1
5361.5
5361.5
5361.5
5361.5
5361.5
4586.0
4281.2
3966.6
3652.0
3337.5
3022.9
2708.3
94
72
71
84
67
77
64
74
16-bit XINTF Data Bus
53
60
38
45
35
42
42.6
32
39
42.6
29
36
42.6
26
33
42.6
23
30
42.6
20
27
42.6
(1) Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are
8 mA.
(2) I = Input, O = Output, Z = High impedance
(3) PU = pin has internal pullup; PD = pin has internal pulldown
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(1)
Table 2-3. Signal Descriptions
(continued)
PIN NO.
DIE PAD
X-CENTER
(mm)
DIE PAD
Y-CENTER
(mm)
DIE PAD
NO.
NAME
I/O/Z(2) PU/PD(3)
DESCRIPTION
172-PIN
HFG
Microprocessor/Microcomputer Mode
Select. Switches between microprocessor
and microcomputer mode. When high,
Zone 7 is enabled on the external interface.
When low, Zone 7 is disabled from the
external interface and on-chip boot ROM
may be accessed instead. This signal is
latched into the XINTCNF2 register on a
reset and the user can modify this bit in
software. The state of the XMP/MC pin is
ignored after reset.
XMP/MC
17
23
2308.2
42.6
I
PD
External Hold Request. XHOLD, when
active (low), requests the XINTF to release
the external bus and place all buses and
strobes into a high-impedance state. The
XINTF releases the bus when any current
access is complete and there are no
pending accesses on the XINTF.
XHOLD
155
174
42.6
2157.6
4137.4
I
PU
External Hold Acknowledge. XHOLDA is
driven active (low) when the XINTF has
granted a XHOLD request. All XINTF buses
and strobe signals are in a high-impedance
state. XHOLDA is released when the
XHOLD signal is released. External devices
should only drive the external bus when
XHOLDA is active (low).
XHOLDA
80
93
5361.5
O/Z
–
XINTF Zone 0 and Zone 1 Chip Select.
XZCS0AND1 is active (low) when an
access to the XINTF Zone 0 or Zone 1 is
performed.
XZCS0AND1
XZCS2
43
86
50
5148.5
5361.5
42.6
42.6
O/Z
O/Z
O/Z
–
–
–
XINTF Zone 2 Chip Select. XZCS2 is active
(low) when an access to the XINTF Zone 2
is performed.
100
146
4844.2
4888.6
XINTF Zone 6 and Zone 7 Chip Select.
XZCS6AND7 is active (low) when an
access to the XINTF Zone 6 or Zone 7 is
performed.
XZCS6AND7
130
Write Enable. Active-low write strobe. The
write strobe waveform is specified, per zone
basis, by the Lead, Active, and Trail periods
in the XTIMINGx registers.
XWE
XRD
82
41
95
48
5361.5
4900.6
4347.5
42.6
O/Z
O/Z
–
–
Read Enable. Active-low read strobe. The
read strobe waveform is specified, per zone
basis, by the Lead, Active, and Trail periods
in the XTIMINGx registers.
NOTE: The XRD and XWE signals are
mutually exclusive.
Read Not Write Strobe. Normally held high.
When low, XR/W indicates write cycle is
active; when high, XR/W indicates read
cycle is active.
XR/W
50
57
5361.5
42.6
755.0
O/Z
–
Ready Signal. Indicates peripheral is ready
to complete the access when asserted to 1.
XREADY can be configured to be a
XREADY
157
176
1972.4
I
PU
synchronous or an asynchronous input.
See the timing diagrams for more details.
18
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NAME
SGUS062A–JUNE 2009–REVISED APRIL 2010
(1)
Table 2-3. Signal Descriptions
(continued)
PIN NO.
DIE PAD
X-CENTER
(mm)
DIE PAD
Y-CENTER
(mm)
DIE PAD
NO.
I/O/Z(2) PU/PD(3)
DESCRIPTION
172-PIN
HFG
JTAG AND MISCELLANEOUS SIGNALS
Oscillator Input – input to the internal
oscillator. This pin is also used to feed an
external clock. The 28× can be operated
with an external clock source, provided that
the proper voltage levels be driven on the
X1/XCLKIN pin. It should be noted that the
X1/XCLKIN pin is referenced to the 1.8-V
(or 1.9-V) core digital power supply (VDD),
rather than the 3.3-V I/O supply (VDDIO). A
clamping diode may be used to clamp a
buffered clock signal to ensure that the
logic-high level does not exceed VDD
(1.8 V or 1.9 V) or a 1.8-V oscillator may be
used.
X1/XCLKIN
75
88
5361.5
3668.7
I
X2
74
87
5361.5
1701.2
3582.6
5057.5
O
O
Oscillator Output
Output clock derived from SYSCLKOUT to
be used for external wait-state generation
and as a general-purpose clock source.
XCLKOUT is either the same frequency,
1/2 the frequency, or 1/4 the frequency of
SYSCLKOUT. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can
be turned off by setting bit 3 (CLKOFF) of
the XINTCNF2 register to 1.
XCLKOUT
117
132
–
Test Pin. Reserved for TI. Must be
connected to ground.
TESTSEL
131
147
42.6
4764.6
I
PD
Device Reset (in) and Watchdog Reset
(out).
Device reset. XRS causes the device to
terminate execution. The PC points to the
address contained at the location
0x3FFFC0. When XRS is brought to a high
level, execution begins at the location
pointed to by the PC. This pin is driven low
by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is
driven low for the watchdog reset duration
of 512 XCLKIN cycles.
XRS
156
175
42.6
2077.8
I/O
PU
The output buffer of this pin is an
open-drain with an internal pullup (100 mA,
typical). It is recommended that this pin be
driven by an open-drain device.
Test Pin. Reserved for TI. On F281x
devices, TEST1 must be left unconnected.
TEST1
TEST2
66
65
76
75
5361.5
5361.5
2522.3
2436.1
I/O
I/O
–
–
Test Pin. Reserved for TI. On F281x
devices, TEST2 must be left unconnected.
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(1)
Table 2-3. Signal Descriptions
(continued)
PIN NO.
DIE PAD
X-CENTER
(mm)
DIE PAD
Y-CENTER
(mm)
DIE PAD
NO.
NAME
I/O/Z(2) PU/PD(3)
DESCRIPTION
172-PIN
HFG
JTAG test reset with internal pulldown.
TRST, when driven high, gives the scan
system control of the operations of the
device. If this signal is not connected or
driven low, the device operates in its
functional mode, and the test reset signals
are ignored.
NOTE: Do not use pullup resistors on
TRST; it has an internal pulldown device. In
a low-noise environment, TRST can be left
floating. In a high-noise environment, an
additional pulldown resistor may be
TRST
132
148
42.6
4684.8
I
PD
needed. The value of this resistor should be
based on drive strength of the debugger
pods applicable to the design. A 2.2-kΩ
resistor generally offers adequate
protection. Since this is application specific,
it is recommended that each target board is
validated for proper operation of the
debugger and the application.
TCK
TMS
133
123
149
139
42.6
4605.1
5057.5
I
I
PU
PU
JTAG test clock with internal pullup
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked
into the TAP controller on the rising edge of
TCK.
872.5
JTAG test data input (TDI) with internal
pullup. TDI is clocked into the selected
register (instruction or data) on a rising
edge of TCK.
TDI
128
124
133
143
144
140
150
161
350.4
777.9
42.6
5057.5
5057.5
4525.3
3430.9
I
PU
–
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction
or data) is shifted out of TDO on the falling
edge of TCK.
TDO
EMU0
EMU1
O/Z
Emulator pin 0. When TRST is driven high,
this pin is used as an interrupt to or from
the emulator system and is defined as
input/output through the JTAG scan.
I/O/Z
I/O/Z
PU
PU
Emulator pin 1. When TRST is driven high,
this pin is used as an interrupt to or from
the emulator system and is defined as
input/output through the JTAG scan.
42.6
20
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SGUS062A–JUNE 2009–REVISED APRIL 2010
(1)
Table 2-3. Signal Descriptions
(continued)
PIN NO.
DIE PAD
X-CENTER
(mm)
DIE PAD
Y-CENTER
(mm)
DIE PAD
NO.
I/O/Z(2) PU/PD(3)
DESCRIPTION
172-PIN
HFG
ADC ANALOG INPUT SIGNALS
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
163
164
165
166
167
168
169
170
9
186
188
190
192
194
196
197
198
13
11
10
8
42.6
42.6
1253.9
1094.3
954.0
794.4
654.1
513.9
434.1
354.3
42.6
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
42.6
Eight-channel analog inputs for
42.6
Sample-and-Hold A. The ADC pins should
not be driven before VDDA1, VDDA2, and
VDDAIO pins have been fully powered up.
42.6
42.6
42.6
42.6
1355.2
1164.6
1069.2
878.6
688.0
497.4
402.1
306.8
8
42.6
7
42.6
Eight-channel analog inputs for
6
42.6
Sample-and-Hold B. The ADC pins should
not be driven before the VDDA1, VDDA2, and
VDDAIO pins have been fully powered up.
5
6
42.6
4
4
42.6
3
3
42.6
2
2
42.6
ADC Voltage Reference Output (2 V).
Requires a low ESR (50 mΩ – 1.5 Ω)
ceramic bypass capacitor of 10 mF to
analog ground. (Can accept external
reference input
ADCREFP
11
15
1545.8
42.6
O
(2 V) if the software bit is enabled for this
mode. 1-mF to 10-mF low ESR capacitor
can be used in the external reference
mode.)
ADC Voltage Reference Output (1 V).
Requires a low ESR (50 mΩ – 1.5 Ω)
ceramic bypass capacitor of 10 mF to
analog ground. (Can accept external
reference input
ADCREFM
10
14
1450.5
42.6
O
(1 V) if the software bit is enabled for this
mode. 1-mF to 10-mF low ESR capacitor
can be used in the external reference
mode.)
ADC External Current Bias Resistor
(24.9 kΩ ±5%)
ADCRESEXT
ADCBGREFIN
16
22
2212.9
42.6
42.63
O
I
Test Pin. Reserved for TI. Must be left
unconnected.
160
180
1680.9
AVSSREFBG
AVDDREFBG
12
13
17
18
1831.7
1736.4
42.6
42.6
I
I
ADC Analog GND
ADC Analog Power (3.3 V)
Common Low Side Analog Input. Connect
to analog ground.
ADCLO
171
199
42.6
274.5
I
VSSA1
VSSA2
VDDA1
VDDA2
VSS1
15
161
14
21
182
19
2117.6
42.6
42.6
1550.7
42.6
I
I
I
I
I
I
ADC Analog GND
ADC Analog GND
1927.0
42.6
ADC Analog 3.3-V Supply
ADC Analog 3.3-V Supply
ADC Digital GND
162
159
158
1
184
178
177
1
1394.2
1830.8
1901.0
42.6
42.6
VDD1
42.6
ADC Digital 1.8-V (or 1.9-V) Supply
3.3-V Analog I/O Power Pin
Analog I/O Ground Pin
VDDAIO
VSSAIO
211.5
42.6
172
200
204.3
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(1)
Table 2-3. Signal Descriptions
(continued)
PIN NO.
DIE PAD
X-CENTER
(mm)
DIE PAD
Y-CENTER
(mm)
DIE PAD
NO.
NAME
I/O/Z(2) PU/PD(3)
DESCRIPTION
172-PIN
HFG
POWER SIGNALS
42.6
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
22
36
55
73
-
29
43
2927.6
4395.4
5361.5
5361.5
5361.5
3861.3
2451.9
663.7
42.6
62
1256.0
3496.4
4671.835
5057.5
5057.5
5057.5
3845.1
2635.3
42.6
86
1.8-V or 1.9-V Core Digital Power Pins. See
Section 6.2, Recommended Operating
Conditions, for voltage requirements.
98
98
110
125
140
150
-
113
125
141
156
169
25
42.6
42.6
2517.7
3871.3
4490.7
5361.5
5361.5
5361.5
5361.5
5361.5
3956.0
3280.5
2357.2
1587.1
569.0
31
37
51
57
-
38
42.6
44
42.6
58
869.2
65
1514.6
2818.6
3754.9
4585.7
5057.5
5057.5
5057.5
5057.5
5057.5
3915.2
3580.8
2705.4
42.6
79
76
84
97
103
111
-
89
97
Core and Digital I/O Ground Pins
112
118
126
133
142
155
159
168
37
126
139
-
42.6
42.6
-
42.6
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
30
63
79
-
3776.0
5361.5
5361.5
4784.7
2262.5
42.6
73
2226.0
4051.2
5057.5
5057.5
3510.7
92
3.3–V I/O Digital Power Pins
105
127
160
112
142
3.3–V Flash Core Power Pin. This pin
should be connected to 3.3 V at all times
after power-up sequence requirements
have been met. This pin is used as VDDIO
in ROM parts and must be connected to
3.3 V in ROM parts as well.
VDD3VFL
68
78
5361.5
2732.4
22
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GPIO
SGUS062A–JUNE 2009–REVISED APRIL 2010
Signal Descriptions (Continued)(1)
PIN NO.
PERIPHERAL
SIGNAL
DIE PAD
DIE PAD
DIE PAD NO.
I/O/Z(2) PU/PD(3)
DESCRIPTION
172-PIN
HFG
X-CENTER Y-CENTER
GPIO OR PERIPHERAL SIGNALS
GPIOA OR EVA SIGNALS
GPIO or PWM
Output Pin #1
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
GPIOA8
GPIOA9
PWM1 (O)
90
91
104
106
107
108
111
114
115
117
119
120
122
129
130
135
136
137
4908.6
4690.0
4566.0
4442.1
4070.1
3766.6
3642.7
3394.7
3185.9
3061.9
2814.0
2073.2
1949.2
1368.4
1244.5
1120.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
5057.5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
GPIO or PWM
Output Pin #2
PWM2 (O)
GPIO or PWM
Output Pin #3
PWM3 (O)
92
GPIO or PWM
Output Pin #4
PWM4 (O)
93
GPIO or PWM
Output Pin #5
PWM5 (O)
96
GPIO or PWM
Output Pin #6
PWM6 (O)
99
GPIO or Timer 1
Output
T1PWM_T1CMP (I)
T2PWM_T2CMP (I)
CAP1_QEP1 (I)
CAP2_QEP2 (I)
100
102
104
105
107
114
115
119
120
121
GPIO or Timer 2
Output
GPIO or Capture
Input #1
GPIO or Capture
Input #2
GPIO or Capture
Input #3
GPIOA10 CAP3_QEPI1 (I)
GPIOA11 TDIRA (I)
GPIO or Timer
Direction
GPIO or Timer Clock
Input
GPIOA12 TCLKINA (I)
GPIOA13 C1TRIP (I)
GPIOA14 C2TRIP (I)
GPIOA15 C3TRIP (I)
GPIO or Compare 1
Output Trip
GPIO or Compare 2
Output Trip
GPIO or Compare 3
Output Trip
GPIOB OR EVB SIGNALS
GPIO or PWM
Output Pin #7
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
PWM7 (O)
44
45
46
47
48
49
52
54
51
52
53
54
55
56
59
61
5361.5
5361.5
5361.5
5361.5
5361.5
5361.5
5361.5
5361.5
211.5
302.1
392.7
483.2
573.8
664.4
955.3
1169.9
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
PU
PU
GPIO or PWM
Output Pin #8
PWM8 (O)
GPIO or PWM
Output Pin #9
PWM9 (O)
GPIO or PWM
Output Pin #10
PWM10 (O)
GPIO or PWM
Output Pin #11
PWM11 (O)
GPIO or PWM
Output Pin #12
PWM12 (O)
GPIO or Timer 3
Output
T3PWM_T3CMP (I)
T4PWM_T4CMP (I)
GPIO or Timer 4
Output
(1) Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
(2) I = Input, O = Output, Z = High impedance
(3) PU = pin has internal pullup; PD = pin has internal pulldown
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Introduction
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(1)
Signal Descriptions (Continued)
(continued)
PIN NO.
PERIPHERAL
SIGNAL
DIE PAD
X-CENTER Y-CENTER
DIE PAD
GPIO
DIE PAD NO.
I/O/Z(2) PU/PD(3)
DESCRIPTION
172-PIN
HFG
GPIO or Capture
Input #4
GPIOB8
GPIOB9
CAP4_QEP3 (I)
CAP5_QEP4 (I)
56
58
59
69
70
60
61
62
64
66
67
81
82
69
71
72
5361.5
5361.5
5361.5
5361.5
5361.5
5361.5
5361.5
5361.5
1428.4
1600.7
1691.3
2990.9
3081.5
1868.1
2044.8
2135.4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
PU
PU
GPIO or Capture
Input #5
GPIO or Capture
Input #6
GPIOB10 CAP6_QEPI2 (I)
GPIOB11 TDIRB (I)
GPIO or Timer
Direction
GPIO or Timer Clock
Input
GPIOB12 TCLKINB (I)
GPIOB13 C4TRIP (I)
GPIOB14 C5TRIP (I)
GPIOB15 C6TRIP (I)
GPIO or Compare 4
Output Trip
GPIO or Compare 5
Output Trip
GPIO or Compare 6
Output Trip
GPIOD OR EVA SIGNALS
Timer 1 Compare
Output Trip
GPIOD0
GPIOD1
T1CTRIP_PDPINTA (I)
108
113
123
128
2690.0
2167.8
5057.5
5057.5
I/O/Z
I/O/Z
PU
PU
Timer 2 Compare
Output Trip or
External ADC
Start-of-Conversion
EV-A
T2CTRIP/EVASOC (I)
GPIOD OR EVB SIGNALS
Timer 3 Compare
Output Trip
GPIOD5
GPIOD6
T3CTRIP_PDPINTB (I)
T4CTRIP/EVBSOC (I)
77
81
90
5361.5
3841.1
4261.4
I/O/Z
I/O/Z
PU
PU
Timer 4 Compare
Output Trip or
External ADC
Start-of-Conversion
EV-B
94
5361.5
GPIOE OR INTERRUPT SIGNALS
GPIO or XINT1 or
XBIO input
GPIOE0
GPIOE1
GPIOE2
XINT1_XBIO (I)
146
148
147
164
166
165
42.6
42.6
42.6
3059.0
2899.4
2979.2
I/O/Z
I/O/Z
I/O/Z
–
–
GPIO or XINT2 or
ADC start of
conversion
XINT2_ADCSOC (I)
XNMI_XINT13 (I)
GPIO or XNMI or
XINT13
PU
GPIOF OR SPI SIGNALS
GPIO or SPI slave
in, master out
GPIOF0
SPISIMOA (O)
39
46
4709.9
42.6
I/O/Z
–
GPIO or SPI slave
out, master in
GPIOF1
GPIOF2
GPIOF3
SPISOMIA (I)
SPICLKA (I/O)
SPISTEA (I/O)
40
33
34
47
40
41
4805.3
4090.6
4185.9
42.6
42.6
42.6
I/O/Z
I/O/Z
I/O/Z
–-
–
GPIO or SPI clock
GPIO or SPI slave
transmit enable
–
GPIOF OR SCI-A SIGNALS
GPIO or SCI
GPIOF4
GPIOF5
SCITXDA (O)
SCIRXDA (I)
151
153
170
172
42.6
42.6
2565.1
2361.3
I/O/Z
I/O/Z
PU
PU
asynchronous serial
port TX data
GPIO or SCI
asynchronous serial
port RX data
24
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SGUS062A–JUNE 2009–REVISED APRIL 2010
(1)
Signal Descriptions (Continued)
(continued)
PIN NO.
DIE PAD
PERIPHERAL
SIGNAL
DIE PAD
GPIO
DIE PAD NO.
172-PIN
I/O/Z(2) PU/PD(3)
DESCRIPTION
X-CENTER Y-CENTER
HFG
GPIOF OR CAN SIGNALS
GPIO or eCAN
transmit data
GPIOF6
GPIOF7
CANTXA (O)
85
87
99
5361.5
5192.7
4758.0
5057.5
I/O/Z
I/O/Z
PU
PU
GPIO or eCAN
receive data
CANRXA (I)
101
GPIOF OR McBSP SIGNALS
GPIO or transmit
clock
GPIOF8
MCLKXA (I/O)
MCLKRA (I/O)
MFSXA (I/O)
MFSRA (I/O)
MDXA (O)
27
24
25
28
21
19
34
31
32
35
28
26
3461.4
3146.8
3242.2
3556.7
2832.3
2613.0
42.6
42.6
42.6
42.6
42.6
42.6
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
–
GPIO or receive
clock
GPIOF9
GPIO or transmit
frame synch
GPIOF10
GPIOF11
GPIOF12
GPIOF13
GPIO or receive
frame synch
GPIO or transmitted
serial data
GPIO or received
serial data
MDRA (I)
PU
GPIOF OR XF CPU OUTPUT SIGNAL
This pin has three
functions:
1. XF –
General-purpose
output pin.
2. XPLLDIS – This
pin is sampled
during reset to check
if the PLL needs to
be disabled. The
PLL will be disabled
if this pin is sensed
low. HALT and
GPIOF14
XF_XPLLDIS (O)
137
153
42.6
4153.3
I/O/Z
PU
STANDBY modes
cannot be used
when the PLL is
disabled.
3. GPIO – GPIO
function
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Introduction
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(1)
Signal Descriptions (Continued)
(continued)
PIN NO.
PERIPHERAL
SIGNAL
DIE PAD
X-CENTER Y-CENTER
DIE PAD
GPIO
DIE PAD NO.
I/O/Z(2) PU/PD(3)
DESCRIPTION
172-PIN
HFG
GPIOG OR SCI-B SIGNALS
GPIO or SCI
GPIOG4
GPIOG5
SCITXDB (O)
88
89
102
103
5098.0
5003.3
5057.5
5057.5
I/O/Z
I/O/Z
–
–
asynchronous serial
port transmit data
GPIO or SCI
asynchronous serial
port receive data
SCIRXDB (I)
NOTE
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions.
26
Introduction
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SGUS062A–JUNE 2009–REVISED APRIL 2010
3
Functional Overview
Memory Bus
TINT0
CPU-Timer 0
CPU-Timer 1
CPU-Timer 2
Real-Time JTAG
TINT2
INT14
Control
External
PIE
(96 interrupts)
Interface
(XINTF)
Address(19)
Data(16)
†
INT[12:1]
TINT1
M0 SARAM
1K x 16
INT13
NMI
XINT13
External Interrupt
Control
(XINT1/2/13, XNMI)
M1 SARAM
1K x 16
XNMI
G
P
I
SCIA/SCIB
SPI
FIFO
FIFO
FIFO
‡
L0 SARAM
4K x 16
O
GPIO Pins
‡
L1 SARAM
4K x 16
McBSP
C28x CPU
M
U
X
eCAN
‡
Flash
EVA/EVB
128K x 16
12-Bit ADC
16 Channels
‡
OTP
System Control
XRS
X1/XCLKIN
X2
1K x 16
RS
(Oscillator and PLL
+
Peripheral Clocking
CLKIN
+
H0 SARAM
8K ⋅ 16
XF_XPLLDIS
Low-Power
Modes
+
Memory Bus
Boot ROM
4K ⋅ 16
WatchDog)
Peripheral Bus
†
45 of the possible 96 interrupts are used on the device.
Protected by the code-security module.
‡
Figure 3-1. Functional Block Diagram
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Functional Overview
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3.1 Memory Map
Block
Start Address
On-Chip Memory
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
0x00 0040
0x00 0400
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
0x00 0800
0x00 0D00
Peripheral Frame 0
Reserved
(2K × 16)
PIE Vector - RAM
(256 × 16)
Reserved
(Enabled if VMAP
= 1, ENPIE = 1)
0x00 0E00
0x00 2000
Reserved
0x00 2000
0x00 4000
XINTF Zone 0 (8K × 16, XZCS0AND1)
XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)
Reserved
0x00 6000
0x00 7000
Peripheral Frame 1
(4K × 16, Protected)
Reserved
Peripheral Frame 2
(4K × 16, Protected)
Reserved
0x00 8000
0x00 9000
0x00 A000
L0 SARAM (4K × 16, Secure Block)
L1 SARAM (4K × 16, Secure Block)
0x08 0000
0x10 0000
0x18 0000
XINTF Zone 2 (0.5M × 16, XZCS2)
XINTF Zone 6 (0.5M × 16, XZCS6AND7)
Reserved
0x3D 7800
OTP (or ROM) (1K × 16, Secure Block)
0x3D 7C00
0x3D 8000
0x3F 7FF8
Reserved (1K)
Reserved
Flash (or ROM) (128K × 16, Secure Block)
128-Bit Password
0x3F 8000
0x3F A000
H0 SARAM (8K × 16)
Reserved
0x3F C000
0x3F F000
0x3F FFC0
XINTF Zone 7 (16K × 16, XZCS6AND7)
Boot ROM (4K × 16)
(Enabled if MP/MC = 1)
(Enabled if MP/MC = 0)
XINTF Vector - RAM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 1, ENPIE = 0)
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
E. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
Figure 3-2. F2812 Memory Map (See Notes A. Through G.)
28
Functional Overview
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Table 3-1. Addresses of Flash Sectors in F2812
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3D 8000
0x3D 9FFF
Sector J, 8K × 16
Sector I, 8K × 16
0x3D A000
0x3D BFFF
0x3D C000
0x3D FFFF
Sector H, 16K × 16
Sector G, 16K × 16
Sector F, 16K × 16
Sector E, 16K × 16
Sector D, 16K × 16
Sector C, 16K × 16
0x3E 0000
0x3E 3FFF
0x3E 4000
0x3E 7FFF
0x3E 8000
0x3E BFFF
0x3E C000
0x3E FFFF
0x3F 0000
0x3F 3FFF
0x3F 4000
0x3F 5FFF
Sector B, 8K × 16
Sector A, 8K × 16
0x3F 6000
0x3F 7F80
0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6
0x3F 7FF7
Boot-to-Flash (or ROM) Entry Point
(program branch instruction here)
0x3F 7FF8
0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
The Low 64K of the memory address range maps into the data space of the 240x. The High 64K of the
memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code only
executes from the High 64K memory area. Hence, the top 32K of Flash/ROM and H0 SARAM block can
be used to run 24x/240x-compatible code (if MP/MC mode is low) or, on the F2812, code can be executed
from XINTF Zone 7 (if MP/MC mode is high).
The XINTF consists of five independent zones. One zone has its own chip select and the remaining four
zones share two chip selects. Each zone can be programmed with its own timing (wait states) and to
either sample or ignore external ready signal. This makes interfacing to external peripherals easy and
glueless.
NOTE
The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select
(XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged together into a
single chip select (XZCS6AND7). See Section 3.5, External Interface, XINTF (2812 only), for
details.
Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these
blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, appears in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected so as to
make sure that operations occur as written (the penalty is extra cycles are added to align the operations).
This mode is programmable and by default, it protects the selected zones.
On the F2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high
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memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows
the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on
reset is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in
software and hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are
affected by XMP/MC.
I/O space is not supported on the F2812 XINTF.
Table 3-2. Wait States
AREA
WAIT-STATES
0-wait
COMMENTS
M0 and M1 SARAMs
Peripheral Frame 0
Fixed
Fixed
0-wait
0-wait (writes)
2-wait (reads)
Peripheral Frame 1
Fixed
Fixed
0-wait (writes)
2-wait (reads)
Peripheral Frame 2
L0 and L1 SARAMs
OTP (or ROM)
0-wait
Programmable,
1-wait minimum
Programmed via the Flash registers. 1-wait-state operation is possible at a reduced
CPU frequency. See Section 3.2.6, Flash (F281x Only), for more information.
Programmed via the Flash registers. 0-wait-state operation is possible at reduced
CPU frequency. The CSM password locations are hardwired for 16 wait-states.
See Section 3.2.6, Flash (F281x Only), for more information.
Programmable,
0-wait minimum
Flash (or ROM)
H0 SARAM
Boot-ROM
0-wait
1-wait
Fixed
Fixed
Programmed via the XINTF registers.
Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
Programmable,
1-wait minimum
XINTF
30
Functional Overview
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3.2 Brief Descriptions
3.2.1 C28x CPU
The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is
source code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their
significant software investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling
users to develop not only their system control software in a high-level language, but also enables math
algorithms to be developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system
control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a
second processor in many systems. The 32 × 32-bit MAC capabilities of the C28x and its 64-bit
processing capabilities, enable the C28x to efficiently handle higher numerical resolution problems that
would otherwise demand a more expensive floating-point processor solution. Add to this the fast interrupt
response with automatic context save of critical registers, resulting in a device that is capable of servicing
many asynchronous events with minimal latency. The C28x has an 8-level-deep protected pipeline with
pipelined memory accesses. This pipelining enables the C28x to execute at high speeds without resorting
to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for
conditional discontinuities. Special store conditional operations further improve performance.
3.2.2 Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus prioritizes memory accesses. Generally, the priority of Memory Bus
accesses can be summarized as follows:
Highest:
Data Writes(1)
Program Writes
Data Reads
Program Reads(2)
Lowest:
Fetches
3.2.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP families, the F2812
adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the
various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines
and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported
on the F2812. One version only supports 16-bit accesses (called peripheral frame 2) and this retains
compatibility with C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses
(called peripheral frame 1).
3.2.4 Real-Time JTAG and Analysis
The F2812 implement the standard IEEE 1149.1 JTAG interface. Additionally, the F2812 supports
real-time mode of operation whereby the contents of memory, peripheral and register locations can be
modified while the processor is running and executing code and servicing interrupts. The user can also
(1) Simultaneous Data and Program writes cannot occur on the Memory Bus.
(2) Simultaneous Program Reads and Fetches cannot occur on the Memory Bus.
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single step through non-time critical code while enabling time-critical interrupts to be serviced without
interference. The F2812 implements the real-time mode in hardware within the CPU. This is a unique
feature to the F2812, no software monitor is required. Additionally, special analysis hardware is provided
which allows the user to set hardware breakpoint or data/address watch-points and generate various user
selectable break events when a match occurs.
3.2.5 External Interface (XINTF)
This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The
chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single
chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed
with a different number of wait states, strobe signal setup and hold timing and each zone can be
programmed for extending wait states externally or not. The programmable wait-state, chip-select, and
programmable strobe timing enables glueless interface to external memories and peripherals.
3.2.6 Flash
The F2812 contains 128K × 16 of embedded flash memory, segregated into four 8K × 16 sectors, and six
16K × 16 sectors. The F2810 has 64K × 16 of embedded flash, segregated into two 8K × 16 sectors, and
three 16K × 16 sectors. The device also contains a single 1K × 16 of OTP memory at address range 0x3D
7800 - 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving
other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute
flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the
flash module to achieve higher performance. The flash/OTP is mapped to both program and data space;
therefore, it can be used to execute code or store data information.
NOTE
The F2812 Flash and OTP wait states can be configured by the application. This allows
applications running at slower frequencies to configure the flash to use fewer wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution is much faster than the raw performance indicated by the wait state configuration
alone. The exact performance gain when using the Flash pipeline mode is
application-dependent. The pipeline mode is not available for the OTP block.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the TMS320x281x System Control and Interrupts Reference Guide (SPRU078).
3.2.7 L0, L1, H0 SARAMs
The F2812 contains an additional 16K × 16 of single-access RAM, divided into three blocks (4K + 4K +
8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block is mapped to
both program and data space.
3.2.8 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after
device reset and checks several GPIO pins to determine which boot mode to enter. For example, the user
can select to execute code already present in the internal Flash or download new software to internal
RAM through one of several serial ports. Other boot modes exist as well. The Boot ROM also contains
details of how various boot modes may be invoked. See the TMS320x281x DSP Boot ROM Reference
Guide (SPRS095), for more information.
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Table 3-3. Boot Mode Selection
GPIOF4
(SCITXDA)
GPIOF12
(MDXA)
GPIOF3
(SPISTEA)
GPIOF2
BOOT MODE SELECTED(1)
(SPICLK)(2)
GPIO PU status(3)
PU
No PU
No PU
No PU
Jump to Flash/ROM address 0x3F 7FF6
A branch instruction must have been programmed here prior to
reset to redirect code execution as desired.
1
x
x
x
Call SPI_Boot to load from an external serial SPI EEPROM
Call SCI_Boot to load from SCI-A
0
0
0
0
0
1
0
0
0
0
x
1
1
0
0
x
1
0
1
0
Jump to H0 SARAM address 0x3F 8000
Jump to OTP address 0x3D 7800
Call Parallel_Boot to load from GPIO Port B
(1) If the boot mode selected is Flash, H0, or OTP, then no external code is loaded by the bootloader.
(2) Extra care must be taken due to any effect toggling SPICLK to select a boot mode may have on external logic.
(3) PU = pin has an internal pullup. No PU = pin does not have an internal pullup
3.2.9 Security
The F2812 supports high levels of security to protect the user firmware from being reversed engineered.
The security features a 128–bit password (hardcoded for 16 wait states), which the user programs into the
flash. One code security module (CSM) is used to protect the flash/ROM/OTP and the L0/L1 SARAM
blocks. The security feature prevents unauthorized users from examining the memory contents via the
JTAG port, executing code from external memory or trying to boot–load some undesirable software that
would export the secure memory contents. To enable access to the secure blocks, the user must write the
correct 128–bit KEY value, which matches the value stored in the password locations within the
Flash/ROM.
NOTE
For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be
used as program code or data, but must be programmed to 0x0000 when the Code Security
Passwords are programmed. If security is not a concern, then these addresses may be used
for code or data.
The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing
so would permanently lock the device.
Code Security Module Disclaimer
The Code Security Module (CSM) included on this device was designed to password
protect the data stored in the associated memory (either ROM or Flash) and is warranted
by Texas Instruments (TI), in accordance with its standard terms and conditions, to
conform to TI’s published specifications for the warranty period applicable for this device.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT
BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE
ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.
MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
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IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING
IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR
NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS
OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
3.2.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F2812, 45 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12
CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is, automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI)
The F2812 supports three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one
non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts
can be selected for negative or positive edge triggering and can also be enabled/disabled (including the
XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a
valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.
3.2.12 Oscillator and PLL
The F2812 can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.13 Watchdog
The F2812 supports a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog generates a reset to the processor. The watchdog
can be disabled if necessary.
3.2.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the
event managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of
peripherals to be decoupled from increasing CPU clock speeds.
3.2.15 Low-Power Modes
The F2812 device is a full-static CMOS device. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively
and only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral wakes the processor from IDLE mode.
STANDBY: Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event wakes the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event.
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HALT:
Turn off oscillator. This mode basically shuts down the device and places it in the
lowest possible power consumption mode. Only a reset or XNMI wakes the
device from this mode.
3.2.16 Peripheral Frames 0, 1, 2 (PFn)
The F2812 segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0:
XINTF:
PIE:
External Interface Configuration Registers (2812 only)
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Control, Programming, Erase, Verify Registers
CPU-Timers 0, 1, 2 Registers
Flash:
Timers:
CSM:
eCAN:
SYS:
Code Security Module KEY Registers
PF1:
PF2:
eCAN Mailbox and Control Registers
System Control Registers
GPIO:
EV:
GPIO Mux Configuration and Control Registers
Event Manager (EVA/EVB) Control Registers
McBSP Control and TX/RX Registers
McBSP:
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Peripheral Interface (SPI) Control and RX/TX Registers
12-Bit ADC Registers
SPI:
ADC:
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the
user to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are
configured as inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches.
3.2.18 32-Bit CPU Timers (0, 1, 2)
CPU Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU Timer 2 is
reserved for Real-Time OS (RTOS)/BIOS applications. CPU Timer 1 is also reserved for TI system
functions. CPU Timer 2 is connected to INT14 of the CPU. CPU Timer 1 can be connected to INT13 of the
CPU. CPU Timer 0 is for general use and is connected to the PIE block.
3.2.19 Control Peripherals
The F2812 supports the following peripherals which are used for embedded control and communication:
EV:
The event manager module includes general-purpose timers, full-compare/PWM units,
capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event
managers are provided which enable two three-phase motors to be driven or four
two-phase motors. The event managers on the F2812 is compatible to the event
managers on the 240x devices (with some minor enhancements).
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
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3.2.20 Serial Port Peripherals
The F2812 supports the following serial communication peripherals:
eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
McBSP This is the multichannel buffered serial port that is used to connect to E1/T1 lines,
:
phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC
devices. The McBSP receive and transmit registers are supported by a 16-level FIFO.
This significantly reduces the overhead for servicing this peripheral.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between
the DSP controller and external peripherals or another processor. Typical applications
include external I/O or peripheral expansion through devices such as shift registers,
display drivers, and ADCs. Multi-device communications are supported by the
master/slave operation of the SPI. On the F2812, the port supports a 16-level receive
and transmit FIFO for reducing servicing overhead.
SCI:
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F2812, the port supports a 16-level receive and transmit FIFO
for reducing servicing overhead.
3.3 Register Map
The F2812 device contains three peripheral register spaces. The spaces are categorized as follows:
•
•
•
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
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Table 3-4. Peripheral Frame 0 Registers(1)
NAME
ADDRESS RANGE
SIZE (×16)
ACCESS TYPE(2)
0x00 0880
0x00 09FF
Device Emulation Registers
reserved
384
EALLOW protected
0x00 0A00
0x00 0A7F
128
96
0x00 0A80
0x00 0ADF
EALLOW protected
CSM Protected
FLASH Registers(3)
Code Security Module Registers
reserved
0x00 0AE0
0x00 0AEF
16
EALLOW protected
0x00 0AF0
0x00 0B1F
48
0x00 0B20
0x00 0B3F
XINTF Registers
reserved
32
Not EALLOW protected
Not EALLOW protected
0x00 0B40
0x00 0BFF
192
64
0x00 0C00
0x00 0C3F
CPU-TIMER0/1/2 Registers
reserved
0x00 0C40
0x00 0CDF
160
32
0x00 0CE0
0x00 0CFF
PIE Registers
Not EALLOW protected
EALLOW protected
0x00 0D00
0x00 0DFF
PIE Vector Table
Reserved
256
512
0x00 0E00
0x00 0FFF
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS
instruction disables writes. This prevents stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-5. Peripheral Frame 1 Registers(1)
NAME
ADDRESS RANGE
SIZE (×16)
ACCESS TYPE
0x00 6000
0x00 60FF
256
(128 × 32)
Some eCAN control registers (and selected bits in
other eCAN control registers) are EALLOW-protected.
eCAN Registers
0x00 6100
0x00 61FF
256
(128 × 32)
eCAN Mailbox RAM
reserved
Not EALLOW-protected
0x00 6200
0x00 6FFF
3584
(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
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Table 3-6. Peripheral Frame 2 Registers(1)
NAME
ADDRESS RANGE
SIZE (×16)
ACCESS TYPE
0x00 7000
0x00 700F
reserved
16
0x00 7010
0x00 702F
System Control Registers
reserved
32
16
EALLOW Protected
0x00 7030
0x00 703F
0x00 7040
0x00 704F
SPI-A Registers
SCI-A Registers
reserved
16
Not EALLOW Protected
Not EALLOW Protected
0x00 7050
0x00 705F
16
0x00 7060
0x00 706F
16
0x00 7070
0x00 707F
External Interrupt Registers
reserved
16
Not EALLOW Protected
0x00 7080
0x00 70BF
64
0x00 70C0
0x00 70DF
GPIO Mux Registers
GPIO Data Registers
ADC Registers
reserved
32
EALLOW Protected
0x00 70E0
0x00 70FF
32
Not EALLOW Protected
Not EALLOW Protected
0x00 7100
0x00 711F
32
0x00 7120
0x00 73FF
736
64
0x00 7400
0x00 743F
EV-A Registers
reserved
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
0x00 7440
0x00 74FF
192
64
0x00 7500
0x00 753F
EV-B Registers
reserved
0x00 7540
0x00 774F
528
16
0x00 7750
0x00 775F
SCI-B Registers
reserved
0x00 7760
0x00 77FF
160
64
0x00 7800
0x00 783F
McBSP Registers
reserved
0x00 7840
0x00 7FFF
1984
(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
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3.4 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
Table 3-7. Device Emulation Registers
NAME
DEVICECNF
reserved
ADDRESS RANGE
SIZE (×16)
DESCRIPTION
Device Configuration Register
0x00 0880
0x00 0881
2
1
0x00 0882
Not supported on Revision C and later silicon
Device ID Register (0x0003 – Silicon – Rev. C and D)
Device ID Register (0x0004 – Reserved)
DEVICEID
0x00 0883
1
Device ID Register (0x0005 – Silicon – Rev. E)
PROTSTART
PROTRANGE
0x00 0884
0x00 0885
1
1
Block Protection Start Address Register
Block Protection Range Address Register
0x00 0886
0x00 09FF
reserved
378
3.5 External Interface, XINTF
This section gives a top-level view of the external interface (XINTF) that is implemented on the F2812
device.
The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The
Figure 3-3 shows the F2812 XINTF signals.
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Data Space
Prog Space
0x00 0000
XD(15:0)
XA(18:0)
0x00 2000
0x00 4000
XINTF Zone 0
XZCS0
XZCS1
(8K × 16)
XZCS0AND1
XINTF Zone 1
(8K × 16)
0x00 6000
0x08 0000
XINTF Zone 2
(512K × 16)
XZCS2
0x10 0000
XINTF Zone 6
(512K × 16)
XZCS6
XZCS7
XZCS6AND7
0x18 0000
0x3F C000
XINTF Zone 7
(16K × 16)
(mapped here if MP/MC = 1)
0x40 0000
XWE
XRD
XR/W
XREADY
XMP/MC
XHOLD
XHOLDA
XCLKOUT
A. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of
XINTCNF2 register). Zones 0, 1, 2, and 6 are always enabled.
B. Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip
selects (XZCS0AND1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These
features enable glueless connection to many external memories and peripherals.
C. The chip selects for Zone 0 and 1 are ANDed internally together to form one chip select (XZCS0AND1). Any external
memory that is connected to XZCS0AND1 is dually mapped to both Zones 0 and Zone 1.
D. The chip selects for Zone 6 and 7 are ANDed internally together to form one chip select (XZCS6AND7). Any external
memory that is connected to XZCS6AND7 is dually mapped to both Zones 6 and Zone 7. This means that if Zone 7 is
disabled (via the MP/MC mode) then any external memory is still accessible via Zone 6 address space.
Figure 3-3. External Interface Block Diagram
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The operation and timing of the external interface, can be controlled by the registers listed in Table 3-8.
Table 3-8. XINTF Configuration and Control Register Mappings
NAME
ADDRESS
SIZE (×16)
DESCRIPTION
XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit
register
XTIMING0
0x00 0B20
2
XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit
register
XTIMING1
XTIMING2
XTIMING6
XTIMING7
XINTCNF2
0x00 0B22
0x00 0B24
0x00 0B2C
0x00 0B2E
0x00 0B34
2
2
2
2
2
XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit
register
XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit
register
XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit
register
XINTF Configuration Register can access as two 16-bit registers or one 32-bit
register
XBANK
0x00 0B38
0x00 0B3A
1
1
XINTF Bank Control Register
XINTF Revision Register
XREVISION
3.5.1 Timing Registers
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold
times to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters
can be configured individually for each zone. This allows the programmer to maximize the efficiency of the
bus, based on the type of memory or peripheral that the user needs to access. All XINTF timing values
are with respect to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure
6-27.
For detailed information on the XINTF timing and configuration register bit fields, see the TMS320x281x
DSP External Interface (XINTF) Reference Guide (SPRU067).
3.5.2 XREVISION Register
The XREVISION register contains a unique number to identify the particular version of XINTF used in the
Table 3-9. XREVISION Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
Current XINTF Revision. For internal use/reference. Test purposes only.
Subject to change.
15-0
REVISION
R
0x0004
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3.6 Interrupts
Figure 3-4 shows how the various interrupt sources are multiplexed within the F2812 device.
Peripherals (SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
WDINT
Watchdog
WAKEINT
LPMINT
Low-Power Modes
XINT1
Interrupt Control
PIE
XINT1CR(15:0)
XINT1CTR(15:0)
INT1 to INT12
XINT2
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
C28x CPU
GPIO
MUX
TINT0
TIMER 0
TINT2
TINT1
TIMER 2 (for RTOS)
TIMER 1 (for RTOS)
INT14
INT13
select
enable
NMI
XNMI_XINT13
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
†
Out of a possible 96 interrupts, 45 are currently used by peripherals.
Figure 3-4. Interrupt Sources
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the F2812, 45 of these are used by peripherals as
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IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals or
External
INTx
MUX
INTx.6
INTx.7
INTx.8
Interrupts
PIEACKx
(Enable)
(Flag)
(Enable/Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
Figure 3-5. Multiplexing of Interrupts Using the PIE Block
Table 3-10. PIE Peripheral Interrupts(1)
PIE INTERRUPTS
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
PDPINTB
(EV-B)
PDPINTA
(EV-A)
INT1
INT2
INT3
INT4
INT5
INT6
XINT2
XINT1
reserved
T1OFINT
(EV-A)
T1UFINT
(EV-A)
T1CINT
(EV-A)
T1PINT
(EV-A)
CMP3INT
(EV-A)
CMP2INT
(EV-A)
CMP1INT
(EV-A)
reserved
reserved
reserved
reserved
reserved
CAPINT3
(EV-A)
CAPINT2
(EV-A)
CAPINT1
(EV-A)
T2OFINT
(EV-A)
T2UFINT
(EV-A)
T2CINT
(EV-A)
T2PINT
(EV-A)
T3OFINT
(EV-B)
T3UFINT
(EV-B)
T3CINT
(EV-B)
T3PINT
(EV-B)
CMP6INT
(EV-B)
CMP5INT
(EV-B)
CMP4INT
(EV-B)
CAPINT6
(EV-B)
CAPINT5
(EV-B)
CAPINT4
(EV-B)
T4OFINT
(EV-B)
T4UFINT
(EV-B)
T4CINT
(EV-B)
T4PINT
(EV-B)
MXINT
(McBSP)
MRINT
(McBSP)
SPITXINTA
(SPI)
SPIRXINTA
(SPI)
reserved
reserved
reserved
INT7
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ECAN1INT
(CAN)
ECAN0INT
(CAN)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT9
reserved
reserved
INT10
INT11
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
(1) Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However,
these interrupts can be used as software interrupts if they are enabled at the PIEIFRx level.
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Table 3-11. PIE Configuration and Control Registers(1)
NAME
PIECTRL
ADDRESS
0x0000-0CE0
0x0000-0CE1
0x0000-0CE2
0x0000-0CE3
0x0000-0CE4
0x0000-0CE5
0x0000-0CE6
0x0000-0CE7
0x0000-0CE8
0x0000-0CE9
0x0000-0CEA
0x0000-0CEB
0x0000-0CEC
0x0000-0CED
0x0000-0CEE
0x0000-0CEF
0x0000-0CF0
0x0000-0CF1
0x0000-0CF2
0x0000-0CF3
0x0000-0CF4
0x0000-0CF5
0x0000-0CF6
0x0000-0CF7
0x0000-0CF8
0x0000-0CF9
SIZE (×16)
DESCRIPTION
PIE, Control Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
0x0000-0CFA
0x0000-0CFF
Reserved
6
Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.
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3.6.1 External Interrupts
Table 3-12. External Interrupts Registers
NAME
XINT1CR
ADDRESS
SIZE (×16)
DESCRIPTION
XINT1 control register
0x00 7070
0x00 7071
1
1
XINT2CR
XINT2 control register
0x00 7072
0x00 7076
reserved
5
XNMICR
0x00 7077
0x00 7078
0x00 7079
1
1
1
XNMI control register
XINT1 counter register
XINT2 counter register
XINT1CTR
XINT2CTR
0x00 707A
0x00 707E
reserved
5
1
XNMICTR
0x00 707F
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For
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3.7 System Control
This section describes the F2812 oscillator, PLL and clocking mechanisms, the watchdog function and the
discussed.
See Note A
A. CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 3-6. Clock and Reset Domains
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The PLL, clocking, watchdog, and low-power modes are controlled by the registers listed in Table 3-13.
Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers(1)
NAME
reserved
ADDRESS
SIZE (×16)
DESCRIPTION
0x00 7010
0x00 7017
8
reserved
reserved
HISPCP
LOSPCP
PCLKCR
reserved
LPMCR0
LPMCR1
reserved
PLLCR
0x00 7018
0x00 7019
0x00 701A
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
0x00 7021
0x00 7022
0x00 7023
0x00 7024
0x00 7025
1
1
1
1
1
1
1
1
1
1
1
1
1
1
High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock
Peripheral Clock Control Register
Low Power Mode Control Register 0
Low Power Mode Control Register 1
PLL Control Register(2)
SCSR
System Control & Status Register
Watchdog Counter Register
WDCNTR
reserved
WDKEY
Watchdog Reset Key Register
Watchdog Control Register
0x00 7026
0x00 7028
reserved
WDCR
3
1
6
0x00 7029
0x00 702A
0x00 702F
reserved
(1) All of the above registers can only be accessed by executing the EALLOW instruction.
(2) The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio)
does not reset PLLCR.
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3.8 OSC and PLL Block
Figure 3-7 shows the OSC and PLL block on the F2812.
XPLLDIS
Latch
XRS
XF_XPLLDIS
OSCCLK (PLL Disabled)
X1/XCLKIN
XCLKIN
0
1
CLKIN
CPU
SYSCLKOUT
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
4-Bit PLL Select
X2
PLL
4-Bit PLL Select
PLL Block
Figure 3-7. OSC and PLL Block
The on-chip oscillator circuit enables a crystal to be attached to the F2812 device using the X1/XCLKIN
and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to the
X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not exceed
VDD. The PLLCR bits [3:0] set the clocking ratio.
Table 3-14. PLLCR Register Bit Definitions
BIT(S)
NAME
TYPE
XRS RESET(1)
DESCRIPTION
15:04
reserved
R = 0
0:00
SYSCLKOUT = (XCLKIN x n)/2, where n is the PLL multiplication factor.
Bit Value
n
SYSCLKOUT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL Bypassed XCLKIN/2
1
2
XCLKIN/2
XCLKIN
3
4
5
6
7
8
9
10
11
12
13
14
15
XCLKIN × 1.5
XCLKIN × 2
XCLKIN × 2.5
XCLKIN × 3
XCLKIN × 3.5
XCLKIN × 4
XCLKIN × 4.5
XCLKIN × 5
Reserved
Reserved
Reserved
Reserved
Reserved
3:00
DIV
R/W
0,0,0,0
(1) The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not
changed.
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3.8.1 Loss of Input Clock
In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL still
issues a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1 MHz to 4 MHz. The PLLCR register should have been written to with a non-zero value for
this feature to work.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog
reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops
decrementing (i.e., the watchdog counter does not change with the limp-mode clock). This condition could
be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.
3.9 PLL-Based Clock Module
The F2812 has an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control to
select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR
register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131 072
XCLKIN cycles.
The PLL-based clock module provides two modes of operation:
•
Crystal operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
•
External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an
external clock source input on the X1/XCLKIN pin.
X1/XCLKIN
X2
X1/XCLKIN
X2
External Clock Signal
C
b1
C
b2
(Toggling 0−V
)
DD
(see Note A)
Crystal
(a)
(see Note A)
NC
(b)
A. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the
DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also
advise the customer regarding the proper tank component values that ensures start-up and stability over the entire
operating range.
Figure 3-8. Recommended Crystal/Clock Connection
Table 3-15. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled. Clock input
to the CPU (CLKIN) is directly derived from the clock signal present at the X1/XCLKIN pin.
PLL Disabled
XCLKIN
Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is bypassed.
However, the /2 module in the PLL block divides the clock input at the X1/XCLKIN pin by
two before feeding it to the CPU.
PLL Bypassed
PLL Enabled
XCLKIN/2
Achieved by writing a non-zero value n into PLLCR register. The /2 module in the PLL block
now divides the output of the PLL by two before feeding it to the CPU.
(XCLKIN × n) / 2
3.10 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
•
•
Fundamental mode, parallel resonant
CL (load capacitance) = 12 pF
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•
•
•
CL1 = CL2 = 24 pF
Cshunt = 6 pF
ESR range = 25 to 40 Ω
3.11 Watchdog Block
The watchdog block on the F2812 is identical to the one used on the 240x devices. The watchdog module
generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter
has reached its maximum value. To prevent this, the user disables the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register which resets the watchdog
WDCR (WDPS(2:0))
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
WDCLK
8-Bit
Watchdog
Counter
CLR
Watchdog
Prescaler
/512
Clear Counter
Internal
Pullup
WDKEY(7:0)
WDRST
WDINT
Generate
Output Pulse
(512 OSCCLKs)
Bad Key
Watchdog
55 + AA
Key Detector
Good Key
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK(2:0))
1
0
1
WDRST
(See Note A)
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-9. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module runs off the PLL clock or the oscillator clock. The
WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See
Section 3.12, Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so
is the WATCHDOG.
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3.12 Low-Power Modes Block
modes.
Table 3-16. F2812 Low-Power Modes
MODE
LPM(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
Normal
X,X
on
on
on
–
XRS,
WDINT,
IDLE
0,0
on
on
on(2)
Any Enabled Interrupt,
XNMI
Debugger(3)
XRS,
WDINT,
XINT1,
XNMI,
on
T1/2/3/4CTRIP,
C1/2/3/4/5/6TRIP,
SCIRXDA,
SCIRXDB,
CANRX,
STANDBY
0,1
1,X
off
off
off
off
(watchdog still running)
Debugger(3)
off
XRS,
XNMI,
HALT
(oscillator and PLL turned off,
watchdog not functional)
Debugger(4)
(1) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the IDLE
mode is not exited and the device goes back into the indicated low power mode.
(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
(3) On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
(4) On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized
by the processor. The LPM block performs no tasks during this mode as long
as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode: All other signals (including XNMI) wake the device from STANDBY mode if
selected by the LPMCR1 register. The user needs to select which signal(s)
wakes the device. The selected signal(s) are also qualified by the OSCCLK
before waking the device. The number of OSCCLKs is specified in the
LPMCR0 register.
HALT Mode:
Only the XRS and XNMI external signals can wake the device from HALT
mode. The XNMI input to the core has an enable/disable bit. Hence, it is safe
to use the XNMI signal for this function.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included). They
are in whatever state the code left them in when the IDLE instruction was executed.
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4
Peripherals
The integrated peripherals of the F2812 are described in the following subsections:
•
•
•
•
•
•
•
•
Three 32-bit CPU-Timers
Two event-manager modules (EVA, EVB)
Enhanced analog-to-digital converter (ADC) module
Enhanced controller area network (eCAN) module
Multichannel buffered serial port (McBSP) module
Serial communications interface modules (SCI-A, SCI-B)
Serial peripheral interface (SPI) module
Digital I/O and shared pin functions
4.1 32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the F2812 devices (CPU-TIMER0/1/2).
CPU-Timers 1 and 2 are reserved for the real-time OS (such as DSP/BIOS). CPU-Timer 0 can be used in
user applications. These timers are different from the general-purpose (GP) timers that are present in the
Event Manager modules (EVA, EVB).
NOTE
If the application is not using DSP/BIOS, then CPU-Timers 1 and 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
32-Bit Timer Period
TDDRH:TDDR
PRDH:PRD
16-Bit Prescale Counter
SYSCLKOUT
PSCH:PSC
TCR.4
32-Bit Counter
TIMH:TIM
(Timer Start Status)
Borrow
Borrow
TINT
Figure 4-1. CPU-Timers
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In the F2812 device, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
INT1
to
TINT0
PIE
CPU-TIMER 0
INT12
C28x
CPU-TIMER 1
(Reserved for TI
system functions)
TINT1
INT13
INT14
XINT13
CPU-TIMER 2
(Reserved for TI
system functions)
TINT2
A. The timer registers are connected to the Memory Bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4-2. CPU-Timer Interrupts Signals and Output Signal (See Notes A. and B.)
The general operation of the timer is as follows: The 32-bit counter register TIMH:TIM is loaded with the
value in the period register PRDH:PRD. The counter register, decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x281x
System Control and Interrupts Reference Guide (literature number SPRU078).
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Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
0x00 0C00
0x00 0C01
0x00 0C02
0x00 0C03
0x00 0C04
0x00 0C05
0x00 0C06
0x00 0C07
0x00 0C08
0x00 0C09
0x00 0C0A
0x00 0C0B
0x00 0C0C
0x00 0C0D
0x00 0C0E
0x00 0C0F
0x00 0C10
0x00 0C11
0x00 0C12
0x00 0C13
0x00 0C14
0x00 0C15
0x00 0C16
0x00 0C17
SIZE (×16)
DESCRIPTION
TIMER0TIM
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU-Timer 0, Counter Register
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
reserved
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
TIMER2TPR
TIMER2TPRH
CPU-Timer 2, Prescale Register
CPU-Timer 2, Prescale Register High
0x00 0C18
0x00 0C3F
reserved
40
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4.2 Event Manager Modules (EVA, EVB)
The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units,
and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units
function identically. However, timer/unit names differ for EVA and EVB. Table 4-2 shows the module and
modules and highlights EVA nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB
starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units,
capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to
information, see the TMS320x281x DSP Event Manager (EV) Reference Guide (literature number
SPRU065).
Table 4-2. Module and Signal Names for EVA and EVB
EVA
EVB
EVENT MANAGER MODULES
GP Timers
MODULE
SIGNAL
MODULE
SIGNAL
GP Timer 1
GP Timer 2
T1PWM/T1CMP
T2PWM/T2CMP
GP Timer 3
GP Timer 4
T3PWM/T3CMP
T4PWM/T4CMP
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare 4
Compare 5
Compare 6
PWM7/8
PWM9/10
PWM11/12
Compare Units
Capture Units
Capture 1
Capture 2
Capture 3
CAP1
CAP2
CAP3
Capture 4
Capture 5
Capture 6
CAP4
CAP5
CAP6
QEP1
QEP2
QEPI1
QEP3
QEP4
QEPI2
QEP1
QEP2
QEP3
QEP4
QEP Channels
Direction
External Clock
TDIRA
TCLKINA
Direction
External Clock
TDIRB
TCLKINB
External Clock Inputs
External Trip Inputs
C1TRIP
C2TRIP
C3TRIP
C4TRIP
C5TRIP
C6TRIP
Compare
Compare
T1CTRIP_PDPINTA
(1)
T3CTRIP_PDPINTB
T4CTRIP/EVBSOC
(1)
External Trip Inputs
T2CTRIP/EVASOC
(1) In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as
PDPINTB.
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Table 4-3. EVA Registers(1)
NAME
GPTCONA
T1CNT
ADDRESS
0x00 7400
SIZE (×16)
DESCRIPTION
GP Timer Control Register A
GP Timer 1 Counter Register
GP Timer 1 Compare Register
GP Timer 1 Period Register
GP Timer 1 Control Register
GP Timer 2 Counter Register
GP Timer 2 Compare Register
GP Timer 2 Period Register
GP Timer 2 Control Register
GP Extension Control Register A
Compare Control Register A
Compare Action Control Register A
Dead–Band Timer Control Register A
Compare Register 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0x00 7401
0x00 7402
0x00 7403
0x00 7404
0x00 7405
0x00 7406
0x00 7407
0x00 7408
0x00 7409
0x00 7411
0x00 7413
0x00 7415
0x00 7417
0x00 7418
0x00 7419
0x00 7420
0x00 7422
0x00 7423
0x00 7424
0x00 7425
0x00 7427
0x00 7428
0x00 7429
0x00 742C
0x00 742D
0x00 742E
0x00 742F
0x00 7430
0x00 7431
T1CMPR
T1PR
T1CON
T2CNT
T2CMPR
T2PR
T2CON
EXTCONA(2)
COMCONA
ACTRA
DBTCONA
CMPR1
CMPR2
Compare Register 2
CMPR3
Compare Register 3
CAPCONA
CAPFIFOA
CAP1FIFO
CAP2FIFO
CAP3FIFO
CAP1FBOT
CAP2FBOT
CAP3FBOT
EVAIMRA
EVAIMRB
EVAIMRC
EVAIFRA
EVAIFRB
EVAIFRC
Capture Control Register A
Capture FIFO Status Register A
Two-Level Deep Capture FIFO Stack 1
Two-Level Deep Capture FIFO Stack 2
Two–Level Deep Capture FIFO Stack 3
Bottom Register Of Capture FIFO Stack 1
Bottom Register Of Capture FIFO Stack 2
Bottom Register Of Capture FIFO Stack 3
Interrupt Mask Register A
Interrupt Mask Register B
Interrupt Mask Register C
Interrupt Flag Register A
Interrupt Flag Register B
Interrupt Flag Register C
(1) The EV-B register set is identical except the address range is from 0x00–7500 to 0x00–753F. The above registers are mapped to Zone
2. This space allows only 16-bit accesses. 32-bit accesses produce undefined results.
(2) New register compared to 24x/240x
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GPTCONA(12:4), CAPCONA(8), EXTCONA[0]
Control Logic
EVAENCLK
EVATO ADC (Internal)
T1CTRIP/PDPINTA, T2CTRIP, C1TRIP, C2TRIP, C3TRIP
EVASOC ADC (External)
Output
T1PWM_T1CMP
Logic
Timer 1 Compare
T1CON(1)
T1CON(5,4)
GPTCONA(1,0)
Prescaler
TCLKINA
HSPCLK
clock
dir
GP Timer 1
T1CON(10:8)
TDIRA
T1CON(15:11,6,3,2)
PWM1
PWM2
PWM3
Full Compare 1
Full Compare 2
Full Compare 3
SVPWM
State
Output
Logic
Dead
-
Band
Logic
PWM4
PWM5
PWM6
Machine
DBTCONA(15:0)
COMCONA(15:5,2:0)
ACTRA(15:12),
COMCONA(12),
T1CON(13:11)
ACTRA(11:0)
Output
Logic
Timer 2 Compare
T2CON(1)
T2PWM_T2CMP
T2CON(5,4)
GPTCONA(3,2)
TCLKINA
HSPCLK
clock
dir
Prescaler
GP Timer 2
QEPCLK
QEPDIR
reset
T2CON(10:8)
T2CON(15:11,7,6,3,2,0)
QEP
Logic
CAPCONA(10,9)
TDIRA
CAP1_QEP1
CAP2_QEP2
Capture Units
CAP3_QEPI1
Index Qual
CAPCONA(15:12,7:0)
EXTCONA(1:2)
A. The EVB module is similar to the EVA module.
Figure 4-3. Event Manager A Functional Block Diagram (See Note A.)
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4.2.1 General-Purpose (GP) Timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
•
•
•
•
•
•
•
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-control register, TxCON, for reads or writes
Selectable internal or external input clocks
A programmable prescaler for internal or external clock inputs
Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
•
A selectable direction input pin (TDIRx) (to count up or down when directional up- / down-count mode
is selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There
are three continuous modes of operations for each GP timer in up- or up / down-counting operations.
Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also
provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM
circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering
of the period and compare registers allows programmable change of the timer (PWM) period and the
compare/PWM pulse width as needed.
4.2.2 Full-Compare Units
There are three full-compare units on each event manager. These compare units use GP timer1 as the
time base and generate six outputs for compare and PWM-waveform generation using programmable
deadband circuit. The state of each of the six outputs is configured independently. The compare registers
of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse
widths as needed.
4.2.3 Programmable Deadband Generator
Deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit
output signal. The output states of the deadband generator are configurable and changeable as needed
by way of the double-buffered ACTRx register.
4.2.4 PWM Waveform Generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two
independent PWMs by the GP-timer compares.
4.2.5 Double Update PWM Mode
The F2812 Event Manager supports Double Update PWM Mode. This mode refers to a PWM operation
mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse are
independently modifiable in each PWM period. To support this mode, the compare register that
determines the position of the edges of a PWM pulse must allow (buffered) compare value update once at
the beginning of a PWM period and another time in the middle of a PWM period. The compare registers in
F2812 Event Managers are all buffered and support three compare value reload/update (value in buffer
becoming active) modes. These modes have earlier been documented as compare value reload
conditions. The reload condition that supports double update PWM mode is reloaded on Underflow
(beginning of PWM period) OR Period (middle of PWM period). Double update PWM mode can be
achieved by using this condition for compare value reload.
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4.2.6 PWM Characteristics
Characteristics of the PWMs are as follows:
•
•
•
•
•
•
16-bit registers
Wide range of programmable deadband for the PWM output pairs
Change of the PWM carrier frequency for PWM frequency wobbling as needed
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and
four-space vector PWM waveforms
•
•
Minimized CPU overhead using auto-reload of the compare and period registers
The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after
PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the
COMCONx register.
–
–
PDPINTA pin status is reflected in bit 8 of COMCONA register.
PDPINTB pin status is reflected in bit 8 of COMCONB register.
•
EXTCON register bits provide options to individually trip control for each PWM pair of signals
4.2.7 Capture Unit
The capture unit provides a logging function for different events or transitions. The values of the selected
GP timer counter are captured and stored in the two-level-deep FIFO stacks when selected transitions are
detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit
consists of three capture circuits.
•
Capture units include the following features:
–
–
–
–
–
One 16-bit capture control register, CAPCONx (R/W)
One 16-bit capture FIFO status register, CAPFIFOx
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit.
[All inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the
input must hold at its current level to meet the input qualification circuitry requirements. The input
pins CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.]
–
–
–
User-specified transition (rising edge, falling edge, or both edges) detection
Three maskable interrupt flags, one for each capture unit
The capture pins can also be used as general-purpose interrupt pins, if they are not used for the
capture function.
4.2.8 Quadrature-Encoder Pulse (QEP) Circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the
on-chip QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed
on-chip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or
decremented by the rising and falling edges of the two input signals (four times the frequency of either
input pulse).
With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly,
with EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin.
4.2.9 External ADC Start-of-Conversion
EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC
interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively.
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4.3 Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 4-4. The ADC module
consists of a 12-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module
include:
•
•
•
•
•
12-bit ADC core with built-in S/H
Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS
16-channel, MUXed inputs
Autosequencing capability provides up to 16 autoconversions in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
•
•
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state
sequencer (i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
–
The digital value of the input analog voltage is derived by:
Digital Value = 0,
when input ≤ 0 V
Digital Value =
when 0 v < input < 3 V
Input Analog Voltage - ADCLO
4096 ´
,
3
Digital Value = 4095,
when input ≥ 3 V
•
Multiple triggers as sources for the start-of-conversion (SOC) sequence
–
–
–
S/W - software immediate start
EVA - Event manager A (multiple event sources within EVA)
EVB - Event manager B (multiple event sources within EVB)
•
•
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in start/stop mode, allowing multiple time-sequenced triggers to synchronize
conversions
•
•
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
The ADC module in the F2812 has been enhanced to provide flexible interface to event managers A and
B. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at
25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel
modules to service event managers A and B. The two independent 8-channel modules can be cascaded
to form a 16-channel module. Although there are multiple input channels and two sequencers, there is
The two 8-channel modules have the capability to autosequence a series of conversions, each module
has the choice of selecting any one of the respective eight channels available through an analog MUX. In
the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer,
once the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to
perform oversampling algorithms. This gives increased resolution over traditional single-sampled
conversion results.
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SYSCLKOUT
C28x
System
Control Block
High-Speed
Prescaler
ADCENCLK
HSPCLK
Analog
MUX
Result Registers
70A8h
Result Reg 0
Result Reg 1
ADCINA0
S/H
ADCINA7
ADCINB0
ADCINB7
12-Bit
ADC
Module
Result Reg 7
Result Reg 8
70AFh
70B0h
S/H
Result Reg 15
70B7h
ADC Control Registers
S/W
EVA
ADCSOC
S/W
EVB
SOC
SOC
Sequencer 2
Sequencer 1
Figure 4-4. Block Diagram of the F2812 ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins
( VDDA1/VDDA2 , AVDDREFBG) from the digital supply. Figure 4-5 shows the ADC pin connections for the
F2812 device.
NOTE
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the
ADC module is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT
signals is as follows:
ADCENCLK: On reset, this signal is low. While reset is active-low (XRS), the clock to the
register still functions. This is necessary to make sure all registers and modes go into
their default reset state. The analog module is in a low-power inactive state. As soon as
reset goes high, then the clock to the registers is disabled. When the user sets the
ADCENCLK signal high, then the clocks to the registers is enabled and the analog
module is enabled. There is a certain time delay (ms range) before the ADC is stable and
can be used.
HALT: This signal only affects the analog module. It does not affect the registers. If low,
the ADC module is powered. If high, the ADC module goes into low-power mode. The
HALT mode stops the clock to the CPU, which stops the HSPCLK. Therefore the ADC
register logic is turned off indirectly.
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Figure 4-5 shows the ADC pin-biasing for internal reference and Figure 4-6 shows the ADC pin-biasing for
external reference.
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Test Pin
Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
†
ADCBGREFIN
24.9 kW/20 kW (See Note C)
ADC External Current Bias Resistor ADCRESEXT
‡
10 mF
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP
ADCREFM
ADCREFP and ADCREFM should not
be loaded by external circuitry
‡
10 mF
V
V
V
Analog 3.3 V
Analog 3.3 V
DDA1
DDA2
ADC Analog Power
SSA1
SSA2
V
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Reference Power
ADC Analog I/O Power
ADC Digital Power
V
DDAIO
Analog 3.3 V
Analog Ground
V
SSAIO
V
DD1
1.8 V
can use the same 1.8 V (or 1.9 V) supply as the
digital core but separate the two with a ferrite
bead or a filter
V
SS1
Digital Ground
†
‡
Provide access to this pin in PCB layouts. Intended for test purposes only.
TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent
NOTES: A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
C. Use 24.9 kΩ for ADC clock range 1 − 18.75 MHz; use 20 kΩ for ADC clock range 18.75 − 25 MHz.
Figure 4-5. ADC Pin Connections With Internal Reference (See Notes A and B)
NOTE
The temperature rating of any recommended component must match the rating of the end
product.
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ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Test Pin
Analog Input 0−3 V With Respect to ADCLO
Connect to Analog Ground
ADCBGREFIN
24.9 k /20 kW (See Note C)
W
ADC External Current Bias Resistor
ADC Reference Positive Input
ADC Reference Medium Input
ADCRESEXT
ADCREFP
(See
Note D)
2 V
1 V
ADCREFM
1
m
F
−
1
0
m
F
1
m
F
−
1
0
m
F
V
V
V
V
Analog 3.3 V
Analog 3.3 V
DDA1
DDA2
ADC Analog Power
SSA1
SSA2
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Reference Power
ADC Analog I/O Power
ADC Digital Power
V
DDAIO
Analog 3.3 V
Analog Ground
V
SSAIO
V
DD1
1.8 V Can use the same 1.8-V (or 1.9-V)
Digital Ground
V
SS1
supply as the digital core but separate the
two with a ferrite bead or a filter
NOTES: A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
C. Use 24.9 kΩ for ADC clock range 1 − 18.75 MHz; use 20 kΩ for ADC clock range 18.75 − 25 MHz.
D. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP−ADCREFM)
= 1 V $ 0.1% or better.
External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of
external reference is critical for overall gain. The voltage ADCREFP−ADCREFM determines the overall accuracy. Do
not enable internal references when external references are connected to ADCREFP and ADCREFM. See the
TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) for more
information.
Figure 4-6. ADC Pin Connections With External Reference
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Table 4-4. ADC Registers(1)
NAME
ADDRESS
0x00 7100
0x00 7101
0x00 7102
0x00 7103
0x00 7104
0x00 7105
0x00 7106
0x00 7107
0x00 7108
0x00 7109
0x00 710A
0x00 710B
0x00 710C
0x00 710D
0x00 710E
0x00 710F
0x00 7110
0x00 7111
0x00 7112
0x00 7113
0x00 7114
0x00 7115
0x00 7116
0x00 7117
0x00 7118
0x00 7119
SIZE (×16)
DESCRIPTION
ADC Control Register 1
ADCTRL1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADCTRL2
ADC Control Register 2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADCRESULT5
ADCRESULT6
ADCRESULT7
ADCRESULT8
ADCRESULT9
ADCRESULT10
ADCRESULT11
ADCRESULT12
ADCRESULT13
ADCRESULT14
ADCRESULT15
ADCTRL3
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto–Sequence Status Register
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
ADC Conversion Result Buffer Register 5
ADC Conversion Result Buffer Register 6
ADC Conversion Result Buffer Register 7
ADC Conversion Result Buffer Register 8
ADC Conversion Result Buffer Register 9
ADC Conversion Result Buffer Register 10
ADC Conversion Result Buffer Register 11
ADC Conversion Result Buffer Register 12
ADC Conversion Result Buffer Register 13
ADC Conversion Result Buffer Register 14
ADC Conversion Result Buffer Register 15
ADC Control Register 3
ADCST
ADC Status Register
0x00 711C
0x00 711F
reserved
4
(1) The above registers are Peripheral Frame 2 Registers.
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4.4 Enhanced Controller Area Network (eCAN) Module
The CAN module has the following features:
•
•
•
Fully compliant with CAN protocol, version 2.0B
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
–
–
–
–
–
–
–
–
–
–
Configurable as receive or transmit
Configurable with standard or extended identifier
Has a programmable receive mask
Supports data and remote frame
Composed of 0 to 8 bytes of data
Uses a 32-bit time stamp on receive and transmit message
Protects against reception of new message
Holds the dynamically programmable priority of transmit message
Employs a programmable interrupt scheme with two interrupt levels
Employs a programmable alarm on transmission or reception time-out
•
•
•
•
•
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)
•
Self-test mode
–
Operates in a loopback mode receiving its own message. A dummy acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE
For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.
The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for further details.
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Address
Controls
Data
32
eCAN0INT
eCAN1INT
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 × 32-Bit Words
32
32
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 4-7. eCAN Block Diagram and Interface Circuit
Table 4-5. 3.3-V eCAN Transceivers for the SM320F2812 DSP
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
PART NUMBER
VREF
OTHER
TA
–40°C to 85°C
SN65HVD230
SN65HVD230Q
SN65HVD231
SN65HVD231Q
SN65HVD232
SN65HVD232Q
SN65HVD233
SN65HVD234
SN65HVD235
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Standby
Standby
Sleep
Adjustable
Adjustable
Adjustable
Adjustable
None
Yes
Yes
–
–
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
Yes
–
Sleep
Yes
–
None
None
None
None
None
None
–
None
None
–
Standby
Standby & Sleep
Standby
Adjustable
Adjustable
Adjustable
Diagnostic Loopback
–
Autobaud Loopback
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eCAN Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
eCAN Memory (512 Bytes)
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
6000h
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Control and Status Registers
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Message Object Time Stamps (MOTS)
Bit-Timing Configuration − CANBTC
Error and Status − CANES
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
(32 × 32-Bit RAM)
eCAN Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
6100h−6107h
6108h−610Fh
6110h−6117h
6118h−611Fh
6120h−6127h
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
61E0h−61E7h
61E8h−61EFh
61F0h−61F7h
61F8h−61FFh
Reserved
Message Mailbox (16 Bytes)
Message Identifier − MSGID
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
61E8h−61E9h
61EAh−61EBh
61ECh−61EDh
61EEh−61EFh
Figure 4-8. eCAN Memory Map
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The CAN registers listed in Table 4-6 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 4-6. CAN Registers Map(1)
REGISTER NAME
CANME
ADDRESS
0x00 6000
0x00 6002
0x00 6004
0x00 6006
0x00 6008
0x00 600A
0x00 600C
0x00 600E
0x00 6010
0x00 6012
0x00 6014
0x00 6016
0x00 6018
0x00 601A
0x00 601C
0x00 601E
0x00 6020
0x00 6022
0x00 6024
0x00 6026
0x00 6028
0x00 602A
0x00 602C
0x00 602E
0x00 6030
0x00 6032
SIZE (×32)
DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mailbox enable
CANMD
Mailbox direction
CANTRS
CANTRR
CANTA
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
CANAA
CANRMP
CANRML
CANRFP
CANGAM
CANMC
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
CANBTC
CANES
Bit-timing configuration
Error and status
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
RX I/O control
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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4.5 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
•
•
•
•
•
•
•
•
•
•
•
Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices, except the DMA features
Full-duplex communication
Double-buffered data registers which allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8/12/16/20/24 or 32-bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Support A-bis mode
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
•
•
•
Works with SPI-compatible devices
Two 16 x 16-level FIFO for Transmit channel
Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
•
•
T1/E1 framers
MVIP switching-compatible and ST-BUS-compliant devices including:
–
–
–
–
–
–
MVIP framers
H.100 framers
SCSA framers
IOM-2 compliant devices
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS-compliant devices
CLKSRG
McBSP clock rate = CLKG =
,
1+ CLKGDIV
•
where CLKSRG source could be LSPCLK, CLKX, or CLKR.(2)
(2) Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is
less than the I/O buffer speed limit—20-MHz maximum.
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Figure 4-9 shows the block diagram of the McBSP module with FIFO, interfaced to the F2812 version of
Peripheral Frame 2.
Peripheral Write Bus
TX FIFO
Interrupt
TX FIFO _15
—
TX FIFO _15
—
MXINT
TX Interrupt Logic
To CPU
TX FIFO _1
TX FIFO _0
TX FIFO _1
TX FIFO _0
McBSP Transmit
Interrupt Select Logic
TX FIFO Registers
16
16
DXR2 Transmit Buffer DXR1 Transmit Buffer
LSPCLK
FSX
McBSP Registers
and Control Logic
16
16
CLKX
Compand Logic
XSR2
XSR1
DX
DR
RSR1
16
RSR2
16
CLKR
Expand Logic
FSR
RBR2 Register
16
RBR1 Register
16
McBSP
DRR2 Receive Buffer
16
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
RX FIFO _15
—
RX FIFO _15
—
RX FIFO
Interrupt
RX FIFO _1
RX FIFO _0
RX FIFO _1
RX FIFO _0
RX Interrupt Logic
MRINT
To CPU
RX FIFO Registers
Peripheral Read Bus
Figure 4-9. McBSP Module With FIFO
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Table 4-7 provides a summary of the McBSP registers.
Table 4-7. McBSP Register Summary
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
DATA REGISTERS, RECEIVE, TRANSMIT(1)
–
–
–
–
–
–
–
–
–
0x0000
0x0000
0x0000
McBSP Receive Buffer Register
McBSP Receive Shift Register
McBSP Transmit Shift Register
McBSP Data Receive Register 2
–Read First if the word size is greater than 16 bits, else ignore DRR2
DRR2
DRR1
DXR2
DXR1
0
R
0x0000
0x0000
0x0000
0x0000
McBSP Data Receive Register 1
–Read Second if the word size is greater than 16 bits, else read DRR1
only
01
02
03
R
McBSP Data Transmit Register 2
–Write First if the word size is greater than 16 bits, else ignore DXR2
W
W
McBSP Data Transmit Register 1
–Write Second if the word size is greater than 16 bits, else write to DXR1
only
McBSP CONTROL REGISTERS
SPCR2
SPCR1
RCR2
04
05
06
07
08
09
0A
0B
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Serial Port Control Register 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
McBSP Serial Port Control Register 1
McBSP Receive Control Register 2
McBSP Receive Control Register 1
McBSP Transmit Control Register 2
McBSP Transmit Control Register 1
McBSP Sample Rate Generator Register 2
McBSP Sample Rate Generator Register 1
RCR1
XCR2
XCR1
SRGR2
SRGR1
MULTICHANNEL CONTROL REGISTERS
MCR2
MCR1
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Multichannel Register 2
McBSP Multichannel Register 1
RCERA
RCERB
XCERA
XCERB
PCR
McBSP Receive Channel Enable Register Partition A
McBSP Receive Channel Enable Register Partition B
McBSP Transmit Channel Enable Register Partition A
McBSP Transmit Channel Enable Register Partition B
McBSP Pin Control Register
RCERC
RCERD
XCERC
XCERD
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
XCERH
McBSP Receive Channel Enable Register Partition C
McBSP Receive Channel Enable Register Partition D
McBSP Transmit Channel Enable Register Partition C
McBSP Transmit Channel Enable Register Partition D
McBSP Receive Channel Enable Register Partition E
McBSP Receive Channel Enable Register Partition F
McBSP Transmit Channel Enable Register Partition E
McBSP Transmit Channel Enable Register Partition F
McBSP Receive Channel Enable Register Partition G
McBSP Receive Channel Enable Register Partition H
McBSP Transmit Channel Enable Register Partition G
McBSP Transmit Channel Enable Register Partition H
(1) DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
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Table 4-7. McBSP Register Summary (continued)
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
FIFO MODE REGISTERS (applicable only in FIFO mode)
FIFO Data Registers(1)
McBSP Data Receive Register 2 – Top of receive FIFO
–Read First FIFO pointers does not advance
DRR2
00
01
02
03
R
0x0000
0x0000
0x0000
0x0000
McBSP Data Receive Register 1 – Top of receive FIFO
–Read Second for FIFO pointers to advance
DRR1
DXR2
DXR1
R
W
W
McBSP Data Transmit Register 2 – Top of transmit FIFO
–Write First FIFO pointers does not advance
McBSP Data Transmit Register 1 – Top of transmit FIFO
–Write Second for FIFO pointers to advance
FIFO Control Registers
MFFTX
MFFRX
MFFCT
MFFINT
MFFST
20
21
22
23
24
R/W
R/W
R/W
R/W
R/W
0xA000
0x201F
0x0000
0x0000
0x0000
McBSP Transmit FIFO Register
McBSP Receive FIFO Register
McBSP FIFO Control Register
McBSP FIFO Interrupt Register
McBSP FIFO Status Register
(1) FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
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4.6 Serial Communications Interface (SCI) Module
The F2812 device include two serial communications interface (SCI) modules. The SCI modules support
digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its
own separate enable and interrupt bits. Both can be operated independently or simultaneously in the
full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,
overrun, and framing errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit
baud-select register.
Features of each SCI module include:
•
Two external pins:
–
–
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE
Both pins can be used as GPIO if not used for SCI.
•
Baud rate programmable to 64K different rates
– Baud rate
LSPCLK
when BRR ≠ 0
,
=
(BRR + 1) · 8
LSPCLK
,
16
=
when BRR = 0
•
Data-word format
–
–
–
–
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) andTX
EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
150MHz
6
= 9.375 ´10 b/ s
2´ 8
Max bit rate =
•
•
•
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
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NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
•
•
Auto baud-detect hardware logic
16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9.
Table 4-8. SCI-A Registers(1)
NAME
ADDRESS
0x00 7050
0x00 7051
0x00 7052
0x00 7053
0x00 7054
0x00 7055
0x00 7056
0x00 7057
0x00 7059
0x00 705A
0x00 705B
0x00 705C
0x00 705F
SIZE (×16)
DESCRIPTION
SCI-A Communications Control Register
SCI-A Control Register 1
SCICCRA
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA
SCIFFRXA
SCIFFCTA
SCIPRIA
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Shaded registers are new registers for the FIFO mode.
Table 4-9. SCI-B Registers(1) (2)
NAME
ADDRESS
SIZE (×16)
DESCRIPTION
SCI-B Communications Control Register
SCI-B Control Register 1
SCICCRB
0x00 7750
0x00 7751
0x00 7752
0x00 7753
0x00 7754
0x00 7755
0x00 7756
0x00 7757
0x00 7759
0x00 775A
0x00 775B
0x00 775C
0x00 775F
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB
SCIFFRXB
SCIFFCTB
SCIPRIB
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
(1) Shaded registers are new registers for the FIFO mode.
(2) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
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Figure 4-10 shows the SCI module block diagram.
SCICTL1.1
SCITXD
Frame Format and Mode
SCITXD
TXSHF
TXENA
Register
Parity
Even/Odd Enable
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY
TX INT ENA
Transmitter−Data
Buffer Register
SCICTL2.7
TXWAKE
SCICTL1.3
1
SCICTL2.0
8
TX FIFO
Interrupts
TXINT
TX FIFO _0
TX Interrupt
Logic
TX FIFO _1
−−−−−
SCITXBUF.7−0
To CPU
TX FIFO _15
SCI TX Interrupt select logic
WUT
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 − 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 − 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7−0
RXRDY
RX/BK INT ENA
SCIRXST.6
8
BRKDT
RX FIFO _15
SCIRXST.5
−−−−−
RX FIFO _0
RX FIFO
Interrupts
RX FIFO_1
RXINT
RX Interrupt
Logic
SCIRXBUF.7−0
RX FIFO registers
To CPU
RXFFOVF
SCIRXST.7 SCIRXST.4 − 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt select logic
SCICTL1.6
Figure 4-10. Serial Communications Interface (SCI) Module Block Diagram
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4.7 Serial Peripheral Interface (SPI) Module
The F2812 device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be
shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSP controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
•
Four external pins:
–
–
–
–
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE
All four pins can be used as GPIO, if the SPI module is not used.
•
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates
– Baud rate
LSPCLK
when BRR ≠ 0
,
=
(SPIBRR + 1)
LSPCLK
,
=
when BRR = 0, 1, 2, 3
4
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted
such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.
•
•
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.
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Enhanced feature:
•
•
16-level transmit/receive FIFO
Delayed transmit control
Table 4-10. SPI Registers(1)
NAME
SPICCR
SPICTL
ADDRESS
0x00 7040
0x00 7041
0x00 7042
0x00 7044
0x00 7046
0x00 7047
0x00 7048
0x00 7049
0x00 704A
0x00 704B
0x00 704C
0x00 704F
SIZE (×16)
DESCRIPTION
SPI Configuration Control Register
SPI Operation Control Register
SPI Status Register
1
1
1
1
1
1
1
1
1
1
1
1
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI Baud Rate Register
SPI Receive Emulation Buffer Register
SPI Serial Input Buffer Register
SPI Serial Output Buffer Register
SPI Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI FIFO Transmit Register
SPI FIFO Receive Register
SPI FIFO Control Register
SPI Priority Control Register
(1) The above registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Figure 4-11 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPISTS.7
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
SPIINT/SPIRXINT
RX FIFO Interrupt
−−−−−
RX Interrupt
Logic
RX FIFO _15
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
−−−−−
TX FIFO _1
SPITXINT
TX FIFO _0
16
SPI INT
ENA
SPI INT FLAG
SPITXBUF
Buffer Register
SPISTS.6
SPICTL.0
16
16
M
S
M
SPIDAT
Data Register
S
SW1
SW2
SPISIMO
M
S
M
SPIDAT.15 − 0
S
SPISOMI
Talk
SPICTL.1
†
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 − 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
LSPCLK
SPICCR.6
SPICTL.3
SPICLK
SPIBRR.6 − 0
M
6
5
4
3
2
1
0
†
SPISTE is driven low by the master for a slave device.
Figure 4-11. Serial Peripheral Interface Module Block Diagram (Slave Mode)
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4.8 GPIO MUX
The GPIO Mux registers are used to select the operation of shared pins on the F2812 device. The pins
can be individually selected to operate as Digital I/O or connected to Peripheral I/O signals (via the
GPxMUX registers). If selected for Digital I/O mode, registers are provided to configure the pin direction
(via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL)
Table 4-11. GPIO Mux Registers(1) (2) (3)
NAME
GPAMUX
GPADIR
GPAQUAL
reserved
GPBMUX
GPBDIR
GPBQUAL
reserved
reserved
reserved
reserved
reserved
GPDMUX
GPDDIR
GPDQUAL
reserved
GPEMUX
GPEDIR
GPEQUAL
reserved
GPFMUX
GPFDIR
reserved
reserved
GPGMUX
GPGDIR
reserved
reserved
ADDRESS
0x00 70C0
0x00 70C1
0x00 70C2
0x00 70C3
0x00 70C4
0x00 70C5
0x00 70C6
0x00 70C7
0x00 70C8
0x00 70C9
0x00 70CA
0x00 70CB
0x00 70CC
0x00 70CD
0x00 70CE
0x00 70CF
0x00 70D0
0x00 70D1
0x00 70D2
0x00 70D3
0x00 70D4
0x00 70D5
0x00 70D6
0x00 70D7
0x00 70D8
0x00 70D9
0x00 70DA
0x00 70DB
SIZE (×16)
REGISTER DESCRIPTION
GPIO A Mux Control Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPIO A Direction Control Register
GPIO A Input Qualification Control Register
GPIO B Mux Control Register
GPIO B Direction Control Register
GPIO B Input Qualification Control Register
GPIO D Mux Control Register
GPIO D Direction Control Register
GPIO D Input Qualification Control Register
GPIO E Mux Control Register
GPIO E Direction Control Register
GPIO E Input Qualification Control Register
GPIO F Mux Control Register
GPIO F Direction Control Register
GPIO G Mux Control Register
GPIO G Direction Control Register
0x00 70DC
0x00 70DF
reserved
4
(1) Reserved locations returns undefined values and writes is ignored.
(2) Not all inputs support input signal qualification.
(3) These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
If configured for Digital I/O mode, additional registers are provided for setting individual I/O signals (via the
GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual
I/O signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the
TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078).
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Table 4-12. GPIO Data Registers(1) (2)
NAME
GPADAT
ADDRESS
0x00 70E0
0x00 70E1
0x00 70E2
0x00 70E3
0x00 70E4
0x00 70E5
0x00 70E6
0x00 70E7
0x00 70E8
0x00 70E9
0x00 70EA
0x00 70EB
0x00 70EC
0x00 70ED
0x00 70EE
0x00 70EF
0x00 70F0
0x00 70F1
0x00 70F2
0x00 70F3
0x00 70F4
0x00 70F5
0x00 70F6
0x00 70F7
0x00 70F8
0x00 70F9
0x00 70FA
0x00 70FB
SIZE (×16)
REGISTER DESCRIPTION
GPIO A Data Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPASET
GPIO A Set Register
GPIO A Clear Register
GPIO A Toggle Register
GPIO B Data Register
GPIO B Set Register
GPIO B Clear Register
GPIO B Toggle Register
GPACLEAR
GPATOGGLE
GPBDAT
GPBSET
GPBCLEAR
GPBTOGGLE
reserved
reserved
reserved
reserved
GPDDAT
GPIO D Data Register
GPIO D Set Register
GPIO D Clear Register
GPIO D Toggle Register
GPIO E Data Register
GPIO E Set Register
GPIO E Clear Register
GPIO E Toggle Register
GPIO F Data Register
GPIO F Set Register
GPIO F Clear Register
GPIO F Toggle Register
GPIO G Data Register
GPIO G Set Register
GPIO G Clear Register
GPIO G Toggle Register
GPDSET
GPDCLEAR
GPDTOGGLE
GPEDAT
GPESET
GPECLEAR
GPETOGGLE
GPFDAT
GPFSET
GPFCLEAR
GPFTOGGLE
GPGDAT
GPGSET
GPGCLEAR
GPGTOGGLE
0x00 70FC
0x00 70FF
reserved
4
(1) Reserved location returns undefined values and writes are ignored.
(2) These registers are NOT EALLOW protected. The above registers are typically accessed regularly by the user.
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Figure 4-12 shows how the various register bits select the various modes of operation for GPIO function.
GPxDAT/SET/CLEAR/TOGGLE
Digital I/O
Peripheral I/O
Register Bit(s)
High-
Impedance
Control
GPxQUAL
Register
GPxMUX
Register Bit Register Bit
GPxDIR
0
1
0
1
MUX
MUX
SYSCLKOUT
Input Qualification
High-Impedance
Enable (1)
XRS
Internal (Pullup or Pulldown)
PIN
A. In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only
gives the value written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the
GPxDAT register, provided the corresponding direction bit is zero (input mode).
B. Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification
sampling period. The sampling window is 6 samples wide and the output is only changed when all samples are the
same (all 0's or all 1's). This feature removes unwanted spikes from the input signal.
Figure 4-12. GPIO/Peripheral Pin Multiplexing
NOTE
The input function of the GPIO pin and the input path to the peripheral are always enabled. It
is the output function of the GPIO pin that is multiplexed with the output path of the primary
(peripheral) function. Since the output buffer of a pin connects back to the input buffer, any
GPIO signal present at the pin is propagated to the peripheral module as well. Therefore,
when a pin is configured for GPIO operation, the corresponding peripheral functionality (and
interrupt-generating capability) must be disabled. Otherwise, interrupts may be inadvertently
triggered. This is especially critical when the PDPINTA and PDPINTB pins are used as GPIO
pins, since a value of zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) puts PWM pins in a
high-impedance state. The CxTRIP and TxCTRIP pins also put the corresponding PWM pins
in high impedance, if they are driven low (as GPIO pins) and bit EXTCONx.0 = 1.
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5
Development Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of F2812-based applications:
Software Development Tools
•
Code Composer Studio™ Integrated Development Environment (IDE)
–
–
–
–
C/C++ Compiler
Code generation tools
Assembler/Linker
Cycle Accurate Simulator
•
•
Application algorithms
Sample applications code
Hardware Development Tools
•
•
•
•
F2812 eZdsp
JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510 USB
Universal 5-V dc power supply
Documentation and cables
5.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
[TMS320] DSP devices and support tools. Each [TMS320] DSP commercial family member has one of
three prefixes: TMX, TMP, or TMS (e.g., TMS320F2812GHH). Texas Instruments recommends two of
three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully
qualified production devices/tools (TMS/TMDS).
TMX—Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP—Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification
TMS/SM—Fully qualified production device
SMJ—Fully qualified production device
Support tool development evolutionary flow:
TMDX—Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS—Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
Developmental product is intended for internal evaluation purposes.
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
family member.
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SM 320
F
2812
HFG
M
PREFIX
TEMPERATURE RANGE
S = -55°C to 220°C
TMX = experimental device
TMP = prototype device
TMS = qualified device
SM
SMJ = MIL-PRF-38535 (QML)
=
commercial processing
PACKAGE TYPE†
DEVICE FAMILY
HFG = 172-pin CQFP
KGD = Die
320 = TMS320 DSP Family
DEVICE
2810
2811
2812
TECHNOLOGY
F = Flash EEPROM (1.8-V/1.9-V Core/3.3-V I/O)
C = ROM (1.8-V/1.9-V Core/3.3-V I/O)
† Not all combinations of processing options, temperature ranges and packages are available.
CQFP = Ceramic Quad Flatpack
Figure 5-1. 28x Device Nomenclature
5.2 Documentation Support
Extensive documentation supports all of the TMS320E DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets and data manuals, with design specifications; and hardware and software applications. Useful
reference documentation includes:
TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430) describes
the central processing unit (CPU) and the assembly language instructions of the TMS320C28x™
fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs.
TMS320x281x Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060)
describes the ADC module. The module is a 12-bit pipelined ADC. The analog circuits of this converter,
referred to as the core in this document, include the front-end analog multiplexers (MUXs),
sample-and-hold (S/H) circuits, the conversion core, voltage regulators, and other analog supporting
circuits. Digital circuits, referred to as the wrapper in this document, include programmable conversion
sequencer, result registers, interface to analog circuits, interface to device peripheral bus, and interface to
other on-chip modules.
TMS320x281x Boot ROM Reference Guide (literature number SPRU095) describes the purpose and
features of the bootloader (factory-programmed boot-loading software). It also describes other contents of
the device on-chip boot ROM and identifies where all of the information is located within that memory.
TMS320x281x Event Manager (EV) Reference Guide (literature number SPRU065) describes the EV
modules that provide a broad range of functions and features that are particularly useful in motion control
and motor control applications. The EV modules include general-purpose (GP) timers, full-compare/PWM
units, capture units, and quadrature-encoder pulse (QEP) circuits.
TMS320x281x External Interface (XINTF) Reference Guide (literature number SPRU067) describes the
external interface (XINTF) of the 281x digital signal processors (DSPs).
TMS320x281x Multi-channel Buffered Serial Ports (McBSPs) Reference Guide (literature number
SPRU061) describes the McBSP) available on the 281x devices. The McBSPs allow direct interface
between a DSP and other devices in a system.
TMS320x281x System Control and Interrupts Reference Guide (literature number SPRU078)
describes the various interrupts and system control features of the 281x digital signal processors (DSPs).
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TMS320x281x, 280x Enhanced Controller Area Network (eCAN) Reference Guide (literature number
SPRU074) describes the eCAN that uses established protocol to communicate serially with other
controllers in electrically noisy environments. With 32 fully configurable mailboxes and time-stamping
feature, the eCAN module provides a versatile and robust serial communication interface. The eCAN
module implemented in the C28x DSP is compatible with the CAN 2.0B standard (active).
TMS320x281x, 280x Peripheral Reference Guide (literature number SPRU566) describes the peripheral
reference guides of the 28x digital signal processors (DSPs).
TMS320x281x, 280x Serial Communication Interface (SCI) Reference Guide (literature number
SPRU051) describes the SCI that is a two-wire asynchronous serial port, commonly known as a UART.
The SCI modules support digital communications between the CPU and other asynchronous peripherals
that use the standard non-return-to-zero (NRZ) format.
TMS320x281x, 280x Serial Peripheral Interface (SPI) Reference Guide (literature number SPRU059)
describes the SPI – a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream
of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed
bit-transfer rate. The SPI is used for communications between the DSP controller and external peripherals
or another controller.
3.3 V DSP for Digital Motor Control Application Report (literature number SPRA550). New generations
of motor control digital signal processors (DSPs) lower their supply voltages from 5 V to 3.3 V to offer
higher performance at lower cost. Replacing traditional 5-V digital control circuitry by 3.3-V designs
introduce no additional system cost and no significant complication in interfacing with TTL and CMOS
compatible components, as well as with mixed voltage ICs such as power transistor gate drivers. Just like
5-V based designs, good engineering practice should be exercised to minimize noise and EMI effects by
proper component layout and PCB design when 3.3-V DSP, ADC, and digital circuitry are used in a mixed
signal environment, with high and low voltage analog and switching signals, such as a motor control
system. In addition, software techniques such as Random PWM method can be used by special features
of the Texas Instruments (TI) TMS320x24xx DSP controllers to significantly reduce noise effects caused
by EMI radiation.
This application report reviews designs of 3.3-V DSP versus 5-V DSP for low HP motor control
applications. The application report first describes a scenario of a 3.3-V-only motor controller indicating
that for most applications, no significant issue of interfacing between 3.3 V and 5 V exists. Cost-effective
3.3-V – 5-V interfacing techniques are then discussed for the situations where such interfacing is needed.
On-chip 3.3-V ADC versus 5-V ADC is also discussed. Sensitivity and noise effects in 3.3-V and 5-V ADC
conversions are addressed. Guidelines for component layout and printed circuit board (PCB) design that
can reduce system's noise and EMI effects are summarized in the last section.
The TMS320C28x Instruction Set Simulator Technical Overview (literature number SPRU608)
describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates
the instruction set of the C28x core.
TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide (literature number
SPRU625) describes development using DSP/BIOS.
TMS320C28x Assembly Language Tools User's Guide (literature number SPRU513) describes the
assembly language tools (assembler and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic debugging directives for the
TMS320C28x™ device.
TMS320C28x Optimizing C Compiler User's Guide (literature number SPRU514) describes the
TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces
TMS320™ DSP assembly language source code for the TMS320C28x device.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320™ DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320™ DSP customers on product information.
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Updated information on the TMS320™ DSP controllers can be found on the worldwide web at:
To send comments regarding this TMS320F281x/TMS320C281x data manual (literature number
SPRS174), use the commentsatbooks.sc.ti.com email address, which is a repository for feedback. For
questions
and
support,
contact
the
Product
Information
Center
listed
at
the
6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
SM/SMJ320F2812 DSP.
6.1 Absolute Maximum Ratings
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature
ranges. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated under Section 6.2 is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability. All voltage values are with respect to VSS
.
VALUE
UNIT
Supply voltage range, VDDIO, VDDA1, VDDA2, VDDAIO, and
AVDDREFBG
–0.3 to 4.6
V
Supply voltage range, VDD, VDD1
VDD3VFL range
–0.5 to 2.5
–0.3 to 4.6
–0.3 to 4.6
–0.3 to 4.6
±20
V
V
Input voltage range, VIN
V
Output voltage range, VO
V
(1)
Input clamp current, IIK (VIN < 0 or VIN > VDDIO
)
mA
mA
°C
Output clamp current, IOK (VO < 0 or VO > VDDIO
)
±20
(2)
Operating ambient temperature range, TA
S Temp
–55 to 220
(1) Continuous clamp current per pin is ±2 mA
(2) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device
life.
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6.2 Recommended Operating Conditions
(1)
See
MIN
3.14
NOM
3.3
MAX
3.47
UNIT
VDDIO
Device supply voltage, I/O
Device supply voltage, CPU
V
1.8 V (135 MHz)
1.9 V (150 MHz)
1.71
1.81
1.8
1.9
0
1.89
2
VDD, VDD1
V
VSS
Supply ground
V
V
VDDA1, VDDA2
AVDDREFBG, VDDAIO
,
ADC supply voltage
3.14
3.14
3.3
3.3
3.47
3.47
Flash programming supply
voltage
VDD3VFL
V
VDD = 1.9 V ± 5%
2
150
135
Device clock frequency
(system clock)
fSYSCLKOUT
MHz
VDD = 1.8 V ± 5%
2
2
All inputs except XCLKIN
XCLKIN (at 50 mA max)
All inputs except XCLKIN
XCLKIN (at 50 mA max)
All I/Os except Group 2
VDDIO
VDD
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
0.7VDD
0.8
0.3VDD
–4
High-level output source
current,
VOH = 2.4 V
IOH
mA
Group 2(2)
–8
All I/Os except Group 2
Group 2(2)
4
8
Low-level output sink current,
VOL = VOL MAX
IOL
TA
mA
°C
Ambient temperature
–55
25
220
(2) Group 2 pins are as follows: XINTF pins, PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.
In Revision C, EVA (GPIOA0–GPIOA15) and GPIOD0 are 4 mA drive.
.
6.3 Electrical Characteristics
Over recommended operating conditions (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
IOH = IOHMAX
MIN
TYP
MAX
UNIT
V
2.4
VOH
VOL
High-level output voltage
Low-level output voltage
VDDIO
– 0.2
IOH = 50 mA
IOL = IOLMAX
0.4
V
All I/Os(2) (including XRS)
except EVB
–80
–13
–140
–190
VDDIO = 3.3 V,
VIN = 0 V
Input
current
(low level)
With pullup
IIL
mA
GPIOB/EVB
–25
–35
±2
With pulldown
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDD
Input
With pullup
±2
current
(high
level)
IIH
mA
VDDIO = 3.3 V,
VIN = VDD
With pulldown(3)
28
50
80
±2
Output current,
high-impedance state (off-state)
IOZ
VO = VDDIO or 0 V
mA
CI
Input capacitance
Output capacitance
7
7
pF
pF
Co
(1) Minimum and maximum parameters are characterized for operation at TA = 220°C unless otherwise noted, but may not be production
tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5.
(3) The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST.
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1.00E+06
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1.00E+05
1.00E+04
1.00E+03
1.00E+02
70
150
200
220
Die Junction Temperature (°C)
Figure 6-1. SM320F2812-HT Life Expectancy Curve
Notes:
1. See data sheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package
interconnect life).
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6.4 Current Consumption by Power-Supply Pins Over Recommended Operating
Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
TA = –55°C to 125°C
IDDIO IDD3VFL
MAX(2) MAX(2)
TYP
TA = 220°C
(1)
(1)
MODE
TEST CONDITIONS
IDD
MAX(2)
IDDA
TYP
IDD
IDDIO
IDD3VFL
TYP MAX
IDDA
TYP
TYP
MAX(2)
TYP
MAX
TYP
MAX
TYP
MAX
All peripheral clocks
are enabled. All
PWM pins are
toggled at 100 kHz.
Data is continuously
transmitted out of the
SCIA, SCIB, and
CAN ports. The
hardware multiplier is
exercised.
Operational
195 mA 230 mA 15 mA 30 mA 40 mA 45 mA 40 mA 50 mA 275 mA 330 mA 17 mA 30 mA 45 mA 50 mA 40 mA 52 mA
Code is running out
of flash with 5
wait-states.
–Flash is powered
down
–XCLKOUT is turned
off
IDLE
125 mA 150 mA 5 mA
10 mA
2 mA
4 mA
1 mA
35 mA 200 mA
10 mA
56 mA 100 mA 320 mA 450 mA
–All peripheral clocks
are on, except ADC
–Flash is powered
down
–Peripheral clocks
are turned off
–Pins without an
internal PU/PD are
tied high/low
STANDBY
5 mA
10 mA
5 mA
20 mA
2 mA
4 mA
1 mA
35 mA 27 mA 40 mA 160 mA 200 mA 56 mA 100 mA 320 mA 450 mA
–Flash is powered
down
–Peripheral clocks
are turned off
–Pins without an
internal PU/PD are
tied high/low
HALT
70 mA
5 mA
20 mA
2 mA
4 mA
1mA
35 mA 9.8 mA
160 mA 200 mA 56 mA 100 mA 320 mA 450 mA
– Input clock is
disabled
(1) IDDA includes current into VDDA1, VDDA2, VDD1, AVDDREFBG , and VDDAIO pins.
(2) MAX numbers are at 125°C, and max voltage (VDD = 2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
NOTE
HALT and STANDBY modes cannot be used when the PLL is disabled.
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6.5 Current Consumption Graphs
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
SYSCLKOUT (MHz)
IDD
IDDIO
IDD3VFL
IDDA
Total 3.3−V current
A. Test conditions are as defined in Table 6-5 for operational currents under nominal process voltage and temperature
conditions.
B. IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a trivial amount of current (<1 mA) drawn
by VDD1
.
C. IDDA represents the current drawn by VDDA1 and VDDA2 rails.
D. Total 3.3-V current is the sum of IDDIO, IDD3VFL, and IDDA. It includes a trivial amount of current (<1 mA) drawn by
VDDAIO.
Figure 6-2. Typical Current Consumption Over Frequency
700
600
500
400
300
200
100
0
0
20
40
60
80
100
120
140
160
SYSCLKOUT (MHz)
TOTAL POWER
Figure 6-3. Typical Power Consumption Over Frequency
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6.6 Reducing Current Consumption
28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current
consumption can be achieved by turning off the clock to any peripheral module which is not used in a
given application. Table 6-1 indicates the typical reduction in current consumption achieved by turning off
the clocks to various peripherals.
Table 6-1. Typical Current Consumption by Various Peripherals (at 150 MHz)(1)
(2)
PERIPHERAL MODULE
IDD CURRENT REDUCTION (mA)
eCAN
EVA
12
6
EVB
6
ADC
SCI
8(3)
4
SPI
5
McBSP
13
(1) All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is
possible only after the peripheral clocks are turned on.
(2) Not production tested.
(3) This number represents the current drawn by the digital portion of the ADC module. Turning off the
clock to the ADC module results in the elimination of the current drawn by the analog portion of the
ADC (ICCA) as well.
6.7 Power Sequencing Requirements
SM320F2812 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the CPU, Flash, ROM,
ADC, and the I/Os. To ensure the correct reset state for all modules during power up, there are some
requirements to be met while powering up/powering down the device. The current F2812 silicon reference
schematics (Spectrum Digital Incorporated eZdsp. board) suggests two options for the power sequencing
circuit.
•
Option 1:
In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1 (1.8 V or
1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC (VDDA1/VDDA2/AVDDREFBG
)
modules are ramped up. While option 1 is still valid, TI has simplified the requirement. Option 2 is the
recommended approach.
•
Option 2:
Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and thenramp
1.8 V (or 1.9 V) (VDD/VDD1) supply pins.
1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset
signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the
modules inside the device. See Figure 6-8 for power-on reset timing.
•
Power-Down Sequencing:
During power-down, the device reset should be asserted low (8 ms, minimum) before the VDD supply
reaches 1.5 V. This helps to keep on-chip flash logic in reset prior to the VDDIO/VDD power supplies
ramping down. It is recommended that the device reset control from Low-Dropout (LDO) regulators or
voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing
(with the aid of additional external components) may be used to meet the power sequencing
requirement. See www.spectrumdigital.com for F2812 eZdsp™ schematics and updates.
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Table 6-2. Recommended Low-Dropout Regulators
SUPPLIER
PART NUMBER
Texas Instruments
TPS767D301
NOTE
The GPIO pins are undefined until VDD = 1 V and VDDIO = 2.5 V.
See Figure 6-8,
Figure 6-4. F2812 Typical Power-Up and Power-Down Sequence – Option 2
6.8 Signal Transition Levels
Note that some of the signals use different reference voltages, see the recommended operating conditions
table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of
0.4 V.
Figure 6-5 shows output levels.
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2.4 V (V )
OH
80%
20%
0.4 V (V
)
OL
Figure 6-5. Output Levels
Output transition times are specified as follows:
•
For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of
the total voltage range and lower and the level at which the output is said to be low is 20% of the total
voltage range and lower.
•
For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total
voltage range and higher and the level at which the output is said to be high is 80% of the total voltage
range and higher.
Figure 6-6 shows the input levels.
2.0 V (V )
IH
90%
10%
0.8 V (V )
IL
Figure 6-6. Input Levels
Input transition times are specified as follows:
•
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high
is 90% of the total voltage range and lower and the level at which the input is said to be low is 10% of
the total voltage range and lower.
•
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
10% of the total voltage range and higher and the level at which the input is said to be high is 90% of
the total voltage range and higher.
NOTE
See the individual timing diagrams for levels used for testing timing parameters.
6.9 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don’t care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
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6.10 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.11 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The
transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data
sheet timing.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6-7. 3.3-V Test Load Circuit
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6.12 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
Table 6-3. Clock Table and Nomenclature
MIN
28.6
20
NOM
MAX
50
UNIT
ns
tc(OSC), Cycle time
Frequency
On-chip oscillator clock
XCLKIN
35
MHz
ns
tc(CI), Cycle time
Frequency
6.67
4
250
150
500
150
2000
150
MHz
ns
tc(SCO), Cycle time
Frequency
6.67
2
SYSCLKOUT
XCLKOUT
HSPCLK
MHz
ns
tc(XCO), Cycle time
Frequency
6.67
0.5
6.67
MHz
ns
tc(HCO), Cycle time
Frequency
13.3(1)
75(1)
26.6(1)
37.5(1)
150
75
MHz
ns
tc(LCO), Cycle time
13.3
40
LSPCLK
Frequency
MHz
ns
tc(ADCCLK), Cycle time(2)
Frequency
ADC clock
SPI clock
25
MHz
ns
tc(SPC), Cycle time
Frequency
50
20
MHz
ns
tc(CKG), Cycle time
Frequency
50
McBSP
20
MHz
ns
tc(XTIM), Cycle time
Frequency
6.67
XTIMCLK
150
MHz
(1) This is the default reset value if SYSCLKOUT = 150 MHz.
(2) The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be
SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
6.13 Clock Requirements and Characteristics
6.13.1 Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
Table 6-4. Input Clock Frequency(1)
PARAMETER
MIN
20
20
4
TYP
MAX
35
UNIT
MHz
MHz
Resonator(2)
Crystal(2)
XCLKIN
fx
fl
Input clock frequency
35
150
2
Limp mode clock frequency
(1) Not production tested.
(2) Not guaranteed for TA > 125°C.
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Table 6-5. XCLKIN Timing Requirements – PLL Bypassed or Enabled(1)
NO.
MIN
MAX
250
6
UNIT
C8
tc(CI)
tf(CI)
Cycle time, XCLKIN
Fall time, XCLKIN
6.67
ns
Up to 30 MHz
C9
ns
ns
30 MHz to 150 MHz
Up to 30 MHz
2
6
C10
tr(CI)
Rise time, XCLKIN
30 MHz to 150 MHz
2
C11
C12
tw(CIL)
tw(CIH)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI)
40
40
60
60
%
%
(1) Not production tested.
Table 6-6. XCLKIN Timing Requirements – PLL Disabled(1)
NO.
MIN
MAX UNIT
C8
tc(CI)
tf(CI)
Cycle time, XCLKIN
6.67
250
6
ns
Up to 30 MHz
C9
Fall time, XCLKIN
ns
30 MHz to 150 MHz
Up to 30 MHz
2
6
C10
C11
C12
tr(CI)
Rise time, XCLKIN
ns
%
%
30 MHz to 150 MHz
XCLKIN ≤ 120 MHz
120 < XCLKIN ≤ 150 MHz
XCLKIN ≤ 120 MHz
120 < XCLKIN ≤ 150 MHz
2
40
45
40
45
60
55
60
55
tw(CIL)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
Pulse duration, X1/XCLKIN high as a percentage of
tc(CI)
tw(CIH)
(1) Not production tested.
Table 6-7. Possible PLL Configuration Modes(1)
PLL MODE
REMARKS
SYSCLKOUT
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled. Clock input to the
CPU (CLKIN) is directly derived from the clock signal present at the X1/XCLKIN pin.
PLL Disabled
XCLKIN
Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is bypassed.
PLL Bypassed However, the /2 module in the PLL block divides the clock input at the X1/XCLKIN pin by two before
feeding it to the CPU.
XCLKIN/2
Achieved by writing a non-zero value n into PLLCR register. The /2 module in the PLL block now
PLL Enabled
(XCLKIN × n)/2
divides the output of the PLL by two before feeding it to the CPU.
(1) Not production tested.
6.13.2 Output Clock Characteristics
Table 6-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1) (2)
NO.
C1
PARAMETER
Cycle time, XCLKOUT
MIN
6.67(3)
TYP
MAX
UNIT
ns
tc(XCO)
tf(XCO)
tr(XCO)
tw(XCOL)
tw(XCOH)
tp
C3(4)
C4(4)
C5(4)
C6(4)
C7(4)
Fall time, XCLKOUT
2
2
ns
Rise time, XCLKOUT
ns
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time(5)
H–2
H–2
H+2
H+2
ns
ns
131 072tc(CI)
ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) The PLL must be used for maximum frequency operation.
(4) Not production tested..
(5) This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.
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See Note A
See Note B
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in
Figure 6-8 is intended to illustrate the timing parameters only and may differ based on configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-8. Clock Timing
6.14 Reset Timing
Table 6-9. Reset (XRS) Timing Requirements(1) (2)
MIN
8tc(CI)
8tc(CI)
NOM
MAX
UNIT
cycles
cycles
tw(RSL1)
tw(RSL2)
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
Warm reset
WD-initiated reset
512tc(CI)
512tc(CI)
Pulse duration, reset pulse generated by
watchdog
tw(WDRS)
td(EX)
cycles
Delay time, address/data valid after XRS high
Oscillator start-up time
32tc(CI)
10
cycles
ms
(3)
tOSCST
1
16tc(CI)
16tc(CI)
tsu(XPLLDIS)
th(XPLLDIS)
th(XMP/MC)
th(boot-mode)
Setup time for XPLLDIS pin
Hold time for XPLLDIS pin
cycles
cycles
cycles
cycles
Hold time for XMP/MC pin
16tc(CI)
(4)
Hold time for boot-mode pins
2520tc(CI)
(1) If external oscillator/clock source isused, reset time has to be low at least for 1 ms after VDD reaches 1.5 V.
(2) Not production tested.
(3) Dependent on crystal/resonator and board design.
(4) The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the
TMS320x281x Boot ROM Reference Guide (literature number SPRU095) and TMS320x281x System Control and Interrupts Reference
Guide (literature number SPRU078) for further information.
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V
V
, V
DDIO DD3VFL
2.5 V
0.3 V
, V
DDAn DDAIO
(3.3 V)
(See Note B)
V
, V
DD DD1
(1.8 V (or 1.9 V))
XCLKIN
X1
XCLKIN/8 (See Note C)
XCLKOUT
User-Code Dependent
t
OSCST
t
w(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
User-Code Execution Phase
User-Code Dependent
t
d(EX)
t
su(XPLLDIS)
t
h(XPLLDIS)
XPLLDIS Sampling
(Don’t Care)
XF/XPLLDIS
XMP/MC
GPIOF14
t
h(XMP/MC)
(Don’t Care)
t
h(boot-mode)
(See Note D)
User-Code Dependent
Boot-Mode Pins
See Note A
GPIO Pins as Input
Peripheral/GPIO Function
Based on Boot Code
Boot-ROM Execution Starts
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
I/O Pins
NOTES: A. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V
and 3.3-V supply reaches 2.5 V.
B.
V
DDAn
− V
/V
and AV
DDA1 DDA2 DDREFBG
C. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2
register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why
XCLKOUT = XCLKIN/8 during this phase.
D. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then
samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot
code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution
time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on
the current SYSCLKOUT speed. The SYSCLKOUT is based on user environment and could be with or without PLL enabled.
Figure 6-9. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)
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V
V
, V
DDIO DD3VFL
2.5 V
0.3 V
, V
DDAn DDAIO
(3.3 V)
V
, V
DD DD1
(1.8 V (or
1.9 V))
XCLKIN
X1
t
OSCST
XCLKOUT
XRS
User-Code Dependent
XCLKIN/8 (See Note A)
t
w(RSL)
Address/Data/Control Valid Execution
Begins From External Boot Address 0x3FFFC0
t
d(EX)
Address/Data/
Control
(Don’t Care)
XPLLDIS Sampling
(Don’t Care)
t
h(XPLLDIS)
XF/XPLLDIS
XMP/MC
GPIOF14/XF (User-Code Dependent)
t
su(XPLLDIS)
(Don’t Care)
t
h(XMP/MC)
I/O Pins
User-Code Dependent
See Note B
Input Configuration (State Depends on Internal PU/PD)
NOTES: A. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2
register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why
XCLKOUT = XCLKIN/8 during this phase.
B. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V
and 3.3-V supply reaches 2.5 V..
Figure 6-10. Power-on Reset in Microprocessor Mode (XMP/MC = 1)
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XCLKIN
X1
XCLKIN/8
XCLKOUT
(XCLKIN * 5)
User-Code Dependent
t
w(RSL2)
XRS
User-Code Execution Phase
t
d(EX)
Address/Data/
Control
(Don’t Care)
User-Code Execution
GPIOF14/XF
t
t
su(XPLLDIS)
h(XPLLDIS)
(Don’t Care)
XF/XPLLDIS
XMP/MC
GPIOF14
User-Code Dependent
(Don’t Care)
XPLLDIS Sampling
t
h(XMP/MC)
(Don’t Care)
t
(see Note A)
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Peripheral/GPIO Function
User-Code Dependent
Boot-Mode Pins
I/O Pins
Peripheral/GPIO Function
User-Code Execution Starts
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and
then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination
memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN
cycles from boot ROM execution time for proper selection of Boot modes. If Boot ROM code executes after power-on
conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT is based on user environment and could be with or without PLL enabled.
Figure 6-11. Warm Reset in Microcomputer Mode
X1/XCLKIN
Write to PLLCR
SYSCLKOUT
XCLKIN x 2
XCLKIN/2
XCLKIN x 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(Changed CPU Frequency)
(PLL Lock-up Time, t ) is
p
131072 XCLKIN Cycles Long.)
Figure 6-12. Effect of Writing Into PLLCR Register
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6.15 Low-Power Mode Wakeup Timing
Table 6-10 is also the IDLE Mode Wake-Up Timing Requirements table.
Table 6-10. IDLE Mode Switching Characteristics(1)
PARAMETER
TEST CONDITIONS
Without input qualifier
With input qualifier
MIN
2 x tc(SCO)
1 × tc(SCO) + IQT(2)
TYP
MAX
UNIT
Cycles
Cycles
Pulse duration, external wake-up
signal
tw(WAKE-INT)
Delay time, external wake signal
to program execution resume(3)
–Wake-up from Flash
–Flash module in active state
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
8 × tc(SCO)
8 × tc(SCO) + IQT(2)
1050 × tc(SCO)
Cycles
Cycles
Cycles
Cycles
– Wake-up from Flash
–Flash module in active state
td(WAKE-IDLE)
–Wake-up from Flash
–Flash module in sleep state
–Wake-up from Flash
–Flash module in sleep state
1050 × tc(SCO) + IQT(2)
–Wake-up from SARAM
–Wake-up from SARAM
Without input qualifier
With input qualifier
8 × tc(SCO)
8 × tc(SCO) + IQT(2)
Cycles
Cycles
(1) Not production tested.
(2) Input Qualification Time (IQT) = [5 × QUALPRD × 2] × tc(SCO)
(3) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up) signal involves additional latency.
t
d(WAKE−IDLE)
A0−A15
XCLKOUT
(see Note A)
t
w(WAKE−INT)
WAKE INT
(see Note B)
A. XCLKOUT = SYSCLKOUT
B. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-13. IDLE Entry and Exit Timing
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Table 6-11 is also the STANDBY Mode Wake-Up Timing Requirements table.
Table 6-11. STANDBY Mode Switching Characteristics(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT high
td(IDLE-XCOH)
32 × tc(SCO)
12 × tc(CI)
Cycles
Without input
qualifier
12 × tc(CI)
Cycles
Cycles
Pulse duration, external
wake-up signal
tw(WAKE-INT)
With input qualifier
(2 + QUALSTDBY)(2) × tc(CI)
Delay time, external wake
signal to program execution
resume(3)
–Wake-up from Flash
–Flash module in active
state
Without input
qualifier
12 × tc(CI)
12 × tc(CI) + tw(WAKE-INT)
1125 × tc(SCO)
Cycles
Cycles
Cycles
Cycles
–Wake-up from Flash
–Flash module in active
state
With input qualifier
td(WAKE-STBY)
–Wake-up from Flash
–Flash module in sleep
state
Without input
qualifier
–Wake-up from Flash
–Flash module in sleep
state
With input qualifier
1125 × tc(SCO) + tw(WAKE-INT)
Without input
qualifier
–Wake-up from SARAM
–Wake-up from SARAM
12 x tc(CI)
Cycles
Cycles
With input qualifier
12 × tc(CI) + tw(WAKE-INT)
(1) Not production tested.
(2) QUALSTDBY is a 6-bit field in the LPMCR0 register.
(3) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up) signal involves additional latency.
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A
C
E
B
D
F
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake−up
Signal
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/XCLKIN
t
d(IDLE−XCOH)
†
XCLKOUT
32 SYSCLKOUT Cycles
NOTES: A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned
off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. The device is now in STANDBY mode.
D. The external wake-up signal is driven active (negative edge triggered shown as an example).
E. After a latency period, the STANDBY mode is exited.
F. Normal operation resumes. The device responds to the interrupt (if enabled).
Figure 6-14. STANDBY Entry and Exit Timing
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Table 6-12. HALT Mode Switching Characteristics(1)
PARAMETER
MIN
TYP
MAX
UNIT
Delay time, IDLE instruction executed to XCLKOUT
high
td(IDLE-XCOH)
32 × tc(SCO)
45 × tc(SCO)
Cycles
tw(WAKE-XNMI)
tw(WAKE-XRS)
tp
Pulse duration, XNMI wakeup signal
Pulse duration, XRS wakeup signal
PLL lock-up time
2 × tc(CI)
8 × tc(CI)
Cycles
Cycles
Cycles
131 072 × tc(CI)
Delay time, PLL lock to program execution resume
–Wake-up from flash
–Flash module in sleep state
td(wake)
1125 × tc(SCO
)
Cycles
Cycles
–Wake-up from SARAM
35 × tc(SCO)
(1) Not production tested.
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A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned
off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush perperly.
C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT
mode and consumes absolute minimum power.
D. When XNMI is friven active (negative edge triggered shown, as an example), the oscillator is turned on; but the PLL is
not activiated.
E. When XNMI is deactiveted, it initiates the PLL lock sequence, which takes 131, 072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device responds to the interrupt (if enabled), after a latency. The HALT mode
is now exited.
G. Normal operation resumes.
H. XCLKOUT = SYSCLKOUT
Figure 6-15. HALT Wakeup Using XNMI
6.16 Event Manager Interface
6.16.1 PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
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Table 6-13. PWM Switching Characteristics(1) (2)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
ns
(3) (4)
tw(PWM)
Pulse duration, PWMx output high/low
Delay time, XCLKOUT high to PWMx output switching
25
td(PWM)XCO
XCLKOUT = SYSCLKOUT/4
10
ns
(1) See the GPIO output timing for fall/rise times for PWM pins.
(2) PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
(3) PWM outputs may be 100%, 0%, or increments of tc(HCO) with respect to the PWM period.
(4) Not production tested.
Table 6-14. Timer and Capture Unit Timing Requirements(1) (2) (3)
MIN
MAX
UNIT
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
2 × tc(SCO)
1 × tc(SCO) + IQT(4)
2 × tc(SCO)
tw(TDIR)
Pulse duration, TDIRx low/high
cycles
tw(CAP)
Pulse duration, CAPx input low/high
cycles
1 x tc(SCO) + IQT(4)
tw(TCLKINL)
tw(TCLKINH)
tc(TCLKIN)
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time
Cycle time, TCLKINx
40
60
60
%
%
ns
40
4 × tc(HCO)
(1) The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling
period is 2n SYSCLKOUT cycles, where n is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the
qualification sampling period is 1 × 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2 SYSCLKOUT cycles). Six such samples
are taken over five sampling windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width that is
needed is 5 × 2 = 10 SYSCLKOUT cycles. However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse
ensures reliable recognition.
(2) Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]
(3) Not production tested.
(4) Input Qualification Time (IQT) = [5 × QUALPRD × 2] × tc(SCO)
XCLKOUT
(see Note A)
t
d(PWM)XCO
t
w(PWM)
PWMx
A. XCLKOUT = SYSCLKOUT
Figure 6-16. PWM Output Timing
XCLKOUT
(see Note A)
t
w(TDIR)
TDIRx
A. XCLKOUT = SYSCLKOUT
Figure 6-17. TDIRx Timing
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Table 6-15. External ADC Start-of-Conversion – EVA – Switching Characteristics(1) (2)
PARAMETER
MIN
MAX
UNIT
cycle
ns
td(XCOH-EVASOCL)
tw(EVASOCL)
Delay time, XCLKOUT high to EVASOC low
Pulse duration, EVASOC low
1 × tc(SCO)
32 × tc(HCO)
(1) XCLKOUT = SYSCLKOUT
(2) Not production tested.
XCLKOUT
t
d(XCOH-EVASOCL)
t
w(EVASOCL)
EVASOC
Figure 6-18. EVASOC Timing
Table 6-16. External ADC Start-of-Conversion – EVB – Switching Characteristics(1) (2)
PARAMETER
MIN
MAX UNIT
1 × tc(SCO) cycle
ns
td(XCOH-EVBSOCL)
tw(EVBSOCL)
Delay time, XCLKOUT high to EVBSOC low
Pulse duration, EVBSOC low
32 × tc(HCO)
(1) XCLKOUT = SYSCLKOUT
(2) Not production tested.
XCLKOUT
t
d(XCOH-EVBSOCL)
t
w(EVBSOCL)
EVBSOC
Figure 6-19. EVBSOC Timing
6.16.2 Interrupt Timing
Table 6-17. Interrupt Switching Characteristics
PARAMETER
MIN
MAX
UNIT
Without input
qualifier
12
Delay time, PDPINTx low to PWM
high-impedance state
td(PDP-PWM)HZ
ns
1 × tc(SCO) + IQT +
12(1)
With input qualifier
Without input
qualifier
3 × tc(SCO)
Delay time, CxTRIP/TxCTRIP signals low
to PWM high-impedance state
(2)
td(TRIP-PWM)HZ
ns
ns
With input qualifier
[2 × tc(SCO)] + IQT(1)
Delay time, INT low/high to
interrupt-vector fetch
(2)
td(INT)
tqual + 12tc(XCO)
(1) Input Qualification Time (IQT) = [5 × QUALPRD × 2] × tc(SCO)
(2) Not production tested.
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Table 6-18. Interrupt Timing Requirements
MIN
2 × tc(SCO)
1 × tc(SCO) + IQT(2)
MAX
UNIT
with no qualifier
(1)
tw(INT)
Pulse duration, INT input low/high
cycles
with qualifier
with no qualifier
with qualifier
2 × tc(SCO)
tw(PDP)
Pulse duration, PDPINTx input low
Pulse duration, CxTRIP input low
Pulse duration, TxCTRIP input low
cycles
cycles
cycles
1 × tc(SCO) + IQT(2)
2 × tc(SCO)
1 × tc(SCO) + IQT(2)
with no qualifier
with qualifier
(1)
tw(CxTRIP)
with no qualifier
with qualifier
2 × tc(SCO)
1 × tc(SCO) + IQT(2)
(1)
tw(TxCTRIP)
(1) Not production tested.
(2) Input Qualification Time (IQT) = [5 × QUALPRD × 2] × tc(SCO)
XCLKOUT
(see Note A)
t
, t
, t
w(PDP) w(CxTRIP) w(TxCTRIP)
TxCTRIP, CxTRIP,
PDPINTx
(see Note B)
t
, t
d(PDP-PWM)HZ d(TRIP-PWM)HZ
PWM
(see Note C)
t
w(INT)
XNMI, XINT1, XINT2
t
d(INT)
Interrupt Vector
A0−A15
A. XCLKOUT = SYSCLKOUT
B. TxCTRIP – T1CTRIP, T2CTRIP, T3CTRIP, T4CTRIP . CxTRIP – C1TRIP, C2TRIP, C3TRIP, C4TRIP, C5TRIP, or
C6TRIP. PDPINTx – PDPINTA or PDPINTB
C. PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins or PWM pin pair relevant to each
CxTRIP pin). The state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit.
Figure 6-20. External Interrupt Timing
6.17 General-Purpose Input/Output (GPIO) – Output Timing
Table 6-19. General-Purpose Output Switching Characteristics
PARAMETER
Delay time, XCLKOUT high to GPIO low/high
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
MIN
MAX
UNIT
cycle
ns
td(XCOH-GPO)
All GPIOs
All GPIOs
All GPIOs
1 × tc(SCO)
(1)
tr(GPO)
10
10
20
(1)
tf(GPO)
ns
(1)
fGPO
MHz
(1) Not production tested.
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XCLKOUT
t
d(XCOH-GPO)
GPIO
t
r(GPO)
t
f(GPO)
Figure 6-21. General-Purpose Output Timing
6.18 General-Purpose Input/Output (GPIO) – Input Timing
See Note A
GPIO
Signal
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
QUALPRD
Sampling Window
QUALPRD = 1
SYSCLKOUT
(2 x SYSCLKOUT cycles) x 5
Output From
Qualifier
NOTES: A. This glitch is ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00
to 0xFF. Input qualification is not applicable when QUALPRD = 00. For any other value n, the qualification sampling period in 2n
SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycle, the GPIO pin is sampled). Six consecutive samples must be of the
same value for a given input to be recognized.
B. For the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs
should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure six sampling windows for detection to occur.
Since external signals are driven asynchronously, an 11-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 6-22. GPIO Input Qualifier – Example Diagram for QUALPRD = 1
Table 6-20. General-Purpose Input Timing Requirements(1)
MIN
2 × tc(SCO)
1 × tc(SCO) + IQT(2)
MAX
UNIT
With no qualifier
With qualifier
tw(GPI)
Pulse duration, GPIO low/high
All GPIOs
cycles
(1) Not production tested.
(2) Input Qualification Time (IQT) = [5 × QUALPRD × 2] × tc(SCO)
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XCLKOUT
GPIOxn
t
w(GPI)
Figure 6-23. General-Purpose Input Timing
NOTE
The pulse width requirement for general-purpose input is applicable for the XBIO and
ADCSOC pins as well.
6.19 SPI Master Mode Timing
Table 6-21. SPI Master Mode External Timing (Clock Phase = 0)(1) (2) (3)
SPI WHEN (SPIBRR + 1)
IS EVEN OR
SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1)
IS ODD AND
NO.
UNIT
ns
SPIBRR > 3
MIN
MAX
MIN
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
Pulse duration, SPICLK high
(clock polarity = 0)
tw(SPCH)M
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
–10
0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10
0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10
0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO)
0.5tc(SPC)M – 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
10
2(4)
ns
Pulse duration, SPICLK low
(clock polarity = 1)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
tw(SPCL)M
3(4)
4(4)
5(4)
8(4)
9(4)
ns
ns
ns
ns
ns
Pulse duration, SPICLK high
(clock polarity = 1)
tw(SPCH)M
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
tv(SPCL-SOMI)M
tv(SPCH-SOMI)M
10
10
–10
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
–10
–10
0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M + 0.5tc(LCO) – 10
0
10
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
0
0
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25tc(SPC)M – 10
0.25tc(SPC)M – 10
0.5tc(SPC)M – 0.5tc(LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO) – 10
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
LSPCLK
LSPCLK
(SPIBRR ) 1)
tc(SPC) + SPI clock cycle time +
or
+ tc(LCO) + LSPCLK cycle time
4
(2)
(3) Not production tested.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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NOTE
Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than
the I/O buffer speed limit (20 MHz).
1
SPICLK
(clock polarity = 0)
2
4
3
SPICLK
(clock polarity = 1)
5
SPISIMO
SPISOMI
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISTE
(see Note A)
A. In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-24. SPI Master Mode External Timing (Clock Phase = 0)
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Table 6-22. SPI Master Mode External Timing (Clock Phase = 1)(1) (2) (3)
SPI WHEN (SPIBRR + 1)
IS EVEN OR
SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1)
IS ODD AND
NO.
UNIT
ns
SPIBRR > 3
MIN
MAX
MIN
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
Pulse duration, SPICLK high
(clock polarity = 0)
tw(SPCH)M
tw(SPCL)M
tw(SPCL)M
tw(SPCH)M
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10
0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10
0.5tc(SPC)M – 0.5tc(LCO)
0.5tc(SPC)M – 0.5tc(LCO)
0.5tc(SPC)M – 0.5tc(LCO)
0.5tc(SPC)M – 0.5tc(LCO)
2(4)
ns
Pulse duration, SPICLK low
(clock polarity = 1)
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)M
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) – 10
0.5tc(SPC)M + 0.5tc(LCO) – 10
3(4)
ns
ns
Pulse duration, SPICLK high
(clock polarity = 1)
Setup time, SPISIMO data valid
before SPICLK high (clock
polarity = 0)
tsu(SIMO-SPCH)M
tsu(SIMO-SPCL)M
tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0
6(4)
Setup time, SPISIMO data valid
before SPICLK low (clock
polarity = 1)
Valid time, SPISIMO data valid
after SPICLK high (clock polarity
= 0)
7(4)
ns
ns
ns
Valid time, SPISIMO data valid
after SPICLK low (clock polarity
= 1)
Setup time, SPISOMI before
SPICLK high
(clock polarity = 0)
10(4)
Setup time, SPISOMI before
SPICLK low
(clock polarity = 1)
0
0
Valid time, SPISOMI data valid
after SPICLK high (clock polarity
= 0)
0.25tc(SPC)M – 10
0.25tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
11(4)
Valid time, SPISOMI data valid
after SPICLK low (clock polarity
= 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
LSPCLK
LSPCLK
(SPIBRR ) 1)
tc(SPC) + SPI clock cycle time +
or
+ tc(LCO) + LSPCLK cycle time
4
(2)
(3) Not production tested..
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
SPISOMI
Master Out Data Is Valid
10
Data Valid
11
Master In Data
Must Be Valid
SPISTE
(see Note A)
A. In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-25. SPI Master External Timing (Clock Phase = 1)
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6.20 SPI Slave Mode Timing
Table 6-23. SPI Slave Mode External Timing (Clock Phase = 0)(1) (2) (3)
NO.
MIN
MAX
UNIT
(2)
12
tc(SPC)S
Cycle time, SPICLK
4tc(LCO)
ns
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S – 10
0.5tc(SPC)S – 10
0.5tc(SPC)S – 10
0.5tc(SPC) – 10
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
13(4)
14(4)
ns
ns
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
td(SPCH-SOMI)S
td(SPCL-SOMI)S
tv(SPCL-SOMI)S
0.375tc(SPC)S – 10
0.375tc(SPC)S – 10
0.75tc(SPC)S
15(4)
ns
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
16(4)
19(4)
20(4)
ns
ns
ns
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
tv(SPCH-SOMI)S
0.75tc(SPC)S
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
0
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
tv(SPCL-SIMO)S
tv(SPCH-SIMO)S
0.5tc(SPC)S
0.5tc(SPC)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
LSPCLK
LSPCLK
(SPIBRR ) 1)
tc(SPC) + SPI clock cycle time +
or
+ tc(LCO) + LSPCLK cycle time
4
(2)
(3) Not production tested.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISIMO
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISTE
(see Note A)
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-26. SPI Slave Mode External Timing (Clock Phase = 0)
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Table 6-24. SPI Slave Mode External Timing (Clock Phase = 1)(1) (2) (3)
NO.
MIN
8tc(LCO)
MAX
UNIT
12
tc(SPC)S
Cycle time, SPICLK
ns
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S – 10
0.5tc(SPC)S – 10
0.5tc(SPC)S – 10
0.5tc(SPC)S – 10
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
13(4)
14(4)
ns
ns
Setup time, SPISOMI before SPICLK high (clock polarity =
0)
tsu(SOMI-SPCH)S
tsu(SOMI-SPCL)S
tv(SPCH-SOMI)S
tv(SPCL-SOMI)S
tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
tv(SPCH-SIMO)S
tv(SPCL-SIMO)S
0.125tc(SPC)S
0.125tc(SPC)S
0.75tc(SPC)S
0.75tc(SPC)S
0
17(4)
18(4)
21(4)
22(4)
ns
ns
ns
ns
Setup time, SPISOMI before SPICLK low (clock polarity =
1)
Valid time, SPIS OMI data valid after SPICLK high
(clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
Setup time, SPISIMO before SPICLK high (clock polarity =
0)
Setup time, SPISIMO before SPICLK low (clock polarity =
1)
0
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S
0.5tc(SPC)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
LSPCLK
LSPCLK
(SPIBRR ) 1)
tc(SPC) + SPI clock cycle time +
or
+ tc(LCO) + LSPCLK cycle time
4
(2)
(3) Not production tested.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
SPISIMO
SPISOMI Data Is Valid
21
Data Valid
22
SPISIMO Data
Must Be Valid
SPISTE
(see Note A)
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-27. SPI Slave Mode External Timing (Clock Phase = 1)
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6.21 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone. Table 6-25 shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-25. Relationship Between Parameters Configured in XTIMING and Duration of Pulse(1) (2) (3)
DURATION (ns)
DESCRIPTION
X2TIMING = 0
XRDLEAD × tc(XTIM)
X2TIMING = 1
LR
Lead period, read access
Active period, read access
Trail period, read access
Lead period, write access
Active period, write access
Trail period, write access
(XRDLEAD × 2) × tc(XTIM)
AR
TR
LW
AW
TW
(XRDACTIVE + WS + 1) × tc(XTIM)
XRDTRAIL × tc(XTIM)
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
(XWRACTIVE + WS + 1) x tc(XTIM)
XWRTRAIL × tc(XTIM)
(XWRACTIVE × 2 + WS + 1) × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
(1) Not production tested.
(2) tc(XTIM) – Cycle time, XTIMCLK
(3) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait state requirements must be met when configuring each zone's XTIMING register. These
requirements are in addition to any timing requirements as specified by that device's data sheet. No
internal device hardware is included to detect illegal settings.
• If the XREADY signal is ignored (USEREADY = 0), then:
1. Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
Table 6-26. XTIMING Register Configuration Restrictions(1) (2)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 0
≥ 0
≥ 1
≥ 0
≥ 0
0, 1
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
Examples
of
valid
and
invalid
timing
when
not
sampling
XREADY:
Table 6-27. Valid and Invalid Timing(1) (2)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid
Valid
0
1
0
0
0
0
0
1
0
0
0
0
0, 1
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
• If the XREADY signal is sampled in the Synchronous mode (USEREADY = 1, READYMODE = 0),
then:
1. Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
2. Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
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NOTE
Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions:
Table 6-28. XTIMING Register Configuration Restrictions(1) (2)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 1
≥ 0
≥ 1
≥ 1
≥ 0
0, 1
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
Examples of valid and invalid timing when using Synchronous XREADY:
Table 6-29. Valid and Invalid Timing when using Synchronous XREADY(1) (2)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid
Invalid
Valid
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0, 1
0, 1
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
• If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1),
then:
1. Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
2. Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
NOTE
Restriction does not include external hardware wait states
3. Lead + Active:
LR + AR ≥ 4 × tc(XTIM)
LW + AW ≥ 4 × tc(XTIM)
NOTE
Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions:
Table 6-30. XTIMING Register Configuration Restrictions(1) (2)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 2
0
≥ 1
≥ 2
0
0, 1
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
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or
Table 6-31. XTIMING Register Configuration Restrictions(1) (2)
XRDLEAD
≥ 2
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
0
≥ 2
≥ 1
0
0, 1
Examples of valid and invalid timing when using Asynchronous XREADY:
Table 6-32. Asynchronous XREADY(1) (2)
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
Invalid
Invalid
Valid
0
1
1
1
1
2
0
0
1
1
2
1
0
0
0
0
0
0
0
1
1
1
1
2
0
0
1
1
2
1
0
0
0
0
0
0
0, 1
0, 1
0
1
Valid
0, 1
0, 1
Valid
(1) Not production tested.
(2) No hardware to detect illegal XTIMING configurations
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-33.
Table 6-33. XINTF Clock Configurations
MODE
SYSCLKOUT
150 MHz
XTIMCLK
SYSCLKOUT
150 MHz
XCLKOUT
SYSCLKOUT
150 MHz
1
Example:
2
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
Example:
3
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
Example:
4
150 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
Example:
150 MHz
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XTIMING0
XTIMING1
XTIMING2
XTIMING6
XTIMING7
XBANK
LEAD/ACTIVE/TRAIL
SYSCLKOUT
XCLKOUT
C28x
CPU
†
XTIMCLK
0
1
0
1
/2
†
1
/2
0
0
XINTCNF2
(CLKOFF)
XINTCNF2
(XTIMCLK)
XINTCNF2
(CLKMODE)
†
Default Value after reset
Figure 6-28. Relationship Between XTIMCLK and SYSCLKOUT
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6.22 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock
XTIMCLK. Strobes such as XRD, XWE, and zone chip-select (XZCS) change state in relationship to the
rising edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or
one-half the frequency of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes changes state with respect to the
rising edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes change state
either on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables, the
notation XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising
edge (high) or XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of
XCLKOUT, the notation XCOH is used.
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change is aligned
can be determined based on the number of XTIMCLK cycles from the start of the access to the point at
which the signal changes. If this number of XTIMCLK cycles is even, the alignment is with respect to the
rising edge of XCLKOUT. If this number is odd, then the signal changes with respect to the falling edge of
XCLKOUT. Examples include the following:
•
Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
XZCSL
Zone chip-select active low
XR/W active low
XRNWL
•
Strobes that change at the beginning of the active period aligns to the rising edge of XCLKOUT if the
total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is
odd, then the alignment is with respect to the falling edge of XCLKOUT.
Examples:
XRDL
XWEL
XRD active low
XWE active low
•
•
Strobes that change at the beginning of the trail period aligns to the rising edge of XCLKOUT if the
total number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If
the number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment
is with respect to the falling edge of XCLKOUT.
Examples:
XRDH
XWEH
XRD inactive high
XWE inactive high
Strobes that change at the end of the access aligns to the rising edge of XCLKOUT if the total number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead +
active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment is with respect
to the falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive high
XR/W inactive high
XRNWH
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6.23 External Interface Read Timing
Table 6-34. External Memory Interface Read Switching Characteristics(1)
PARAMETER
MIN
MAX UNIT
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
1
3
2
1
1
ns
ns
ns
ns
ns
ns
ns
–2
td(XCOHL-XRDL)
td(XCOHL-XRDH
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
–2
(2)
(2)
th(XA)XRD
(1) Not production tested.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-35. External Memory Interface Read Timing Requirements(1)
MIN
MAX
(LR + AR) – 14(2)
AR – 12(2)
UNIT
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
ns
tsu(XD)XRD
th(XD)XRD
12
0
ns
ns
(1) Not production tested.
Trail
Active
Lead
XCLKOUT=XTIMCLK
XCLKOUT= 1/2 XTIMCLK
t
d(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
XA[0:18]
XRD
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
t
su(XD)XRD
XWE
XR/W
t
a(A)
t
h(XD)XRD
t
a(XRD)
DIN
XD[0:15]
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignmentcycle before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6-29. Example Read Access
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XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY
≥ 1 ≥ 0 ≥ 0
(1) N/A = "Don't care" for this example
X2TIMING
XWRLEAD
N/A(1)
XWRACTIVE XWRTRAIL READYMODE
0
0
N/A(1)
N/A(1)
N/A(1)
6.24 External Interface Write Timing
Table 6-36. External Memory Interface Write Switching Characteristics(1)
PARAMETER
MIN
MAX
UNIT
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/W low
1
3
2
2
2
1
1
ns
ns
–2
ns
td(XCOH-XA)
td(XCOHL-XWEL)
ns
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
ns
ns
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE low
Delay time, data valid after XWE active low
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE inactive high
Data bus disabled after XR/W inactive high
–2
0
ns
ns
td(XWEL-XD)
4
ns
(2)ns
th(XA)XZCSH
th(XD)XWE
TW–2(3)
4
ns
tdis(XD)XRNW
ns
(1) Not production tested.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Active
Lead
Trail
XCLKOUT=XTIMCLK
XCLKOUT= 1/2 XTIMCLK
t
d(XCOHL-XZCSH)
t
d(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
t
d(XCOH-XA)
XA[0:18]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
XR/W
t
t
dis(XD)XRNW
d(XWEL-XD)
t
t
en(XD)XWEL
h(XD)XWEH
DOUT
XD[0:15]
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6-30. Example Write Access
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XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY
N/A(1) N/A(1) N/A(1)
(1) N/A = "Don't care" for this example
X2TIMING
XWRLEAD
XWRACTIVE XWRTRAIL READYMODE
0
0
≥ 1
≥ 0
≥ 0
N/A(1)
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6.25 External Interface Ready-on-Read Timing With One External Wait State
Table 6-37. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)(1)
PARAMETER
MIN
MAX UNIT
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
1
3
2
1
1
ns
ns
ns
ns
ns
ns
ns
–2
td(XCOHL-XRDL)
td(XCOHL-XRDH
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
–2
(2)
(2)
th(XA)XRD
(1) Not production tested.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-38. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)(1)
MIN
MAX
(LR + AR) – 14(2)
AR – 12(2)
UNIT
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
ns
tsu(XD)XRD
th(XD)XRD
12
0
ns
ns
(1) Not production tested.
Table 6-39. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)(1) (2)
MIN
15
MAX UNIT
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (Synch) low before XCLKOUT high/low
Hold time, XREADY (Synch) low
ns
ns
12
te(XRDYsynchH)
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Synch) high before XCLKOUT high/low
Hold time, XREADY (Synch) held high after zone chip select high
3
ns
ns
ns
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
15
0
(1) Not production tested.
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access completes. If XREADY (Synch) is found to be low, it is
sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-40. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)(1) (2)
MIN
11
8
MAX
UNIT
ns
tsu(XRDYAsynchL)XCOHL
th(XRDYAsynchL)
Setup time, XREADY (Asynch) low before XCLKOUT high/low
Hold time, XREADY (Asynch) low
ns
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT
edge
te(XRDYAsynchH)
3
ns
(1) Not production tested.
E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access completes. If XREADY (Asynch) is found to be low, it wis
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
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(1) (2)
Table 6-40. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
(continued)
MIN
11
0
MAX
UNIT
ns
tsu(XRDYAsynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (Asynch) high before XCLKOUT high/low
Hold time, XREADY (Asynch) held high after zone chip select high
ns
WS (Synch)
See Notes A and B
Active
See Note C
Lead
Trail
XCLKOUT=XTIMCLK
XCLKOUT= 1/2 XTIMCLK
t
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
d(XCOH-XA)
XA[0:18]
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
t
su(XD)XRD
XWE
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
XD[0:15]
DIN
t
su(XRDYsynchL)XCOHL
t
e(XRDYsynchH)
t
h(XRDYsynchL)
t
h(XRDYsynchH)XZCSH
t
su(XRDHsynchH)XCOHL
XREADY(Synch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment
cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n − 1) t
− t
su(XRDYsynchL)XCOHL
c(XTIM)
E. Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) t
c(XTIM)
where n is the sample number: n = 1, 2, 3, and so forth.
Figure 6-31. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY
≥ 1 ≥ 1
(1) N/A = "Don't care" for this example
X2TIMING
XWRLEAD
XWRACTIVE XWRTRAIL READYMODE
0 = XREADY
3
1
0
N/A(1)
N/A(1)
N/A(1)
(Synch)
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WS (Asynch)
Active
S
e
e
N
o
t
e
s
See Note C
Lead
Trail
A
a
n
d
B
XCLKOUT=XTIMCLK
XCLKOUT= 1/2 XTIMCLK
t
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
XZCS0AND1, XZCS2,
XZCS6AND7
d(XCOH-XA)
XA[0:18]
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
XWE
XR/W
t
su(XD)XRD
t
a(XRD)
t
a(A)
t
h(XD)XRD
DIN
XD[0:15]
t
su(XRDYasynchL)XCOHL
t
e(XRDYasynchH)
t
h(XRDYasynchH)XZCSH
t
h(XRDYasynchL)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. During inactive cycles, the XINTF address bus always hold sthe last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE −3 +n) t
− t
su(XRDYasynchL)XCOHL
c(XTIM)
where n is the sample number: n = 1, 2, 3, and so forth.
E. Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE −2) t
c(XTIM)
Figure 6-32. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY
≥ 1 ≥ 1
X2TIMING
XWRLEAD
XWRACTIVE XWRTRAIL READYMODE
1 = XREADY
3
1
0
N/A(1)
N/A(1)
N/A(1)
(Asynch)
(1) N/A = "Don't care" for this example
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6.26 External Interface Ready-on-Write Timing With One External Wait State
Table 6-41. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)(1)
PARAMETER
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/W low
1
3
2
2
2
1
1
–2
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE low
Delay time, data valid after XWE active low
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE inactive high
Data bus disabled after XR/W inactive high
–2
0
td(XWEL-XD)
4
(2)
th(XA)XZCSH
th(XD)XWE
TW–2(3)
4
tdis(XD)XRNW
(1) Not production tested.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-42. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1) (2)
MIN
15
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (Synch) low before XCLKOUT high/low
Hold time, XREADY (Synch) low
12
ns
te(XRDYsynchH)
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Synch) high before XCLKOUT high/low
Hold time, XREADY (Synch) held high after zone chip select high
3
ns
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
15
0
ns
ns
(1) Not production tested.
E =(XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access completes. If XREADY (Synch) is found to be low, it is
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D =(XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-43. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1) (2)
MIN
11
8
MAX UNIT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
Setup time, XREADY (Asynch) low before XCLKOUT high/low
Hold time, XREADY (Asynch) low
ns
ns
te(XRDYasynchH)
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Asynch) high before XCLKOUT high/low
Hold time, XREADY (Asynch) held high after zone chip select high
3
ns
ns
ns
tsu(XRDYasynchH)XCOHL
th(XRDYasynchH)XZCSH
11
0
(1) Not production tested.
(2) The first XREADY (Synch) sample occurs with respect to E in Figure 6-33:
E = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access completes. If XREADY (Asynch) is found to be low, it is
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
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WS (Synch)
Active
See
See Note C
Trail
Notes A
and B
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
t
t
h(XRDYsynchH)XZCSH
d(XCOH-XA)
XA[0:18]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
)
t
h(XD)XWEH
t
en(XD)XWEL
XD[0:15]
DOUT
t
su(XRDYsynchL)XCOHL
t
e(XRDYsynchH)
t
h(XRDYsynchL)
t
su(XRDHsynchH)XCOHL
XREADY(Synch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES:
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access
to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as
D = (XWRLEAD + XWRACTIVE + n − 1) t
− t
su(XRDYsynchL)XCOHL
c(XTIM)
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE) t
c(XTIM)
Figure 6-33. Write With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY
N/A(1) N/A(1) N/A(1)
X2TIMING
XWRLEAD
XWRACTIVE XWRTRAIL READYMODE
0 = XREADY
1
0
≥ 1
3
≥ 1
(Synch)
(1) N/A = "Don't care" for this example
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WS (Asynch)
Active
S
e
e
N
o
t
e
s
S
e
e
N
o
t
e
C
Trail
A
a
n
d
B
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
XZCS0AND1, XZCS2,
XZCS6AND7
t
h(XRDYasynchH)XZCSH
t
d(XCOH-XA)
XA[0:18]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE
t
t
d(XCOH-XRNWL)
d(XCOHL-XRNWH)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
)
t
h(XD)XWEH
t
en(XD)XWEL
XD[0:15]
DOUT
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
e(XRDYasynchH)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignmentcycle before an access to meet this requirement.
B. During alignment cycles, all signals transitions to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment
cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE −3 + n) t
− t
su(XRDYasynchL)XCOHL
c(XTIM)
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE −2) t
c(XTIM)
Figure 6-34. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY
N/A(1) N/A(1) N/A(1)
X2TIMING
XWRLEAD
XWRACTIVE XWRTRAIL READYMODE
1 = XREADY
1
0
≥ 1
3
≥ 1
(Asynch)
(1) N/A = "Don't care" for this example
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6.27 XHOLD and XHOLDA
f the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the
bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active
low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still
execute code from internal memory. If an access is made to the external interface, the CPU is stalled until
the XHOLD signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[18:0]
XD[15:0]
XWE, XRD
XR/W
XZCS0AND1
XZCS2
XZCS6AND7
All other signals not listed in this group remain in their default or functional operational modes during these
signal events. Detailed timing diagram is released in a future revision of this data sheet.
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6.28 XHOLD/XHOLDA Timing
Table 6-44. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)(1) (2) (3)
MIN
MAX UNIT
td(HL–HiZ)
td(HL–HAL)
td(HH–HAH)
td(HH–BV)
Delay time, XHOLD low to Hi–Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
4tc(XTIM)
ns
ns
ns
ns
5tc(XTIM)
3tc(XTIM)
4tc(XTIM)
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
(1) When a low signal is detected on XHOLD, all pending XINTF accesses are completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) Not production tested.
XCLKOUT
(/1 Mode)
t
d(HL-Hiz)
XHOLD
t
d(HH-HAH)
XHOLDA
t
d(HL-HAL)
t
d(HH-BV)
XR/W,
XZCS0AND1,
XZCS2,
High-Impedance
XZCS6AND7
Valid
XA[18:0]
XD[15:0]
Valid
High-Impedance
Valid
See Note A
See Note B
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-35. External Interface Hold Waveform
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Table 6-45. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)(1) (2) (3) (4)
MIN
MAX
4tc(XTIM) + tc(XCO)
4tc(XTIM) + 2tc(XCO)
4tc(XTIM)
UNIT
ns
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
ns
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
ns
6tc(XTIM)
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses are completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT.
Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value
specified.
(4) Not production tested.
See Note B
See Note A
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
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6.29 On-Chip Analog-to-Digital Converter
6.29.1 ADC Absolute Maximum Ratings
VALUE(1)
–0.3 to 4.6
–0.3 to 2.5
±20
UNIT
V
VSSA1/VSSA2 to VDDA1/VDDA2/AVDDREFBG
Supply voltage range
VSS1 to VDD1
V
Analog Input (ADCIN) Clamp Current, total (max)(2)
mA
(1) Unless otherwise noted, the absolute maximum ratings are specified over operating conditions. Stresses beyond those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above VDDA or below VSS. The continuous
clamp current per pin is ±2 mA.
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6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions
Table 6-46. DC Specifications(1) (2)
TA = –55°C to 220°C
PARAMETER
UNIT
MIN
TYP
MAX
Resolution
ADC clock(3)
12
1
Bits
kHz
MHz
25
ACCURACY
INL (Integral nonlinearity)(4)
DNL (Differential nonlinearity)(4)
Offset error(5)
1–18.75 MHz ADC clock
1–18.75 MHz ADC clock
±1.5
±1
LSB
LSB
LSB
–80
80
Overall gain error with internal
reference(6)
–200
200
50
LSB
LSB
Overall gain error with external
reference(7)
If ADCREFP-ADCREFM = 1 V ±0.1%
–50
Channel-to-channel offset variation
Channel-to-channel Gain variation
±8
±8
LSB
LSB
ANALOG INPUT
Analog input voltage (ADCINx to
ADCLO)(8)
0
3
5
V
ADCLO
–5
0
10
3
mV
pF
Input capacitance
Input leakage current
±5
mA
INTERNAL VOLTAGE REFERENCE(6)
Accuracy, ADCVREFP
Accuracy, ADCVREFM
1.9
2
1
2.1
V
V
0.95
1.05
Voltage difference, ADCREFP –
ADCREFM
1
V
Temperature coefficient
Reference noise
50
PPM/°C
V
100
EXTERNAL VOLTAGE REFERENCE(7)
Accuracy, ADCVREFP
Accuracy, ADCVREFM
1.9
2
1
2.1
V
V
0.95
1.05
Input voltage difference, ADCREFP –
ADCREFM
0.99
1
1.01
V
(1) Not production tested.
(2) Tested at 12.5-MHz ADCCLK
(3) If SYSCLKOUT ≤ 25 MHz, ADC clock ≤ SYSCLKOUT/2
(4) The INL degrades for frequencies beyond 18.75 MHz –25 MHz. Applications that require these sampling rates should use a 20-kΩ
resistor as bias resistor on the ADCRESEXT pin. This improves overall linearity and typical current drawn by the ADC is a few mA more
than 24.9 kW bias.
(5) 1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
(6) A single internal band gap reference (±5% accuracy) sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error is the combination of the gain
error shown here and the voltage reference accuracy (ADCREFP – ADCREFM). A software-based calibration procedure is
recommended for better accuracy. See F2812 ADC Calibration Application Note (literature number SPRA989) and Section 5.2,
Documentation Support, for relevant documents.
(7) In this mode, the accuracy of external reference is critical for overall gain. The voltage difference (ADCREFP–ADCREFM) determines
the overall accuracy.
(8) Voltages above VDDA + 0.3 V or below VSS – 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
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Table 6-47. AC Specifications(1) (2)
TA = –55°C to 125°C
TA = 220°C
PARAMETER
UNIT
MIN
TYP
62
MAX
MIN
TYP
57
MAX
SINAD
SNR
Signal-to-noise ratio + distortion
Signal-to-noise ratio
dB
dB
62
57
THD
Total harmonic distortion
Effective number of bits
Spurious free dynamic range
-68
10.1
69
-68
9.1
68
dB
ENOB (SNR)
SFDR
Bits
dB
(1) Not production tested.
(2) Validated at the following conditions: ADC Input Frequency = 10.71 KHz, XCLKIN = 30 MHz, PLLCR = 0xA (SYSCLK = 150 MHz),
HSPCP = 3 (ADCCLK= 25 MHz), ADCCLKPS = 1 (ADCCLK= 12.5 MHz), CPS = 0 (ADCCLK =12.5 MHZ), ACQ_PS (SH) = 3
6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
Table 6-48. Current Consumption(1)
IDDA (TYP)(2)
IDDAIO (TYP)
IDD1 (TYP)
ADC OPERATING MODE/CONDITIONS(3)
Mode A (Operational Mode):
40 mA
1 mA
0.5 mA
–BG and REF enabled
–PWD disabled
Mode B:
–ADC clock enabled
–BG and REF enabled
–PWD enabled
7 mA
0
0
0
5 mA
5 mA
0
Mode C:
–ADC clock enabled
–BG and REF disabled
–PWD enabled
1 mA
Mode D:
–ADC clock disabled
–BG and REF disabled
–PWD enabled
1 mA
(1) Not production tested.
(2) IDDA – includes current into VDDA1/ VDDA2 and AVDDREFBG
(3) Test Conditions: SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
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R
1 kΩ
on
Switch
R
s
ADCIN0
C
10 pF
C
h
1.25 pF
p
Source
Signal
ac
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (R ):
1 kΩ
1.25 pF
on
Sampling Capacitor (C ):
h
Parasitic Capacitance (C ): 10 pF
p
Source Resistance (R ):
50 Ω
s
Figure 6-37. ADC Analog Input Impedance Model
6.29.4 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
t
d(BGR)
PWDNADC
t
d(PWD)
Request for
ADC
Conversion
Figure 6-38. ADC Power-Up Control Bit Timing
Table 6-49. ADC Power-Up Delays(1) (2)
MIN
7
TYP
8
MAX UNIT
Delay time for band gap reference to be stable. Bits 6 and 5 of the ADCTRL3 register
(PWDNBG and PWDNREF) are to be set to 1 before the ADCPWDN bit is enabled.
td(BGR)
td(PWD)
10
ms
20
50
ms
Delay time for power-down control to be stable. Bit 7 of the ADCTRL3 register (ADCPWDN)
is to be set to 1 before any ADC conversions are initiated.
1
ms
(1) These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If
conversions are started without these delays, the ADC results shows a higher gain. For power down, all three bits can be cleared at the
same time.
(2) Not production tested.
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6.29.5 Detailed Description
6.29.5.1 Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP
is set to 2 V and ADCVREFM is set to 1 V.
6.29.5.2 Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at
a time. These inputs are software-selectable.
6.29.5.3 Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with
low power consumption.
6.29.5.4 Conversion Modes
The conversion can be performed in two different conversion modes:
•
•
Sequential sampling mode (SMODE = 0)
Simultaneous sampling mode (SMODE = 1)
6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC does conversions on the
selected channel on every Sample/Hold pulse. The conversion time and latency of the Result register
update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result
register update. The selected channel is sampled at every falling edge of the Sample/Hold pulse. The
Sample/Hold pulse width can be programmed to be one ADC clock wide (minimum) or 16 ADC clocks
wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Sample n
Channel Ax or Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschx_n+1
t
dschx_n
ADC Event Trigger from
EV or Other Sources
t
SH
Figure 6-39. Sequential Sampling Mode (Single-Channel) Timing
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Table 6-50. Sequential Sampling Mode Timing(1)
AT 25–MHz ADC
CLOCK,
SAMPLE n
SAMPLE n + 1
REMARKS
tc(ADCCLK) = 40 ns
Delay time from event trigger to
sampling
td(SH)
2.5tc(ADCCLK)
(1 + Acqps) ×
tc(ADCCLK)
Acqps value = 0-15
ADCTRL1[8:11]
tSH
Sample/Hold width/Acquisition width
40 ns with Acqps = 0
160 ns
Delay time for first result to appear
in the Result register
td(schx_n)
td(schx_n+1)
4tc(ADCCLK)
Delay time for successive results to
appear in the Result register
(2 + Acqps) ×
tc(ADCCLK)
80 ns
(1) Not production tested.
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6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB),
software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC does conversions on
two selected channels on every Sample/Hold pulse. The conversion time and latency of the Result
register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the
Result register update. The selected channels are sampled simultaneously at the falling edge of the
Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum)
or 16 ADC clocks wide (maximum).
NOTE
In Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, etc.).
Sample n
Sample n+2
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bv
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschA0_n+1
t
SH
ADC Event Trigger from
EV or Other Sources
t
t
dschA0_n
dschB0_n+1
t
dschB0_n
Figure 6-40. Simultaneous Sampling Mode Timing
Table 6-51. Simultaneous Sampling Mode Timing(1)
AT 25-MHz ADC
CLOCK,
SAMPLE n
SAMPLE n + 1
REMARKS
tc(ADCCLK) = 40 ns
Delay time from event
trigger to sampling
td(SH)
tSH
2.5tc(ADCCLK)
Sample/Hold
width/Acquisition Width
(1 + Acqps) ×
tc(ADCCLK)
Acqps value = 0–15
ADCTRL1[8:11]
40 ns with Acqps = 0
160 ns
Delay time for first result
to appear in Result
register
td(schA0_n)
td(schB0_n)
td(schA0_n+1)
4tc(ADCCLK)
Delay time for first result
to appear in Result
register
5tc(ADCCLK)
200 ns
120 ns
Delay time for successive
results to appear in Result
register
(3 + Acqps) ×
tc(ADCCLK)
(1) Not production tested.
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(1)
Table 6-51. Simultaneous Sampling Mode Timing
(continued)
AT 25-MHz ADC
SAMPLE n
SAMPLE n + 1
CLOCK,
REMARKS
tc(ADCCLK) = 40 ns
Delay time for successive
results to appear in Result
register
(3 + Acqps) ×
tc(ADCCLK)
td(schB0_n+1)
120 ns
6.29.8 Definitions of Specifications and Terminology
6.29.8.1 Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is
defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of
each particular code to the true straight line between these two points.
6.29.8.2 Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
6.29.8.3 Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
6.29.8.4 Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last
transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code transitions and the ideal difference between
first and last code transitions.
6.29.8.5 Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
6.29.8.6 Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(SINAD -1.76)
N =
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus,
effective number of bits for a device for sine wave inputs at a given input frequency can be calculated
directly from its measured SINAD.
6.29.8.7 Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
6.29.8.8 Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
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6.30 Multichannel Buffered Serial Port (McBSP) Timing
6.30.1 McBSP Transmit and Receive Timing
Table 6-52. McBSP Timing Requirements(1) (2) (3)
NO.
MIN
MAX
20(4)
1
UNIT
kHz
MHz
ns
1
McBSP module clock (CLKG, CLKX, CLKR) range
McBSP module cycle time (CLKG, CLKX, CLKR) range
50
ms
ns
M11
M12
M13
M14
tc(CKRX)
tw(CKRX)
tr(CKRX)
tf(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
2P
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
P–7
ns
7
7
ns
Fall time, CLKR/X
ns
18
2
M15
M16
M17
M18
M19
M20
tsu(FRH-CKRL)
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
0
6
18
2
0
Hold time, DR valid after CLKR low
6
18
2
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKX ext
CLKX int
0
CLKX ext
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the
timing references of that signal are also inverted.
CLKSRG
(1 ) CLKGDV)
CLKG +
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux.
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching
speed.
(3) Not production tested.
(4) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (20 MHz).
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Table 6-53. McBSP Switching Characteristics(1) (2) (3)
NO.
PARAMETER
MIN
MAX
UNIT
ns
M1
M2
M3
tc(CKRX)
tw(CKRXH)
tw(CKRXL)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
2P
D – 5(4)
C – 5(4)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D + 5(4)
C + 5(4)
ns
ns
0
3
0
3
4
27
M4
M5
M6
td(CKRH-FRV)
td(CKXH-FXV)
tdis(CKXH-DXHZ)
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
4
27
8
Disable time, CLKX high to DX high impedance following last
data bit
14
9
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
28
8
M7
td(CKXH-DXV)
Delay time, CLKX high to DX valid
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
ns
14
P + 8
P + 14
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY= 01b or 10b) modes
0
6
Enable time, CLKX high to DX driven
M8
M9
ten(CKXH-DX)
ns
ns
ns
P
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY= 01b or 10b) modes
P + 6
8
14
Delay time, FSX high to DX valid
FSX ext
td(FXH-DXV)
FSX int
P + 8
P + 14
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY= 00b) mode.
FSX ext
FSX int
0
6
Enable time, FSX high to DX driven
FSX ext
M10 ten(FXH-DX)
FSX int
P
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY= 00b) mode
FSX ext
P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns
(3) Not production tested.
(4) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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M1, M11
M2, M12
M3, M12
M13
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
(RDATDLY= 00b)
M18
DR
Bit (n−1)
(n−3)
(n−2)
(RDATDLY= 01b)
M17
M18
DR
Bit (n−1)
(RDATDLY= 10b)
Figure 6-41. McBSP Receive Timing
M1, M11
M2, M12
M13
M14
M3, M12
CLKX
FSX (int)
FSX (ext)
M5
M5
M19
M20
M9
M7
M7
M10
Bit 0
DX
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−3)
(n−2)
(XDATDLY= 00b)
M8
DX
Bit (n−1)
M8
(n−2)
M7
Bit 0
M6
(XDATDLY= 01b)
DX
Bit 0
Bit (n−1)
(XDATDLY= 10b)
Figure 6-42. McBSP Transmit Timing
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6.30.2 McBSP as SPI Master or Slave Timing
Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)(1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
P – 10
P – 10
MAX
M30
M31
M32
M33
tsu(DRV0CKXL)
th(CKXL0DRV)
tsu(BFXL0CKXH)
tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P
(1) Not production tested.
Table 6-55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)(1) (2)
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
2P
P
MAX
M24
M25
th(CKXL0FXL)
td(FXL0CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
ns
ns
Disable time, DX high impedance following last data bit from
FSX high
M28
M29
tdis(FXH0DXHZ)
td(FXL0DXV)
6
6
6P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) Not production tested.
(2) 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV
= 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16, that is 4.5 MHz and P = 13.3 ns.
M33
M32
MSB
LSB
CLKX
FSX
M25
M24
M28
M29
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M30
M31
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6-43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)(1)
MASTER
MIN
SLAVE
MIN
NO.
UNIT
MAX
MAX
M39
M40
M41
M42
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXH)
tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
P – 10
8P – 10
ns
ns
ns
ns
P – 10
2P
8P – 10
16P + 10
16P
(1) Not production tested.
Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)(1) (2)
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
P
MAX
M34
M35
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
ns
ns
2P
Disable time, DX high impedance following last data bit
from CLKX low
M37
M38
tdis(CKXL-DXHZ)
td(FXL-DXV)
P + 6
6
7P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) Not production tested.
(2) 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV
= 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns.
M42
MSB
LSB
M41
CLKX
FSX
DX
M35
M34
M37
M38
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
M39
M40
(n-2)
DR
Bit 0
(n-3)
(n-4)
Figure 6-44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)(1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
P – 10
P – 10
MAX
M49 tsu(DRV-CKXH)
M50 th(CKXH-DRV)
M51 tsu(FXL-CKXL)
M52 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P
(1) Not production tested.
Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)(1) (2)
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
2P
P
MAX
M43 th(CKXH-FXL)
M44 td(FXL-CKXL)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
Disable time, DX high impedance following last data bit from FSX
high
M47 tdis(FXH-DXHZ)
M48 td(FXL-DXV)
6
6
6P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) Not production tested.
(2) 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV
= 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns.
M52
M51
MSB
LSB
CLKX
FSX
M43
M44
M48
M47
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
M50
(n-3)
(n-4)
M49
Bit 0
(n-2)
(n-3)
(n-4)
Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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Table 6-60. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)(1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
P – 10
P – 10
MAX
M58 tsu(DRV-CKXL)
M59 th(CKXL-DRV)
M60 tsu(FXL-CKXL)
M61 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P
(1) Not production tested.
Table 6-61. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1) (2)
MASTER(3)
SLAVE
NO.
PARAMETER
UNIT
MIN
P
MAX
MIN
MAX
M53 th(CKXH-FXL)
M54 td(FXL-CKXL)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
2P
Disable time, DX high impedance following last data bit from CLKX
high
M56 tdis(CKXH-DXHZ)
M57 td(FXL-DXV)
P + 6
6
7P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) Not production tested.
(2) 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV
= 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16, that is 4.5 MHz and P = 13.3 ns.
(3) C = CLKX low pulse width = P
D = CLKX high pulse width = P
M61
M60
MSB
M54
LSB
CLKX
FSX
DX
M53
M56
M55
M57
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M58
M59
(n-2)
DR
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6-46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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6.31 Flash Timing
6.31.1 Recommended Operating Conditions(4)
MIN
NOM
MAX
UNIT
Nf
Flash endurance for the array (Write/erase cycles)
0°C to 85°C
0°C to 85°C
100
1000
cycles
Maximum One-Time Programmable (OTP) endurance for the array (Write
cycles)
NOTP
1
write
(4) Flash Timing Endurance is the minimum number of write/erase or write cycles specified over a programming temperature range of 0°C
to 85°C. Flash may be read over the operating temperature range of the device.
Table 6-62. Flash Parameters at 150-MHz SYSCLKOUT(1) (2)
PARAMETER
MIN
TYP
35
MAX
UNIT
ms
16-Bit Word
8K Sector
16K Sector
8K Sector
16K Sector
Program
Time
170
320
10
ms
ms
s
Erase Time
IDD3VFLP
11
s
Erase
75
mA
mA
mA
mA
VDD3VFL current consumption during the Erase/Program cycle
Program
35
IDDP
VDD current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
140
20
IDDIOP
(1) Typical parameters as seen at room temperature using flash API V1 including function call overhead.
(2) Not production tested.
Table 6-63. Flash/OTP Access Timing(1) (2)
PARAMETER
MIN
36
TYP
MAX UNIT
ta(fp)
Paged Flash access time
Random Flash access time
OTP access time
ns
ns
ns
ta(fr)
36
ta(OTP)
60
(1) For 150 MHz, PAGE WS = 5 and RANDOM WS = 5
For 135 MHz, PAGE WS = 4 and RANDOM WS = 4
(2) Not production tested.
Table 6-64. Minimum Required Wait-States at Different Frequencies(1)
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
PAGE WAIT-STATE(2)
RANDOM WAIT STATE(2) (3)
150
120
100
75
6.67
8.33
10
5
4
3
2
1
1
0
0
5
4
3
2
1
1
1
1
13.33
20
50
30
33.33
40
25
15
66.67
(1) Not production tested.
(2) Formulas to compute page wait state and random wait state:
(3) Random wait state must be greater than or equal to 1
Copyright © 2009–2010, Texas Instruments Incorporated
Electrical Specifications
149
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(1)
Table 6-64. Minimum Required Wait-States at Different Frequencies
(continued)
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
PAGE WAIT-STATE(2)
RANDOM WAIT STATE(2) (3)
4
250
0
1
150
Electrical Specifications
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SGUS062A–JUNE 2009–REVISED APRIL 2010
7
Mechanical Data
The following mechanical package diagram(s) reflect the most current released mechanical data available
for the designated device(s).
Copyright © 2009–2010, Texas Instruments Incorporated
Mechanical Data
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PACKAGE OPTION ADDENDUM
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28-May-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
TBD
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SM320F2812HFGS150
SM320F2812KGDS150A
ACTIVE
ACTIVE
CFP
HFG
KGD
172
0
1
AU
N / A for Pkg Type
N / A for Pkg Type
Contact TI Distributor
or Sales Office
XCEPT
36
TBD
Call TI
Contact TI Distributor
or Sales Office
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
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lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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