Texas Instruments Network Card TSB12LV26 User Manual

Data Manual

2000

Bus Solutions

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TSB12LV26

OHCI-Lynx PCI-Based IEEE 1394

Host Controller

Data Manual

Literature Number: SLLS366A

March 2000

Printed on Recycled Paper

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

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Contents

Section

Title

Page

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1

1.2

1.3

1.4

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

TSB12LV26 Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 3–6

Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

OHCI Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

3.10 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

3.11 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

3.12 Power Management Capabilities Pointer Register . . . . . . . . . . . . . . . 3–9

3.13 Interrupt Line and Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

3.14 MIN_GNT and MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

3.15 OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

3.16 Capability ID and Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . 3–11

3.17 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 3–12

3.18 Power Management Control and Status Register . . . . . . . . . . . . . . . . 3–13

3.19 Power Management Extension Register . . . . . . . . . . . . . . . . . . . . . . . . 3–13

3.20 Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

3.21 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

3.22 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

3.23 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.1

4.2

4.3

4.4

4.5

4.6

OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

GUID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . . 4–6

CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

iii

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4.7

4.8

4.9

Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

4.10 GUID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

4.11 GUID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

4.12 Configuration ROM Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4.13 Posted Write Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4.14 Posted Write Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

4.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

4.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

4.17 Self-ID Buffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

4.18 Self-ID Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

4.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . . 4–15

4.20 Isochronous Receive Channel Mask Low Register . . . . . . . . . . . . . . . 4–16

4.21 Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

4.22 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

4.23 Isochronous Transmit Interrupt Event Register . . . . . . . . . . . . . . . . . . 4–20

4.24 Isochronous Transmit Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 4–21

4.25 Isochronous Receive Interrupt Event Register . . . . . . . . . . . . . . . . . . . 4–22

4.26 Isochronous Receive Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 4–22

4.27 Fairness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

4.28 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24

4.29 Node Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25

4.30 PHY Layer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

4.31 Isochronous Cycle Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

4.32 Asynchronous Request Filter High Register . . . . . . . . . . . . . . . . . . . . . 4–28

4.33 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . 4–30

4.34 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31

4.35 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33

4.36 Physical Upper Bound Register (Optional Register) . . . . . . . . . . . . . . 4–34

4.37 Asynchronous Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . 4–35

4.38 Asynchronous Context Command Pointer Register . . . . . . . . . . . . . . 4–36

4.39 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . . 4–37

4.40 Isochronous Transmit Context Command Pointer Register . . . . . . . . 4–38

4.41 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . . 4–38

4.42 Isochronous Receive Context Command Pointer Register . . . . . . . . 4–40

4.43 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . . 4–41

GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Serial ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

7.1

7.2

7.3

7.4

Absolute Maximum Ratings Over Operating Temperature Ranges . 7–1

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2

Electrical Characteristics Over Recommended Operating Conditions 7–3

Switching Characteristics for PCI Interface . . . . . . . . . . . . . . . . . . . . . . 7–3

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7.5

Switching Characteristics for PHY-Link Interface . . . . . . . . . . . . . . . . . 7–3

Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1

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List of Illustrations

Figure

2–1

Title

Page

Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

TSB12LV26 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

GPIO2 and GPIO3 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

3–1

5–1

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List of Tables

Table

Title

Page

2–1

2–2

2–3

2–4

2–5

2–6

2–7

2–8

3–1

3–2

3–3

3–4

3–5

3–6

3–7

3–8

3–9

Signals Sorted by Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Signal Names Sorted Alphanumerically to Terminal Number . . . . . . . . . . 2–3

Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

IEEE 1394 PHY/Link Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . 3–6

Latency Timer and Class Cache Line Size Register Description . . . . . . . 3–6

Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . 3–7

OHCI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Subsystem Identification Register Description . . . . . . . . . . . . . . . . . . . . . . 3–8

3–10 Interrupt Line and Pin Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

3–11 MIN_GNT and MAX_LAT Register Description . . . . . . . . . . . . . . . . . . . . . 3–10

3–12 OHCI Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

3–13 Capability ID and Next Item Pointer Register Description . . . . . . . . . . . . . 3–11

3–14 Power Management Capabilities Register Description . . . . . . . . . . . . . . . 3–12

3–15 Power Management Control and Status Register Description . . . . . . . . . 3–13

3–16 Power Management Extension Register Description . . . . . . . . . . . . . . . . . 3–13

3–17 Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

3–18 Link Enhancement Control Register Description . . . . . . . . . . . . . . . . . . . . 3–15

3–19 Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

3–20 GPIO Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

4–1

4–2

4–3

4–4

4–5

4–6

4–7

4–8

4–9

OHCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

OHCI Version Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

GUID ROM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Asynchronous Transmit Retries Register Description . . . . . . . . . . . . . . . . 4–6

CSR Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

Configuration ROM Header Register Description . . . . . . . . . . . . . . . . . . . . 4–8

Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . . 4–11

Posted Write Address High Register Description . . . . . . . . . . . . . . . . . . . . 4–12

vii

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4–10 Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . 4–13

4–11 Self-ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

4–12 Isochronous Receive Channel Mask High Register Description . . . . . . . 4–15

4–13 Isochronous Receive Channel Mask Low Register Description . . . . . . . . 4–16

4–14 Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

4–15 Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

4–16 Isochronous Transmit Interrupt Event Register Description . . . . . . . . . . . 4–20

4–17 Isochronous Receive Interrupt Event Register Description . . . . . . . . . . . 4–22

4–18 Fairness Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

4–19 Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24

4–20 Node Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25

4–21 PHY Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

4–22 Isochronous Cycle Timer Register Description . . . . . . . . . . . . . . . . . . . . . . 4–27

4–23 Asynchronous Request Filter High Register Description . . . . . . . . . . . . . 4–28

4–24 Asynchronous Request Filter Low Register Description . . . . . . . . . . . . . . 4–30

4–25 Physical Request Filter High Register Description . . . . . . . . . . . . . . . . . . . 4–31

4–26 Physical Request Filter Low Register Description . . . . . . . . . . . . . . . . . . . 4–33

4–27 Asynchronous Context Control Register Description . . . . . . . . . . . . . . . . . 4–35

4–28 Asynchronous Context Command Pointer Register Description . . . . . . . 4–36

4–29 Isochronous Transmit Context Control Register Description . . . . . . . . . . 4–37

4–30 Isochronous Receive Context Control Register Description . . . . . . . . . . . 4–38

4–31 Isochronous Receive Context Match Register Description . . . . . . . . . . . . 4–41

6–1

6–2

Registers and Bits Loadable through Serial ROM . . . . . . . . . . . . . . . . . . . 6–1

Serial ROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

viii

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1 Introduction

1.1 Description

The Texas Instruments TSB12LV26 is a PCI-to-1394 host controller compatible with the latest PCI Local Bus, PCI

Bus Power Management Interface, IEEE 1394-1995, and 1394 Open Host Controller Interface Specification. The

chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s,

and 400 Mbits/s.

As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE proposal 1394a specification,

internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed

through configuration cycles specified by PCI, and provides Plug-and-Play (PnP) compatibility. Furthermore, the

TSB12LV26 is compliant with the PCI Bus Power Management Interface Specification, per the PC 99 Design Guide

requirements. TSB12LV26 supports the D0, D2, and D3 power states.

The TSB12LV26 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at

132 Mbytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided

to buffer 1394 data.

TheTSB12LV26providesphysicalwritepostingbuffersandahighlytunedphysicaldatapathforSBP-2performance.

The TSB12LV26 also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal

arbitration, and bus holding buffers on the PHY/link interface.

An advanced CMOS process is used to achieve low power consumption while operating at PCI clock rates up to

33 MHz.

1.2 Features

The TSB12LV26 supports the following features:

•

3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

Serial bus data rates of 100, 200, and 400 Mbits/s

Provides bus-hold buffers on physical interface for low-cost single capacitor isolation

Physical write posting of up to three outstanding transactions

Serial ROM interface supports 2-wire devices

External cycle timer control for customized synchronization

Implements PCI burst transfers and deep FIFOs to tolerate large host latency

Provides two general-purpose I/Os

Fabricated in advanced low-power CMOS process

Packaged in 100-terminal LQFP (PZ)

Supports PCI_CLKRUN protocol

1–1

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1.3 Related Documents

•

1394 Open Host Controller Interface Specification 1.0

P1394 Standard for a High Performance Serial Bus (IEEE 1394-1995)

P1394a Draft Standard for a High Performance Serial Bus (Supplement)

PC 99 Design Guide

PCI Bus Power Management Interface Specification (Revision 1.0)

PCI Local Bus Specification (Revision 2.2)

Serial Bus Protocol 2 (SBP–2)

1.4 Ordering Information

ORDERING NUMBER

NAME

OHCI-Lynx PCI-Based IEEE 1394 Host Controller

VOLTAGE

PACKAGE

TSB12LV26

3.3V-, 5V-Tolerant I/Os

100-Terminal LQFP

1–2

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2 Terminal Descriptions

This section provides the terminal descriptions for the TSB12LV26. Figure 2–1 shows the signal assigned to each

terminal in the package. Table 2–1 is a listing of signal names arranged in terminal number order, and Table 2–2 lists

terminals in alphanumeric order by signal names.

PZ PACKAGE

(TOP VIEW)

GND

GPIO2

GPIO3

SCL

GND

PCI_AD0

PCI_AD1

PCI_AD2

SDA

PCI_AD3

3.3 V

CCP

PCI_CLKRUN

PCI_INTA

PCI_AD4

PCI_AD5

PCI_AD6

PCI_AD7

PCI_C/BE0

PCI_AD8

3.3 V

G_RST

GND

PCI_CLK

3.3 V

CCP

PCI_GNT

PCI_REQ

PCI_AD9

PCI_AD10

GND

PCI_AD11

PCI_AD12

PCI_AD13

PCI_AD14

CCP

PCI_PME

PCI_AD31

PCI_AD30

3.3 V

PCI_AD29

3.3 V

PCI_AD28

PCI_AD27

GND

PCI_AD15

PCI_C/BE1

PCI_PAR

PCI_AD26

PCI_SERR

Figure 2–1. Terminal Assignments

2–1

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Table 2–1. Signals Sorted by Terminal Number

NO.

TERMINAL NAME

NO.

TERMINAL NAME

PCI_AD25

PCI_AD24

PCI_C/BE3

PCI_IDSEL

GND

NO.

TERMINAL NAME

PCI_SERR

PCI_PAR

NO.

100

TERMINAL NAME

PCI_RST

GND

GPIO2

GPIO3

SCL

CYCLEOUT

CYCLEIN

PCI_C/BE1

PCI_AD15

REG_EN

SDA

3.3 V

CCP

PCI_AD23

PCI_AD22

PCI_AD21

PCI_AD20

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

GND

PHY_DATA7

PHY_DATA6

GND

PCI_CLKRUN

PCI_INTA

3.3 V

PHY_DATA5

PHY_DATA4

PHY_DATA3

G_RST

GND

3.3 V

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD10

PCI_AD9

PCI_CLK

CCP

3.3 V

CCP

PHY_DATA2

PHY_DATA1

PHY_DATA0

PCI_GNT

PCI_REQ

CCP

PCI_AD8

PCI_C/BE0

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD16

PCI_C/BE2

REG18

CCP

3.3 V

PCI_PME

PCI_AD31

PCI_AD30

PHY_CTL1

PHY_CTL0

GND

PCI_FRAME

PCI_IRDY

PCI_TRDY

3.3 V

PHY_SCLK

PCI_AD29

PCI_AD28

PCI_AD27

GND

3.3 V

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD0

GND

3.3 V

PCI_DEVSEL

PCI_STOP

PCI_PERR

GND

PHY_LREQ

PHY_LINKON

PHY_LPS

PCI_AD26

REG18

2–2

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Table 2–2. Signal Names Sorted Alphanumerically to Terminal Number

TERMINAL NAME

CYCLEIN

CYCLEOUT

GND

NO.

TERMINAL NAME

PCI_AD11

PCI_AD12

PCI_AD13

PCI_AD14

PCI_AD15

PCI_AD16

PCI_AD17

PCI_AD18

PCI_AD19

PCI_AD20

PCI_AD21

PCI_AD22

PCI_AD23

PCI_AD24

PCI_AD25

PCI_AD26

PCI_AD27

PCI_AD28

PCI_AD29

PCI_AD30

PCI_AD31

PCI_C/BE0

PCI_C/BE1

PCI_C/BE2

PCI_C/BE3

NO.

TERMINAL NAME

PCI_CLK

NO.

TERMINAL NAME

PHY_DATA7

PHY_LINKON

PHY_LPS

PHY_LREQ

PHY_SCLK

REG_EN

NO.

100

PCI_CLKRUN

PCI_DEVSEL

PCI_FRAME

PCI_GNT

GND

PCI_IDSEL

PCI_INTA

GND

REG18

GND

PCI_IRDY

REG18

GND

PCI_PAR

SCL

GND

PCI_PERR

PCI_PME

SDA

GND

CCP

GPIO2

PCI_REQ

GPIO3

PCI_RST

G_RST

PCI_AD0

PCI_AD1

PCI_AD2

PCI_AD3

PCI_AD4

PCI_AD5

PCI_AD6

PCI_AD7

PCI_AD8

PCI_AD9

PCI_AD10

PCI_SERR

PCI_STOP

PCI_TRDY

PHY_CTL0

PHY_CTL1

PHY_DATA0

PHY_DATA1

PHY_DATA2

PHY_DATA3

PHY_DATA4

PHY_DATA5

PHY_DATA6

3.3 V

The terminals in Table 2–3 through Table 2–8 are grouped in tables by functionality, such as PCI system function

and power supply function. The terminal numbers are also listed for convenient reference.

Table 2–3. Power Supply Terminals

TERMINAL

I/O

DESCRIPTION

NAME

NO.

1, 11, 24, 30,

50, 60, 75, 83,

GND

Device ground terminals

6, 16, 39, 63,

CCP

PCI signaling clamp voltage power input. PCI signals are clamped per the PCI Local Bus Specification.

3.3-V power supply terminals

9, 13, 20, 35,

46, 55, 70, 80,

91, 96

3.3 V

2–3

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Table 2–4. PCI System Terminals

TERMINAL

NAME

I/O

DESCRIPTION

NO.

Global power reset. This reset brings all of the TSB12LV26 internal registers to their default states, including

those registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonfunctional.

When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets

to the TSB12LV26. G_RST should be a one-time power-on reset, and PCI_RST should be connected to the

PCI bus RST. If wake capabilities are not required, G_RST may be connected to the PCI bus RST (see

PCI_RST, terminal 76).

G_RST

PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at rising edge

of PCI_CLK.

PCI_CLK

PCI_INTA

Interruptsignal. This output indicates interrupts from the TSB12LV26 to the host. This terminal is implemented

as open-drain.

PCI reset. When this bus reset is asserted, the TSB12LV26 places all output buffers in a high impedance state

and resets all internal registers except device power management context- and vendor-specific bits initialized

by host power-on software. When PCI_RST is asserted, the device is completely nonfunctional.

If this terminal is implemented, then it should be connected to the PCI bus RST signal. Otherwise, it should

PCI_RST

be pulled high to link V

10).

through a 4.7-kΩ resistor, or strapped to the G_RST terminal (see G_RST, terminal

2–4

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Table 2–5. PCI Address and Data Terminals

TERMINAL

I/O

DESCRIPTION

NAME

NO.

PCI_AD31

PCI_AD30

PCI_AD29

PCI_AD28

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

PCI_AD22

PCI_AD21

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD0

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface.

During the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other destination information.

During the data phase, AD31–AD0 contain data.

I/O

2–5

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Table 2–6. PCI Interface Control Terminals

TERMINAL

NAME

I/O

DESCRIPTION

NO.

PCI_C/BE0

PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI

I/O terminals. During the address phase of a bus cycle PCI_C/BE3–PCI_C/BE0 defines the bus command. During

the data phase, this 4-bit bus is used as byte enables.

PCI_C/BE1

PCI_C/BE2

PCI_C/BE3

Clock run. This terminal provides clock control through the PCI_CLKRUN protocol. An internal pulldown

I/O resistor is implemented on this terminal.

PCI_CLKRUN

PCI_DEVSEL

PCI_FRAME

This terminal is implemented as open-drain.

PCI device select. The TSB12LV26 asserts this signal to claim a PCI cycle as the target device. As a PCI

I/O initiator, the TSB12LV26 monitors this signal until a target responds. If no target responds before time-out

occurs, then the TSB12LV26 terminates the cycle with an initiator abort.

PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to indicate

I/O thatabustransactionisbeginning, anddatatransferscontinuewhilethissignalisasserted. WhenPCI_FRAME

is deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB12LV26 access to the PCI bus after

PCI_GNT

PCI_IDSEL

PCI_IRDY

the current data transaction has completed. This signal may or may not follow a PCI bus request, depending

upon the PCI bus parking algorithm.

Initializationdevice select. IDSEL selects the TSB12LV26 during configuration space accesses. IDSEL can be

connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the

I/O transaction. A data phase is completed upon a rising edge of PCLK where both PCI_IRDY and PCI_TRDY are

asserted.

PCI parity. In all PCI bus read and write cycles, the TSB12LV26 calculates even parity across the AD and C/BE

buses. As an initiator during PCI cycles, the TSB12LV26 outputs this parity indicator with a one PCI_CLK delay.

As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare

PCI_PAR

I/O

can result in a parity error assertion (PCI_PERR).

PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match

PCI_PAR when PERR_ENB (bit 6) is set in the PCI command register (offset 04h, see Section 3.4).

PCI_PERR

PCI_PME

PCI_REQ

I/O

Power management event. This terminal indicates wake events to the host.

PCI bus request. Asserted by the TSB12LV26 to request access to the bus as an initiator. The host arbiter

asserts the PCI_GNT signal when the TSB12LV26 has been granted access to the bus.

PCI system error. When SERR_ENB (bit 8) in the PCI command register (offset 04h, see Section 3.4) is set

the output is pulsed, indicating an address parity error has occurred. The TSB12LV26 needs not be the target

of the PCI cycle to assert this signal.

PCI_SERR

This terminal is implemented as open-drain.

PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus

PCI_STOP

PCI_TRDY

I/O transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do

not support burst data transfers.

PCI target ready. PCI_TRDY indicates the ability of the PCI bus targer to complete the current data phase of

I/O the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and

PCI_TRDY are asserted.

2–6

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Table 2–7. IEEE 1394 PHY/Link Terminals

DESCRIPTION

TERMINAL

NAME

I/O

NO.

PHY-link interface control. These bidirectional signals control passage of information between the two devices.

I/O The TSB12LV26 can only drive these terminals after the PHY has granted permission following a link request

(PHY_LREQ).

PHY_CTL1

PHY_CTL0

PHY_DATA7

PHY_DATA6

PHY_DATA5

PHY_DATA4

PHY_DATA3

PHY_DATA2

PHY_DATA1

PHY_DATA0

PHY-link interface data. These bidirectional signals pass data between the TSB12LV26 and the PHY device.

These terminals are driven by the TSB12LV26 on transmissions and are driven by the PHY on reception. Only

PHY_DATA1–PHY_DATA0 are valid for 100-Mbit speeds, PHY_DATA3–PHY_DATA0 are valid for 200-Mbit

speeds, and PHY_DATA7–PHY_DATA0 are valid for 400-Mbit speeds.

I/O

LinkOn wake indication. The PHY_LINKON signal is pulsed by the PHY to activate the link, and 3.3-V signaling

is required.

PHY_LINKON

I/O

When connected to the TSB41LV0X C/LKON terminal, a 1-kΩ series resistor is required between the link and

PHY.

Link power status. The PHY_LPS signal is asserted when the link is powered on, and 3.3-V signaling is

required.

PHY_LPS

I/O

PHY_LREQ

PHY_SCLK

Link request. This signal is driven by the TSB12LV26 to initiate a request for the PHY to perform some service.

System clock. This input from the PHY provides a 49.152-MHz clock signal for data synchronization.

Table 2–8. Miscellaneous Terminals

TERMINAL

NAME

I/O

DESCRIPTION

NO.

CYCLEOUT

I/O This terminal provides an 8-kHz cycle timer synchronization signal.

TheCYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization with other

system devices.

CYCLEIN

GPIO2

I/O

If this terminal is not implemented, then it should be pulled high to the link V

through a 4.7-kΩ resistor.

General-purpose I/O [2]. This terminal defaults as an input and if it is not implemented, then it is recommended

that it be pulled low to ground with a 220-Ω resistor.

General-purpose I/O [3]. This terminal defaults as an input and if it is not implemented, then it is recommended

that it be pulled low to ground with a 220-Ω resistor.

GPIO3

I/O

REG_EN

REG18

Regulator enable. This terminal is pulled low to ground through a 220-Ω resistor.

100

The REG18 terminals are connected to a 0.01 µF capacitor which, in turn, is connected to ground. The

capacitor provides a local bypass for the internal core voltage.

Serial clock. The TSB12LV26 determines whether a two-wire serial ROM is implemented at reset. If a two-wire

serial ROM is implemented, then this terminal provides the SCL serial clock signaling.

SCL

SDA

I/O

This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design),

this terminal should be pulled high to the ROM V

to ground with a 220-Ω resistor.

with a 2.7-kΩ resistor. Otherwise, it should be pulled low

Serial data. The TSB12LV26 determines whether a two-wire serial ROM is implemented at reset. If a two-wire

serial ROM is detected, then this terminal provides the SDA serial data signaling. This terminal must be wired

low to indicate no serial ROM is present.

This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design),

this terminal should be pulled high to the ROM V

to ground with a 220-Ω resistor.

with a 2.7-kΩ resistor. Otherwise, it should be pulled low

2–7

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2–8

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3 TSB12LV26 Controller Programming Model

This section describes the internal registers used to program the TSB12LV26. All registers are detailed in the same

format: a brief description for each register, followed by the register offset and a bit table describing the reset state

for each register.

A bit description table, typically included when the register contains bits of more than one type or purpose, indicates

bit field names, field access tags which appear in the type column,and a detailed field description. Table 3–1

describes the field access tags.

Table 3–1. Bit Field Access Tag Descriptions

ACCESS TAG

NAME

Read

Write

Set

MEANING

Field may be read by software.

Field may be written by software to any value.

Field may be set by a write of 1. Writes of 0 have no effect.

Field may be cleared by a write of 1. Writes of 0 have no effect.

Field may be autonomously updated by the TSB12LV26.

Clear

Update

A simplified block diagram of the TSB12LV26 is provided in Figure 3–1.

3–1

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Serial

ROM

PCI

Target

Internal

Registers

OHCI PCI Power

Mgmt & CLKRUN

GPIOs

MISC

Interface

ISO Transmit

Contexts

Transmit

FIFO

Async Transmit

Contexts

Physical DMA

& Response

Link

Transmit

Resp

Timeout

Receive

Acknowledge

PCI

Host

Bus

Central

Arbiter

PCI

Initiator

PHY

Cycle Start

Generator &

Cycle Monitor

Interface

Access

& Status

Monitor

CRC

PHY /

Link

Interface

Synthesized

Bus Reset

Request

Filters

Link

General

Receive

Request Receive

Receive

FIFO

Async Response

Receive

ISO Receive

Contexts

Figure 3–1. TSB12LV26 Block Diagram

3–2

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3.1 PCI Configuration Registers

The TSB12LV26 is a single-function PCI device. The configuration header is compliant with the PCI Local Bus

Specification as a standard header. Table 3–2 illustrates the PCI configuration header that includes both the

predefined portion of the configuration space and the user definable registers.

Table 3–2. PCI Configuration Register Map

OFFSET

00h

Device ID

Status

Vendor ID

Command

04h

Class code

Header type

OHCI registers base address

Revision ID

08h

BIST

Latency timer

Cache line size

0Ch

10h

TI extension registers base address

14h

Reserved

18h

1Ch

20h

24h

28h

Subsystem ID

Subsystem vendor ID

2Ch

30h

Reserved

PCI power

management

capabilities pointer

Reserved

34h

38h

3Ch

Maximum latency

Minimum grant

Interrupt pin

Interrupt line

Capability ID

PCI OHCI control register

40h

Power management capabilities

PM data PMCSR_BSE

Reserved

Next item pointer

44h

Power management CSR

48h

4Ch–ECh

F0h

PCI miscellaneous configuration register

Link_Enhancements register

F4h

Subsystem ID alias

Subsystem vendor ID alias

Reserved

F8h

GPIO3

GPIO2

FCh

3.2 Vendor ID Register

The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.

The vendor ID assigned to Texas Instruments is 104Ch.

Bit

Name

Type

Default

Vendor ID

Type:

Offset:

Default:

Vendor ID

Read-only

00h

104Ch

3–3

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3.3 Device ID Register

The device ID register contains a value assigned to the TSB12LV26 by Texas Instruments. The device identification

for the TSB12LV26 is 8020h.

Bit

Name

Type

Default

Device ID

Type:

Offset:

Default:

Device ID

Read-only

02h

8020h

3.4 Command Register

The command register provides control over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the

definitions in the PCI Local Bus Specification, as seen in the bit descriptions of Table 3–3.

Bit

Name

Type

Default

Command

R/W

Type:

Command

Read/Write, Read-only

Offset:

Default:

04h

0000h

Table 3–3. Command Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15–10 RSVD

Reserved. Bits 15–10 return 0s when read.

Fast back-to-back enable. The TSB12LV26 does not generate fast back-to-back transactions, thus

this bit returns 0 when read.

FBB_ENB

R/W

PCI_SERR enable. When this bit is set, the TSB12LV26 PCI_SERR driver is enabled. PCI_SERR can

be asserted after detecting an address parity error on the PCI bus.

SERR_ENB

STEP_ENB

PERR_ENB

VGA_ENB

Address/data stepping control. The TSB12LV26 does not support address/data stepping, thus this bit

is hardwired to 0.

Parity error enable. When this bit is set, the TSB12LV26 is enabled to drive PCI_PERR response to

parity errors through the PCI_PERR signal.

R/W

VGA palette snoop enable. The TSB12LV26 does not feature VGA palette snooping. This bit returns 0

when read.

Memory write and invalidate enable. When this bit is set, the TSB12LV26 is enabled to generate MWI

PCI bus commands. If this bit is cleared, then the TSB12LV26 generates memory write commands

instead.

MWI_ENB

R/W

Specialcycle enable. The TSB12LV26function does not respond to special cycle transactions. This bit

returns 0 when read.

SPECIAL

MASTER_ENB

MEMORY_ENB

R/W

Bus master enable. When this bit is set, the TSB12LV26 is enabled to initiate cycles on the PCI bus.

Memoryresponse enable. Setting this bit enables the TSB12LV26 to respond to memory cycles on the

PCI bus. This bit must be set to access OHCI registers.

I/O space enable. The TSB12LV26 does not implement any I/O mapped functionality; thus, this bit re-

turns 0 when read.

IO_ENB

3–4

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3.5 Status Register

The status register provides status over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the

definitions in the PCI Local Bus Specification. See Table 3–4 for a complete description of the register contents.

Bit

Name

Type

Default

Status

RCU RCU RCU RCU RCU

RCU

Type:

Status

Read/Clear/Update, Read-only

Offset:

Default:

06h

0210h

Table 3–4. Status Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

PAR_ERR

RCU

Detected parity error. This bit is set when a parity error is detected, either address or data parity errors.

Signaled system error. This bit is set when PCI_SERR is enabled and the TSB12LV26 has signaled a

system error to the host.

SYS_ERR

RCU

Receivedmasterabort.ThisbitissetwhenacycleinitiatedbytheTSB12LV26onthePCIbushasbeen

terminated by a master abort.

MABORT

Received target abort. This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus was

terminated by a target abort.

TABORT_REC

TABORT_SIG

PCI_SPEED

Signaledtarget abort. This bit is set by the TSB12LV26 when it terminates a transaction on the PCI bus

with a target abort.

DEVSEL timing. Bits 10–9 encode the timing of PCI_DEVSEL and are hardwired to 01b indicating that

the TSB12LV26 asserts this signal at a medium speed on nonconfiguration cycle accesses.

10–9

Data parity error detected. This bit is set when the following conditions have been met:

a. PCI_PERR was asserted by any PCI device including the TSB12LV26.

b. The TSB12LV26 was the bus master during the data parity error.

DATAPAR

RCU

c. The parity error response bit is set in the PCI command register (offset 04h, see Section 3.4).

Fast back-to-back capable. The TSB12LV26 cannot accept fast back-to-back transactions; thus, this

bit is hardwired to 0.

FBB_CAP

UDF

User definable features (UDF) supported. The TSB12LV26 does not support the UDF; thus, this bit is

hardwired to 0.

66-MHz capable. The TSB12LV26 operates at a maximum PCI_CLK frequency of 33 MHz; therefore,

this bit is hardwired to 0.

66MHZ

Capabilitieslist. This bit returns 1 when read, indicating that capabilities additional to standard PCI are

implemented. The linked list of PCI power management capabilities is implemented in this function.

CAPLIST

RSVD

3–0

Reserved. Bits 3–0 return 0s when read.

3–5

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3.6 Class Code and Revision ID Register

The class code and revision ID register categorizes the TSB12LV26 as a serial bus controller (0Ch), controlling an

IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the

least significant byte. See Table 3–5 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Class code and revision ID

Name

Type

Default

Class code and revision ID

Type:

Offset:

Default:

Class code and revision ID

Read-only

08h

0C00 1000h

Table 3–5. Class Code and Revision ID Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus

controller.

31–24 BASECLASS

23–16 SUBCLASS

Subclass. This field returns 00h when read, which specifically classifies the function as controlling an

IEEE 1394 serial bus.

Programming interface. This field returns 10h when read, indicating that the programming model is

compliant with the 1394 Open Host Controller Interface Specification.

15–8

7–0

PGMIF

CHIPREV

Silicon revision. This field returns 00h when read, indicating the silicon revision of the TSB12LV26.

3.7 Latency Timer and Class Cache Line Size Register

The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size

and the latency timer associated with the TSB12LV26. See Table 3–6 for a complete description of the register

contents.

Bit

Name

Type

Default

Latency timer and class cache line size

R/W

Type:

Offset:

Default:

Latency timer and class cache line size

Read/Write,

0Ch

0000h

Table 3–6. Latency Timer and Class Cache Line Size Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

PCI latency timer. The value in this register specifies the latency timer for the TSB12LV26, in units of

PCI clock cycles. When the TSB12LV26 is a PCI bus initiator and asserts PCI_FRAME, the latency

timer begins counting from zero. If the latency timer expires before the TSB12LV26 transaction has

terminated, then the TSB12LV26 terminates the transaction when its PCI_GNT is deasserted.

15–8

LATENCY_TIMER

R/W

Cache line size. This value is used by the TSB12LV26 during memory write and invalidate, memory

read line, and memory read multiple transactions.

7–0

CACHELINE_SZ

R/W

3–6

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3.8 Header Type and BIST Register

The header type and BIST register indicates the TSB12LV26 PCI header type, and indicates no built-in self test. See

Table 3–7 for a complete description of the register contents.

Bit

Name

Type

Default

Header type and BIST

Type:

Offset:

Default:

Header type and BIST

Read-only

0Eh

0000h

Table 3–7. Header Type and BIST Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Built-in self test. The TSB12LV26 does not include a built-in self test; thus, this field returns 00h when

read.

15–8

BIST

HEADER_TYPE

PCI header type. The TSB12LV26 includes the standard PCI header, and this is communicated by

returning 00h when this field is read.

7–0

3.9 OHCI Base Address Register

The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control.

When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of

memory address space are required for the OHCI registers. See Table 3–8 for a complete description of the register

contents.

Bit

Name

Type

Default

Bit

OHCI base address

R/W

Name

Type

Default

OHCI address

R/W

Type:

Offset:

Default:

OHCI base address

Read/Write, Read-only

10h

0000 0000h

Table 3–8. OHCI Base Address Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

OHCI register pointer. Specifies the upper 21 bits of the 32-bit OHCI base address register.

31–11

OHCIREG_PTR

R/W

OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a

2-Kbyte region of memory.

10–4

OHCI_SZ

OHCI_PF

OHCI register prefetch. This bit returns 0 when read, indicating that the OHCI registers are

nonprefetchable.

OHCImemorytype. Thisfieldreturns0swhenread, indicatingthattheOHCIbaseaddressregisteris

32 bits wide and mapping can be done anywhere in the 32-bit memory space.

2–1

OHCI_MEMTYPE

OHCI_MEM

OHCI memory indicator. This bit returns 0 when read, indicating that the OHCI registers are mapped

into system memory space.

3–7

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3.10 TI Extension Base Address Register

The TI extension base address register is programmed with a base address referencing the memory-mapped TI

extension registers. See the OHCI Base Address Register, Section 3.9, for bit field details.

Bit

Name

Type

Default

Bit

TI extension base address

R/W

Name

Type

Default

TI extension base address

R/W

Type:

Offset:

Default:

TI extension base address

Read/Write, Read-only

14h

0000 0000h

3.11 Subsystem Identification Register

The subsystem identification register is used for system and option card identification purposes. This register can

be initialized from the serial ROM or programmed via the subsystem ID and subsystem vendor ID alias registers at

offset F8h. See Table 3–9 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Subsystem identification

Name

Type

Default

Subsystem identification

Type:

Offset:

Default:

Subsystem identification

Read/Update

2Ch

0000 0000h

Table 3–9. Subsystem Identification Register Description

BIT

31–16

15–0

FIELD NAME

TYPE

DESCRIPTION

OHCI_SSID

Subsystem device ID. This field indicates the subsystem device ID.

Subsystem vendor ID. This field indicates the subsystem vendor ID.

OHCI_SSVID

3–8

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3.12 Power Management Capabilities Pointer Register

The power management capabilities pointer register provides a pointer into the PCI configuration header where the

PCI power management register block resides. The TSB12LV26 configuration header double-words at offsets 44h

and 48h provide the power management registers. This register is read-only and returns 44h when read.

Bit

Name

Type

Default

Power management capabilities pointer

Type:

Offset:

Default:

Power management capabilities pointer

Read-only

34h

44h

3.13 Interrupt Line and Pin Register

The interrupt line and pin register is used to communicate interrupt line routing information. See Table 3–10 for a

complete description of the register contents.

Bit

Name

Type

Default

Interrupt line and pin

R/W

Type:

Offset:

Default:

Interrupt line and pin

Read/Write, Read-only

3Ch

0100h

Table 3–10. Interrupt Line and Pin Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Interruptpin. Returns 01h when read, indicating that the TSB12LV26 PCI function signals interrupts on

the PCI_INTA pin.

15–8

INTR_PIN

Interrupt line. This field is programmed by the system and indicates to software which interrupt line the

TSB12LV26 PCI_INTA is connected to.

7–0

INTR_LINE

R/W

3–9

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3.14 MIN_GNT and MAX_LAT Register

The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of bits 15–8 of the

latency timer and class cache line size register (offset 0Ch, see Section 3.7). If a serial ROM is detected, then the

contents of this register are loaded through the serial ROM interface after a PCI reset. If no serial ROM is detected,

then this register returns a default value that corresponds to the MIN_GNT = 2, MAX_LAT = 4. See Table 3–11 for

a complete description of the register contents.

Bit

Name

Type

Default

MIN_GNT and MAX_LAT

Type:

Offset:

Default:

MIN_GNT and MAX_LAT

Read/Update

3Eh

0402h

Table 3–11. MIN_GNT and MAX_LAT Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Maximum latency. The contents of this register may be used by host BIOS to assign an arbitration

priority-level to the TSB12LV26. The default for this register indicates that the TSB12LV26 may need to

access the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The

contents of this field may also be loaded through the serial ROM.

15–8

MAX_LAT

Minimum grant. The contents of this register may be used by host BIOS to assign a latency timer and class

cache line size register (offset 0Ch, see Section 3.7) value to the TSB12LV26. The default for this register

indicates that the TSB12LV26 may need to sustain burst transfers for nearly 64 µs; thus, requesting a large

value be programmed in bits 15–8 of the TSB12LV26 latency timer and class cache line size register.

7–0

MIN_GNT

3.15 OHCI Control Register

The OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for

big endian PCI support. See Table 3–12 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

OHCI control

Name

Type

Default

OHCI control

R/W

Type:

Offset:

Default:

OHCI control

Read/Write

40h

0000 0000h

Table 3–12. OHCI Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–1

RSVD

Reserved. Bits 31–1 return 0s when read.

When this bit is set, all quadlets read from and written to the PCI interface are byte swapped (big

endian). This bit is loaded from ROM and should be programmed to 0 for normal operation.

GLOBAL_SWAP

R/W

3–10

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3.16 Capability ID and Next Item Pointer Register

The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the

next capability item. See Table 3–13 for a complete description of the register contents.

Bit

Name

Type

Default

Capability ID and next item pointer

Type:

Offset:

Default:

Capability ID and next item pointer

Read-only

44h

0001h

Table 3–13. Capability ID and Next Item Pointer Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Next item pointer. The TSB12LV26 supports only one additional capability that is communicated to

the system through the extended capabilities list; thus, this field returns 00h when read.

15–8

NEXT_ITEM

Capabilityidentification. This field returns 01h when read, which is the unique ID assigned by the PCI

SIG for PCI power management capability.

7–0

CAPABILITY_ID

3–11

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3.17 Power Management Capabilities Register

The power management capabilities register indicates the capabilities of the TSB12LV26 related to PCI power

management. See Table 3–14 for a complete description of the register contents.

Bit

Name

Type

Default

Power management capabilities

Type:

Power management capabilities

Read/Update, Read-only

Offset:

Default:

46h

6401h

Table 3–14. Power Management Capabilities Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

PCI_PMEsupportfromD3

from D3

configured by host software using bit 15 (PME_D3COLD) in the PCI miscellaneous configuration

.Whenthisbitisset,theTSB12LV26generatesaPCI_PMEwakeevent

cold

. This bit state is dependent upon the TSB12LV26 V

implementation and may be

cold AUX

PME_D3COLD

PCI_PME support. This 4-bit field indicates the power states from which the TSB12LV26 may assert

PCI_PME. This field returns a value of 1100b by default, indicating that PCI_PME may be asserted

14–11

PME_SUPPORT

from the D3

and D2 power states. Bit 13 may be modified by host software using bit 13

hot

(PME_SUPPORT_D2) in the PCI miscellaneous configuration register (offset F0h, see Section 3.20).

D2 support. This bit can be set or cleared via bit 10 (D2_SUPPORT) in the PCI miscellaneous

configuration register (see Section 3.20). The PCI miscellaneous configuration register is loaded from

ROM. When this bit is set, it indicates that D2 support is present. When this bit is cleared, it indicates

that D2 support is not present for backward compatibility with the TSB12LV22. For normal operation,

this bit is set to 1.

D2_SUPPORT

D1_SUPPORT

D1 support. This bit returns a 0 when read, indicating that the TSB12LV26 does not support the D1

power state.

Dynamic data support. This bit returns a 0 when read, indicating that the TSB12LV26 does not report

dynamic power consumption data.

DYN_DATA

RSVD

7–6

Reserved. Bits 7–6 return 0s when read.

Device specific initialization. This bit returns 0 when read, indicating that the TSB12LV26 does not

require special initialization beyond the standard PCI configuration header before a generic class

driver is able to use it.

DSI

Auxiliary power source. Since the TSB12LV26 does not support PCI_PME generation in the D3

device state, this bit returns 0 when read.

cold

AUX_PWR

PME_CLK

PME clock. This bit returns 0 when read, indicating that no host bus clock is required for the

TSB12LV26 to generate PCI_PME.

Power management version. This field returns 001b when read, indicating that the TSB12LV26 is

compatible with the registers described in the PCI Bus Power Management Interface Specification

Rev. 1.0.

2–0

PM_VERSION

3–12

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3.18 Power Management Control and Status Register

The power management control and status register implements the control and status of the PCI power management

function. This register is not affected by the internally generated reset caused by the transition from the D3 to D0

hot

state. See Table 3–15 for a complete description of the register contents.

Bit

Name

Type

Default

Power management control and status

R/W

Type:

Power management control and status

Read/Clear, Read/Write, Read-only

Offset:

Default:

48h

0000h

Table 3–15. Power Management Control and Status Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

This bit is set when the TSB12LV26 would normally be asserting the PME signal, independent of the

state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, and this also clears the PCI_PME

signal driven by the TSB12LV26. Writing a 0 to this bit has no effect.

PME_STS

Dynamic data control. This field returns 0s when read since the TSB12LV26 does not report dynamic

data.

14–9

DYN_CTRL

PME_ENB

PCI_PME enable. This bit enables the function to assert PCI_PME. If this bit is cleared, then assertion

of PCI_PME is disabled.

R/W

7–5

RSVD

DYN_DATA

RSVD

Reserved. Bits 7–5 return 0s when read.

Dynamic data. This bit returns 0 when read since the TSB12LV26 does not report dynamic data.

Reserved. Bits 3–2 return 0s when read.

3–2

Power state. This 2-bit field is used to set the TSB12LV26 device power state and is encoded as

follows:

00 = Current power state is D0

01 = Current power state is D1

10 = Current power state is D2

11 = Current power state is D3

1–0

PWR_STATE

R/W

3.19 Power Management Extension Register

The power management extension register provides extended power management features not applicable to the

TSB12LV26, thus it is read-only and returns 0s when read. See Table 3–16 for a complete description of the register

contents.

Bit

Name

Type

Default

Power management extension

Type:

Offset:

Default:

Power management extension

Read-only

4Ah

0000h

Table 3–16. Power Management Extension Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Power management data. This field returns 00h when read since the TSB12LV26 does not report

dynamic data.

15–8

PM_DATA

Power management CSR – bridge support extensions. This field returns 00h when read since the

TSB12LV26 does not provide P2P bridging.

7–0

PMCSR_BSE

3–13

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3.20 Miscellaneous Configuration Register

The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3–17 for a

complete description of the register contents.

Bit

Name

Type

Default

Bit

Miscellaneous configuration

Name

Type

Default

Miscellaneous configuration

R/W

Type:

Offset:

Default:

Miscellaneous configuration

Read/Write, Read-only

F0h

0000 2400h

Table 3–17. Miscellaneous Configuration Register

BIT

FIELD NAME

TYPE

DESCRIPTION

Reserved. Bits 31–16 return 0s when read.

PCI_PME support from D3 . This bit is used to program bit 15 (PME_D3COLD) in the power

31–16

RSVD

PME_D3COLD

RSVD

cold

R/W

management capabilities register (offset 46h, see Section 3.17).

Reserved. Bit 14 returns 0 when read.

PCI_PME support. This bit is used to program bit 13 (PME_SUPPORT_D2) in the power

managementcapabilities register (offset 46h, see Section 3.17). If wake from the D2 power state

implemented in the TSB12LV26 is not desired, then this bit may be cleared to indicate to power

management software that wake-up from D2 is not supported.

12–11

PME_SUPPORT_D2

RSVD

R/W

Reserved. Bits 12–11 return 0s when read.

D2 support. This bit is used to program bit 10 (D2_SUPPORT) in the power management

capabilities register (offset 46h, see Section 3.17). If the D2 power state implemented in the

TSB12LV26isnotdesired, thenthisbitmaybeclearedtoindicatetopowermanagementsoftware

that D2 is not supported.

D2_SUPPORT

RSVD

R/W

9–5

Reserved. Bits 9–5 return 0s when read.

Thisbitdefaultsto0, whichprovidesOHCI-Lynxcompatibletargetabortsignaling. Whenthisbitis

set to 1, it enables the no-target-abort mode, in which the TSB12LV26 returns indeterminate data

instead of signaling target abort.

ThelinkisdividedintothePCI_CLKandSCLKdomains. Ifsoftwaretriestoaccessregistersinthe

link that are not active because the SCLK is disabled, a target abort is issued by the link. On some

systems this can cause a problem resulting in a fatal system error. Enabling this bit allows the link

to respond to these types of requests by returning FFh.

DIS_TGT_ABT

R/W

It is recommended that this bit be set to 1.

When this bit is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA,

respectively. The GPIO3 and GPIO2 terminals are also placed in a high impedance state.

GP2IIC

R/W

When this bit is set to 1, the internal SCLK runs identically with the chip input. This bit is a test

feature only and should be cleared to 0 (all applications).

DISABLE_SCLKGATE

DISABLE_PCIGATE

KEEP_PCLK

When this bit is set, the internal PCI clock runs identically with the chip input. This bit is a test

feature only and should be cleared to 0 (all applications).

When this bit is set to 1, the PCI clock is always kept running through the PCI_CLKRUN protocol.

When this bit is cleared, the PCI clock may be stopped using PCI_CLKRUN.

3–14

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3.21 Link Enhancement Control Register

The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial

ROM, if present. After these bits are set, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host

controller control register (OHCI offset 50h/54h, see Section 4.16) is set. See Table 3–18 for a complete description

of the register contents.

Bit

Name

Type

Default

Bit

Link enhancement control

Name

Type

Default

Link enhancement control

R/W

Type:

Offset:

Default:

Link enhancement control

Read/Write, Read-only

F4h

0000 1000h

Table 3–18. Link Enhancement Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Reserved. Bits 31–14 return 0s when read.

31–14

RSVD

This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the

TSB12LV26 retries the packet, it uses a 2-Kbyte threshold resulting in a store-and-forward operation.

00 = Threshold ~ 2K bytes resulting in a store-and-forward operation

01 = Threshold ~ 1.7K bytes (default)

10 = Threshold ~ 1K bytes

11 = Threshold ~ 512 bytes

These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K threshold

is optimal. Changing this value may increase or decrease the 1394 latency depending on the average

PCI bus latency.

13–12

atx_thresh

R/W

Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds,

or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than

the AT threshold, then the remaning data must be received before the AT FIFO is emptied; otherwise,

an underrun condition will occur, resulting in a packet error at the receiving node. As a result, the link

will then commence store-and-forward operation, i.e., wait until it has the complete packet in the FIFO

before retransmitting it on the second attempt, to ensure delivery.

An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data

will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to

2K results in only complete packets being transmitted.

11–8

RSVD

Reserved. Bits 11–8 return 0s when read.

Enable asynchronous priority requests. OHCI-Lynx compatible. Setting this bit to 1 enables the link

to respond to requests with priority arbitration. It is recommended that this bit be set to 1.

enab_unfair

R/W

This bit is not assigned in the TSB12LV26 follow-on products since this bit location loaded by the serial

ROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller

control register (OHCI offset 50h/54h, see Section 4.16).

RSVD

5–3

Reserved. Bits 5–3 return 0s when read.

Enable insert idle. OHCI-Lynx compatible. When the PHY has control of the Ct[0:1] control lines and

D[0:8] data lines and the link requests control, the PHY drives 11b on the Ct[0:1] lines. The link can

then start driving these lines immediately. Setting this bit to 1 inserts an idle state, so the link waits one

clock cycle before it starts driving the lines (turnaround time). It is recommended that this bit be set to

enab_insert_idle

R/W

3–15

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Table 3–18. Link Enhancement Control Register Description (Continued)

BIT

FIELD NAME

enab_accel

RSVD

TYPE

R/W

DESCRIPTION

Enable acceleration enhancements. OHCI-Lynx compatible. When set to 1, this bit notifies the PHY

that the link supports the 1394a acceleration enhancements, i.e., ack-accelerated, fly-by

concatenation, etc. It is recommended that this bit be set to 1.

Reserved. Bit 0 returns 0 when read.

3.22 Subsystem Access Register

Write access to the subsystem access register updates the subsystem identification registers identically to

OHCI-Lynx. The system ID value written to this register may also be read back from this register. See Table 3–19 for

a complete description of the register contents.

Bit

Name

Type

Default

Bit

Subsystem access

R/W

Name

Type

Default

Subsystem access

R/W

Type:

Offset:

Default:

Subsystem access

Read/Write

F8h

0000 0000h

Table 3–19. Subsystem Access Register Description

BIT

31–16

15–0

FIELD NAME

SUBDEV_ID

SUBVEN_ID

TYPE

DESCRIPTION

R/W

Subsystem device ID. This field indicates the subsystem device ID.

Subsystem vendor ID. This field indicates the subsystem vendor ID.

3–16

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3.23 GPIO Control Register

The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3–20 for a

complete description of the register contents.

Bit

Name

Type

Default

Bit

GPIO control

RWU R/W

R/W

RWU

Name

Type

Default

GPIO control

Type:

GPIO control

Read/Write/Update, ReadWrite, Read-only

Offset:

Default:

FCh

0000 0000h

Table 3–20. GPIO Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

When this bit is set, a TSB12LV26 general-purpose interrupt event occurs on a level change of the

GPIO3 input. This event may generate an interrupt, with mask and event status reported through the

OHCI interrupt mask (OHCI offset 88h/8Ch, see Section 4.22) and interrupt event (OHCI offset

80h/84h, see Section 4.21) registers.

INT_3EN

R/W

RSVD

Reserved. Bit 30 returns 0 when read.

GPIO_INV3

R/W

GPIO3 polarity invert. When this bit is set, the polarity of GPIO3 is inverted.

GPIO3 enable control. When this bit is set, the output is enabled. Otherwise, the output is high

impedance.

27–25

GPIO_ENB3

RSVD

R/W

Reserved. Bits 27–25 return 0s when read.

GPIO3 data. Reads from this bit return the logical value of the input to GPIO3. Writes to this bit update

the value to drive to GPIO3 when output is enabled.

GPIO_DATA3

RWU

When this bit is set, a TSB12LV26 general-purpose interrupt event occurs on a level change of the

GPIO2 input. This event may generate an interrupt, with mask and event status reported through the

OHCI interrupt mask (OHCI offset 88h/8Ch, see Section 4.22) and interrupt event (OHCI offset

80h/84h, see Section 4.21) registers.

INT_2EN

R/W

RSVD

Reserved. Bit 22 returns 0 when read.

GPIO_INV2

R/W

GPIO2 polarity invert. When this bit is set, the polarity of GPIO2 is inverted.

GPIO2 enable control. When this bit is set, the output is enabled. Otherwise, the output is high

impedance.

19–17

GPIO_ENB2

RSVD

R/W

Reserved. Bits 19–17 return 0s when read.

GPIO2 data. Reads from this bit return the logical value of the input to GPIO2. Writes to this bit update

the value to drive to GPIO2 when the output is enabled.

GPIO_DATA2

RSVD

RWU

15–0

Reserved. Bits 15–0 return 0s when read.

3–17

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3–18

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4 OHCI Registers

The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a

2-Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see

Section 3.9). These registers are the primary interface for controlling the TSB12LV26 IEEE 1394 link function.

This section provides the register interface and bit descriptions. There are several set/clear register pairs in this

programming model, which are implemented to solve various issues with typical read-modify-write control registers.

There are two addresses for a set/clear register: RegisterSet and RegisterClear. Refer to Table 4–1 for an illustration.

A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set, while a 0 bit leaves the

corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register

to be cleared, while a 0 bit leaves the corresponding bit in the set/clear register unaffected.

Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively.

However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt

event register is an example of this behavior.

Table 4–1. OHCI Register Map

DMA CONTEXT

OHCI version

ABBREVIATION

Version

OFFSET

00h

—

GUID ROM

GUID_ROM

ATRetries

04h

Asynchronous transmit retries

CSR data

08h

CSRData

0Ch

CSR compare data

CSR control

CSRCompareData

CSRControl

ConfigROMhdr

BusID

10h

14h

Configuration ROM header

Bus identification

Bus options

18h

1Ch

BusOptions

GUIDHi

20h

GUID high

24h

GUID low

GUIDLo

28h

Reserved

—

2Ch–30h

34h

Configuration ROM map

Posted write address low

Posted write address high

Vendor identification

ConfigROMmap

PostedWriteAddressLo

PostedWriteAddressHi

VendorID

38h

3Ch

40h–4Ch

50h

HCControlSet

HCControlClr

—

Host controller control

Reserved

54h

58h–5Ch

4–1

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Table 4–1. OHCI Register Map (Continued)

DMA CONTEXT

ABBREVIATION

OFFSET

60h

Self ID

Reserved

—

Self ID buffer

Self ID count

Reserved

SelfIDBuffer

64h

SelfIDCount

68h

—

6Ch

—

IRChannelMaskHiSet

IRChannelMaskHiClear

IRChannelMaskLoSet

IRChannelMaskLoClear

IntEventSet

70h

Isochronous receive channel mask high

Isochronous receive channel mask low

Interrupt event

74h

78h

7Ch

80h

IntEventClear

84h

IntMaskSet

88h

Interrupt mask

IntMaskClear

8Ch

IsoXmitIntEventSet

IsoXmitIntEventClear

IsoXmitIntMaskSet

IsoXmitIntMaskClear

IsoRecvIntEventSet

IsoRecvIntEventClear

IsoRecvIntMaskSet

IsoRecvIntMaskClear

90h

Isochronous transmit interrupt event

Isochronous transmit interrupt mask

Isochronous receive interrupt event

Isochronous receive interrupt mask

94h

98h

9Ch

—

A0h

A4h

A8h

ACh

B0–D8h

DCh

E0h

Reserved

Fairness control

FairnessControl

LinkControlSet

LinkControlClear

NodeID

Link control

E4h

Node identification

PHY layer control

Isochronous cycle timer

Reserved

E8h

PhyControl

ECh

F0h

Isocyctimer

F4h–FCh

100h

104h

108h

10Ch

110h

114h

118h

11Ch

120h

124h–17Ch

AsyncRequestFilterHiSet

AsyncRequestFilterHiClear

AsyncRequestFilterLoSet

AsyncRequestFilterloClear

PhysicalRequestFilterHiSet

PhysicalRequestFilterHiClear

PhysicalRequestFilterLoSet

PhysicalRequestFilterloClear

PhysicalUpperBound

Asynchronous request filter high

Asynchronous request filter low

Physical request filter high

Physical request filter low

Physical upper bound

Reserved

—

4–2

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Table 4–1. OHCI Register Map (Continued)

DMA CONTEXT

ABBREVIATION

OFFSET

180h

ContextControlSet

Asynchronous context control

ContextControlClear

184h

Asychronous

Request Transmit

[ ATRQ ]

Reserved

—

188h

Asynchronous context command pointer

Reserved

CommandPtr

18Ch

—

190h–19Ch

1A0h

ContextControlSet

Asynchronous context control

ContextControlClear

1A4h

Asychronous

Response Transmit

[ ATRS ]

Reserved

—

1A8h

Asynchronous context command pointer

Reserved

CommandPtr

1ACh

—

1B0h–1BCh

1C0h

ContextControlSet

Asynchronous context control

ContextControlClear

1C4h

Asychronous

Request Receive

[ ARRQ ]

Reserved

—

1C8h

Asynchronous context command pointer

Reserved

CommandPtr

1CCh

—

1D0h–1DCh

1E0h

ContextControlSet

Asynchronous context control

ContextControlClear

1E4h

Asychronous

Response Receive

[ ARRS ]

Reserved

—

1E8h

Asynchronous context command pointer

Reserved

CommandPtr

1ECh

—

1F0h–1FCh

200h + 16*n

204h + 16*n

208h + 16*n

ContextControlSet

ContextControlClear

—

Isochronous transmit context control

Reserved

Isochronous

Transmit Context n

n = 0, 1, 2, 3, … , 7

Isochronous transmit context command

pointer

CommandPtr

20Ch + 16*n

Reserved

—

280h – 3FCh

400h + 32*n

404h + 32*n

408h + 32*n

ContextControlSet

ContextControlClear

—

Isochronous receive context control

Isochronous

Receive Context n

n = 0, 1, 2, 3

Reserved

Isochronous receive context command

pointer

CommandPtr

ContextMatch

40Ch + 32*n

410h + 32*n

Context match

4–3

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4.1 OHCI Version Register

This register indicates the OHCI version support, and whether or not the serial ROM is present. See Table 4–2 for

a complete description of the register contents.

Bit

Name

Type

Default

Bit

OHCI version

Name

Type

Default

OHCI version

Type:

Offset:

Default:

OHCI version

Read-only

00h

0X01 0000h

Table 4–2. OHCI Version Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–25

RSVD

Reserved. Bits 31–25 return 0s when read.

The TSB12LV26 sets this bit if the serial ROM is detected. If the serial ROM is present, then the

Bus_Info_Block is automatically loaded on hardware reset.

GUID_ROM

Major version of the OHCI. The TSB12LV26 is compliant with the 1394 Open Host Controller Interface

Specification; thus, this field reads 01h.

23–16

15–8

7–0

version

RSVD

Reserved. Bits 15–8 return 0s when read.

Minor version of the OHCI. The TSB12LV26 is compliant with the 1394 Open Host Controller Interface

Specification; thus, this field reads 00h.

revision

4–4

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4.2 GUID ROM Register

The GUID ROM register is used to access the serial ROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI

version register (OHCI offset 00h, see Section 4.1) is set. See Table 4–3 for a complete description of the register

contents.

Bit

Name

Type

Default

Bit

GUID ROM

RSU

Name

Type

Default

GUID ROM

Type:

GUID ROM

Read/Set/Update, Read/Update, Read-only

Offset:

Default:

04h

00XX 0000h

Table 4–3. GUID ROM Register Description

BIT

FIELD NAME

addrReset

RSVD

TYPE

RSU

DESCRIPTION

Software sets this bit to reset the GUID ROM address to 0. When the TSB12LV26 completes the reset,

it clears this bit. The TSB12LV26 does not automatically fill bits 23–16 (rdData field) with the 0 byte.

30–26

Reserved. Bits 30–26 return 0s when read.

A read of the currently addressed byte is started when this bit is set. This bit is automatically cleared

when the TSB12LV26 completes the read of the currently addressed GUID ROM byte.

rdStart

RSU

RSVD

rdData

RSVD

Reserved. Bit 24 returns 0 when read.

23–16

15–0

This field represents the data read from the GUID ROM.

Reserved. Bits 15–0 return 0s when read.

4–5

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4.3 Asynchronous Transmit Retries Register

The asynchronous transmit retries register indicates the number of times the TSB12LV26 attempts a retry for

asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4–4 for

a complete description of the register contents.

Bit

Name

Type

Default

Bit

Asynchronous transmit retries

Name

Type

Default

Asynchronous transmit retries

R/W

Type:

Offset:

Default:

Asynchronous transmit retries

Read/Write, Read-only

08h

0000 0000h

Table 4–4. Asynchronous Transmit Retries Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–29

28–16

15–12

secondLimit

cycleLimit

RSVD

The second limit field returns 0s when read, since outbound dual-phase retry is not implemented.

The cycle limit field returns 0s when read, since outbound dual-phase retry is not implemented.

Reserved. Bits 15–12 return 0s when read.

This field tells the physical response unit how many times to attempt to retry the transmit operation

for the response packet when a busy acknowledge or ack_data_error is received from the target

node.

11–8

7–4

3–0

maxPhysRespRetries

maxATRespRetries

maxATReqRetries

R/W

This field tells the asynchronous transmit response unit how many times to attempt to retry the

transmit operation for the response packet when a busy acknowledge or ack_data_error is

received from the target node.

This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the

transmit operation for the response packet when a busy acknowledge or ack_data_error is

received from the target node.

4.4 CSR Data Register

The CSR data register is used to access the bus management CSR registers from the host through compare-swap

operations. This register contains the data to be stored in a CSR if the compare is successful.

Bit

Name

Type

Default

Bit

CSR data

Name

Type

Default

CSR data

Type:

Offset:

Default:

CSR data

Read-only

0Ch

XXXX XXXXh

4–6

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4.5 CSR Compare Register

The CSR compare register is used to access the bus management CSR registers from the host through

compare-swap operations. This register contains the data to be compared with the existing value of the CSR

resource.

Bit

Name

Type

Default

Bit

CSR compare

Name

Type

Default

CSR compare

Type:

Offset:

Default:

CSR compare

Read-only

10h

XXXX XXXXh

4.6 CSR Control Register

The CSR control register is used to access the bus management CSR registers from the host through compare-swap

operations. This register is used to control the compare-swap operation and to select the CSR resource. See

Table 4–5 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

CSR control

Name

Type

Default

CSR control

R/W

Type:

CSR control

Read/Write, Read/Update, Read-only

Offset:

Default:

14h

8000 000Xh

Table 4–5. CSR Control Register Description

BIT

FIELD NAME

csrDone

TYPE

DESCRIPTION

This bit is set by the TSB12LV26 when a compare-swap operation is complete. It is cleared whenever

this register is written.

30–2

RSVD

Reserved. Bits 30–2 return 0s when read.

This field selects the CSR resource as follows:

00 = BUS_MANAGER_ID

01 = BANDWIDTH_AVAILABLE

10 = CHANNELS_AVAILABLE_HI

11 = CHANNELS_AVAILABLE_LO

1–0

csrSel

R/W

4–7

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4.7 Configuration ROM Header Register

The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset

FFFF F000 0400h. See Table 4–6 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Configuration ROM header

R/W

Name

Type

Default

Configuration ROM header

R/W

Type:

Configuration ROM header

Read/Write

Offset:

Default:

18h

0000 XXXXh

Table 4–6. Configuration ROM Header Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control

31–24

info_length

R/W

IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control

23–16

15–0

crc_length

R/W

IEEE 1394 bus management field. Must be valid at any time bit 17 (linkEnable) of the host controller

control register (OHCI offset 50h/54h, see Section 4.16) is set. The reset value is undefined if no serial

ROM is present. If a serial ROM is present, then this field is loaded from the serial ROM.

rom_crc_value

4.8 Bus Identification Register

The bus identification register externally maps to the first quadlet in the Bus_Info_Block, and contains the constant

3133 3934h, which is the ASCII value of 1394.

Bit

Name

Type

Default

Bit

Bus identification

Name

Type

Default

Bus identification

Type:

Bus identification

Read-only

Offset:

Default:

1Ch

3133 3934h

4–8

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4.9 Bus Options Register

The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4–7 for a complete

description of the register contents.

Bit

Name

Type

Default

Bit

Bus options

R/W

Name

Type

Default

Bus options

R/W

Type:

Offset:

Default:

Bus options

Read/Write, Read-only

20h

X0XX A0X2h

Table 4–7. Bus Options Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Isochronous resource manager capable. IEEE 1394 bus management field. Must be valid when bit 17

(linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set.

irmc

R/W

Cycle master capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the

host controller control register (OHCI offset 50h/54h, see Section 4.16) is set.

cmc

isc

R/W

Isochronous support capable. IEEE 1394 bus management field. Must be valid when bit 17

(linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16) is set.

Bus manager capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the

host controller control register (OHCI offset 50h/54h, see Section 4.16) is set.

bmc

Power management capable. When set, this indicates that the node is power management capable.

Must be valid when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see

Section 4.16) is set.

pmc

RSVD

R/W

26–24

23–16

Reserved. Bits 26–24 return 0s when read.

Cycle master clock accuracy, in parts per million. IEEE 1394 bus management field. Must be valid

when bit 17 (linkEnable) of the host controller control register (OHCI offset 50h/54h, see Section 4.16)

is set.

cyc_clk_acc

R/W

Maximum request. IEEE 1394 bus management field. Hardware initializes this field to indicate the

maximum number of bytes in a block request packet that is supported by the implementation. This

value, max_rec_bytes must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may

change this field; however, this field must be valid at any time bit 17 (linkEnable) of the host controller

control register (OHCI offset 50h/54h, see Section 4.16) is set. A received block write request packet

withalengthgreaterthanmax_rec_bytesmaygenerateanack_type_error. Thisfieldisnotaffectedby

a soft reset, and defaults to a value indicating 2048 bytes on a hard reset.

15–12

max_rec

R/W

11–8

7–6

5–3

2–0

RSVD

R/W

Reserved. Bits 11–8 return 0s when read.

Generation counter. This field is incremented if any portion of the configuration ROM has been

incremented since the prior bus reset.

RSVD

Lnk_spd

Reserved. Bits 5–3 return 0s when read.

Link speed. This field returns 010, indicating that the link speeds of 100, 200, and 400 Mbits/s are

supported.

4–9

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4.10 GUID High Register

The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third

quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes

to 0s on a hardware reset, which is an illegal GUID value. If a serial ROM is detected, then the contents of this register

are loaded through the serial ROM interface after a PCI reset. At that point, the contents of this register cannot be

changed. If no serial ROM is detected, then the contents of this register are loaded by the BIOS after a PCI reset.

At that point, the contents of this register cannot be changed.

Bit

Name

Type

Default

Bit

GUID high

Name

Type

Default

GUID high

Type:

Offset:

Default:

GUID high

Read-only

24h

0000 0000h

4.11 GUID Low Register

The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to chip_ID_lo

in the Bus_Info_Block. This register initializes to 0s on a hardware reset and behaves identically to the GUID high

Bit

Name

Type

Default

Bit

GUID low

Name

Type

Default

GUID low

Type:

Offset:

Default:

GUID low

Read-only

28h

0000 0000h

4–10

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4.12 Configuration ROM Mapping Register

The configuration ROM mapping register contains the start address within system memory that maps to the start

address of 1394 configuration ROM for this node. See Table 4–8 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Configuration ROM mapping

R/W

Name

Type

Default

Configuration ROM mapping

R/W

Type:

Offset:

Default:

Configuration ROM mapping

Read/Write, Read-only

34h

0000 0000h

Table 4–8. Configuration ROM Mapping Register Description

BIT

31–10

9–0

FIELD NAME

configROMaddr

RSVD

TYPE

R/W

DESCRIPTION

If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is

received,thenthelow-order10bitsoftheoffsetareaddedtothisregistertodeterminethehostmemory

address of the read request.

Reserved. Bits 9–0 return 0s when read.

4.13 Posted Write Address Low Register

The posted write address low register is used to communicate error information if a write request is posted and an

error occurs while writing the posted data packet. This register contains the lower 32 bits of the 1394 destination offset

of the write request that failed.

Bit

Name

Type

Default

Bit

Posted write address low

Name

Type

Default

Posted write address low

Type:

Offset:

Default:

Posted write address low

Read/Update

38h

XXXX XXXXh

4–11

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4.14 Posted Write Address High Register

The posted write address high register is used to communicate error information if a write request is posted and an

error occurs while writing the posted data packet. See Table 4–9 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Posted write address high

Name

Type

Default

Posted write address high

Type:

Posted write address high

Read/Update

Offset:

Default:

3Ch

XXXX XXXXh

Table 4–9. Posted Write Address High Register Description

BIT

31–16

15–0

FIELD NAME

sourceID

TYPE

DESCRIPTION

This field is the bus and node number of the node that issued the write request that failed. Bits 31–22

are the 10-bit bus number and bits 21–16 are the 6-bit node number.

offsetHi

The upper 16 bits of the 1394 destination offset of the write request that failed.

4.15 Vendor ID Register

The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The

TSB12LV26 does not implement Texas Instruments unique behavior with regards to OHCI. Thus, this register is

read-only and returns 0s when read.

Bit

Name

Type

Default

Bit

Vendor ID

Name

Type

Default

Vendor ID

Type:

Offset:

Default:

Vendor ID

Read-only

40h

0000 0000h

4–12

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4.16 Host Controller Control Register

The host controller control set/clear register pair provides flags for controlling the TSB12LV26. See Table 4–10 for

a complete description of the register contents.

Bit

Name

Type

Default

Bit

Host controller control

RSC

RSC RSCU

Name

Type

Default

Host controller control

Type:

Host controller control

Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only

Offset:

50h

54h

set register

clear register

Default:

X00X 0000h

Table 4–10. Host Controller Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

RSVD

noByteSwapData

RSVD

Reserved. Bit 31 returns 0 when read.

This bit is used to control whether physical accesses to locations outside the TSB12LV26 itself as

well as any other DMA data accesses should be swapped.

RSC

29–24

Reserved. Bits 29–24 return 0s when read.

This bit informs upper level software that lower level software has consistently configured the

P1394aenhancementsintheLinkandPHY. Whenthisbitis1, genericsoftwaresuchastheOHCI

driver is responsible for configuring P1394a enhancements in the PHY and bit 22

(aPhyEnhanceEnable)in the TSB12LV26. When this bit is 0, the generic software may not modify

the P1394a enhancements in the TSB12LV26 or PHY and cannot interpret the setting of bit 22

(aPhyEnhanceEnable). This bit is initialized from serial EEPROM.

programPhyEnable

When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set this bit to

use all P1394a enhancements. When bit 23 (programPhyEnable) is set to 0, the software does

not change PHY enhancements or this bit.

aPhyEnhanceEnable

RSC

21–20

RSVD

LPS

Reserved. Bits 21–20 return 0s when read.

This bit is used to control the link power status. Software must set this bit to 1 to permit link-PHY

communication. A 0 prevents link-PHY communication.

RSC

This bit is used to enable (1) or disable (0) posted writes. Software should change this bit only

when bit 17 (linkEnable) is 0.

postedWriteEnable

linkEnable

RSC

This bit is cleared to 0 by either a hardware or software reset. Software must set this bit to 1 when

the system is ready to begin operation and then force a bus reset. This bit is necessary to keep

other nodes from sending transactions before the local system is ready. When this bit is cleared,

the TSB12LV26 is logically and immediately disconnected from the 1394 bus, no packets are

received or processed nor are packets transmitted.

When this bit is set, all TSB12LV26 states are reset, all FIFOs are flushed, and all OHCI registers

aresettotheirhardwareresetvaluesunlessotherwisespecified. PCIregistersarenotaffectedby

this bit. This bit remains set while the soft reset is in progress and reverts back to 0 when the reset

has completed.

SoftReset

RSVD

RSCU

15–0

Reserved. Bits 15–0 return 0s when read.

4–13

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4.17 Self-ID Buffer Pointer Register

The self-ID buffer pointer register points to the 2-Kbyte aligned base address of the buffer in host memory where the

self-ID packets are stored during bus initialization. Bits 31–11 are read/write accessible. Reserved bits 10–0 are

read-only and return 0s when read.

Bit

Name

Type

Default

Bit

Self-ID buffer pointer

R/W

Name

Type

Default

Self-ID buffer pointer

R/W

Type:

Offset:

Default:

Self ID-buffer pointer

Read/Write, Read-only

64h

XXXX XX00h

4.18 Self-ID Count Register

The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID

packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 4–11 for a complete description

of the register contents.

Bit

Name

Type

Default

Bit

Self-ID count

Name

Type

Default

Self-ID count

Type:

Offset:

Default:

Self-ID count

Read/Update, Read-only

68h

X0XX 0000h

Table 4–11. Self-ID Count Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

When this bit is 1, an error was detected during the most recent self-ID packet reception. The con-

tents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no errors

are detected. Note that an error can be a hardware error or a host bus write error.

selfIDError

30–24

23–16

15–11

RSVD

selfIDGeneration

RSVD

Reserved. Bits 30–24 return 0s when read.

The value in this field increments each time a bus reset is detected. This field rolls over to 0 after

reaching 255.

Reserved. Bits 15–11 return 0s when read.

Thisfield indicates thenumberof quadlets that havebeenwritten intotheself-ID bufferfor the current

bits 23–16(selfIDGenerationfield). Thisincludestheheaderquadletandtheself-IDdata. Thisfieldis

cleared to 0 when the self-ID reception begins.

10–2

1–0

selfIDSize

RSVD

Reserved. Bits 1–0 return 0s when read.

4–14

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4.19 Isochronous Receive Channel Mask High Register

The isochronous receive channel mask high set/clear register is used to enable packet receives from the upper 32

isochronous data channels. A read from either the set register or clear register returns the content of the isochronous

receive channel mask high register. See Table 4–12 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Isochronous receive channel mask high

RSC

Name

Type

Default

Isochronous receive channel mask high

RSC

Type:

Isochronous receive channel mask high

Read/Set/Clear

Offset:

70h

74h

set register

clear register

Default:

XXXX XXXXh

Table 4–12. Isochronous Receive Channel Mask High Register Description

BIT

FIELD NAME

isoChannel63

isoChannel62

isoChannel61

isoChannel60

isoChannel59

isoChannel58

isoChannel57

isoChannel56

isoChannel55

isoChannel54

isoChannel53

isoChannel52

isoChannel51

isoChannel50

isoChannel49

isoChannel48

isoChannel47

isoChannel46

isoChannel45

isoChannel44

isoChannel43

isoChannel42

isoChannel41

isoChannel40

isoChannel39

TYPE

RSC

DESCRIPTION

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 63.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 62.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 61.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 60.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 59.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 58.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 57.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 56.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 55.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 54.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 53.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 52.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 51.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 50.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 49.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 48.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 47.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 46.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 45.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 44.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 43.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 42.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 41.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 40.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 39.

4–15

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Table 4–12. Isochronous Receive Channel Mask High Register Description (Continued)

BIT

FIELD NAME

isoChannel38

isoChannel37

isoChannel36

isoChannel35

isoChannel34

isoChannel33

isoChannel32

TYPE

RSC

DESCRIPTION

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 38.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 37.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 36.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 35.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 34.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 33.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 32.

4.20 Isochronous Receive Channel Mask Low Register

The isochronous receive channel mask low set/clear register is used to enable packet receives from the lower 32

isochronous data channels. See Table 4–13 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Isochronous receive channel mask low

RSC

Name

Type

Default

Isochronous receive channel mask low

RSC

Type:

Isochronous receive channel mask low

Read/Set/Clear

Offset:

78h

7Ch

set register

clear register

Default:

XXXX XXXXh

Table 4–13. Isochronous Receive Channel Mask Low Register Description

BIT

FIELD NAME

isoChannel31

isoChannel30

TYPE

RSC

DESCRIPTION

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 31.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 30.

Bits 29 through 2 follow the same pattern.

isoChannel1

isoChannel0

RSC

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 1.

When this bit is set, the TSB12LV26 is enabled to receive from iso channel number 0.

4–16

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4.21 Interrupt Event Register

The interrupt event set/clear register reflects the state of the various TSB12LV26 interrupt sources. The interrupt bits

are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set

register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register.

This register is fully compliant with OHCI and the TSB12LV26 adds an OHCI 1.0 compliant vendor-specific interrupt

function to bit 30. When reading the interrupt event register, the return value is the bit-wise AND function of the

interrupt event and interrupt mask registers per the 1394 Open Host Controller Interface Specification. See

Table 4–14 for a complete description of the register contents.

Bit

Interrupt event

RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU

Name

Type

Default

Bit

RSC

RSCU RSCU

Name

Type

Default

Interrupt event

RSCU RSCU

RSCU RSCU RSCU RSCU RSCU RSCU

Type:

Interrupt event

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only

Offset:

80h

84h

set register

clear register [returns the content of the interrupt event and interrupt mask registers

when read]

Default:

XXXX 0XXXh

Table 4–14. Interrupt Event Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

RSVD

Reserved. Bit 31 returns 0 when read.

This vendor-specific interrupt event is reported when either of the general-purpose interrupts occur

which are enabled via INT3_EN and INT2_EN in the GPIO control register (offset FCh, see Section

3.23).

vendorSpecific

RSC

29–27

RSVD

Reserved. Bits 29–27 return 0s when read.

TheTSB12LV26 has received a PHY register data byte which can be read from the PHY layercontrol

phyRegRcvd

RSCU

If bit 21 (cycleMaster) of the link control register (OHCI offset E0h/E4h, see Section 4.28) is set, then

cycleTooLong

RSCU this indicates that over 125 µs have elapsed between the start of sending a cycle start packet and the

end of a subaction gap. The link control register bit 21 (cycleMaster) is cleared by this event.

This event occurs when the TSB12LV26 encounters any error that forces it to stop operations on any

unrecoverableError RSCU or all of its subunits, for example, when a DMA context sets its dead bit. While this bit is set, all normal

interrupts for the context(s) that caused this interrupt are blocked from being set.

A cycle start was received that had values for cycleSeconds and cycleCount fields that are different

RSCU from the values in bits 31–25 (cycleSeconds field) and bits 24–12 (cycleCount field) of the

isochronous cycle timer register (OHCI offset F0h, see Section 4.31).

cycleInconsistent

A lost cycle is indicated when no cycle_start packet is sent/received between two successive

cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately

follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after

a cycleSynch event without an intervening cycle start. This bit may be set either when a lost cycle

occurs or when logic predicts that one will occur.

cycleLost

RSCU

cycle64Seconds

cycleSynch

RSCU Indicates that the 7 bit of the cycle second counter has changed.

Indicates that a new isochronous cycle has started. This bit is set when the low order bit of the cycle

RSCU

count toggles.

phy

RSCU Indicates that the PHY requests an interrupt through a status transfer.

RSVD

Reserved. Bit 18 returns 0 when read.

4–17

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Table 4–14. Interrupt Event Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

busReset

RSCU Indicates that the PHY chip has entered bus reset mode.

A selfID packet stream has been received. It is generated at the end of the bus initialization process.

This bit is turned off simultaneously when bit 17 (busReset) is turned on.

15–10

selfIDcomplete

RSVD

RSCU

Reserved. Bits 15–10 return 0s when read.

Indicates that the TSB12LV26 sent a lock response for a lock request to a serial bus register, but did

not receive an ack_complete.

lockRespErr

RSCU

IndicatesthatahostbuserroroccurredwhiletheTSB12LV26wastryingtowritea1394writerequest,

which had already been given an ack_complete, into system memory.

postedWriteErr

isochRx

RSCU

Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have

generated an interrupt. This is not a latched event, it is the logical OR of all bits in the isochronous

receive interrupt event (OHCI offset A0h/A4h, see Section 4.25) and isochronous receive interrupt

mask (OHCI offset A8h/ACh, see Section 4.26) registers. The isochronous receive interrupt event

Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have

generated an interrupt. This is not a latched event, it is the logical OR of all bits in the isochronous

transmit interrupt event (OHCI offset 90h/94h, see Section 4.23) and isochronous transmit interrupt

mask (OHCI offset 98h/9Ch, see Section 4.24) registers. The isochronous transmit interrupt event

isochTx

Indicates that a packet was sent to an asynchronous receive response context buffer and the

descriptor xferStatus and resCount fields have been updated.

RSPkt

RQPkt

RSCU

Indicates that a packet was sent to an asynchronous receive request context buffer and the

descriptor xferStatus and resCount fields have been updated.

AsyncreceiveresponseDMAinterrupt.ThisbitisconditionallysetuponcompletionofanARRSDMA

context command descriptor.

ARRS

Async receive request DMA interrupt. This bit is conditionally set upon completion of an ARRQ DMA

context command descriptor.

ARRQ

Asynchronous response transmit DMA interrupt. This bit is conditionally set upon completion of an

ATRS DMA command.

respTxComplete

reqTxComplete

Asynchronous request transmit DMA interrupt. This bit is conditionally set upon completion of an

ATRQ DMA command.

4–18

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4.22 Interrupt Mask Register

The interrupt mask set/clear register is used to enable the various TSB12LV26 interrupt sources. Reads from either

the set register or the clear register always return the contents of the interrupt mask register. In all cases except

masterIntEnable (bit 31) and VendorSpecific(bit30), theenablesforeachinterrupteventalignwiththeinterruptevent

This register is fully compliant with OHCI and the TSB12LV26 adds an OHCI 1.0 compliant interrupt function to bit 30.

Bit

29 28 27

Name

Type

Default

Bit

Interrupt mask

RSCU RSC

RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU

RSCU RSCU

13 12 11

Name

Type

Default

Interrupt mask

RSCU RSCU

RSCU RSCU RSCU RSCU RSCU RSCU

Type:

Interrupt mask

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only

Offset:

88h

8Ch

set register

clear register

Default:

XXXX 0XXXh

Table 4–15. Interrupt Mask Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Master interrupt enable. If this bit is set, then external interrupts are generated in accordance with the

masterIntEnable

RSCU interruptmask register. If this bit is cleared, then external interrupts are not generated regardless of the

interrupt mask register settings.

When this bit is set, this vendor-specific interrupt mask enables interrupt generation when bit 30

(vendorSpecific) of the interrupt event register (OHCI offset 80h/84h, see Section 4.21) is set.

vendorSpecific

RSC

29–0

See Table 4–14.

4–19

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4.23 Isochronous Transmit Interrupt Event Register

The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit

contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command

completes and its interrupt bits are set. Upon determining that the interrupt event register (OHCI offset 80h/84h, see

Section 4.21) isochTx (bit 6) interrupt has occurred, software can check this register to determine which context(s)

caused the interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing

a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the

corresponding bit in the clear register. See Table 4–16 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Isochronous transmit interrupt event

Name

Type

Default

Isochronous transmit interrupt event

RSC

Type:

Isochronous transmit interrupt event

Read/Set/Clear, Read-only

Offset:

90h

94h

set register

clear register [returns IsoXmitEvent and IsoXmitMask when read]

Default:

0000 00XXh

Table 4–16. Isochronous Transmit Interrupt Event Register Description

BIT

FIELD NAME

RSVD

TYPE

DESCRIPTION

31–8

Reserved. Bits 31–8 return 0s when read.

isoXmit7

isoXmit6

isoXmit5

isoXmit4

isoXmit3

isoXmit2

isoXmit1

isoXmit0

RSC

Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx) interrupt.

4–20

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4.24 Isochronous Transmit Interrupt Mask Register

The isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrupt source on a

per-channel basis. Reads from either the set register or the clear register always return the contents of the

isochronous transmit interrupt mask register. In all cases the enables for each interrupt event align with the event

Bit

Name

Type

Default

Bit

Isochronous transmit interrupt mask

Name

Type

Default

Isochronous transmit interrupt mask

RSC

Type:

Isochronous transmit interrupt mask

Read/Set/Clear, Read-only

Offset:

98h

9Ch

set register

clear register

Default:

0000 00XXh

4–21

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4.25 Isochronous Receive Interrupt Event Register

The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive

contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes

and its interrupt bits are set. Upon determining that the interrupt event register (OHCI offset 80h/84h, see Section

4.21) isochRx (bit 7) interrupt has occurred, software can check this register to determine which context(s) caused

the interrupt. An interrupt bit is set by the asserting edge of the corresponding interrupt signal, or by writing a 1 to the

corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the

corresponding bit in the clear register. See Table 4–17 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Isochronous receive interrupt event

Name

Type

Default

Isochronous receive interrupt event

RSC

Type:

Isochronous receive interrupt event

Read/Set/Clear, Read-only

Offset:

A0h

A4h

set register

clear register [returns the contents of isochronous receive interrupt event and

isochronous receive mask registers when read]

Default:

0000 000Xh

Table 4–17. Isochronous Receive Interrupt Event Register Description

BIT

FIELD NAME

RSVD

TYPE

DESCRIPTION

Reserved. Bits 31–4 return 0s when read.

31–4

isoRecv3

isoRecv2

isoRecv1

isoRecv0

RSC

Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt.

Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt.

Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt.

Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt.

4.26 Isochronous Receive Interrupt Mask Register

TheisochronousreceiveinterruptmaskregisterisusedtoenabletheisochRxinterruptsourceonaperchannelbasis.

Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt

mask register. In all cases the enables for each interrupt event align with the event register bits detailed in Table 4–17.

Bit

Name

Type

Default

Bit

Isochronous receive interrupt mask

Name

Type

Default

Isochronous receive interrupt mask

RSC

Type:

Isochronous receive interrupt mask

Read/Set/Clear, Read-only

Offset:

A8h

ACh

set register

clear register

Default:

0000 000Xh

4–22

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4.27 Fairness Control Register

The fairness control register provides a mechanism by which software can direct the host controller to transmit

multiple asynchronous requests during a fairness interval. See Table 4–18 for a complete description of the register

contents.

Bit

Name

Type

Default

Bit

Fairness control

Name

Type

Default

Fairness control

R/W

Type:

Offset:

Default:

Fairness control

Read-only, Read/Write

DCh

0000 0000h

Table 4–18. Fairness Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Reserved. Bits 31–8 return 0s when read.

31–8

RSVD

This field specifies the maximum number of priority arbitration requests for asynchronous request

packets that the link is permitted to make of the PHY during a fairness interval.

7–0

pri_req

R/W

4–23

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4.28 Link Control Register

The link control set/clear register provides the control flags that enable and configure the link core protocol portions

of the TSB12LV26. It contains controls for the receiver and cycle timer. See Table 4–19 for a complete description

of the register contents.

Bit

Name

Type

Default

Bit

Link control

RSC RSCU RSC

Name

Type

Default

Link control

RSC

Type:

Link control

Read/Set/Clear/Update, Read/Set/Clear, Read-only

Offset:

E0h

E4h

set register

clear register

Default:

00X0 0X00h

Table 4–19. Link Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–23

RSVD

Reserved. Bits 31–23 return 0s when read.

Whenthisbitisset, thecycletimerusesanexternalsource(CYCLEIN)todeterminewhentorollover

the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches 3072 cycles

of the 24.576-MHz clock (125 µs).

cycleSource

cycleMaster

RSC

RSCU

RSC

When this bit is set, and the PHY has notified the TSB12LV26 that the PHY is root, the TSB12LV26

generates a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22.

When this bit is cleared, the OHCI-Lynx accepts received cycle start packets to maintain

synchronization with the node which is sending them. This bit is automatically cleared when bit 25

(cycleTooLong) of the interrupt event register (OHCI offset 80h/84h, see Section 4.21) is set and

cannot be set until bit 25 (cycleTooLong) is cleared.

When this bit is set, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over at the

appropriatetimebasedonthesettingsoftheabovebits. Whenthisbitiscleared, thecycletimeroffset

does not count.

CycleTimerEnable

19–11

RSVD

Reserved. Bits 19–11 return 0s when read.

When this bit is set, the receiver accepts incoming PHY packets into the AR request context if the AR

request context is enabled. This does not control receipt of self-ID packets.

RcvPhyPkt

RSC

When this bit is set, the receiver accepts incoming self-ID packets. Before setting this bit to 1,

software must ensure that the self-ID buffer pointer register contains a valid address.

RcvSelfID

RSVD

RSC

8–0

Reserved. Bits 8–0 return 0s when read.

4–24

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4.29 Node Identification Register

The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indicates

the valid node number status. The 16-bit combination of the busNumber field (bits 15–6) and the NodeNumber field

(bits 5–0) is referred to as the node ID. See Table 4–20 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Node identification

Name

Type

Default

Node identification

RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Type:

Node identification

Read/Write/Update, Read/Update, Read-only

Offset:

Default:

E8h

0000 FFXXh

Table 4–20. Node Identification Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

ThisbitindicateswhetherornottheTSB12LV26hasavalidnodenumber.Itisclearedwhena1394bus

reset is detected and set when the TSB12LV26 receives a new node number from the PHY.

iDValid

root

RSVD

CPS

This bit is set during the bus reset process if the attached PHY is root.

Reserved. Bits 29–28 return 0s when read.

29–28

Set if the PHY is reporting that cable power status is OK.

Reserved. Bits 26–16 return 0s when read.

26–16

RSVD

This number is used to identify the specific 1394 bus the TSB12LV26 belongs to when multiple

1394-compatible buses are connected via a bridge.

15–6

5–0

BusNumber

RWU

This number is the physical node number established by the PHY during self-ID. It is automatically set

to the value received from the PHY after the self-ID phase. If the PHY sets the NodeNumber to 63, then

software should not set the run bit (bit 15) of the asynchronous context control register (see Section

4.37) for either of the AT DMA contexts.

NodeNumber

4–25

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4.30 PHY Layer Control Register

The PHY layer control register is used to read or write a PHY register. See Table 4–21 for a complete description of

the register contents.

Bit

Name

Type

Default

Bit

PHY layer control

Name

Type

Default

PHY layer control

RWU RWU

R/W

Type:

PHY layer control

Read/Write/Update, Read/Write, Read/Update, Read-only

Offset:

Default:

ECh

0000 0000h

Table 4–21. PHY Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

This bit is cleared to 0 by the TSB12LV26 when either bit 15 (rdReg) or bit 14 (wrReg) is set. This bit is

set when a register transfer is received from the PHY.

rdDone

30–28

27–24

23–16

RSVD

rdAddr

rdData

Reserved. Bits 30–28 return 0s when read.

This is the address of the register most recently received from the PHY.

This field is the contents of a PHY register which has been read.

This bit is set by software to initiate a read request to a PHY register and is cleared by hardware when

the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must be used exclusively.

rdReg

wrReg

RWU

This bit is set by software to initiate a write request to a PHY register and is cleared by hardware when

the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must be used exclusively.

13–12

11–8

7–0

RSVD

regAddr

wrData

Reserved. Bits 13–12 return 0s when read.

R/W

This field is the address of the PHY register to be written or read.

This field is the data to be written to a PHY register and is ignored for reads.

4–26

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4.31 Isochronous Cycle Timer Register

The isochronous cycle timer register indicates the current cycle number and offset. When the TSB12LV26 is cycle

master, this register is transmitted with the cycle start message. When the TSB12LV26 is not cycle master, this

registerisloadedwiththedatafieldinanincomingcyclestart. Intheeventthatthecyclestartmessageisnotreceived,

the fields can continue incrementing on their own (if programmed) to maintain a local time reference. See Table 4–22

for a complete description of the register contents.

Bit

Isochronous cycle timer

RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Name

Type

Default

Bit

Name

Type

Default

Isochronous cycle timer

RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Type:

Offset:

Default:

Isochronous cycle timer

Read/Write/Update

F0h

XXXX XXXXh

Table 4–22. Isochronous Cycle Timer Register Description

BIT

FIELD NAME

cycleSeconds

cycleCount

TYPE

RWU

DESCRIPTION

31–25

24–12

This field counts seconds [rollovers from bits 24–12 (cycleCount field)] modulo 128.

This field counts cycles [rollovers from bits 11–0 (cycleOffset field)] modulo 8000.

This field counts 24.576-MHz clocks modulo 3072, i.e., 125 µs. If an external 8-kHz clock configuration

is being used, then this bit must be cleared to 0 at each tick of the external clock.

11–0

cycleOffset

RWU

4–27

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4.32 Asynchronous Request Filter High Register

The asynchronous request filter high set/clear register is used to enable asynchronous receive requests on a

per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context

or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set in this register,

then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the source

node is on the same bus as the TSB12LV26. Nonlocal bus sourced packets are not acknowledged unless bit 31 in

this register is set. See Table 4–23 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Asynchronous request filter high

RSC

Name

Type

Default

Asynchronous request filter high

RSC

Type:

Asynchronous request filter high

Read/Set/Clear

Offset:

100h set register

104h clear register

0000 0000h

Default:

Table 4–23. Asynchronous Request Filter High Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

If this bit is set, then all asynchronous requests received by the TSB12LV26 from nonlocal bus

nodes are accepted.

asynReqAllBuses

asynReqResource62

asynReqResource61

asynReqResource60

asynReqResource59

asynReqResource58

asynReqResource57

asynReqResource56

asynReqResource55

asynReqResource54

asynReqResource53

asynReqResource52

asynReqResource51

RSC

If this bit is set for local bus node number 62, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

RSC

If this bit is set for local bus node number 61, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 60, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 59, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 58, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 57, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 56, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 55, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 54, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 53, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 52, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 51, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

4–28

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Table 4–23. Asynchronous Request Filter High Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

If this bit is set for local bus node number 50, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

asynReqResource50

RSC

If this bit is set for local bus node number 49, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

asynReqResource49

asynReqResource48

asynReqResource47

asynReqResource46

asynReqResource45

asynReqResource44

asynReqResource43

asynReqResource42

asynReqResource41

asynReqResource40

asynReqResource39

asynReqResource38

asynReqResource37

asynReqResource36

asynReqResource35

asynReqResource34

asynReqResource33

asynReqResource32

RSC

If this bit is set for local bus node number 48, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 47, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 46, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 45, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 44, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 43, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 42, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 41, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 40, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 39, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 38, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 37, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 36, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 35, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 34, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 33, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

If this bit is set for local bus node number 32, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

4–29

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4.33 Asynchronous Request Filter Low Register

The asynchronous request filter low set/clear register is used to enable asynchronous receive requests on a per-node

basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the

asynchronous request filter high register. See Table 4–24 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Asynchronous request filter low

RSC

Name

Type

Default

Asynchronous request filter low

RSC

Type:

Asynchronous request filter low

Read/Set/Clear

Offset:

108h set register

10Ch clear register

0000 0000h

Default:

Table 4–24. Asynchronous Request Filter Low Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

If this bit is set for local bus node number 31, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

asynReqResource31

asynReqResource30

RSC

If this bit is set for local bus node number 30, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

RSC

Bits 29 through 2 follow the same pattern.

If this bit is set for local bus node number 1, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

asynReqResource1

asynReqResource0

RSC

If this bit is set for local bus node number 0, then asynchronous requests received by the

TSB12LV26 from that node are accepted.

4–30

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4.34 Physical Request Filter High Register

The physical request filter high set/clear register is used to enable physical receive requests on a per-node basis and

handles the upper node IDs. When a packet is destined for the physical request context and the node ID has been

compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding

to the node ID is not set in this register, then the request is handled by the ARRQ context instead of the physical

request context. The node ID comparison is done if the source node is on the same bus as the TSB42AD2. Nonlocal

bus sourced packets are not acknowledged unless bit 31 in this register is set. See Table 4–25 for a complete

description of the register contents.

Bit

Name

Type

Default

Bit

Physical request filter high

RSC

Name

Type

Default

Physical request filter high

RSC

Type:

Physical request filter high

Read/Set/Clear

Offset:

110h set register

114h clear register

0000 0000h

Default:

Table 4–25. Physical Request Filter High Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

If this bit is set, then all physical requests received by the TSB12LV26 from non-local bus nodes

are accepted.

physReqAllBusses

physReqResource62

physReqResource61

physReqResource60

physReqResource59

physReqResource58

physReqResource57

physReqResource56

physReqResource55

physReqResource54

physReqResource53

physReqResource52

RSC

Ifthisbitissetforlocalbusnodenumber62, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

RSC

Ifthisbitissetforlocalbusnodenumber61, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber60, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber59, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber58, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber57, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber56, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber55, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber54, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber53, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber52, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

4–31

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Table 4–25. Physical Request Filter High Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

Ifthisbitissetforlocalbusnodenumber51, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

physReqResource51

RSC

Ifthisbitissetforlocalbusnodenumber50, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

physReqResource50

physReqResource49

physReqResource48

physReqResource47

physReqResource46

physReqResource45

physReqResource44

physReqResource43

physReqResource42

physReqResource41

physReqResource40

physReqResource39

physReqResource38

physReqResource37

physReqResource36

physReqResource35

physReqResource34

physReqResource33

physReqResource32

RSC

Ifthisbitissetforlocalbusnodenumber49, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber48, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber47, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber46, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber45, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber44, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber43, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber42, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber41, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber40, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber39, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber38, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber37, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber36, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber35, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber34, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber33, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

Ifthisbitissetforlocalbusnodenumber32, thenphysicalrequestsreceivedbytheTSB12LV26

from that node are handled through the physical request context.

4–32

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4.35 Physical Request Filter Low Register

The physical request filter low set/clear register is used to enable physical receive requests on a per-node basis and

handles the lower node IDs. When a packet is destined for the physical request context and the node ID has been

compared against the asynchronous request filter registers, then the node ID comparison is done again with this

asynchronous request context instead of the physical request context. See Table 4–26 for a complete description of

the register contents.

Bit

Name

Type

Default

Bit

Physical request filter low

RSC

Name

Type

Default

Physical request filter low

RSC

Type:

Physical request filter low

Read/Set/Clear

Offset:

118h set register

11Ch clear register

0000 0000h

Default:

Table 4–26. Physical Request Filter Low Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

If this bit is set for local bus node number 31, then physical requests received by the TSB12LV26

from that node are handled through the physical request context.

physReqResource31

physReqResource30

RSC

If this bit is set for local bus node number 30, then physical requests received by the TSB12LV26

from that node are handled through the physical request context.

RSC

Bits 29 through 2 follow the same pattern.

If this bit is set for local bus node number 1, then physical requests received by the TSB12LV26

from that node are handled through the physical request context.

physReqResource1

physReqResource0

RSC

If this bit is set for local bus node number 0, then physical requests received by the TSB12LV26

from that node are handled through the physical request context.

4–33

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4.36 Physical Upper Bound Register (Optional Register)

The physical upper bound register is an optional register and is not implemented. It returns all 0s when read.

Bit

Name

Type

Default

Bit

Physical upper bound

Name

Type

Default

Physical upper bound

Type:

Physical upper bound

Read-only

Offset:

Default:

120h

0000 0000h

4–34

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4.37 Asynchronous Context Control Register

The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See

Table 4–27 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Asynchronous context control

Name

Type

Default

Asynchronous context control

RSCU

RSU

Type:

Offset:

Asynchronous context control

Read/Set/Clear/Update, Read/Set/Update, Read/Update, Read-only

180h set register [ATRQ]

184h clear register [ATRQ]

1A0h set register [ATRS]

1A4h clear register [ATRS]

1C0h set register [ARRQ]

1C4h clear register [ARRQ]

1E0h set register [ARRS]

1E4h clear register [ARRS]

0000 X0XXh

Default:

Table 4–27. Asynchronous Context Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

Reserved. Bits 31–16 return 0s when read.

31–16

RSVD

This bit is set by software to enable descriptor processing for the context and cleared by software to

stop descriptor processing. The TSB12LV26 changes this bit only on a hardware or software reset.

14–13

run

RSCU

RSVD

wake

Reserved. Bits 14–13 return 0s when read.

Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing. The

TSB12LV26 clears this bit on every descriptor fetch.

RSU

The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets

bit 15 (run).

dead

active

RSVD

The TSB12LV26 sets this bit to 1 when it is processing descriptors.

Reserved. Bits 9–8 return 0s when read.

9–8

This field indicates the speed at which a packet was received or transmitted, and only contains

meaningful information for receive contexts. This field is encoded as:

000 = 100 Mbits/sec,

7–5

4–0

spd

001 = 200 Mbits/sec, and

010 = 400 Mbits/sec. All other values are reserved.

This field holds the acknowledge sent by the link core for this packet, or holds an internally generated

error code if the packet was not transferred successfully.

eventcode

4–35

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4.38 Asynchronous Context Command Pointer Register

The asynchronous context command pointer register contains a pointer to the address of the first descriptor block

that the TSB12LV26 accesses when software enables the context by setting the asynchronous context control

Bit

Asynchronous context command pointer

RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Name

Type

Default

Bit

Name

Type

Default

Asynchronous context command pointer

RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Type:

Offset:

Asynchronous context command pointer

Read/Write/Update

18Ch [ATRQ]

1ACh [ATRS]

1CCh [ArRQ]

1ECh [ArRS]

Default:

XXXX XXXXh

Table 4–28. Asynchronous Context Command Pointer Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–4

descriptorAddress

RWU

Contains the upper 28 bits of the address of a 16-byte-aligned descriptor block.

Indicatesthe number of contiguous descriptors at the address pointed to by the descriptor address. If

Z is 0, then it indicates that the descriptorAddress field (bits 31–4) is not valid.

3–0

RWU

4–36

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4.39 Isochronous Transmit Context Control Register

The isochronous transmit context control set/clear register controls options, state, and status for the isochronous

transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3,… ,

7). See Table 4–29 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Isochronous transmit context control

RSCU RSC

RSC

RSC RSC

RSC

Name

Type

Default

Isochronous transmit context control

RSC

RSU

Type:

Isochronous transmit context control

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only

Offset:

200h + (16 * n)

204h + (16 * n)

XXXX X0XXh

set register

clear register

Default:

Table 4–29. Isochronous Transmit Context Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

When this bit is set to 1, processing occurs such that the packet described by the context first

descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field

(bits 30–16). The cycleMatch field (bits 30–16) must match the low-order two bits of cycleSeconds

and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before

isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead,

the processing of the first descriptor block may begin slightly in advance of the actual cycle in which

the first packet is transmitted.

cycleMatchEnable

RSCU

The effects of this bit, however, are impacted by the values of other bits in this register and are

explained in the 1394 Open Host Controller Interface Specification. Once the context has become

active, hardware clears this bit.

Contains a 15-bit value, corresponding to the low-order two bits of the bus isochronous cycle timer

(bits 24–12). If bit 31 (cycleMatchEnable) is set, then this isochronous transmit DMA context

becomes enabled for transmits when the low-order two bits of the bus isochronous cycle timer

(cycleMatch) value.

30–16

cycleMatch

RSC

This bit is set by software to enable descriptor processing for the context and cleared by software to

stop descriptor processing. The TSB12LV26 changes this bit only on a hardware or software reset.

14–13

run

RSC

RSVD

wake

Reserved. Bits 14–13 return 0s when read.

Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing. The

TSB12LV26 clears this bit on every descriptor fetch.

RSU

The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets

bit 15 (run).

dead

active

RSVD

spd

The TSB12LV26 sets this bit to 1 when it is processing descriptors.

Reserved. Bits 9–8 return 0s when read.

9–8

7–5

This field is not meaningful for isochronous transmit contexts.

FollowinganOUTPUT_LAST*command, theerrorcodeisindicatedinthisfield. Possiblevaluesare:

ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.

4–0

event code

4–37

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4.40 Isochronous Transmit Context Command Pointer Register

The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor

block that the TSB12LV26 accesses when software enables an isochronous transmit context by setting the

isochronous transmit context control register (see Section 4.39) bit 15 (run). The n value in the following register

addresses indicates the context number (n = 0, 1, 2, 3, … , 7).

Bit

Name

Type

Default

Bit

Isochronous transmit context command pointer

Name

Type

Default

Isochronous transmit context command pointer

Type:

Isochronous transmit context command pointer

Read-only

Offset:

Default:

20Ch + (16 * n)

XXXX XXXXh

4.41 Isochronous Receive Context Control Register

The isochronous receive context control set/clear register controls options, state, and status for the isochronous

receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).

See Table 4–30 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Isochronous receive context control

RSC

RSC RSCU RSC

Name

Type

Default

Isochronous receive context control

RSCU

RSU

Type:

Isochronous receive context control

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only

Offset:

400h + (32 * n)

404h + (32 * n)

X000 X0XXh

set register

clear register

Default:

Table 4–30. Isochronous Receive Context Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

When this bit is set, received packets are placed back-to-back to completely fill each receive buffer.

When this bit is cleared, each received packet is placed in a single buffer. If bit 28 (multiChanMode)

is set to 1, then this bit must also be set to 1. The value of this bit must not be changed while bit 10

(active) or bit 15 (run) is set.

bufferFill

RSC

When this bit is 1, received isochronous packets include the complete 4-byte isochronous packet

headerseenbythelinklayer. TheendofthepacketismarkedwithxferStatusinthefirstdoublet, and

a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart packet.

When this bit is cleared, the packet header is stripped from received isochronous packets. The

packet header, if received, immediately precedes the packet payload. The value of this bit must not

be changed while bit 10 (active) or bit 15 (run) is set.

isochHeader

RSC

4–38

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Table 4–30. Isochronous Receive Context Control Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

When this bit is set, the context begins running only when the 13-bit cycleMatch field (bits 24–12) in

the isochronous receive context match register (see Section 4.43) matches the 13-bit cycleCount

fieldin the cycleStart packet. The effects of this bit, however, are impacted by the values of other bits

in this register. Once the context has become active, hardware clears this bit. The value of this bit

must not be changed while bit 10 (active) or bit 15 (run) is set.

cycleMatchEnable

RSCU

When this bit is set, the corresponding isochronous receive DMA context receives packets for all

isochronouschannelsenabledintheisochronousreceivechannelmaskhigh(OHCIoffset70h/74h,

see Section 4.19) and isochronous receive channel mask low (OHCI offset 78h/7Ch, see Section

4.20) registers. The isochronous channel number specified in the isochronous receive context

match register (see Section 4.43) is ignored.

When this bit is cleared, the isochronous receive DMA context receives packets for that single

channel. Only one isochronous receive DMA context may use the isochronous receive channel

mask registers. If more than one isochronous receive context control register has this bit set, then

results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is

set to 1.

multiChanMode

RSC

27–16

RSVD

run

RSCU

Reserved. Bits 27–16 return 0s when read.

This bit is set by software to enable descriptor processing for the context and cleared by software to

stop descriptor processing. The TSB12LV26 changes this bit only on a hardware or software reset.

14–13

RSVD

wake

Reserved. Bits 14–13 return 0s when read.

Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing. The

TSB12LV26 clears this bit on every descriptor fetch.

RSU

The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets

bit 15 (run).

dead

active

RSVD

The TSB12LV26 sets this bit to 1 when it is processing descriptors.

Reserved. Bits 9–8 return 0s when read.

9–8

This field indicates the speed at which the packet was received.

000 = 100 Mbits/sec,

7–5

4–0

spd

001 = 200 Mbits/sec, and

010 = 400 Mbits/sec. All other values are reserved.

For bufferFill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and

evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and

packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode, possible

values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read,

evt_data_write, and evt_unknown.

event code

4–39

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4.42 Isochronous Receive Context Command Pointer Register

The isochronous receive context command pointer register contains a pointer to the address of the first descriptor

block that the TSB12LV26 accesses when software enables an isochronous receive context by setting the

isochronous receive context control register (see Section 4.41) bit 15 (run). The n value in the following register

addresses indicates the context number (n = 0, 1, 2, 3).

Bit

Name

Type

Default

Bit

Isochronous receive context command pointer

Name

Type

Default

Isochronous receive context command pointer

Type:

Isochronous receive context command pointer

Read-only

Offset:

Default:

40Ch + (32 * n)

XXXX XXXXh

4–40

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4.43 Isochronous Receive Context Match Register

The isochronous receive context match register is used to start an isochronous receive context running on a specified

cycle number, to filter incoming isochronous packets based on tag values, and to wait for packets with a specified

sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See

Table 4–31 for a complete description of the register contents.

Bit

Name

Type

Default

Bit

Isochronous receive context match

R/W

Name

Type

Default

Isochronous receive context match

R/W

Type:

Offset:

Default:

Isochronous receive context match

Read/Write, Read-only

410Ch + (32 * n)

XXXX XXXXh

Table 4–31. Isochronous Receive Context Match Register Description

BIT

FIELD NAME

tag3

TYPE

R/W

DESCRIPTION

If this bit is set, then this context matches on iso receive packets with a tag field of 11b.

If this bit is set, then this context matches on iso receive packets with a tag field of 10b.

If this bit is set, then this context matches on iso receive packets with a tag field of 01b.

If this bit is set, then this context matches on iso receive packets with a tag field of 00b.

Reserved. Bits 27–25 return 0s when read.

tag2

tag1

tag0

27–25

RSVD

Contains a 15-bit value, corresponding to the low-order two bits of cycleSeconds and the 13-bit

cycleCount field in the cycleStart packet. If isochronous receive context control register (see Section

4.41)bit 29 (cycleMatchEnable) is set, then this context is enabled for receives when the two low-order

bits of the bus isochronous cycle timer register (OHCI offset F0h, see Section 4.31) cycleSeconds field

(bits 31–25) and cycleCount field (bits 24–12) value equal this (cycleMatch) field value.

24–12

cycleMatch

R/W

This field contains the 4-bit field which is compared to the sync field of each iso packet for this channel

when the command descriptor w field is set to 11b.

11–8

sync

R/W

RSVD

Reserved. Bit 7 returns 0 when read.

Ifthisbitandbit29(tag1)areset, thenpacketswithtag01bareacceptedintothecontextifthetwomost

significant bits of the packets sync field are 00b. Packets with tag values other than 01b are filtered

according to tag0, tag2, and tag3 (bits 28, 30, and 31, respectively) without any additional restrictions.

tag1SyncFilter

R/W

If this bit is cleared, then this context matches on isochronous receive packets as specified in

bits 28–31 (tag0–tag3) with no additional restrictions.

This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA

context accepts packets.

5–0

channelNumber

4–41

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4–42

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5 GPIO Interface

The general-purpose input/output (GPIO) interface consists of two GPIO ports. GPIO2 and GPIO3 power up as

general-purpose inputs and are programmable via the GPIO control register. Figure 5–1 shows the logic diagram for

GPIO2 and GPIO3 implementation.

GPIO Read Data

GPIO Port

GPIO Write Data

GPIO_Invert

GPIO Enable

Figure 5–1. GPIO2 and GPIO3 Logic Diagram

5–1

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5–2

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6 Serial ROM Interface

The TSB12LV26 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI

configurationregistersthroughaserialROM. TheTSB12LV26communicateswiththeserialROMviathe2-wireserial

interface.

After power-up the serial interface initializes the locations listed in Table 6–1. While the TSB12LV26 is accessing the

serial ROM, all incoming PCI slave accesses are terminated with retry status. Table 6–2 shows the serial ROM

memory map required for initializing the TSB12LV26 registers.

Table 6–1. Registers and Bits Loadable through Serial ROM

BITS LOADED

FROM ROM

ROM OFFSET

OHCI/PCI OFFSET

00h

01h

03h

PCI register (3Eh)

PCI register (2Dh)

PCI register (2Ch)

OHCI register (50h)

PCI register (F4h)

OHCI register (24h)

OHCI register(28h)

PCI register (F4h)

PCI register (F0h)

PCI register (40h)

PCI maximum latency, PCI minimum grant

PCI vendor ID

15–0

PCI subsystem ID

15–0

05h (bit 6)

05h

Host controller control register

Link enhancements control register

GUID high

7, 2, 1

31–0

06h – 0Ah

0Bh – 0Eh

10h

GUID low

31–0

Link enhancements control register

PCI miscellaneous register

PCI OHCI register

13, 12

15, 13, 10

12h

13h

6–1

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Table 6–2. Serial ROM Map

BYTE

ADDRESS

BYTE DESCRIPTION

PCI maximum latency (0h)

PCI_minimum grant (0h)

PCI vendor ID

PCI vendor ID (msbyte)

PCI subsystem ID (lsbyte)

PCI subsystem ID

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Link_enhancement-

HCControl.

RSVD

RSVD Link_enhancement- Link_enhancement-

RSVD

Control.enab_unfair ProgramPhy

Enable

Control.enab_

insert_idle

Control.enab_accel

Mini ROM address

GUID high (lsbyte 0)

GUID high (byte 1)

GUID high (byte 2)

GUID high (msbyte 3)

GUID low (lsbyte 0)

GUID low (byte 1)

GUID low (byte 2)

GUID low (msbyte 3)

Checksum

[15]

RSVD

[14]

RSVD

[13–12]

AT threshold

[11]

RSVD

[10]

RSVD

[9]

RSVD

[8]

RSVD

[7]

RSVD

[6]

RSVD

[5]

RSVD

[4]

[3]

[2]

[1]

[0]

Keep PCI

Disable GP2IIC Disable SCLK gate

Target

Abort

Disable PCI gate

[15]

PME D3 Cold

[14]

RSVD

[13]

PME

Support

[12]

RSVD

[11]

RSVD

[10]

D2 support

[9]

RSVD

[8]

RSVD

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

RSVD

Global

swap

15–1E

RSVD

6–2

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7 Electrical Characteristics

†

7.1 Absolute Maximum Ratings Over Operating Temperature Ranges

Supply voltage range, V

Input voltage range for PCI, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V

Input voltage range for miscellaneous and PHY interface, V . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V

Output voltage range for PCI, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V

CCP

+ 0.5 V

CCP

CCI

CCP

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V

Input voltage range for miscellaneous and PHY interface, V . . . . . . . . . . . . . . . . . . . . . –0.5 to V

Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

Output clamp current, I

(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

†

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and

functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Applies to external input and bidirectional buffers. V > V

CCP

2. Applies to external output and bidirectional buffers. V > V

CCP

7–1

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7.2 Recommended Operating Conditions

OPERATION

3.3 V

MIN

NOM

3.3

MAX

3.6

UNIT

Core voltage

Commercial

3.3 V

3.6

PCI I/O clamping voltage

CCP

5 V

4.5

5.5

3.3 V

0.475 V

CCP

PCI

5 V

†

High-level input voltage

Low-level input voltage

PHY interface

Miscellaneous

‡

3.3 V

5 V

0.325 V

CCP

PCI

0.8

†

PHY interface

Miscellaneous

PCI

0.8

‡

0.8

3.3 V

CCP

PHY interface

Miscellaneous

PCI

Input voltage

CCP

PHY interface

Miscellaneous

PCI

Output voltage

CCP

Input transition time (t and t )

°C

Operating ambient temperature

Virtual junction temperature

115

†

‡

Applies for external inputs and bidirectional buffers without hysteresis.

Miscellaneous pins are: GPIO2, GPIO3, SDA, SCL, CYCLEOUT.

Applies for external output buffers.

The junction temperatures reflect simulation conditions. Customer is responsible for verifying junction temperature.

7–2

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7.3 Electrical Characteristics Over Recommended Operating Conditions (unless

otherwise noted)

TEST

OPERATION

MIN

0.9 V

MAX

UNIT

CONDITIONS

= – 0.5 mA

= – 2 mA

= – 4 µA

= – 8 mA

= – 4 mA

= 1.5 mA

= 6 mA

PCI

2.4

2.8

High-level output voltage

Low-level output voltage

PHY interface

Miscellaneous

PCI

– 0.6

‡

– 0.6

0.1 V

0.55

0.4

†

= 4 mA

PHY interface

= 8 mA

‡

Miscellaneous

Output pins

Input pins

= 4 mA

0.5

±20

3-state output high-impedance

Low-level input current

3.6 V

= V or GND

µA

‡

V = GND

µA

†

‡

I/O pins

V = GND

±20

†

‡

PCI

V = V

±20

High-level input current

µA

†

Others

V = V

±20

†

‡

For I/O pins, input leakage (I and I ) includes I

IL IH

of the disabled output.

Miscellaneous pins are: GPIO2, GPIO3, SDA, SCL, CYCLEOUT.

7.4 Switching Characteristics for PCI Interface

PARAMETER

MEASURED

–50% to 50%

MIN

TYP

MAX

UNIT

Setup time before PCLK

Hold time before PCLK

Delay time, PHY_CLK to data valid

These parameters are ensured by design.

7.5 Switching Characteristics for PHY-Link Interface

PARAMETER

MEASURED

–50% to 50%

MIN

TYP

MAX

UNIT

Setup time, Dn, CTLn, LREQ to PHY_CLK

Hold time, Dn, CTLn, LREQ before PHY_CLK

Delay time, PHY_CLK to Dn, CTLn

These parameters are ensured by design.

7–3

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7–4

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8 Mechanical Information

The TSB12LV26 is packaged in a 100-terminal PZ package. The following shows the mechanical dimensions for the

PZ package.

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

0,08

100

0,13 NOM

12,00 TYP

Gage Plane

14,20

13,80

0,25

16,20

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MO-136

8–1

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8–2