TMS320TCI648x Serial RapidIO (SRIO)
User's Guide
Literature Number: SPRUE13A
September 2006
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Contents
Preface.............................................................................................................................. 14
1
Overview .................................................................................................................. 16
1.1
1.2
1.3
1.4
1.5
General RapidIO System ...................................................................................... 16
RapidIO Feature Support in SRIO............................................................................ 19
Standards........................................................................................................ 20
External Devices Requirements .............................................................................. 20
TI Devices Supported By This Document ................................................................... 20
2
SRIO Functional Description....................................................................................... 21
2.1
2.2
2.3
Overview......................................................................................................... 21
SRIO Pins ....................................................................................................... 25
Functional Operation ........................................................................................... 26
3
4
Logical/Transport Error Handling and Logging ............................................................. 83
Interrupt Conditions................................................................................................... 85
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
CPU Interrupts .................................................................................................. 85
General Description ............................................................................................ 85
Interrupt Condition Status and Clear Registers............................................................. 86
Interrupt Condition Routing Registers........................................................................ 93
Interrupt Status Decode Registers ........................................................................... 97
Interrupt Generation............................................................................................ 99
Interrupt Pacing ................................................................................................. 99
Interrupt Handling ............................................................................................. 100
5
SRIO Registers........................................................................................................ 102
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Introduction .................................................................................................... 102
Peripheral Identification Register (PID) .................................................................... 111
Peripheral Control Register (PCR).......................................................................... 112
Peripheral Settings Control Register (PER_SET_CNTL) ................................................ 113
Peripheral Global Enable Register (GBL_EN) ............................................................ 116
Peripheral Global Enable Status Register (GBL_EN_STAT)............................................ 117
Block n Enable Register (BLKn_EN) ....................................................................... 119
Block n Enable Status Register (BLKn_EN_STAT) ...................................................... 120
RapidIO DEVICEID1 Register (DEVICEID_REG1)....................................................... 121
5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2)....................................................... 122
5.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn)............................... 123
5.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn).................................. 124
5.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) .................................. 130
5.16 DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR) ............................. 132
5.17 DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR) .............................. 133
5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ................................................... 134
5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)..................................................... 135
5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) .................................................... 136
5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) ..................................................... 137
5.22 LSU Interrupt Condition Status Register (LSU_ICSR) ................................................... 138
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5.23 LSU Interrupt Condition Clear Register (LSU_ICCR) .................................................... 141
5.24 Error, Reset, and Special Event Interrupt Condition Status Register
(ERR_RST_EVNT_ICSR).................................................................................... 142
5.25 Error, Reset, and Special Event Interrupt Condition Clear Register
(ERR_RST_EVNT_ICCR) ................................................................................... 143
5.26 DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and
DOORBELLn_ICRR2)........................................................................................ 144
5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3) .............................. 147
5.30 Error, Reset, and Special Event Interrupt Condition Routing Registers
5.31 Interrupt Status Decode Register (INTDSTn_DECODE) ................................................ 150
5.32 INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL)................................... 154
5.33 LSUn Control Register 0 (LSUn_REG0) ................................................................... 155
5.34 LSUn Control Register 1 (LSUn_REG1) ................................................................... 156
5.35 LSUn Control Register 2 (LSUn_REG2) ................................................................... 157
5.36 LSUn Control Register 3 (LSUn_REG3) ................................................................... 158
5.37 LSUn Control Register 4 (LSUn_REG4) ................................................................... 159
5.38 LSUn Control Register 5 (LSUn_REG5) ................................................................... 160
5.39 LSUn Control Register 6 (LSUn_REG6) ................................................................... 161
5.48 Receive CPPI Control Register (RX_CPPI_CNTL)....................................................... 173
5.51 Flow Control Table Entry Register n (FLOW_CNTLn) ................................................... 181
5.52 Device Identity CAR (DEV_ID) .............................................................................. 182
5.53 Device Information CAR (DEV_INFO) ..................................................................... 183
5.54 Assembly Identity CAR (ASBLY_ID) ....................................................................... 184
5.55 Assembly Information CAR (ASBLY_INFO)............................................................... 185
5.56 Processing Element Features CAR (PE_FEAT) .......................................................... 186
5.57 Source Operations CAR (SRC_OP)........................................................................ 188
5.58 Destination Operations CAR (DEST_OP) ................................................................. 189
5.59 Processing Element Logical Layer Control CSR (PE_LL_CTL) ........................................ 190
5.60 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR)................................. 191
5.61 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR)................................... 192
5.62 Base Device ID CSR (BASE_ID) ........................................................................... 193
5.63 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK)............................................. 194
5.64 Component Tag CSR (COMP_TAG) ....................................................................... 195
5.65 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD).......................... 196
5.66 Port Link Time-Out Control CSR (SP_LT_CTL) .......................................................... 197
5.67 Port Response Time-Out Control CSR (SP_RT_CTL)................................................... 198
5.68 Port General Control CSR (SP_GEN_CTL) ............................................................... 199
4
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5.69 Port Link Maintenance Request CSR n (SPn_LM_REQ)................................................ 200
5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP) ............................................ 201
5.71 Port Local AckID Status CSR n (SPn_ACKID_STAT) ................................................... 202
5.72 Port Error and Status CSR n (SPn_ERR_STAT) ......................................................... 203
5.73 Port Control CSR n (SPn_CTL) ............................................................................. 206
5.74 Error Reporting Block Header Register (ERR_RPT_BH)................................................ 209
5.75 Logical/Transport Layer Error Detect CSR (ERR_DET) ................................................. 210
5.76 Logical/Transport Layer Error Enable CSR (ERR_EN) .................................................. 212
5.77 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT).............................. 214
5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT)........................................ 215
5.79 Logical/Transport Layer Device ID Capture CSR (ID_CAPT)........................................... 216
5.80 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) ......................................... 217
5.81 Port-Write Target Device ID CSR (PW_TGT_ID)......................................................... 218
5.82 Port Error Detect CSR n (SPn_ERR_DET)................................................................ 219
5.83 Port Error Rate Enable CSR n (SPn_RATE_EN)......................................................... 221
5.84 Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) ............................ 223
5.85 Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1)................................................. 224
5.86 Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2)................................................. 225
5.87 Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3)................................................. 226
5.88 Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4)................................................. 227
5.89 Port Error Rate CSR n (SPn_ERR_RATE)................................................................ 228
5.90 Port Error Rate Threshold CSR n (SPn_ERR_THRESH) ............................................... 229
5.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) ...................... 230
5.92 Port IP Mode CSR (SP_IP_MODE) ........................................................................ 231
5.93 Port IP Prescaler Register (IP_PRESCAL) ................................................................ 233
5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3]) .............................................. 234
5.95 Port Reset Option CSR n (SPn_RST_OPT)............................................................... 235
5.96 Port Control Independent Register n (SPn_CTL_INDEP) ............................................... 236
5.97 Port Silence Timer n Register (SPn_SILENCE_TIMER) ................................................ 238
5.99 Port Control Symbol Transmit n Register (SPn_CS_TX) ................................................ 240
Index............................................................................................................................... 241
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List of Figures
1
RapidIO Architectural Hierarchy.......................................................................................... 17
RapidIO Interconnect Architecture ....................................................................................... 18
Serial RapidIO Device to Device Interface Diagrams ................................................................. 19
SRIO Peripheral Block Diagram.......................................................................................... 22
Operation Sequence ....................................................................................................... 23
1x/4x RapidIO Packet Data Stream (Streaming-Write Class)........................................................ 24
Serial RapidIO Control Symbol Format.................................................................................. 24
SRIO Component Block Diagram ........................................................................................ 27
SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) ............................................... 28
SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)............................... 31
SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) .............................. 33
2
3
4
5
6
7
8
9
10
11
12
Load/Store Registers for RapidIO (Address Offset: LSU1 400h–418h, LSU2 420h–438h, LSU3
440h–458h, LSU4 460h-478h) ........................................................................................... 36
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
LSU Registers Timing ..................................................................................................... 38
Example Burst NWRITE_R ............................................................................................... 39
Load/Store Module Data Flow Diagram................................................................................. 40
CPPI RX Scheme for RapidIO............................................................................................ 44
Message Request Packet................................................................................................. 45
Mailbox to Queue Mapping Register Pair............................................................................... 46
RX Buffer Descriptor Fields............................................................................................... 47
RX CPPI Mode Explanation .............................................................................................. 49
CPPI Boundary Diagram .................................................................................................. 51
TX Buffer Descriptor Fields ............................................................................................... 52
Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh)................................... 56
RX Buffer Descriptors...................................................................................................... 62
TX Buffer Descriptors...................................................................................................... 63
Doorbell Operation ......................................................................................................... 64
Flow Control Table Entry Registers (Address Offset 0900h–093Ch) ............................................... 66
Transmit Source Flow Control Masks ................................................................................... 67
Fields Within Each Flow Mask............................................................................................ 67
Configuration Bus Example ............................................................................................... 69
DMA Example .............................................................................................................. 69
GBL_EN (Address 0030h) ................................................................................................ 71
GBL_EN_STAT (Address 0034h)........................................................................................ 71
BLK0_EN (Address 0038h) ............................................................................................... 72
BLK0_EN_STAT (Address 003Ch) ...................................................................................... 73
BLK1_EN (Address 0040h) ............................................................................................... 73
BLK1_EN_STAT (Address 0044h)....................................................................................... 73
BLK8_EN (Address 0078h) ............................................................................................... 73
BLK8_EN_STAT (Address 007Ch) ...................................................................................... 73
Peripheral Control Register (PCR) - Address Offset 0004h .......................................................... 74
Bootload Operation ........................................................................................................ 80
Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) Offsets 0x0090, 0x0098, 0x00A0,
0x00A8....................................................................................................................... 81
Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) Offsets 0x0094, 0x009C, 0x00A4,
43
0x00AC ...................................................................................................................... 82
44
45
46
47
48
49
Logical/Transport Layer Error Detect CSR (ERR_DET) .............................................................. 83
RapidIO DOORBELL Packet for Interrupt Use......................................................................... 85
Doorbell 0 Interrupt Condition Status and Clear Registers ........................................................... 87
Doorbell 1 Interrupt Condition Status and Clear Registers ........................................................... 87
Doorbell 2 Interrupt Condition Status and Clear Registers ........................................................... 88
Doorbell 3 Interrupt Condition Status and Clear Registers ........................................................... 88
6
List of Figures
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50
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65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
RX CPPI Interrupt Condition Status and Clear Registers............................................................. 89
TX CPPI Interrupt Condition Status and Clear Registers ............................................................. 89
LSU Interrupt Condition Status and Clear Registers .................................................................. 90
Error, Reset, and Special Event Interrupt Condition Status and Clear Registers ................................. 91
Doorbell 0 Interrupt Condition Routing Registers ...................................................................... 94
RX CPPI Interrupt Condition Routing Registers........................................................................ 94
TX CPPI Interrupt Condition Routing Registers........................................................................ 95
LSU Interrupt Condition Routing Registers ............................................................................. 96
Error, Reset, and Special Event Interrupt Condition Routing Registers ............................................ 97
Interrupt Status Decode Register (INTDSTn_DECODE) ............................................................. 98
Interrupt Sources Assigned to ISDR Bits ............................................................................... 98
Example Diagram of Interrupt Status Decode Register Mapping.................................................... 99
INTDSTn_RATE_CNTL Interrupt Rate Control Register ............................................................ 100
Peripheral ID Register (PID) - Address Offset 0000h................................................................ 111
Peripheral Control Register (PCR) - Address Offset 0004h......................................................... 112
Peripheral Settings Control Register (PER_SET_CNTL) (Address Offset 0020h)............................... 113
Peripheral Global Enable Register (GBL_EN) (Address Offset 0030h) ........................................... 116
Peripheral Global Enable Status Register (GBL_EN_STAT) - Address 0034h .................................. 117
Block n Enable Register (BLKn_EN)................................................................................... 119
Block n Enable Status Register (BLKn_EN) .......................................................................... 120
RapidIO DEVICEID1 Register (DEVICEID_REG1) (Offset 0080h) ................................................ 121
RapidIO DEVICEID2 Register (DEVICEID_REG2) (Offset 0x0084)............................................... 122
Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) .......................................... 123
Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) ............................................. 124
SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) ............................. 125
SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL)............................. 128
SERDES Macro Configuration Register n (SERDES_CFGn_CNTL).............................................. 130
Doorbell n Interrupt Condition Status Register (DOORBELLn_ICSR)............................................. 132
Doorbell n Interrupt Condition Clear Register (DOORBELLn_ICCR).............................................. 133
RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) - Address Offset 0240h ...................... 134
RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) - Address Offset 0248h ....................... 135
TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) - Address Offset 0250h....................... 136
TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) - Address Offset 0258h........................ 137
LSU Interrupt Condition Status Register (LSU_ICSR) - Address Offset 0260h .................................. 138
LSU Interrupt Condition Clear Register (LSU_ICCR) - Address Offset 0268h ................................... 141
Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) - Address
Offset 0270h............................................................................................................... 142
Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) - Address
86
Offset 0278h............................................................................................................... 143
87
88
89
90
91
92
93
94
95
96
97
98
99
Doorbell n Interrupt Condition Routing Registers..................................................................... 144
RX CPPI Interrupt Condition Routing Registers ...................................................................... 145
TX CPPI Interrupt Condition Routing Registers ...................................................................... 146
LSU Interrupt Condition Routing Registers............................................................................ 147
Error, Reset, and Special Event Interrupt Condition Routing Registers........................................... 149
Interrupt Status Decode Register (INTDSTn_DECODE)............................................................ 150
INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL) .............................................. 154
LSUn Control Register 0 (LSUn_REG0)............................................................................... 155
LSUn Control Register 1 (LSUn_REG1)............................................................................... 156
LSUn Control Register 2 (LSUn_REG2)............................................................................... 157
LSUn Control Register 3 (LSUn_REG3)............................................................................... 158
LSUn Control Register 4 (LSUn_REG4)............................................................................... 159
LSUn Control Register 5 (LSUn_REG5)............................................................................... 160
100 LSUn Control Register 6 (LSUn_REG6)............................................................................... 161
LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) ......................................... 162
101
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102 LSUn FLOW_MASK Fields.............................................................................................. 162
103
104
105
106
107
Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) ......................... 164
Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP) ................................. 165
Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP).......................... 166
Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP).................................. 167
108 Transmit CPPI Supported Flow Mask Registers ..................................................................... 170
109 TX Queue n FLOW_MASK Fields...................................................................................... 170
110
111
112
Receive CPPI Control Register (RX_CPPI_CNTL) (Address Offset 0744h)...................................... 173
Transmit CPPI Weighted Round Robin Control Registers .......................................................... 174
113 Mailbox to Queue Mapping Register Pair ............................................................................. 179
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
Flow Control Table Entry Register n (FLOW_CNTLn)............................................................... 181
Device Identity CAR (DEV_ID) - Address Offset 1000h ............................................................. 182
Device Information CAR (DEV_INFO) - Address Offset 1004h .................................................... 183
Assembly Identity CAR (ASBLY_ID) - Address Offset 1008h ...................................................... 184
Assembly Information CAR (ASBLY_INFO) - Address Offset 100Ch ............................................. 185
Processing Element Features CAR (PE_FEAT) - Address Offset 1010h ......................................... 186
Source Operations CAR (SRC_OP) - Address Offset 1018h....................................................... 188
Destination Operations CAR (DEST_OP) - Address Offset 101Ch................................................ 189
Processing Element Logical Layer Control CSR (PE_LL_CTL) - Address Offset 104Ch....................... 190
Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) - Address Offset 1058h................ 191
Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) - Address Offset 105Ch ................. 192
Base Device ID CSR (BASE_ID) - Address Offset 1060h .......................................................... 193
Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) - Address Offset 1068h............................ 194
Component Tag CSR (COMP_TAG) - Address Offset 106Ch ..................................................... 195
1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) - Address Offset 1100h........ 196
Port Link Time-Out Control CSR (SP_LT_CTL) - Address Offset 1120h ......................................... 197
Port Response Time-Out Control CSR (SP_RT_CTL) - Address Offset 1124h.................................. 198
Port General Control CSR (SP_GEN_CTL) - Address Offset 113Ch.............................................. 199
Port Link Maintenance Request CSR n (SPn_LM_REQ) ........................................................... 200
Port Link Maintenance Response CSR n (SPn_LM_RESP)........................................................ 201
Port Local AckID Status CSR n (SPn_ACKID_STAT) ............................................................... 202
135 Port Error and Status CSR n (SPn_ERR_STAT)..................................................................... 203
136 Port Control CSR n (SPn_CTL)......................................................................................... 206
137
138
139
140
141
142
143
144
Error Reporting Block Header Register (ERR_RPT_BH) - Address Offset 2000h............................... 209
Logical/Transport Layer Error Detect CSR (ERR_DET) - Address Offset 2008h ................................ 210
Logical/Transport Layer Error Enable CSR (ERR_EN) - Address Offset 200Ch................................. 212
Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) - Address Offset 2010h............. 214
Logical/Transport Layer Address Capture CSR (ADDR_CAPT) - Address Offset 2014h....................... 215
Logical/Transport Layer Device ID Capture CSR (ID_CAPT) - Address Offset 2018h.......................... 216
Logical/Transport Layer Control Capture CSR (CTRL_CAPT) - Address Offset 201Ch ........................ 217
Port-Write Target Device ID CSR (PW_TGT_ID) - Address Offset 2028h........................................ 218
145 Port Error Detect CSR n (SPn_ERR_DET) ........................................................................... 219
146 Port Error Rate Enable CSR n (SPn_RATE_EN) .................................................................... 221
147
148
149
150
151
Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0)........................................ 223
Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1)............................................................. 224
Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2)............................................................. 225
Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3)............................................................. 226
Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4)............................................................. 227
152 Port Error Rate CSR n (SPn_ERR_RATE)............................................................................ 228
153
154
Port Error Rate Threshold CSR n (SPn_ERR_THRESH)........................................................... 229
Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) - Address Offset 12000h.... 230
8
List of Figures
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155
156
Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h...................................................... 231
Port IP Prescaler Register (IP_PRESCAL) - Address Offset 12008h ............................................. 233
157 Port-Write-In Capture CSRs............................................................................................. 234
158 Port Reset Option CSR n (SPn_RST_OPT) .......................................................................... 235
159
160
161
162
Port Control Independent Register n (SPn_CTL_INDEP)........................................................... 236
Port Silence Timer n Register (SPn_SILENCE_TIMER) ............................................................ 238
Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) ............................ 239
Port Control Symbol Transmit n Register (SPn_CS_TX)............................................................ 240
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List of Figures
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List of Tables
1
TI Devices Supported By This Document............................................................................... 20
Registers Checked for Multicast DeviceID.............................................................................. 21
Packet Types ............................................................................................................... 25
Pin Description.............................................................................................................. 26
SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions ......................... 29
Line Rate versus PLL Output Clock Frequency........................................................................ 30
Effect of the RATE Bits .................................................................................................... 30
Frequency Range versus MPY Value ................................................................................... 30
EQ Bits....................................................................................................................... 33
DE Bits of SERDES_CFGTXn_CNTL ................................................................................... 34
SWING Bits of SERDES_CFGTXn_CNTL.............................................................................. 35
LSU Control/Command Register Fields ................................................................................. 36
LSU Status Register Fields ............................................................................................... 37
RX DMA State Head Descriptor Pointer (HDP) (Address Offset 600h–63Ch)..................................... 46
RX DMA State Completion Pointer (CP) (Address Offset 680h–6BCh) ............................................ 46
RX Buffer Descriptor Field Descriptions................................................................................. 47
TX DMA State Head Descriptor Pointer (HDP) (Address Offset 500h–53Ch) ..................................... 51
TX DMA State Completion Pointer (CP) (Address Offset 58h–5BCh) .............................................. 52
TX Buffer Descriptor Field Definitions ................................................................................... 52
Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh)................................... 56
Examples of DOORBELL_INFO Designations (See Figure 26 )..................................................... 64
Flow Control Table Entry Register n (FLOW_CNTLn) Field Descriptions .......................................... 67
Fields Within Each Flow Mask............................................................................................ 68
Reset Hierarchy ............................................................................................................ 70
Global Enable and Global Enable Status Field Descriptions......................................................... 72
Block Enable and Block Enable Status Field Descriptions ........................................................... 73
Peripheral Control Register (PCR) Field Descriptions................................................................. 74
Port Mode Register Settings.............................................................................................. 77
Multicast DeviceID Operation............................................................................................. 81
Packet Forwarding Register n for 16-Bit DeviceIDs (PF_16B_CNTLn) Field Descriptions ...................... 81
Packet Forwarding Register n for 8-Bit DeviceIDs (PF_8B_CNTLn) Field Descriptions ......................... 82
Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ........................................ 83
Interrupt Condition Status and Clear Bits ............................................................................... 87
Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR .......................................... 90
Interrupt Clearing Sequence for Special Event Interrupts ............................................................ 92
Interrupt Condition Routing Options ..................................................................................... 93
Serial RapidIO (SRIO) Registers ....................................................................................... 102
Peripheral ID Register (PID) Field Descriptions ...................................................................... 111
Peripheral Control Register (PCR) Field Descriptions ............................................................... 112
Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions ..................................... 113
Peripheral Global Enable Register (GBL_EN) Field Descriptions.................................................. 116
Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions................................. 117
Block n Enable Registers and the Associated Blocks ............................................................... 119
Block n Enable Register (BLKn_EN) Field Descriptions............................................................. 119
Block n Enable Status Registers and the Associated Blocks....................................................... 120
Block n Enable Status Register (BLKn_EN_STAT) Field Descriptions............................................ 120
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3
4
5
6
7
8
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10
List of Tables
SPRUE13A–September 2006
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50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions ............................................ 121
RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions ............................................ 122
PF_16B_CNTL Registers................................................................................................ 123
Packet Forwarding Register n for 16-Bit DeviceIDs (PF_16B_CNTLn) Field Descriptions ..................... 123
PF_8B_CNTL Registers ................................................................................................. 124
Packet Forwarding Register n for 8-Bit DeviceIDs (PF_8B_CNTLn) Field Descriptions ........................ 124
SERDES_CFGRXn_CNTL Registers and the Associated Ports ................................................... 125
EQ Bits ..................................................................................................................... 126
SERDES_CFGTXn_CNTL Registers and the Associated Ports ................................................... 128
DE Bits of SERDES_CFGTXn_CNTL.................................................................................. 129
SWING Bits of SERDES_CFGTXn_CNTL ............................................................................ 129
SERDES_CFGn_CNTL Registers and the Associated Ports....................................................... 130
SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) Field Descriptions........................ 130
DOORBELLn_ICSR Registers .......................................................................................... 132
DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR) Field Descriptions................... 132
DOORBELLn_ICCR Registers.......................................................................................... 133
DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR) Field Descriptions.................... 133
RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) Field Descriptions............................. 134
RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) Field Descriptions.............................. 135
TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) Field Descriptions ............................. 136
TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) Field Descriptions .............................. 137
LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions......................................... 138
LSU Interrupt Condition Clear Register (LSU_ICCR) Field Descriptions.......................................... 141
Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) Field
Descriptions ............................................................................................................... 142
76
Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) Field
Descriptions ............................................................................................................... 143
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
DOORBELLn_ICRR Registers.......................................................................................... 144
DOORBELLn Interrupt Condition Routing Register Field Descriptions............................................ 144
RX CPPI Interrupt Condition Routing Register Field Descriptions ................................................. 145
TX CPPI Interrupt Condition Routing Register Field Descriptions ................................................. 146
LSU Interrupt Condition Routing Register Field Descriptions....................................................... 148
Error, Reset, and Special Event Interrupt Condition Routing Register Field Descriptions...................... 149
INTDSTn_DECODE Registers and the Associated Interrupt Destinations ....................................... 150
Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions...................................... 150
INTDSTn_RATE_CNTL Registers and the Associated Interrupt Destinations ................................... 154
INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL) Field Descriptions........................ 154
LSUn_REG0 Registers and the Associated LSUs ................................................................... 155
LSUn Control Register 0 (LSUn_REG0) Field Descriptions ........................................................ 155
LSUn_REG1 Registers and the Associated LSUs ................................................................... 156
LSUn Control Register 1 (LSUn_REG1) Field Descriptions ........................................................ 156
LSUn_REG2 Registers and the Associated LSUs ................................................................... 157
LSUn Control Register 2 (LSUn_REG2) Field Descriptions ........................................................ 157
LSUn_REG3 Registers and the Associated LSUs ................................................................... 158
LSUn Control Register 3 (LSUn_REG3) Field Descriptions ........................................................ 158
LSUn_REG4 Registers and the Associated LSUs ................................................................... 159
LSUn Control Register 4 (LSUn_REG4) Field Descriptions ........................................................ 159
LSUn_REG5 Registers and the Associated LSUs ................................................................... 160
LSUn Control Register 5 (LSUn_REG5) Field Descriptions ........................................................ 160
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99
LSUn_REG6 Registers and the Associated LSUs ................................................................... 161
LSUn Control Register 6 (LSUn_REG6) Field Descriptions ........................................................ 161
LSUn_FLOW_MASKS Registers and the Associated LSUs........................................................ 162
LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) Field Descriptions ................... 162
100
101
102
103 LSUn FLOW_MASK Fields.............................................................................................. 162
104 QUEUEn_TXDMA_HDP Registers..................................................................................... 164
105
106 QUEUEn_TXDMA_CP Registers....................................................................................... 165
107
Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) Field Descriptions............ 165
108 QUEUEn_RXDMA_HDP Registers..................................................................................... 166
109
110 QUEUEn_RXDMA_CP Registers ...................................................................................... 167
111
112
113
Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) Field Descriptions ........... 167
Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions ......................... 168
TX_CPPI_FLOW_MASKS Registers and the Associated TX Queues ............................................ 169
114 TX Queue n FLOW_MASK Field Descriptions........................................................................ 170
115
116
117
118
119
120
Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions ......................... 172
Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions ............................................ 173
Transmit CPPI Weighted Round Robin Control Register Field Descriptions ..................................... 175
Mailbox to Queue Mapping Registers and the Associated RX Mappers.......................................... 177
Mailbox-to-Queue Mapping Register Ln (RXU_MAP_Ln) Field Descriptions..................................... 179
Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) Field Descriptions.................................... 179
121 FLOW_CNTLn Registers ................................................................................................ 181
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
Flow Control Table Entry Register n (FLOW_CNTLn) Field Descriptions ........................................ 181
Device Identity CAR (DEV_ID) Field Descriptions ................................................................... 182
Device Information CAR (DEV_INFO) Field Descriptions........................................................... 183
Assembly Identity CAR (ASBLY_ID) Field Descriptions............................................................. 184
Assembly Information CAR (ASBLY_INFO) Field Descriptions .................................................... 185
Processing Element Features CAR (PE_FEAT) Field Descriptions ............................................... 186
Source Operations CAR (SRC_OP) Field Descriptions ............................................................. 188
Destination Operations CAR (DEST_OP) Field Descriptions....................................................... 189
Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions.............................. 190
Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions ...................... 191
Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions ........................ 192
Base Device ID CSR (BASE_ID) Field Descriptions................................................................. 193
Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) Field Descriptions .................................. 194
Component Tag CSR (COMP_TAG) Field Descriptions ............................................................ 195
1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) Field Descriptions .............. 196
Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions ................................................. 197
Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions ........................................ 198
Port General Control CSR (SP_GEN_CTL) Field Descriptions .................................................... 199
SPn_LM_REQ Registers and the Associated Ports ................................................................. 200
Port Link Maintenance Request CSR n (SPn_LM_REQ) Field Descriptions ..................................... 200
SPn_LM_RESP Registers and the Associated Ports................................................................ 201
Port Link Maintenance Response CSR n (SPn_LM_RESP) Field Descriptions ................................. 201
SPn_ACKID_STAT Registers and the Associated Ports............................................................ 202
Port Local AckID Status CSR n (SPn_ACKID_STAT) Field Descriptions......................................... 202
SPn_ERR_STAT Registers and the Associated Ports .............................................................. 203
Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions .............................................. 203
148 SPn_CTL Registers and the Associated Ports ....................................................................... 206
Port Control CSR n (SPn_CTL) Field Descriptions .................................................................. 206
149
12
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150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
Error Reporting Block Header Register (ERR_RPT_BH) Field Descriptions ..................................... 209
Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ...................................... 210
Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions ....................................... 212
Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions ................... 214
Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions ............................. 215
Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Field Descriptions ................................ 216
Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Field Descriptions............................... 217
Port-Write Target Device ID CSR (PW_TGT_ID) Field Descriptions .............................................. 218
SPn_ERR_DET Registers and the Associated Ports................................................................ 219
Port Error Detect CSR n (SPn_ERR_DET) Field Descriptions ..................................................... 219
SPn_RATE_EN Registers and the Associated Ports ................................................................ 221
Port Error Rate Enable CSR n (SPn_RATE_EN) Field Descriptions .............................................. 221
SPn_ERR_ATTR_CAPT_DBG0 Registers and the Associated Ports............................................. 223
Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) Field Descriptions ................. 223
SPn_ERR_CAPT_DBG1 Registers and the Associated Ports ..................................................... 224
Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1) Field Descriptions ...................................... 224
SPn_ERR_CAPT_DBG2 Registers and the Associated Ports ..................................................... 225
Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2) Field Descriptions ...................................... 225
SPn_ERR_CAPT_DBG3 Registers and the Associated Ports ..................................................... 226
Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3) Field Descriptions ...................................... 226
SPn_ERR_CAPT_DBG4 Registers and the Associated Ports ..................................................... 227
Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4) Field Descriptions ...................................... 227
SPn_ERR_RATE Registers and the Associated Ports .............................................................. 228
Port Error Rate CSR n (SPn_ERR_RATE) Field Descriptions ..................................................... 228
SPn_ERR_THRESH Registers and the Associated Ports .......................................................... 229
Port Error Rate Threshold CSR n (SPn_ERR_THRESH) Field Descriptions..................................... 229
Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) Field Descriptions............ 230
Port IP Mode CSR (SP_IP_MODE) Field Descriptions.............................................................. 231
Port IP Prescaler Register (IP_PRESCAL) Field Descriptions ..................................................... 233
179 Port-Write-In Capture CSR Field Descriptions........................................................................ 234
180
181
182
183
184
185
186
187
188
189
SPn_RST_OPT Registers and the Associated Ports ................................................................ 235
Port Reset Option CSR n (SPn_RST_OPT) Field Descriptions .................................................... 235
SPn_CTL_INDEP Registers and the Associated Ports.............................................................. 236
Port Control Independent Register n (SPn_CTL_INDEP) Field Descriptions .................................... 236
SPn_SILENCE_TIMER Registers and the Associated Ports ....................................................... 238
Port Silence Timer n Register (SPn_SILENCE_TIMER) Field Descriptions...................................... 238
SPn_MULT_EVNT_CS Registers and the Associated Ports ....................................................... 239
Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) Field Descriptions ...... 239
SPn_CS_TX Registers and the Associated Ports.................................................................... 240
Port Control Symbol Transmit n Register (SPn_CS_TX) Field Descriptions ..................................... 240
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Preface
SPRUE13A–September 2006
Read This First
About This Manual
This document describes the Serial RapidIO® (SRIO) peripheral on the TMS320TCI648x™ devices.
Notational Conventions
This document uses the following conventions.
•
Hexadecimal numbers are shown with the suffix h. For example, the following number represents 40
hexadecimal (decimal 64): 40h.
•
Registers in this document are shown in figures and described in tables.
–
Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
–
Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000™ devices and related support tools. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
Implementing Serial RapidIO (SRIO) PCB Layout on a TMS320TCI6482 Hardware Design (literature
number SPRAAB0) specifies a complete printed circuit board (PCB) solution for the TCI6482 as well as a
list of compatible SRIO devices showing two DSPs connected via a 4x SRIO link. TI has performed the
simulation and system characterization to ensure all SRIO interface timings in this solution are met;
therefore, no electrical data/timing information is supplied here for this interface.
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) gives an
introduction to the TMS320C62x™ and TMS320C67x™ DSPs, development tools, and third-party support.
TMS320C6000 Programmer's Guide (literature number SPRU198) describes ways to optimize C and
assembly code for the TMS320C6000™ DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301) introduces the Code
Composer Studio™ integrated development environment and software tools.
Code Composer Studio Application Programming Interface Reference Guide (literature number
SPRU321) describes the Code Composer Studio™ application programming interface (API), which allows
you to program custom plug-ins for Code Composer.
TMS320C64x+ Megamodule Reference Guide (literature number SPRU871) describes the
TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct
memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection,
bandwidth management, and the memory and cache.
TMS320TCI648x Bootloader User's Guide(literature number SPRUEC7) describes the features of the
on-chip Bootloader provided with the TMS320TCI648x Digital Signal Processor (DSP). Included are
descriptions of the available boot modes and any interfacing requirements associated with them,
instructions on generating the boot table, and information on the different versions of the Bootloader.
14
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Related Documentation From Texas Instruments
Trademarks
TMS320TCI648x, C6000, TMS320C62x, TMS320C67x, TMS320C6000, Code Composer Studio are
trademarks of Texas Instruments.
RapidIO is a registered trademark of RapidIO Trade Association.
InfiniBand is a trademark of the InfiniBand Trade Association.
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User's Guide
SPRUE13A–September 2006
Serial RapidIO (SRIO)
1
Overview
The RapidIO peripheral used in the TMS320TCI648x is called a serial RapidIO (SRIO). This chapter
describes the general operation of a RapidIO system, how this module is connected to the outside world,
the definitions of terms used within this document, and the features supported and not supported for
SRIO.
1.1 General RapidIO System
RapidIO®is a non-proprietary high-bandwidth system level interconnect. It is a packet-switched
interconnect intended primarily as an intra-system interface for chip-to-chip and board-to-board
communications at Gigabyte-per-second performance levels. Uses for the architecture can be found in
connected microprocessors, memory, and memory mapped I/O devices that operate in networking
equipment, memory subsystems, and general purpose computing. Principle features of RapidIO include:
•
•
•
•
•
•
•
•
Flexible system architecture allowing peer-to-peer communication
Robust communication with error detection features
Frequency and port width scalability
Operation that is not software intensive
High bandwidth interconnect with low overhead
Low pin count
Low power
Low latency
1.1.1
RapidIO Architectural Hierarchy
RapidIO is defined as a 3-layer architectural hierarchy.
•
Logical layer: Specifies the protocols, including packet formats, which are needed by endpoints to
process transactions
•
•
Transport layer: Defines addressing schemes to correctly route information packets within a system
Physical layer: Contains the device level interface information such as the electrical characteristics,
error management data, and basic flow control data
In the RapidIO architecture, a single specification for the transport layer is compatible with differing
16
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Overview
Figure 1. RapidIO Architectural Hierarchy
Logical specification
Globally
shared
Future
logical
spec
I/O
Message
passing
Information necessary for the end point
to process the transaction (i.e., transaction
type, size, physical address)
system
memory
Transport specification
Common
transport
spec
Information to transport packet from end
to end in the system (i.e., routing address)
Physical specification
Future
physical
spec
8/16
1x/4x
Information necessary to move packet
between two physical devices (i.e., electrical
interface, flow control)
LP-LVDS
LP serial
Inter-
Compliance
checklist
operability
specification
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Overview
1.1.2
RapidIO Interconnect Architecture
The interconnect architecture is defined as a packet switched protocol independent of a physical layer
Figure 2. RapidIO Interconnect Architecture
Host Subsystem
I/O Control Subsystem
InfiniBand™ HCA
Memory
Memory
IO
Processor
Control
Processor
ASIC/FPGA
Memory
Host
Processor
Host
Processor
To System Area
Network
RapidIO
Switch
RapidIO to
InfiniBand
Memory
RapidIO
RapidIO
RapidIO
RapidIO
RapidIO
RapidIO
Switch
RapidIO
Switch
Backplane
RapidIO
RapidIO to
PCI Bridge
RapidIO
Switch
RapidIO
Memory
Comm
Processor
Comm
Processor
RapidIO
Memory
PCI
DSP
DSP
DSP
DSP
Legacy
TDM,GMII, Utopia
DSP Farm
Communications Subsystem
PCI Subsystem
(1) InfiniBand™ is a trademark of the InfiniBand Trade Association.
1.1.3
Physical Layer 1x/4x LP-Serial Specification
Currently, there are two physical layer specifications recognized by the RapidIO Trade Association: 8/16
LP-LVDS and 1x/4x LP-Serial. The 8/16 LP-LVDS specification is a point-to-point synchronous clock
sourcing DDR interface. The 1x/4x LP-Serial specification is a point-to-point, AC coupled, clock recovery
interface. The two physical layer specifications are not compatible.
SRIO complies with the 1x/4x LP-Serial specification. The serializer/deserializer (SERDES) technology in
SRIO also aligns with that specification.
The RapidIO Physical Layer 1x/4x LP-Serial Specification currently covers three frequency points: 1.25,
2.5, and 3.125 Gbps. This defines the total bandwidth of each differential pair of I/O signals. An 8-bit/10-bit
encoding scheme ensures ample data transitions for the clock recovery circuits. Due to the 8-bit/10-bit
encoding overhead, the effective data bandwidth per differential pair is 1.0, 2.0, and 2.5 Gbps
respectively. Serial RapidIO only specifies these rates for both the 1x and 4x ports. A 1x port is defined as
1 TX and 1 RX differential pair. A 4x port is a combination of four of these pairs. This document describes
a 4x RapidIO port that can also be configured as four 1x ports, thus providing a scalable interface capable
of supporting a data bandwidth of 1 to 10 Gbps.
Figure 3 shows how to interface two 1x devices and two 4x devices. Each positive transmit data line (TDx)
on one device is connected to a positive receive data line (RDx) on the other device. Likewise, each
negative transmit data line (TDx) is connected to a negative receive data line (RDx).
18
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Overview
Figure 3. Serial RapidIO Device to Device Interface Diagrams
1x Device
TD[0]
1x Device
RD[0]
TD[0]
RD[0]
RD[0]
RD[0]
TD[0]
TD[0]
Serial RapidIO 1x Device to 1x Device Interface Diagram
4x Device
TD[0-3]
4x Device
RD[0-3]
TD[0-3]
RD[0-3]
RD[0-3]
RD[0-3]
TD[0-3]
TD[0-3]
Serial RapidIO 4x Device to 4x Device Interface Diagram
1.2 RapidIO Feature Support in SRIO
Features Supported in SRIO Peripheral:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RapidIO Interconnect Specification V1.2 compliance, Errata 1.2
Physical Layer 1x/4x LP-Serial Specification V1.2 compliance
4x Serial RapidIO with auto-negotiation to 1x port, optional operation for four 1x ports
Integrated clock recovery with TI SERDES
Hardware error handling including Cyclic Redundancy Code (CRC)
Differential CML signaling supporting AC coupling
Support for 1.25, 2.5, and 3.125 Gbps rates
Power-down option for unused ports
Read, write, write with response, streaming write, outgoing Atomic, and maintenance operations
Generates interrupts to the CPU (Doorbell packets and internal scheduling)
Support for 8-bit and 16-bit device ID
Support for receiving 34-bit addresses
Support for generating 34-bit, 50-bit, and 66-bit addresses
Support for the following data sizes: byte, half-word, word, double-word
Big endian data transfers
Direct I/O transfers
Message passing transfers
Data payloads of up to 256 bytes
Single messages consisting of up to 16 packets
Elastic storage FIFOs for clock domain handoff
Short run and long run compliance
Support for Error Management Extensions
Support for Congestion Control Extensions
Support for one multi-cast ID
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Overview
Features Not Supported:
•
•
•
•
•
Compliance with the Global Shared Memory specification (GSM)
8/16 LP-LVDS compatible
Destination support of RapidIO Atomic Operations
Simultaneous mixing of frequencies between 1x ports (all ports must be the same frequency)
Target atomic operations (including increment, decrement, test-and-swap, set, and clear) for internal
L2 memory and registers
1.3 Standards
The SRIO peripheral is compliant to V1.2 of the RapidIO Interconnect Specification and V1.2 of the
RapidIO Physical Layer 1x/4x LP-Serial Specification. These and the various associated documents listed
herein can be found at the official RapidIO website: www.RapidIO.org.
1.4 External Devices Requirements
SRIO provides a seamless interface to all devices which are compliant to V1.2 of the RapidIO Physical
Layer 1x/4x LP-Serial Specification. This includes ASIC, microprocessor, DSP, and switch fabric devices
from multiple vendors. Compliance to the specification can be verified with bus-functional models available
through the RapidIO Trade Association, as well as test suites currently available for licensing.
1.5 TI Devices Supported By This Document
Table 1. TI Devices Supported By This Document
Number of
DSP Cores (CPUs)
Number of
Ports
Number of
Lanes
SRIO Module
Frequency
Device
Configurations
TMS320TCI6482
1
4
4
1x/4x, 1x/1x
DSP frequency ÷ 4
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SRIO Functional Description
2
SRIO Functional Description
2.1 Overview
2.1.1
Peripheral Data Flow
This peripheral is designed to be an externally driven slave module that is capable of acting as a master in
the DSP system. This means that an external device can push (burst write) data to the DSP as needed,
without having to generate an interrupt to the CPU or without relying on the DSP EDMA. This has several
benefits. It cuts down on the total number of interrupts, it reduces handshaking (latency) associated with
read-only peripherals, and it frees up the EDMA for other tasks.
SRIO specifies data packets with payloads up to 256 bytes. Many times, transactions will span across
multiple packets. RapidIO specifies a maximum of 16 transactions per message. Although a request is
generated for each packet transaction so that the DMA can transfer the data to L2 memory, an interrupt is
only generated after the final packet of the message. This interrupt notifies the CPU that data is available
in L2 Memory for processing.
As an endpoint device, the peripheral accepts packets based on the destination ID. Two options exist for
packet acceptance and are mode selectable. The first option is to only accept packets whose DestIDs
match the local deviceID in 0x0080. This provides a level of security. The second option is is system
multicast operation. When multicast is enabled in SP_IP_MODE (offset 12004h) bit 5, incoming packets
matching the deviceID in the registers shown in are accepted.
Table 2. Registers Checked for Multicast DeviceID
Registers Checked For Multicast DeviceID
Device
Name
Address Offset
0080h
TMS320TCI6482
Local DeviceID Register
Multicast DeviceID Register
0084h
Data flow through the peripheral can be explained using the high-level block diagram shown in Figure 4.
High-speed data enters from the device pins into the RX block of the SERDES macro. The RX block is a
differential receiver expecting a minimum of 175mV peak-to-peak differential input voltage (Vid). Level
shifting is performed in the RX block, such that the output is single ended CMOS. The serial data is then
fed to the SERDES clock recovery block. The sole purpose of this block is to extract a clock signal from
the data stream. To do this, a low-frequency reference clock is required. Typically, this clock comes from
an off-chip stable crystal oscillator and is a LVDS device input separate to the SERDES. This clock is
distributed to the SERDES PLL block which multiplies that frequency up to that of the data rate. Multiple
high-speed clock phases are created and routed to the clock recovery blocks. The clock recovery blocks
further interpolate between these clocks to provide maximum Unit Interval (UI) resolution on the recovered
clock. The clock recovery block samples the incoming data and monitors the relative positions of the data
edges. With this information, it can provide the data and a center-aligned clock to the S2P block. The S2P
block uses the newly recovered clock to de-multiplex the data into 10-bit words. At this point, the data
leaves the SERDES macro at 1/10th the pin data rate, accompanied by an aligned byte clock.
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SRIO Functional Description
Figure 4. SRIO Peripheral Block Diagram
1.25 to 3.125 Gbps
differential data
SERDES
10b
S2P Clk
Clock
recovery
8b/10b 8b
decode
RX
FIFO
FIFO
FIFO
FIFO
Capability
registers
10b
S2P Clk
Clock
recovery
8b/10b 8b
decode
RX
RX
10b
S2P Clk
Clock
recovery
8b/10b 8b
decode
10b
S2P Clk
Clock
recovery
8b/10b 8b
decode
RX
DMA
bus
System
clock
Control
PLL
10b
Clk
8b/10b 8b
coding
TX P2S
FIFO
FIFO
FIFO
FIFO
10b
Clk
8b/10b 8b
coding
TX P2S
TX P2S
10b
Clk
8b/10b 8b
coding
Command
and status
registers
10b
Clk
8b/10b 8b
coding
TX P2S
Clock domain 3
Clock domain 2
Clock domain 1
Within the physical layer, the data next goes to the 8-bit/10-bit (8b/10b) decode block. 8b/10b encoding is
used by RapidIO to ensure adequate data transitions for the clock recovery circuits. Here the 20%
encoding overhead is removed as the 10-bit data is decoded to the raw 8-bit data. At this point, the
recovered byte clock is still being used.
The next step is clock synchronization and data alignment. These functions are handled by the FIFO and
lane de-skewing blocks. In the RapidIO Interconnect Specification, a "lane" is one serial differential pair.
The FIFO provides an elastic store mechanism used to hand off between the recovered clock domains
and a common system clock. After the FIFO, the four lanes are synchronized in frequency and phase,
whether 1X or 4X mode is being used. The FIFO is 8 words deep. The lane de-skew is only meaningful in
the 4X mode, where it aligns each channel’s word boundaries, such that the resulting 32-bit word is
correctly aligned.
The CRC error detection block keeps a running tally of the incoming data and computes the expected
CRC value for the 1X or 4X mode. The expected value is compared against the CRC value at the end of
the received packet.
After the packet reaches the logical layer, the packet fields are decoded and the payload is buffered.
Depending on the type of received packet, the packet routing is handled by functional blocks which control
the DMA access.
2.1.2
SRIO Packets
The SRIO data stream consists of data fields pertaining to the logical layer, the transport layer, and the
physical layer.
•
•
The logical layer consists of the header (defining the type of access) and the payload (if present).
The transport layer is partially dependent on the physical topology in the system, and consists of
source and destination IDs for the sending and receiving devices.
•
The physical layer is dependent on the physical interface (i.e., serial versus parallel RapidIO) and
includes priority, acknowledgment, and error checking fields.
2.1.2.1
Operation Sequence
SRIO transactions are based on request and response packets. Packets are the communication element
between endpoint devices in the system. A master or initiator generates a request packet which is
transmitted to a target. The target then generates a response packet back to the initiator to complete the
transaction.
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SRIO Functional Description
SRIO endpoints are typically not connected directly to each other but instead have intervening connection
fabric devices. Control symbols are used to manage the flow of transactions in the SRIO physical
interconnect. Control symbols are used for packet acknowledgment, flow control information, and
Figure 5. Operation Sequence
Initiator
Operation
Issued By
Master
Operation
Completed for
Master
Request
Packet Issued
Acknowledge
Symbol
Fabric
Response
Packet
Forwarded
Acknowledge
Symbol
Acknowledge
Symbol
Request Packet
Forwarded
Target
Response Packet
Issued
Acknowledge
Symbol
Target
Completes
Operation
2.1.2.2
Example Packet – Streaming Write
An example packet is shown as two data streams in Figure 6. The first is for payload sizes of 80 bytes or
less, while the second applies to payload sizes of 80 to 256 bytes. SRIO packets must have a length that
is an even integer of 32 bits. If the combination of physical, logical and transport layers has a length that is
an integer of 16 bits, a 16-bit pad of value 0000h is added to the end of the packet, after the CRC (not
shown). Bit fields that are defined as reserved are assigned to logic 0s when generated and ignored when
received. All request and response packet formats are described in the RapidIO Input/Output Logical
Specification and MIessage Passing Logical Specification.
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SRIO Functional Description
Figure 6. 1x/4x RapidIO Packet Data Stream (Streaming-Write Class)
n*64+80
PHY
LOG
LOG
TRA
PHY
16
TRA
10
2
4
16
n*64+32
PHY = Physical layer
TRA = Transport layer
LOG = Logical layer
...
xamsbs
2
double-word 0 double-word 1
double-word n-2 double-word n-1 CRC
64 64 16
acklD rsv
tt ftype
rsrv
prio
2
destID
8
address
29
sourcelD
8
5
3
2
4
1
64
64
(n-4)*64
n*64+96
PHY
TRA
2
LOG
TRA
LOG
PHY
16
LOG
PHY
16
10
4
16
9
*
6
4
+
32
(n-9)*64
prio tt ftype
acklD rsv
destID sourcelD address rsrv xamsbs double-word 0 double-word 1
29 64 64
...
double-word 8 double-word 9 CRC double-word 10
64 64 16 64
double-word 11
64
...
double-word n-2 double-word n-1 CRC
64 64 16
5
3
2
2
4
8
8
1
2
5*64
(n-13)*64
The device ID, being an 8-bit field, will address up to 256 nodes in the system. If 16-bit addresses were
used, the system could accommodate up to 64k nodes.
The data stream includes a Cyclic Redundancy Code (CRC) field to ensure the data was correctly
received. The CRC value protects the entire packet except the ackID and one bit of the reserved PHY
field. The peripheral checks the CRC automatically in hardware. If the CRC is correct, a Packet-Accepted
control symbol is sent by the receiving device. If the CRC is incorrect, a Packet-Not-Accepted control
symbol is sent so that transmission may be retried.
2.1.2.3
Control Symbols
Control symbols are physical layer message elements used to manage link maintenance, packet
delimiting, packet acknowledgment, error reporting, and error recovery. All transmitted data packets are
delimited by start-of-packet and end-of-packet delimiters. SRIO control symbols are 24 bits long and are
convey the status of the port transmitting the symbol, and stype1 symbols are requests to the receiving
port or transmission delimiters. They have the following format, which is detailed in Section 3 of the
RapidIO Physical Layer 1x/4x LP-Serial Specification.
Figure 7. Serial RapidIO Control Symbol Format
Delimiter
1st Byte
2nd Byte
3rd Byte
SC or PD
8
stype0
Parameter0 parameter1
stype1
cmd
3
CRC
5
3
5
5
3
Control symbols are delimited by special characters at the beginning of the symbol. If the control symbol
contains a packet delimiter(start-of-packet, end-of-packet, etc.), the special character PD (K28.3) is used.
If the control symbol does not contain a packet delimiter, the special character SC (K28.0) is used. This
use of special characters provides an early warning of the contents of the control symbol. The CRC does
not protect the special characters, but an illegal or invalid character is recognized and flagged as
Packet-Not-Accepted. Since control symbols are known length, they do not need end delimiters.
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SRIO Functional Description
The type of received packet determines how the packet routing is handled. Reserved or undefined packet
types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous
allocation of resources to them. Unsupported packet types are responded to with an error response
2.1.2.4
SRIO Packet Type
The type of SRIO packet is determined by the combination of Ftype and Ttype fields in the packet. Table 3
lists all supported combinations of Ftype/Ttype and the corresponding decoded actions on the packets.
Table 3. Packet Types
Ftype
Ttype
Packet Type
Ftype = 0
Ftype = 2
Ttype = don't care
Ttype = 0100b
Ttype = 1100b
Ttype = 1101b
Ttype = 1110b
Ttype = 1111b
Ttype = others
Ttype = 0100b
Ttype = 0101b
Ttype = 1110b
Ttype = others
Ttype = don't care
Ttype = don't care
Ttype = 0000b
Ttype = 0001b
Ttype = 0010b
Ttype = 0011b
Ttype = 0100b
Ttype = others
Ttype = don't care
Ttype = don't care
Ttype = 0000b
Ttype = 0001b
Ttype = 1000b
Ttype = other
NREAD
Atomic increment
Atomic decrement
Atomic set
Atomic clear
Ftype = 5
NWRITE
NWRITE_R
Atomic test and swap
Ftype = 6
Ftype = 7
Ftype = 8
SWRITE
Congestion control
Maintenance read
Maintenance write
Maintenance read response
Maintenance write response
Maintenance port-write
Ftype = 10
Ftype = 11
Ftype = 13
Doorbell
Message
Response(+Doorbell Resp)
Message Response
Response w/payload
Undefined Ftypes: 1,3,4,9,12,14,15
2.2 SRIO Pins
The SRIO device pins are high-speed differential signals based on Current-Mode Logic (CML) switching
levels. The transmit and receive buffers are self-contained within the clock recovery blocks. The reference
clock input is not incorporated into the SERDES macro. It uses a differential input buffer that is compatible
with the LVDS and LVPECL interfaces available from crystal oscillator manufacturers. Table 4 describes
the device pins for the SRIO peripheral.
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SRIO Functional Description
Table 4. Pin Description
Pin
Signal
Pin Name
Count
Direction
Description
RIOTX3/ RIOTX3
2
2
2
2
2
2
2
2
2
Output
Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins. Most significant bits in 1
port 4X device. Used in 4 port 1X device.
RIOTX2/ RIOTX2
RIOTX1/ RIOTX1
RIOTX0/ RIOTX0
RIORX3/ RIORX3
RIORX2/ RIORX2
RIORX1/ RIORX1
RIORX0/ RIORX0
RIOCLK/ RIOCLK
Output
Output
Output
Input
Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins. Bit used in 4 port 1x
device and 1 port 4X device.
Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins. Bit used in 4 port 1x
device and 1 port 4X device.
Transmit Data – Differential point-to-point unidirectional bus. Transmits
packet data to a receiving device’s RX pins. Bit used in 1 port 1X
device, 4 port 1x device, and 1 port 4X device.
Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins. Most significant bits in
1 port 4X device. Used in 4 port 1X device.
Input
Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins. Bit used in 4 port 1x
device and 1 port 4X device.
Input
Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins. Bit used in 4 port 1x
device and 1 port 4X device.
Input
Receive Data – Differential point-to-point unidirectional bus. Receives
packet data for a transmitting device’s TX pins. Bit used in 1 port 1X
device, 4 port 1x device, and 1 port 4X device.
Input
Reference Clock Input Buffer for peripheral clock recovery circuitry.
2.3 Functional Operation
2.3.1
Component Block Diagram
Figure 8 shows a component block diagram of the SRIO peripheral. The load/store unit (LSU) controls the
transmission of direct I/O packets, and the memory access unit (MAU) controls the reception of direct I/O
packets. The LSU also controls the transmission of maintenance packets. Message packets are
transmitted by the TXU and received by the RXU. These four units use the internal DMA to communicate
with internal memory, and they use buffers and receive/transmit ports to communicate with external
devices. Serializer/deserializer (SERDES) macros support the ports by performing the parallel-to-serial
coding for transmission and serial-to-parallel decoding for reception.
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SRIO Functional Description
Figure 8. SRIO Component Block Diagram
DMA bus
Load/Store
units (LSUs)
TX direct I/O
Memory
TXU
access unit
(MAU)
RXU
Messaging
Messaging
RX direct I/O
Maintenance
4.5 KB TX
4.5 KB RX
shared
Queue
handle
shared
buffer
buffer
TX buffering
32 x 276B
Logical
layer
Transaction
mapping
8 buffers per 1X port - all priorities
32 buffers per 4X port - 8 per priority
buffers
UDI
Port 0
Port 1
Port 2
Port 3
Physical
layer
8 x 276 TX
8 x 276 RX
8 x 276 TX
8 x 276 RX
8 x 276 TX
8 x 276 RX
8 x 276 TX
8 x 276 RX
buffers
4x mode
data path
SERDES 0
SERDES 1
SERDES 2
SERDES 3
SERDES
differential
signals
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SRIO Functional Description
2.3.2
SERDES Macro and its Configurations
SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use of
TI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable. The same peripheral can
be used for all three frequency nodes specified in V1.2 of the RapidIO Interconnect Specification (1.25,
2.5, and 3.125 Gbps). This allows you to design to only one protocol throughout the system and
selectively choose the bandwidth, thus eliminating the need for user’s proprietary protocols in many
instances, and providing a faster design turn and production ramp. Since this interface is serial, the
application space is not limited to a single board. It will propagate into backplane applications as well.
Integration of these macros on an ASIC or DSP allows you to reduce the number of discrete components
on the board and eliminates the need for bus driver chips.
Additionally, there are some valuable features built into TI SERDES. System optimization can be uniquely
managed to meet individual customer applications. For example, control registers within the SERDES
allow you to adjust the TX differential output voltage (Vod) on a per driver basis. This allows power
savings on short trace links (on the same board) by reducing the TX swing. Similarly, data edge rates can
be adjusted through the control registers to help reduce any EMI affects. Unused links can be individually
powered down without affecting the working links.
The SERDES macro is a self-contained macro which includes transmitter (TX), receiver (RX),
phase-locked-loop (PLL), clock recovery, serial-to-parallel (S2P), and parallel-to-serial (P2S) blocks. The
internal PLL multiplies a user-supplied reference clock. All loop filter components of the PLL are onchip.
Likewise, the differential TX and RX buffers contain on-chip termination resistors. The only off-chip
component requirement is for DC blocking capacitors.
2.3.2.1
Enabling the PLL
The Physical layer SERDES has a built-in PLL, which is used for the clock recovery circuitry. The PLL is
responsible for clock multiplication of a slow speed reference clock. This reference clock has no timing
relationship to the serial data and is asynchronous to any CPU system clock. The multiplied high-speed
clock is only routed within the SERDES block; it is not distributed to the remaining blocks of the peripheral,
nor is it a boundary signal to the core of the device. It is extremely important to have a good quality
reference clock, and to isolate it and the PLL from all noise sources. Since RapidIO requires 8-bit/10-bit
encoded data, the 8-bit mode of the SERDES PLL is not be used.
The SERDES macro is configured with the register SERDES_CFG0_CNTL, SERDES_CFGRXn_CNTL,
and SERDES_CFGTXn_CNTL, where n is the number of the macro. To enable the internal PLL, the
necessary to allow 1µs for the regulator to stabilize. Thereafter, the PLL will take no longer than 200
reference clock cycles to lock to the required frequency, provided RIOCLK and RIOCLK are stable.
Registers SERDES_CFG1_CNTL, SERDES_CFG2_CNTL, and SERDES_CFG3_CNTL are not used.
Figure 9. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL)
31
15
16
Reserved
R-0000h
10
9
8
7
6
5
1
0
Reserved
R-00h
LB
Reserved
R-0
MPY
ENPLL
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
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Table 5. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions
Bit
31–10
9–8
Field
Value
Description
Reserved
LB
0000h
Reserved
Loop bandwidth. Specify loop bandwidth settings. Jitter on the reference clock will
degrade both the transmit eye and receiver jitter tolerance thereby impairing system
performance. Performance of the integrated PLL can be optimized according to the
jitter characteristics of the reference clock via the LB field.
00b
Frequency dependent bandwidth. The PLL bandwidth is set to a twelfth of the
frequency of RIOCLK/RIOCLK. This setting is suitable for most systems that input the
reference clock via a low jitter input cell, and is required for standards compliance
01b
10b
Reserved
Low bandwidth. The PLL bandwidth is set to a twentieth of the frequency of
RIOCLK/RIOCLK, or 3MHz (whichever is larger). In systems where the reference
clock is directly input via a low jitter input cell, but is of lower quality, this setting may
offer better performance. It will reduce the amount of reference clock jitter transferred
through the PLL. However, it also increases the susceptibility to loop noise generated
within the PLL itself. It is difficult to predict whether the improvement in the former will
more than offset the degradation in the latter.
11b
00h
High bandwidth. The PLL bandwidth is set to a eighth of the frequency of
RIOCLK/RIOCLK. This is the setting appropriate for systems where the reference
clock is cleaned through an ultra low jitter LC-based PLL. Standards compliance will
be achieved even if the reference clock input to the cleaner PLL is outside the
specification for the standard.
7–6
5–1
Reserved
MPY
Reserved
PLL multiply. Select PLL multiply factors between 4 and 60.
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01111b
1xxxxb
4x
5x
6x
Reserved
8x
10x
12x
12.5x
15x
20x
25x
Reserved
Reserved
Reserved
Reserved
Enable PLL
PLL disabled
PLL enabled
0
ENPLL
0
1
Based on the MPY value, the line rate versus PLL output clock frequency can be calculated. This is
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Table 6. Line Rate versus PLL Output Clock Frequency
Rate
Full
Line Rate
x Gbps
PLL Output Frequency
0.5x GHz
RATESCALE
0.5
1
Half
x Gbps
x GHz
Quarter
x Gbps
2x GHz
2
RIOCLK and RIOCLKFREQ
=
LINERATE × RATESCALE
MPY
The rate is defined by the RATE bits of the SERDES_CFGRXn_CNTL register and the
SERDES_CFGTXn_CNTL register, respectively.
The primary operating frequency of the SERDES macro is determined by the reference clock frequency
and PLL multiplication factor. However, to support lower frequency applications, each receiver and
transmitter can also be configured to operate at a half or quarter of this rate via the RATE bits of the
Table 7. Effect of the RATE Bits
RATE
00b
Description
Full rate. Two data samples taken per PLL output clock cycle.
Half rate. One data sample taken per PLL output clock cycle.
Quarter rate. One data sample taken every two PLL output clock cycles.
Reserved.
01b
10b
11b
Table 8. Frequency Range versus MPY Value
RIOCLK and RIOCLK
Range (MHz)
250 - 425
Line Rate Range (Gbps)
MPY
4x
Full
Half
Quarter
2 - 3.4
1 - 1.7
0.5 - 0.85
5x
200 - 425
2 - 4.25
2 - 4.25
2 - 4.25
2 - 4.25
2 - 4.25
2 - 4.25
2 - 4.25
2 - 4.25
2 - 4.25
1 - 2.125
1 - 2.125
1 - 2.125
1 - 2.125
1 - 2.125
1 - 2.125
1 - 2.125
1 - 2.125
1 - 2.125
0.5 - 1.0625
0.5 - 1.0625
0.5 - 1.0625
0.5 - 1.0625
0.5 - 1.0625
0.5 - 1.0625
0.5 - 1.0625
0.5 - 1.0625
0.5 - 1.0625
6x
167 - 354.167
125 - 265.625
100 - 212.5
83.33 - 177.08
80 - 170
8x
10x
12x
12.5x
15x
20x
25x
66.67 - 141.67
50 - 106.25
40 - 85
2.3.2.2
Enabling the Receiver
To enable a receiver for deserialization, the ENRX bit of the associated SERDES_CFGRXn_CNTL
When ENRX is low, all digital circuitry within the receiver will be disabled, and clocks will be gated off. All
current sources within the receiver will be fully powered down, with the exception of those associated with
the loss of signal detector and IEEE1149.6 boundary scan comparators. Loss of signal power down is
independently controlled via the LOS bits of SERDES_CFGRXn_CNTL. When enabled, the differential
signal amplitude of the received signal is monitored. Whenever loss of signal is detected, the clock
recovery algorithm is frozen to prevent the phase and frequency of the recovered clock from being
modified by low level signal noise.
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The clock recovery algorithms listed in the CDR bits operate to adjust the clocks used to sample the
received message so that the data samples are taken midway between data transitions. The second order
algorithm can be optionally disabled, and both can be configured to optimize their dynamics. Both
algorithms use the same basic technique for determining whether the sampling clock is ideally placed, and
if not whether it needs to be moved earlier or later. When two contiguous data samples are different, the
phase sample between the two is examined. Eight data samples and nine phase samples are taken with
each result counted as a vote to move the sample point either earlier or later. These eight data bits
constitute the voting window. The eight votes are then counted, and an action to adjust the position of the
sampling clock occurs if there is a majority of early or late votes. The first order algorithm makes a single
phase adjustment per majority vote. The second order algorithm acts repeatedly according to the net
difference between early and late majority votes, thereby adjusting for the rate of change of phase.
Setting the ALIGN field to 01 enables alignment to the K28 comma symbols included in the 8b:10b data
encoding scheme defined by the IEEE and employed by numerous transmission standards. For systems
which cannot use comma based symbol alignment, the single bit alignment jog capability provides a
means to control the symbol realignment features of the receiver directly from logic implemented in the
ASIC core. This logic can be designed to support whatever alignment detection protocol is required.
The EQ bits allow for enabling and configuring the adaptive equalizer incorporated in all of the receive
channels, which can compensate for channel insertion loss by attenuating the low frequency components
with respect to the high frequency components of the signal, thereby reducing inter-symbol interference.
Above the zero frequency, the gain increases at 6dB/octave until it reaches the high frequency gain. When
enabled, the receiver equalization logic analyzes data patterns and transition times to determine whether
the low frequency gain of the equalizer should be increased or decreased. For the fully adaptive setting
(EQ = 0001), if the low frequency gain reaches the minimum value, the zero frequency is then reduced.
Likewise, if it reaches the maximum value, the zero frequency is then increased. This decision logic is
implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that
results reduces the probability of incorrect decisions but allows the equalizer to compensate for the
relatively stable response of the channel.
•
•
•
No adaptive equalization. The equalizer provides a flat response at the maximum gain. This setting
may be appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than
frequency dependent loss.
Fully adaptive equalization. Both the low frequency gain and zero position of the equalizer are
determined algorithmically by analysing the data patterns and transition positions in the received data.
This setting should be used for most applications.
Partially adaptive equalisation. The low frequency gain of the equalizer is determined algorithmically by
analysing the data patterns and transition positions in the received data. The zero position is fixed in
one of eight zero positions. For any given application, the optimal setting is a function of the loss
characteristics of the channel and the spectral density of the signal as well as the data rate, which
means it is not possible to identify the best setting by data rate alone, although generally speaking, the
lower the line rate, the lower the zero frequency that will be required.
Figure 10. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)
31
15
26 25
24
23
22
19 18
16
Reserved
(write 0s)
Reserved
R-0
—
EQ
CDR
R/W-0
1
R/W-0
8
R-0
R/W-0
14 13
12
11
—
10
7
6
5
4
2
0
TERM
(write 001b)
—
(write 0)
LOS
ALIGN
R/W-0
INVPAIR
R/W-0
RATE
R/W-0
BUSWIDTH
R/W-0
ENRX
R/W-0
R/W-0
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field
Descriptions
Bit
Field
Value
Description
31–26
Reserved
000000b
These read-only bits return 0s when read.
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Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field
Descriptions (continued)
Bit
25–24
23
Field
Value
00b
0
Description
Reserved
Reserved
EQ
Always write 0s to these reserved bits.
This read-only bit returns 0 when read.
22–19
0000b–1111b Equalizer. Enables and configures the adaptive equalizer to compensate for loss
18–16
CDR
Clock/data recovery. Configures the clock/data recovery algorithm.
000b
001b
First order. Phase offset tracking up to ±488 ppm.
Second order. Highest precision frequency offset matching but poorest response
to changes in frequency offset, and longest lock time. Suitable for use in systems
with fixed frequency offset.
010b
011b
Second order. Medium precision frequency offset matching, frequency offset
change response, and lock time.
Second order. Best response to changes in frequency offset and fastest lock time,
but lowest precision frequency offset matching. Suitable for use in systems with
spread spectrum clocking.
100b
101b
110b
111b
First order with fast lock. Phase offset tracking up to ±1953 ppm in the presence of
..10101010.. training pattern, and ±448 ppm otherwise.
Second order with fast lock. As per setting 001, but with improved response to
changes in frequency offset when not close to lock.
Second order with fast lock. As per setting 010, but with improved response to
changes in frequency offset when not close to lock.
Second order with fast lock. As per setting 011, but with improved response to
changes in frequency offset when not close to lock.
15–14
LOS
Loss of signal. Enables loss of signal detection with 2 selectable thresholds.
Disabled. Loss of signal detection disabled.
00b
01b
High threshold. Loss of signal detection threshold in the range 85 to 195mVdfpp
.
This setting is suitable for Infiniband.
10b
11b
Low threshold. Loss of signal detection threshold in the range 65 to 175mVdfpp
This setting is suitable for PCI-E and S-ATA.
.
Reserved
13–12
ALIGN
Symbol alignment. Enables internal or external symbol alignment.
00b
01b
10b
Alignment disabled. No symbol alignment will be performed while this setting is
selected, or when switching to this selection from another.
Comma alignment enabled. Symbol alignment will be performed whenever a
misaligned comma symbol is received.
Alignment jog. The symbol alignment will be adjusted by one bit position when this
mode is selected (that is, the ALIGN value changes from 0xb to 1xb).
11b
0
Reserved
11
Reserved
TERM
This read-only bit returns 0 when read.
10–8
001b
Input termination. The only valid value for this field is 001b; all other values are
reserved. The value 001b sets the common point to 0.8 VDDT and supports AC
coupled systems using CML transmitters. The transmitter has no effect on the
receiver common mode, which is set to optimize the input sensitivity of the
receiver. Common mode termination is via a 50 pF capacitor to VSSA.
7
INVPAIR
RATE
Invert polarity. Inverts polarity of RIORXn and RIORXn.
Normal polarity. RIORXn is considered to be positive data and RIORXn negative.
Inverted polarity. RIORXn is considered to be negative data and RIORXn positive.
Operating rate. Selects full, half, or quarter rate operation.
Full rate. Two data samples taken per PLL output clock cycle.
Half rate. One data sample taken per PLL output clock cycle.
Quarter rate. One data sample taken every two PLL output clock cycles.
Reserved
0
1
6–5
00b
01b
10b
11b
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Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field
Descriptions (continued)
Bit
Field
Value
Description
4–2
BUSWIDTH
000b
Bus width. Always write 000b to this field, to indicate a 10-bit-wide parallel bus to
the bus.
1
0
Reserved
ENRX
0
Always write 0 to this reserved bit.
Enable receiver
0
1
Disable this receiver.
Enable this receiver.
Table 10. EQ Bits
CFGRX[22–19]
Low Freq Gain
Maximum
Zero Freq (at e28 (min))
0000b
0001b
001xb
01xxb
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
–
Adaptive
Adaptive
Reserved
Reserved
Adaptive
1084MHz
805MHz
573MHz
402MHz
304MHz
216MHz
156MHz
135MHz
2.3.2.3
Enabling the Transmitter
To enable a transmitter for serialization, the ENTX bit of the associated SERDES_CFGTXn_CNTL
registers (110h–10Ch) must be set high. When ENTX is low, all digital circuitry within the transmitter will
be disabled, and clocks will be gated off, with the exception of the transmit clock (TXBCLK[n]) output,
which will continue to operate normally. All current sources within the transmitter will be fully powered
down, with the exception of the current mode logic (CML) driver, which will remain powered up if boundary
Figure 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL)
31
15
17
16
Reserved
R-0
ENFTP
R/W-1
12 11
9
8
7
6
5
4
2
1
0
DE
SWING
R/W-0
CM
INVPAIR
R/W-0
RATE
R/W-0
BUSWIDTH
R/W-0
(write 0) ENTX
R/W-0 R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field
Descriptions
Bit
31–17 Reserved
16 ENFTP
Field
Value
Description
0
1
These read-only bits return 0s when read.
Enables fixed phase relationship of transmit input clock with respect to transmit output
clock. The only valid value for this field is 1b; all other values are reserved.
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SRIO Functional Description
Table 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field
Descriptions (continued)
Bit
Field
Value
Description
15–12 DE
0000b–1111b
De-emphasis. Selects one of 15 output de-emphasis settings from 4.76 to 71.42%.
De-emphasis provides a means to compensate for high frequency attenuation in the
attached media. It causes the output amplitude to be smaller for bits which are not
11–9 SWING
000b–111b
Output swing. Selects one of 8 outputs amplitude settings between 125 and
8
CM
Common mode. Adjusts the common mode to suit the termination at the attached
receiver. For output swing settings above 750mV, this reduced common mode can
cause distortion of the waveform. Under these conditions, this bit should be set high to
offset some of the common mode reduction.
0
1
Normal common mode. Common mode not adjusted.
Raised common mode. Common mode raised by 5% of difference between RIOTXn
and RIOTXn
7
INVPAIR
RATE
Invert polarity. Inverts the polarity of RIOTXn and RIOTXn.
Normal polarity. RIOTXn is considered to be positive data and RIOTXn negative.
Inverted polarity. RIOTXn is considered to be negative data and RIOTXn positive.
Operating rate. Selects full, half, or quarter rate operation.
Full rate. Two data samples taken per PLL output clock cycle.
Half rate. One data sample taken per PLL output clock cycle.
Quarter rate. One data sample taken every two PLL output clock cycles.
Reserved
0
1
6–5
00b
01b
10b
11b
000b
4–2
BUSWIDTH
Bus width. Always write 000b to this field, to indicate a 10-bit-wide parallel bus to the
1
0
Reserved
ENTX
0
Always write 0 to this reserved bit.
Enable transmitter
0
1
Disable this transmitter.
Enable this transmitter.
Table 12. DE Bits of SERDES_CFGTXn_CNTL
Amplitude Reduction
DE Bits
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
%
dB
0
0
4.76
–0.42
–0.87
–1.34
–1.83
–2.36
–2.92
–3.52
–4.16
–4.86
–5.61
–6.44
–7.35
–8.38
–9.54
–10.87
9.52
14.28
19.04
23.8
28.56
33.32
38.08
42.85
47.61
52.38
57.14
61.9
66.66
71.42
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Table 13. SWING Bits of SERDES_CFGTXn_CNTL
SWING Bits
000b
Amplitude (mVdfpp)
125
250
001b
010b
500
011b
625
100b
750
101b
1000
1125
1250
110b
111b
2.3.2.4
SERDES Configuration Example
//full sample rate at 3.125 Gbps
//SERDES reference clock (RIOCLK) 125 MHz
//MPY = 12.5
125MHz = ((3.125 Gbps)(.5))/MPY
SRIO_REGS->SERDES_CFG0_CNTL = 0x0000000F;
SRIO_REGS->SERDES_CFG1_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFG2_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFG3_CNTL = 0x00000000;
// SRIO_REGS->SERDES_CFG1_CNTL not used
// SRIO_REGS->SERDES_CFG2_CNTL not used
// SRIO_REGS->SERDES_CFG3_CNTL not used
//four ports enabled
SRIO_REGS->SERDES_CFGRX0_CNTL
SRIO_REGS->SERDES_CFGRX1_CNTL
SRIO_REGS->SERDES_CFGRX2_CNTL
SRIO_REGS->SERDES_CFGRX3_CNTL
SRIO_REGS->SERDES_CFGTX0_CNTL
SRIO_REGS->SERDES_CFGTX1_CNTL
SRIO_REGS->SERDES_CFGTX2_CNTL
SRIO_REGS->SERDES_CFGTX3_CNTL
= 0x00081101 ;
= 0x00081101 ;
= 0x00081101 ;
= 0x00081101 ;
= 0x00010801 ;
= 0x00010801 ;
= 0x00010801 ;
= 0x00010801 ;
2.3.3
Direct I/O Operation
The direct I/O (Load/Store) module serves as the source of all outgoing direct I/O packets. With direct I/O,
the RapidIO packet contains the specific address where the data should be stored or read in the
destination device. Direct I/O requires that a RapidIO source device keep a local table of addresses for
memory within the destination device. Once these tables are established, the RapidIO source controller
uses this data to compute the destination address and insert it into the packet header. The RapidIO
destination peripheral extracts the destination address from the received packet header and transfers the
payload to memory via the DMA.
When a CPU wants to send data from memory to an external processing element (PE) or read data from
an external PE, it provides the RIO peripheral vital information about the transfer such as DSP memory
address, target device ID, target destination address, packet priority, etc. Essentially, a means must exist
to fill all the header fields of the RapidIO packet. The Load/Store module provides a mechanism to handle
this information exchange via a set of MMRs acting as transfer descriptors. These registers, shown in
LSUn_REG5, a data transfer is initiated for either an NREAD, NWRITE, NWRITE_R, SWRITE, ATOMIC,
or MAINTENANCE RapidIO transaction. Some fields, such as the RapidIO srcTID/targetTID field, are
assigned by hardware and do not have a corresponding command register field.
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Figure 12. Load/Store Registers for RapidIO (Address Offset: LSU1 400h–418h, LSU2 420h–438h, LSU3
440h–458h, LSU4 460h-478h)
LSUn_REG0
RapidIO Address MSB
RapidIO Address LSB/Config_offset
DSP Address
Control
Control
Control
0
0
0
0
31
31
31
31
LSUn_REG1
LSUn_REG2
LSUn_REG3
RSV
Byte_count
Control
Control
12 11
LSUn_REG4 OutPortID Priority xambs ID Size DestID
RSV
7
Interrupt Req
0
31
31
31
30 29 28 27 26 25 24 23
8
1
LSUn_REG5
Drbll Info
RSV
Hop Count
Packet Type
7
Command
Status
16 15
8
0
LSUn_REG6
Completion Code
Bsy
0
5
4
1
The mapping of LSU register fields to RapidIO packet header fields is explained in Table 14 and Table 15.
Table 14. LSU Control/Command Register Fields
LSU Register Field
RapidIO Packet Header Field
RapidIO Address MSB
32-bit Extended Address Fields – Packet Types 2, 5, and 6
RapidIO Address
LSB/Config_offset
1. 32-bit Address– Packet Types 2, 5, and 6 (Will be used in conjunction with BYTE_COUNT to
create 64-bit aligned RapidIO packet header address)
2. 24-bit Config_offset Field – Maintenance Packets Type 8 (Will be used in conjunction with
BYTE_COUNT to create 64-bit aligned RapidIO packet header Config_offset). The 2 LSBs of
this field must be zero since the smallest configuration access is 4 bytes.
DSP Address
Byte_Count
32-bit DSP byte address. Not available in RapidIO Header.
Number of data bytes to Read/Write - up to 4K bytes. (Used in conjunction with RapidIO address
to create WRSIZE/RDSIZE and WDPTR in RapidIO packet header.)
000000000000b – 4K bytes
000000000001b – 1 byte
000000000010b – 2 bytes
. . .
111111111111b – 4095 bytes
(Maintenance requests are limited to 4 bytes)
RapidIO tt field specifying 8- or 16-bit DeviceIDs.
00b – 8-bit deviceIDs
ID Size
01b – 16-bit deviceIDs
10b - reserved
11b - reserved
Priority
RapidIO prio field specifying packet priority (0 = lowest, 3 = highest). Request packets should not
be sent at a priority level of 3 to avoid system deadlock. It is the responsibility of the software to
assign the appropriate outgoing priority.
Xamsbs
RapidIO xamsb field specifying the extended address MSBs.
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Table 14. LSU Control/Command Register Fields (continued)
LSU Register Field
RapidIO Packet Header Field
DestID
RapidIO destinationID field specifying the target device.
4 MSBs: 4-bit ftype field for all packets
4 LSBs: 4-bit trans field for packet types 2, 5, and 8
Not available in RapidIO header.
Packet Type
OutPortID
Indicates the output port number for the packet to be transmitted from. Specified by the CPU
along with NodeID.
Drbll Info
RapidIO hop_count field specified for Type 8 Maintenance packets.
Not available in RapidIO header.
Hop Count
Interrupt Req
CPU controlled request bit used for interrupt generation. Typically used in conjunction with
non-posted commands to alert the CPU when the requested data/status is present.
0 - An interrupt is not requested upon completion of command
1- An interrupt is requested upon completion of command
Table 15. LSU Status Register Fields
LSU Register Field
Function
BSY
Indicates status of the command registers.
0 - Command registers are available (writable) for next set of transfer descriptors
1 - Command registers are busy with current transfer
Completion Code
Indicates the status of the pending command.
000b – Transaction complete, no errors (Posted/Non-posted)
001b – Transaction timeout occurred on Non-posted transaction
010b – Transaction complete, packet not sent due to flow control blockade (Xoff)
011b – Transaction complete, non-posted response packet (type 8 and 13) contained ERROR status, or
response payload length was in error
100b – Transaction complete, packet not sent due to unsupported transaction type or invalid programming
encoding for one or more LSU register fields
101b – DMA data transfer error
110b – Retry DOORBELL response received, or Atomic Test-and-swap was not allowed (semaphore in
use)
(1)
111b – Transaction complete, packet not sent due to unavailable outbound credit at given priority
(1)
Status available only when busy (BSY) signal = 0.
Four LSU register sets exist. This allows four outstanding requests for all transaction types that require a
response (i.e., non-posted). For multi-core devices, software manages the usage of the registers. A
shared configuration bus accesses all register sets. A single core device can utilize all four LSU blocks.
Figure 13 shows the timing diagram for accessing the LSU registers. The busy (BSY) signal is deasserted.
LSUn_REG1 is written on configuration bus clock cycle T0, LSUn_REG2 is written on cycle T1,
LSUn_REG3 is written on cycle T2, and LSUn_REG4 is written on cycle T3. The command register
LSUn_REG5 is written on cycle T4. The extended address field in LSUn_REG0 is assumed to be constant
in this example. Upon completion of the write to the command register (next clock cycle T5), the BSY
signal is asserted, at which point the preceding completion code is invalid and accesses to the LSU
registers are not allowed. Once the transaction completes (either as a successful transmission, or
unsuccessfully, such as flow control prevention or response timeout) and any required interrupt service
routine is completed, the BSY signal is deasserted and the completion code becomes valid and the
registers are accessible again.
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Figure 13. LSU Registers Timing
After Transaction Completes
T5 Tn
T0
T1
T2
T3
T4
LSUn_REG1
Valid
LSUn_REG2
LSUn_REG3
LSUn_REG4
LSUn_REG5
Valid
Valid
Valid
Valid
Rdy/BSY
Completion
Valid
Valid
The following code illustrates an LSU registers programming example.
SRIO_REGS->LSU1_REG0 =
SRIO_REGS->LSU1_REG1 =
SRIO_REGS->LSU1_REG2 =
SRIO_REGS->LSU1_REG3 =
SRIO_REGS->LSU1_REG4 =
CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_MSB,0 );
CSL_FMK( SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET,(int)&rcvBuff1[0] );
CSL_FMK( SRIO_LSU1_REG2_DSP_ADDRESS, (int)&xmtBuff1[0]);
CSL_FMK( SRIO_LSU1_REG3_BYTE_COUNT,byte_count );
CSL_FMK( SRIO_LSU1_REG4_OUTPORTID,0 )
CSL_FMK( SRIO_LSU1_REG4_PRIORITY,0 )
CSL_FMK( SRIO_LSU1_REG4_XAMSB,0 )
CSL_FMK( SRIO_LSU1_REG4_ID_SIZE,1 )
|
|
|
|
CSL_FMK( SRIO_LSU1_REG4_DESTID,0xBEEF )|
CSL_FMK( SRIO_LSU1_REG4_INTERRUPT_REQ,1 );
CSL_FMK( SRIO_LSU1_REG5_DRBLL_INFO,0x0000 )|
SRIO_REGS->LSU1_REG5 =
CSL_FMK( SRIO_LSU1_REG5_HOP_COUNT,0x00 )
|
CSL_FMK( SRIO_LSU1_REG5_PACKET_TYPE,type );
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Figure 14. Example Burst NWRITE_R
LSUn_REG2
DMA Read
DSP Address
Source Address
Destination Address
Count
LSUn_REG4
OutPortID
31 30 29
Priority
xambs
ID Size
24 23
DestID
RSV
Interrupt Req
0
28 27
26 25
8
7
1
LSUn_REG3
LSUn_REG5
Byte Count
Drbll
Hop Count
Packet
31
16 15
8
7
0
Count
translator
LSUn_REG0
LSUn_REG1
rdsize/ rdptr/
wsize
RapioIO Address/Config_offset
wptr
NodeID
Count*8
ackID
rsv
3
prio
tt
2
ftype
4
destID sourceID
trans
4
wrsize
4
srcTID ext addr address
32 29
wr ptr
1
xamsbs payload
2
CRC
16
5
2
8
8
8
TX Shared Buffer Pool
For WRITE commands, the payload is combined with the header information from the control/command
registers and buffered in the shared TX buffer resource pool. Finally, it is forwarded to the TX FIFO for
transmission. READ commands have no payload. In this case, only the control/command register fields
are buffered and used to create a RapidIO NREAD packet, which is forwarded to the TX FIFO.
Corresponding response packet payloads from READ transactions are buffered in the shared RX buffer
resource pool when forwarded from the receive ports. Both posted and non-posted operations rely on the
OutPortID command register field to specify the appropriate output port/FIFO.
The data is burst internally to the Load/Store module at the DMA clock rate.
2.3.3.1
Detailed Data Path Description
The Load/Store module is for generating all outgoing RapidIO direct I/O packets. Any read or write
transaction, other than the messaging protocol, uses this interface. In addition, outgoing DOORBELL
packets are generated through this interface.
The data path for this module uses DMA bus as the DMA interface. The configuration bus is used by the
CPU to access the control/command registers. The registers contain transfer descriptors that are needed
to initiate READ and WRITE packet generation. After the transfer descriptors are written, flow control
status is queried. The unit examines the DESTID and PRIORITY fields of LSUn_REG4 to determine if that
flow has been Xoffd. Additionally, the free buffer status of the TX FIFO is checked (based on the
OutPortID register field). Only after the flow control access is granted, and a TX FIFO buffer has been
allocated, can a DMA bus read command be issued for payload data to be moved into the shared TX
buffer. Data is moved from the shared TX buffer to the appropriate output TX FIFO in simple sequential
order based on completion of the DMA bus transaction. However, if fabric congestion occurs, priority can
affect the order in which the data leaves the TX FIFOs.
Here a reordering mechanism exists, which transmits the highest priority packets first if RETRY
acknowledges. Once in the FIFO, the data is guaranteed to be transmitted through the pins. Alternatively,
if an intended flow has been shut down, the peripheral signals the CPU with an interrupt to notify that the
packet was not sent and sets the completion code to 010b in the status register. The registers are held
until the interrupt service routine is complete before the BSY signal is released (BSY=0 in LSUn_REG6)
and the CPU can then rewrite or overwrite the transfer descriptors with new data. Figure 15 illustrates the
data path and buffering that is required to support the Load/Store module.
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Figure 15. Load/Store Module Data Flow Diagram
UDI
Peripheral boundary
RapidIO transport
and physical layers
Load/Store module
MMR command
Write transfer
descriptors
Config bus
access
CPU
Control
and
Port x transmission
FIFO queues
arbitrator
Shared
TX
TX
FIFO
DMA
request
buffer
I/O
pins
Response
timer
RX
FIFO
Shared
RX
buffer
L2 memory
DMA
response
= Shared resource for CPPI and MAU
2.3.3.2
Direct I/O TX Operation
WRITE Transactions:
The TX buffers are implemented in a single SRAM and shared between multiple cores. A state machine
arbitrates and assigns available buffers between the LSUs. When the DMA bus read request is
transmitted, the appropriate TX buffer address is specified within it. The data payload is written to that
buffer through the DMA bus response transaction. Depending on the architecture of the device,
interleaving of multi-segmented DMA bus responses from the DMA is possible. Upon receipt of a DMA
bus read response segment, the unit checks the completion status of the payload. Note that only one
payload can be completed in any single DMA bus cycle. The Load/Store module can only forward the
packet to the TX FIFO after the final payload byte from the DMA bus response has been written into the
shared TX buffer. Once the packet is forwarded to the TX FIFO, the shared TX buffer can be released and
made available for a new transaction.
The TX buffer space is dynamically shared among all outgoing sources, including the Load/Store module
and the TX CPPI, as well as the response packets from RX CPPI and the memory access unit (MAU).
Thus, the buffer space memory is partitioned to handle packets with and without payloads. A 4.5K-byte
buffer space is configured to support 16 packets with payloads up to 256 bytes, in addition to 16 packets
without payloads. The SRAM is configured as a 128-bit wide two port, which matches the UDI width of the
TX FIFOs.
Note: The "UDI" ("User Defined Interface") is a reference to the interface between (a) the
SERDES and the FIFO queues and (b) the logical buffers, shared buffers, LSU and MAU
modules, response timer, and controllers (together known as the "User Application"). UDI
could also be known as the "logical/physical interface". No action is required to "define"
this interface.
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Data leaves the shared TX buffer sequentially in order of receipt, not based on the packet priority.
However, if fabric congestion occurs, priority can affect the order in which the data leaves the TX FIFOs. A
reordering mechanism exists here, which transmits the highest priority packets first if RETRY
acknowledges.
For posted WRITE operations, which do not require a RapidIO response packet, a core may submit
multiple outstanding requests. For instance, a single core may have many streaming write packets
buffered at any given time, given outgoing resources. In this application, the control/command registers
can be released (BSY = 0) to the CPU as soon as the header info is written into the shared TX buffer. If
the request has been flow controlled, the peripheral will set the completion code status register and
appropriate interrupt bit of the ICSR. The control/command registers can be released after the interrupt
service routine completes.
For non-posted WRITE operations, which do require a RapidIO response packet, there can be only one
outstanding request per core at any given time. The payload data and header information is written to the
shared TX buffer as described above; however, the command registers cannot be released (BSY = 1) until
the response packet is routed back to the module and the appropriate completion code is set in the status
register. One special case exists for outgoing test-and-swap packets (Ftype 5, Transaction 1110b). This is
the only WRITE class packet that expects a response with payload. This response payload is routed to the
LSU, where it is examined to verify whether the semaphore was accepted, and then the appropriate
completion code is set. The payload is not transferred out of the peripheral via the DMA bus.
So the general flow is as follows:
•
•
•
•
•
•
•
•
•
•
LSU registers are written using the configuration bus
Flow control is determined
TX FIFO free buffer availability is determined
DMA bus read request for data payload
DMA bus response writes data to specified module buffer in the shared TX buffer space
DMA bus read response is monitored for last byte of payload
Header data in the LSU registers is written to the shared TX buffer space
Payload and header are transferred to the TX FIFO
The LSU registers are released if no RapidIO response is needed
Transfer from the TX FIFO to external device based on priority
READ Transactions:
The flow for generating READ transactions is similar to non-posted WRITE with response transactions.
There are two main differences: READ packets contain no data payload, and READ responses have a
payload. So READ commands simply require a non-payload shared TX buffer. In addition, they require a
shared RX buffer. This buffer is not pre-allocated before transmitting the READ request packet, since
doing so could cause traffic congestion of other in-bound packets destined to other functional blocks.
Again, the control/command registers cannot be released (BSY = 1) until the response packet is routed
back to the module and appropriate completion code is set in the status register.
So the general flow would be:
•
•
•
•
•
•
•
LSU registers are written using the configuration bus
Flow control is determined
TX FIFO free buffer availability is determined
Header data in the LSU registers is written to the shared TX buffer
Payload and header are transferred to the TX FIFO
The LSU registers are released if no RapidIO response is needed
Transfer from the TX FIFO to external device based on priority
For all transactions, the shared TX buffers are released as soon as the packet is forwarded to the TX
FIFOs. If an ERROR or RETRY response is received for a non-posted transaction, the CPU must either
reinitiate the process by writing to the LSU register, or initiate a new transaction altogether.
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Segmentation:
The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count
of Read/Write requests exceeds 256 bytes (up to 4K bytes). The second type is when Read/Write request
RapidIO address is non-64-bit aligned. In both cases, the outgoing request is broken up into multiple
RapidIO request packets. For example, assume that the CPU wants to perform a 1K-byte store operation
to an external RapidIO device. After setting up the LSU registers, the CPU performs one write to the
LSUn_REG5 register. The peripheral hardware then segments the store operation into four RapidIO write
packets of 256 bytes each, and calculates the 64-bit-aligned RapidIO address, WRSIZE, and WDPTR as
required for each packet. This example requires four outbound handles to be assigned and four DMA
transmit requests. The LSU registers cannot be released until all posted request packets are passed to
the TX FIFOs. Alternatively, for non-posted operations, such as CPU loads, all packet responses must be
received before the LSU registers are released.
2.3.3.3
Direct I/O RX Operation
Response packets are always type 13 RapidIO packets. All response packets with transaction types not
equal to 0001b are routed to the LSU block sequentially in order of reception. These packets may have a
payload, depending on the type of corresponding request packet that was originally sent. Due to the
nature of RapidIO switch fabric systems, response packets can arrive in any order. The data payload, if
any, and header data is moved from the RX FIFO to the shared RX buffer. The targetTID field of the
packet is examined to determine which core and corresponding set of registers are waiting for the
response. Remember, there can be only one outstanding request per core. Any payload data is moved
from the shared RX buffer into memory through normal DMA bus operations.
Registers for all non-posted operations should only be held for a finite amount of time to avoid blocking
resources when a request or response packet is somehow lost in the switch fabric. This time correlates to
the 24-bit Port Response Time-out Control CSR value discussed in sections 5.10.1 and 6.1.2.4 of the
RapidIO Physical Layer 1x/4x LP-Serial Specification. If the time expires, control/command register
resources should be released, and an error is logged in the error-management RapidIO registers. The
RapidIO Interconnect Specification states that the maximum time interval (all 1s) is between 3 and 6
seconds. A logical layer timeout occurs if the response packet is not received before a countdown timer
(initialized to this CSR value) reaches zero.
Each outstanding packet response timer requires a 4-bit register. The register is loaded with the current
timecode when the transaction is sent. The timecode comes from a 4 bit counter associated with the 24 bit
down counter that continually counts down and is re-loaded with the value of SP_RT_CTL (Address offset
1124h) when it reaches 0. Each time the timecode changes, a 4-bit compare is done to the register. If the
register becomes equal to the timecode again, without a response being seen, then the transaction has
timed out. Essentially, instead of the 24-bit value representing the period of the response timer, the period
is now defined as P = (2^24 x 16)/F. This means the countdown timer frequency needs to be 44.7 –
89.5Mhz for a 6 – 3 second response timeout. Because the needed timer frequency is derived from the
DMA bus clock (which is device dependent), the hardware supports a programmable configuration register
field to properly scale the clock frequency. This configuration register field is described in the Peripheral
Setting Control register (Address offset 0020h).
If a response packet indicates ERROR status, the Load/Store module notifies the CPU by generating an
error interrupt for the pending non-posted transaction. If the response has completed successfully, and the
Interrupt Req bit is set in the control register, the module generates a CPU servicing interrupt to notify the
CPU that the response is available. The control/command registers can be released as soon as the
response packet is received by the logical layer. The hardware is not responsible for attempting a
retransmission of the non-posted transaction.
If a Doorbell response packet indicates Retry status, the Load/Store module notifies the CPU by
generating an interrupt. The control/command registers can be released as soon as the response packet
is received by the logical layer. The hardware is not responsible for attempting retransmission of the
Doorbell transaction.
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So the general flow is as follows:
•
•
Previously, the control/command registers were written and the request packet was sent
Response Packet Type13, Trans != 0001b arrives at module interface, and is handled sequentially (not
based on priority)
•
•
•
The argetTID is examined to determine routing of a response to the appropriate core
The status field of the response packet is checked for ERROR, RETRY or DONE
If the field is DONE, it submits DMA bus request and transmits the payload (if any) to DSP address. If
the field is ERROR/RETRY, it sets an interrupt
•
•
Command registers are released (BSY = 0)
Optional Interrupt to CPU notifying packet reception
2.3.3.4
Reset and Power Down State
Upon reset, the Load/Store module clears the command register fields and wait for a write by the CPU.
The Load/Store module can be powered down if the direct I/O protocol is not being supported in the
application. For example, if the messaging protocol is being used for data transfers, powering down the
Load/Store module will save power. In this situation, the command registers should be powered down and
inaccessible. Clocks should be gated to these blocks while in the power down state.
2.3.4
Message Passing
The Communications Port Programming Interface (CPPI) module is the incoming and outgoing
message-passing protocol engine of the RapidIO peripheral. Messages contain application specific data
that is pushed to the receiving device comparable to a streaming write. Messages do not contain read
operations, but do have response packets.
With message passing, a destination address is not specified. Instead, a mailbox identifier is used within
the RapidIO packet. The mailbox is controlled and mapped to memory by the local (destination) device.
For RapidIO message passing, four mailbox locations are specified. Each mailbox can contain 4 separate
transactions (or letters), effectively providing 16 messages. Single packet messages provide 64 mailboxes
with 4 letters, effectively providing 256 messages. Mailboxes can be defined for different data types or
priorities. The advantage of message passing is that the source device does not require any knowledge of
the destination device’s memory map. The DSP contains buffer description tables for each mailbox. These
tables define a memory map and pointers for each mailbox. Messages are transferred to the appropriate
memory locations via the DMA.
The data path for this module uses the DMA bus as the DMA interface. The ftype header field of the
received RapidIO message packets are decoded by the logical layer of the peripheral. Only Type 11 and
Type 13 (transaction type 1) packets are routed to this module. Data is routed from the priority-based RX
FIFOs to the CPPI module’s data buffer within the shared buffer pool. The mbox (mailbox) header fields
are examined by the mailbox mapper block of the CPPI module. Based on the mailbox and message
length, the data is assigned memory addresses within memory. Data is transferred via DMA bus
commands to memory from the buffer space of the peripheral. The maximum buffer space should
accommodate 256 bytes of data, as that is the maximum payload size of a RapidIO packet. Each
message in memory will be represented by a buffer descriptor in the queue.
The following rules exist for all CPPI traffic:
•
•
One buffer descriptor is provided per message (each buffer descriptor consists of 4 words or 16 bytes).
Contiguous memory space is required for multi-segment read and write operations.
–
There are fixed buffer sizes (configured to handle the application's maximum message size).
An ERROR response is sent if the RX message is too big for the allotted buffer space.
ERROR responses are sent for all subsequent segments of that message.
•
–
•
•
An ERROR response is sent if the mailbox is not mapped, or if it is mapped to a non-existent queue.
An ERROR response is sent if the mailbox is mapped but the queue is not initialized (the head
descriptor pointer is not written), or if the queue is disabled (due to a teardown).
•
An ERROR response is sent if the RX buffer descriptor queue has no empty buffers (there is an
overflow) .
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•
•
Out-of-order responses are allowed.
A RETRY response is issued to the first received segment of a multi-segment message when the RX
queue is busy servicing another request.
–
Subsequent RETRY responses may have to be sent for received pipeline segments or additional
pipelined messages to the same queue.
•
•
•
•
•
In-order message reception for dedicated flows is mode programmable.
A queue is needed for each supported simultaneous multi-segment RX message.
A minimum of 1.25K bytes of SRAM (64 buffer descriptors) is supported.
The transmit source must be able to retry any given segment of a message.
DestID is equal to port for TX operations, and the same DestID is not accessible from multiple ports.
2.3.4.1
RX Operation
As message packets are received by the RapidIO ports, the data is written into memory while maintaining
accurate state information that is needed for future processing. For instance, if a message spans multiple
packets, information is saved that allows re-assembly of those packets by the CPU. The CPPI module
provides a scheme for tracking single and multi-packet messages, linking messages in queues, and
Figure 16. CPPI RX Scheme for RapidIO
Buffer descriptor
queues:
Mailbox 1...64
Descriptor per message
from RapidIO packet
All priorities
Header - Received on any
input port
Dedicated single-segment
message descriptor queue
L2 memory
data buffer, up to 256B
A
C
D
Mailbox mapper
n data packet
n+3 data packet
n+4 data packet
Q15
Q2
Q1
Q0
Packet
manager
E
n+6 data packet
256B free buffer
Queue assignable to any core
n
A
B
B
C
D
B
E
null
n+1
n+2
n+3
n+4
n+5
n+6
L2 memory
data buffer, up to 4K
n+1 data packet
n+2 data packet
n+5 data packet
Multi-segment message
descriptor queue
B
Multi-segment message
descriptor queue N
null
4KB free buffer
Messages addressed to any of the 64 mailbox locations can be received on any of the RapidIO ports
simultaneously. Packets are handled sequentially in order of receipt. The function of the mailbox mapper
block is to direct the inbound messages to the appropriate queue and finally to the correct core. The
queue mapping is programmable and must be configured after device reset. RapidIO originally supported
only 4 mailboxes with 4 letters/mailbox. Letters allow concurrent message traffic between sender and
receiver. However, for messages that consist of only single packets, the unused 4-bit packet field normally
indicating the message segment extends the available number of mailboxes. Figure 17 shows the packet
header fields for message requests.
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Figure 17. Message Request Packet
n*64+64
PHY
10
TRA
2
LOG
4
TRA
16
LOG
PHY
16
n*64+16
acklD
5
rsv
3
prio
2
tt
ftype
4
sourcelD msglen ssize letter mbox msgseg/xmbox double-word 0 double-word 1
...
double-word n-2
64
double-word n-1 CRC
64 16
destID
8
(n-4)*64
2
8
4
4
2
2
4
64
64
ftype = 1011
This enables the letter and mailbox fields to instead allow four concurrent single-segment messages to
sixty-four possible mailboxes (256 total locations) for a source and destination pair. The mailbox mapper
directs the inbound messages to the appropriate queue based on a pre-programmed routing table. It
bases the decision on the SOURCEID, MSGLEN (the size indicates whether the message is segmented),
MBOX, LETTER, and XMBOX fields of the RapidIO packet.
There are 32 programmable look-up table entries for mapping mailboxes to queues. Each entry consists
these register's field is in Section 5.50. In total, there are 64 registers, at address offsets 0800h–08FCh.
Each entry stores the queue number associated with the message’s intended mailbox/letter. If a
mailbox/letter is not supported or does not have a mapping table entry, the message is discarded and an
ERROR response sent. The mapping entries can explicitly call out a mailbox and letter combination, or
alternatively, the mask fields can be used to grant multiple mailbox/letter combinations access to a queue
using the same table entry. A masking value of 0 in the mailbox or letter mask fields indicates that the
corresponding bit in the mailbox or letter field will not be used to match for this queue mapping entry. For
example, a mailbox mask of all zeros would allow a mapping entry to be used for all incoming mailboxes.
The mapping table entry also provides a security feature to enable or disable access from specific external
devices to local mailboxes. The sourceID field indicates which external device has access to the mapping
entry and corresponding queue. A compare is performed between the sourceID of the incoming message
packet and each relevant mailbox/letter table mapping entry SOURCEID field. If they do not match, an
ERROR response is sent back to the sender, and the transaction is logged in the logical layer error
management capture registers, which sets an interrupt. A PROMISCUOUS bit allows this security feature
to be disabled. When the PROMISCUOUS bit is set, full access to the mapping entry from any sourceID is
allowed. Note that when the PROMISCUOUS bit is set, the mailbox/letter and corresponding mask bits
are still in effect. When the PROMISCUOUS bit is cleared, it equals a mask value of FFFFh, and only a
request with the matching sourceID is allowed access to the mailbox.
Each table entry also indicates if it used for single or multi-segment message mapping. Single segment
message mapping entries utilize all six bits of the mailbox and corresponding mask fields. Multi-segment
entries uses only the 2 LSBs. The number of simultaneous supported multi-segment messages is
determined by the number of dedicated RX queues as discussed further below. It is recommended to
dedicate a multi-segment mapping entry for each supported simultaneous letter. Essentially, letter masks
should be avoided for multi-segment mapping to reduce excessive retries. Note that it is possible to
configure the table entries such that incoming single segment and multi-segment messages are directed
to the same queue. To avoid this condition, properly program the mapping table entries.
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Figure 18. Mailbox to Queue Mapping Register Pair
Mailbox to Queue Mapping Register L n (RXU_MAP_L n )
31 30 29
LETTER_MASK
R/W-11
24 23
22 21
16
0
MAILBOX_MASK
R/W-111111
LETTER
R/W-00
MAILBOX
R/W-000000
15
SOURCEID
R/W-0000h
Mailbox to Queue Mapping Register H n (RXU_MAP_H n )
31
Reserved
R-0
10
9
8
7
6
5
2
1
0
SEGMENT
MAPPING
Reserved
R-0
TT
Reserved
R-00
QUEUE_ID
R/W-0000
PROMISCUOUS
R/W-0
R/W-01
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
The packet manager maintains the RX DMA state of free and used data buffers within the memory space.
It directs the data to specific addresses within the memory and maintains and updates the buffer
descriptor queues. There is a single buffer descriptor per RapidIO message. For example, single segment
messages have one buffer descriptor, as do multi-segment messages with up to 4K-byte payloads.
There can be multiple RX buffer descriptor queues per core. It is suggested that one queue be dedicated
to single segment messages and additional queues be dedicated to multi-segment messages. Each
multi-segment message queue can support only one incoming message at a time. Depending on the
application, it may be necessary to support multiple simultaneous segmentation and reassembly (SAR)
operations per core. In this case, a buffer descriptor queue is allocated for each desired simultaneous
message. The peripheral supports a total of 16 assignable RX queues and their associated RX DMA state
registers. Each of the queues can be assigned to single or multi-segment messages.
Table 16. RX DMA State Head Descriptor Pointer (HDP) (Address Offset 600h–63Ch)
Bit
Name
Description
31–0
RX Queue Head
Descriptor Pointer
RX Queue Head Descriptor Pointer: This field is the memory address for the first buffer descriptor
in the channel receive queue. This field is written by the DSP core to initiate queue receive
operations and is zeroed by the port when all free buffers have been used. An error condition
results if the DSP core writes this field when the current field value is nonzero. The address must
be 32-bit word aligned.
Table 17. RX DMA State Completion Pointer (CP) (Address Offset 680h–6BCh)
Bit
Name
Description
31–0
RX Queue
RX Queue Completion Pointer: This field is the memory address for the receive queue completion
Completion Pointer pointer. This register is written by the DSP core with the buffer descriptor address for the last buffer
processed by the DSP core during interrupt processing. The port uses the value written to
determine if the interrupt should be deasserted.
If a multi-segment buffer descriptor queue is not currently free, and an RX port receives another
multi-segment message that is destined for that queue, the RX CPPI sends a RETRY RESPONSE packet
(type 13) to the sender, indicating that an internal buffering problem exists. If a multi-segment buffer
descriptor queue is busy and there is another incoming multi-segment message with the same
SOURCEID, MAILBOX, and LETTER, an ERROR response is sent. This usually indicates that a TX
programming error has occurred, where duplicate segments or segments outside the MSGLEN were sent.
Upon successful reception of any message segment, the RX CPPI is responsible for sending a DONE
response to the sender.
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If a RX message’s length is greater than that of the targeted buffer descriptor, an ERROR response is
sent back to the source device. In addition, the DSP is notified with the use of the CC field of the RX CPPI
buffer descriptor, described as follows. This situation can result from a DSP software error (misallocating a
buffer for the queue), or as a result of sender error (sending to a wrong mailbox).
An RX transaction timeout is used by all multi-segment queues, in order to not hang receive mailbox
resources in the event that a message segment is lost in the fabric. This response-to-request timer
controls the time-out period for sending a response packet and receiving the next request packet of a
given multi-segment message. It has the same value and is analogous to the request-to-response timer
discussed in the TX CPPI and LSU sections, which is defined by the 24-bit value in the port response
time-out CSR (See Section 2.3.3.3). The RapidIO Interconnect Specification states that the maximum time
interval (all 1s) is between 3 and 6 seconds. Each multi-segment receive timer requires a 4-bit register.
The register is loaded with the current timecode when the response is sent. Each time the timecode
changes, a 4-bit compare is done to the register. If the register becomes equal to the timecode again,
without the next message segment being seen, then the transaction has timed out. If this happens, the RX
buffer resources can be released.
The buffer descriptor points to the corresponding data buffer in memory and also points to the next buffer
descriptor in the queue. As segments of a received message arrive, the msgseg field of each segment is
monitored to detect the completion of the received message. Once a full message is received, the
OWNERSHIP bit is cleared in the packet’s buffer descriptor to give control to the host. At this point, a host
interrupt is issued. This interface works with programmable interrupt rate control. There is an ICSR bit for
each supported queue. On interrupt, the CPU processes the RX buffer queue, detecting received packets
by the status of the OWNERSHIP bit in each buffer descriptor. The host processes the RX queue until it
reaches a buffer descriptor with a set OWNERSHIP bit, or set EOQ bit. Once processing is complete, the
host updates the RX DMA State Completion Pointer, allowing the peripheral to reuse the buffer.
Figure 19 shows the RX buffer descriptor fields and Table 18 describes them. A RX buffer descriptor is a
contiguous block of four 32-bit data words aligned on a 32-bit boundary. Accesses to these registers are
restricted to 32-bit boundaries.
Figure 19. RX Buffer Descriptor Fields
Bit Fields
Word
Offset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
next_descriptor_pointer
0
1
2
buffer_pointer
src_id
pri
tt
reserved
mailbox
o
w
n
e
r
s
h
i
t
e
a
r
d
o
w
n
s
o
p
e
o
p
e
o
q
cc
message_length
3
reserved
p
Table 18. RX Buffer Descriptor Field Descriptions
Field
Description
next_descriptor_pointer
Next Descriptor Pointer: The 32-bit word aligned memory address of the next buffer
descriptor in the RX queue. This references the next buffer descriptor from the current
buffer descriptor. If the value of this pointer is zero, then the current buffer is the last
buffer in the queue. The DSP core sets the next_descriptor_pointer.
buffer_pointer
sop = 1
Buffer Pointer: The byte aligned memory address of the buffer associated with the
buffer descriptor. The DSP core sets the buffer_pointer.
Start of Message: Indicates that the descriptor buffer is the first buffer in the message.
•
This bit will always be set, as this device only supports one buffer per message.
eop = 1
End of Message: Indicates that the descriptor buffer is the last buffer in the message.
•
This bit will always be set, as this device only supports one buffer per message.
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Table 18. RX Buffer Descriptor Field Descriptions (continued)
Field
Description
ownership
Ownership: Indicates ownership of the message and is valid only on sop. This bit is set
by the DSP core and cleared by the port when the message has been transmitted. The
DSP core uses this bit to reclaim buffers.
0: The message is owned by the DSP core
1: The message is owned by the port
eoq
End Of Queue: Set by the port to indicate that the RX queue empty condition exists.
This bit is valid only on eop. The port determines the end of queue condition by a zero
next_descriptor_pointer.
0: The RX queue has more buffers available for reception.
1: The Descriptor buffer is the last buffer in the last message in the queue.
teardown_complete
message_length
Teardown Complete: Set by the port to indicate that the host commanded teardown
process is complete, and the channel buffers may be reclaimed by the host.
0: The port has not completed the teardown process.
1: The port has completed the commanded teardown process.
Message Length: Initially written by the DSP core to specify the maximum number of
double-words the buffer can receive. Updated by the peripheral (after receiving a
message) to indicate the actual number of double-words in the entire message.
Message payloads are limited to a maximum size of 512 double-words (4096 bytes).
000000000b: 512 double words
000000001b: 1 double word
000000010b: 2 double words
. . .
111111111b: 511 double words
src_id
tt
Source Node ID: Unique node identifier of the source of the message. Written by the
DSP core.
RapidIO tt field specifying 8- or 16-bit DeviceIDs. Written by the DSP core.
00b: 8-bit deviceIDs
01b: 16-bit deviceIDs
10: reserved
11: reserved
pri
cc
Message Priority: Specifies the SRIO priority at which the message was sent. Written
by the DSP core.
Completion Code: Written by the port.
000: Good completion. Message received.
001: Error, RX message length greater than supported buffer descriptor
message_length
010: Error, TimeOut on receiving one of the segments
011: DMA transfer error on one or more segments
100: Queue teardown completed, data invalid
101: 111 Reserved
mailbox
Destination Mailbox: Specifies the mailbox to which the message was sent. Written by
the DSP core.
000000b: Mailbox 0
000001b: Mailbox 1
. . .
000100b: Mailbox 4
. . .
111111b: Mailbox 63
For multi-segment messages, only the two LSBs of this mailbox are valid. Hardware
ignores the four MSBs if the incoming message has multiple segments.
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Although the switch fabric delivers the segments of multi-packet messages in the order they were sent,
buffer resources at the receiving endpoint may only become available after the initial segment(s) of a
message have had to be retried. The peripheral can accept out-of-order segments and track completion of
For applications that are set up for specific message flows between a single source and destination, it may
require in-order delivery of messages. This is described in scenario B of Figure 20. This scenario is similar
to scenario A, although one message may be retried due to a lack of receiver resources, subsequent
pipelined messages may arrive just as resources are freed up. This is a problem for systems requiring
in-order message delivery. In this case, the peripheral needs to record the Src_id/mailbox/letter of the first
retried message and retry all subsequent new requests until resources are available and a segment for
that Src_id/mailbox/letter is received. As long as all messages are from the same source and that source
sends (and retries) packets in order, then all messages will be received in order. Note that this solution is
less effective when multiple sources share an RX queue. The RX CPPI Control register (Address offset
0744h) sets this mode of operation on all receive queues. Once this mode is set and a retry is issued, the
queue will continue to wait for an incoming message that matches the Src_id/mailbox/letter combination. If
no such packet arrives, the RX queue is unusable in a locked state. To reenable the queue, the in-order
bit in the RX CPPI Control register must be disabled by software for that queue, after which it may be
enabled again if desired. The in-order mode of operation is only valid on multi-segment queues because
single-segment messages will never generate RETRY responses.
Figure 20. RX CPPI Mode Explanation
Data flow destined for the
same RX queue
RX queue status when
packet arrives
Scenario A - Default
Open
Open
Open
Open
Open
Full
C0
B2
B1
B0
A1
A0
Switch
Endpoint
Retry
Retry
Retry
Retry
Accept
Retry
Action
RX queue status when
packet arrives
Scenario B - In order mode
Open
Open
Open
Open
Full
Full
C0
B2
B1
B0
A1
A0
Switch
Endpoint
Retry
Retry
Retry
Retry
Retry
Retry
Action
Records SourceID/letter of
first retry packet
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In addition, multiple messages can be interleaved at the receive port due to ordering within a connected
switch’s output queue. This can occur when using a single or multiple priorities. The RX CPPI block can
handle simultaneous interleaved multi-segment messages. This implies that state information (write
pointers and sourceID) is maintained on each simultaneous message to properly store the segments in
memory. The number of simultaneous transactions supported directly impacts the number of states to be
stored, and the size of the buffer descriptor memory outside the peripheral. With this in mind, the
peripheral’s supported buffer descriptor SRAM is parameterizable. A minimum size of 1.25K bytes is
recommended, which will allow up to 64 buffer descriptors to be stored at any given time for one core.
These buffer descriptors can be configured to support any combination of single and multi-segment
messages. For example, if the application only handles single-segment messages, all 64 buffers can be
allotted to that queue. Note that a given RX queue can contain packets of all priorities which have been
directed from any of the receive ports.
A CPU may wish to stop receiving messages and reclaim buffers belonging to a specific queue. This is
called queue teardown. The CPU initiates a RX queue teardown by writing to the RX Queue Teardown
command register (Address Offset 0740h).
Teardown of an RX queue causes the following actions:
•
If teardown is issued by software during the time when the RX state machine is idle, then the state
machine will immediately start the teardown procedure:
–
If the queue to be torn down is in-message (waiting for one or more segments), then the queue will
be torn down and reported with the current buffer descriptor (teardown bit set, ownership bit
cleared, CC = 100b). All other fields of the buffer descriptor are invalid. The peripheral completes
the teardown procedure by clearing the HDP register, setting the CP register to FFFFFFFCh, and
issuing an interrupt for the given queue. The teardown command register bit is automatically
cleared by the peripheral.
–
–
If the queue is not in-message, and active (next descriptor available), then the next descriptor will
be fetched and updated to report teardown (teardown bit set, ownership bit cleared, CC = 100b). All
other fields of the buffer descriptor are invalid. The peripheral completes the teardown procedure by
clearing the HDP register, setting the CP register to FFFFFFFCh, and issuing an interrupt for the
given queue. The teardown command register bit is automatically cleared by the peripheral.
If the queue is not in-message, but inactive (next descriptor unavailable), then no additional buffer
descriptor will be written. The HDP register and the CP register remain unchanged. An interrupt is
not issued. The teardown command register bit is automatically cleared by the peripheral.
•
If teardown is issued by software during the time when the RXU state machine is busy, the teardown
procedure will be postponed until the state machine is idle.
After the teardown process is complete and the interrupt is serviced by the CPU, the software must
re-initialize the RX queue to restart normal operation.
The buffer descriptor queues are maintained in local SRAM just outside of the peripheral, as shown in
Figure 21. This allows the quickest access time, while maintaining a level of configurability for device
implementation. The SRAM is accessible by the CPU through the configuration bus. Alternatively, the
buffer descriptors could use L2 memory as well.
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Figure 21. CPPI Boundary Diagram
Peripheral boundary
CPPI block
Config bus access
32
32
CPU
CPPI control
registers
32
Buffer
descriptor
dual-port
SRAM
(Nx20B)
DMA
128
Data buffer
L2 memory
2.3.4.2
TX Operation
Outgoing messages are handled similarly, with buffer descriptor queues that are assigned by the CPUs.
The queues are configured and initialized upon reset. When a CPU wants to send a message to an
external RapidIO device, it writes the buffer descriptor information via the configuration bus into the
SRAM. Again, there is a single buffer descriptor per RapidIO message. Upon completion of writing the
buffer descriptor, the OWNERSHIP bit is set to give control to the peripheral. The CPU then writes the TX
DMA State HDP register to initiate the queue transmit. For TX operation, PortID is specified to direct the
Figure 22 shows the TX buffer descriptor fields and Table 21 describes them. A TX buffer descriptor is a
contiguous block of four 32-bit data words aligned on a 32-bit boundary.
Table 19. TX DMA State Head Descriptor Pointer (HDP) (Address Offset 500h–53Ch)
Bit
Name
Description
31–0
TX Queue Head
Descriptor Pointer
TX Queue Head Descriptor Pointer: This field is the DSP core memory address for the first buffer
descriptor in the transmit queue. This field is written by the DSP core to initiate queue transmit
operations and is zeroed by the port when all packets in the queue have been transmitted. An error
condition results if the DSP core writes this field when the current field value is nonzero. The
address must be 32-bit word aligned.
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Table 20. TX DMA State Completion Pointer (CP) (Address Offset 58h–5BCh)
Bit
Name
Description
31–0
TX Queue
TX Queue Completion Pointer: This field is the DSP core memory address for the transmit queue
Completion Pointer completion pointer. This register is written by the DSP core with the buffer descriptor address for
the last buffer processed by the DSP core during interrupt processing. The port uses the value
written to determine if the interrupt should be deasserted.
Figure 22. TX Buffer Descriptor Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
next_descriptor_pointer
Word
Offset
9
8
7
6
5
4
3
2
1
0
0
1
2
buffer_pointer
dest_id
pri
port_id
tt
ssize
mailbox
o
w
n
e
r
s
h
i
t
e
a
r
d
o
w
n
s
o
p
e
o
p
e
o
q
retry_count
cc
message_length
3
reserved
p
Table 21. TX Buffer Descriptor Field Definitions
Field
Description
next_descriptor_pointer
Next Descriptor Pointer: The 32-bit word aligned memory address of the next buffer
descriptor in the TX queue. This is the mechanism used to reference the next buffer
descriptor from the current buffer descriptor. If the value of this pointer is zero then the
current buffer is the last buffer in the queue. The DSP core sets the
next_descriptor_pointer.
buffer_pointer
sop = 1
Buffer Pointer: The byte aligned memory address of the buffer associated with the
buffer descriptor. The DSP core sets the buffer_pointer.
Start of Message: Indicates that the descriptor buffer is the first buffer in the message.
•
This bit will always be set as this device only supports one buffer per message.
End of Message: Indicates that the descriptor buffer is the last buffer in the message.
This bit will always be set as this device only supports one buffer per message.
eop = 1
•
ownership
Ownership: Indicates ownership of the message and is valid only on sop. This bit is set
by the DSP core and cleared by the port when the message has been transmitted. The
DSP core uses this bit to reclaim buffers.
0: The message is owned by the DSP core
1: The message is owned by the port
eoq
End Of Queue: Set by the port to indicate that all messages in the queue have been
transmitted and the TX queue is empty. End of queue is determined by the port when
the next_descriptor_pointer is zero on an eop buffer. This bit is valid only on eop.
0: The TX queue has more messages to transfer.
1: The Descriptor buffer is the last buffer in the last message in the queue.
teardown_complete
Teardown Complete: Set by the port to indicate that the DSP core commanded
teardown process is complete, and the channel buffers may be reclaimed by the DSP
core.
0: The port has not completed the teardown process.
1: The port has completed the commanded teardown process.
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Table 21. TX Buffer Descriptor Field Definitions (continued)
Field
Description
retry_count
Message Retry Count: Set by the DSP core to indicate the total number of retries
allowed for this message, including all segments. Decremented by the port each time a
message is retried.
000000b: Infinite Retries
000001b: Retry Message 1 time
000002b: Retry Message 2 times
. . .
111111b: Retry Message 63 times
cc
Completion Code: Set by the port.
000: Good Completion. Message received a done response.
001: Transaction error. Message received an error response. *
010: Excessive Retries. Message received more than retry_count retry responses.
011: Transaction timeout. Transaction timer elapsed without any message response
being received.
100: DMA data transfer error
101: Descriptor Programming error
110: TX Queue Teardown Complete
111: Outbound Credit not available.
* An ERROR transfer completion code indicates an error in one or more segments of a
transmitted multi-segment message.
message_length
Message Length: Message Length – Written by the DSP core to specify the number of
double-words to transmit. Message payloads are limited to a maximum size of 512
double-words (4096 bytes).
000000000b: 512 double words
000000001b: 1 double word
000000010b: 2 double words
. . .
111111111b: 511 double words
dest_id
pri
Destination Node Id: Unique Node identifier for the Destination of the message. Written
by the DSP core.
Message Priority: Specifies the SRIO priority at which the message will be sent.
Messages should not be sent at a priority level of 3 because the message response is
required to promote the priority to avoid system deadlock. It is the responsibility of the
software to assign the appropriate outgoing priority.
tt
RapidIO tt field specifying 8- or 16-bit DeviceIDs. Written by the host.
00: 8-bit deviceIDs
01: 16-bit deviceIDs
10: reserved
11: reserved
port_id
Port number for routing outgoing packet. Written by the DSP core.
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Table 21. TX Buffer Descriptor Field Definitions (continued)
Field
Description
ssize
RIO standard message payload size. Indicates how the hardware should segment the
outgoing message by specifying the maximum number of double-words per packet. If
the message is a multi-segment message, this field remains the same for all outgoing
segments. All segments of the message, except for the last segment, have payloads
equal to this size. The last message segment may be equal or less than this size.
Maximum message size for a 16 segment message is shown below.
Message_length/16 must be less than or equal to Ssize, if not, the message is not sent
and CC 101b is set. Written by the DSP core.
0000b - 1000b: Reserved
1001b: 1 Double-word payload (Supports up to a 128-byte message)
1010b: 2 Double-word payload (Supports up to a 256-byte message)
1011b: 4 Double-word payload (Supports up to a 512-byte message)
1100b: 8 Double-word payload (Supports up to a 1024-byte message)
1101b: 16 Double-word payload (Supports up to a 2048-byte message)
1110b: 32 Double-word payload (Supports up to a 4096-byte message)
1111b: Reserved
mailbox
Destination Mailbox: Specifies the mailbox to which the message will be sent. Written
by the DSP core.
000000b: Mailbox 0
000001b: Mailbox 1
. . .
000100b: Mailbox 4
. . .
111111b: Mailbox 63
For multi-segment messages, only the 2 LSBs of this mailbox field are valid. Hardware
will ignore the 4 MSBs of this field if the outgoing message is multi-segment.
Once the port controls the buffer descriptor, the DEST_ID field can be queried to determine flow control. If
the transaction has been flow controlled, the DMA bus READ request is postponed so that the TX buffer
space is not wasted. Because buffer descriptors cannot be reordered in the link list, if the transaction at
the head of the buffer descriptor queue is flow controlled, head-of-line (HOL) blocking will occur on that
queue. When this occurs, all transactions located in that queue are stalled. To counter the effects and
reduce back-up of more TX packets, multiple queues are available. The peripheral supports a total of 16
assignable TX queues and their associated TX DMA state registers. The transmission order between
queues is based on a programmable weighted round-robin scheme at the message level. The
programmable control registers are shown in Figure 23. This scheme allows configurability of the queue
transmission order, as well as the weight of each queue within the round robin.
The TX state machine begins by processing the current TX_Queue_Map(n). It will attempt to process the
queue and number of buffer descriptors from that queue programmed in this mapping entry. Then it will
move to TX_Queue_Map(n+1), followed by TX_Queue_Map(n+2) and so forth. It is important to note that
this mapping order is fixed in a circular pattern. Each mapper can point to any queue and multiple
mappers can point to a single queue. If a mapper points to an inactive queue, the peripheral recognizes
this and moves to the next mapper. In order for an active queue to transmit packets, at least one mapper
must be pointing to that queue. The default settings dictate an equally weighted round-robin that starts on
queue0 and increments by one until reaching queue15.
The round-robin scheme does not provide precise control over the order of data sent out of the device.
The ordering of the messages provided by the entries in the Weighted Round Robin Programming
Registers is not an absolute guarantee of the actual transmission order or receive order of the messages.
For example, take a case where there are two active queues and the TX_Queue_Map registers are setup
to continuously send 2 messages from Queue 0, followed by 1 message from Queue 1. If the first
message from Queue 0 attempts to reuse a mailbox/letter combination already in use (Content
Addressable Memory (CAM) violation), or fails to gain outbound credit due to buffer congestion at a given
priority, then the state machine will re-evaluate the TX_Queue_Map to decide on the next step. Since the
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TX_Queue_Map has been programmed to send two messages from Queue 0 before moving to Queue 1,
it will re-attempt to send the same message from Queue 0 before moving on. Whether it is successful or
not, the next attempt will come from Queue 1. Within a given queue, the hardware will always try to send
the head buffer descriptor and can not move to the next buffer descriptor in the queue until a completion
code is written. The weighted round robin control advocates, that statistically over many transmissions, the
messages will be transmitted in accordance with the percentages programmed into the registers .
Network traffic can also affect the packet delivery order. The physical layer of the RapidIO peripheral can
re-order packets of different priorities when fabric congestion occurs.
If message ordering is needed, the following must be obeyed:
•
Multi Segmented Messages
–
If there are only two devices A sending to B where ordering has to be guaranteed:
•
•
•
- Use one TX queue
- Use the same priority
- Map all messages to the same RX queue
–
If there are multiple devices A and B both sending to C, and ordering has to be guaranteed for
both:
•
•
•
- Use one TX queue in each sending device
- Use the same priority within each TX queue
- Map all A messages to the same RX queue and all B messages to another queue by disabling
the promiscuous mode and programming allowable sourceIDs.
•
Single Segmented Messages
There will never be a retry so even if there are multiple senders:
–
•
•
•
- Use one TX queue in each sending device
- Use the same priority within each TX queue
- Map all messages to the same RX queue
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Figure 23. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh)
TX_QUEUE_CNTL0 - Address Offset 7E0h
<-------------------------------- TX_Queue_Map3 ----------------------------->
<-------------------------------- TX_Queue_Map2 ----------------------------->
31
28 27
24 23
20 19
16
Number of Msgs
R/W-0h
Queue Pointer
R/W-3h
Number of Msgs
R/W-0
Queue Pointer
R/W-2h
<-------------------------------- TX_Queue_Map1 ----------------------------->
15 12 11
<-------------------------------- TX_Queue_Map0 ----------------------------->
8
7
4
3
0
Number of Msgs
R/W-0h
Queue Pointer
R/W-1h
Number of Msgs
R/W-0h
Queue Pointer
R/W-0h
TX_QUEUE_CNTL1 - Address Offset 7E4h
<-------------------------------- TX_Queue_Map7 ----------------------------->
31 28 27 24 23
<-------------------------------- TX_Queue_Map6 ----------------------------->
20 19 16
Number of Msgs
R/W-0
Queue Pointer
R/W-7h
Number of Msgs
R/W-0h
Queue Pointer
R/W-6h
<-------------------------------- TX_Queue_Map5 ----------------------------->
15 12 11
<-------------------------------- TX_Queue_Map4 ----------------------------->
8
7
4
3
0
Number of Msgs
R/W-0h
Queue Pointer
R/W-5h
Number of Msgs
R/W-0h
Queue Pointer
R/W-4h
TX_QUEUE_CNTL2 - Address Offset 7E8h
<-------------------------------- TX_Queue_Map11 -----------------------------> <-------------------------------- TX_Queue_Map10 ----------------------------->
31 28 27 24 23 20 19 16
Number of Msgs
R/W-0h
Queue Pointer
R/W-Bh
Number of Msgs
R/W-0h
Queue Pointer
R/W-Ah
<-------------------------------- TX_Queue_Map9 ----------------------------->
15 12 11
<-------------------------------- TX_Queue_Map8 ----------------------------->
8
7
4
3
0
Number of Msgs
R/W-0h
Queue Pointer
R/W-9h
Number of Msgs
R/W-0h
Queue Pointer
R/W-8h
TX_QUEUE_CNTL3 - Address Offset 7ECh
<-------------------------------- TX_Queue_Map15 -----------------------------> <-------------------------------- TX_Queue_Map14 ----------------------------->
31 28 27 24 23 20 19 16
Number of Msgs
R/W-0h
Queue Pointer
R/W-Fh
Number of Msgs
R/W-0h
Queue Pointer
R/W-Eh
<-------------------------------- TX_Queue_Map13 -----------------------------> <-------------------------------- TX_Queue_Map12 ----------------------------->
15 12 11
8
7
4
3
0
Number of Msgs
R/W-0h
Queue Pointer
R/W-Dh
Number of Msgs
R/W-0h
Queue Pointer
R/W-Ch
Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh)
Field Pair
Register[Bits]
Field
Value
Description
TX_Queue_Map0
TX_QUEUE_CNTL0[3–0]
Queue Pointer
0h to Fh
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
TX_QUEUE_CNTL0[7–4]
Number of Msgs
0h to Fh
0h to Fh
0h to Fh
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map1.
TX_Queue_Map1
TX_QUEUE_CNTL0[11–8] Queue Pointer
TX_QUEUE_CNTL0[15–12] Number of Msgs
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map2.
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Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued)
Field Pair
Register[Bits]
Field
Value
Description
TX_Queue_Map2
TX_QUEUE_CNTL0[19–16] Queue Pointer
TX_QUEUE_CNTL0[23–20] Number of Msgs
TX_QUEUE_CNTL0[27–24] Queue Pointer
TX_QUEUE_CNTL0[31–28] Number of Msgs
0h to Fh
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map3.
TX_Queue_Map3
TX_Queue_Map4
TX_Queue_Map5
TX_Queue_Map6
TX_Queue_Map7
TX_Queue_Map8
TX_Queue_Map9
TX_Queue_Map10
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map4.
TX_QUEUE_CNTL1[3–0]
TX_QUEUE_CNTL1[7–4]
Queue Pointer
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of Msgs
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map5.
TX_QUEUE_CNTL1[11–8] Queue Pointer
TX_QUEUE_CNTL1[15–12] Number of Msgs
TX_QUEUE_CNTL1[19–16] Queue Pointer
TX_QUEUE_CNTL1[23–20] Number of Msgs
TX_QUEUE_CNTL1[27–24] Queue Pointer
TX_QUEUE_CNTL1[31–28] Number of Msgs
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map6.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map7.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map8.
TX_QUEUE_CNTL2[3–0]
TX_QUEUE_CNTL2[7–4]
Queue Pointer
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of Msgs
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map9.
TX_QUEUE_CNTL2[11–8] Queue Pointer
TX_QUEUE_CNTL2[15–12] Number of Msgs
TX_QUEUE_CNTL2[19–16] Queue Pointer
TX_QUEUE_CNTL2[23–20] Number of Msgs
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map10.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map11.
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Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued)
Field Pair
Register[Bits]
Field
Value
Description
TX_Queue_Map11
TX_QUEUE_CNTL2[27–24] Queue Pointer
0h to Fh
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
TX_QUEUE_CNTL2[31–28] Number of Msgs
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map12.
TX_Queue_Map12
TX_Queue_Map13
TX_Queue_Map14
TX_Queue_Map15
TX_QUEUE_CNTL3[3–0]
TX_QUEUE_CNTL3[7–4]
Queue Pointer
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of Msgs
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map13.
TX_QUEUE_CNTL3[11–8] Queue Pointer
TX_QUEUE_CNTL3[15–12] Number of Msgs
TX_QUEUE_CNTL3[19–16] Queue Pointer
TX_QUEUE_CNTL3[23–20] Number of Msgs
TX_QUEUE_CNTL3[27–24] Queue Pointer
TX_QUEUE_CNTL3[31–28] Number of Msgs
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map14.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map15.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map0.
The TX queues are treated differently than the RX queues. A TX queue can mix single and multi-segment
message buffer descriptors. The software manages the queue usage.
All outgoing message segments have responses that indicate the status of the transaction. Responses
may indicate DONE, ERROR or RETRY. A buffer descriptor may be released back to CPU control
(OWNERSHIP = 0), only after all segment responses are received, or alternatively if a response timeout
occurs. Timeouts and response evaluation have high priority in the state-machine since they are the only
means to release TX packet resources. The CC is set in the buffer descriptor to indicate the response
status to the CPU. If there is a RETRY response, the TX CPPI module will immediately retry the packet
before continuing to the next queue in the round-robin loop, as long as the RETRY_COUNT is not
exceeded. Once this limit is exceeded, the buffer can be released back to CPU control with the
appropriate CC set. Retry of a message segment does not imply retrying a whole message. Only
segments for which a RETRY response is received should be re-transmitted. This will involve calculating
the correct starting point within the TX data buffer based on the failed segment number and message
length. To achieve respectable performance, the peripheral must not wait for a message/segment
response before sending out the next packet.
Since RapidIO allows for out-of-order responses, the TX CPPI hardware must support this functionality. As
responses are received, the hardware updates the corresponding TX buffer descriptor to reflect the status.
However, if the response is out-of-order, the hardware does not update the CP or set the corresponding
interrupt. Only after all preceding outstanding message responses are received, will the CP and interrupt
be updated. This ensures that a contiguous block of buffer descriptors, starting at the oldest outstanding
descriptor, has been processed by the hardware and is ready for the CPU to reclaim the buffers.
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A transaction timeout is used by all outgoing message and direct I/O packets. It has the same value and is
analogous to the request-to-response timer discussed in the RX CPPI and LSU sections, which is defined
by the 24-bit value in the port response time-out CSR (See Section 2.3.3.3 ). The RapidIO Interconnect
Specification states that the maximum time interval (all 1s) is between 3 and 6 seconds. A logical layer
timeout occurs if the response packet is not received before a countdown timer (initialized to this CSR
value) reaches zero. Since transaction responses can be acknowledged out-of-order, a timer is needed for
each supported outstanding packet in the TX queue. Each outstanding packet response timer requires a
4-bit register. The register is loaded with the current timecode when the transaction is sent. Each time the
timecode changes, a 4-bit compare is done to the 16 outstanding packet registers. If the register becomes
equal to the timecode again, without a response being seen, then the transaction has timed out and the
buffer descriptor is written.
Essentially, instead of the 24-bit value representing the period of the response timer, the period is now
defined as P = (224 x 16)/F. This means the countdown timer frequency needs to be 44.7–89.5 MHz for a
6–3 second response timeout. Since the needed timer frequency is derived from the DMA bus clock
(which is device dependent), the hardware supports a programmable configuration register field to
properly scale the clock frequency. This configuration register field is described in the Peripheral Setting
Control register (Address offset 0020h).
The CPU initiates a TX queue teardown by writing to the TX Queue Teardown command register.
Teardown of a TX queue will cause the following actions:
•
•
No new messages will be sent.
All messages (single and multi-segment) already started will be completed.
–
Failing to complete the message TX would leave an active receiver blocked waiting for the final
segments until the transaction eventually times-out.
–
Note that normal TX State Machine operation is to not send any more segments once an error
response has been received on any segment. So if the receiver has also been torn-down (and is
receiving error responses) multi-segment transmit will complete as soon as all in-transit segments
have been responded to.
•
When all in-transit messages/segments have been responded to, teardown will be completed as
follows:
–
–
–
If the queue is active, the teardown bit will be set in the next buffer descriptor in the queue. The
peripheral completes the teardown procedure by clearing the HDP register, setting the CP register
to FFFFFFFCh, and issuing an interrupt for the given queue. The teardown command register bit is
automatically cleared by the peripheral.
If the queue is in-active (no additional buffer descriptors available), or becomes inactive after a
message in transmission is completed, no buffer descriptor fields are written. The HDP register and
the CP register remain unchanged. An interrupt is not issued. The teardown command register bit
is automatically cleared by the peripheral.
Because of topology differences between flow's response, packets may arrive in a different order to
the order of requests.
After the teardown process is complete and the interrupt is serviced by the CPU, software must
re-initialize the TX queue to restart normal operation.
2.3.4.3
Reset and Power Down State
Upon reset, the CPPI module must be configured by the CPU. The CPU sets up the receive and transmit
queues in memory. Then the CPU updates the CPPI module with the appropriate RX/TX DMA state head
descriptor pointer, so the peripheral knows with which buffer descriptor address to start. Additionally, the
CPU must provide the CPPI module with initial buffer descriptor values for each data buffer.
The CPPI module can be powered down if the message passing protocol is not being supported in the
application. For example, if the direct I/O protocol is being used for data transfers, powering down the
CPPI module will save power. In this situation, the buffer descriptor queue SRAMs and mailbox mapper
logic should be powered down. Clocks should be gated to these blocks while in the power down state.
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SRIO Functional Description
2.3.4.4
Message Passing Software Requirements
Software performs the following functions for messaging:
RX Operation
•
Assigns Mailbox-to-queue mapping and allowable SourceIDs/mailbox- Queue Mapping
Sets up associated buffer descriptor memory – CPPI RAM or L2 RAM
Link-lists the buffer descriptors, next_descriptor_pointer
Assigns single segment (256-byte payload) and multi-segment (4K-byte payload) buffers to queues
buffer_length
•
•
•
•
•
Assigns buffer descriptor to data buffer, buffer_pointer
Gives control of the buffer to the peripheral, ownership = 1
Configures and initiates RX queues
•
•
Assigns Head Descriptor Pointer, HDP, for up to 16 queues: RX DMA State HDP
Port begins to consume buffers beginning with HDP descriptor and sets ownership = 0 for each buffer
descriptor used. Writes Completion Pointer, CP, RX DMA State CP and moves to next buffer.
•
Port hardware generates pending interrupt when CP is written. Physical interrupt generated when
Interrupt Pacing Count down timer = 0.
Processes interrupt
•
•
•
•
Determines ICSR bit and process corresponding queue until ownership = 1 or eoq = 1
Sets processed buffer descriptor ownership = 1
Writes CP value of last buffer descriptor processed
Port hardware clears ICSR bit only if the CP value written by CPU equals port written value in the RX
DMA State CP register
•
Resets interrupt pacing value
TX Operation
Sets up associated buffer descriptor memory – CPPI RAM or L2 RAM
•
•
•
•
•
•
•
Link-lists the buffer descriptors, next_descriptor_pointer
Assigns buffer descriptor to data buffer, buffer_pointer
CPU writes buffer descriptors and sets ownership = 1 for each used.
Specifies RIO fields: Dest_id, Pri, tt, Mailbox
Sets parameters: PortID, Message_length
Port starts queue transmit on CPU write to HDP for up to 16 queues - TX DMA State HDP
Port processes corresponding queues until ownership = 0 or next_descriptor_pointer = all 0s. Port sets
eoq = 1 and writes all 0s to the HDP.
•
When each packet transmission is complete, the port sets ownership = 0 and issues an interrupt to the
CPU by writing the last processed buffer descriptor address to the CP, TX DMA State CP
Processes interrupt
•
The CPU processes the buffer queue to reclaim buffers. If ownership = 0, the packet has been
transmitted and the buffer is reclaimed.
•
•
CPU processes the queue until eoq = 1 or ownership = 1
CPU determines all packets have been transmitted if ownership
next_descriptor_pointer = all 0s in last processed buffer descriptor
=
0, eoq
=
1, and
•
•
•
CPU acknowledges the interrupt after re-claiming all available buffer descriptors.
CPU acknowledges the interrupt by writing the CP value
This value is compared against the port written value in the TX DMA State CP register, if equal, the
interrupt is deasserted.
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Initialization Example
SRIO_REGS->Queue0_RXDMA_HDP
SRIO_REGS->Queue1_RXDMA_HDP
SRIO_REGS->Queue2_RXDMA_HDP
SRIO_REGS->Queue3_RXDMA_HDP
SRIO_REGS->Queue4_RXDMA_HDP
SRIO_REGS->Queue5_RXDMA_HDP
SRIO_REGS->Queue6_RXDMA_HDP
SRIO_REGS->Queue7_RXDMA_HDP
SRIO_REGS->Queue8_RXDMA_HDP
SRIO_REGS->Queue9_RXDMA_HDP
= 0 ;
= 0 ;
= 0 ;
= 0 ;
= 0 ;
= 0 ;
= 0 ;
= 0 ;
= 0 ;
= 0 ;
SRIO_REGS->Queue10_RXDMA_HDP = 0 ;
SRIO_REGS->Queue11_RXDMA_HDP = 0 ;
SRIO_REGS->Queue12_RXDMA_HDP = 0 ;
SRIO_REGS->Queue13_RXDMA_HDP = 0 ;
SRIO_REGS->Queue14_RXDMA_HDP = 0 ;
SRIO_REGS->Queue15_RXDMA_HDP = 0 ;
Queue Mapping
SRIO_REGS->RXU_MAP01_L = CSL_FMK( SRIO_RXU_MAP01_L_LETTER_MASK, 3)|
CSL_FMK( SRIO_RXU_MAP01_L_MAILBOX_MASK, 0x3F)
CSL_FMK( SRIO_RXU_MAP01_L_LETTER, 0)
|
|
|
CSL_FMK( SRIO_RXU_MAP01_L_MAILBOX, 1)
CSL_FMK( SRIO_RXU_MAP01_L_SOURCEID, 0xBEEF);
SRIO_REGS->RXU_MAP01_H = CSL_FMK( SRIO_RXU_MAP01_H_TT, 1)
CSL_FMK( SRIO_RXU_MAP01_H_QUEUE_ID, 0)
|
|
CSL_FMK( SRIO_RXU_MAP01_H_PROMISCUOUS, 1)|
CSL_FMK( SRIO_RXU_MAP01_H_SEGMENT_MAPPING, 1);
RX Buffer Descriptor
RX_DESCP0_0->RXDESC0 = CSL_FMK( SRIO_RXDESC0_N_POINTER,(int )RX_DESCP0_1 ); //link to RX_DESCP0_1
RX_DESCP0_0->RXDESC1 = CSL_FMK( SRIO_RXDESC1_B_POINTER,(int )&rcvBuff1[0] );
RX_DESCP0_0->RXDESC2 = CSL_FMK( SRIO_RXDESC2_SRC_ID, 0xBEEF)|
CSL_FMK( SRIO_RXDESC2_PRI, 1)
CSL_FMK( SRIO_RXDESC2_TT, 1)
CSL_FMK( SRIO_RXDESC2_MAILBOX, 0);
|
|
RX_DESCP0_0->RXDESC3 = CSL_FMK( SRIO_RXDESC3_SOP,1 )
CSL_FMK( SRIO_RXDESC3_EOP,1 )
|
|
CSL_FMK( SRIO_RXDESC3_OWNERSHIP,1 )|
CSL_FMK( SRIO_RXDESC3_EOQ,1 )
CSL_FMK( SRIO_RXDESC3_TEARDOWN,0 ) |
CSL_FMK( SRIO_RXDESC3_CC,0 )
CSL_FMK( SRIO_RXDESC3_MESSAGE_LENGTH,MLEN_512DW);
|
|
RX_DESCP0_1->RXDESC0 = CSL_FMK( SRIO_RXDESC0_N_POINTER, 0);
//end of message
RX_DESCP0_1->RXDESC1 = CSL_FMK( SRIO_RXDESC1_B_POINTER,(int )&rcvBuff2[0] );
RX_DESCP0_1->RXDESC2 = CSL_FMK( SRIO_RXDESC2_SRC_ID, 0xBEEF)|
CSL_FMK( SRIO_RXDESC2_PRI, 1)
CSL_FMK( SRIO_RXDESC2_TT, 1)
CSL_FMK( SRIO_RXDESC2_MAILBOX, 1);
|
|
RX_DESCP0_1->RXDESC3 = CSL_FMK( SRIO_RXDESC3_SOP,1 )
CSL_FMK( SRIO_RXDESC3_EOP,1 )
|
|
CSL_FMK( SRIO_RXDESC3_OWNERSHIP,1 )|
CSL_FMK( SRIO_RXDESC3_EOQ,1 )
CSL_FMK( SRIO_RXDESC3_TEARDOWN,0 ) |
CSL_FMK( SRIO_RXDESC3_CC,0 )
|
|
CSL_FMK( SRIO_RXDESC3_MESSAGE_LENGTH,MLEN_512DW );
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Figure 24. RX Buffer Descriptors
Descriptor
Buffer
Descriptor
Buffer
RX queue head descriptor
pointer
Port RX DMA
state
TX Buffer Descriptor
TX_DESCP0_0->TXDESC0 = CSL_FMK( SRIO_TXDESC0_N_POINTER,(int )TX_DESCP0_1 );
TX_DESCP0_1
//link to
TX_DESCP0_0->TXDESC1 = CSL_FMK( SRIO_TXDESC1_B_POINTER,(int )&xmtBuff1[0] );
Pointer
//Buffer
TX_DESCP0_0->TXDESC2 = CSL_FMK( SRIO_TXDESC2_DESTID, 0xBEEF)
CSL_FMK( SRIO_TXDESC2_PRI, 1)
|
|
|
|
CSL_FMK( SRIO_TXDESC2_TT, 1)
CSL_FMK( SRIO_TXDESC2_PORTID, 3)
CSL_FMK( SRIO_TXDESC2_SSIZE, SSIZE_256B)|
CSL_FMK( SRIO_TXDESC2_MAILBOX, 0);
TX_DESCP0_0->TXDESC3 = CSL_FMK( SRIO_TXDESC3_SOP,1 )
|
|
|
|
|
CSL_FMK( SRIO_TXDESC3_EOP,1 )
CSL_FMK( SRIO_TXDESC3_OWNERSHIP,1 )
CSL_FMK( SRIO_TXDESC3_EOQ,1 )
CSL_FMK( SRIO_TXDESC3_TEARDOWN,0 )
CSL_FMK( SRIO_TXDESC3_RETRY_COUNT,0 )|
CSL_FMK( SRIO_TXDESC3_MESSAGE_LENGTH,MLEN_512DW );
TX_DESCP0_1->TXDESC0 = CSL_FMK( SRIO_TXDESC0_N_POINTER, 0);
//end of message
TX_DESCP0_1->TXDESC1 = CSL_FMK( SRIO_TXDESC1_B_POINTER,(int )&xmtBuff2[0] );
TX_DESCP0_1->TXDESC2 = CSL_FMK( SRIO_TXDESC2_DESTID, 0xBEEF)
CSL_FMK( SRIO_TXDESC2_PRI, 1)
|
|
|
|
CSL_FMK( SRIO_TXDESC2_TT, 1)
CSL_FMK( SRIO_TXDESC2_PORTID, 3)
CSL_FMK( SRIO_TXDESC2_SSIZE, SSIZE_256B)|
CSL_FMK( SRIO_TXDESC2_MAILBOX, 1);
TX_DESCP0_1->TXDESC3 = CSL_FMK( SRIO_TXDESC3_SOP,1 )
|
|
|
|
|
CSL_FMK( SRIO_TXDESC3_EOP,1 )
CSL_FMK( SRIO_TXDESC3_OWNERSHIP,1 )
CSL_FMK( SRIO_TXDESC3_EOQ,1 )
CSL_FMK( SRIO_TXDESC3_TEARDOWN,0 )
CSL_FMK( SRIO_TXDESC3_RETRY_COUNT,0 )|
CSL_FMK( SRIO_TXDESC3_MESSAGE_LENGTH,MLEN_512DW );
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SRIO Functional Description
Figure 25. TX Buffer Descriptors
Descriptor
Buffer
Descriptor
Buffer
TX queue head descriptor
pointer
Port TX DMA
state
Start Message Passing
SRIO_REGS->Queue0_RXDMA_HDP
= (int )RX_DESCP0_0 ;
= (int )TX_DESCP0_0 ;
SRIO_REGS->Queue0_TXDMA_HDP
2.3.5
Maintenance
The type 8 MAINTENANCE packet format accesses the RapidIO capability registers (CARs), command
and status registers (CSRs), and data structures. Unlike other request formats, the type 8 packet format
serves as both the request and the response format for maintenance operations. Type 8 packets contain
no addresses and only contain data payloads for write requests and read responses. All configuration
register read accesses are word (4-byte) accesses. All configuration register write accesses are also word
(4-byte) accesses.
The wrsize field specifies the maximum size of the data payload for multiple double-word transactions.
The data payload may not exceed that size but may be smaller if desired. Both the maintenance read and
the maintenance write request generate the appropriate maintenance response.
The maintenance port-write operation is a write operation that does not have guaranteed delivery and
does not have an associated response. This maintenance operation is useful for sending messages such
as error indicators or status information from a device that does not contain an endpoint, such as a switch.
The data payload is typically placed in a queue in the targeted endpoint and an interrupt is typically
generated to a local processor. A port-write request to a queue that is full or busy servicing another
request may be discarded.
SRIO_REGS->LSU1_REG0 = CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_MSB,0 );
SRIO_REGS->LSU1_REG1 = CSL_FMK( SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET, (int )car_csr );
SRIO_REGS->LSU1_REG2 = CSL_FMK( SRIO_LSU1_REG2_DSP_ADDRESS, (int )&xmtBuff[0]);
SRIO_REGS->LSU1_REG3 = CSL_FMK( SRIO_LSU1_REG3_BYTE_COUNT,byte_count );
SRIO_REGS->LSU1_REG4 = CSL_FMK( SRIO_LSU1_REG4_OUTPORTID,0 )
CSL_FMK( SRIO_LSU1_REG4_PRIORITY,0 )
|
|
|
|
|
CSL_FMK( SRIO_LSU1_REG4_XAMSB,0 )
CSL_FMK( SRIO_LSU1_REG4_ID_SIZE,1 )
CSL_FMK( SRIO_LSU1_REG4_DESTID,0xBEEF )
CSL_FMK( SRIO_LSU1_REG4_INTERRUPT_REQ,0 );
//no extended address
SRIO_REGS->LSU1_REG5 = CSL_FMK( SRIO_LSU1_REG5_DRBLL_INFO,0x0000 )|
CSL_FMK( SRIO_LSU1_REG5_HOP_COUNT,0x03 )
|
CSL_FMK( SRIO_LSU1_REG5_PACKET_TYPE,type );
//type = REQ_MAINT_RD
2.3.6
Doorbell Operation
(typically a DONE response), and it is used by a processing element to send a very short message to
another processing element through the interconnect fabric. The DOORBELL transaction contains the info
field to hold information and does not have a data payload. This field is software-defined and can be used
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for any desired purpose; see the RapidIO Interconnect Specification, Section 3.1.4, Type 10 Packet
Formats (Doorbell Class), for information about the info field. A processing element that receives a
doorbell transaction takes the packet and puts it in a doorbell message queue within the processing
element. This queue may be implemented in hardware or in local memory. This behavior is similar to that
of typical message passing mailbox hardware. The local processor is expected to read the queue to
determine the sending processing element and the info field, and determine what action to take.
The DOORBELL functionality is user-defined, but this packet type is commonly used to initiate DSP core
(CPU) interrupts. A DOORBELL packet is not associated with a particular data packet that was previously
transferred, so the info field of the packet must be configured to reflect the DOORBELL bit to be serviced
for the correct TID (Transfer Information Descriptor) information to be processed.
Figure 26. Doorbell Operation
PHY
10
TRA
LOG
4
TRA
16
LOG
32
PHY
16
2
acklD
5
rsv
3
prio
2
tt
1010 destID sourcelD Reserved
srcTID
8
info (msb)
8
info (lsb)
8
CRC
16
2
4
8
8
8
1
9
2
4
Reserved
Doorbell Reg #
rsv
Doorbell bit
The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There
are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers
Routing Registers. Additionally, each status bit is user-defined for the application. For instance, it may be
desirable to support multiple priorities with multiple TID circular buffers per core if control data uses a high
priority (for example, priority = 2), while data packets are sent on priority 0 or 1. This allows the control
packets to have preference in the switch fabric and arrive as quickly as possible. Since it may be required
to interrupt the CPU for both data and control packet processing separately, separate circular buffers are
used, and DOORBELL packets need to distinguish between them for interrupt servicing. If any reserved
bit in the DOORBELL info field is set, an error response is sent.
info Field Segments
Value Written To
DOORBELL_INFO
Field Of
Associated
Doorbell Interrupt
Routing Bits
Mapped To This
Doorbell Interrupt
Status Bit
Doorbell
Doorbell
Bit
Reserved
000000000b
000000000b
000000000b
000000000b
000000000b
000000000b
000000000b
000000000b
Reg #
00b
00b
01b
01b
10b
10b
11b
11b
rsv
LSUn_REG5
0b
0b
0b
0b
0b
0b
0b
0b
0000b
1001b
0111b
1100b
0101b
1111b
0110b
1011b
0000h
0009h
0027h
002Ch
0045h
004Fh
0066h
006Bh
DOORBELL0_ICRR[3:0]
DOORBELL0_ICRR2[7:4]
DOORBELL1_ICRR[31:28]
DOORBELL0_ICSR[0]
DOORBELL0_ICSR[9]
DOORBELL1_ICSR[7]
DOORBELL1_ICRR2[19:16] DOORBELL1_ICSR[12]
DOORBELL2_ICRR[23:20] DOORBELL2_ICSR[5]
DOORBELL2_ICRR2[31:28] DOORBELL2_ICSR[15]
DOORBELL3_ICRR[27:24] DOORBELL3_ICSR[6]
DOORBELL3_ICRR2[15:12] DOORBELL3_ICSR[11]
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SRIO_REGS->LSU1_REG0 = CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_MSB,0 );
SRIO_REGS->LSU1_REG1 = CSL_FMK( SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET, 0);
SRIO_REGS->LSU1_REG2 = CSL_FMK( SRIO_LSU1_REG2_DSP_ADDRESS, 0);
SRIO_REGS->LSU1_REG3 = CSL_FMK( SRIO_LSU1_REG3_BYTE_COUNT, 0 );
SRIO_REGS->LSU1_REG4 = CSL_FMK( SRIO_LSU1_REG4_OUTPORTID,1 )
CSL_FMK( SRIO_LSU1_REG4_PRIORITY,0 )
|
|
|
|
CSL_FMK( SRIO_LSU1_REG4_XAMSB,0 )
CSL_FMK( SRIO_LSU1_REG4_ID_SIZE,1 )
CSL_FMK( SRIO_LSU1_REG4_DESTID,0xBEEF )|
CSL_FMK( SRIO_LSU1_REG4_INTERRUPT_REQ,0 );
SRIO_REGS->LSU1_REG5 = CSL_FMK( SRIO_LSU1_REG5_DRBLL_INFO,0x0000 )|
CSL_FMK( SRIO_LSU1_REG5_HOP_COUNT,0x03 )
|
CSL_FMK( SRIO_LSU1_REG5_PACKET_TYPE,type );//type = DOORBELL
2.3.7
Atomic Operations
The Atomic operation is a combination read and write operation. The destination reads the data at the
specified address, returns the read data to the requestor, performs the required operation to the data, and
then writes the modified data back to the specified address without allowing any intervening activity to that
address. Defined operations are increment, decrement, test-and-swap, set, and clear (see Table 3, Packet
Type). Of these, only test-and-swap requires the requesting processing element to supply data. Incoming
Atomic operations which target the device are not supported for internal L2 memory or registers. Atomic
request operations to external devices are supported and have a response packet.
Request Atomic operations (Ftype 2) never contain a data payload. These operations are like NREAD
(24h) transactions. The data payload size for the response to an Atomic transaction is 8 bytes. The
addressing scheme defined for the read portion of the Atomic transaction also controls the size of the
atomic operation in memory so that the bytes are contiguous and of size byte, half-word (2 bytes), or word
(4 bytes), and are aligned to that boundary and byte lane as with a regular read transaction. Double-word
(8-byte), 3-byte, 5-byte, 6-byte, and 7-byte Atomic transactions are not allowed.
Atomic test-and-swap operations (Ftype 5) to external devices are limited to a payload of one double-word
(8 bytes). These operations are like NWRITE with response (55h) transactions. The addressing scheme
defined for the write transactions also controls the size of the Atomic operation in memory so that the
bytes are contiguous and of size byte, half-word (2 bytes), or word (4 bytes), and are aligned to that
boundary and byte lane as with a regular write transaction. Double-word (8-byte), 3-byte, 5-byte, 6-byte,
and 7-byte Atomic test-and-swap transactions are not allowed. Upon receipt of the request, the targeted
device swaps the contents of the specified memory location and the payload if the contents of the memory
location are all 0s. The contents of the memory location are returned, and the appropriate completion code
2.3.8
Congestion Control
The RapidIO Logical Layer Flow Control Extensions Specification. This section describes the requirements
and implementation of congestion control within the peripheral.
The peripheral is notified of switch fabric congestion through type 7 RapidIO packets. The packets are
referred to as Congestion Control Packets (CCPs). The purpose of these packets is to turn off (Xoff), or
turn on (Xon) specific flows defined by DESTID and PRIORITY of outgoing packets. CCPs are sent at the
highest priority in an attempt to address fabric congestion as quickly as possible. CCPs do not have a
response packet and they do not have guaranteed delivery.
When the peripheral receives an Xoff CCP, the peripheral must block outgoing LSU and CPPI packets
that are destined for that flow. When the peripheral receives an Xon, the flow may be enabled. Since
CCPs may arrive from different switches within the fabric, it is possible to receive multiple Xoff CCPs for
the same flow. For this reason, the peripheral must maintain a table and count of Xoff CCPs for each flow.
For example, if two Xoff CCPs are received for a given flow, two Xon CCPs must be received before the
flow is enabled.
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Since CCPs do not have guaranteed delivery and can be dropped by the fabric, an implicit method of
enabling an Xoff’d flow must exist. A simple timeout method is used. Additionally, flow control checks can
be enabled or disabled through the Transmit Source Flow Control Masks. Received CCPs are not passed
through the DMA bus interface.
2.3.8.1
Detailed Description
To avoid large and complex table management, a basic scheme is implemented for congestion
management. The primary goal is to avoid large parallel searches of a centralized congested route table
for each outgoing packet request. The congested route table requirements and subsequent searches
would be overwhelming if each possible DESTID and PRIORITY combination had its own entry. To
implement a more basic scheme, the following assumptions have been made:
•
A small number of flows constitute the majority of traffic, and these flows are most likely to cause
congestion
•
•
HOL blocking is undesired, but allowable for TX CPPI queues
Flow control will be based on DESTID only, regardless of PRIORITY
The congested route table is therefore more static in nature. Instead of dynamically updating a table with
each CCP’s flow information as it arrives, a small finite-entry table is set up and configured by software to
reflect the more critical flows it is using. Only these flows have a discrete table entry. A 16 entry table
reflects 15 critical flows, leaving the sixteenth entry for general other flows, which are categorized
together. Figure 27 and Table 24 summarize the DESTID table entries that are programmable by the CPU
through dedicated flow control registers. A 3-bit hardware counter is implemented for table entries 0
through 14, to maintain a count of Xoff CCPs for that flow. The other flows table entry counts Xoff CCPs
for all flows other than the discrete entries. The counter for this table entry has 5 bits. All outgoing flows
with non-zero Xoff counts are disabled. The counter value is decremented for each corresponding Xon
CCP that is received, but it is not decrement below zero. Additionally, a hardware timer exists for each
table entry to turn on flows that may have been abandoned by lost Xon CCPs. The timer value is of an
order of magnitude larger than the 32-bit Port Response Time-out CSR value. For this reason, each
transmission source adds 2 bits to its 4-bit response time-out counter. Descriptions of this type of time-out
counter are in Section 2.3.3.3 and Section 2.3.4.2. The additional 2 bits count three timecode revolutions
and provide an implicit Xon timer equal to 3x the Response time-out counter value.
Figure 27. Flow Control Table Entry Registers (Address Offset 0900h–093Ch)
31-18
17-16
15-0
FLOW_CNTL0
Reserved
TT
FLOW_CNTL_ID
R/W-0x0000
R-0x00000
R/W-01
31-18
17-16
15-0
FLOW_CNTL1
FLOW_CNTL2
Reserved
TT
FLOW_CNTL_ID
R/W-0x0000
R-0x00000
R/W-01
31-18
17-16
15-0
Reserved
TT
FLOW_CNTL_ID
R/W-0x0000
R-0x00000
R/W-01
31-18
17-16
15-0
FLOW_CNTL15
Reserved
TT
FLOW_CNTL_ID
R/W-0x0000
R-0x00000
R/W-01
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
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Table 24. Flow Control Table Entry Register n (FLOW_CNTLn) Field Descriptions
Bit
Field
Value
Description
31–18
17–16
Reserved
TT
0
These read-only bits return 0s when read.
Transfer type for flow n
8-bit destination IDs
16-bit destination IDs
Reserved
00b
01b
1xb
15–0
FLOW_CNTL_ID
0000h–FFFFh
Destination ID for flow n. When 8-bit destination IDs are used (TT = 00b),
the 8 MSBs of this field are don't care bits.
Each transmit source, including any LSU and any TX CPPI queue, indicates which of the 16 flows it uses
with a 16-bit flow mask. Figure 28 illustrates the registers that contain the flow masks, and Figure 29
illustrates the general form of an individual flow mask. As can be seen from Table 25, bits 0 through 15 of
the flow mask correspond to flows 0 through 15, respectively.
The CPU must configure the flow masks upon reset. The default setting is all 1s, indicating that the
transmit source supports all flows. If the register is set to all 0s, the transmit source does not support any
flow, and consequently, that source is never flow-controlled. If any of the table entry counters that a
transmit source supports have a corresponding non-zero Xoff count, the transmit source is flow-controlled.
A simple 16-bit bus indicates the Xoff state of all 16 flows and is compared to the transmit source mask
register. Each source interprets this result and performs flow control accordingly. For example, an LSU
module that is flow-controlled can reload its registers and attempt to send a packet to another flow, while a
TX CPPI queue that is flow-controlled may create HOL blocking issues on that queue.
Figure 28. Transmit Source Flow Control Masks
15-0
31-16
RIO_LSUn_FLOW_MASKS
(Address Offsets: 0x041C,
0x043C, 0x045C, 0x047C)
Reserved
LSU n Flow Mask
R, 0x0000
31-16
R/W, 0xFFFF
15-0
31-16
15-0
TX Queue1
Flow Mask
RIO_TX_CPPI_FLOW_MASKS0
(Address Offsets: 0x0704)
TX Queue0
Flow Mask
RIO_TX_CPPI_FLOW_MASKS4
(Address Offsets: 0x0714)
TX Queue9
Flow Mask
TX Queue8
Flow Mask
R/W, 0xFFFF
R/W, 0xFFFF
R/W, 0xFFFF
R/W, 0xFFFF
31-16
15-0
31-16
15-0
TX Queue3
Flow Mask
RIO_TX_CPPI_FLOW_MASKS1
(Address Offsets: 0x0708)
TX Queue2
Flow Mask
RIO_TX_CPPI_FLOW_MASKS5
(Address Offsets: 0x0718)
TX Queue11
Flow Mask
TX Queue10
Flow Mask
R/W, 0xFFFF
R/W, 0xFFFF
R/W, 0xFFFF
R/W, 0xFFFF
31-16
15-0
31-16
15-0
TX Queue5
Flow Mask
RIO_TX_CPPI_FLOW_MASKS2
(Address Offsets: 0x070C)
TX Queue4
Flow Mask
RIO_TX_CPPI_FLOW_MASKS6
(Address Offsets: 0x071C)
TX Queue13
Flow Mask
TX Queue12
Flow Mask
R/W, 0xFFFF
R/W, 0xFFFF
R/W, 0xFFFF
R/W, 0xFFFF
31-16
15-0
31-16
15-0
TX Queue7
Flow Mask
RIO_TX_CPPI_FLOW_MASKS3
(Address Offsets: 0x0710)
TX Queue6
Flow Mask
RIO_TX_CPPI_FLOW_MASKS7
(Address Offsets: 0x0720)
TX Queue15
Flow Mask
TX Queue14
Flow Mask
R/W, 0xFFFF
R/W, 0xFFFF
R/W, 0xFFFF
R/W, 0xFFFF
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Figure 29. Fields Within Each Flow Mask
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FL15
FL14
FL13
FL12
FL11
FL10
FL9
FL8
FL7
FL6
FL5
FL4
FL3
FL2
FL1
FL0
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; -n = Value after reset
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SRIO Functional Description
Table 25. Fields Within Each Flow Mask
Bit
Field
Value Description
15
FL15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TX source does not support Flow 15 from table entry
TX source supports Flow 15 from table entry
TX source does not support Flow 14 from table entry
TX source supports Flow 14 from table entry
TX source does not support Flow 13 from table entry
TX source supports Flow 13 from table entry
TX source does not support Flow 12 from table entry
TX source supports Flow 12 from table entry
TX source does not support Flow 11 from table entry
TX source supports Flow 11 from table entry
TX source does not support Flow 10 from table entry
TX source supports Flow 10 from table entry
TX source does not support Flow 9 from table entry
TX source supports Flow 9 from table entry
14
13
12
11
10
9
FL14
FL13
FL12
FL11
FL10
FL9
8
FL8
TX source does not support Flow 8 from table entry
TX source supports Flow 8 from table entry
7
FL7
TX source does not support Flow 7 from table entry
TX source supports Flow 7 from table entry
6
FL6
TX source does not support Flow 6 from table entry
TX source supports Flow 6 from table entry
5
FL5
TX source does not support Flow 5 from table entry
TX source supports Flow 5 from table entry
4
FL4
TX source does not support Flow 4 from table entry
TX source supports Flow 4 from table entry
3
FL3
TX source does not support Flow 3 from table entry
TX source supports Flow 3 from table entry
2
FL2
TX source does not support Flow 2 from table entry
TX source supports Flow 2 from table entry
1
FL1
TX source does not support Flow 1 from table entry
TX source supports Flow 1 from table entry
0
FL0
TX source does not support Flow 0 from table entry
TX source supports Flow 0 from table entry
2.3.9
Endianness
RapidIO is based on Big Endian. This is discussed in detail in Section 2.4 of the RapidIO Interconnect
Specification. Essentially, Big Endian specifies the address ordering as the most significant bit/byte first.
For example, in the 29-bit address field of a RapidIO packet (shown in Figure 6) the left-most bit that is
transmitted first in the serial bit stream is the MSB of the address. Likewise, the data payload of the packet
is double-word aligned Big Endian, which means the MSB is transmitted first. Bit 0 of all the
RapidIO-defined MMR registers is the MSB.
All Endian-specific conversion is handled within the peripheral. For double-word aligned payloads, the
data should be written contiguously into memory beginning at the specified address. Any unaligned
payloads will be padded and properly aligned within the 8-byte boundary. In this case, WDPTR, RDSIZE,
and WRSIZE RapidIO header fields indicate the byte position of the data within the double-word
boundary. An example of an unaligned transfer is shown in Section 2.4 of the RapidIO Interconnect
Specification.
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SRIO Functional Description
2.3.9.1
Translation for MMR space
There are no Endian translation requirements for accessing the local MMR space. Regardless of the
device memory Endian configuration, all configuration bus accesses are performed on 32-bit values at a
fixed address position. The bit positions in the 32-bit word are defined by this specification. This means
that a memory image which will be copied to a MMR is identical between Little Endian and Big Endian
concept. The desired operation is to locally update a serial RapidIO MMR (offset 1000h) with a value of
A0A1A2A3h, using the configuration bus.
Figure 30. Configuration Bus Example
Byte
lane 0
Byte
lane 3
31
A0 A1 A2 A3
0
A0 A1 A2 A3
DSP defined MMR
offset 0x1000
L2 offset 0x0
DMA 32b
When accessing RapidIO defined MMR within an external device, RapidIO allows 4 bytes, 8 bytes, or any
multiple of a double-word access (up to 64 bytes) for type 8 (maintenance) packets. The peripheral only
supports 4-byte accesses as the target, but can generate all sizes of request packets. RapidIO is defined
as Big Endian only, and has double-word aligned Big Endian packet payloads.
2.3.9.2
Endian Conversion (TMS320TCI6482)
The DMA, however, supports byte wide accesses. The peripheral performs Endian conversion on the
payload if Little Endian is used on the device. This conversion is not only applicable for type 8 packets, but
is also relevant for all outgoing payloads of NWRITE, NWRITE_R, SWRITE, NREAD, and message
packets. This means that the memory image is different between Little Endian and Big Endian
Figure 31. DMA Example
The desired operation is to send a Type 8 maintenance request to an external device.
The goal is to read 16B of RapidIO MMR from an external device, starting offset 0x0000.
This operation involves the LSU block and utilizes the DMA for transferring the response
packet payload.
RapidIO defined bit positions
0
31
A0 A1 A2 A3
MMR offset 0x0000
MMR offset 0x0004
MMR offset 0x0008
MMR offset 0x000C
RapidIO
defined
MMR
B0 B1 B2 B3
C0 C1 C2 C3
D0 D1 D2 D3
offsets
Type 8
Response
Header fields
A0A1A2A3B0B1B2B3 C0C1C2C3D0D1D2D3
Double-word0 Double-word1
Big Endian
Little Endian
Byte
address 0
Byte
address 3
Byte
address 0
Byte
address 3
A0 A1 A2 A3
A3 A2 A1 A0
L2 offset 0x0
L2 offset 0x4
L2 offset 0x8
L2 offset 0xC
L2 offset 0x0
L2 offset 0x4
L2 offset 0x8
L2 offset 0xC
B0 B1 B2 B3
C0 C1 C2 C3
D0 D1 D2 D3
B3 B2 B1 B0
C3 C2 C1 C0
D3 D2 D1 D0
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SRIO Functional Description
2.3.10 Reset and Power Down
The RapidIO peripheral allows independent software controlled shutdown for the logical blocks listed in
signals are deasserted, the clocks are gated to these blocks, effectively providing a shutdown function.
Table 26. Reset Hierarchy
Bus
Reset
GBL
_EN
BLK0
_EN
BLK1
_EN
BLK2
_EN
BLK3
_EN
BLK4
_EN
BLK5
_EN
BLK6
_EN
BLK7
_EN
BLK8
_EN
Logical Block
DMA interface
√
√
√
√
MMRs:
Reset/power-
down control
registers
MMRs:
√
√
√
√
√
Non-reset/power-
down control
registers
Interrupt handling
unit (IHU)
Traffic flow logic
√
√
√
√
Congestion
control unit
(CCU)
LSU (Direct I/O
initiator)
√
√
√
√
√
√
√
√
√
MAU (Direct I/O
target)
√
TXU (message
passing initiator)
√
RXU (message
passing target)
√
Port 0 datapath
Port 1 datapath
Port 2 datapath
Port 3 datapath
√
√
√
√
√
√
√
√
√
√
√
√
Reset of the SERDES macros is handled independently of the registers discussed in this section. The
SERDES can be configured to shutdown unused links or fully shutdown. SERDES TX and RX channels
may be enabled/disabled by writing to bit 0 of the SERDES_CFGTXn_CNTL and
SERDES_CFGRXn_CNTL registers. The PLL and remaining SERDES functional blocks can be controlled
by writing to the ENPLL signal in the SERDES_CFG0_CNTL register. This bit will drive the SERDES
signal input, which will gate the reference clock to these blocks internally. This reference clock is sourced
from a device pin specifically for the SERDES and is not derived from the CPU clock, thus it resets
asynchronously. ENPLL will disable all SERDES high-speed output clocks. Since these clocks are
distributed to all the links, ENPLL should only be used to completely shutdown the peripheral. It should be
noted that shutdown of SERDES links in between normal packet transmissions is not permissible for two
reasons. First, the serial RapidIO sends idle packets between data packets to maintain synchronization
and lane alignment. Without this mechanism, the RapidIO RX logic can be mis-aligned for both 1X and 4X
ports. Second, the lock time of the SERDES PLL would need to reoccur, which would slow down the
operation.
When the SERDES ENTX signal is held low, the corresponding transmitter is powered down. In this state,
both outputs, TXP and TXN, will be pulled high to VDDT.
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2.3.10.1 Reset and Power Down Summary
After reset, the state of the peripheral depends on the default register values.
Software can also perform a hard reset of each logical block within the peripheral via the GBL_EN and
BLKn_EN bits. The GBL_EN bit resets the peripheral, while the rest of the device is not reset. The
BLKn_EN bits shut down unused portions of the peripheral, which minimizes power by resetting the
appropriate logical block(s) and gating off the clock to the appropriate logical block(s). This should be
considered an abrupt reset that is independent of the state of the peripheral and that resets the peripheral
to its original state.
Upon reset of the peripheral, the device must reestablish communication with its link partner. Depending
on the system, this may include a discovery phase in which a host processor reads the peripheral’s
CAR/CSR registers to determine its capabilities. In its simplest form, it involves retraining the SERDES
and going through the initialization phase to synchronize on bit and word boundaries by using idle and
control symbols, as described in Section 5.5.2 of the Part VI of the RapidIO Interconnect Specification.
Until the peripheral and its partner are fully initialized and ready for normal operation, the peripheral will
not send any data packets or non-status control symbols.
•
•
•
GBL_EN: Resets all MMRs, excluding Reset Ctl Values (0000h–01FCh). Resets all logical blocks
except MMR configuration bus i/f. While asserted, the slave configuration bus is operational.
BLK_EN0: Resets all MMRs, excluding Reset Ctl Values (0000h–01FCh). Other logical blocks are
unaffected, including MMR configuration bus i/f.
2.3.10.2 Enable and Enable Status Registers
The enable and enable status registers are comprised of two global registers and nine pairs of
block-specific registers. The global registers are summarized by Figure 32, Figure 33, Table 26, and
Table 27. The GBL_EN register is implemented with a single enable bit. This bit is logically ORed with the
reset input to the module and is fanned out to all logical blocks within the peripheral.
Figure 32. GBL_EN (Address 0030h)
31
1
0
Reserved
R-0
EN
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Figure 33. GBL_EN_STAT (Address 0034h)
31
23
15
24
16
Reserved
R-0
Reserved
R-0
10
9
8
Reserved
R-0
BLK8_EN_
STAT
BLK7_EN_
STAT
R-1
1
R-1
0
7
6
5
4
3
2
BLK6_EN_
STAT
BLK5_EN_
STAT
BLK4_EN_
STAT
BLK3_EN_
STAT
BLK2_EN_
STAT
BLK1_EN_
STAT
BLK0_EN_
STAT
GBL_EN_
STAT
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
LEGEND: R = Read only; -n = Value after reset
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Table 27. Global Enable and Global Enable Status Field Descriptions
Register (Bit)
GBL_EN(31–1)
GBL_EN(0)
Field
Value Description
Reserved
EN
0
These read-only bits return 0s when read.
Global enable. This bit controls reset to all clock domains within the
peripheral.
0
1
0
The peripheral is to be disabled (held in reset with clocks disabled).
The peripheral is to be enabled.
GBL_EN_STAT(31–10)
GBL_EN_STAT(9)
Reserved
These read-only bits return 0s when read.
BLK8_EN_STAT
Block 8 enable status. Logical block 8 is SRIO port 3.
Logical block 8 is in reset with its clock off.
0
1
Logical block 8 is enabled with its clock running.
Block 7 enable status. Logical block 7 is SRIO port 2.
Logical block 7 is in reset with its clock off.
GBL_EN_STAT(8)
GBL_EN_STAT(7)
GBL_EN_STAT(6)
GBL_EN_STAT(5)
GBL_EN_STAT(4)
GBL_EN_STAT(3)
GBL_EN_STAT(2)
BLK7_EN_STAT
BLK6_EN_STAT
BLK5_EN_STAT
BLK4_EN_STAT
BLK3_EN_STAT
BLK2_EN_STAT
BLK1_EN_STAT
0
1
Logical block 7 is enabled with its clock running.
Block 6 enable status. Logical block 6 is SRIO port 1.
Logical block 6 is in reset with its clock off.
0
1
Logical block 6 is enabled with its clock running.
Block 5 enable status. Logical block 5 is SRIO port 0.
Logical block 5 is in reset with its clock off.
0
1
Logical block 5 is enabled with its clock running.
Block 4 enable status. Logical block 4 is the message receive unit (RXU).
Logical block 4 is in reset with its clock off.
0
1
Logical block 4 is enabled with its clock running.
Block 3 enable status. Logical block 3 is the message transmit unit (TXU).
Logical block 3 is in reset with its clock off.
0
1
Logical block 3 is enabled with clock running.
Block 2 enable status. Logical block 2 is the memory access unit (MAU).
Logical block 2 is in reset with its clock off.
0
1
Logical block 2 is enabled with its clock running.
Block 1 enable status. Logical block 1 is the Load/Store module, which is
comprised of the four Load/Store units (LSU1, LSU2, LSU3, and LSU4).
0
1
Logical block 1 is in reset with its clock off.
Logical block 1 is enabled with its clock running.
GBL_EN_STAT(1)
GBL_EN_STAT(0)
BLK0_EN_STAT
GBL_EN_STAT
Block 0 enable status. Logical block 0 is the set of memory-mapped control
registers for the SRIO peripheral.
0
1
Logical block 0 is in reset with its clock off.
Logical block 0 is enabled with its clock running.
Global enable status
0
1
The peripheral is in reset with all its clocks off.
The peripheral is enabled with all its clocks running.
The 18 block-specific registers are represented by Figure 34 through Figure 39. These register pairs have
Figure 34. BLK0_EN (Address 0038h)
31
1
0
Reserved
R-0
EN
R/W-1
LEGEND: R = Read, W = Write, -n = Value after reset
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Figure 35. BLK0_EN_STAT (Address 003Ch)
31
1
1
1
0
Reserved
R-0
EN_STAT
R-1
LEGEND: R = Read, W = Write, -n = Value after reset
Figure 36. BLK1_EN (Address 0040h)
31
0
Reserved
R-0
EN
R/W-1
LEGEND: R = Read, W = Write, -n = Value after reset
Figure 37. BLK1_EN_STAT (Address 0044h)
31
0
Reserved
R-0
EN_STAT
R-1
LEGEND: R = Read, W = Write, -n = Value after reset
•
•
•
Figure 38. BLK8_EN (Address 0078h)
31
1
1
0
Reserved
R-0
EN
R/W-1
LEGEND: R = Read, W = Write, -n = Value after reset
Figure 39. BLK8_EN_STAT (Address 007Ch)
31
0
Reserved
R-0
EN_STAT
R-1
LEGEND: R = Read, W = Write, -n = Value after reset
Table 28. Block Enable and Block Enable Status Field Descriptions
Register(Bit)
Field
Valu Description
e
BLKn_EN(31–1)
Reserved
EN
0
These read-only bits return 0s when read.
BLKn_EN(0)
Block n enable
0
1
0
Logical block n is to be reset with its clock off.
Logical block n is to be enabled with its clock running.
These read-only bits return 0s when read.
Block n enable status
BLKn_EN_STAT(31–1)
Reserved
EN_STAT
BLKn_EN_STAT(0)
0
1
Logical block n is reset with its clock off.
Logical block n is enabled with its clock running.
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SRIO Functional Description
2.3.10.3 Software Shutdown Details
Power consumption is minimized for all logical blocks that are in shutdown. In addition to simply asserting
the appropriate reset signal to each logical block within the peripheral, clocks are gated off to the
corresponding logical block as well. Clocks are allowed to run for 32 clock cycles, which is necessary to
fully reset each logical block. When the appropriate logical block is fully reset, the clock input to that
subblock is gated off. When software asserts GBL_EN/BLKn_EN to release the logical block from reset,
the clocks are un-gated and the GBL_EN_STAT/BLKn_EN_STAT bit(s) indicate a value of 1b.
Note: The BLK_EN bits allow you to shut down and gate clocks to unused portions of the logic,
while other parts of the peripheral continue to operate. When shutting down an individual
block, if TXU and RXU queues are not torn down correctly, the DMA bus could hang. For
example, setting BLK3_EN = 0 (disabling the TXU) before a teardown of the queue could
cause any outstanding DMA request returned to the peripheral for the TXU to hang the
bus.
When using the GBL_EN to shutdown/reset the entire peripheral, it is important to first stop all
master-initiated commands on the DMA bus interface. For example, if the GBL_EN is asserted in the
middle of a DMA transfer from the peripheral, this could hang the bus. The procedure to follow is:
1. Stop all RapidIO source transactions, including LSU and TXU operations. The four LSU blocks should
indiciate a BSY status of 0b (offsets 0418h, 0438h, 0458h, 0478h). If an EDMA channel is used for
driving the LSU, it must be stopped to prevent new/additional transfers. This procedure is outside the
scope of this specification. Teardown of the TXU queues is accomplished by writing 0000FFFFh to
RIO_TX_QUEUE_TEAR_DOWN (offset 0700h). Hardware will then tear down the queues and clear
these bits automatically when the teardown is complete.
2. Stop all RapidIO message receive, RXU, operations. Teardown of the RXU queues is accomplished by
writing 0000FFFFh to RIO_RX_QUEUE_TEAR_DOWN (offset 0740h). Hardware will then tear down
the queues and clear these bits automatically when complete.
3. Once teardown is complete, clear the PEREN bit of the RIO_PCR (offset 0004h) to stop all new logical
layer transactions.
4. Wait 1 second to finish any current DMA transfer.
5. Deassert GBL_EN (offset 0030h).
2.3.11 Emulation
Expected behavior during emulation halt is controlled within the peripheral by the SOFT and FREE bits of
Figure 40. Peripheral Control Register (PCR) - Address Offset 0004h
31
15
16
Reserved
R-0
3
2
1
0
Reserved
R-0
PEREN SOFT FREE
R/W-0 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 29. Peripheral Control Register (PCR) Field Descriptions
Bit
Field
Value Description
31–3 Reserved
0
These read-only bits return 0s when read.
2
PEREN
Peripheral enable. Controls the flow of data in the logical layer of the peripheral. As an initiator, it
will prevent TX transaction generation; as a target, it will disable incoming requests. This should be
the last enable bit to toggle when bringing the device out of reset to begin normal operation.
0
1
Data flow control is disabled.
Data flow control is enabled.
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Table 29. Peripheral Control Register (PCR) Field Descriptions (continued)
Bit
Field
Value Description
1
SOFT
Soft stop. This bit and the FREE bit determine how the SRIO peripheral behaves during emulation
halts.
0
1
Hard stop. All status registers are frozen in default state. (This mode is not supported on the SRIO
peripheral.)
Soft stop
0
FREE
Free run
0
1
The SOFT bit takes effect.
Free run. Peripheral ignores the emulation suspend signal and functions normally.
Free Run Mode: (default mode) Peripheral does not respond to an emulation suspend assertion. The
peripheral functions normally, irrespective of the CPU emulation state.
Soft Stop Mode: The peripheral gracefully halts operations. The peripheral halts operation at a point that
makes sense both to the internal DMA/data access operation and to the pin interface as described below,
after finishing packet reception or transmission in progress:
•
DMA bus DMA master: DMA bus requests in progress are allowed to complete (DMA bus has no
means to throttle command in progress from the master). DMA bus requests that correspond to the
same network packet are allowed to complete. No new DMA bus requests will be generated on the
next new packet.
•
•
•
Configuration bus MMR interface: All memory-mapped register (MMR) configuration bus requests
are serviced as normal.
Events/interrupts: New events/interrupts are not generated to the CPU for newly arriving packets.
Current transactions are allowed to finish and may cause an interrupt upon completion.
Slave pin interface: The pin interface functions as normal. If buffering is available in the peripheral,
the peripheral services externally generated requests as long as possible. When the internal buffers
are consumed, the peripheral will retry incoming network packets in the physical layer.
•
Master pin interface: No new master requests are generated. Master requests in progress are
allowed to complete, including all packets located in the physical layer transmit buffers.
Hard Stop Mode: The peripheral halts immediately. This mode is not supported in the peripheral.
2.3.12 TX Buffers, Credit, and Packet Reordering
Packets to be transmitted by the SRIO peripheral travel to logical layer buffers. The packets are then
moved from the logical layer buffers to physical layer buffers. From the physical layer buffers, the packets
are transmitted through a port to a connected device.
2.3.12.1 Multiple Ports With 1x Operation
With multiple ports in 1x mode, logical layer buffers are grouped per port and contain all priorities. Each
group is 8 buffers deep. A counter is maintained for each port to track available buffer credit across the
UDI. The count is initialized to 8 credits per port. The count is decremented each time a packet is sent
across the UDI for a port. Each port buffer group has a buffer release signal which indicates the release of
a packet from the logical layer buffer to the port's physical buffer, thus indicating the freeing up of space in
the port's logical buffer.
Thresholds are used to govern outbound credit when requested by the protocol units (MAU, RXU, TXU,
and the LSUs). These thresholds are programmable in the peripheral settings control register
(PER_SET_CNTL at address offset 0020h).
The physical layer buffer tries to process all packets in the order they were sent across the UDI. However,
it is also governed by a re-ordering algorithm to decide which packets may be sent to the physical layer
buffer depending on credit availability there.
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The physical layer buffers act like a FIFO unless there is a retry of a packet from the connected device, in
which case a re-ordering algorithm is used. The algorithm searches backward through the buffer group for
the first packet with the highest priority. If there are no higher priority packets in the queue, the current
packet is sent again. As an example of the re-ordering algorithm, suppose a physical layer buffer group
contains packets with the following priorities:
0 0 1 2 3 3 1 0
where the leftmost 0 represents the packet that was the first in, or the head of the queue. If this packet is
retried, the next packet to be sent is the earliest packet with priority 3 (the lefthand 3). If that packet is sent
successfully, the physical layer attempts to send the original retried packet again; otherwise, the physical
layer repeats the re-ordering algorithm.
2.3.12.2 Single Port With 1x or 4x Operation
In the case when only one portis used, logical layer buffers are grouped per priority. Each priority is 8
buffers deep. A counter is maintained for each priority to track available buffer credit across the UDI. The
count is initialized to 8 credits per port. The count is decremented each time a packet is sent across the
UDI for a port. Each port buffer group has a buffer release signal which indicates the release of a packet
from the logical layer buffer to the port's physical buffer, thus indicating the freeing up of space in the
port's logical buffer.
A priority arbiter empties the logical layer buffer with the highest priority available first. For example, it
empties all available priority 3 buffers before priority 2, 1, or 0.
The physical layer buffers act like a FIFO unless there is a retry of a packet from the connected device, in
which case a re-ordering algorithm is used.The algorithm searches backward through the buffer group for
the first packet with the highest priority. If there are no higher priority packets in the queue, the current
packet is sent again. As an example of the re-ordering algorithm, suppose a physical layer buffer group
contains packets with the following priorities:
0 0 1 2 3 3 1 0
where the leftmost 0 represents the packet that was the first in, or head of the queue. If this packet is
retried, the next packet to be sent is the earliest packet with priority 3 (the lefthand 3). If that packet is sent
successfully, the physical layer attempts to send the original retried packet again; otherwise, the physical
layer repeats the re-ordering algorithm.
2.3.12.3 Unavailable Outbound Credit
At any time, if one of the credit counters reaches 0, no more buffer credit is available. The following
describes how the protocol units deal with this case.
MAU or RXU.In the case of the MAU or the RXU, all outbound packets are response packets. As a result,
the MAU or RXU is free to promote a packet’s priority level until priority 3 is reached. If priority 3 cannot
warrant a credit, the MAU or RXU keeps retrying on priority 3 until credit is available. The assumption is
that if all priority levels become backed up, the physical layer re-ordering mechanism will be implemented
to send out the highest priority packets first.
LSUs. For single-packet transfers, if the transfer is unsuccessful after 256 times of credit request, a
completion code of 111b is indicated in the LSU status register (LSUn_REG6). After reading this status,
software must determine whether to try again, increase the priority, or try a different control flow.
For transfers (with up to 4K-byte payloads) requiring multiple packets, if the transfer is unsuccessful after
256 times of credit request for the first packet, a completion code of 111b is indicated in LSUn_REG6.
After the first packet is successfully completed, subsequent packets are given more retry attempts. The
LSU makes up to 64K attempts to gain outbound credit for the subsequent packets. If the LSU is
unsuccessful after the 64K attempts, a completion code of 111b is indicated in LSUn_REG6.
TXU. The TXU cannot change state to handle inbound responses while it is requesting outbound credit.
To avoid deadlock situations, the TXU tries for outbound credit in the following manner.
For single-segment messages, if the transfer is unsuccessful after 256 times of credit request, the TXU
moves to the next queue in the round-robin loop of TX buffer descriptor queues. The TXU tries to send the
unsent message again the next time the round-robin scheduler returns to the given queue.
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For multi-segment messages, if the transfer is unsuccessful after 256 times of credit request for the first
segment, the TXU moves to the next queue in the round-robin loop. The TXU tries to send the unsent
message again the next time around the loop. After the first segment is granted outbound credit and is
sent to the physical layer for transmission, all subsequent segments are given 64K attempts to gain
outbound credit. If the TXU is unsuccessful after the 64K attempts, a completion code of 111b is written to
the buffer descriptor, and the message is cancelled with no attempt to resend.
2.3.13 Initialization Example
2.3.13.1 Enabling the SRIO Peripheral
When the device is powered on, the SRIO peripheral is in a disabled state. Before any SRIO specific
initialization can take place, the peripheral needs to be enabled; otherwise, its registers cannot be written,
and the reads will all return a value of zero.
/* Glb enable srio */
SRIO_REGS->GBL_EN
= 0x00000001 ;
SRIO_REGS->BLK0_EN = 0x00000001 ; //MMR_EN
SRIO_REGS->BLK5_EN = 0x00000001 ; //PORT0_EN
SRIO_REGS->BLK1_EN = 0x00000001 ; //LSU_EN
SRIO_REGS->BLK2_EN = 0x00000001 ; //MAU_EN
SRIO_REGS->BLK3_EN = 0x00000001 ; //TXU_EN
SRIO_REGS->BLK4_EN = 0x00000001 ; //RXU_EN
SRIO_REGS->BLK6_EN = 0x00000001 ; //PORT1_EN
SRIO_REGS->BLK7_EN = 0x00000001 ; //PORT2_EN
SRIO_REGS->BLK8_EN = 0x00000001 ; //PORT3_EN
2.3.13.2 PLL, Ports, Device ID and Data Rate Initializations
Table 30. Port Mode Register Settings
Device
SP_IP_MODE (offset 0x12004)
Bits 31-30
PER_SET_CNTL (offset 0x0020)
Bit 8
Port Mode
TMS320TCI6482
TMS320TCI6482
0x00
0x01
0x00
0x01
1x/4p
1x/1x
For example, Enable PLL, 333MHz, 1x/4p (srio4p1x_mode = 1), x20, 125MHz ref. clock, 2.5 Gbps, half
rate:
if (srio4p1x_mode){
rdata = SRIO_REGS->PER_SET_CNTL;
wdata = 0x0000014F;
mask = 0x000001FF;
//4p1x
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata ; // enable PLL
}
else{
wdata = 0x0000004F; // enable PLL, 1p4x
rdata = SRIO_REGS->PER_SET_CNTL;
mask = 0x000001FF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata ; // enable PLL, 1p1x/4x
}
//INIT_MAC0
if (srio4p1x_mode){
SRIO_REGS->SP_IP_MODE = 0x4400003F; // Jadis mltc/rst/pw enable, clear
}
else{
SRIO_REGS->SP_IP_MODE = 0x0400003F; // Jadis mltc/rst/pw enable, clear
}
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SRIO_REGS->SERDES_CFG0_CNTL = 0x00000013;
SRIO_REGS->SERDES_CFG1_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFG2_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFG3_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFGRX0_CNTL = 0x00081121 ; // enable rx, half rate
SRIO_REGS->SERDES_CFGRX1_CNTL = 0x00081121 ; // enable rx, half rate
SRIO_REGS->SERDES_CFGRX2_CNTL = 0x00081121 ; // enable rx, half rate
SRIO_REGS->SERDES_CFGRX3_CNTL = 0x00081121 ; // enable rx, half rate
SRIO_REGS->SERDES_CFGTX0_CNTL = 0x00010821 ; // enable tx, half rate
SRIO_REGS->SERDES_CFGTX1_CNTL = 0x00010821 ; // enable tx, half rate
SRIO_REGS->SERDES_CFGTX2_CNTL = 0x00010821 ; // enable tx, half rate
SRIO_REGS->SERDES_CFGTX3_CNTL = 0x00010821 ; // enable tx, half rate
2.3.13.3 Peripheral Initializations
Set Device ID Registers
rdata = SRIO_REGS->DEVICEID_REG1;
wdata = 0x00ABBEEF;
mask = 0x00FFFFFF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->DEVICEID_REG1 = mdata ; // id-16b=BEEF, id-08b=AB
rdata = SRIO_REGS->DEVICEID_REG2;
wdata = 0x00ABBEEF;
mask = 0x00FFFFFF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->DEVICEID_REG2 = mdata ; // id-16b=BEEF, id-08b=AB
rdata = SRIO_REGS->PER_SET_CNTL;
data = 0x00000000;
mask = 0x01000000;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata; // bootcmpl=0
SRIO_REGS->DEV_ID
= 0xBEEF0030 ;
= 0x00000000 ;
= 0x00000030 ;
= 0x00000000;
= 0x20000019 ;
= 0x0000FDF4;
= 0x0000FC04;
= 0x00000001;
= 0x00000000 ;
= 0x00000000;
= 0x00ABBEEF;
// id=BEEF, ti=0x0030
// 0
// ti=0x0030
// 0x0000, next ext=0x0100
// proc, bu ext, 16-bit ID, 34-bit addr
// all
// all except atomic
// 34-bit addr
SRIO_REGS->DEV_INFO
SRIO_REGS->ASBLY_ID
SRIO_REGS->ASBLY_INFO
SRIO_REGS->PE_FEAT
SRIO_REGS->SRC_OP
SRIO_REGS->DEST_OP
SRIO_REGS->PE_LL_CTL
SRIO_REGS->LCL_CFG_HBAR
SRIO_REGS->LCL_CFG_BAR
SRIO_REGS->BASE_ID
// 0
// 0
// 16b-id=BEEF, 08b-id=AB
// id=BEEF, lock
// not touched
SRIO_REGS->HOST_BASE_ID_LOCK = 0x0000BEEF;
SRIO_REGS->COMP_TAG = 0x00000000;
SRIO_REGS->SP_IP_DISCOVERY_TIMER = 0x90000000;// 0, short cycles for sim
SRIO_REGS->IP_PRESCAL = 0x00000021; // srv_clk prescalar=0x21 (333MHz)
SRIO_REGS->SP0_SILENCE_TIMER = 0x20000000;
SRIO_REGS->SP1_SILENCE_TIMER = 0x20000000;
SRIO_REGS->SP2_SILENCE_TIMER = 0x20000000;
SRIO_REGS->SP3_SILENCE_TIMER = 0x20000000;
rdata = SRIO_REGS->PER_SET_CNTL;
wdata = 0x01000000;
mask = 0x01000000;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->PER_SET_CNTL = mdata; // bootcmpl=1
RIO_REGS->SP_LT_CTL
= 0xFFFFFF00; // long
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SRIO_REGS->SP_RT_CTL
= 0xFFFFFF00; // long
SRIO_REGS->SP_GEN_CTL
SRIO_REGS->SP0_CTL
SRIO_REGS->SP1_CTL
SRIO_REGS->SP2_CTL
SRIO_REGS->SP3_CTL
= 0x40000000; // agent, master, undiscovered
= 0x00600000; // enable i/o
= 0x00600000; // enable i/o
= 0x00600000; // enable i/o
= 0x00600000; // enable i/o
SRIO_REGS->ERR_DET
SRIO_REGS->ERR_EN
SRIO_REGS->H_ADDR_CAPT
SRIO_REGS->ADDR_CAPT
SRIO_REGS->ID_CAPT
SRIO_REGS->CTRL_CAPT
= 0x00000000 ; // clear
= 0x00000000 ; // disable
= 0x00000000 ; // clear
= 0x00000000 ; // clear
= 0x00000000 ; // clear
= 0x00000000 ; // clear
SRIO_REGS->SP_IP_PW_IN_CAPT0 = 0x00000000 ; // clear
SRIO_REGS->SP_IP_PW_IN_CAPT1 = 0x00000000 ; // clear
SRIO_REGS->SP_IP_PW_IN_CAPT2 = 0x00000000 ; // clear
SRIO_REGS->SP_IP_PW_IN_CAPT3 = 0x00000000 ; // clear
//INIT_WAIT wait for lane initialization
Read register to check portx(1-4) OK bit
// polling SRIO_MAC's port_ok bit
rdata = SRIO_REGS->P0_ERR_STAT ;
while ((rdata & 0x00000002) != 0x00000002)
{
rdata = SRIO_REGS->P0_ERR_STAT ;
}
if (srio4p1x_mode){
rdata = SRIO_REGS->P1_ERR_STAT;
while ((rdata & 0x00000002) != 0x00000002)
{
rdata = SRIO_REGS->P1_ERR_STAT;
}
rdata = SRIO_REGS->P2_ERR_STAT;
while ((rdata & 0x00000002) != 0x00000002)
{
rdata = SRIO_REGS->P2_ERR_STAT;
}
rdata = SRIO_REGS->P3_ERR_STAT;
while ((rdata & 0x00000002) != 0x00000002)
{
rdata = SRIO_REGS->P3_ERR_STAT;
}
}
Assert the PEREN bit to enable logical layer data flow
SRIO_REGS->PCR = 0x00000004;
// peren
2.3.14 Bootload Capability
2.3.14.1 Configuration and Operation
Figure 41 illustrates the system components involved in bootload operation. It is assumed that an external
device will initiate the bootload data transfer and master the DMA interface. Upon reset, the following
sequence of events must occur:
1. DSP is placed in SRIO boot mode by HW mode pins.
2. Host takes DSP out of reset (POR or RST). The peripheral’s state machines and registers are reset.
3. Internal boot-strap ROM configures device registers, including SERDES, and DMA. DSP executes
internal ROM code to initialize SRIO.
•
•
Choice of 4 pin selectable configurations
Optionally, I2C boot can be used to configure SRIO
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SRIO Functional Description
4. DSP executes idle instruction.
5. RapidIO ports send Idle control symbols to train PHYs.
6. Host enabled to explore system with RapidIO Maintenance packets.
7. Host identifies, enumerates and initializes the RapidIO device.
8. Host controller configures DSP peripherals through maintenance packets.
•
SRIO Device IDs are set for DSPs (either by pin strapping or by host manipulation)
9. Boot Code sent from host controller to DSP L2 memory base address via NWRITE.
10. DSP CPU is awakened by an interrupt such as a RapidIO DOORBELL packet.
11. Boot Code is executed and normal operation follows.
Figure 41. Bootload Operation
Boot
Program
1x RapidIO
DSP
Host
Optional
I2C
EEPROM
Controller
ROM
2.3.14.2 Bootload Data Movement
The system host is responsible for writing the bootload data into the DSP’s L2 memory. As such, bootload
is only supported using the direct I/O model, and not the message passing model. Bootload data must be
sent in packets with explicit L2 memory addresses indicating proper destination within the DSP. As part of
the peripheral’s configuration, it should be set up to transfer the desired bootload program to the DSP's
memory through normal DMA bus commands.
2.3.14.3 Device Wakeup
Upon completion of the bootload data transfer, the system host issues a DOORBELL interrupt to the DSP.
monitoring the DMA bus write-with-response commands to ensure that the data has been completely
transferred through the DMA. This interrupt wakes up the CPUs by pulling them out of their reset state.
The 16-bit data field of the DOORBELL packet should be configured to interrupt Core 0 by setting a
2.3.15 RX Multicast Support, Daisy Chain Operation and Packet Forwarding
2.3.15.1 RX Multicast Support
Multicast transactions are I/O packets that specify a destination address within the header. This address is
used directly for the internal DSP transfers and is not modified in any way. For this reason, multi-cast
support is limited to groups containing devices with the same memory map, or other devices that can
perform address translation. It is the responsibility of the system designer to pre-determine valid multi-cast
address ranges.
When a packet is received, the packet’s tt field and DestID are checked against the main DeviceID (offset
forwarded to the logical layer. If there is a match, it is forwarded to the logical layer. Since multicast
operations are defined to be operations that do not require responses, they are limited to NWRITE and
SWRITE operations and forwarded to the MAU.
As an endpoint device, the peripheral accepts packets based on the destination ID. Two options exist for
packet acceptance and are mode selectable. The first option is to only accept packets whose DestIDs
match the local deviceID in 0x0080. This provides a level of security. The second option is is system
multicast operation.
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Table 31. Multicast DeviceID Operation
Local DeviceID
Register Offset
Multicast DeviceID
Register Offset
Device
TMS320TCI6482
Endpoint Device Requirements
0080h
0084h
Accepts discrete multiple DestIDs from
incoming packet
2.3.15.2 Daisy Chain Operation and Packet Forwarding
Some applications may require daisy chaining of devices together versus using a switch fabric. Typically,
these applications are low cost implementations. Daisy chains have variable system latency depending on
device position within the chain. Daisy chain implementations also have reduced bandwidth capabilities,
since the link bandwidth doesn’t change, the bandwidth allocated to each device in the chain is limited
(sum of devices’ individual bandwidth needs can’t exceed link bandwidth).
To support daisy chain or ring topologies, the peripheral features a hardware packet forwarding function.
This feature eliminates the need for software to be involved in routing a packet to the next device in the
chain. The basic idea behind the hardware packet forwarding logic is to provide an input port to output
port path such that the packets never leave the peripheral (no DMA transfer). A simple check of an
in-coming packet’s DestID versus the device’s DeviceID and MulticastID is done to determine if the packet
should be forwarded. If the packet’s DestID matches DeviceID, the packet is accepted and processed by
the device. If the packet’s DestID matches the MulticastID, the packet is accepted by the device and
forwarded based on the rules outlined in Section 2.3.15.1. If the packet’s DestID doesn’t match either, the
packet is simply destroyed or forwarded, depending on the whether the hardware packet forwarding is
enabled.
Additionally, it is beneficial to be able to only forward a packet if the destination ID is one of the devices in
the chain/ring. Otherwise, a rogue packet may be forwarded endlessly using up valuable bandwidth. The
mapping entries allow programmable selection of output port based on the in-coming packets DestID
range. Since the packet forwarding is done at the logical layer and not the physical layer, CRCs will be
regenerated for each forwarded packet.
2.3.15.3 Enabling Multicast and Packet Forwarding
In order to enable multicast support, bit 5 of the SP_IP_MODE (offset 0x12004) must be set to 1.The
multicast mode is disabled by simply writing the same deviceID into the registers listed in Table 31.
Hardware packet forwarding can be disabled by assigning all the table entry Upper and Lower deviceID
boundaries equal to the local DeviceID value.
Figure 42. Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) Offsets 0x0090,
0x0098, 0x00A0, 0x00A8
31
16 15
0
16BIT_DEVID_UP_BOUND
R/W-FFFFh
16BIT_DEVID_LOW_BOUND
R/W-FFFFh
LEGEND: R/W = Read/Write; -n = Value after reset
Table 32. Packet Forwarding Register n for 16-Bit DeviceIDs (PF_16B_CNTLn) Field Descriptions
Bit
Field
Value
Description
31–16
16BIT_DEVID_UP_BOUND
0000h–FFFFh
Upper 16-bit DeviceID boundary. DestID above this range
cannot use the table entry.
15–0
16BIT_DEVID_LOW_BOUND
0000h–FFFFh
Lower 16-bit DeviceID boundary. DestID lower than this
number cannot use the table entry.
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Figure 43. Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) Offsets 0x0094,
0x009C, 0x00A4, 0x00AC
31
18 17
16
OUT_BOUND_
PORT
Reserved
R-0
R/W-3
15
7
8
8BIT_DEVID_UP_BOUND
R/W-FFh
0
8BIT_DEVID_LOW_BOUND
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 33. Packet Forwarding Register n for 8-Bit DeviceIDs (PF_8B_CNTLn) Field Descriptions
Bit
Field
Value
0
Description
31–18
17–16
Reserved
Reserved
OUT_BOUND_PORT
0–3
Output port number for packets whose DestID falls within the 8-bit or
16-bit range for this table entry.
15–8
7–0
8BIT_DEVID_UP_BOUND
8BIT_DEVID_LOW_BOUND
00h–FFh
00h–FFh
Upper 8-bit DeviceID boundary. DestID above this range cannot use
the table entry.
Lower 8-bit DeviceID boundary. DestID lower than this number cannot
use the table entry.
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Logical/Transport Error Handling and Logging
3
Logical/Transport Error Handling and Logging
Error management registers allow detection and logging of logical/transport layer errors. The detectable
errors are captured in the logical layer error detect CSR (see Figure 44). Table 34 names the functional
block(s) involved for each detectable error condition, and includes brief descriptions of the errors captured.
Figure 44. Logical/Transport Layer Error Detect CSR (ERR_DET)
31
30
29
Reserved
R-0
28
27
26
Reserved
R-0
25
24
IO_ERR_
RSPNS
MSG_ERR_
RSPNS
ERR_MSG_
FORMAT
ILL_TRANS_
DECODE
MSG_REQ_
TIMEOUT
PKT_RSPNS_
TIMEOUT
R/W-0
23
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
22
21
UNSOLICITED_
RSPNS
UNSUPPORTED_
TRANS
Reserved
R-0
R/W-0
R/W-0
8
Reserved
R-0
7
6
5
0
RX_CPPI_
SECURITY
RX_IO_DMA_
ACCESS
Reserved
R-0
R/W-0
R/W-0
LEGEND: R = Read; W = Write; -n = Value after reset
Table 34. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions
Bit
Field
Value
Description
31
IO_ERR_RSPNS
IO error response (endpoint device only)
An LSU did not receive an ERROR response to an IO logical layer request.
0
1
An LSU received an ERROR response to an IO logical layer request. To clear
this bit, write 0 to it.
30
MSG_ERR_RSPNS
Message error response (endpoint device only)
0
1
0
The TXU did not receive an ERROR response to a message logical layer
request.
The TXU received an ERROR response to a message logical layer request. To
clear this bit, write 0 to it.
29
28
Reserved
This read-only bit returns 0 when read.
ERR_MSG_FORMAT
Error in message format (endpoint device only)
0
1
The RXU did not receive a message data payload with an invalid size or
segment.
The RXU received a message data payload with an invalid size or segment. To
clear this bit, write 0 to it.
27
ILL_TRANS_DECODE
Illegal transaction decode (switch or endpoint device)
For an LSU or the TXU:
0
1
The LSU/TXU did not receive illegal fields in the response packet for an
IO/message transaction.
The LSU/TXU received illegal fields in the response packet for an IO/message
transaction. To clear this bit, write 0 to it.
For the MAU or the RXU:
0
1
0
The MAU/RXU did not receive illegal fields in the request packet for an
IO/message transaction.
The MAU/RXU received illegal fields in the request packet for an IO/message
transaction. To clear this bit, write 0 to it.
26
Reserved
This read-only bit returns 0 when read.
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Logical/Transport Error Handling and Logging
Table 34. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued)
Bit
Field
Value
Description
25
MSG_REQ_TIMEOUT
Message request timeout (endpoint device only)
A timeout has not been detected by RXU.
0
1
A timeout has been detected by the RXU. A required message request has not
been received by the RXU within the specified time-out interval. To clear this
bit, write 0 to it.
24
PKT_RSPNS_TIMEOUT
Packet response timeout (endpoint device only)
0
1
A timeout has not been detected by an LSU or the TXU.
A timeout has been detected by an LSU or the TXU. A required response has
not been received by the LSU/TXU within the specified timeout interval. To
clear this bit, write 0 to it.
23
22
UNSOLICITED_RSPNS
UNSUPPORTED_TRANS
Unsolicited response (switch or endpoint device)
0
1
An unsolicited response packet has not been received by an LSU or the TXU.
An unsolicited response packet has been received by an LSU or the TXU. To
clear this bit, write 0 to it.
Unsupported transaction (switch or endpoint device)
The MAU has not received an unsupported transaction.
0
1
The MAU has received an unsupported transaction. That is, the MAU received
a transaction that is not supported in the destination operations CAR. To clear
this bit, write 0 to it.
21–8
7
Reserved
0
These read-only bits return 0 when read.
RX CPPI security error
RX_CPPI_SECURITY
0
1
The RXU has not detected an access block.
The RXU has detected an access block. That is, access to one of the RX
queues was blocked. To clear this bit, write 0 to it.
6
RX_IO_DMA_ACCESS
Reserved
RX IO DMA access error
0
1
0
A DMA access to the MAU has not been blocked.
A DMA access to the MAU was blocked. To clear this bit, write 0 to it.
These read-only bits return 0 when read.
5–0
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Interrupt Conditions
4
Interrupt Conditions
This section defines the CPU interrupt capabilities and requirements of the peripheral.
4.1 CPU Interrupts
The following interrupts are supported by the RIO peripheral.
•
Error status: Event indicating that a run-time error was reached. The CPU should reset/resynchronize
the peripheral.
•
•
Critical error: Event indicating that a critical error state was reached. The CPU should reset the system.
CPU servicing: Event indicating that the CPU should service the peripheral.
4.2 General Description
The RIO peripheral is capable of generating various types of CPU interrupts. The interrupts serve two
general purposes: error indication and servicing requests.
Since RapidIO is a packet oriented interface, the peripheral must recognize and respond to inbound
signals from the serial interface. There are no GPIO or external pins used to indicate an interrupt request.
Thus, the interrupt requests are signaled either by an external RapidIO device through the packet
protocols discussed as follows, or are generated internally by the RIO peripheral.
CPU servicing interrupts lag behind the corresponding data, which was generally transferred from an
external processing element into local L2 memory. This transfer can use a messaging or direct I/O
protocol. When the single or multi-packet data transfer is complete, the external PE, or the peripheral
itself, must notify the local processor that the data is available for processing. To avoid erroneous data
being processed by the local CPU, the data transfer must complete through the DMA before the CPU
interrupt is serviced. This condition could occur since the data and interrupt queues are independent of
each other, and DMA transfers can stall. To avoid this condition, all data transfers from the peripheral
through the DMA use write-with-response DMA bus commands, allowing the peripheral to always be
aware that outstanding transfers have completed. Interrupts are generated only after all DMA bus
responses are received. Since all RapidIO packets are handled sequentially, and submitted on the same
DMA priority queue, the peripheral must keep track of the number of DMA requests submitted and the
number of responses received. Thus, a simple counter within the peripheral ensures that data packets
have arrived in memory before submitting an interrupt.
The sending device initiates the interrupt by using the RapidIO defined DOORBELL message. The
packet type is commonly used to initiate CPU interrupts. A DOORBELL packet is not associated with a
particular data packet that was previously transferred, so the INFO field of the packet must be configured
to reflect the DOORBELL bit to be serviced for the correct TID info to be processed.
Figure 45. RapidIO DOORBELL Packet for Interrupt Use
PHY
10
TRA
LOG
4
TRA
16
LOG
32
PHY
16
2
acklD
5
rsv
3
prio
2
tt
1010 destID sourcelD Reserved
srcTID
8
info (msb)
8
info (lsb)
8
CRC
16
2
4
8
8
8
1
9
2
4
Reserved
Doorbell Reg #
rsv
Doorbell bit
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Interrupt Conditions
The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There
are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers
(see Table 23 for assignment of the 16 bits of DOORBELL_INFO field). Each bit can be assigned to any
core as described by the Interrupt Condition Routing Registers. Additionally, each status bit is
user-defined for the application. For instance, it may be desirable to support multiple priorities with multiple
TID circular buffers per core if control data uses a high priority (for example, priority = 2), while data
packets are sent on priority 0 or 1. This allows the control packets to have preference in the switch fabric
and arrive as quickly as possible. Since it may be required to interrupt the CPU for both data and control
packet processing separately, separate circular buffers are used, and DOORBELL packets must
distinguish between them for interrupt servicing. If any reserved bit in the DOORBELL info field is set, an
error response is sent.
The interrupt approach to the messaging protocol is somewhat different. Since the source device is
unaware of the data's physical location in the destination device, and since each messaging packet
contains size and segment information, the peripheral can automatically generate the interrupt after it has
successfully received all packet segments comprising the complete message. This DMA interface uses
the Communications Port Programming Interface (CPPI). This interface is a link-listed approach versus a
circular buffer approach. Data buffer descriptors which contain information such as start of Packet (SOP),
end of packet (EOP), end of queue (EOQ), and packet length are built from the RapidIO header fields.
The data buffer descriptors also contain the address of the corresponding data buffer as assigned by the
receive device. The data buffer descriptors are then link-listed together as multiple packets are received.
Interrupts are generated by the peripheral after all segments of the messages are received and
successfully transferred through the DMA bus with the write-with-response commands. Interrupt pacing is
Error handling on the RapidIO link is handled by the peripheral, and as such, does not require the
intervention of software for recovery. This includes CRC errors due to bit rate errors that may cause
erroneous or invalid operations. The exception to this statement is the use of the RapidIO error
management extended features. This specification monitors and tabulates the errors that occur on a per
port basis. If the number of errors exceeds a pre-determined configurable amount, the peripheral should
interrupt the CPU software and notify that an error condition exits. Alternatively, if a system host is used,
the peripheral may issue a port-write operation to notify the system software of a bad link.
A system reset, or Critical Error interrupt, can be initialized through the RapidIO link. This procedure
allows an external device to reset the local device, causing all state machine and configuration registers to
reset to their original values. This is executed with the Reset-Device command described in Part VI,
Section 3.4.5 of the RapidIO Physical Layer 1x/4x LP-Serial Specification. Four sequential Reset-Device
control symbols are needed to avoid inadvertent resetting of a device.
4.3 Interrupt Condition Status and Clear Registers
Interrupt condition status and clear registers configure which CPU interrupts are to be generated and how,
based on the peripheral activity. All peripheral conditions that result in a CPU interrupt are grouped so that
the interrupt can be accessed in the minimum number of register reads possible.
For each of the three types of interrupts (CPU servicing, error status, and critical error), there are two sets
of registers:
•
Interrupt Condition Status Register (ICSR): Status register that reflects the state of each condition that
can trigger the interrupt. The general description of each interrupt condition status bit (ICSx) is given in
•
Interrupt Condition Clear Register (ICCR): Command register that allows each condition to be cleared.
This is typically required prior to enabling a condition, so that spurious interrupts are not generated.
These registers are accessible in the memory map of the CPU. The CPU controls the clear register. The
status register is readable by the CPU to determine the peripheral condition.
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Interrupt Conditions
Table 35. Interrupt Condition Status and Clear Bits
Field
Access
Reset Value
Value Function
ICSx
R
0
0
1
0
1
Condition not present
Condition present
ICCx
W
0
No effect
Clear the condition status bit (ICSx)
4.3.1
Doorbell Interrupt Condition Status and Clear Registers
The interrupt condition status registers (ICSRs) and the interrupt condition clear registers (ICCRs) for the
peripheral receives doorbell packets. The 16 ICS bits of each interrupt condition status register (ICSR)
indicate the incoming doorbell information packet. For example, the bits ICS15, ICS8, and ICS0 of
DOORBELL0_ICSR correspond to Doorbell 0 information bits 15, 8, and 0. The 16 ICC bits of each
interrupt condition clear register (ICCR) are used to clear the corresponding bits in the ICSR. For example,
the ICC7 bit of DOORBELL2_ICCR is used to clear the ICS7 bit of DOORBELL2_ICSR.
Figure 46. Doorbell 0 Interrupt Condition Status and Clear Registers
Doorbell 0 Interrupt Condition Status Register (DOORBELL0_ICSR) (Address Offset 0200h)
31
16
Reserved
R-0
15
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
R-0 R-0 R-0 R-0 R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS8
R-0
ICS7
R-0
ICS6
R-0
ICS5
R-0
ICS4
R-0
ICS3
R-0
ICS2
R-0
ICS1
R-0
ICS0
R-0
Doorbell 0 Interrupt Condition Clear Register (DOORBELL0_ICCR) (Address Offset 0208h)
31
16
Reserved
R-0
15
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Figure 47. Doorbell 1 Interrupt Condition Status and Clear Registers
Doorbell 1 Interrupt Condition Status Register (DOORBELL1_ICSR) (Address Offset 0210h)
31
16
Reserved
R-0
15
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
R-0 R-0 R-0 R-0 R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS8
R-0
ICS7
R-0
ICS6
R-0
ICS5
R-0
ICS4
R-0
ICS3
R-0
ICS2
R-0
ICS1
R-0
ICS0
R-0
Doorbell 1 Interrupt Condition Clear Register (DOORBELL1_ICCR) (Address Offset 0218h)
31
16
Reserved
R-0
15
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
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Interrupt Conditions
Figure 48. Doorbell 2 Interrupt Condition Status and Clear Registers
Doorbell 2 Interrupt Condition Status Register (DOORBELL2_ICSR) (Address Offset 0220h)
31
16
Reserved
R-0
15
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
R-0 R-0 R-0 R-0 R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS8
R-0
ICS7
R-0
ICS6
R-0
ICS5
R-0
ICS4
R-0
ICS3
R-0
ICS2
R-0
ICS1
R-0
ICS0
R-0
Doorbell 2 Interrupt Condition Clear Register (DOORBELL2_ICCR) (Address Offset 0228h)
31
16
Reserved
R-0
15
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Figure 49. Doorbell 3 Interrupt Condition Status and Clear Registers
Doorbell 3 Interrupt Condition Status Register (DOORBELL3_ICSR) (Address Offset 0230h)
31
16
Reserved
R-0
15
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
R-0 R-0 R-0 R-0 R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS8
R-0
ICS7
R-0
ICS6
R-0
ICS5
R-0
ICS4
R-0
ICS3
R-0
ICS2
R-0
ICS1
R-0
ICS0
R-0
Doorbell 3 Interrupt Condition Clear Register (DOORBELL3_ICCR) (Address Offset 0238h)
31
16
Reserved
R-0
15
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
4.3.2
CPPI Interrupt Condition Status and Clear Registers
interrupt condition registers are used when the SRIO peripheral receives and transmits data message
packets. Each ICS bit corresponds to the interrupt for one of the buffer descriptor queues. For example,
the bits ICS15, ICS8, and ICS0 of RX_CPPI_ICSR correspond to RX buffer descriptor queues 15, 8, and
0. Similarly, the bits ICS15, ICS8, and ICS0 of TX_CPPI_ICSR support TX buffer descriptor queues 15, 8,
and 0. The 16 ICC bits of each interrupt condition clear register (ICCR) are used to clear the
corresponding bits in the ICSR.
For reception, the clearing of any ICSR bit depends on the CPU writing the value of the last buffer
descriptor processed to the completion pointer (CP) register for the queue (QUEUEn_RXDMA_CP). Port
hardware clears the ICSR bit only if the CP value written by the CPU equals the port written value in the
CP register.
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Interrupt Conditions
For transmission, the clearing of any ICSR bit is dependent on the CPU writing to the CP register for the
queue (QUEUEn_TXDMA_CP). The CPU acknowledges the interrupt after reclaiming all available buffer
descriptors by writing the CP value. This value is compared against the port written value in the CP
register. If the values are equal, the interrupt is deasserted.
Figure 50. RX CPPI Interrupt Condition Status and Clear Registers
RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) (Address Offset 0240h)
31
16
Reserved
R-0
15
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
R-0 R-0 R-0 R-0 R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS8
R-0
ICS7
R-0
ICS6
R-0
ICS5
R-0
ICS4
R-0
ICS3
R-0
ICS2
R-0
ICS1
R-0
ICS0
R-0
RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) (Address Offset 0248h)
31
16
Reserved
R-0
15
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Figure 51. TX CPPI Interrupt Condition Status and Clear Registers
TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) (Address Offset 0250h)
31
16
Reserved
R-0
15
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
R-0 R-0 R-0 R-0 R-0 R-0 R-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS8
R-0
ICS7
R-0
ICS6
R-0
ICS5
R-0
ICS4
R-0
ICS3
R-0
ICS2
R-0
ICS1
R-0
ICS0
R-0
TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) (Address Offset 0258h)
31
16
Reserved
R-0
15
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
4.3.3
LSU Interrupt Condition Status and Clear Registers
The ICSR and the ICCR for the LSUs are shown in Figure 52. These interrupt condition registers are used
when the SRIO peripheral transmits direct I/O packets. As described in Table 36, each of the status and
clear bits corresponds to a particular type of transaction interrupt condition for a particular LSU. The ICS
bits of LSU_ICSR indicate the occurrence of the conditions. The ICC bits of LSU_ICCR are used to clear
the corresponding ICS bits.
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Interrupt Conditions
Figure 52. LSU Interrupt Condition Status and Clear Registers
LSU Interrupt Condition Status Register (LSU_ICSR) (Address Offset 0260h)
31 30 29 28 27 26 25 24 23
ICS31 ICS30 ICS29 ICS28 ICS27 ICS26 ICS25 ICS24 ICS23 ICS22 ICS21 ICS20 ICS19 ICS18 ICS17 ICS16
22
21
20
19
18
17
16
R-0
15
R-0
14
R-0
13
R-0
12
R-0
11
R-0
10
R-0
9
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
8
7
6
5
4
3
2
1
0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
R-0 R-0 R-0 R-0 R-0 R-0 R-0
ICS8
R-0
ICS7
R-0
ICS6
R-0
ICS5
R-0
ICS4
R-0
ICS3
R-0
ICS2
R-0
ICS1
R-0
ICS0
R-0
LSU Interrupt Condition Clear Register (LSU_ICCR) (Address Offset 0268h)
31 30 29 28 27 26 25 24 23
22
21
20
19
18
17
16
ICC31 ICC30 ICC29 ICC28 ICC27 ICC26 ICC25 ICC24 ICC23 ICC22 ICC21 ICC20 ICC19 ICC18 ICC17 ICC16
W-0
15
W-0
14
W-0
13
W-0
12
W-0
11
W-0
10
W-0
9
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
8
7
6
5
4
3
2
1
0
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Table 36. Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR
Bit
31
30
Associated LSU
LSU4
Interrupt Condition
Packet not sent due to unavailable outbound credit at given priority
LSU4
Retry Doorbell response received or Atomic test-and-swap was not allowed (semaphore in
use)
29
28
27
26
25
24
23
22
LSU4
LSU4
LSU4
LSU4
LSU4
LSU4
LSU3
LSU3
Transaction was not sent due to DMA data transfer error
Transaction timeout occurred
Transaction was not sent due to unsupported transaction type or invalid field encoding
Transaction was not sent due to Xoff condition
Non-posted transaction received ERROR response, or error in response payload
Transaction complete, No errors (posted/non-posted)(1)
Packet not sent due to unavailable outbound credit at given priority
Retry Doorbell response received or Atomic test-and-swap was not allowed (semaphore in
use)
21
20
19
18
17
16
15
14
LSU3
LSU3
LSU3
LSU3
LSU3
LSU3
LSU2
LSU2
Transaction was not sent due to DMA data transfer error
Transaction timeout occurred
Transaction was not sent due to unsupported transaction type or invalid field encoding
Transaction was not sent due to Xoff condition
Non-posted transaction received ERROR response, or error in response payload
Transaction complete, No errors (posted/non-posted)(1)
Packet not sent due to unavailable outbound credit at given priority
Retry Doorbell response received or Atomic test-and-swap was not allowed (semaphore in
use)
13
12
11
10
9
LSU2
LSU2
LSU2
LSU2
LSU2
LSU2
LSU1
Transaction was not sent due to DMA data transfer error
Transaction timeout occurred
Transaction was not sent due to unsupported transaction type or invalid field encoding
Transaction was not sent due to Xoff condition
Non-posted transaction received ERROR response, or error in response payload
Transaction complete, No errors (posted/non-posted)(1)
Packet not sent due to unavailable outbound credit at given priority
8
7
(1)
Enable for this interrupt is ultimately controlled by the Interrupt Req register bit of LSUn_REG4. This allows enabling/disabling
on a per request basis. For optimum LSU performance, interrupt pacing should not be used on the LSU interrupts. Section 4.7
describes interrupt pacing.
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Interrupt Conditions
Table 36. Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR (continued)
Bit
Associated LSU
Interrupt Condition
6
LSU1
Retry Doorbell response received or Atomic test-and-swap was not allowed (semaphore in
use)
5
4
3
2
1
0
LSU1
LSU1
LSU1
LSU1
LSU1
LSU1
Transaction was not sent due to DMA data transfer error
Transaction timeout occurred
Transaction was not sent due to unsupported transaction type or invalid field encoding
Transaction was not sent due to Xoff condition
Non-posted transaction received ERROR response, or error in response payload
Transaction complete, No errors (posted/non-posted)(1)
4.3.4
Error, Reset, and Special Event Interrupt Condition Status and Clear Registers
The ICSR and the ICCR for the SRIO ports are shown in Figure 53. As described in Table 37, each of the
nonreserved status and clear bits corresponds to a particular interrupt condition in one or more of the
SRIO ports. The ICS bits of ERR_RST_EVNT_ICSR indicate the occurrence of the conditions. The ICC
bits of ERR_RST_EVNT_ICCR are used to clear the corresponding ICS bits.
Figure 53. Error, Reset, and Special Event Interrupt Condition Status and Clear Registers
Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) (Address Offset 0270h)
31
17
16
ICS16
R-0
Reserved
R-0
15
12
11
ICS11 ICS10 ICS9
R-0 R-0 R-0
10
9
8
7
3
2
1
0
Reserved
R-0
ICS8
R-0
Reserved
R-0
ICS2
R-0
ICS1
R-0
ICS0
R-0
Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) (Address Offset 0278h)
31
17
16
Reserved
R-0
ICC16
W-0
15
12
11
ICC11 ICC10 ICC9
W-0 W-0 W-0
10
9
8
7
3
2
1
0
Reserved
R-0
ICC8
W-0
Reserved
R-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Table 37. Interrupt Conditions Shown in ERR_RST_EVNT_ICSR and Cleared
With ERR_RST_EVNT_ICCR
Bit
31–17
16
Interrupt Condition
Reserved
Device reset interrupt from any port
Reserved
15–12
11
Port 3 error (TMS320TCI6482 Only)
Port 2 error (TMS320TCI6482 Only)
Port 1 error
10
9
8
Port 0 error
7–3
2
Reserved
Logical layer error management event capture
Port-write-in request received on any port
Multi-cast event control symbol interrupt received on any port
1
0
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The interrupt status bits found in the ERR_RST_EVNT (0x0270) can be cleared by writing to the ICCR
register (0x0278) in the same manner as other interrupts. However, in order for new event detection and
interrupt generation to occur for these special interrupts, additional register bits must be cleared. The
following table notes the additional interrupt source register bits that need to be cleared and the
appropriated sequence. These are all the bits that can cause the ERR_RST_EVNT status bits to be set
Table 38. Interrupt Clearing Sequence for Special Event Interrupts
Interrupt Function
1st Step
2 nd Step
3rd Step
Multicast Event Control Symbol Write 1 to clear:
Write 1 to clear:
Offset 0x12004
SP_IP_MODE[4]
Write 1 to clear:
Offset 0x12004
SP_IP_MODE[0]
received on any port
Offset 0x0278
ERR_RST_EVNT_ICCR[0]
Write 1 to clear:
Port Write In Request received
on any port
Offset 0x0278
ERR_RST_EVNT_ICCR[1]
Write 1 to clear:
Port 0 Error
Write 1 to clear any of the
following possible bits:
Write 1 to clear:
Offset 0x0278
Offset 0x2040
Offset 0x14004
ERR_RST_EVNT_ICCR[8]
SP0_ERR_STAT[2] – Fatal
error
SP0_CTL_INDEP[6]
SP0_ERR_STAT[25] – Failed
Threshold
SP0_ERR_STAT[24] –
Degraded Threshold
Offset 0x14004
SP0_CTL_INDEP[20] – Illegal
Transaction
SP0_CTL_INDEP[16] – Max
Retry Error
Port 1 Error
Write 1 to clear:
Write 1 to clear any of the
following possible bits:
Write 1 to clear:
Offset 0x0278
Offset 0x2080
Offset 0x14104
ERR_RST_EVNT_ICCR[9]
SP1_ERR_STAT[2] – Fatal
error
SP1_CTL_INDEP[6]
SP1_ERR_STAT[25] – Failed
Threshold
SP1_ERR_STAT[24] –
Degraded Threshold
Offset 0x14104
SP1_CTL_INDEP[20] – Illegal
Transaction
SP1_CTL_INDEP[16] – Max
Retry Error
Port 2 Error
(TMS320TCI6482 Only)
Write 1 to clear:
Write 1 to clear any of the
following possible bits:
Write 1 to clear:
Offset 0x0278
Offset 0x20C0
Offset 0x14204
ERR_RST_EVNT_ICCR[10]
SP2_ERR_STAT[2] – Fatal
error
SP2_CTL_INDEP[6]
SP2_ERR_STAT[25] – Failed
Threshold
SP2_ERR_STAT[24] –
Degraded Threshold
Offset 0x14204
SP2_CTL_INDEP[20] – Illegal
Transaction
SP2_CTL_INDEP[16] – Max
Retry Error
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Table 38. Interrupt Clearing Sequence for Special Event Interrupts (continued)
Interrupt Function
1st Step
2 nd Step
3rd Step
Port 3 Error
(TMS320TCI6482 Only)
Write 1 to clear:
Write 1 to clear any of the
following possible bits:
Write 1 to clear:
Offset 0x0278
Offset 0x2100
Offset 0x14304
ERR_RST_EVNT_ICCR[11]
SP3_ERR_STAT[2] – Fatal
error
SP_CTL_INDEP[6]
SP3_ERR_STAT[25] – Failed
Threshold
SP3_ERR_STAT[24] –
Degraded Threshold
Offset 0x14304
SP3_CTL_INDEP[20] – Illegal
Transaction
SP3_CTL_INDEP[16] – Max
Retry Error
Device Reset
Write 1 to clear:
Write 1 to clear:
Offset 0x12004
SP_IP_MODE[2]
Offset 0x0278
ERR_RST_EVNT_ICCR[16]
4.4 Interrupt Condition Routing Registers
The interrupt conditions are programmable to select the interrupt output that will be driven. Using the
interrupt condition routing registers (ICRRs), software can independently route each interrupt request to
any of the interrupt destinations supported by the device. For example, a quad core device may support
four CPU servicing interrupt destinations, one per core (INTDST0 for Core0, INTDST1 for Core1,
INTDST2 for Core2, and INTDST3 for Core3). In addition, INTDST4 may be globally routed to all cores
and provide notification of a change in the one ICSR, while INTDST5 may be globally routed to all cores
and provide notification of a change in a different ICSR. The routing defaults for an interrupt condition
Table 39. Interrupt Condition Routing Options
Field
Access
Reset Value
Value Function
ICRx
R
0000b
0000b Routed to INTDST0
0001b Routed to INTDST1
0010b Routed to INTDST2
0011b Routed to INTDST3
0100b Routed to INTDST4
0101b Routed to INTDST5
0110b Routed to INTDST6
0111b Routed to INTDST7
1111b No interrupt destination, interrupt source disabled
other
Reserved
4.4.1
Doorbell Interrupt Condition Routing Registers
Figure 54 shows the interrupt condition routing registers for Doorbell 0. The other doorbell ICRRs have the
same bit field map, with the following addresses:
•
•
•
DOORBELL1_ICRR and DOORBELL1_ICCR2 (Address offsets 0290h and 0294h)
DOORBELL2_ICRR and DOORBELL2_ICRR2 (Address offset 02A0h and 02A4h)
DOORBELL3_ICRR and DOORBELL3_ICRR2 (Address offset 02B0h and 02B4h)
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When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requests
to interrupt destinations. For example, if ICS6 = 1 in DOORBELL2_ICSR and ICR6 = 0010b in
DOORBELL2_ICRR, the interrupt request from Doorbell 2, bit 6 is sent to interrupt destination 2.
Figure 54. Doorbell 0 Interrupt Condition Routing Registers
Doorbell 0 Interrupt Condition Routing Register (DOORBELL0_ICRR) (Address Offset 0280h)
31
28 27
24 23
20 19
16
0
ICR7
ICR6
ICR5
ICR4
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR3
ICR2
ICR1
ICR0
R/W-0000
R/W-0000
R/W-0000
R/W-0000
Doorbell 0 Interrupt Condition Routing Register 2 (DOORBELL0_ICRR2) (Address Offset 0284h)
31
28 27
24 23
20 19
16
0
ICR15
ICR14
ICR13
ICR12
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR11
ICR10
ICR9
ICR8
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LEGEND: R/W = Read/Write; -n = Value after reset
4.4.1.1
CPPI Interrupt Condition Routing Registers
route queue interrupts to interrupt destinations. For example, if ICS6 = 1 in RX_CPPI_ICSR and ICR6 =
0010b in RX_CPPI_ICRR, the interrupt request from RX buffer descriptor queue 6 is sent to interrupt
destination 2. Similarly, if ICS6 = 1 in TX_CPPI_ICSR and ICR6 = 0011b in TX_CPPI_ICRR, the interrupt
request from TX buffer descriptor queue 6 is sent to interrupt destination 3.
Figure 55. RX CPPI Interrupt Condition Routing Registers
RX CPPI Interrupt Condition Routing Register (RX_CPPI_ICRR) (Address Offset 02C0h)
31
28 27
24 23
20 19
16
0
ICR7
ICR6
ICR5
ICR4
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR3
ICR2
ICR1
ICR0
R/W-0000
R/W-0000
R/W-0000
R/W-0000
RX CPPI Interrupt Condition Routing Register 2 (RX_CPPI_ICRR2) (Address Offset 02C4h)
31
28 27
24 23
20 19
16
0
ICR15
ICR14
ICR13
ICR12
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR11
ICR10
ICR9
ICR8
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LEGEND: R/W = Read/Write; -n = Value after reset
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Figure 56. TX CPPI Interrupt Condition Routing Registers
TX CPPI Interrupt Condition Routing Register (TX_CPPI_ICRR) (Address Offset 02D0h)
31
28 27
24 23
20 19
16
ICR7
ICR6
ICR5
ICR4
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
0
ICR3
ICR2
ICR1
ICR0
R/W-0000
R/W-0000
R/W-0000
R/W-0000
TX CPPI Interrupt Condition Routing Register 2 (TX_CPPI_ICRR2) (Address Offset 02D4h)
31
28 27
24 23
20 19
16
ICR15
ICR14
ICR13
ICR12
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
0
ICR11
ICR10
ICR9
ICR8
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LEGEND: R/W = Read/Write; -n = Value after reset
4.4.1.2
LSU Interrupt Condition Routing Registers
Figure 57 shows the ICRRs for the LSU interrupt requests. These registers route LSU interrupt requests to
interrupt destinations. For example, if ICS4 = 1 in LSU_ICSR and ICR4 = 0000b in LSU_ICRR0, LSU1
has generated a transaction-timeout interrupt request, and that request is routed to interrupt destination 0.
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Figure 57. LSU Interrupt Condition Routing Registers
LSU Interrupt Condition Routing Register 0 (LSU_ICRR0) (Address Offset 02E0h)
31
15
28 27
24 23
20 19
16
0
ICR7
ICR6
ICR5
ICR4
R/W-0000
R/W-0000
R/W-0000
R/W-0000
12 11
8
7
4
3
ICR3
ICR2
ICR1
ICR0
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LSU Interrupt Condition Routing Register 1 (LSU_ICRR1) (Address Offset 02E4h)
31
28 27
24 23
20 19
16
0
ICR15
ICR14
ICR13
ICR12
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR11
ICR10
ICR9
ICR8
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LSU Interrupt Condition Routing Register 2 (LSU_ICRR2) (Address Offset 02E8h)
31
28 27
24 23
20 19
16
0
ICR23
ICR22
ICR21
ICR20
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR19
ICR18
ICR17
ICR16
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LSU Interrupt Condition Routing Register 3 (LSU_ICRR3) (Address Offset 02ECh)
31
28 27
24 23
20 19
16
0
ICR31
ICR30
ICR29
ICR28
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR27
ICR26
ICR25
ICR24
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LEGEND: R/W = Read/Write; -n = Value after reset
4.4.1.3
Error, Reset, and Special Event Interrupt Condition Routing Registers
The ICRRs shown in Figure 58 route port interrupt requests to interrupt destinations. For example, if
ICS8 = 1 in ERR_RST_EVNT_ICSR and ICR8 = 0001b in ERR_RST_EVNT_ICRR2, port 0 has generated
an error interrupt request, and that request is routed to interrupt destination 1.
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Figure 58. Error, Reset, and Special Event Interrupt Condition Routing Registers
Error, Reset, and Special Event ICRR (ERR_RST_EVNT_ICRR) (Address Offset 02F0h)
31
Reserved
R-0
12 11
8
7
4
4
4
3
3
3
0
Reserved
R-0
ICR2
ICR1
ICR0
R/W-0000
R/W-0000
R/W-0000
Error, Reset, & Special Event ICRR 2 (ERR_RST_EVNT_ICRR2) (Address Offset 02F4h)
31
16
Reserved
R-0
15
12 11
8
7
0
ICR11
ICR10
ICR9
ICR8
R/W-0000
R/W-0000
R/W-0000
R/W-0000
Error, Reset, and Special Event ICRR 3 (ERR_RST_EVNT_ICRR3) (Address Offset 02F8h)
31
Reserved
R-0
0
Reserved
ICR16
R-0
R/W-0000
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
4.5 Interrupt Status Decode Registers
There are 8 blocks of the ICSRs to indicate the source of a pending interrupt.
0x0200: Doorbell0 interrupts
0x0210: Doorbell1 interrupts
0x0220: Doorbell2 interrupts
0x0230: Doorbell3 interrupts
0x0240: RX CPPI interrupts
0x0250: TX CPPI interrupts
0x0260: LSU interrupts
0x0270: Error, Reset, and Special Event interrupts
To reduce the number of reads (up to 5 reads) required to find the source bit, an Interrupt Status Decode
Register (ISDR) is implemented for each supported physical interrupt destination. The device supports up
to eight interrupt destinations, INTDST0–INTDST7. The names of the ISDRs and their address offsets are:
•
•
•
•
•
•
•
•
INTDST0_DECODE (Address offset 0300h)
INTDST1_DECODE (Address offset 0304h)
INTDST2_DECODE (Address offset 0308h)
INTDST3_DECODE (Address offset 030Ch)
INTDST4_DECODE (Address offset 0310h)
INTDST5_DECODE (Address offset 0314h)
INTDST6_DECODE (Address offset 0318h)
INTDST7_DECODE (Address offset 031Ch)
Aside from supporting different interrupt destinations, the ISDRs are the same in content and functionality.
The register fields are shown in Figure 59. Figure 60 shows which interrupt sources can be mapped to
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each bit in the ISDR. Bits within the LSU interrupt condition status register (ICSR) are logically grouped for
a given core and ORed together into a single bit (bit 31) of the decode register. Similarly, the bits within
the Error, Reset, and Special Event ICSR are ORed together into bit 30 of the decode register. The TX
CPPI and RX CPPI interrupt sources (one for each buffer descriptor queue) can be mapped to bits 31–16
An interrupt source is mapped to ISDR bits only if the ICRR for that interrupt source routes it to the
corresponding interrupt destination. When multiple interrupt sources are mapped to the same bit, the bit
status is a logical OR of those interrupt sources. The mapping of interrupt source bits to decode bits is
fixed and is not programmable.
Figure 59. Interrupt Status Decode Register (INTDSTn_DECODE)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ISD31 ISD30 ISD29 ISD28 ISD27 ISD26 ISD25 ISD24 ISD23 ISD22 ISD21 ISD20 ISD19 ISD18 ISD17 ISD16
R-0
15
R-0
14
R-0
13
R-0
12
R-0
11
R-0
10
R-0
9
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
8
7
6
5
4
3
2
1
0
ISD15 ISD14 ISD13 ISD12 ISD11 ISD10 ISD9
R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = Value after reset
ISD8
R-0
ISD7
R-0
ISD6
R-0
ISD5
R-0
ISD4
R-0
ISD3
R-0
ISD2
R-0
ISD1
R-0
ISD0
R-0
Figure 60. Interrupt Sources Assigned to ISDR Bits
A
B
Please note that bits 0 through 15 of this ICSR correspond to bits 31 through 16 of the ISDR. For example, bit 15 of
the ICSR corresponds to bit 31 of the ISDR, and so on.
Please note that bits 15 through 0 of this ICSR correspond to bits 15 through 0 of the ISDR. For example, bit 15 of
the ICSR corresponds to bit 15 of the ISDR, and so on.
As an example of reading an ISDR, if bit 29 of the ISDR is set, this indicates that there is a pending
interrupt on either the TX CPPI queue 2 or RX CPPI queue 2. Figure 61 illustrates the decode routing for
this example.
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Figure 61. Example Diagram of Interrupt Status Decode Register Mapping
The following are suggestions for minimizing the number of register reads to identifying the interrupt
source:
•
Dedicate each doorbell ICSR to one core. The CPU can then determine the interrupt source from a
single read of the decode register.
•
Assign the RX and TX CPPI queues orthogonally to different cores. The CPU can then determine the
interrupt source from a single read of the decode registers. The only exceptions to this are bits 31 and
30, which are also logically ORed with LSU and port interrupt sources.
4.6 Interrupt Generation
Interrupts are triggered on a 0-to-1 logic-signal transition. Regardless of the interrupt sources, the physical
interrupts are set only when the total number of set ICSR bits transitions from none to one or more. The
peripheral is responsible for setting the correct bit within the ICSR. The ICRR register maps the pending
interrupt request to the appropriate physical interrupt line. The corresponding CPU is interrupted and
reads the ISDR and ICSR registers to determine the interrupt source and appropriate action. Interrupt
4.7 Interrupt Pacing
The rate at which an interrupt can be generated is controllable for each physical interrupt destination. Rate
control is implemented with a programmable down-counter. The load value of the counter is written by the
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immediately starts down-counting each time the CPU writes these registers. When the rate control counter
register is written, and the counter value reaches zero (note that the CPU may write zero immediately for
a zero count), the interrupt pulse generation logic is allowed to fire a single pulse if any bits in the
corresponding ICSR register bits are set (or become set after the zero count is reached). The counter
remains at zero. When the single pulse is generated, the logic will not generate another pulse, regardless
of interrupt status changes, until the rate control counter register is written again.
An interrupt rate control register (INTDSTn_RATE_CNTL) is implemented for each supported physical
interrupt destination. The device supports up to eight interrupt destinations, INTDST0–INTDST7. The
names of the registers and their address offsets are:
•
•
•
•
•
•
•
•
INTDST0_RATE_CNTL (Address offset 0320h)
INTDST1_RATE_CNTL (Address offset 0324h)
INTDST2_RATE_CNTL (Address offset 0328h)
INTDST3_RATE_CNTL (Address offset 032Ch)
INTDST4_RATE_CNTL (Address offset 0330h)
INTDST5_RATE_CNTL (Address offset 0334h)
INTDST6_RATE_CNTL (Address offset 0338h)
INTDST7_RATE_CNTL (Address offset 033Ch)
If interrupt pacing is not desired for a particular interrupt destination, the CPU must still write 00000000h
into the INTDSTn_RATE_CNTL register after clearing the corresponding ICSR bits to acknowledge the
physical interrupt. If an ICSR is not mapped to an interrupt destination, pending interrupt bits within the
ICSR maintain current status. When enabled, the interrupt logic re-evaluates all pending interrupts and
re-pulses the interrupt signal if any interrupt conditions are pending. The down-counter is based on the
DMA clock cycle.
Figure 62. INTDSTn_RATE_CNTL Interrupt Rate Control Register
31
0
32-bit Count Down Value
R/W-0
LEGEND: R/W = Read/Write; -n = Value after reset
4.8 Interrupt Handling
Interrupts are either signaled externally through RapidIO packets, or internally by state machines in the
peripheral. CPU servicing interrupts are signaled externally by the DOORBELL RapidIO packet in direct
I/O mode, or internally by the CPPI module in the message passing mode. Error Status interrupts are
signaled when error counting logic within the peripheral have reached their thresholds. In either case, it is
the peripheral that signals the interrupt and sets the corresponding status bits.
When the CPU is interrupted, it reads the ICSR registers to determine the source of the interrupt and
appropriate action to take. For example, if it is a DOORBELL interrupt, the CPU will read from an L2
address that is specified by its circular buffer read pointer that is managed by software. There may be
more than one circular buffer for each core. The correct circular buffer to read from and increment
depends on the bit set in the ICSR register. The CPU then clears the status bit.
For Error Status interrupts, the peripheral must indicate to all the CPUs that one of the link ports has
reached the error threshold. In this case, the peripheral sets the status bit indicating degraded or failed
limits have been reached, and an interrupt is generated to each core through the ICRR mapping. The
cores can then scan the ICSR registers to determine the port with the error problems. Further action can
then be taken as determined by the application.
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Interrupt Handler
temp1 = SRIO_REGS->TX_CPPI_ICSR;
if ((temp1 & 0x00000001) == 0x00000001)
{
SRIO_REGS->Queue0_TXDMA_CP = (int )TX_DESCP0_0;
}
temp2 = SRIO_REGS->RX_CPPI_ICSR;
if ((temp2 & 0x00000001) == 0x00000001)
{
SRIO_REGS->Queue0_RXDMA_CP = (int )RX_DESCP0_0;
}
SRIO_REGS->DOORBELL0_ICCR=0xFFFFFFFF;
SRIO_REGS->DOORBELL1_ICCR=0xFFFFFFFF;
SRIO_REGS->DOORBELL2_ICCR=0xFFFFFFFF;
SRIO_REGS->DOORBELL3_ICCR=0xFFFFFFFF;
SRIO_REGS->INTDST0_Rate_CNTL=1;
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SRIO Registers
5
SRIO Registers
5.1 Introduction
(SRIO) peripheral. See the device-specific data manual for the exact memory addresses of these
registers.
Table 40. Serial RapidIO (SRIO) Registers
Offset
0000h
0004h
0020h
0030h
0034h
0038h
003Ch
0040h
0044h
0048h
004Ch
0050h
0054h
0058h
005Ch
0060h
0064h
0068h
006Ch
0070h
0074h
0078h
007Ch
0080h
0084h
0090h
0094h
0098h
009Ch
00A0h
00A4h
00A8h
00ACh
0100h
0104h
0108h
010Ch
0110h
0114h
0118h
Acronym
Register Description
Section
PID
Peripheral Identification Register
Peripheral Control Register
Section 5.2
Section 5.3
Section 5.4
Section 5.5
Section 5.6
Section 5.7
Section 5.8
Section 5.7
Section 5.8
Section 5.7
Section 5.8
Section 5.7
Section 5.8
Section 5.7
Section 5.8
Section 5.7
Section 5.8
Section 5.7
Section 5.8
Section 5.7
Section 5.8
Section 5.7
Section 5.8
Section 5.9
Section 5.10
Section 5.11
Section 5.12
Section 5.11
Section 5.12
Section 5.11
Section 5.12
Section 5.11
Section 5.12
Section 5.13
Section 5.13
Section 5.13
Section 5.13
Section 5.14
Section 5.14
Section 5.14
PCR
PER_SET_CNTL
GBL_EN
Peripheral Settings Control Register
Peripheral Global Enable Register
Peripheral Global Enable Status
Block Enable 0
GBL_EN_STAT
BLK0_EN
BLK0_EN_STAT
BLK1_EN
Block Enable Status 0
Block Enable 1
BLK1_EN_STAT
BLK2_EN
Block Enable Status 1
Block Enable 2
BLK2_EN_STAT
BLK3_EN
Block Enable Status 2
Block Enable 3
BLK3_EN_STAT
BLK4_EN
Block Enable Status 3
Block Enable 4
BLK4_EN_STAT
BLK5_EN
Block Enable Status 4
Block Enable 5
BLK5_EN_STAT
BLK6_EN
Block Enable Status 5
Block Enable 6
BLK6_EN_STAT
BLK7_EN
Block Enable Status 6
Block Enable 7
BLK7_EN_STAT
BLK8_EN
Block Enable Status 7
Block Enable 8
BLK8_EN_STAT
DEVICEID_REG1
DEVICEID_REG2
PF_16B_CNTL0
PF_8B_CNTL0
PF_16B_CNTL1
PF_8B_CNTL1
PF_16B_CNTL2
PF_8B_CNTL2
PF_16B_CNTL3
PF_8B_CNTL3
SERDES_CFGRX0_CNTL
SERDES_CFGRX1_CNTL
SERDES_CFGRX2_CNTL
SERDES_CFGRX3_CNTL
SERDES_CFGTX0_CNTL
SERDES_CFGTX1_CNTL
SERDES_CFGTX2_CNTL
Block Enable Status 8
RapidIO DEVICEID1 Register
RapidIO DEVICEID2 Register
Packet Forwarding Register 0 for 16-bit DeviceIDs
Packet Forwarding Register 0 for 8-bit DeviceIDs
Packet Forwarding Register 1 for 16-bit DeviceIDs
Packet Forwarding Register 1 for 8-bit DeviceIDs
Packet Forwarding Register 2 for 16-bit DeviceIDs
Packet Forwarding Register 2 for 8-bit DeviceIDs
Packet Forwarding Register 3 for 16-bit DeviceIDs
Packet Forwarding Register 3 for 8-bit DeviceIDs
SERDES Receive Channel Configuration Register 0
SERDES Receive Channel Configuration Register 1
SERDES Receive Channel Configuration Register 2
SERDES Receive Channel Configuration Register 3
SERDES Transmit Channel Configuration Register 0
SERDES Transmit Channel Configuration Register 1
SERDES Transmit Channel Configuration Register 2
102
Serial RapidIO (SRIO)
SPRUE13A–September 2006
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SRIO Registers
Table 40. Serial RapidIO (SRIO) Registers (continued)
Offset
011Ch
0120h
0124h
0128h
012Ch
0200h
0208h
0210h
0218h
0220h
0228h
0230h
0238h
0240h
0248h
0250h
0258h
0260h
0268h
0270h
Acronym
Register Description
Section
SERDES_CFGTX3_CNTL
SERDES_CFG0_CNTL
SERDES_CFG1_CNTL
SERDES_CFG2_CNTL
SERDES_CFG3_CNTL
DOORBELL0_ICSR
DOORBELL0_ICCR
DOORBELL1_ICSR
DOORBELL1_ICCR
DOORBELL2_ICSR
DOORBELL2_ICCR
DOORBELL3_ICSR
DOORBELL3_ICCR
RX_CPPI_ICSR
SERDES Transmit Channel Configuration Register 3
SERDES Macro Configuration Register 0
Section 5.14
Section 5.15
Section 5.15
Section 5.15
Section 5.15
Section 5.16
Section 5.17
Section 5.16
Section 5.17
Section 5.16
Section 5.17
Section 5.16
Section 5.17
Section 5.18
Section 5.19
Section 5.20
Section 5.21
Section 5.22
Section 5.23
Section 5.24
SERDES Macro Configuration Register 1
SERDES Macro Configuration Register 2
SERDES Macro Configuration Register 3
DOORBELL Interrupt Condition Status Register 0
DOORBELL Interrupt Condition Clear Register 0
DOORBELL Interrupt Condition Status Register 1
DOORBELL Interrupt Condition Clear Register 1
DOORBELL Interrupt Condition Status Register 2
DOORBELL Interrupt Condition Clear Register 2
DOORBELL Interrupt Condition Status Register 3
DOORBELL Interrupt Condition Clear Register 3
RX CPPI Interrupt Condition Status Register
RX CPPI Interrupt Condition Clear Register
TX CPPI Interrupt Condition Status Register
TX CPPI Interrupt Condition Clear Register
LSU Interrupt Condition Status Register
RX_CPPI_ICCR
TX_CPPI_ICSR
TX_CPPI_ICCR
LSU_ICSR
LSU_ICCR
LSU Interrupt Condition Clear Register
ERR_RST_EVNT_ICSR
Error, Reset, and Special Event Interrupt Condition Status
Register
0278h
ERR_RST_EVNT_ICCR
Error, Reset, and Special Event Interrupt Condition Clear
Register
Section 5.25
0280h
0284h
0290h
0294h
02A0h
02A4h
02B0h
02B4h
02C0h
02C4h
02D0h
02D4h
02E0h
02E4h
02E8h
02ECh
02F0h
DOORBELL0_ICRR
DOORBELL0_ICRR2
DOORBELL1_ICRR
DOORBELL1_ICRR2
DOORBELL2_ICRR
DOORBELL2_ICRR2
DOORBELL3_ICRR
DOORBELL3_ICRR2
RX_CPPI _ICRR
RX_CPPI _ICRR2
TX_CPPI _ICRR
TX_CPPI _ICRR2
LSU_ICRR0
DOORBELL0 Interrupt Condition Routing Register
DOORBELL 0 Interrupt Condition Routing Register 2
DOORBELL1 Interrupt Condition Routing Register
DOORBELL 1 Interrupt Condition Routing Register 2
DOORBELL2 Interrupt Condition Routing Register
DOORBELL 2 Interrupt Condition Routing Register 2
DOORBELL3 Interrupt Condition Routing Register
DOORBELL 3 Interrupt Condition Routing Register 2
Receive CPPI Interrupt Condition Routing Register
Receive CPPI Interrupt Condition Routing Register 2
Transmit CPPI Interrupt Condition Routing Register
Transmit CPPI Interrupt Condition Routing Register 2
LSU Interrupt Condition Routing Register 0
Section 5.26
Section 5.26
Section 5.26
Section 5.26
Section 5.26
Section 5.26
Section 5.26
Section 5.26
Section 5.27
Section 5.27
Section 5.28
Section 5.28
Section 5.29
Section 5.29
Section 5.29
Section 5.29
Section 5.30
LSU_ICRR1
LSU Interrupt Condition Routing Register 1
LSU_ICRR2
LSU Interrupt Condition Routing Register 2
LSU_ICRR3
LSU Interrupt Condition Routing Register 3
ERR_RST_EVNT_ICRR
Error, Reset, and Special Event Interrupt Condition Routing
Register
02F4h
02F8h
ERR_RST_EVNT_ICRR2
ERR_RST_EVNT_ICRR3
Error, Reset, and Special Event Interrupt Condition Routing
Register 2
Section 5.30
Section 5.30
Error, Reset, and Special Event Interrupt Condition Routing
Register 3
0300h
0304h
0308h
INTDST0_DECODE
INTDST1_DECODE
INTDST2_DECODE
INTDST Interrupt Status Decode Register 0
INTDST Interrupt Status Decode Register 1
INTDST Interrupt Status Decode Register 2
Section 5.31
Section 5.31
Section 5.31
SPRUE13A–September 2006
Serial RapidIO (SRIO)
103
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SRIO Registers
Table 40. Serial RapidIO (SRIO) Registers (continued)
Offset
030Ch
0310h
0314h
0318h
031Ch
0320h
0324h
0328h
032Ch
0330h
0334h
0338h
033Ch
0400h
0404h
0408h
040Ch
0410h
0414h
0418h
041Ch
0420h
0424h
0428h
042Ch
0430h
0434h
0438h
043Ch
0440h
0444h
0448h
044Ch
0450h
0454h
0458h
045Ch
0460h
0464h
0468h
046Ch
0470h
0474h
0478h
047Ch
0500h
Acronym
Register Description
Section
INTDST3_DECODE
INTDST4_DECODE
INTDST5_DECODE
INTDST6_DECODE
INTDST7_DECODE
INTDST0_RATE_CNTL
INTDST1_RATE_CNTL
INTDST2_RATE_CNTL
INTDST3_RATE_CNTL
INTDST4_RATE_CNTL
INTDST5_RATE_CNTL
INTDST6_RATE_CNTL
INTDST7_RATE_CNTL
LSU1_REG0
INTDST Interrupt Status Decode Register 3
INTDST Interrupt Status Decode Register 4
INTDST Interrupt Status Decode Register 5
INTDST Interrupt Status Decode Register 6
INTDST Interrupt Status Decode Register 7
INTDST Interrupt Rate Control Register 0
INTDST Interrupt Rate Control Register 1
INTDST Interrupt Rate Control Register 2
INTDST Interrupt Rate Control Register 3
INTDST Interrupt Rate Control Register 4
INTDST Interrupt Rate Control Register 5
INTDST Interrupt Rate Control Register 6
INTDST Interrupt Rate Control Register 7
LSU1 Control Register 0
Section 5.31
Section 5.31
Section 5.31
Section 5.31
Section 5.31
Section 5.32
Section 5.32
Section 5.32
Section 5.32
Section 5.32
Section 5.32
Section 5.32
Section 5.32
Section 5.33
Section 5.34
Section 5.35
Section 5.36
Section 5.37
Section 5.38
Section 5.39
Section 5.40
Section 5.33
Section 5.34
Section 5.35
Section 5.36
Section 5.37
Section 5.38
Section 5.39
Section 5.40
Section 5.33
Section 5.34
Section 5.35
Section 5.36
Section 5.37
Section 5.38
Section 5.39
Section 5.40
Section 5.33
Section 5.34
Section 5.35
Section 5.36
Section 5.37
Section 5.39
Section 5.40
Section 5.41
LSU1_REG1
LSU1 Control Register 1
LSU1_REG2
LSU1 Control Register 2
LSU1_REG3
LSU1 Control Register 3
LSU1_REG4
LSU1 Control Register 4
LSU1_REG5
LSU1 Control Register 5
LSU1_REG6
LSU1 Control Register 6
LSU1_FLOW_MASKS
LSU2_REG0
LSU1 Congestion Control Flow Mask Register
LSU2 Control Register 0
LSU2_REG1
LSU2 Control Register 1
LSU2_REG2
LSU2 Control Register 2
LSU2_REG3
LSU2 Control Register 3
LSU2_REG4
LSU2 Control Register 4
LSU2_REG5
LSU2 Control Register 5
LSU2_REG6
LSU2 Control Register 6
LSU2_FLOW_MASKS1
LSU3_REG0
LSU2 Congestion Control Flow Mask Register
LSU3 Control Register 0
LSU3_REG1
LSU3 Control Register 1
LSU3_REG2
LSU3 Control Register 2
LSU3_REG3
LSU3 Control Register 3
LSU3_REG4
LSU3 Control Register 4
LSU3_REG5
LSU3 Control Register 5
LSU3_REG6
LSU3 Control Register 6
LSU3_FLOW_MASKS2
LSU4_REG0
LSU3 Congestion Control Flow Mask Register
LSU4 Control Register 0
LSU4_REG1
LSU4 Control Register 1
LSU4_REG2
LSU4 Control Register 2
LSU4_REG3
LSU4 Control Register 3
LSU4_REG4
LSU4 Control Register 4
LSU4_REG5
LSU4 Control Register 5
LSU4_REG6
LSU4 Control Register 6
LSU4_FLOW_MASKS3
QUEUE0_TXDMA_HDP
LSU4 Congestion Control Flow Mask Register
Queue Transmit DMA Head Descriptor Pointer Register 0
104
Serial RapidIO (SRIO)
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SRIO Registers
Table 40. Serial RapidIO (SRIO) Registers (continued)
Offset
0504h
0508h
050Ch
0510h
0514h
0518h
051Ch
0520h
0524h
0528h
052Ch
0530h
0534h
0538h
053Ch
0580h
0584h
0588h
058Ch
0590h
0594h
0598h
059Ch
05A0h
05A4h
05A8h
05ACh
05B0h
05B4h
05B8h
05BCh
0600h
0604h
0608h
060Ch
0610h
0614h
0618h
061Ch
0620h
0624h
0628h
062Ch
0630h
0634h
0638h
Acronym
Register Description
Section
QUEUE1_TXDMA_HDP
QUEUE2_TXDMA_HDP
QUEUE3_TXDMA_HDP
QUEUE4_TXDMA_HDP
QUEUE5_TXDMA_HDP
QUEUE6_TXDMA_HDP
QUEUE7_TXDMA_HDP
QUEUE8_TXDMA_HDP
QUEUE9_TXDMA_HDP
QUEUE10_TXDMA_HDP
QUEUE11_TXDMA_HDP
QUEUE12_TXDMA_HDP
QUEUE13_TXDMA_HDP
QUEUE14_TXDMA_HDP
QUEUE15_TXDMA_HDP
QUEUE0_TXDMA_CP
QUEUE1_TXDMA_CP
QUEUE2_TXDMA_CP
QUEUE3_TXDMA_CP
QUEUE4_TXDMA_CP
QUEUE5_TXDMA_CP
QUEUE6_TXDMA_CP
QUEUE7_TXDMA_CP
QUEUE8_TXDMA_CP
QUEUE9_TXDMA_CP
QUEUE10_TXDMA_CP
QUEUE11_TXDMA_CP
QUEUE12_TXDMA_CP
QUEUE13_TXDMA_CP
QUEUE14_TXDMA_CP
QUEUE15_TXDMA_CP
QUEUE0_RXDMA_HDP
QUEUE1_RXDMA_HDP
QUEUE2_RXDMA_HDP
QUEUE3_RXDMA_HDP
QUEUE4_RXDMA_HDP
QUEUE5_RXDMA_HDP
QUEUE6_RXDMA_HDP
QUEUE7_RXDMA_HDP
QUEUE8_RXDMA_HDP
QUEUE9_RXDMA_HDP
QUEUE10_RXDMA_HDP
QUEUE11_RXDMA_HDP
QUEUE12_RXDMA_HDP
QUEUE13_RXDMA_HDP
QUEUE14_RXDMA_HDP
Queue Transmit DMA Head Descriptor Pointer Register 1
Queue Transmit DMA Head Descriptor Pointer Register 2
Queue Transmit DMA Head Descriptor Pointer Register 3
Queue Transmit DMA Head Descriptor Pointer Register 4
Queue Transmit DMA Head Descriptor Pointer Register 5
Queue Transmit DMA Head Descriptor Pointer Register 6
Queue Transmit DMA Head Descriptor Pointer Register 7
Queue Transmit DMA Head Descriptor Pointer Register 8
Queue Transmit DMA Head Descriptor Pointer Register 9
Queue Transmit DMA Head Descriptor Pointer Register 10
Queue Transmit DMA Head Descriptor Pointer Register 11
Queue Transmit DMA Head Descriptor Pointer Register 12
Queue Transmit DMA Head Descriptor Pointer Register 13
Queue Transmit DMA Head Descriptor Pointer Register 14
Queue Transmit DMA Head Descriptor Pointer Register 15
Queue Transmit DMA Completion Pointer Register 0
Queue Transmit DMA Completion Pointer Register 1
Queue Transmit DMA Completion Pointer Register 2
Queue Transmit DMA Completion Pointer Register 3
Queue Transmit DMA Completion Pointer Register 4
Queue Transmit DMA Completion Pointer Register 5
Queue Transmit DMA Completion Pointer Register 6
Queue Transmit DMA Completion Pointer Register 7
Queue Transmit DMA Completion Pointer Register 8
Queue Transmit DMA Completion Pointer Register 9
Queue Transmit DMA Completion Pointer Register 10
Queue Transmit DMA Completion Pointer Register 11
Queue Transmit DMA Completion Pointer Register 12
Queue Transmit DMA Completion Pointer Register 13
Queue Transmit DMA Completion Pointer Register 14
Queue Transmit DMA Completion Pointer Register 15
Queue Receive DMA Head Descriptor Pointer Register 0
Queue Receive DMA Head Descriptor Pointer Register 1
Queue Receive DMA Head Descriptor Pointer Register 2
Queue Receive DMA Head Descriptor Pointer Register 3
Queue Receive DMA Head Descriptor Pointer Register 4
Queue Receive DMA Head Descriptor Pointer Register 5
Queue Receive DMA Head Descriptor Pointer Register 6
Queue Receive DMA Head Descriptor Pointer Register 7
Queue Receive DMA Head Descriptor Pointer Register 8
Queue Receive DMA Head Descriptor Pointer Register 9
Queue Receive DMA Head Descriptor Pointer Register 10
Queue Receive DMA Head Descriptor Pointer Register 11
Queue Receive DMA Head Descriptor Pointer Register 12
Queue Receive DMA Head Descriptor Pointer Register 13
Queue Receive DMA Head Descriptor Pointer Register 14
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.41
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.42
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
Section 5.43
SPRUE13A–September 2006
Serial RapidIO (SRIO)
105
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SRIO Registers
Table 40. Serial RapidIO (SRIO) Registers (continued)
Offset
063Ch
0680h
0684h
0688h
068Ch
0690h
0694h
0698h
069Ch
06A0h
06A4h
06A8h
06ACh
06B0h
06B4h
06B8h
06BCh
0700h
0704h
0708h
070Ch
0710h
0714h
0718h
071Ch
0720h
0740h
0744h
07E0h
07E4h
07E8h
07ECh
0800h
0804h
0808h
080Ch
0810h
0814h
0818h
081Ch
0820h
0824h
0828h
082Ch
0830h
0834h
Acronym
Register Description
Section
QUEUE15_RXDMA_HDP
QUEUE0_RXDMA_CP
QUEUE1_RXDMA_CP
QUEUE2_RXDMA_CP
QUEUE3_RXDMA_CP
QUEUE4_RXDMA_CP
QUEUE5_RXDMA_CP
QUEUE6_RXDMA_CP
QUEUE7_RXDMA_CP
QUEUE8_RXDMA_CP
QUEUE9_RXDMA_CP
QUEUE10_RXDMA_CP
QUEUE11_RXDMA_CP
QUEUE12_RXDMA_CP
QUEUE13_RXDMA_CP
QUEUE14_RXDMA_CP
QUEUE15_RXDMA_CP
TX_QUEUE_TEAR_DOWN
TX_CPPI_FLOW_MASKS0
TX_CPPI_FLOW_MASKS1
TX_CPPI_FLOW_MASKS2
TX_CPPI_FLOW_MASKS3
TX_CPPI_FLOW_MASKS4
TX_CPPI_FLOW_MASKS5
TX_CPPI_FLOW_MASKS6
TX_CPPI_FLOW_MASKS7
RX_QUEUE_TEAR_DOWN
RX_CPPI_CNTL
Queue Receive DMA Head Descriptor Pointer Register 15
Queue Receive DMA Completion Pointer Register 0
Queue Receive DMA Completion Pointer Register 1
Queue Receive DMA Completion Pointer Register 2
Queue Receive DMA Completion Pointer Register 3
Queue Receive DMA Completion Pointer Register 4
Queue Receive DMA Completion Pointer Register 5
Queue Receive DMA Completion Pointer Register 6
Queue Receive DMA Completion Pointer Register 7
Queue Receive DMA Completion Pointer Register 8
Queue Receive DMA Completion Pointer Register 9
Queue Receive DMA Completion Pointer Register 10
Queue Receive DMA Completion Pointer Register 11
Queue Receive DMA Completion Pointer Register 12
Queue Receive DMA Completion Pointer Register 13
Queue Receive DMA Completion Pointer Register 14
Queue Receive DMA Completion Pointer Register 15
Transmit Queue Teardown Register
Section 5.43
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.44
Section 5.45
Section 5.46
Section 5.46
Section 5.46
Section 5.46
Section 5.46
Section 5.46
Section 5.46
Section 5.46
Section 5.47
Section 5.48
Section 5.49
Section 5.49
Section 5.49
Section 5.49
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Transmit CPPI Supported Flow Mask Register 0
Transmit CPPI Supported Flow Mask Register 1
Transmit CPPI Supported Flow Mask Register 2
Transmit CPPI Supported Flow Mask Register 3
Transmit CPPI Supported Flow Mask Register 4
Transmit CPPI Supported Flow Mask Register 5
Transmit CPPI Supported Flow Mask Register 6
Transmit CPPI Supported Flow Mask Register 7
Receive Queue Teardown Register
Receive CPPI Control Register
TX_QUEUE_CNTL0
TX_QUEUE_CNTL1
TX_QUEUE_CNTL2
TX_QUEUE_CNTL3
RXU_MAP_L0
Transmit CPPI Weighted Round Robin Control Register 0
Transmit CPPI Weighted Round Robin Control Register 1
Transmit CPPI Weighted Round Robin Control Register 2
Transmit CPPI Weighted Round Robin Control Register 3
MailBox-to-Queue Mapping Register L0
RXU_MAP_H0
MailBox-to-Queue Mapping Register H0
RXU_MAP_L1
MailBox-to-Queue Mapping Register L1
RXU_MAP_H1
MailBox-to-Queue Mapping Register H1
RXU_MAP_L2
MailBox-to-Queue Mapping Register L2
RXU_MAP_H2
MailBox-to-Queue Mapping Register H2
RXU_MAP_L3
MailBox-to-Queue Mapping Register L3
RXU_MAP_H3
MailBox-to-Queue Mapping Register H3
RXU_MAP_L4
MailBox-to-Queue Mapping Register L4
RXU_MAP_H4
MailBox-to-Queue Mapping Register H4
RXU_MAP_L5
MailBox-to-Queue Mapping Register L5
RXU_MAP_H5
MailBox-to-Queue Mapping Register H5
RXU_MAP_L6
MailBox-to-Queue Mapping Register L6
RXU_MAP_H6
MailBox-to-Queue Mapping Register H6
106
Serial RapidIO (SRIO)
SPRUE13A–September 2006
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SRIO Registers
Table 40. Serial RapidIO (SRIO) Registers (continued)
Offset
0838h
083Ch
0840h
0844h
0848h
084Ch
0850h
0854h
0858h
085Ch
0860h
0864h
0868h
086Ch
0870h
0874h
0878h
087Ch
0880h
0884h
0888h
088Ch
0890h
0894h
0898h
089Ch
08A0h
08A4h
08A8h
08ACh
08B0h
08B4h
08B8h
08BCh
08C0h
08C4h
08C8h
Acronym
Register Description
Section
RXU_MAP_L7
RXU_MAP_H7
RXU_MAP_L8
RXU_MAP_H8
RXU_MAP_L9
RXU_MAP_H9
RXU_MAP_L10
RXU_MAP_H10
RXU_MAP_L11
RXU_MAP_H11
RXU_MAP_L12
RXU_MAP_H12
RXU_MAP_L13
RXU_MAP_H13
RXU_MAP_L14
RXU_MAP_H14
RXU_MAP_L15
RXU_MAP_H15
RXU_MAP_L16
RXU_MAP_H16
RXU_MAP_L17
RXU_MAP_H17
RXU_MAP_L18
RXU_MAP_H18
RXU_MAP_L19
RXU_MAP_H19
RXU_MAP_L20
RXU_MAP_H20
RXU_MAP_L21
RXU_MAP_H21
RXU_MAP_L22
RXU_MAP_H22
RXU_MAP_L23
RXU_MAP_H23
RXU_MAP_L24
RXU_MAP_H24
RXU_MAP_L25
MailBox-to-Queue Mapping Register L7
MailBox-to-Queue Mapping Register H7
MailBox-to-Queue Mapping Register L8
MailBox-to-Queue Mapping Register H8
MailBox-to-Queue Mapping Register L9
MailBox-to-Queue Mapping Register H9
MailBox-to-Queue Mapping Register L10
MailBox-to-Queue Mapping Register H10
MailBox-to-Queue Mapping Register L11
MailBox-to-Queue Mapping Register H11
MailBox-to-Queue Mapping Register L12
MailBox-to-Queue Mapping Register H12
MailBox-to-Queue Mapping Register L13
MailBox-to-Queue Mapping Register H13
MailBox-to-Queue Mapping Register L14
MailBox-to-Queue Mapping Register H14
MailBox-to-Queue Mapping Register L15
MailBox-to-Queue Mapping Register H15
MailBox-to-Queue Mapping Register L16
MailBox-to-Queue Mapping Register H16
MailBox-to-Queue Mapping Register L17
MailBox-to-Queue Mapping Register H17
MailBox-to-Queue Mapping Register L18
MailBox-to-Queue Mapping Register H18
MailBox-to-Queue Mapping Register L19
MailBox-to-Queue Mapping Register H19
MailBox-to-Queue Mapping Register L20
MailBox-to-Queue Mapping Register H20
MailBox-to-Queue Mapping Register L21
MailBox-to-Queue Mapping Register H21
MailBox-to-Queue Mapping Register L22
MailBox-to-Queue Mapping Register H22
MailBox-to-Queue Mapping Register L23
MailBox-to-Queue Mapping Register H23
MailBox-to-Queue Mapping Register L24
MailBox-to-Queue Mapping Register H24
MailBox-to-Queue Mapping Register L25
MailBox-to-Queue Mapping Register H25
MailBox-to-Queue Mapping Register L26
MailBox-to-Queue Mapping Register H26
MailBox-to-Queue Mapping Register L27
MailBox-to-Queue Mapping Register H27
MailBox-to-Queue Mapping Register L28
MailBox-to-Queue Mapping Register H28
MailBox-to-Queue Mapping Register L29
MailBox-to-Queue Mapping Register H29
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.50
08CCh RXU_MAP_H25
08D0h
08D4h
08D8h
RXU_MAP_L26
RXU_MAP_H26
RXU_MAP_L27
08DCh RXU_MAP_H27
08E0h
08E4h
08E8h
08ECh
RXU_MAP_L28
RXU_MAP_H28
RXU_MAP_L29
RXU_MAP_H29
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SRIO Registers
Table 40. Serial RapidIO (SRIO) Registers (continued)
Offset
08F0h
08F4h
08F8h
08FCh
0900h
0904h
0908h
090Ch
0910h
0914h
0918h
091Ch
0920h
0924h
0928h
092Ch
0930h
0934h
0938h
093Ch
1000h
1004h
1008h
100Ch
1010h
1018h
101Ch
104Ch
1058h
105Ch
1060h
1068h
106Ch
1100h
1120h
1124h
113Ch
1140h
1144h
1148h
1158h
115Ch
1160h
1164h
1168h
1178h
Acronym
Register Description
Section
RXU_MAP_L30
RXU_MAP_H30
RXU_MAP_L31
RXU_MAP_H31
FLOW_CNTL0
FLOW_CNTL1
FLOW_CNTL2
FLOW_CNTL3
FLOW_CNTL4
FLOW_CNTL5
FLOW_CNTL6
FLOW_CNTL7
FLOW_CNTL8
FLOW_CNTL9
FLOW_CNTL10
FLOW_CNTL11
FLOW_CNTL12
FLOW_CNTL13
FLOW_CNTL14
FLOW_CNTL15
DEV_ID
MailBox-to-Queue Mapping Register L30
MailBox-to-Queue Mapping Register H30
MailBox-to-Queue Mapping Register L31
MailBox-to-Queue Mapping Register H31
Flow Control Table Entry Register 0
Flow Control Table Entry Register 1
Flow Control Table Entry Register 2
Flow Control Table Entry Register 3
Flow Control Table Entry Register 4
Flow Control Table Entry Register 5
Flow Control Table Entry Register 6
Flow Control Table Entry Register 7
Flow Control Table Entry Register 8
Flow Control Table Entry Register 9
Flow Control Table Entry Register 10
Flow Control Table Entry Register 11
Flow Control Table Entry Register 12
Flow Control Table Entry Register 13
Flow Control Table Entry Register 14
Flow Control Table Entry Register 15
Device Identity CAR
Section 5.50
Section 5.50
Section 5.50
Section 5.50
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.51
Section 5.52
Section 5.53
Section 5.54
Section 5.55
Section 5.56
Section 5.57
Section 5.58
Section 5.59
Section 5.60
Section 5.61
Section 5.62
Section 5.63
Section 5.64
Section 5.65
Section 5.66
Section 5.67
Section 5.68
Section 5.69
Section 5.70
Section 5.71
Section 5.72
Section 5.73
Section 5.69
Section 5.70
Section 5.71
Section 5.72
DEV_INFO
Device Information CAR
ASBLY_ID
Assembly Identity CAR
ASBLY_INFO
PE_FEAT
Assembly Information CAR
Processing Element Features CAR
Source Operations CAR
SRC_OP
DEST_OP
Destination Operations CAR
PE_LL_CTL
Processing Element Logical Layer Control CSR
Local Configuration Space Base Address 0 CSR
Local Configuration Space Base Address 1 CSR
Base Device ID CSR
LCL_CFG_HBAR
LCL_CFG_BAR
BASE_ID
HOST_BASE_ID_LOCK
COMP_TAG
Host Base Device ID Lock CSR
Component Tag CSR
SP_MB_HEAD
SP_LT_CTL
1x/4x LP_Serial Port Maintenance Block Header
Port Link Time-Out Control CSR
Port Response Time-Out Control CSR
Port General Control CSR
SP_RT_CTL
SP_GEN_CTL
SP0_LM_REQ
SP0_LM_RESP
SP0_ACKID_STAT
SP0_ERR_STAT
SP0_CTL
Port 0 Link Maintenance Request CSR
Port 0 Link Maintenance Response CSR
Port 0 Local AckID Status CSR
Port 0 Error and Status CSR
Port 0 Control CSR
SP1_LM_REQ
SP1_LM_RESP
SP1_ACKID_STAT
SP1_ERR_STAT
Port 1 Link Maintenance Request CSR
Port 1 Link Maintenance Response CSR
Port 1 Local AckID Status CSR
Port 1 Error and Status CSR
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SRIO Registers
Table 40. Serial RapidIO (SRIO) Registers (continued)
Offset
117Ch
1180h
1184h
1188h
1198h
119Ch
11A0h
11A4h
11A8h
11B8h
11BCh
2000h
2008h
200Ch
2010h
2014h
2018h
201Ch
2028h
2040h
2044h
2048h
204Ch
2050h
2054h
2058h
2068h
206Ch
2080h
2084h
2088h
208Ch
2090h
2094h
2098h
20A8h
20ACh
20C0h
20C4h
20C8h
Acronym
Register Description
Section
SP1_CTL
Port 1 Control CSR
Section 5.73
Section 5.69
Section 5.70
Section 5.71
Section 5.72
Section 5.73
Section 5.69
Section 5.70
Section 5.71
Section 5.72
Section 5.73
Section 5.74
Section 5.75
Section 5.76
Section 5.77
Section 5.78
Section 5.79
Section 5.80
Section 5.81
Section 5.82
Section 5.83
Section 5.84
Section 5.85
Section 5.86
Section 5.87
Section 5.88
Section 5.89
Section 5.90
Section 5.82
Section 5.83
Section 5.84
Section 5.85
Section 5.86
Section 5.87
Section 5.88
Section 5.89
Section 5.90
Section 5.82
Section 5.83
Section 5.84
Section 5.85
Section 5.86
Section 5.87
Section 5.88
Section 5.89
Section 5.90
SP2_LM_REQ
SP2_LM_RESP
Port 2 Link Maintenance Request CSR
Port 2 Link Maintenance Response CSR
SP2_ACKID_STAT
SP2_ERR_STAT
SP2_CTL
Port 2 Local AckID Status CSR
Port 2 Error and Status CSR
Port 2 Control CSR
SP3_LM_REQ
Port 3 Link Maintenance Request CSR
Port 3 Link Maintenance Response CSR
Port 3 Local AckID Status CSR
SP3_LM_RESP
SP3_ACKID_STAT
SP3_ERR_STAT
SP3_CTL
Port 3 Error and Status CSR
Port 3 Control CSR
ERR_RPT_BH
Error Reporting Block Header
ERR_DET
Logical/Transport Layer Error Detect CSR
Logical/Transport Layer Error Enable CSR
Logical/Transport Layer High Address Capture CSR
Logical/Transport Layer Address Capture CSR
Logical/Transport Layer Device ID Capture CSR
Logical/Transport Layer Control Capture CSR
Port-Write Target Device ID CSR
ERR_EN
H_ADDR_CAPT
ADDR_CAPT
ID_CAPT
CTRL_CAPT
PW_TGT_ID
SP0_ERR_DET
Port 0 Error Detect CSR
SP0_RATE_EN
Port 0 Error Enable CSR
SP0_ERR_ATTR_CAPT_DBG0
SP0_ERR_CAPT_DBG1
SP0_ERR_CAPT_DBG2
SP0_ERR_CAPT_DBG3
SP0_ERR_CAPT_DBG4
SP0_ERR_RATE
SP0_ERR_THRESH
SP1_ERR_DET
Port 0 Attributes Error Capture CSR 0
Port 0 Packet/Control Symbol Error Capture CSR 1
Port 0 Packet/Control Symbol Error Capture CSR 2
Port 0 Packet/Control Symbol Error Capture CSR 3
Port 0 Packet/Control Symbol Error Capture CSR 4
Port 0 Error Rate CSR 0
Port 0 Error Rate Threshold CSR
Port 1 Error Detect CSR
SP1_RATE_EN
Port 1 Error Enable CSR
SP1_ERR_ATTR_CAPT_DBG0
SP1_ERR_CAPT_DBG1
SP1_ERR_CAPT_DBG2
SP1_ERR_CAPT_DBG3
SP1_ERR_CAPT_DBG4
SP1_ERR_RATE
SP1_ERR_THRESH
SP2_ERR_DET
Port 1 Attributes Error Capture CSR 0
Port 1 Packet/Control Symbol Error Capture CSR 1
Port 1 Packet/Control Symbol Error Capture CSR 2
Port 1 Packet/Control Symbol Error Capture CSR 3
Port 1 Packet/Control Symbol Error Capture CSR 4
Port 1 Error Rate CSR
Port 1 Error Rate Threshold CSR
Port 2 Error Detect CSR
SP2_RATE_EN
Port 2 Error Enable CSR
SP2_ERR_ATTR_CAPT_DBG0
Port 2 Attributes Error Capture CSR 0
Port 2 Packet/Control Symbol Error Capture CSR 1
Port 2 Packet/Control Symbol Error Capture CSR 2
Port 2 Packet/Control Symbol Error Capture CSR 3
Port 2 Packet/Control Symbol Error Capture CSR 4
Port 2 Error Rate CSR
20CCh SP2_ERR_CAPT_DBG1
20D0h
20D4h
20D8h
20E8h
20ECh
SP2_ERR_CAPT_DBG2
SP2_ERR_CAPT_DBG3
SP2_ERR_CAPT_DBG4
SP2_ERR_RATE
SP2_ERR_THRESH
Port 2 Error Rate Threshold CSR
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SRIO Registers
Table 40. Serial RapidIO (SRIO) Registers (continued)
Offset
2100h
2104h
2108h
210Ch
2110h
2114h
2118h
2128h
212Ch
Acronym
Register Description
Port 3 Error Detect CSR
Port 3 Error Enable CSR
Section
SP3_ERR_DET
SP3_RATE_EN
Section 5.82
Section 5.83
Section 5.84
Section 5.85
Section 5.86
Section 5.87
Section 5.88
Section 5.89
Section 5.90
Section 5.91
Section 5.92
Section 5.93
Section 5.94
Section 5.94
Section 5.94
Section 5.94
Section 5.95
Section 5.96
Section 5.97
Section 5.98
Section 5.99
Section 5.95
Section 5.96
Section 5.97
Section 5.98
Section 5.99
Section 5.95
Section 5.96
Section 5.97
Section 5.98
Section 5.99
Section 5.95
Section 5.96
Section 5.97
Section 5.98
Section 5.99
SP3_ERR_ATTR_CAPT_DBG0
SP3_ERR_CAPT_DBG1
SP3_ERR_CAPT_DBG2
SP3_ERR_CAPT_DBG3
SP3_ERR_CAPT_DBG4
SP3_ERR_RATE
Port 3 Attributes Error Capture CSR 0
Port 3 Packet/Control Symbol Error Capture CSR 1
Port 3 Packet/Control Symbol Error Capture CSR 2
Port 3 Packet/Control Symbol Error Capture CSR 3
Port 3 Packet/Control Symbol Error Capture CSR 4
Port 3 Error Rate CSR
SP3_ERR_THRESH
Port 3 Error Rate Threshold CSR
12000h SP_IP_DISCOVERY_TIMER
12004h SP_IP_MODE
Port IP Discovery Timer in 4x mode
Port IP Mode CSR
12008h IP_PRESCAL
Port IP Prescaler Register
12010h SP_IP_PW_IN_CAPT0
12014h SP_IP_PW_IN_CAPT1
12018h SP_IP_PW_IN_CAPT2
1201Ch SP_IP_PW_IN_CAPT3
14000h SP0_RST_OPT
Port-Write-In Capture CSR Register 0
Port-Write-In Capture CSR Register 1
Port-Write-In Capture CSR Register 2
Port-Write-In Capture CSR Register 3
Port 0 Reset Option CSR
14004h SP0_CTL_INDEP
14008h SP0_SILENCE_TIMER
1400Ch SP0_MULT_EVNT_CS
14014h SP0_CS_TX
Port 0 Control Independent Register
Port 0 Silence Timer Register
Port 0 Multicast-Event Control Symbol Request Register
Port 0 Control Symbol Transmit Register
Port 1 Reset Option CSR
14100h SP1_RST_OPT
14104h SP1_CTL_INDEP
14108h SP1_SILENCE_TIMER
1410Ch SP1_MULT_EVNT_CS
14114h SP1_CS_TX
Port 1 Control Independent Register
Port 1 Silence Timer Register
Port 1 Multicast-Event Control Symbol Request Register
Port 1 Control Symbol Transmit Register
Port 2 Reset Option CSR
14200h SP2_RST_OPT
14204h SP2_CTL_INDEP
14208h SP2_SILENCE_TIMER
1420Ch SP2_MULT_EVNT_CS
14214h SP2_CS_TX
Port 2 Control Independent Register
Port 2 Silence Timer Register
Port 2 Multicast-Event Control Symbol Request Register
Port 2 Control Symbol Transmit Register
Port 3 Reset Option CSR
14300h SP3_RST_OPT
14304h SP3_CTL_INDEP
14308h SP3_SILENCE_TIMER
1430Ch SP3_MULT_EVNT_CS
14314h SP3_CS_TX
Port 3 Control Independent Register
Port 3 Silence Timer Register
Port 3 Multicast-Event Control Symbol Request Register
Port 3 Control Symbol Transmit Register
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5.2 Peripheral Identification Register (PID)
The peripheral identification register (PID) is a read-only register that contains the ID and ID revision
number for that peripheral. The PID stores version information used to identify the peripheral. Writes have
no effect to this register. The values are hard coded and will not change from their reset state.
Figure 63. Peripheral ID Register (PID) - Address Offset 0000h
31
15
24 23
16
0
Reserved
R-00h
TYPE
R-01h
8
7
CLASS
R-0Ah
REV
R-01h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 41. Peripheral ID Register (PID) Field Descriptions
Bit
Field
Value Description
31–24 Reserved
23–16 TYPE
Reserved
Peripheral type: Identifies the type of the peripheral RIO
Peripheral class: Identifies the class Switch Fabric
15–8 CLASS
7–0
REV
Peripheral revision: Identifies the revision of the peripheral. This value should begin at 01h and be
incremented each time the design is revised .
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SRIO Registers
5.3 Peripheral Control Register (PCR)
The peripheral control register (PCR) contains a bit that enables or disables data flow in the logical layer
of the entire peripheral. In addition, the PCR has emulation control bits that control the peripheral behavior
during emulation halts. PCR is shown in Figure 64 and described in Table 42. For additional programming
Figure 64. Peripheral Control Register (PCR) - Address Offset 0004h
31
15
16
Reserved
R-0
3
2
1
0
Reserved
R-0
PEREN SOFT FREE
R/W-0 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 42. Peripheral Control Register (PCR) Field Descriptions
Bit
Field
Value Description
31–3 Reserved
0
These read-only bits return 0s when read.
2
PEREN
Peripheral flow control enable. Controls the flow of data in the logical layer of the peripheral. As an
initiator, it will prevent TX transaction generation; as a target, it will disable incoming requests. This
should be the last enable bit to toggle when bringing the device out of reset to begin normal
operation.
0
1
Data flow control is disabled.
Data flow control is enabled.
1
0
SOFT
FREE
Soft stop. This bit and the FREE bit determine how the SRIO peripheral behaves during emulation
halts.
0
1
Hard stop. All status registers are frozen in default state. (This mode is not supported on the SRIO
peripheral.)
Soft stop
Free run
0
1
The SOFT bit takes effect.
Free run. Peripheral ignores the emulation suspend signal and functions normally.
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5.4 Peripheral Settings Control Register (PER_SET_CNTL)
Figure 65. Peripheral Settings Control Register (PER_SET_CNTL) (Address Offset 0020h)
31
23
27
26
25
24
SW_MEM_SLEEP_
OVERRIDE
BOOT_
COMPLETE
Reserved
R-0
LOOPBACK
R/W-0
R/W-1
R/W-0
21 20
18 17
16
Reserved
R-0
TX_PRI2_WM
R/W-01h
TX_PRI1_WM
R/W-02h
9
15
14
12 11
8
TX_PRI1_WM
R/W-02h
TX_PRI0_WM
R/W-03h
CBA_TRANS_PRI
1X_MODE
R/W-0
R/W-0
7
4
3
2
1
0
PRESCALER_SELECT
R/W-0
ENPLL4
R/W-0
ENPLL3
R/W-0
ENPLL2
R/W-0
ENPLL1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions
Bit
31–27
26
Field
Value
Description
Reserved
00000b
These read-only bits return 0s when read.
Software memory sleep override
Memories are put in sleep mode while in shutdown
Memories are not put in sleep mode while in shutdown
Loopback mode
SW_MEM_SLEEP_OVERRIDE
0
1
25
24
LOOPBACK
0
1
Normal operation
Loop back mode. Transmit data to receive on the same port. Packet
data is looped back in the digital domain before the SERDES macros.
BOOT_COMPLETE
Controls ability to write any register during initialization. It also includes
read only registers during normal mode of operation that have
application defined reset value.
0
1
Write to read-only registers enabled
Write to read-only registers disabled. Usually the boot_complete is
asserted once after reset to define power on configuration.
23–21
20–18
Reserved
000b
These read-only bits return 0s when read.
TX_PRI2_WM
000b–111b Transmit credit threshold. Sets the required number of logical layer TX
buffers needed to send priority 2 packets across the UDI. This is valid
for all ports in 1x mode only.
Required buffer count for transmit credit threshold 2 value
(TX_PRI2_WM):
•
•
•
•
•
•
•
•
000→8, 7, 6, 5, 4, 3, 2, 1 (effectively lets all of this priority pass)
001→8, 7, 6, 5, 4, 3, 2
010→8, 7, 6, 5, 4, 3
011→8, 7, 6, 5, 4
100→8, 7, 6, 5
101→8, 7, 6
110→8, 7
111→8
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Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued)
Bit
Field
Value
Description
17–15
TX_PRI1_WM
000b–111b Transmit credit threshold. Sets the required number of logical layer TX
buffers needed to send priority 1 packets across the UDI. This is valid
for all ports in 1x mode only.
Required buffer count for transmit credit threshold 1 value
(TX_PRI1_WM):
•
•
•
•
•
•
•
•
000→8, 7, 6, 5, 4, 3, 2, 1 (effectively lets all of this priority pass)
001→8, 7, 6, 5, 4, 3, 2
010→8, 7, 6, 5, 4, 3
011→8, 7, 6, 5, 4
100→8, 7, 6, 5
101→8, 7, 6
110→8, 7
111→8
14–12
TX_PRI0_WM
000b–111b Transmit credit threshold. Sets the required number of logical layer TX
buffers needed to send priority 0 packets across the UDI. This is valid
for all ports in 1x mode only.
Required buffer count for transmit credit threshold 0 value
(TX_PRI0_WM):
•
•
•
•
•
•
•
•
000→8, 7, 6, 5, 4, 3, 2, 1 (effectively lets all of this priority pass)
001→8, 7, 6, 5, 4, 3, 2
010→8, 7, 6, 5, 4, 3
011→8, 7, 6, 5, 4
100→8, 7, 6, 5
101→8, 7, 6
110→8, 7
111→8
11–9
8
CBA_TRANS_PRI
1X_MODE
000b–111b DSP system transaction priority. 000b – Highest Priority … 111b –
Lowest Priority.
This register bit determines the UDI buffering setup (priority versus port).
For additional programming information, see Section 2.3.13.2.
0
1
UDI buffers are priority based
UDI buffers are port based. This mode must be selected when using
more than one 1x port
7–4
PRESCALER_SELECT
Internal frequency prescaler, used to drive the request to response
timers. These 4 bits are the prescaler reload value allowing division of
the DMA clock by a range from 1 up to 16. Setting should reflect the
device DMA frequency in MHz.
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Sets the internal clock frequency Min 44.7 and Max 89.5
Sets the internal clock frequency Min 89.5 and Max 179.0
Sets the internal clock frequency Min 134.2 and Max 268.4
Sets the internal clock frequency Min 180.0 and Max 360.0
Sets the internal clock frequency Min 223.7 and Max 447.4
Sets the internal clock frequency Min 268.4 and Max 536.8
Sets the internal clock frequency Min 313.2 and Max 626.4
Sets the internal clock frequency Min 357.9 and Max 715.8
sets the internal clock frequency Min 402.7 and Max 805.4
Sets the internal clock frequency Min 447.4 and Max 894.8
Sets the internal clock frequency Min 492.1 and Max 984.2
Sets the internal clock frequency Min 536.9 and Max 1073.8
Sets the internal clock frequency Min 581.6 and Max 1163.2
Sets the internal clock frequency Min 626.3 and Max 1252.6
Sets the internal clock frequency Min 671.1 and Max 1342.2
Sets the internal clock frequency Min 715.8 and Max 1431.6
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SRIO Registers
Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued)
Bit
Field
Value
Description
3
ENPLL4
0
enable SERDES PLL.
2
1
0
ENPLL3
ENPLL2
ENPLL1
0
0
0
enable SERDES PLL.
enable SERDES PLL.
enable SERDES PLL.
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5.5 Peripheral Global Enable Register (GBL_EN)
GBL_EN is implemented with a single enable bit for the entire SRIO peripheral. This bit is logically ORed
with the reset input to the module and is fanned out to all logical blocks within the peripheral. GBL_EN is
Figure 66. Peripheral Global Enable Register (GBL_EN) (Address Offset 0030h)
31
1
0
Reserved
R-0
EN
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 44. Peripheral Global Enable Register (GBL_EN) Field Descriptions
Bit
31–1
0
Field
Value
Description
Reserved
EN
00000000h
These read-only bits return 0s when read.
Global enable. This bit controls reset to all clock domains within the peripheral.
The peripheral is to be disabled (held in reset with clocks disabled).
The peripheral is to be enabled.
0
1
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5.6 Peripheral Global Enable Status Register (GBL_EN_STAT)
Figure 67. Peripheral Global Enable Status Register (GBL_EN_STAT) - Address 0034h
31
23
15
24
16
Reserved
R-0
Reserved
R-0
10
9
8
BLK8_EN_
STAT
BLK7_EN_
STAT
Reserved
R-0
R-1
1
R-1
0
7
6
5
4
3
2
BLK6_EN_
STAT
BLK5_EN_
STAT
BLK4_EN_
STAT
BLK3_EN_
STAT
BLK2_EN_
STAT
BLK1_EN_
STAT
BLK0_EN_
STAT
GBL_EN_
STAT
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
LEGEND: R = Read only; -n = Value after reset
Table 45. Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions
Bit
31–10
9
Field
Value
Description
Reserved
BLK8_EN_STAT
0
These read-only bits return 0s when read.
Block 8 enable status. Logical block 8 is SRIO port 3.
Logical block 8 is in reset with its clock off.
0
1
Logical block 8 is enabled with its clock running.
Block 7 enable status. Logical block 7 is SRIO port 2.
Logical block 7 is in reset with its clock off.
8
7
6
5
4
3
2
BLK7_EN_STAT
BLK6_EN_STAT
BLK5_EN_STAT
BLK4_EN_STAT
BLK3_EN_STAT
BLK2_EN_STAT
BLK1_EN_STAT
0
1
Logical block 7 is enabled with its clock running.
Block 6 enable status. Logical block 6 is SRIO port 1.
Logical block 6 is in reset with its clock off.
0
1
Logical block 6 is enabled with its clock running.
Block 5 enable status. Logical block 5 is SRIO port 0.
Logical block 5 is in reset with its clock off.
0
1
Logical block 5 is enabled with its clock running.
Block 4 enable status. Logical block 4 is the message receive unit (RXU).
Logical block 4 is in reset with its clock off.
0
1
Logical block 4 is enabled with its clock running.
Block 3 enable status. Logical block 3 is the message transmit unit (TXU).
Logical block 3 is in reset with its clock off.
0
1
Logical block 3 is enabled with clock running.
Block 2 enable status. Logical block 2 is the memory access unit (MAU).
Logical block 2 is in reset with its clock off.
0
1
Logical block 2 is enabled with its clock running.
Block 1 enable status. Logical block 1 is the Load/Store module, which is
comprised of the four Load/Store units (LSU1, LSU2, LSU3, and LSU4).
0
1
Logical block 1 is in reset with its clock off.
Logical block 1 is enabled with its clock running.
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Table 45. Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions (continued)
Bit
Field
Value
Description
1
BLK0_EN_STAT
Block 0 enable status. Logical block 0 is the set of memory-mapped registers
(MMRs) for the SRIO peripheral.
0
1
Logical block 0 is in reset with its clock off.
Logical block 0 is enabled with its clock running.
Global enable status
0
GBL_EN_STAT
0
1
The peripheral is in reset with all its clocks off.
The peripheral is enabled with all its clocks running.
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5.7 Block n Enable Register (BLKn_EN)
There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers and
the blocks they support are listed in Table 46. The general form for a block n enable register (BLKn_EN) is
Table 46. Block n Enable Registers and the Associated Blocks
Register
Address Offset
Associated Block
BLK0_EN
0038h
Logical block 0: the set of memory-mapped control registers for the SRIO
peripheral
BLK1_EN
BLK2_EN
BLK3_EN
BLK4_EN
BLK5_EN
BLK6_EN
BLK7_EN
BLK8_EN
0040h
0048h
0050h
0058h
0060h
0068h
0070h
0078h
Logical block 1: the Load/Store module (the four LSUs and supporting logic)
Logical block 2: the memory access unit (MAU)
Logical block 3: the message transmit unit (TXU)
Logical block 4: the message receive unit (RXU).
Logical block 5: SRIO port 0
Logical block 6: SRIO port 1.
Logical block 7: SRIO port 2.
Logical block 8: SRIO port 3.
Figure 68. Block n Enable Register (BLKn_EN)
31
1
0
Reserved
R-0
EN
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 47. Block n Enable Register (BLKn_EN) Field Descriptions
Bit
31-1
0
Field
Value Description
Reserved
Reserved
EN
0
Block n enable
0
1
Logical block n is to be reset with its clock off.
Logical block n is to be enabled with its clock running.
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5.8 Block n Enable Status Register (BLKn_EN_STAT)
There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers and
the blocks they support are listed in Table 48. The general form for a block n enable status register
Table 48. Block n Enable Status Registers and the Associated Blocks
Register
Address Offset
Associated Block
BLK0_EN_STAT
003Ch
Logical block 0: the set of memory-mapped control registers for the SRIO
peripheral
BLK1_EN_STAT
BLK2_EN_STAT
BLK3_EN_STAT
BLK4_EN_STAT
BLK5_EN_STAT
BLK6_EN_STAT
BLK7_EN_STAT
BLK8_EN_STAT
0044h
004Ch
0054h
005Ch
0064h
006Ch
0074h
007Ch
Logical block 1: the Load/Store module (the four LSUs and supporting logic)
Logical block 2: the memory access unit (MAU)
Logical block 3: the message transmit unit (TXU)
Logical block 4: the message receive unit (RXU).
Logical block 5: SRIO port 0
Logical block 6: SRIO port 1.
Logical block 7: SRIO port 2.
Logical block 8: SRIO port 3.
Figure 69. Block n Enable Status Register (BLKn_EN)
31
1
0
Reserved
R-0
EN_STAT
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 49. Block n Enable Status Register (BLKn_EN_STAT) Field Descriptions
Bit
31-1
0
Field
Value Description
Reserved
EN_STAT
0
These read-only bits return 0s when read.
Block n enable status
0
1
Logical block n is reset with its clock off.
Logical block n is enabled with its clock running.
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5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1)
Figure 70. RapidIO DEVICEID1 Register (DEVICEID_REG1) (Offset 0080h)
31
15
24 23
16
0
Reserved
R-00h
8BNODEID
R/W-FFh
16BNODEID
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 50. RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions
Bit
Field
Value
0
Description
31–24
23–16
Reserved
8BNODEID
Reserved
00h–FFh
This value is equal to the value of the RapidIO Base Device ID CSR. The CPU must
read the CSR value and set this register, so that outgoing packets contain the correct
SOURCEID value
15–0
16BNODEID
0000h–FFFFh
This value is equal to the value of the RapidIO Base Device ID CSR. The CPU must
read the CSR value and set this register, so that outgoing packets contain the correct
SOURCEID value
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5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2)
additional programming information, see Section 2.3.15.1 and Section 2.3.15.3.
Figure 71. RapidIO DEVICEID2 Register (DEVICEID_REG2) (Offset 0x0084)
31
15
24 23
16
0
Reserved
R-00h
8BNODEID
R/W-FFh
16BNODEID
R-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 51. RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions
Bit
Field
Value
0
Description
31–24
23–16
Reserved
8BNODEID
Reserved
00h–FFh
This is a secondary supported DeviceID checked against an incoming packet's DestID
field. Typically used for Multi-cast support.
15–0
16BNODEID
0000h–FFFFh
This is a secondary supported DeviceID checked against an incoming packet's DestID
field. Typically used for Multi-cast support.
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5.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn)
There are four of these registers (see Table 52). The general form of a packet forwarding register for
Table 52. PF_16B_CNTL Registers
Register
Address Offset
0090h
PF_16B_CNTL0
PF_16B_CNTL1
PF_16B_CNTL2
PF_16B_CNTL3
0098h
00A0h
00A8h
Figure 72. Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn)
31
16 15
0
16BIT_DEVID_UP_BOUND
R/W-FFFFh
16BIT_DEVID_LOW_BOUND
R/W-FFFFh
LEGEND: R/W = Read/Write; -n = Value after reset
Table 53. Packet Forwarding Register n for 16-Bit DeviceIDs (PF_16B_CNTLn) Field Descriptions
Bit
Field
Value
Description
31–16
16BIT_DEVID_UP_BOUND
0000h–FFFFh
Upper 16-bit DeviceID boundary. DestID above this range
cannot use the table entry.
15–0
16BIT_DEVID_LOW_BOUND
0000h–FFFFh
Lower 16-bit DeviceID boundary. DestID lower than this
number cannot use the table entry.
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5.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn)
There are four of these registers (see Table 54). The general form of a packet forwarding register for
16-bit DeviceIDs is shown in Figure 73 and described in Table 55. For additiona programming information
Table 54. PF_8B_CNTL Registers
Register
Address Offset
0094h
PF_8B_CNTL0
PF_8B_CNTL1
PF_8B_CNTL2
PF_8B_CNTL3
009Ch
00A4h
00ACh
Figure 73. Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn)
31
18 17
16
OUT_BOUND_
PORT
Reserved
R-0
R/W-3
15
7
8
8BIT_DEVID_UP_BOUND
R/W-FFh
0
8BIT_DEVID_LOW_BOUND
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 55. Packet Forwarding Register n for 8-Bit DeviceIDs (PF_8B_CNTLn) Field Descriptions
Bit
Field
Value
0
Description
31–18
17–16
Reserved
Reserved
OUT_BOUND_PORT
0–3
Output port number for packets whose DestID falls within the 8-bit or
16-bit range for this table entry.
15–8
7–0
8BIT_DEVID_UP_BOUND
8BIT_DEVID_LOW_BOUND
00h–FFh
00h–FFh
Upper 8-bit DeviceID boundary. DestID above this range cannot use
the table entry.
Lower 8-bit DeviceID boundary. DestID lower than this number cannot
use the table entry.
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5.13 SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)
There are four of these registers, to support four ports (see ). The general form for a SERDES receive
complete explanation of the programming of these registers.
Table 56. SERDES_CFGRXn_CNTL Registers and the Associated Ports
Register
Address Offset
0100h
Associated Port
Port 0
SERDES_CFGRX0_CNTL
SERDES_CFGRX1_CNTL
SERDES_CFGRX2_CNTL
SERDES_CFGRX3_CNTL
0104h
Port 1
0108h
Port 2 (TMS320TCI6482 Only)
Port 3 (TMS320TCI6482 Only)
010Ch
Figure 74. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)
31
15
26 25
24
23
22
19 18
16
Reserved
(write 0s)
Reserved
R-0
—
EQ
CDR
R/W-0
1
R/W-0
8
R-0
R/W-0
14 13
12
11
—
10
7
6
5
4
2
0
TERM
(write 001b)
—
(write 0)
LOS
ALIGN
R/W-0
INVPAIR
R/W-0
RATE
R/W-0
BUSWIDTH
R/W-0
ENRX
R/W-0
R/W-0
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 57. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field
Descriptions
Bit
Field
Value
000000b
00b
Description
31–26
25–24
23
Reserved
Reserved
Reserved
EQ
These read-only bits return 0s when read.
Always write 0s to these reserved bits.
This read-only bit returns 0 when read.
0
22–19
0000b–1111b Equalizer. Enables and configures the adaptive equalizer to compensate for loss
18–16
CDR
Clock/data recovery. Configures the clock/data recovery algorithm.
000b
001b
First order. Phase offset tracking up to ±488 ppm.
Second order. Highest precision frequency offset matching but poorest response
to changes in frequency offset, and longest lock time. Suitable for use in systems
with fixed frequency offset.
010b
011b
Second order. Medium precision frequency offset matching, frequency offset
change response, and lock time.
Second order. Best response to changes in frequency offset and fastest lock time,
but lowest precision frequency offset matching. Suitable for use in systems with
spread spectrum clocking.
100b
101b
110b
111b
First order with fast lock. Phase offset tracking up to ±1953 ppm in the presence of
..10101010.. training pattern, and ±448 ppm otherwise.
Second order with fast lock. As per setting 001, but with improved response to
changes in frequency offset when not close to lock.
Second order with fast lock. As per setting 010, but with improved response to
changes in frequency offset when not close to lock.
Second order with fast lock. As per setting 011, but with improved response to
changes in frequency offset when not close to lock.
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Table 57. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field
Descriptions (continued)
Bit
Field
Value
Description
15–14
LOS
Loss of signal. Enables loss of signal detection with 2 selectable thresholds.
Disabled. Loss of signal detection disabled.
00b
01b
High threshold. Loss of signal detection threshold in the range 85 to 195mVdfpp
.
This setting is suitable for Infiniband.
10b
11b
Low threshold. Loss of signal detection threshold in the range 65 to 175mVdfpp
This setting is suitable for PCI-E and S-ATA.
.
Reserved
13–12
ALIGN
Symbol alignment. Enables internal or external symbol alignment.
00b
01b
10b
Alignment disabled. No symbol alignment will be performed while this setting is
selected, or when switching to this selection from another.
Comma alignment enabled. Symbol alignment will be performed whenever a
misaligned comma symbol is received.
Alignment jog. The symbol alignment will be adjusted by one bit position when this
mode is selected (that is, the ALIGN value changes from 0xb to 1xb).
11b
0
Reserved
11
Reserved
TERM
This read-only bit returns 0 when read.
10–8
001b
Input termination. The only valid value for this field is 001b. This value sets the
common point to 0.8 VDDT and supports AC coupled systems using CML
transmitters. The transmitter has no effect on the receiver common mode, which is
set to optimize the input sensitivity of the receiver. Common mode termination is
via a 50 pF capacitor to VSSA.
7
INVPAIR
RATE
Invert polarity. Inverts polarity of RIORXn and RIORXn.
Normal polarity. RIORXn is considered to be positive data and RIORXn negative.
Inverted polarity. RIORXn is considered to be negative data and RIORXn positive.
Operating rate. Selects full, half, or quarter rate operation.
Full rate. Two data samples taken per PLL output clock cycle.
Half rate. One data sample taken per PLL output clock cycle.
Quarter rate. One data sample taken every two PLL output clock cycles.
Reserved
0
1
6–5
00b
01b
10b
11b
000b
4–2
BUSWIDTH
Bus width. Always write 000b to this field, to indicate a 10-bit-wide parallel bus to
the bus.
1
0
Reserved
ENRX
0
Always write 0 to this reserved bit.
Enable receiver
0
1
Disable this receiver.
Enable this receiver.
Table 58. EQ Bits
CFGRX[22–19]
Low Freq Gain
Maximum
Zero Freq (at e28 (min))
0000b
0001b
001xb
01xxb
–
Adaptive
Adaptive
Reserved
Reserved
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Table 58. EQ Bits (continued)
CFGRX[22–19]
1000b
Low Freq Gain
Zero Freq (at e28 (min))
1084MHz
805MHz
Adaptive
1001b
1010b
573MHz
1011b
402MHz
1100b
304MHz
1101b
216MHz
1110b
156MHz
1111b
135MHz
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5.14 SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL)
There are four of these registers, to support four ports (see Table 59). The general form for a SERDES
transmit channel configuration register is summarized by Figure 75 and Table 60. See Section 2.3.2.3 for
a complete explanation of the programming for these registers.
Table 59. SERDES_CFGTXn_CNTL Registers and the Associated Ports
Register
Address Offset
0110h
Associated Port
Port 0
SERDES_CFGTX0_CNTL
SERDES_CFGTX1_CNTL
SERDES_CFGTX2_CNTL
SERDES_CFGTX3_CNTL
0114h
Port 1
0118h
Port 2 (TMS320TCI6482 Only)
Port 3 (TMS320TCI6482 Only)
011Ch
Figure 75. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL)
31
15
17
16
Reserved
R-0
ENFTP
R/W-0
12 11
9
8
7
6
5
4
2
1
0
—
(write 0)
DE
SWING
R/W-0
CM
INVPAIR
R/W-0
RATE
R/W-0
BUSWIDTH
R/W-0
ENTX
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 60. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field
Descriptions
Bit
31–17 Reserved
16 ENFTP
Field
Value
Description
0
1
These read-only bits return 0s when read.
Enables fixed phase relationship of transmit input clock with respect to transmit
output clock. The only valid value for this field is 1b; all other values are reserved.
15–12 DE
0000b–1111b
De-emphasis. Selects one of 15 output de-emphasis settings from 4.76 to 71.42%.
De-emphasis provides a means to compensate for high frequency attenuation in
the attached media. It causes the output amplitude to be smaller for bits which are
11–9
8
SWING
000b–111b
Output swing. Selects one of 8 output amplitude settings between 125 and
CM
Common mode. Adjusts the common mode to suit the termination at the attached
receiver.
0
1
Normal common mode. Common mode not adjusted.
Raised common mode. Common mode raised by 5% of e54
.
7
INVPAIR
RATE
Invert polarity. Inverts the polarity of RIOTXn and RIOTXn.
0
1
Normal polarity. RIOTXn is considered to be positive data and RIOTXn negative.
Inverted polarity. RIOTXn is considered to be negative data and RIOTXn positive.
Operating rate. Selects full, half, or quarter rate operation.
Full rate. Two data samples taken per PLL output clock cycle.
Half rate. One data sample taken per PLL output clock cycle.
Quarter rate. One data sample taken every two PLL output clock cycles.
Reserved
6–5
00b
01b
10b
11b
000b
4–2
1
BUSWIDTH
Reserved
Bus width. Always write 000b to this field, to indicate a 10-bit-wide parallel bus to
the bus.
0
Always write 0 to this reserved bit.
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Table 60. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field
Descriptions (continued)
Bit
Field
Value
Description
0
ENTX
Enable transmitter
Disable this transmitter.
Enable this transmitter.
0
1
Table 61. DE Bits of SERDES_CFGTXn_CNTL
Amplitude Reduction
DE Bits
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
%
dB
0
0
4.76
–0.42
–0.87
–1.34
–1.83
–2.36
–2.92
–3.52
–4.16
–4.86
–5.61
–6.44
–7.35
–8.38
–9.54
–10.87
9.52
14.28
19.04
23.8
28.56
33.32
38.08
42.85
47.61
52.38
57.14
61.9
66.66
71.42
Table 62. SWING Bits of SERDES_CFGTXn_CNTL
SWING Bits
000b
Amplitude (mVdfpp)
125
250
001b
010b
500
011b
625
100b
750
101b
1000
1125
1250
110b
111b
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5.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)
There are four of these registers, to support four ports (see Table 63). The general form for a SERDES
transmit channel configuration register is summarized by Figure 76 and Table 64. See Section 2.3.2.1 for
a complete explanation of the programming of this register.
Table 63. SERDES_CFGn_CNTL Registers and the Associated Ports
Register
Address Offset
0120h
Associated Port
SERDES_CFG0_CNTL
SERDES_CFG1_CNTL
Port 0, Port 1, Port 2, and Port 3
0124h
Not Used. Program as
0x00000000
SERDES_CFG2_CNTL
SERDES_CFG3_CNTL
0128h
012Ch
Not Used. Program as
0x00000000
Not Used. Program as
0x00000000
Figure 76. SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)
31
15
16
Reserved
R-0
10
9
8
7
6
5
1
0
Reserved
R-0
LB
Reserved
R-0
MPY
ENPLL
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 64. SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) Field Descriptions
Bit
31–10
9–8
Field
Value
Description
Reserved
LB
0
Reserved
Loop bandwidth. Specify loop bandwidth settings. Jitter on the reference clock will
degrade both the transmit eye and receiver jitter tolerance thereby impairing system
performance. Performance of the integrated PLL can be optimized according to the
jitter characteristics of the reference clock via the LB field.
00b
Frequency dependent bandwidth. The PLL bandwidth is set to a twelfth of the
frequency of RIOCLK/RIOCLK. This setting is suitable for most systems that input the
reference clock via a low jitter input cell, and is required for standards compliance
01b
10b
Reserved
Low bandwidth. The PLL bandwidth is set to a twentieth of the frequency of
RIOCLK/RIOCLK, or 3MHz (whichever is larger). In systems where the reference
clock is directly input via a low jitter input cell, but is of lower quality, this setting may
offer better performance. It will reduce the amount of reference clock jitter transferred
through the PLL. However, it also increases the susceptibility to loop noise generated
within the PLL itself. It is difficult to predict whether the improvement in the former will
more than offset the degradation in the latter.
11b
0
High bandwidth. The PLL bandwidth is set to a eighth of the frequency of
RIOCLK/RIOCLK. This is the setting appropriate for systems where the reference
clock is cleaned through an ultra low jitter LC-based PLL. Standards compliance will
be achieved even if the reference clock input to the cleaner PLL is outside the
specification for the standard.
7–6
Reserved
Reserved
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Table 64. SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) Field Descriptions
(continued)
Bit
Field
Value
Description
5–1
MPY
PLL multiply. Select PLL multiply factors between 4 and 60.
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01111b
1xxxxb
4x
5x
6x
Reserved
8x
10x
12x
12.5x
15x
20x
25x
Reserved
Reserved
Reserved
Reserved
Enable PLL
PLL disabled
PLL enabled
0
ENPLL
0
1
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5.16 DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR)
The four doorbell interrupts are mapped to these registers (see Table 65). The general form of a doorbell
Table 65. DOORBELLn_ICSR Registers
Register
Address Offset
0200h
DOORBELL0_ICSR
DOORBELL1_ICSR
DOORBELL2_ICSR
DOORBELL3_ICSR
0210h
0220h
0230h
Figure 77. Doorbell n Interrupt Condition Status Register (DOORBELLn_ICSR)
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
ICS8
ICS7
ICS6
ICS5
ICS4
ICS3
ICS2
ICS1
ICS0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 66. DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR) Field Descriptions
Bit
Field
Value
Description
31–16
15–0
Reserved
0
These read-only bits return 0s when read.
Doorbell n interrupt condition status bit
Bit x of the doorbell information value is 0.
Bit x of the doorbell information value is 1, generating an interrupt request.
ICSx
(x = 15 to 0)
0
1
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5.17 DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR)
The four doorbells interrupts that are mapped are cleared by this register (see Table 67). The general form
of a doorbell interrupt condition clear register is shown in Figure 78 and described in Table 68. For
Table 67. DOORBELLn_ICCR Registers
Register
Address Offset
0208h
DOORBELL0_ICCR
DOORBELL1_ICCR
DOORBELL2_ICCR
DOORBELL3_ICCR
0218h
0228h
0238h
Figure 78. Doorbell n Interrupt Condition Clear Register (DOORBELLn_ICCR)
31
16
Reserved
R-0
15
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: W = Write only; R = Read only; -n = Value after reset
Table 68. DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR) Field Descriptions
Bit
Field
Value
Description
31–16
15–0
Reserved
0
These read-only bits return 0s when read.
Doorbell n interrupt condition clear bit
No effect
ICCx
(x = 15 to 0)
0
1
Clear bit x of the corresponding doorbell interrupt condition status register
(ICSR).
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5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR)
The bits in this register indicate any active interrupt requests from RX buffer descriptor queues. The RX
Figure 79. RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) - Address Offset 0240h
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
ICS8
ICS7
ICS6
ICS5
ICS4
ICS3
ICS2
ICS1
ICS0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 69. RX CPPI Interrupt Condition Status Register (RX_CPPI_ICSR) Field Descriptions
Bit
Field
Value Description
31–16 Reserved
0
These read-only bits return 0 when read.
15–0 ICSx
RX CPPI interrupt status
(x = 15 to 0)
0
1
RX buffer descriptor queue x has not generated an interrupt request.
RX buffer descriptor queue x has generated an interrupt request.
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5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)
This register is used to clear bits in RX_CPPI_ICSR to acknowledge interrupts from the RX buffer
Figure 80. RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) - Address Offset 0248h
31
16
Reserved
R-0
15
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Table 70. RX CPPI Interrupt Condition Clear Register (RX_CPPI_ICCR) Field Descriptions
Bit
Field
Value Description
31–16 Reserved
0
These read-only bits return 0 when read.
15–0 ICCx
RX CPPI interrupt clear
No effect
(x = 15 to 0)
0
1
Clear bit x of RX_CPPI_ICSR.
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5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)
The bits in this register indicate any active interrupt requests from TX buffer descriptor queues.
Figure 81. TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) - Address Offset 0250h
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
ICS8
ICS7
ICS6
ICS5
ICS4
ICS3
ICS2
ICS1
ICS0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 71. TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) Field Descriptions
Bit
Field
Value Description
31–16 Reserved
0
These read-only bits return 0 when read.
15–0 ICSx
TX CPPI interrupt status
(x = 15 to 0)
0
1
TX buffer descriptor queue x has not generated an interrupt request.
TX buffer descriptor queue x has generated an interrupt request.
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5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)
This register is used to clear bits in TX_CPPI_ICSR to acknowledge interrupts from the TX buffer
Figure 82. TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) - Address Offset 0258h
31
16
Reserved
R-0
15
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Table 72. TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) Field Descriptions
Bit
Field
Value Description
31–16 Reserved
0
These read-only bits return 0 when read.
TX CPPI interrupt clear
15–0 ICCx
(x = 15 to 0)
0
1
No effect
Clear bit x of TX_CPPI_ICSR.
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5.22 LSU Interrupt Condition Status Register (LSU_ICSR)
Each of the status bits in this register indicates the occurrence of a particular type of transaction interrupt
condition for a particular LSU. LSU_ICSR is shown in Figure 83 and described in Table 73. For additional
Figure 83. LSU Interrupt Condition Status Register (LSU_ICSR) - Address Offset 0260h
<--------------------------------- Bits for LSU4 --------------------------------->
31 30 29 28 27 26 25 24
ICS31 ICS30 ICS29 ICS28 ICS27 ICS26 ICS25 ICS24 ICS23 ICS22 ICS21 ICS20 ICS19 ICS18 ICS17 ICS16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
<--------------------------------- Bits for LSU2 ---------------------------------> <--------------------------------- Bits for LSU1 --------------------------------->
<--------------------------------- Bits for LSU3 --------------------------------->
23 22 21 20 19 18 17 16
15
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9
R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = Value after reset
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS8
R-0
ICS7
R-0
ICS6
R-0
ICS5
R-0
ICS4
R-0
ICS3
R-0
ICS2
R-0
ICS1
R-0
ICS0
R-0
Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions
Bit
Field
Value Description
31
ICS31
0
1
LSU4 interrupt condition not detected.
LSU4 interrupt condition detected. Packet not sent due to unavailable outbound credit at given
priority.
30
ICS30
0
1
LSU4 interrupt condition not detected.
LSU4 interrupt condition detected. Retry Doorbell response received or Atomic test-and-swap was
not allowed (semaphore in use).
29
28
27
ICS29
ICS28
ICS27
0
1
0
1
0
1
LSU4 interrupt condition not detected.
LSU4 interrupt condition detected. Transaction was not sent due to DMA data transfer error.
LSU4 interrupt condition not detected.
LSU4 interrupt condition detected. Transaction timeout occurred.
LSU4 interrupt condition not detected.
LSU4 interrupt condition detected. Transaction was not sent due to unsupported transaction type or
invalid field encoding.
26
25
ICS26
ICS25
0
1
0
1
LSU4 interrupt condition not detected.
LSU4 interrupt condition detected. Transaction was not sent due to Xoff condition.
LSU4 interrupt condition not detected.
LSU4 interrupt condition detected. Non-posted transaction received ERROR response, or error in
response payload.
24
ICS24
0
1
LSU4 interrupt condition not detected.
LSU4 interrupt condition detected. Transaction complete, No errors (posted/non-posted). Enable for
this interrupt is ultimately controlled by the Interrupt Req bit of LSU4_REG4. This allows
enabling/disabling on a per request basis. For optimum LSU performance, interrupt pacing should
not be used on the LSU interrupts.
23
22
ICS23
ICS22
0
1
LSU3 interrupt condition not detected.
LSU3 interrupt condition detected. Packet not sent due to unavailable outbound credit at given
priority.
0
1
LSU3 interrupt condition not detected.
LSU3 interrupt condition detected. Retry Doorbell response received or Atomic test-and-swap was
not allowed (semaphore in use).
21
20
ICS21
ICS20
0
1
0
1
LSU3 interrupt condition not detected.
LSU3 interrupt condition detected. Transaction was not sent due to DMA data transfer error.
LSU3 interrupt condition not detected.
LSU3 interrupt condition detected. Transaction timeout occurred.
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Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued)
Bit
Field
Value Description
19
ICS19
0
1
LSU3 interrupt condition not detected.
LSU3 interrupt condition detected. Transaction was not sent due to unsupported transaction type or
invalid field encoding.
18
17
ICS18
ICS17
0
1
0
1
LSU3 interrupt condition not detected.
LSU3 interrupt condition detected. Transaction was not sent due to Xoff condition.
LSU3 interrupt condition not detected.
LSU3 interrupt condition detected. Non-posted transaction received ERROR response, or error in
response payload.
16
ICS16
0
1
LSU3 interrupt condition not detected.
LSU3 interrupt condition detected. Transaction complete, No errors (posted/non-posted). Enable for
this interrupt is ultimately controlled by the Interrupt Req bit of LSU3_REG4. This allows
enabling/disabling on a per request basis. For optimum LSU performance, interrupt pacing should
not be used on the LSU interrupts.
15
14
ICS15
ICS14
0
1
LSU2 interrupt condition not detected.
LSU2 interrupt condition detected. Packet not sent due to unavailable outbound credit at given
priority.
0
1
LSU2 interrupt condition not detected.
LSU2 interrupt condition detected. Retry Doorbell response received or Atomic test-and-swap was
not allowed (semaphore in use).
13
12
11
ICS13
ICS12
ICS11
0
1
0
1
0
1
LSU2 interrupt condition not detected.
LSU2 interrupt condition detected. Transaction was not sent due to DMA data transfer error.
LSU2 interrupt condition not detected.
LSU2 interrupt condition detected. Transaction timeout occurred.
LSU2 interrupt condition not detected.
LSU2 interrupt condition detected. Transaction was not sent due to unsupported transaction type or
invalid field encoding.
10
9
ICS10
ICS9
0
1
0
1
LSU2 interrupt condition not detected.
LSU2 interrupt condition detected. Transaction was not sent due to Xoff condition.
LSU2 interrupt condition not detected.
LSU2 interrupt condition detected. Non-posted transaction received ERROR response, or error in
response payload.
8
ICS8
0
1
LSU2 interrupt condition not detected.
LSU2 interrupt condition detected. Transaction complete, No errors (posted/non-posted). Enable for
this interrupt is ultimately controlled by the Interrupt Req bit of LSU2_REG4. This allows
enabling/disabling on a per request basis. For optimum LSU performance, interrupt pacing should
not be used on the LSU interrupts.
7
6
ICS7
ICS6
0
1
LSU1 interrupt condition not detected.
LSU1 interrupt condition detected. Packet not sent due to unavailable outbound credit at given
priority.
0
1
LSU1 interrupt condition not detected.
LSU1 interrupt condition detected. Retry Doorbell response received or Atomic test-and-swap was
not allowed (semaphore in use).
5
4
3
ICS5
ICS4
ICS3
0
1
0
1
0
1
LSU1 interrupt condition not detected.
LSU1 interrupt condition detected. Transaction was not sent due to DMA data transfer error.
LSU1 interrupt condition not detected.
LSU1 interrupt condition detected. Transaction timeout occurred.
LSU1 interrupt condition not detected.
LSU1 interrupt condition detected. Transaction was not sent due to unsupported transaction type or
invalid field encoding.
2
ICS2
0
1
LSU1 interrupt condition not detected.
LSU1 interrupt condition detected. Transaction was not sent due to Xoff condition.
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Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued)
Bit
Field
Value Description
1
ICS1
0
1
LSU1 interrupt condition not detected.
LSU1 interrupt condition detected. Non-posted transaction received ERROR response, or error in
response payload.
0
ICS0
0
1
LSU1 interrupt condition not detected.
LSU1 interrupt condition detected. Transaction complete, No errors (posted/non-posted). Enable for
this interrupt is ultimately controlled by the Interrupt Req bit of LSU1_REG4. This allows
enabling/disabling on a per request basis. For optimum LSU performance, interrupt pacing should
not be used on the LSU interrupts.
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5.23 LSU Interrupt Condition Clear Register (LSU_ICCR)
Setting a bit in this register clears the corresponding bit in LSU_ICSR, to acknowledge the interrupt.
LSU_ICCR is shown in Figure 84 and described in Table 74. For additional programming information, see
Figure 84. LSU Interrupt Condition Clear Register (LSU_ICCR) - Address Offset 0268h
<--------------------------------- Bits for LSU4 --------------------------------->
31 30 29 28 27 26 25 24
ICC31 ICC30 ICC29 ICC28 ICC27 ICC26 ICC25 ICC24 ICC23 ICC22 ICC21 ICC20 ICC19 ICC18 ICC17 ICC16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
<--------------------------------- Bits for LSU2 ---------------------------------> <--------------------------------- Bits for LSU1 --------------------------------->
<--------------------------------- Bits for LSU3 --------------------------------->
23 22 21 20 19 18 17 16
15
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9
W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: W = Write only; -n = Value after reset
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICC8
W-0
ICC7
W-0
ICC6
W-0
ICC5
W-0
ICC4
W-0
ICC3
W-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
Table 74. LSU Interrupt Condition Clear Register (LSU_ICCR) Field Descriptions
Bit
31–0 ICCx
(x = 31 to 0)
Field
Value Description
0
1
No effect
Clear bit x of the LSU interrupt condition status register (LSU_ICSR).
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5.24 Error, Reset, and Special Event Interrupt Condition Status Register
(ERR_RST_EVNT_ICSR)
Each of the nonreserved bits in this register indicate the status of a particular interrupt condition in one or
Figure 85. Error, Reset, and Special Event Interrupt Condition Status Register
(ERR_RST_EVNT_ICSR) - Address Offset 0270h
31
15
17
16
ICS16
R-0
Reserved
R-0
12
11
ICS11 ICS10 ICS9
R-0 R-0 R-0
10
9
8
7
3
2
1
0
Reserved
R-0
ICS8
R-0
Reserved
R-0
ICS2
R-0
ICS1
R-0
ICS0
R-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Table 75. Error, Reset, and Special Event Interrupt Condition Status Register
(ERR_RST_EVNT_ICSR) Field Descriptions
Bit
31–17
16
Field
Value
Description
Reserved
ICS16
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
These reserved bits return 0s when read.
Device reset interrupt not received from any port
Device reset interrupt received from any port
These reserved bits return 0s when read.
Error not detected on port 3
15–12
11
Reserved
ICS11
Error detected on port 3
10
9
ICS10
ICS9
ICS8
Error not detected on port 2
Error detected on port 2
Error not detected on port 1
Error detected on port 1
8
Error not detected on port 0
Error detected on port 0
7–3
2
Reserved
ICS2
These reserved bits return 0s when read.
Logical layer error management event capture not detected
Logical layer error management event capture detected
Port-write-in request not received on any port
Port-write-in request received on any port
Multi-cast event control symbol interrupt not received on any port
Multi-cast event control symbol interrupt received on any port
1
0
ICS1
ICS0
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5.25 Error, Reset, and Special Event Interrupt Condition Clear Register
(ERR_RST_EVNT_ICCR)
Each bit in this register is used to clear the corresponding status bit in ERR_RST_EVNT_ICSR. The field
Figure 86. Error, Reset, and Special Event Interrupt Condition Clear Register
(ERR_RST_EVNT_ICCR) - Address Offset 0278h
31
15
17
16
Reserved
R-0
ICC16
W-0
12
11
ICC11 ICC10 ICC9
W-0 W-0 W-0
10
9
8
7
3
2
1
0
Reserved
R-0
ICC8
W-0
Reserved
R-0
ICC2
W-0
ICC1
W-0
ICC0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Table 76. Error, Reset, and Special Event Interrupt Condition Clear Register
(ERR_RST_EVNT_ICCR) Field Descriptions
Bit
31–17
16
Field
Value
Description
Reserved
ICC16
0
0
1
0
0
1
0
0
1
These read-only bits return 0s when read.
No effect
Clear bit 16 of ERR_RST_EVNT_ICSR.
These read-only bits return 0s when read.
No effect
15–12
11–8
Reserved
ICCx
(x = 11 to 8)
Clear bit x of ERR_RST_EVNT_ICSR.
These read-only bits return 0s when read.
No effect
7–3
2–0
Reserved
ICCy
(y = 2 to 0)
Clear bit y of ERR_RST_EVNT_ICSR.
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5.26 DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and
DOORBELLn_ICRR2)
When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requests
from the associated doorbell ICSR to user-selected interrupt destinations. Each of the four doorbells can
be mapped to these registers (see Table 77). The general field description in Table 78 applies to an ICRx
field of either register. For additional programming information, see Section 4.4.1 and Section 2.3.6.
Table 77. DOORBELLn_ICRR Registers
Register
Address Offset
0280h
DOORBELL0_ICRR
DOORBELL0_ICRR2
DOORBELL1_ICRR
DOORBELL1_ICRR2
DOORBELL2_ICRR
DOORBELL2_ICRR2
DOORBELL3_ICRR
DOORBELL3_ICRR3
0284h
0290h
0294h
02A0h
02A4h
02B0h
02B4h
Figure 87. Doorbell n Interrupt Condition Routing Registers
Doorbell n Interrupt Condition Routing Register (DOORBELLn_ICRR)
31
28 27
24 23
20 19
16
0
ICR7
ICR6
ICR5
ICR4
R/W-0h
R/W-0h
R/W-0h
R/W-0h
15
12 11
8
7
4
3
ICR3
ICR2
ICR1
ICR0
R/W-0000
R/W-0000
R/W-0000
R/W-0000
Doorbell n Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2)
31
28 27
24 23
20 19
16
0
ICR15
ICR14
ICR13
ICR12
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR11
ICR10
ICR9
ICR8
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LEGEND: R/W = Read/Write; -n = Value after reset
Table 78. DOORBELLn Interrupt Condition Routing Register Field Descriptions
Field
Value
Description
ICRx
Interrupt condition routing. Routes the interrupt request from doorbell n, bit x to one of eight
(x = 0 to 15)
interrupt destinations (INTDST0–INTDST7). For example, if ICS6 = 1 in DOORBELL2_ICSR and
ICR6 = 0010b in DOORBELL2_ICRR, the interrupt request from doorbell 2, bit 6 is sent to interrupt
destination 2.
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1xxxb
INTDST0
INTDST1
INTDST2
INTDST3
INTDST4
INTDST5
INTDST6
INTDST7
Reserved
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5.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2)
interrupt destinations. For example, if ICS6 = 1 in RX_CPPI_ICSR and ICR6 = 0010b in RX_CPPI_ICRR,
the interrupt request from RX buffer descriptor queue 6 is sent to interrupt destination 2. For additional
Figure 88. RX CPPI Interrupt Condition Routing Registers
RX CPPI Interrupt Condition Routing Register (RX_CPPI_ICRR) (Address Offset 02C0h)
31
28 27
24 23
20 19
16
0
ICR7
ICR6
ICR5
ICR4
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR3
ICR2
ICR1
ICR0
R/W-0000
R/W-0000
R/W-0000
R/W-0000
RX CPPI Interrupt Condition Routing Register 2 (RX_CPPI_ICRR2) (Address Offset 02C4h)
31
28 27
24 23
20 19
16
0
ICR15
ICR14
ICR13
ICR12
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR11
ICR10
ICR9
ICR8
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LEGEND: R/W = Read/Write; -n = Value after reset
Table 79. RX CPPI Interrupt Condition Routing Register Field Descriptions
Field
Value
Description
ICRx
Interrupt condition routing. Routes the interrupt request from RX buffer descriptor queue x to one of
(x = 0 to 15)
eight interrupt destinations (INTDST0–INTDST7).
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1xxxb
INTDST0
INTDST1
INTDST2
INTDST3
INTDST4
INTDST5
INTDST6
INTDST7
Reserved
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5.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2)
interrupt destinations. For example, if ICS6 = 1 in TX_CPPI_ICSR and ICR6 = 0011b in TX_CPPI_ICRR,
the interrupt request from TX buffer descriptor queue 6 is sent to interrupt destination 3. For additional
Figure 89. TX CPPI Interrupt Condition Routing Registers
TX CPPI Interrupt Condition Routing Register (TX_CPPI_ICRR) (Address Offset 02D0h)
31
28 27
24 23
20 19
16
0
ICR7
ICR6
ICR5
ICR4
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR3
ICR2
ICR1
ICR0
R/W-0000
R/W-0000
R/W-0000
R/W-0000
TX CPPI Interrupt Condition Routing Register 2 (TX_CPPI_ICRR2) (Address Offset 02D4h)
31
28 27
24 23
20 19
16
0
ICR15
ICR14
ICR13
ICR12
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR11
ICR10
ICR9
ICR8
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LEGEND: R/W = Read/Write; -n = Value after reset
Table 80. TX CPPI Interrupt Condition Routing Register Field Descriptions
Field
Value
Description
ICRx
Interrupt condition routing. Routes the interrupt request from TX buffer descriptor queue x to one of
(x = 0 to 15)
eight interrupt destinations (INTDST0–INTDST7).
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1xxxb
INTDST0
INTDST1
INTDST2
INTDST3
INTDST4
INTDST5
INTDST6
INTDST7
Reserved
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5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3)
Figure 90 shows the ICRRs for the LSU interrupt requests, and Table 81 shows the general description for
an ICRx field in any of the four registers. These registers route LSU interrupt requests from LSU_ICSR to
interrupt destinations. For example, if ICS4 = 1 in LSU_ICSR and ICR4 = 0000b in LSU_ICRR0, LSU1
has generated a transaction-timeout interrupt request, and that request is routed to interrupt destination 0.
Figure 90. LSU Interrupt Condition Routing Registers
LSU Interrupt Condition Routing Register 0 (LSU_ICRR0) (Address Offset 02E0h)
31
28 27
12 11
24 23
20 19
16
0
ICR7
ICR6
ICR5
ICR4
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
8
7
4
3
ICR3
ICR2
ICR1
ICR0
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LSU Interrupt Condition Routing Register 1 (LSU_ICRR1) (Address Offset 02E4h)
31
28 27
24 23
20 19
16
0
ICR15
ICR14
ICR13
ICR12
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR11
ICR10
ICR9
ICR8
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LSU Interrupt Condition Routing Register 2 (LSU_ICRR2) (Address Offset 02E8h)
31
28 27
24 23
20 19
16
0
ICR23
ICR22
ICR21
ICR20
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR19
ICR18
ICR17
ICR16
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LSU Interrupt Condition Routing Register 3 (LSU_ICRR3) (Address Offset 02ECh)
31
28 27
24 23
20 19
16
0
ICR31
ICR30
ICR29
ICR28
R/W-0000
R/W-0000
R/W-0000
R/W-0000
15
12 11
8
7
4
3
ICR27
ICR26
ICR25
ICR24
R/W-0000
R/W-0000
R/W-0000
R/W-0000
LEGEND: R/W = Read/Write; -n = Value after reset
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Table 81. LSU Interrupt Condition Routing Register Field Descriptions
Field
Value
Description
ICRx
(x = 0 to 31)
Interrupt condition routing. Routes the associated LSU interrupt request to one of eight interrupt
destinations (INTDST0–INTDST7). Bits ICR0–ICR7 are for LSU1; bits ICR8–ICR15, for LSU2; bits
ICR16–ICR23, for LSU3; bits ICR24–ICR31, for LSU4.
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1xxxb
INTDST0
INTDST1
INTDST2
INTDST3
INTDST4
INTDST5
INTDST6
INTDST7
Reserved
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5.30 Error, Reset, and Special Event Interrupt Condition Routing Registers
(ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3)
destinations. For example, if ICS8 = 1 in ERR_RST_EVNT_ICSR and ICR8 = 0001b in
ERR_RST_EVNT_ICRR2, port 0 has generated an error interrupt request, and that request is routed to
interrupt destination 1. Table 82 gives a general description for an ICRx field in any of the three registers.
Figure 91. Error, Reset, and Special Event Interrupt Condition Routing Registers
Error, Reset, and Special Event ICRR (ERR_RST_EVNT_ICRR) (Address Offset 02F0h)
31
Reserved
R-0
12 11
8
7
4
4
4
3
3
3
0
Reserved
R-0
ICR2
ICR1
ICR0
R/W-0000
R/W-0000
R/W-0000
Error, Reset, & Special Event ICRR 2 (ERR_RST_EVNT_ICRR2) (Address Offset 02F4h)
31
16
0
Reserved
R-0
15
12 11
8
7
ICR11
ICR10
ICR9
ICR8
R/W-0000
R/W-0000
R/W-0000
R/W-0000
Error, Reset, and Special Event ICRR 3 (ERR_RST_EVNT_ICRR3) (Address Offset 02F8h)
31
Reserved
R-0
0
Reserved
ICR16
R-0
R/W-0000
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 82. Error, Reset, and Special Event Interrupt Condition Routing Register Field Descriptions
Field
Value
Description
ICRx
Interrupt condition routing. Routes the associated port interrupt request to one of eight
interrupt destinations (INTDST0–INTDST7).
(x = 0 to 2, 8 to 11, and 16)
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1xxxb
INTDST0
INTDST1
INTDST2
INTDST3
INTDST4
INTDST5
INTDST6
INTDST7
Reserved
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5.31 Interrupt Status Decode Register (INTDSTn_DECODE)
There are eight of these registers, one for each interrupt destination (see Table 83). This type of register is
register only if the ICRRs routes the interrupt source to the corresponding physical interrupt. Each status
decode bit is a logical OR of multiple interrupt sources that are mapped to the same bit. For additional
Table 83. INTDSTn_DECODE Registers and the Associated Interrupt
Destinations
Register
Address Offset
Associated Interrupt
Destination
INTDST0_DECODE
INTDST1_DECODE
INTDST2_DECODE
INTDST3_DECODE
INTDST4_DECODE
INTDST5_DECODE
INTDST6_DECODE
INTDST7_DECODE
0300h
0304h
0308h
030Ch
0310h
0314h
0318h
031Ch
INTDST0
INTDST1
INTDST2
INTDST3
INTDST4
INTDST5
INTDST6
INTDST7
Figure 92. Interrupt Status Decode Register (INTDSTn_DECODE)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ISD31 ISD30 ISD29 ISD28 ISD27 ISD26 ISD25 ISD24 ISD23 ISD22 ISD21 ISD20 ISD19 ISD18 ISD17 ISD16
R-0
15
R-0
14
R-0
13
R-0
12
R-0
11
R-0
10
R-0
9
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
8
7
6
5
4
3
2
1
0
ISD15 ISD14 ISD13 ISD12 ISD11 ISD10 ISD9
R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read, W = Write, -n = Value after reset
ISD8
R-0
ISD7
R-0
ISD6
R-0
ISD5
R-0
ISD4
R-0
ISD3
R-0
ISD2
R-0
ISD1
R-0
ISD0
R-0
Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions
Bit
Field
Value Description
31
ISD31
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
An LSU (check LSU_ICSR)
TX buffer descriptor queue 0 (bit 0 of TX_CPPI_ICSR)
RX buffer descriptor queue 0 (bit 0 of RX_CPPI_ICSR)
30
ISD30
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
A port (check ERR_RST_EVNT_ICSR)
TX buffer descriptor queue 1 (bit 1 of TX_CPPI_ICSR)
RX buffer descriptor queue 1 (bit 1 of RX_CPPI_ICSR)
29
28
ISD29
ISD28
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 2 (bit 2 of TX_CPPI_ICSR)
RX buffer descriptor queue 2 (bit 2 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 3 (bit 3 of TX_CPPI_ICSR)
RX buffer descriptor queue 3 (bit 3 of RX_CPPI_ICSR)
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Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions (continued)
Bit
Field
Value Description
27
ISD27
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 4 (bit 4 of TX_CPPI_ICSR)
RX buffer descriptor queue 4 (bit 4 of RX_CPPI_ICSR)
26
25
24
23
22
21
20
19
18
17
16
ISD26
ISD25
ISD24
ISD23
ISD22
ISD21
ISD20
ISD19
ISD18
ISD17
ISD16
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 5 (bit 5 of TX_CPPI_ICSR)
RX buffer descriptor queue 5 (bit 5 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 6 (bit 6 of TX_CPPI_ICSR)
RX buffer descriptor queue 6 (bit 6 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 7 (bit 7 of TX_CPPI_ICSR)
RX buffer descriptor queue 7 (bit 7 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 8 (bit 8 of TX_CPPI_ICSR)
RX buffer descriptor queue 8 (bit 8 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 9 (bit 9 of TX_CPPI_ICSR)
RX buffer descriptor queue 9 (bit 9 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 10 (bit 10 of TX_CPPI_ICSR)
RX buffer descriptor queue 10 (bit 10 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 11 (bit 11 of TX_CPPI_ICSR)
RX buffer descriptor queue 11 (bit 11 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 12 (bit 12 of TX_CPPI_ICSR)
RX buffer descriptor queue 12 (bit 12 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 13 (bit 13 of TX_CPPI_ICSR)
RX buffer descriptor queue 13 (bit 13 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 14 (bit 14 of TX_CPPI_ICSR)
RX buffer descriptor queue 14 (bit 14 of RX_CPPI_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
TX buffer descriptor queue 15 (bit 15 of TX_CPPI_ICSR)
RX buffer descriptor queue 15 (bit 15 of RX_CPPI_ICSR)
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Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions (continued)
Bit
Field
Value Description
15
ISD15
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 15 (bit 15 of DOORBELL0_ICSR)
Doorbell 1, bit 15 (bit 15 of DOORBELL1_ICSR)
Doorbell 2, bit 15 (bit 15 of DOORBELL2_ICSR)
Doorbell 3, bit 15 (bit 15 of DOORBELL3_ICSR)
14
13
12
11
10
9
ISD14
ISD13
ISD12
ISD11
ISD10
ISD9
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 14 (bit 14 of DOORBELL0_ICSR)
Doorbell 1, bit 14 (bit 14 of DOORBELL1_ICSR)
Doorbell 2, bit 14 (bit 14 of DOORBELL2_ICSR)
Doorbell 3, bit 14 (bit 14 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 13 (bit 13 of DOORBELL0_ICSR)
Doorbell 1, bit 13 (bit 13 of DOORBELL1_ICSR)
Doorbell 2, bit 13 (bit 13 of DOORBELL2_ICSR)
Doorbell 3, bit 13 (bit 13 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 12 (bit 12 of DOORBELL0_ICSR)
Doorbell 1, bit 12 (bit 12 of DOORBELL1_ICSR)
Doorbell 2, bit 12 (bit 12 of DOORBELL2_ICSR)
Doorbell 3, bit 12 (bit 12 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 11 (bit 11 of DOORBELL0_ICSR)
Doorbell 1, bit 11 (bit 11 of DOORBELL1_ICSR)
Doorbell 2, bit 11 (bit 11 of DOORBELL2_ICSR)
Doorbell 3, bit 11 (bit 11 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 10 (bit 10 of DOORBELL0_ICSR)
Doorbell 1, bit 10 (bit 10 of DOORBELL1_ICSR)
Doorbell 2, bit 10 (bit 10 of DOORBELL2_ICSR)
Doorbell 3, bit 10 (bit 10 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 9 (bit 9 of DOORBELL0_ICSR)
Doorbell 1, bit 9 (bit 9 of DOORBELL1_ICSR)
Doorbell 2, bit 9 (bit 9 of DOORBELL2_ICSR)
Doorbell 3, bit 9 (bit 9 of DOORBELL3_ICSR)
8
ISD8
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 8 (bit 8 of DOORBELL0_ICSR)
Doorbell 1, bit 8 (bit 8 of DOORBELL1_ICSR)
Doorbell 2, bit 8 (bit 8 of DOORBELL2_ICSR)
Doorbell 3, bit 8 (bit 8 of DOORBELL3_ICSR)
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Table 84. Interrupt Status Decode Register (INTDSTn_DECODE) Field Descriptions (continued)
Bit
Field
Value Description
7
ISD7
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 7 (bit 7 of DOORBELL0_ICSR)
Doorbell 1, bit 7 (bit 7 of DOORBELL1_ICSR)
Doorbell 2, bit 7 (bit 7 of DOORBELL2_ICSR)
Doorbell 3, bit 7 (bit 7 of DOORBELL3_ICSR)
6
5
4
3
2
1
0
ISD6
ISD5
ISD4
ISD3
ISD2
ISD1
ISD0
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 6 (bit 6 of DOORBELL0_ICSR)
Doorbell 1, bit 6 (bit 6 of DOORBELL1_ICSR)
Doorbell 2, bit 6 (bit 6 of DOORBELL2_ICSR)
Doorbell 3, bit 6 (bit 6 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 5 (bit 5 of DOORBELL0_ICSR)
Doorbell 1, bit 5 (bit 5 of DOORBELL1_ICSR)
Doorbell 2, bit 5 (bit 5 of DOORBELL2_ICSR)
Doorbell 3, bit 5 (bit 5 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 4 (bit 4 of DOORBELL0_ICSR)
Doorbell 1, bit 4 (bit 4 of DOORBELL1_ICSR)
Doorbell 2, bit 4 (bit 4 of DOORBELL2_ICSR)
Doorbell 3, bit 4 (bit 4 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 3 (bit 3 of DOORBELL0_ICSR)
Doorbell 1, bit 3 (bit 3 of DOORBELL1_ICSR)
Doorbell 2, bit 3 (bit 3 of DOORBELL2_ICSR)
Doorbell 3, bit 3 (bit 3 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 2 (bit 2 of DOORBELL0_ICSR)
Doorbell 1, bit 2 (bit 2 of DOORBELL1_ICSR)
Doorbell 2, bit 2 (bit 2 of DOORBELL2_ICSR)
Doorbell 3, bit 2 (bit 2 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 1 (bit 1 of DOORBELL0_ICSR)
Doorbell 1, bit 1 (bit 1 of DOORBELL1_ICSR)
Doorbell 2, bit 1 (bit 1 of DOORBELL2_ICSR)
Doorbell 3, bit 1 (bit 1 of DOORBELL3_ICSR)
0
1
No interrupt request routed to this bit.
Interrupt request detected. Possible interrupt sources:
•
•
•
•
Doorbell 0, bit 0 (bit 0 of DOORBELL0_ICSR)
Doorbell 1, bit 0 (bit 0 of DOORBELL1_ICSR)
Doorbell 2, bit 0 (bit 0 of DOORBELL2_ICSR)
Doorbell 3, bit 0 (bit 0 of DOORBELL3_ICSR)
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5.32 INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL)
There are eight interrupt rate control registers, one for each interrupt destination (see Table 85). Figure 93
and Table 86 provide a general description for an interrupt rate control register. These registers are used
to set the rate at which an interrupt can be generated for each interrupt destination. A write to one of the
registers reloads a counter and immediately starts the counter decrementing. When the counter value
reaches 0 (after counting down or after a CPU write of 0), the interrupt logic generates a single interrupt
pulse if any bits in the corresponding ICSR are set (or become set after the zero count is reached). For
Table 85. INTDSTn_RATE_CNTL Registers and the Associated Interrupt
Destinations
Register
Address Offset
Associated Interrupt
Destination
INTDST0_RATE_CNTL
INTDST1_RATE_CNTL
INTDST2_RATE_CNTL
INTDST3_RATE_CNTL
INTDST4_RATE_CNTL
INTDST5_RATE_CNTL
INTDST6_RATE_CNTL
INTDST7_RATE_CNTL
0320h
0324h
0328h
032Ch
0330h
0334h
0338h
033Ch
INTDST0
INTDST1
INTDST2
INTDST3
INTDST4
INTDST5
INTDST6
INTDST7
Figure 93. INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL)
31
0
COUNT_DOWN_VALUE
R/W-00000000h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 86. INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL) Field Descriptions
Bit
Field
Value
Description
31–0
COUNT_DOWN_VALUE
00000000h
to
FFFFFFFFh
The value written to this field is immediately transferred to the interrupt
rate counter, which starts counting down (or causes an interrupt if 0 is
written).
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5.33 LSUn Control Register 0 (LSUn_REG0)
There are four of these registers, one for each LSU (see Table 87). The general description for an LSU
Table 87. LSUn_REG0 Registers and the Associated LSUs
Register
Address Offset
0400h
Associated LSU
LSU1
LSU1_REG0
LSU2_REG0
LSU3_REG0
LSU4_REG0
0420h
LSU2
0440h
LSU3
0460h
LSU4
Figure 94. LSUn Control Register 0 (LSUn_REG0)
31
0
ADDRESS_MSB
R/W-00h
LEGEND: R/W = Read/Write; -n = Value after reset
Table 88. LSUn Control Register 0 (LSUn_REG0) Field Descriptions
Bit
Field
Value
Description
31–0
ADDRESS_MSB
00000000h
to
32-bit most significant bits of an extended address specified through LSUn.
FFFFFFFFh
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5.34 LSUn Control Register 1 (LSUn_REG1)
There are four of these registers, one for each LSU (see ). This register's content is shown in Figure 95
Table 89. LSUn_REG1 Registers and the Associated LSUs
Register
Address Offset
0404h
Associated LSU
LSU1
LSU1_REG1
LSU2_REG1
LSU3_REG1
LSU4_REG1
0424h
LSU2
0444h
LSU3
0464h
LSU4
Figure 95. LSUn Control Register 1 (LSUn_REG1)
31
0
ADDRESS_LSB/CONFIG_OFFSET
R/W-00000000h
LEGEND: R/W = Read/Write; -n = Value after reset
Table 90. LSUn Control Register 1 (LSUn_REG1) Field Descriptions
Bit
Field
Value
Description
31–0
ADDRESS_LSB/CONFIG_OFFSET
00000000h
to
FFFFFFFFh
For packet types 2, 5, and 6:
The 32-bit destination address or the 32 least significant bits of
an extended destination address. This value is used in
conjunction with BYTE_COUNT to create a 64-bit aligned
RapidIO packet header address.
For packet type 8 (maintenance packet):
00000000h
to
00FFFFFFh
The right-aligned 24-bit register configuration offset. This value is
used in conjunction with BYTE_COUNT to create a 64-bit aligned
RapidIO packet header Config_offset value. The 2 LSBs of this
field must be 0s because the smallest configuration access is 4
bytes.
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5.35 LSUn Control Register 2 (LSUn_REG2)
Table 91. LSUn_REG2 Registers and the Associated LSUs
Register
Address Offset
0408h
Associated LSU
LSU1
LSU1_REG2
LSU2_REG2
LSU3_REG2
LSU4_REG2
0428h
LSU2
0448h
LSU3
0468h
LSU4
Figure 96. LSUn Control Register 2 (LSUn_REG2)
31
0
DSP_ADDRESS
R/W-00000000h
LEGEND: R/W = Read/Write; -n = Value after reset
Table 92. LSUn Control Register 2 (LSUn_REG2) Field Descriptions
Bit
Field
Value
Description
31–0
DSP_ADDRESS
00000000h
to
32-bit DSP byte address for the source of the LSU transaction
FFFFFFFFh
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5.36 LSUn Control Register 3 (LSUn_REG3)
Table 93. LSUn_REG3 Registers and the Associated LSUs
Register
Address Offset
040Ch
Associated LSU
LSU1
LSU1_REG3
LSU2_REG3
LSU3_REG3
LSU4_REG3
042Ch
LSU2
044Ch
LSU3
046Ch
LSU4
Figure 97. LSUn Control Register 3 (LSUn_REG3)
31
15
16
0
Reserved
R-0000h
12 11
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
BYTE_COUNT
R/W-000h
Table 94. LSUn Control Register 3 (LSUn_REG3) Field Descriptions
Bit
Field
Value
00000h
Description
These read-only bits return 0s when read.
31–12
11–0
Reserved
BYTE_COUNT
000h–FFFh
Number of data bytes to read or write, up to 4K bytes. This value is used in
conjunction with the specified RapidIO address to create the data size and word
pointer fields in the RapidIO packet header.
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5.37 LSUn Control Register 4 (LSUn_REG4)
Table 95. LSUn_REG4 Registers and the Associated LSUs
Register
Address Offset
0410h
Associated LSU
LSU1
LSU1_REG4
LSU2_REG4
LSU3_REG4
LSU4_REG4
0430h
LSU2
0450h
LSU3
0470h
LSU4
Figure 98. LSUn Control Register 4 (LSUn_REG4)
31
OUTPORTID
R/W-00
30 29
28 27
26 25
24 23
PRIORITY
R/W-00
XAMSB
R/W-00
ID_SIZE
R/W-00
DESTID
R/W-0000h
8
7
1
0
INTERRUPT_
REQ
DESTID
Reserved
R-00h
R/W-0000h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
R/W-0
Table 96. LSUn Control Register 4 (LSUn_REG4) Field Descriptions
Bit
Field
Value
Description
31–30
OUTPORTID
00b–11b
Indicates the number of the output port (0, 1, 2, or 3) from which the packet is to
be transmitted. Specified by the CPU along with the node ID. The output port
value is not included in the RapidIO header.
29–28
PRIORITY
00b–11b
00b–11b
Supplies the prio field of the RapidIO packet header to indicate packet priority.
To avoid system deadlock, it is recommended that request packets not be sent
with priority level 3. It is the responsibility of the software to assign the
appropriate outgoing priority.
27–26
25–24
XAMSB
ID_SIZE
Supplies the xamsb field of the RapidIO packet header to specify the 2 MSBs of
the extended RapidIO address.
Supplies the tt field of the RapidIO packet header to specify whether 8-bit or
16-bit DeviceIDs are used.
00b
01b
8 bit device IDs
16 bit device IDs
Reserved
1xb
23–8
DESTID
0000h
Supplies the destination ID field of the RapidIO packet header to specifying
target device.
7–1
0
Reserved
00h
These read-only bits return 0s when read.
INTERRUPT_REQ
Indicates whether the CPU requests an interrupt upon completion of the LSU
command. This is a CPU-controlled request bit and is typically used in
conjunction with non-posted commands to alert the CPU when the requested
data/status is present.
0
1
Interrupt not requested upon completion of command
Interrupt requested upon completion of command
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5.38 LSUn Control Register 5 (LSUn_REG5)
Table 97. LSUn_REG5 Registers and the Associated LSUs
Register
Address Offset
0414h
Associated LSU
LSU1
LSU1_REG5
LSU2_REG5
LSU3_REG5
LSU4_REG5
0434h
LSU2
0454h
LSU3
0474h
LSU4
Figure 99. LSUn Control Register 5 (LSUn_REG5)
31
15
16
0
DRBLL_INFO
R/W-0000h
8
7
HOP_COUNT
R/W-00h
LEGEND: R/W = Read/Write; -n = Value after reset
PACKET_TYPE
R/W-00h
Table 98. LSUn Control Register 5 (LSUn_REG5) Field Descriptions
Bit
31–16
15–8
7–0
Field
Value
0000h–FFFFh
00h–FFh
Description
DRBLL_INFO
HOP_COUNT
PACKET_TYPE
RapidIO hop count field specified for type 8 (maintenance) packets
00h–FFh
The 4 MSBs specify the ftype field for all packet types, and the 4 LSBs
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5.39 LSUn Control Register 6 (LSUn_REG6)
There are four of these registers, one for each LSU (see Table 99). LSUn_REG6 is shown in Figure 100
Table 99. LSUn_REG6 Registers and the Associated LSUs
Register
Address Offset
0418h
Associated LSU
LSU1
LSU1_REG6
LSU2_REG6
LSU3_REG6
LSU4_REG6
0438h
LSU2
0458h
LSU3
0478h
LSU4
Figure 100. LSUn Control Register 6 (LSUn_REG6)
31
15
16
Reserved
R-0000h
5
4
1
0
Reserved
R-000h
COMPLETION_CODE
R-0000
BSY
R-0
LEGEND: R = Read only; -n = Value after reset
Table 100. LSUn Control Register 6 (LSUn_REG6) Field Descriptions
Bit
31–5
4–1
Field
Value
Description
Reserved
0000h
These read-only bits return 0s when read.
Indicates the status of the pending command.
Transaction complete, no errors (posted/non-posted)
Transaction timeout occurred on non-posted transaction
COMPLETION_CODE
0000b
0001b
0010 b
0011b
Transaction complete, packet not sent due to flow control blockade (Xoff)
Transaction complete, non-posted response packet (type 8 and 13)
contained ERROR status, or response payload length was in error
0100b
Transaction complete, packet not sent due to unsupported transaction type or
invalid programming encoding for one or more LSU register fields
0101b
0110b
DMA data transfer error
"Retry" DOORBELL response received, or Atomic test-and-swap was not
allowed (semaphore in use)
0111b
1xxxb
Transaction complete, packet not sent due to unavailable outbound credit at
given priority
Reserved
0
BSY
Indicates status of the writeable LSU registers
LSU registers available (writable) for next set of transfer descriptors
LSU registers busy with current transfer
0
1
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5.40 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS)
Table 101. LSUn_FLOW_MASKS Registers and the Associated LSUs
Register
Address Offset
041Ch
LSU
LSU1_FLOW_MASKS
LSU2_FLOW_MASKS
LSU3_FLOW_MASKS
LSU4_FLOW_MASKS
LSU1
LSU2
LSU3
LSU4
043Ch
045Ch
047Ch
Figure 101. LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS)
31
16 15
0
Reserved
R-00h
FLOW_MASK
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 102. LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) Field Descriptions
Bit
Field
Value
00h
Description
31–16
15–0
Reserved
FLOW_MASK
These read-only bits return 0s when read.
Flow mask for LSUn
00h-FFh
Figure 102. LSUn FLOW_MASK Fields
15
FL15
14
13
12
11
FL11
10
9
8
7
6
5
4
3
2
1
0
FL14
FL13
FL12
FL10
FL9
FL8
FL7
FL6
FL5
FL4
FL3
FL2
FL1
FL0
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R = Read; W = Write; -n = Value after reset
Table 103. LSUn FLOW_MASK Fields
Bit
Field
Value Description
LSUn does not support Flow 15 from table entry
15
FL15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LSUn supports Flow 15 from table entry
LSUn does not support Flow 14 from table entry
LSUn supports Flow 14 from table entry
LSUn does not support Flow 13 from table entry
LSUn supports Flow 13 from table entry
LSUn does not support Flow 12 from table entry
LSUn supports Flow 12 from table entry
LSUn does not support Flow 11 from table entry
LSUn supports Flow 11 from table entry
LSUn does not support Flow 10 from table entry
LSUn supports Flow 10 from table entry
LSUn does not support Flow 9 from table entry
LSUn supports Flow 9 from table entry
14
13
12
11
10
9
FL14
FL13
FL12
FL11
FL10
FL9
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Table 103. LSUn FLOW_MASK Fields (continued)
Bit
Field
Value Description
8
7
6
5
4
3
2
1
0
FL8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LSUn does not support Flow 8 from table entry
LSUn supports Flow 8 from table entry
FL7
FL6
FL5
FL4
FL3
FL2
FL1
FL0
LSUn does not support Flow 7 from table entry
LSUn supports Flow 7 from table entry
LSUn does not support Flow 6 from table entry
LSUn supports Flow 6 from table entry
LSUn does not support Flow 5 from table entry
LSUn supports Flow 5 from table entry
LSUn does not support Flow 4 from table entry
LSUn supports Flow 4 from table entry
LSUn does not support Flow 3 from table entry
LSUn supports Flow 3 from table entry
LSUn does not support Flow 2 from table entry
LSUn supports Flow 2 from table entry
LSUn does not support Flow 1 from table entry
LSUn supports Flow 1 from table entry
LSUn does not support Flow 0 from table entry
LSUn supports Flow 0 from table entry
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5.41 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP)
Table 104. QUEUEn_TXDMA_HDP Registers
Register
Address Offset
0500h
QUEUE0_TXDMA_HDP
QUEUE1_TXDMA_HDP
QUEUE2_TXDMA_HDP
QUEUE3_TXDMA_HDP
QUEUE4_TXDMA_HDP
QUEUE5_TXDMA_HDP
QUEUE6_TXDMA_HDP
QUEUE7_TXDMA_HDP
QUEUE8_TXDMA_HDP
QUEUE9_TXDMA_HDP
QUEUE10_TXDMA_HDP
QUEUE11_TXDMA_HDP
QUEUE12_TXDMA_HDP
QUEUE13_TXDMA_HDP
QUEUE14_TXDMA_HDP
QUEUE15_TXDMA_HDP
0504h
0508h
050Ch
0510h
0514h
0518h
051Ch
0520h
0524h
0528h
052Ch
0530h
0534h
0538h
053Ch
Figure 103. Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP)
31
0
TX_HDP
R/W-00000000h
LEGEND: R/W = Read/Write; -n = Value after reset
Table 105. Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) Field
Descriptions
Bit
Field
Value
Description
31–0
TX_HDP
00000000h
to
FFFFFFFCh
This field is the memory address for the first buffer descriptor in the transmit
queue. This field is written by the DSP core to initiate queue transmit operations
and is zeroed by the port when all packets in the queue have been transmitted.
An error condition results if the DSP core writes this field when the current field
value is nonzero. The address must be 32-bit word aligned (the 2 LSBs must be
0s).
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5.42 Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP)
Table 106. QUEUEn_TXDMA_CP Registers
Register
Address Offset
0580h
QUEUE0_TXDMA_CP
QUEUE1_TXDMA_CP
QUEUE2_TXDMA_CP
QUEUE3_TXDMA_CP
QUEUE4_TXDMA_CP
QUEUE5_TXDMA_CP
QUEUE6_TXDMA_CP
QUEUE7_TXDMA_CP
QUEUE8_TXDMA_CP
QUEUE9_TXDMA_CP
QUEUE10_TXDMA_CP
QUEUE11_TXDMA_CP
QUEUE12_TXDMA_CP
QUEUE13_TXDMA_CP
QUEUE14_TXDMA_CP
QUEUE15_TXDMA_CP
0584h
0588h
058Ch
0590h
0594h
0598h
059Ch
05A0h
05A4h
05A8h
05ACh
05B0h
05B4h
05B8h
05BCh
Figure 104. Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP)
31
0
TX_CP
R/W-00000000h
LEGEND: R/W = Read/Write; -n = Value after reset
Table 107. Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) Field
Descriptions
Bit
Field
Value
Description
31–0
TX_CP
00000000h
to
FFFFFFFFh
This field is the memory address for the transmit queue completion pointer. This
register is written by the DSP core with the buffer descriptor address for the last
buffer processed by the host during interrupt processing. The port uses the value
written to determine if the interrupt should be deasserted.
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5.43 Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP)
Table 108. QUEUEn_RXDMA_HDP Registers
Register
Address Offset
0600h
QUEUE0_RXDMA_HDP
QUEUE1_RXDMA_HDP
QUEUE2_RXDMA_HDP
QUEUE3_RXDMA_HDP
QUEUE4_RXDMA_HDP
QUEUE5_RXDMA_HDP
QUEUE6_RXDMA_HDP
QUEUE7_RXDMA_HDP
QUEUE8_RXDMA_HDP
QUEUE9_RXDMA_HDP
QUEUE10_RXDMA_HDP
QUEUE11_RXDMA_HDP
QUEUE12_RXDMA_HDP
QUEUE13_RXDMA_HDP
QUEUE14_RXDMA_HDP
QUEUE15_RXDMA_HDP
0604h
0608h
060Ch
0610h
0614h
0618h
061Ch
0620h
0624h
0628h
062Ch
0630h
0634h
0638h
063Ch
Figure 105. Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP)
31
0
RX_HDP
R/W-00000000h
LEGEND: R/W = Read/Write; -n = Value after reset
Table 109. Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP) Field
Descriptions
Bit
Field
Value
Description
31–0
RX_HDP
00000000h
to
FFFFFFFCh
RX Queue Head Descriptor Pointer: This field is the memory address for the first
buffer descriptor in the channel receive queue. This field is written by the DSP
core to initiate queue receive operations and is zeroed by the port when all free
buffers have been used. An error condition results if the DSP core writes this
field when the current field value is nonzero. The address must be 32-bit word
aligned (the 2 LSBs must be 0s).
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5.44 Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP)
Table 110. QUEUEn_RXDMA_CP Registers
Register
Address Offset
0680h
QUEUE0_RXDMA_CP
QUEUE1_RXDMA_CP
QUEUE2_RXDMA_CP
QUEUE3_RXDMA_CP
QUEUE4_RXDMA_CP
QUEUE5_RXDMA_CP
QUEUE6_RXDMA_CP
QUEUE7_RXDMA_CP
QUEUE8_RXDMA_CP
QUEUE9_RXDMA_CP
QUEUE10_RXDMA_CP
QUEUE11_RXDMA_CP
QUEUE12_RXDMA_CP
QUEUE13_RXDMA_CP
QUEUE14_RXDMA_CP
QUEUE15_RXDMA_CP
0684h
0688h
068Ch
0690h
0694h
0698h
069Ch
06A0h
06A4h
06A8h
06ACh
06B0h
06B4h
06B8h
06BCh
Figure 106. Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP)
31
0
RX_CP
R/W-00000000h
LEGEND: R/W = Read/Write; -n = Value after reset
Table 111. Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) Field
Descriptions
Bit
Field
Value
Description
31–0
RX_CP
00000000h
to
This field is the memory address for the receive queue completion pointer. This
register is written by the DSP core with the buffer descriptor address for the last
FFFFFFFFh
buffer processed by the DSP core during interrupt processing. The port uses the
value written to determine if the interrupt should be deasserted.
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5.45 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)
Each bit in this register corresponds to one of the 16 TX buffer descriptor queues. If a 1 is written to a bit,
the teardown process is initiated for the associated queue. TX_QUEUE_TEAR_DOWN is shown in
Figure 107. Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) - Address Offset 0700h
31
16
Reserved
R-0000h
15
14
13
12
11
10
9
8
QUEUE15_
TEAR_DWN
QUEUE14_
TEAR_DWN
QUEUE13_
TEAR_DWN
QUEUE12_
TEAR_DWN
QUEUE11_
TEAR_DWN
QUEUE10_
TEAR_DWN
QUEUE9_
TEAR_DWN
QUEUE8_
TEAR_DWN
W-0
7
W-0
6
W-0
5
W-0
4
W-0
3
W-0
2
W-0
1
W-0
0
QUEUE7_
QUEUE6_
QUEUE5_
QUEUE4_
QUEUE3_
QUEUE2_
QUEUE1_
QUEUE0_
TEAR_DWN
TEAR_DWN
TEAR_DWN
TEAR_DWN
TEAR_DWN
TEAR_DWN
TEAR_DWN
TEAR_DWN
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Table 112. Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions
Bit
Field
Value Description
31–16 Reserved
0
These read-oinly bits return 0s when read.
15–0 QUEUEn_TEAR_DWN
Queue n tear down
No effect
(n = 15 to 0)
0
1
Tear down Queue n.
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5.46 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0–7])
Each of the eight TX CPPI flow mask registers holds the flow masks for two TX descriptor buffer queues
(see Table 113). Figure 108 shows the registers, and Figure 109 shows the general form of a flow mask.
Each bit of a flow mask selects or deselects a flow for the associated TX queue (see Table 114). For
Table 113. TX_CPPI_FLOW_MASKS Registers and the Associated TX Queues
Register
Address Offset
0704h
Associated TX Queues
Queues 0 and 1
TX_CPPI_FLOW_MASKS0
TX_CPPI_FLOW_MASKS1
TX_CPPI_FLOW_MASKS2
TX_CPPI_FLOW_MASKS3
TX_CPPI_FLOW_MASKS4
TX_CPPI_FLOW_MASKS5
TX_CPPI_FLOW_MASKS6
TX_CPPI_FLOW_MASKS7
0708h
Queues 2 and 3
070Ch
Queues 4 and 5
0710h
Queues 6 and 7
0714h
Queues 8 and 9
0718h
Queues 10 and 11
Queues 12 and 13
Queues 14 and 15
071Ch
0720h
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Figure 108. Transmit CPPI Supported Flow Mask Registers
Transmit CPPI Supported Flow Mask Register 0 (TX_CPPI_FLOW_MASKS0)
31 16 15
0
QUEUE1_FLOW_MASK
R/W-FFh
QUEUE0_FLOW_MASK
R/W-FFh
Transmit CPPI Supported Flow Mask Register 1 (TX_CPPI_FLOW_MASKS1)
31 16 15
0
0
0
0
0
0
0
QUEUE3_FLOW_MASK
R/W-FFh
QUEUE2_FLOW_MASK
R/W-FFh
Transmit CPPI Supported Flow Mask Register 2 (TX_CPPI_FLOW_MASKS2)
31 16 15
QUEUE5_FLOW_MASK
R/W-FFh
QUEUE4_FLOW_MASK
R/W-FFh
Transmit CPPI Supported Flow Mask Register 3 (TX_CPPI_FLOW_MASKS3)
31 16 15
QUEUE7_FLOW_MASK
R/W-FFh
QUEUE6_FLOW_MASK
R/W-FFh
Transmit CPPI Supported Flow Mask Register 4 (TX_CPPI_FLOW_MASKS4)
31 16 15
QUEUE9_FLOW_MASK
R/W-FFh
QUEUE8_FLOW_MASK
R/W-FFh
Transmit CPPI Supported Flow Mask Register 5 (TX_CPPI_FLOW_MASKS5)
31 16 15
QUEUE11_FLOW_MASK
R/W-FFh
QUEUE10_FLOW_MASK
R/W-FFh
Transmit CPPI Supported Flow Mask Register 6 (TX_CPPI_FLOW_MASKS6)
31 16 15
QUEUE13_FLOW_MASK
R/W-FFh
QUEUE12_FLOW_MASK
R/W-FFh
Transmit CPPI Supported Flow Mask Register 7 (TX_CPPI_FLOW_MASKS7)
31 16 15
QUEUE15_FLOW_MASK
R/W-FFh
QUEUE14_FLOW_MASK
R/W-FFh
LEGEND: R/W = Read/Write; -n = Value after reset
Figure 109. TX Queue n FLOW_MASK Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FL15
FL14
FL13
FL12
FL11
FL10
FL9
FL8
FL7
FL6
FL5
FL4
FL3
FL2
FL1
FL0
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; -n = Value after reset
Table 114. TX Queue n FLOW_MASK Field Descriptions
Bit
Field
Value Description
15
FL15
0
1
0
1
0
1
Queue n does not support Flow 15 from table entry
Queue n supports Flow 15 from table entry
Queue n does not support Flow 14 from table entry
Queue n supports Flow 14 from table entry
Queue n does not support Flow 13 from table entry
Queue n supports Flow 13 from table entry
14
13
FL14
FL13
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Table 114. TX Queue n FLOW_MASK Field Descriptions (continued)
Bit
Field
Value Description
12
11
10
9
FL12
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Queue n does not support Flow 12 from table entry
Queue n supports Flow 12 from table entry
Queue n does not support Flow 11 from table entry
Queue n supports Flow 11 from table entry
Queue n does not support Flow 10 from table entry
Queue n supports Flow 10 from table entry
Queue n does not support Flow 9 from table entry
Queue n supports Flow 9 from table entry
FL11
FL10
FL9
FL8
FL7
FL6
FL5
FL4
FL3
FL2
FL1
FL0
8
Queue n does not support Flow 8 from table entry
Queue n supports Flow 8 from table entry
7
Queue n does not support Flow 7 from table entry
Queue n supports Flow 7 from table entry
6
Queue n does not support Flow 6 from table entry
Queue n supports Flow 6 from table entry
5
Queue n does not support Flow 5 from table entry
Queue n supports Flow 5 from table entry
4
Queue n does not support Flow 4 from table entry
Queue n supports Flow 4 from table entry
3
Queue n does not support Flow 3 from table entry
Queue n supports Flow 3 from table entry
2
Queue n does not support Flow 2 from table entry
Queue n supports Flow 2 from table entry
1
Queue n does not support Flow 1 from table entry
Queue n supports Flow 1 from table entry
0
Queue n does not support Flow 0 from table entry
Queue n supports Flow 0 from table entry
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5.47 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN)
Each of this register's bits corresponds to one of the 16 RX buffer descriptor queues. If a 1 is written to a
bit, the teardown process is started for the associated queue. RX_QUEUE_TEAR_DOWN is shown in
Figure 110 and described in Table 115. For additional programming information, see Section 2.3.4.1 .
Figure 110. Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) (Address Offset 0740h)
31
16
Reserved
R-0000h
15
14
13
12
11
10
9
8
QUEUE15_
TEAR_DWN
QUEUE14_
TEAR_DWN
QUEUE13_
TEAR_DWN
QUEUE12_
TEAR_DWN
QUEUE11_
TEAR_DWN
QUEUE10_
TEAR_DWN
QUEUE9_
TEAR_DWN
QUEUE8_
TEAR_DWN
W-0
7
W-0
6
W-0
5
W-0
4
W-0
3
W-0
2
W-0
1
W-0
0
QUEUE7_
QUEUE6_
QUEUE5_
QUEUE4_
QUEUE3_
QUEUE2_
QUEUE1_
QUEUE0_
TEAR_DWN
TEAR_DWN
TEAR_DWN
TEAR_DWN
TEAR_DWN
TEAR_DWN
TEAR_DWN
TEAR_DWN
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: R = Read only; W = Write; -n = Value after reset
Table 115. Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions
Bit
Field
Value
Description
31–16
15–0
Reserved
0000h
These read-only bits return 0s when read.
Queue n tear down
No effect
QUEUEn_TEAR_DWN
(n = 15 to 0)
0
1
Tear down Queue n.
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5.48 Receive CPPI Control Register (RX_CPPI_CNTL)
Each bit in this register indicates whether the associated RX buffer descriptor queue must receive
messages in the order the source device attempts to transmit them. RX_CPPI_CNTL is shown in and
Figure 111. Receive CPPI Control Register (RX_CPPI_CNTL) (Address Offset 0744h)
31
23
24
16
Reserved
R-00h
Reserved
R-00h
15
14
13
12
11
10
9
8
QUEUE15_
IN_ORDER
QUEUE14_
IN_ORDER
QUEUE13_
IN_ORDER
QUEUE12_
IN_ORDER
QUEUE11_
IN_ORDER
QUEUE10_
IN_ORDER
QUEUE9_
IN_ORDER
QUEUE8_
IN_ORDER
R/W-0
7
R/W-0
6
R/W-0
5
R/W-0
4
R/W-0
3
R/W-0
2
R/W-0
1
R/W-0
0
QUEUE7_
QUEUE6_
QUEUE5_
QUEUE4_
QUEUE3_
QUEUE2_
QUEUE1_
QUEUE0_
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
IN_ORDER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 116. Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions
Bit
Field
Value
Description
31–16
15–0
Reserved
0000h
Reserved
QUEUEn_IN_ORDER
Queuen in order
(n = 15 to 0)
0
1
Allows out-of-order message reception
Requires in-order message reception. Used for applications with
dedicated source-destination flows.
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5.49 Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0–3])
The transmission order among TX buffer descriptor queues is based on the programmable weighted
round-robin scheme explained in Section 2.3.4.2. As part of this scheme, software must program the 16
mappers to determine the order in which the queues are serviced and how many messages are handled
in each queue during each time around the round-robin cycle. The mappers are programmed with the
registers shown in Figure 112. The register fields are described in Table 117. For additional programming
Figure 112. Transmit CPPI Weighted Round Robin Control Registers
TX_QUEUE_CNTL0 - Address Offset 07E0h
<-------------------------------- TX_Queue_Map3 ----------------------------->
<-------------------------------- TX_Queue_Map2 ----------------------------->
20 19 16
31 28 27 24 23
Number of Msgs
R/W-0h
Queue Pointer
R/W-3h
Number of Msgs
R/W-0
Queue Pointer
R/W-2h
<-------------------------------- TX_Queue_Map1 ----------------------------->
15 12 11
<-------------------------------- TX_Queue_Map0 ----------------------------->
8
7
4
3
0
Number of Msgs
R/W-0h
Queue Pointer
R/W-1h
Number of Msgs
R/W-0h
Queue Pointer
R/W-0h
TX_QUEUE_CNTL1 - Address Offset 07E4h
<-------------------------------- TX_Queue_Map7 ----------------------------->
<-------------------------------- TX_Queue_Map6 ----------------------------->
31
28 27
24 23 20 19 16
Number of Msgs
R/W-0
Queue Pointer
R/W-7h
Number of Msgs
R/W-0h
Queue Pointer
R/W-6h
<-------------------------------- TX_Queue_Map5 ----------------------------->
15 12 11
<-------------------------------- TX_Queue_Map4 ----------------------------->
8
7
4
3
0
Number of Msgs
R/W-0h
Queue Pointer
R/W-5h
Number of Msgs
R/W-0h
Queue Pointer
R/W-4h
TX_QUEUE_CNTL2 - Address Offset 07E8h
<-------------------------------- TX_Queue_Map11 -----------------------------> <-------------------------------- TX_Queue_Map10 ----------------------------->
31 28 27 24 23 20 19 16
Number of Msgs
R/W-0h
Queue Pointer
R/W-Bh
Number of Msgs
R/W-0h
Queue Pointer
R/W-Ah
<-------------------------------- TX_Queue_Map9 ----------------------------->
15 12 11
<-------------------------------- TX_Queue_Map8 ----------------------------->
8
7
4
3
0
Number of Msgs
R/W-0h
Queue Pointer
R/W-9h
Number of Msgs
R/W-0h
Queue Pointer
R/W-8h
TX_QUEUE_CNTL3 - Address Offset 07ECh
<-------------------------------- TX_Queue_Map15 -----------------------------> <-------------------------------- TX_Queue_Map14 ----------------------------->
31 28 27 24 23 20 19 16
Number of Msgs
R/W-0h
Queue Pointer
R/W-Fh
Number of Msgs
R/W-0h
Queue Pointer
R/W-Eh
<-------------------------------- TX_Queue_Map13 -----------------------------> <-------------------------------- TX_Queue_Map12 ----------------------------->
15
12 11
8
7
4
3
0
Number of Msgs
R/W-0h
Queue Pointer
R/W-Dh
Number of Msgs
R/W-0h
Queue Pointer
R/W-Ch
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Table 117. Transmit CPPI Weighted Round Robin Control Register Field Descriptions
Field Pair
Register[Bits]
Field
Value
Description
TX_Queue_Map0
TX_Queue_Map1
TX_Queue_Map2
TX_Queue_Map3
TX_Queue_Map4
TX_Queue_Map5
TX_Queue_Map6
TX_Queue_Map7
TX_Queue_Map8
TX_QUEUE_CNTL0[3–0]
Queue Pointer
0h to Fh
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
TX_QUEUE_CNTL0[7–4]
Number of Msgs
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map1.
TX_QUEUE_CNTL0[11–8] Queue Pointer
TX_QUEUE_CNTL0[15–12] Number of Msgs
TX_QUEUE_CNTL0[19–16] Queue Pointer
TX_QUEUE_CNTL0[23–20] Number of Msgs
TX_QUEUE_CNTL0[27–24] Queue Pointer
TX_QUEUE_CNTL0[31–28] Number of Msgs
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map2.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map3.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map4.
TX_QUEUE_CNTL1[3–0]
TX_QUEUE_CNTL1[7–4]
Queue Pointer
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of Msgs
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map5.
TX_QUEUE_CNTL1[11–8] Queue Pointer
TX_QUEUE_CNTL1[15–12] Number of Msgs
TX_QUEUE_CNTL1[19–16] Queue Pointer
TX_QUEUE_CNTL1[23–20] Number of Msgs
TX_QUEUE_CNTL1[27–24] Queue Pointer
TX_QUEUE_CNTL1[31–28] Number of Msgs
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map6.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map7.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map8.
TX_QUEUE_CNTL2[3–0]
TX_QUEUE_CNTL2[7–4]
Queue Pointer
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of Msgs
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map9.
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Table 117. Transmit CPPI Weighted Round Robin Control Register Field Descriptions (continued)
Field Pair
Register[Bits]
Field
Value
Description
TX_Queue_Map9
TX_QUEUE_CNTL2[11–8] Queue Pointer
TX_QUEUE_CNTL2[15–12] Number of Msgs
TX_QUEUE_CNTL2[19–16] Queue Pointer
TX_QUEUE_CNTL2[23–20] Number of Msgs
TX_QUEUE_CNTL2[27–24] Queue Pointer
TX_QUEUE_CNTL2[31–28] Number of Msgs
0h to Fh
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
0h to Fh
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map10.
TX_Queue_Map10
TX_Queue_Map11
TX_Queue_Map12
TX_Queue_Map13
TX_Queue_Map14
TX_Queue_Map15
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map11.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map12.
TX_QUEUE_CNTL3[3–0]
TX_QUEUE_CNTL3[7–4]
Queue Pointer
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of Msgs
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map13.
TX_QUEUE_CNTL3[11–8] Queue Pointer
TX_QUEUE_CNTL3[15–12] Number of Msgs
TX_QUEUE_CNTL3[19–16] Queue Pointer
TX_QUEUE_CNTL3[23–20] Number of Msgs
TX_QUEUE_CNTL3[27–24] Queue Pointer
TX_QUEUE_CNTL3[31–28] Number of Msgs
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map14.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map15.
Pointer to a queue. This pointer can be
programmed to point to any one of the 16
TX buffer descriptor queues.
Number of contiguous messages
(descriptors) to process before moving to
TX_Queue_Map0.
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5.50 Mailbox to Queue Mapping Registers (RXU_MAP_Ln and RXU_MAP_Hn)
Messages addressed to any of the 64 mailbox locations can be received on any of the RapidIO ports
simultaneously. Packets are handled sequentially in order of receipt. A block of 32 mappers directs the
inbound messages to the appropriate RX queues. After a device reset, software must configure each of
the mappers to map incoming messages with selected mailbox and letter numbers to the desired queue.
For a given mapper n, a pair of mailbox to queue mapping registers fully define the configuration for that
register pairs and the associated RX mappers. The general form of an RXU_MAP register pair is
Table 118. Mailbox to Queue Mapping Registers and the Associated RX
Mappers
Register
Address Offset
0800h
0804h
0808h
080Ch
0810h
0814h
0818h
081Ch
0820h
0824h
0828h
082Ch
0830h
0834h
0838h
083Ch
0840h
0844h
0848h
084Ch
0850h
0854h
0858h
085Ch
0860h
0864h
0868h
086Ch
0870h
0874h
0878h
087Ch
0880h
0884h
0888h
088Ch
Associated RX Mapper
Mapper 0
Mapper 0
Mapper 1
Mapper 1
Mapper 2
Mapper 2
Mapper 3
Mapper 3
Mapper 4
Mapper 4
Mapper 5
Mapper 5
Mapper 6
Mapper 6
Mapper 7
Mapper 7
Mapper 8
Mapper 8
Mapper 9
Mapper 9
Mapper 10
Mapper 10
Mapper 11
Mapper 11
Mapper 12
Mapper 12
Mapper 13
Mapper 13
Mapper 14
Mapper 14
Mapper 15
Mapper 15
Mapper 16
Mapper 16
Mapper 17
Mapper 17
RXU_MAP_L0
RXU_MAP_H0
RXU_MAP_L1
RXU_MAP_H1
RXU_MAP_L2
RXU_MAP_H2
RXU_MAP_L3
RXU_MAP_H3
RXU_MAP_L4
RXU_MAP_H4
RXU_MAP_L5
RXU_MAP_H5
RXU_MAP_L6
RXU_MAP_H6
RXU_MAP_L7
RXU_MAP_H7
RXU_MAP_L8
RXU_MAP_H8
RXU_MAP_L9
RXU_MAP_H9
RXU_MAP_L10
RXU_MAP_H10
RXU_MAP_L11
RXU_MAP_H11
RXU_MAP_L12
RXU_MAP_H12
RXU_MAP_L13
RXU_MAP_H13
RXU_MAP_L14
RXU_MAP_H14
RXU_MAP_L15
RXU_MAP_H15
RXU_MAP_L16
RXU_MAP_H16
RXU_MAP_L17
RXU_MAP_H17
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Table 118. Mailbox to Queue Mapping Registers and the Associated RX
Mappers (continued)
Register
Address Offset
0890h
Associated RX Mapper
Mapper 18
Mapper 18
Mapper 19
Mapper 19
Mapper 20
Mapper 20
Mapper 21
Mapper 21
Mapper 22
Mapper 22
Mapper 23
Mapper 23
Mapper 24
Mapper 24
Mapper 25
Mapper 25
Mapper 26
Mapper 26
Mapper 27
Mapper 27
Mapper 28
Mapper 28
Mapper 29
Mapper 29
Mapper 30
Mapper 30
Mapper 31
Mapper 31
RXU_MAP_L18
RXU_MAP_H18
RXU_MAP_L19
RXU_MAP_H19
RXU_MAP_L20
RXU_MAP_H20
RXU_MAP_L21
RXU_MAP_H21
RXU_MAP_L22
RXU_MAP_H22
RXU_MAP_L23
RXU_MAP_H23
RXU_MAP_L24
RXU_MAP_H24
RXU_MAP_L25
RXU_MAP_H25
RXU_MAP_L26
RXU_MAP_H26
RXU_MAP_L27
RXU_MAP_H27
RXU_MAP_L28
RXU_MAP_H28
RXU_MAP_L29
RXU_MAP_H29
RXU_MAP_L30
RXU_MAP_H30
RXU_MAP_L31
RXU_MAP_H31
0894h
0898h
089Ch
08A0h
08A4h
08A8h
08ACh
08B0h
08B4h
08B8h
08BCh
08C0h
08C4h
08C8h
08CCh
08D0h
08D4h
08D8h
08DCh
08E0h
08E4h
08E8h
08ECh
08F0h
08F4h
08F8h
08FCh
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Figure 113. Mailbox to Queue Mapping Register Pair
Mailbox to Queue Mapping Register L n (RXU_MAP_L n )
31 30 29
LETTER_MASK
R/W-11
24 23
22 21
16
0
MAILBOX_MASK
R/W-111111
LETTER
R/W-00
MAILBOX
R/W-000000
15
SOURCEID
R/W-0000h
Mailbox to Queue Mapping Register H n (RXU_MAP_H n )
31
Reserved
R-0
10
9
8
7
6
5
2
1
0
SEGMENT_
MAPPING
Reserved
R-0
TT
Reserved
R-00
QUEUE_ID
R/W-0000
PROMISCUOUS
R/W-0
R/W-01
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 119. Mailbox-to-Queue Mapping Register Ln (RXU_MAP_Ln) Field Descriptions
Bit
Field
Value
Description
31–30
LETTER_MASK
00b–11b
Letter mask. Each 0 in this field indicates a don't care bit in the letter
number. This allows mapper n to handle a set or range of letter numbers
rather than only one.
29–24
MAILBOX_MASK
Mailbox mask. Each 0 in this field indicates a don't care bit in the mailbox
number. This allows mapper n to handle a set or range of mailbox numbers
rather than only one.
For a single-segment message:
6-bit mailbox mask value
000000b–111111b
For a multi-segment message:
3-bit mailbox mask value
xxxx00b–xxxx11b
00b–11b
23–22
21–16
LETTER
Letter number. If LETTER_MASK = 11b, this is the only letter number
handled by mapper n. If LETTER_MASK is not 11b, mapper n handles the
set of letter numbers formed with the mask bit(s).
MAILBOX
Mailbox number. If MAILBOX_MASK = 111111b, this is the only mailbox
number handled by mapper n. If MAILBOX_MASK is not all 1s, mapper n
handles the set of mailbox numbers formed with the mask bit(s).
For a single-segment message:
6-bit mailbox number (0 to 63)
For a multi-segment message:
3-bit mailbox number (0 to 3)
000000b–111111b
xxxx00b–xxxx11b
0000h–FFFFh
15–0
SOURCEID
Source identification number. The SOURCEID field is used to indicate which
external device has access to mapper n and its corresponding queue. A
comparison is performed between the sourceID of the incoming message
packet and the SOURCEID field. If the values do not match, an ERROR
response is sent to the sender, and the transaction is logged in the logical
layer error management capture registers.
Table 120. Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) Field Descriptions
Bit
31–10
9–8
Field
Value
Description
Reserved
TT
0
These read-only bits return 0s when read.
Transport type
0
1
During the sourceID comparison, the incoming sourceID is compared
with the 8 LSBs of the SOURCEID field of RXU_MAP_Ln.
During the sourceID comparison, the incoming sourceID is compared
with all 16 bits of the SOURCEID field of RXU_MAP_Ln.
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Table 120. Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) Field Descriptions (continued)
Bit
7–6
5–2
Field
Value
0
Description
Reserved
QUEUE_ID
These read-only bits return 0s when read.
0–15
Queue identification number. This field selects which of the 16 RX buffer
queues is associated with mapper n.
1
PROMISCUOUS
Promiscuous access
0
1
Mapper n checks the incoming sourceID (access is restricted to one
sender). When determining which transactions to service, the mapper
checks the sourceID in addition to the mailbox and letter qualifications.
Mapper n ignores the incoming sourceID (access is available to any
sender). When determining which transactions to service, the mapper
checks only the mailbox and letter qualifications.
0
SEGMENT_MAPPING
Segment mapping
0
1
Single-segment messaging. Up to 64 mailboxes are available. All six
bits of the MAILBOX and MAILBOX_MASK fields of RXU_MAP_Ln are
valid.
Multi-segment messaging. Up to 4 mailboxes are available. Only the 2
LSBs of the MAILBOX and MAILBOX_MASK fields of RXU_MAP_Ln
are valid.
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5.51 Flow Control Table Entry Register n (FLOW_CNTLn)
There are sixteen of these registers (see Table 121). FLOW_CNTLn is shown in Figure 114 and described
Table 121. FLOW_CNTLn Registers
Register
Address Offset
0900h
FLOW_CNTL0
FLOW_CNTL1
FLOW_CNTL2
FLOW_CNTL3
FLOW_CNTL4
FLOW_CNTL5
FLOW_CNTL6
FLOW_CNTL7
FLOW_CNTL8
FLOW_CNTL9
FLOW_CNTL10
FLOW_CNTL11
FLOW_CNTL12
FLOW_CNTL13
FLOW_CNTL14
FLOW_CNTL15
0904h
0908h
090Ch
0910h
0914h
0918h
091Ch
0920h
0924h
0928h
092Ch
0930h
0934h
0938h
093Ch
Figure 114. Flow Control Table Entry Register n (FLOW_CNTLn)
31
15
18 17
16
0
Reserved
R-0
TT
R/W-01
FLOW_CNTL_ID
R/W-0000h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 122. Flow Control Table Entry Register n (FLOW_CNTLn) Field Descriptions
Bit
Field
Value
Description
31–18
17–16
Reserved
TT
0
These read-only bits return 0s when read.
Transfer type for flow n
8-bit destination IDs
16-bit destination IDs
Reserved
00b
01b
1xb
15–0
FLOW_CNTL_ID
0000h–FFFFh
Destination ID for flow n. When 8-bit destination IDs are used (TT = 00b),
the 8 MSBs of this field are don't care bits.
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5.52 Device Identity CAR (DEV_ID)
effect to this register. The values are hard coded and will not change from their reset state.
Figure 115. Device Identity CAR (DEV_ID) - Address Offset 1000h
31
16 15
0
DEVICEIDENTITY
R-0000h
DEVICE_VENDORIDENTITY
R-0030h
LEGEND: R = Read only; -n = Value after reset
Table 123. Device Identity CAR (DEV_ID) Field Descriptions
Bit
Field
Value
0000h
0030h
Description
31–16
15–0
DEVICEIDENTITY
DEVICE_VENDORIDENTITY
Identifies the type of device. Vendor specific.
Device Vendor ID assigned by RapidIO Trade Association.
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5.53 Device Information CAR (DEV_INFO)
The device information CAR (DEV_INFO) is shown in Figure 116 and described in Table 124. Writes have
no effect to this register. The values are hard coded and will not change from their reset state.
Figure 116. Device Information CAR (DEV_INFO) - Address Offset 1004h
31
0
DEVICEREV
R-00000000h
LEGEND: R = Read only; -n = Value after reset
Table 124. Device Information CAR (DEV_INFO) Field Descriptions
Bit
Field
Value
Description
31–0
DEVICEREV
00000000h
Vendor supply device revision
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5.54 Assembly Identity CAR (ASBLY_ID)
no effect to this register. The values are hard coded and will not change from their reset state.
Figure 117. Assembly Identity CAR (ASBLY_ID) - Address Offset 1008h
31
16 15
0
ASSY_IDENTITY
R-0000h
ASSY_VENDORIDENTITY
R-0030h
LEGEND: R = Read only; -n = Value after reset
Table 125. Assembly Identity CAR (ASBLY_ID) Field Descriptions
Bit
Field
Value
0000h
0030h
Description
31–16
15–0
ASSY_IDENTITY
ASSY_VENDORIDENTITY
Assembly identifier. Vendor specific.
Assembly vendor identifier assigned by RapidIO Trade Association.
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5.55 Assembly Information CAR (ASBLY_INFO)
register is used by SERDES vendor to designate endpoints among the various function blocks of
registers. Writes have no effect to this register. The values are hard coded and will not change from their
reset state.
Figure 118. Assembly Information CAR (ASBLY_INFO) - Address Offset 100Ch
31
16 15
0
ASSYREV
R-0000h
EXTENDEDFEATURESPTR
R-0100h
LEGEND: R = Read only; -n = Value after reset
Table 126. Assembly Information CAR (ASBLY_INFO) Field Descriptions
Bit
Field
Value
0000h
0100h
Description
31–16
15–0
ASSYREV
Assembly revision level.
EXTENDEDFEATURESPTR
Pointer to first entry in extended features list.
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5.56 Processing Element Features CAR (PE_FEAT)
Figure 119. Processing Element Features CAR (PE_FEAT) - Address Offset 1010h
31
BRIDGE
R-0
30
MEMORY
R-0
29
PROCESSOR
R-1
28
SWITCH
R-0
27
24
16
8
Reserved
R-0h
23
15
Reserved
R-00h
Reserved
R-00h
7
6
5
4
3
2
0
FLOW_
CONTROL_
SUPPORT
RETRANSMIT_
SUPPRESS
CRF_
SUPPORT
LARGE_
SUPPORT
EXTENDED_
FEATURES
EXTENDED_ADDRESSING_SUPPORT
R-001
R-0
R-0
R-0
R-0
R-1
LEGEND: R = Read only; -n = Value after reset
Table 127. Processing Element Features CAR (PE_FEAT) Field Descriptions
Bit
Field
Value
Description
31
BRIDGE
PE can bridge to another interface. Examples are PCI,
proprietary processor buses, DRAM, etc.
30
MEMORY
PE has physically addressable local address space and can be
accessed as an endpoint through non-maintenance (i.e.,
non-coherent read and write) operations. This local address
space may be limited to local configuration Registers, or could be
on-chip SRAM, etc.
29
28
PROCESSOR
SWITCH
PE physically contains a local processor or similar device that
executes code. A device that bridges to an interface that
connects to a processor does not count (see bit 31).
PE can bridge to another external RapidIO interface. An internal
port to a local endpoint does not count as a switch port. For
example, a device with two RapidIO ports and a local endpoint is
a two port switch, not a three port switch, regardless of the
internal architecture.
27–8
7
Reserved
0
These read-only bits return 0s when read.
PE supports congestion flow control mechanism
PE does not support flow control
FLOW_CONTROL_SUPPORT
0
1
PE supports flow control
6
5
RETRANSMIT_SUPPRESS
CRF_SUPPORT
PE supports suppression of error recovery on packet CRC errors.
PE does not support suppression
0
1
PE supports suppression
This bit indicates PE support for the Critical Request Flow (CRF)
Function.
0
1
PE does not support CRF Function
PE supports CRF Function
4
3
LARGE_SUPPORT
Support of common transport large systems.
PE does not support common transport large systems
PE supports common transport large systems
0
1
EXTENDED_FEATURES
PE has extended features list; the extended features pointer is
valid.
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Table 127. Processing Element Features CAR (PE_FEAT) Field Descriptions (continued)
Bit
Field
Value
Description
2–0
EXTENDED_ADDRESSING_SUPPORT
Indicates the number address bits supported by the PE both as a
source and target of an operation. All PEs shall at minimum
support 34 bit addresses. Encodings other than below are
reserved.
001b
011b
101b
111b
Other
PE supports 34 bit addresses
PE supports 50 and 34 bit addresses
PE supports 66 and 34 bit addresses
PE supports 66, 50 and 34 bit addresses
Reserved
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5.57 Source Operations CAR (SRC_OP)
Figure 120. Source Operations CAR (SRC_OP) - Address Offset 1018h
31
24
16
Reserved
R-0
23
18 17
Reserved
R-0
IMPLMNT_DEFINED_2
R-00
15
READ
R-0
7
14
WRITE
R-0
13
12
11
DATA_MESS
R-0
10
9
8
STREAM_
WRITE
WRITE_WITH_
RESP
ATOMIC_TEST_
AND_SWAP
DOORBELL
Reserved
R-0
R-0
5
R-0
4
R-0
2
R-0
6
3
1
0
ATOMIC_
INCRMNT
ATOMIC_
DCRMNT
ATOMIC_
SET
ATOMIC_
CLEAR
PORT_
WRITE
Reserved
R-0
IMPLMNT_DEFINED_1
R-00
R-0
R-0
R-0
R-0
R-1
LEGEND: R = Read only; -n = Value after reset
Table 128. Source Operations CAR (SRC_OP) Field Descriptions
Bit
31–18
17–16
15
Field
Value
Description
Reserved
0
These read-only bits return 0s when read.
Defined by the device implementation
PE can support a read operation
IMPLMNT_DEFINED_2
READ
14
WRITE
PE can support a write operation
13
STREAM_WRITE
WRITE_WITH_RESP
DATA_MESS
DOORBELL
Reserved
PE can support a streaming-write operation
PE can support a write-with-response operation
PE can support a data message operation
PE can support a doorbell operation
This read-only bit returns 0 when read.
PE can support an atomic test-and-swap operation
12
11
10
9
0
8
ATOMIC_TEST_
AND_SWAP
7
6
ATOMIC_INCRMNT
ATOMIC_DCRMNT
ATOMIC_SET
PE can support an atomic increment operation
PE can support an atomic decrement operation
PE can support an atomic set operation
PE can support an atomic clear operation
This read-only bit returns 0 when read.
PE can support a port-write generation
Defined by the device implementation
5
4
ATOMIC_CLEAR
Reserved
3
0
2
PORT_WRITE
1–0
IMPLMNT_DEFINED_1
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5.58 Destination Operations CAR (DEST_OP)
Figure 121. Destination Operations CAR (DEST_OP) - Address Offset 101Ch
31
23
24
16
Reserved
R-0
18 17
Reserved
R-0
IMPLMNT_DEFINED_2
R-00
15
READ
R-0
7
14
WRITE
R-0
13
12
11
10
9
8
WRITE_WITH_
RESP
ATOMIC_TEST_
AND_SWAP
STREAM_WRITE
DATA_MESS DOORBELL
Reserved
R-0
R-0
5
R-0
4
R-0
3
R-0
2
R-0
6
1
0
ATOMIC_
INCRMNT
ATOMIC_
DCRMNT
ATOMIC_
SET
ATOMIC_
CLEAR
PORT_
WRITE
Reserved
R-0
IMPLMNT_DEFINED_1
R-00
R-0
R-0
R-0
R-0
R-1
LEGEND: R = Read only; -n = Value after reset
Table 129. Destination Operations CAR (DEST_OP) Field Descriptions
Bit
31–18
17–16
15
14
13
12
11
10
9
Field
Value
Description
Reserved
0
These read-only bits return 0s when read.
Defined by the device implementation
PE can support a read operation
IMPLMNT_DEFINED_2
READ
WRITE
PE can support a write operation
STREAM_WRITE
WRITE_WITH_RESP
DATA_MESS
PE can support a streaming-write operation
PE can support a write-with-response operation
PE can support a data message operation
PE can support a doorbell operation
This read-only bit returns 0 when read.
PE can support an atomic test-and-swap operation
PE can support an atomic increment operation
PE can support an atomic decrement operation
PE can support an atomic set operation
PE can support an atomic clear operation
This read-only bit returns 0 when read.
PE can support a port-write generation
Defined by the device implementation
DOORBELL
Reserved
0
0
8
ATOMIC_TEST_AND_SWAP
ATOMIC_INCRMNT
ATOMIC_DCRMNT
ATOMIC_SET
ATOMIC_CLEAR
Reserved
7
6
5
4
3
2
PORT_WRITE
IMPLMNT_DEFINED_1
1–0
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5.59 Processing Element Logical Layer Control CSR (PE_LL_CTL)
The processing element logical layer control CSR (PE_LL_CTL) is shown in Figure 122 and described in
Figure 122. Processing Element Logical Layer Control CSR (PE_LL_CTL) - Address Offset 104Ch
31
15
16
Reserved
R-0
3
2
0
EXTENDED_
ADDRESSING_
CONTROL
Reserved
R-0
R/W-001
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 130. Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions
Bit
31–3
2–0
Field
Value
Description
Reserved
0
These read-only bits return 0s when read.
Controls the number of address bits generated by the PE as a
EXTENDED_ADDRESSING_CONTROL
source and processed by the PE as the target of an operation. All
other encodings reserved.
001b
010b
100b
Other
PE supports 34 bit addresses
PE supports 50 bit addresses
PE supports 66 bit addresses
Reserved
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5.60 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR)
Figure 123. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) - Address Offset
1058h
31
30
0
Reserved
R-0
LCSBA
R-00000000h
LEGEND: R = Read only; -n = Value after reset
Table 131. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions
Bit
31
Field
Value
Description
Reserved
LCSBA
0
These read-only bits return 0s when read.
30–0
00000000h
to
Bits 30 to 15 are reserved for 34-bit addresses, reserved for 50-bit addresses, and
bits 66 to 51 of a 66-bit address.
FFFFFFFFh
Bits 14 to 0 are reserved for 34-bit addresses, bits 50 to 36 of a 50-bit address, and
bits 50 to 36 of a 66-bit address.
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5.61 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR)
Figure 124. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) - Address Offset
105Ch
31
0
LCSBA
R-00000000h
LEGEND: R = Read only; -n = Value after reset
Table 132. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions
Bit
Field
Value
Description
31–0
LCSBA
00000000h
to
Bit 31 is reserved for 34-bit addresses, bit 35 of a 50-bit address, and bit 35 of a
66-bit address.
FFFFFFFFh
Bits 30 to 0 are bits 34 to 3 of a 34-bit address, bits 35 to 3 of a 50-bit address, and
bits 35 to 3 of a 66-bit address.
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5.62 Base Device ID CSR (BASE_ID)
Figure 125. Base Device ID CSR (BASE_ID) - Address Offset 1060h
31
15
24 23
16
0
Reserved
R-00h
BASE_DEVICEID
R/W-FFh
LARGE_BASE_DEVICEID
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 133. Base Device ID CSR (BASE_ID) Field Descriptions
Bit
Field
Value
00h
Description
31–24
23–16
Reserved
These read-only bits return 0s when read.
BASE_DEVICEID
00h–FFh
This is the base ID of the device in small common transport system
(endpoints only).
15–0
LARGE_BASE_DEVICEID
0000h–FFFFh
This is the base ID of the device in a large common transport system
(Only valid for endpoints, and if bit 4 of the PE_FEAT Register is set).
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5.63 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK)
See Section 2.4.2 of the RapidIO Common Transport Specification for a description of this register. It
provides a lock function that is write-once/reset-able. The host base device ID lock CSR
Figure 126. Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) - Address Offset 1068h
31
16 15
0
Reserved
R-0000h
HOST_BASE_DEVICEID
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 134. Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) Field Descriptions
Bit
Field
Value
0000h
Description
31–16
15–0
Reserved
These read-only bits return 0s when read.
This is the base ID for the Host PE that is initializing this PE.
HOST_BASE_DEVICEID
0000h–FFFFh
194
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5.64 Component Tag CSR (COMP_TAG)
Figure 127. Component Tag CSR (COMP_TAG) - Address Offset 106Ch
31
0
COMPONENT_TAG
R/W-00000000h
LEGEND: R/W = Read/Write; -n = Value after reset
Table 135. Component Tag CSR (COMP_TAG) Field Descriptions
Bit
Field
Value
Description
31–0
COMPONENT_TAG
00000000h
to
Software defined component tag for the PE. Useful for devices without
device IDs.
FFFFFFFFh
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5.65 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD)
Figure 128. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) - Address
Offset 1100h
31
16 15
0
EF_PTR
R-1000h
EF_ID
R-0001h
LEGEND: R = Read only; -n = Value after reset
Table 136. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) Field
Descriptions
Bit
Field
Value
Description
31–16
15–0
EF_PTR
EF_ID
Hard wired pointer to the next block in the data structure.
Hard wired extended features ID.
0001h
0002h
0003h
General endpoint device
General endpoint device with software assisted error recovery option
Switch
196
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5.66 Port Link Time-Out Control CSR (SP_LT_CTL)
Figure 129. Port Link Time-Out Control CSR (SP_LT_CTL) - Address Offset 1120h
31
TIMEOUT_VALUE
R/W-FFFFFFh
8
7
0
TIMEOUT_VALUE
R/W-FFFFFFh
Reserved
R-00h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 137. Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions
Bit
Field
Value
Description
31–8
TIMEOUT_VALUE
Timeout value for all ports on the device. This timeout is for link events
such as sending a packet to receiving the corresponding ACK. Max
value represents 3-6 seconds. Timeout duration = 205 ns * Timeout
Value; where Timeout value is the decimal representation of this register
value.
FFFFFFh
0FFFFFh
00FFFFh
000FFFh
0000FFh
00000Fh
000001h
000000h
00h
3.4 s
215 ms
13.4 ms
839.5 µs
52.3 µs
3.1 µs
205 ns for simulation only
Timer disabled
7–0
Reserved
These read-only bits return 0s when read.
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5.67 Port Response Time-Out Control CSR (SP_RT_CTL)
The port response time-out control CSR (SP_RT_CTL) is shown in Figure 130 and described in Table 138
Figure 130. Port Response Time-Out Control CSR (SP_RT_CTL) - Address Offset 1124h
31
TIMEOUT_VALUE
RW-FFFFFFh
8
7
0
TIMEOUT_VALUE
RW-FFFFFFh
Reserved
R-00h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 138. Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions
Bit
Field
Value
Description
31–8
TIMEOUT_VALUE
000000h
to
FFFFFFh
Timeout value for all ports on the device. This timeout is for sending a packet to
receiving the corresponding response packet. Max value represents 3 to 6
seconds. The timeout duration can be expressed as:
Timeout = 15 x ((Prescale Value + 1) x DMA Clock Period x Timeout Value)
where Prescale value is set in PER_SET_CNTL (offset 0020h) and the Timeout
value is the decimal representation of this register value. For example, given a
400-MHz DMA, a Prescale Value of 4, and a Timeout Value of FFFFFFh, the
Timeout duration would be:
Timeout = 15 x ((4 + 1) x 2.5 ns x 16777216) = 3.15 s
These read-only bits return 0s when read.
7–0
Reserved
00h
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5.68 Port General Control CSR (SP_GEN_CTL)
Figure 131. Port General Control CSR (SP_GEN_CTL) - Address Offset 113Ch
31
30
29
28
0
MASTER_
ENABLE
HOST
R/W-0
DISCOVERED
R/W-0
Reserved
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 139. Port General Control CSR (SP_GEN_CTL) Field Descriptions
Bit
Field
Value
Description
31
HOST
A host device is a device that is responsible for system exploration, initialization,
and maintenance. Agent or slave devices are typically initialized by Host
devices.
0
1
Agent or Slave device
Host device
30
MASTER_ENABLE
The Master Enable bit controls whether or not a device is allowed to issue
requests into the system. If the Master Enable is not set, the device may only
respond to requests.
0
1
Processing element cannot issue requests
Processing element can issue requests
29
DISCOVERED
Reserved
This device has been located by the processing element responsible for system
configuration.
0
1
0
The device has not been previously discovered
The device has been discovered by another processing element
These read-only bits return 0s when read.
28–0
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5.69 Port Link Maintenance Request CSR n (SPn_LM_REQ)
Each of the four ports is supported by a register of this type (see Table 140). SPn_LM_REQ is shown in
Table 140. SPn_LM_REQ Registers and the Associated Ports
Register
Address Offset
1140h
Associated Port
Port 0
SP0_LM_REQ
SP1_LM_REQ
SP2_LM_REQ
SP3_LM_REQ
1160h
Port 1
1180h
Port 2
11A0h
Port 3
Figure 132. Port Link Maintenance Request CSR n (SPn_LM_REQ)
31
3
2
0
Reserved
R-0
COMMAND
R/W-000
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 141. Port Link Maintenance Request CSR n (SPn_LM_REQ) Field Descriptions
Bit
31–3
2–0
Field
Value
0
Description
Reserved
COMMAND
These read-only bits return 0s when read.
000b–111b
A write to this register generates a link-request control symbol on the corresponding
port interface. Command to be sent in the link-request control symbol. When read,
this field returns the last written value.
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5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP)
Each of the four ports is supported by a register of this type (see Table 142). The port link maintenance
Table 142. SPn_LM_RESP Registers and the Associated Ports
Register
Address Offset
1144h
Associated Port
Port 0
SP0_LM_RESP
SP1_LM_RESP
SP2_LM_RESP
SP3_LM_RESP
1164h
Port 1
1184h
Port 2
11A4h
Port 3
Figure 133. Port Link Maintenance Response CSR n (SPn_LM_RESP)
31
30
16
0
RESPONSE_
VALID
Reserved
R-0
R-0
15
10
9
5
4
Reserved
R-0
ACKID_STATUS
R-0
LINK_STATUS
R-0
LEGEND: R = Read only; -n = Value after reset
Table 143. Port Link Maintenance Response CSR n (SPn_LM_RESP) Field Descriptions
Bit
Field
Value
Description
31
RESPONSE_VALID
If the link-request causes a link-response, this bit indicates that the
link-response has been received and the status fields are valid. If the
link-request does not cause a link-response, this bit indicates that the
link-request has been transmitted. This bit automatically clears on read.
30–10
9–5
Reserved
0
These read-only bits return 0s when read.
ACKID_STATUS
LINK_STATUS
00000b–11111b
00000b–11111b
AckID status field from the link-response control symbol
Link status field from the link-response control symbol
4–0
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5.71 Port Local AckID Status CSR n (SPn_ACKID_STAT)
Each of the four ports is supported by a register of this type (see Table 144). The port local ackID status
Table 144. SPn_ACKID_STAT Registers and the Associated Ports
Register
Address Offset
1148h
Associated Port
Port 0
SP0_ACKID_STAT
SP1_ACKID_STAT
SP2_ACKID_STAT
SP3_ACKID_STAT
1168h
Port 1
1188h
Port 2
11A8h
Port 3
Figure 134. Port Local AckID Status CSR n (SPn_ACKID_STAT)
31
15
29 28
Reserved
24 23
16
0
INBOUND_ACKID
R/W-0
Reserved
R-0
R-0
13 12
Reserved
8
7
3
4
OUTSTANDING_ACKID
R/W-0
Reserved
R-0
OUTBOUND_ACKID
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 145. Port Local AckID Status CSR n (SPn_ACKID_STAT) Field Descriptions
Bit
Field
Value
Description
31–29
28–24
23–13
12–8
Reserved
0
These read-only bits return 0s when read.
Input port next expected ackID value
These read-only bits return 0s when read.
INBOUND_ACKID
Reserved
00000b–11111b
0
OUTSTANDING_ACKID
00000b–11111b
Output port unacknowledged ackID status. Next expected acknowledge
control symbol ackID field that indicates the ackID value expected in the
next received acknowledge control symbol.
7–5
4–0
Reserved
0
These read-only bits return 0s when read.
OUTBOUND_ACKID
00000b–11111b
Output port next transmitted ackID value. Software writing this value can
force retransmission of outstanding unacknowledged packets in order to
manually implement error recovery.
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5.72 Port Error and Status CSR n (SPn_ERR_STAT)
Each of the four ports is supported by a register of this type (see Table 146). The port error and status
Table 146. SPn_ERR_STAT Registers and the Associated Ports
Register
Address Offset
1158h
Associated Port
Port 0
SP0_ERR_STAT
SP1_ERR_STAT
SP2_ERR_STAT
SP3_ERR_STAT
1178h
Port 1
1198h
Port 2
11B8h
Port 3
Figure 135. Port Error and Status CSR n (SPn_ERR_STAT)
31
23
15
7
27
26
25
24
OUTPUT_
PKT_
DROP
OUTPUT_
FLD_
OUTPUT_
DEGRD_
ENC
Reserved
R-0
ENC
R/W-0
18
R/W-0
17
R/W-0
16
21
20
19
OUTPUT_
RETRY_
ENC
OUTPUT_
RETRY_
STP
OUTPUT_
ERROR_
ENC
OUTPUT_
ERROR_
STP
OUTPUT_
RETRIED
Reserved
R-0
R/W-0
R-0
R-0
10
R/W-0
9
R-0
8
11
INPUT_
RETRY_
STP
INPUT_
ERROR_
ENC
INPUT_
ERROR_
STP
Reserved
R-0
R-0
2
R/W-0
1
R-0
0
5
4
3
PORT_
WRITE_
PND
PORT_
ERROR
PORT_
OK
PORT_
UNINITIALIZED
Reserved
R-0
Reserved
R-0
R/W-0
R/W-0
R-0
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 147. Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions
Bit
31–27
26
Field
Value
Description
Reserved
0
These read-only bits return 0s when read.
Output packet drop (switch devices only)
The output port has not discarded a packet.
The output port has discarded a packet.
OUTPUT_PKT_DROP
0
1
25
24
OUTPUT_FLD_ENC
Output failed condition encountered. Once set, the OUTPUT_FLD_ENC bit
remains set until software writes a 1 to it.
0
1
The output port has not encountered a failed condition.
The output port has encountered a failed condition. The failed port error
threshold has been reached in the Port n Error Rate Threshold Register.
OUTPUT_DEGRD_ENC
Output degraded condition encountered. Once set, the
OUTPUT_DEGRD_ENC bit remains set until software writes a 1 to it.
0
1
The output port has not encountered a degraded condition.
The output port has encountered a degraded condition. The degraded port
error threshold has been reached in the Port n Error Rate Threshold
Register.
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Table 147. Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions (continued)
Bit
23–21
20
Field
Value
Description
Reserved
0
These read-only bits return 0s when read.
OUTPUT_RETRY_ENC
Output retry condition encountered. Once set, the OUTPUT_RETRY_ENC bit
remains set until software writes a 1 to it.
0
1
The output port has not encountered a retry condition.
The output port has encountered a retry condition. This bit is set when bit 18
is set.
19
18
17
16
OUTPUT_RETRIED
Output retried. OUTPUT_RETRIED is a read-only bit.
0
1
The output port has not received a packet-retry control symbol.
The output port has received a packet-retry control symbol and cannot make
forward progress. This bit is set when bit 18 is set and is cleared when a
packet-accepted or packet-not-accepted control symbol is received.
OUTPUT_RETRY_STP
OUTPUT_ERROR_ENC
OUTPUT_ERROR_STP
Output retry-stopped state. OUTPUT_RETRY_STP is a read-only bit.
0
1
The output port has not received a packet-retry control symbol and/or is not
in the "output retry-stopped" state.
The output port has received a packet-retry control symbol and is in the
"output retry-stopped" state.
Output transmission error encountered. Once set, the
OUTPUT_ERROR_ENC bit remains set until software writes a 1 to it.
0
1
The output port has not encountered a transmission error.
The output port has encountered (and possibly recovered from) a
transmission error. This bit is set when bit 16 is set.
Output error-stopped. OUTPUT_ERROR_STP is a read-only bit.
The output port is not in the "output error-stopped" state.
The output port is in the "output error-stopped" state.
These read-only bits return 0s when read.
0
1
0
15–11
10
Reserved
INPUT_RETRY_STP
Input retry-stopped state. INPUT_RETRY_STP is a read-only bit.
The input port is not in the "input retry-stopped" state.
The input port is in the "input retry-stopped" state.
0
1
9
8
INPUT_ERROR_ENC
INPUT_ERROR_STP
Input port transmission error encountered. Once set, the
INPUT_ERROR_ENC bit remains set until software writes a 1 to it.
0
1
The input port has not encountered a transmission error.
The input port has encountered (and possibly recovered from) a transmission
error. This bit is set when bit 8 is set.
Input error-stopped state. INPUT_ERROR_STP is a read-only bit.
The input port is not in the "input error-stopped" state.
The input port is in the "input error-stopped" state.
These read-only bits return 0s when read.
0
1
0
7–5
4
Reserved
PORT_WRITE_PND
Port-write pending. This bit is only valid if the device is capable of issuing a
maintenance port-write transaction. Once set, the PORT_WRITE_PND bit
remains set until software writes a 1 to it.
0
1
0
The port has not encountered a condition which required it to initiate a
Maintenance Port-write operation.
The port has encountered a condition which required it to initiate a
Maintenance Port-write operation.
3
2
Reserved
This read-only bit returns 0 when read.
PORT_ERROR
Port unrecoverable error. Once set, the PORT_ERROR bit remains set until
software writes a 1 to it.
0
1
The input or output port has not encountered an error from which hardware
was unable to recover.
The input or output port has encountered an error from which hardware was
unable to recover.
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Table 147. Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions (continued)
Bit
Field
Value
Description
1
PORT_OK
Port OK. This bit is a read-only bit.
Port not-OK condition
0
1
Port OK condition. The input and output ports are initialized, and the port is
exchanging error-free control symbols with the attached device.
0
PORT_UNINITIALIZED
Port uninitialized. PORT_UNINITIALIZED is a read-only bit. This bit and the
PORT_OK bit are mutually exclusive.
0
1
Input and output ports are initialized.
Input and output ports are not initialized.
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5.73 Port Control CSR n (SPn_CTL)
Each of the four ports is supported by a register of this type (see Table 148). The port control CSR n
are 2 registers that need to be programmed. The SP_IP_MODE (offset 0x12004) bits 31-30 are set to be
1x/4p or 4 ports (1x mode each). The PER_SET_CNTL (offset 0x0020) bit 8 is set up for port (1x/4p) or
priority based (1x mode each).
Table 148. SPn_CTL Registers and the Associated Ports
Register
SP0_CTL
SP1_CTL
SP2_CTL
SP3_CTL
Address Offset
115Ch
Associated Port
Port 0
117Ch
Port 1
119Ch
Port 2
11BCh
Port 3
Figure 136. Port Control CSR n (SPn_CTL)
31
30 29
27 26
24
16
PORT_WIDTH
R-01
INITIALIZED_PORT_WIDTH
R-000
PORT_WIDTH_OVERRIDE
R/W-000
23
22
21
20
19
18
OUTPUT_
PORT_
ENABLE
INPUT_
PORT_
ENABLE
ERROR_
CHECK_
DISABLE
PORT_
DISABLE
MULTICAST_
PARTICIPANT
Reserved
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
15
7
8
Reserved
R-0
4
3
2
1
0
STOP_PORT_
FLD_ENC_
ENABLE
DROP_
PACKET_
ENABLE
PORT_
LOCKOUT
Reserved
R-0
PORT_TYPE
R-1
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 149. Port Control CSR n (SPn_CTL) Field Descriptions
Bit
Field
Value
Description
31–30
PORT_WIDTH
Port width. This read-only field indicates the hardware width of
the port.
00b
01b
1xb
Single-lane port (valid for all ports)
Four-lane port (valid for port 0 only)
Reserved
29–27
INITIALIZED_PORT_WIDTH
Initialized port width. This read-only field indicates the width of
the ports after initialization.
000b
001b
Single-lane port, lane 0
Single-lane port, lane 2 (See RapidIO Serial Spec 1.2, Chapter
4.4.10)
010b
Four-lane port
Reserved
011b–111b
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Table 149. Port Control CSR n (SPn_CTL) Field Descriptions (continued)
Bit
Field
Value
Description
26–24
PORT_WIDTH_OVERRIDE
Port width override. This read-only field is available as a software
means to override the hardware width.
000b
001b
No override
Reserved
010b
Force single lane, lane 0
Force single lane, lane 2
Reserved
011b
100b–111b
23
22
PORT_DISABLE
Port disable
0
1
Port receivers/drivers are enabled.
Port receivers/drivers are disabled and are unable to
receive/transmit any packets or control symbols.
OUTPUT_PORT_ENABLE
Output port enable
0
The port is stopped and not enabled to issue any packets except
to route or respond to I/O logical maintenance packets,
depending upon the functionality of the processing element.
Control symbols are not affected and are sent normally.
1
0
The port is enabled to issue any packets.
Input port receive enable
21
INPUT_PORT_ENABLE
The port is stopped and only enabled to route or respond I/O
logical maintenance packets, depending upon the functionality of
the processing element. Other packets generate
packet-not-accepted control symbols to force an error condition
to be signaled by the sending device. Control symbols are not
affected and are received and handled normally.
1
Port is enabled to respond to any packet.
Error check disable
20
19
ERROR_CHECK_DISABLE
MULTICAST_PARTICIPANT
0
1
RapidIO transmission error checking and recovery are enabled.
RapiIO transmission error checking and recovery are disabled. If
an error condition occurs, device behavior is undefined.
0
0
Multicast-event participant enable. This read-only bit is 0 to
indicate that multicast-event control symbols cannot be accepted
by this port.
18–4
3
Reserved
These read-only bits return 0s when read.
Stop-on-fail enable
STOP_PORT_FLD_ENC_ENABLE
0
1
Even when the Output Failed-encountered bit is set, the port
continues to attempt to transmit packets to the connected device.
When the Output Failed-encountered bit is set, the port sets the
Port Error bit in the Port n Error and Status CSR and stops
attempting to send packets to the connected device. Packets are
discarded if the Drop Packet Enable bit is set.
2
DROP_PACKET_ENABLE
Drop packet enable
0
1
The output port continues to try to transmit packets that have
been rejected due to transmission errors.
The output port drops packets that are acknowledged with a
packet-not-accepted control symbol when the error failed
threshold is exceeded. If the port "heals", and the current error
rate falls below the failed threshold, the output no longer drops
packets. (switch devices only)
1
PORT_LOCKOUT
Port lockout
0
1
The port is enabled to issue any packets.
The port is stopped and is not enabled to issue or receive any
packets. The input port can still follow the training procedure and
can still send and respond to link-requests. All received packets
return packet-not-accepted control symbols to force an error
condition to be signaled by the sending device.
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Table 149. Port Control CSR n (SPn_CTL) Field Descriptions (continued)
Bit
Field
Value
Description
0
PORT_TYPE
1
Port type. This read-only bit indicates that the port is a serial port
rather than a parallel port.
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5.74 Error Reporting Block Header Register (ERR_RPT_BH)
Figure 137. Error Reporting Block Header Register (ERR_RPT_BH) - Address Offset 2000h
31
16 15
0
EF_PTR
R-0000h
EF_ID
R-0007h
LEGEND: R = Read only; -n = Value after reset
Table 150. Error Reporting Block Header Register (ERR_RPT_BH) Field Descriptions
Bit
Field
Value
0000h
0007h
Description
31–16
15–0
EF_PTR
EF_ID
Hard-wired pointer to the next block in the data structure. NONE EXISTS
Hard-wired Extended Features ID
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5.75 Logical/Transport Layer Error Detect CSR (ERR_DET)
This register allows for the detection of logical/transport layer errors. The detectable errors are captured in
the fields shown in Figure 138 and described in Table 151. For additional programming information, see
Figure 138. Logical/Transport Layer Error Detect CSR (ERR_DET) - Address Offset 2008h
31
30
29
Reserved
R-0
28
27
26
Reserved
R-0
25
24
IO_ERR_
RSPNS
MSG_ERR_
RSPNS
ERR_MSG_
FORMAT
ILL_TRANS_
DECODE
MSG_REQ_
TIMEOUT
PKT_RSPNS_
TIMEOUT
R/W-0
23
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
22
21
UNSOLICITED_
RSPNS
UNSUPPORTED_
TRANS
Reserved
R-0
R/W-0
R/W-0
8
Reserved
R-0
7
6
5
0
RX_CPPI_
SECURITY
RX_IO_DMA_
ACCESS
Reserved
R-0
R/W-0
R/W-0
LEGEND: R = Read; W = Write; -n = Value after reset
Table 151. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions
Bit
Field
Value
Description
31
IO_ERR_RSPNS
I/O error response (endpoint device only)
An LSU did not receive an ERROR response to an I/O logical layer request.
0
1
An LSU received an ERROR response to an I/O logical layer request. To clear
this bit, write 0 to it.
30
MSG_ERR_RSPNS
Message error response (endpoint device only)
0
1
0
The TXU did not receive an ERROR response to a message logical layer
request.
The TXU received an ERROR response to a message logical layer request. To
clear this bit, write 0 to it.
29
28
Reserved
This read-only bit returns 0 when read.
ERR_MSG_FORMAT
Error in message format (endpoint device only)
0
1
The RXU did not receive a message data payload with an invalid size or
segment.
The RXU received a message data payload with an invalid size or segment. To
clear this bit, write 0 to it.
27
ILL_TRANS_DECODE
Illegal transaction decode (switch or endpoint device)
For an LSU or the TXU:
0
1
The LSU/TXU did not receive illegal fields in the response packet for an
IO/message transaction.
The LSU/TXU received illegal fields in the response packet for an IO/message
transaction. To clear this bit, write 0 to it.
For the MAU or the RXU:
0
1
0
The MAU/RXU did not receive illegal fields in the request packet for an
IO/message transaction.
The MAU/RXU received illegal fields in the request packet for an IO/message
transaction. To clear this bit, write 0 to it.
26
Reserved
This read-only bit returns 0 when read.
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Table 151. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued)
Bit
Field
Value
Description
25
MSG_REQ_TIMEOUT
Message request timeout (endpoint device only)
A timeout has not been detected by RXU.
0
1
A timeout has been detected by the RXU. A required message request has not
been received by the RXU within the specified time-out interval. To clear this
bit, write 0 to it.
24
PKT_RSPNS_TIMEOUT
Packet response timeout (endpoint device only)
0
1
A timeout has not been detected by an LSU or the TXU.
A timeout has been detected by an LSU or the TXU. A required response has
not been received by the LSU/TXU within the specified timeout interval. To
clear this bit, write 0 to it.
23
22
UNSOLICITED_RSPNS
UNSUPPORTED_TRANS
Unsolicited response (switch or endpoint device)
0
1
An unsolicited response packet has not been received by an LSU or the TXU.
An unsolicited response packet has been received by an LSU or the TXU. To
clear this bit, write 0 to it.
Unsupported transaction (switch or endpoint device)
The MAU has not received an unsupported transaction.
0
1
The MAU has received an unsupported transaction. That is, the MAU received
a transaction that is not supported in the destination operations CAR. To clear
this bit, write 0 to it.
21–8
7
Reserved
0
These read-only bits return 0 when read.
RX CPPI security error
RX_CPPI_SECURITY
0
1
The RXU has not detected an access block.
The RXU has detected an access block. That is, access to one of the RX
queues was blocked. To clear this bit, write 0 to it.
6
RX_IO_DMA_ACCESS
Reserved
RX I/O DMA access error
0
1
0
A DMA access to the MAU has not been blocked.
A DMA access to the MAU was blocked. To clear this bit, write 0 to it.
These read-only bits return 0 when read.
5–0
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5.76 Logical/Transport Layer Error Enable CSR (ERR_EN)
Figure 139. Logical/Transport Layer Error Enable CSR (ERR_EN) - Address Offset 200Ch
31
30
29
28
27
26
25
24
IO_ERR_
RESP_
ENABLE
MSG_ERR_
RESP_
ENABLE
Reserved
(write 0)
ERR_MSG_
FORMAT_
ENABLE
ILL_TRANS_
DECODE_
ENABLE
Reserved
(write 0)
MSG_REQ_
TIMEOUT_
ENABLE
PKT_RESP_
TIMEOUT_
ENABLE
R/W-0
23
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
22
21
UNSOLICITED_
RESP_ENABLE
UNSUPPORTED_
TRANS_ENABLE
Reserved
R/W-0
R/W-0
R-0
8
0
Reserved
R-0
7
6
5
RX_CPPI_
SECURITY_
ENABLE
RX_IO_
SECURITY_
ENABLE
Reserved
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 152. Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions
Bit
Field
Value
Description
31
IO_ERR_RESP_ENABLE
IO error response reporting enable
Disable reporting of an IO error response.
0
1
Enable reporting of an IO error response (endpoint device only).
Save and lock original request transaction capture information in all
Logical/Transport Layer Capture CSRs.
30
MSG_ERR_RESP_ENABLE
Message error response reporting enable
0
1
Disable reporting of a message error response.
Enable reporting of a message error response (endpoint device
only). Save and lock transaction capture information in all
Logical/Transport Layer Capture CSRs.
29
28
Reserved
0
Always write 0 to this reserved bit.
ERR_MSG_FORMAT_ENABLE
Message format error reporting enable
Disable reporting of a message format error.
0
1
Enable reporting of a message format error (endpoint device only).
Save and lock transaction capture information in Logical/Transport
Layer Device ID and Control Capture CSRs.
27
ILL_TRANS_DECODE_ENABLE
Illegal transaction decode error reporting enable
0
1
Disable reporting of an illegal transaction decode error.
Enable reporting of an illegal transaction decode error (switch or
endpoint device). Save and lock transaction capture information in
Logical/Transport Layer Device ID and Control Capture CSRs.
26
25
Reserved
0
Always write 0 to this reserved bit.
MSG_REQ_TIMEOUT_ENABLE
Message request time-out error reporting enable
Disable reporting of a message request time-out error.
0
1
Enable reporting of a message request time-out error (endpoint
device only). Save and lock transaction capture information in
Logical/Transport Layer Device ID and Control Capture CSRs for the
last message-segment request packet received.
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Table 152. Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions (continued)
Bit
Field
Value
Description
24
PKT_RESP_TIMEOUT_ENABLE
Packet response time-out error reporting enable
Disable reporting of a packet response time-out error.
0
1
Enable reporting of a packet response time-out error (endpoint
device only). Save and lock original request address in
Logical/Transport Layer Address Capture CSRs. Save and lock
original request Destination ID in Logical/Transport Layer Device ID
Capture CSR.
23
22
UNSOLICITED_RESP_ENABLE
Unsolicited response error reporting enable
0
1
Disable reporting of an unsolicited response error.
Enable reporting of an unsolicited response error (switch or endpoint
device). Save and lock transaction capture information in
Logical/Transport Layer Device ID and Control Capture CSRs.
UNSUPPORTED_TRANS_ENABLE
Unsupported transaction error reporting enable
0
1
Disable reporting of an unsupported transaction error.
Enable reporting of an unsupported transaction error (switch or
endpoint device). Save and lock transaction capture information in
Logical/Transport Layer Device ID and Control Capture CSRs.
21–8
7
Reserved
0
These read-only bits return 0s when read.
RX CPPI security error reporting enable
RX_CPPI_SECURITY_ENABLE
0
1
Disable reporting of an attempt at unauthorized access to a RX
queue.
Enable reporting of attempt at unauthorized access to a RX queue.
Save and Lock capture information in appropriate Logical/Transport
Layer Capture CSRs.
6
RX_IO_SECURITY_ENABLE
RX I/O secuirty error reporting enable
0
1
Disable reporting of attempt at unauthorized access to a memory
location.
Enable reporting of attempt at unauthorized access to a memory
location. Save and Lock capture information in appropriate
Logical/Transport Layer Capture CSRs.
5–0
Reserved
0
These read-only bits return 0s when read.
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5.77 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT)
Figure 140. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) - Address Offset
2010h
31
0
ADDRESS_63_32
R-00000000h
LEGEND: R = Read only; -n = Value after reset
Table 153. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions
Bit
Field
Value
Description
31–0
ADDRESS_63_32
00000000h
to
Most significant 32 bits of the address associated with the error (only
valid for devices supporting 66-bit and 50-bit addresses)
FFFFFFFFh
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5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT)
Figure 141. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) - Address Offset 2014h
31
15
16
ADDRESS_31_3
R-0000h
3
2
1
0
ADDRESS_31_3
R-0000h
Reserved
R-0
XAMSBS
R-00
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 154. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions
Bit
Field
Value
Description
31–3
ADDRESS_31_3
00000000h
to
Least significant 29 bits of the address associated with the error
1FFFFFFFh
2
Reserved
XAMSBS
0
This read-only bit returns 0 when read.
1–0
00b–11b
Extended address bits of the address associated with the error
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5.79 Logical/Transport Layer Device ID Capture CSR (ID_CAPT)
Figure 142. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) - Address Offset 2018h
31
15
24 23
16
0
MSB_DESTID
R-00h
DESTID
R-00h
8
7
MSB_SOURCEID
R-00h
SOURCEID
R-00h
LEGEND: R = Read only; -n = Value after reset
Table 155. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Field Descriptions
Bit
Field
Value
Description
31–24
MSB_DESTID
00h–FFh
Most significant byte of the destinationID associated with the error (large
transport systems only)
23–16
15–8
DESTID
00h–FFh
00h–FFh
The destinationID associated with the error
MSB_SOURCEID
Most significant byte of the source ID associated with the error (large transport
systems only)
7–0
SOURCEID
00h–FFh
The sourceID associated with the error
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5.80 Logical/Transport Layer Control Capture CSR (CTRL_CAPT)
Figure 143. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) - Address Offset 201Ch
31
15
28 27
24 23
16
FTYPE
R-0h
TTYPE
R-0h
MSGINFO
R-00h
0
IMP_SPECIFIC
R-0000h
LEGEND: R = Read only; -n = Value after reset
Table 156. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Field Descriptions
Bit
Field
Value
0h–Fh
Description
31–28
27–24
23–16
FTYPE
TTYPE
MSGINFO
Format type associated with the error
Transaction type associated with the error
0h–Fh
00h–FFh
Letter, mailbox, and message segment for the last message request received
for the mailbox that had an error (message errors only)
15–0
IMP_SPECIFIC
0000h–FFFFh
Implementation specific information associated with the error
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5.81 Port-Write Target Device ID CSR (PW_TGT_ID)
Figure 144. Port-Write Target Device ID CSR (PW_TGT_ID) - Address Offset 2028h
31
15
24 23
16
0
DEVICEID_MSB
R/W-00h
DEVICEID
R/W-00h
Reserved
R-0000h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 157. Port-Write Target Device ID CSR (PW_TGT_ID) Field Descriptions
Bit
Field
Value
00h–FFh
00h–FFh
0000h
Description
31–24
23–16
15–0
DEVICEID_MSB
DEVICEID
Reserved
Most significant byte of the port-write target device ID (large transport systems only)
Port-write target deviceID
These read-only bits return 0s when read.
218
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5.82 Port Error Detect CSR n (SPn_ERR_DET)
Each of the four ports is supported by a register of this type (see Table 158). The port error detect CSR n
Table 158. SPn_ERR_DET Registers and the Associated Ports
Register
Address Offset
2040h
Associated Port
Port 0
SP0_ERR_DET
SP1_ERR_DET
SP2_ERR_DET
SP3_ERR_DET
2080h
Port 1
20C0h
Port 2
2100h
Port 3
Figure 145. Port Error Detect CSR n (SPn_ERR_DET)
31
30
24
ERR_IMP_
SPECIFIC
Reserved
R-0
R/W-0
23
22
21
20
19
18
17
16
Reserved
R-0
CNTL_SYM_
UNEXPECTED_
ACKID
PKT_
UNEXPECTED_
ACKID
RCVD_PKT_
WITH_BAD
_CRC
CORRUPT_
CNTL_SYM
RCVD_PKT_
NOT_ACCPT
RCVD_PKT_
OVER_276B
Reserved
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
NON_
OUTSTANDING_
ACKID
PROTOCOL_
ERROR
DELINEATION_
ERROR
UNSOLICITED_
ACK_CNTL_SYM
LINK_
TIMEOUT
Reserved
R-0
Reserved
R-0
R/W-0
R/W-0
R-00h
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 159. Port Error Detect CSR n (SPn_ERR_DET) Field Descriptions
Bit
Field
Value
Description
31
ERR_IMP_SPECIFIC
Implementation-specific error. This bit covers errors that are a result of
an illegal field in a maintenance packet, an illegal destination ID, and
an unsupported transaction.
0
1
0
An implementation specific error has not been detected.
An implementation specific error has been detected.
These read-only bits return 0s when read.
30–23
22
Reserved
CORRUPT_CNTL_SYM
Bad CRC in control symbol
0
1
The port did not receive a control symbol with a bad CRC value.
The port received a control symbol with a bad CRC value.
Unexpected ackID in control symbol
21
CNTL_SYM_UNEXPECTED_ACKID
0
1
The port did not receive an acknowledge control symbol with an
unexpected ackID (packet-accepted or packet-retry).
The port received an acknowledge control symbol with an unexpected
ackID (packet-accepted or packet-retry). The capture registers do not
have valid information during this error detection.
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Table 159. Port Error Detect CSR n (SPn_ERR_DET) Field Descriptions (continued)
Bit
Field
Value
Description
20
RCVD_PKT_NOT_ACCPT
Packet-not-accepted control symbol
0
1
The port did not receive a packet-not-accepted acknowledge control
symbol.
The port received a packet-not-accepted acknowledge control symbol.
Unexpected ackID in packet
19
PKT_UNEXPECTED_ACKID
0
1
The port did not receive a packet with unexpected/out-of-sequence
ackID.
The port received a packet with unexpected/out-of-sequence ackID.
Bad CRC in packet
18
17
RCVD_PKT_WITH_BAD_CRC
RCVD_PKT_OVER_276B
0
1
The port did not receive a packet with a bad CRC value.
The port received a packet with a bad CRC value.
Oversize packet
0
The port did not receive packet that exceeds the maximum allowed
size.
1
0
The port received packet that exceeds the maximum allowed size.
These read-only bits return 0s when read.
16–6
5
Reserved
NON_OUTSTANDING_ACKID
Non-outstanding ackID
0
1
The port did not receive a link response with a non-outstanding ackID.
The port received a link response with an ackID that is not outstanding.
The capture registers do not have valid information during this error
detection.
4
PROTOCOL_ERROR
Protocol error
0
1
0
The port did not receive an unexpected packet or control symbol.
The port received an unexpected packet or control symbol.
This read-only bit returns 0 when read.
Delineation error
3
2
Reserved
DELINEATION_ERROR
0
1
The port did not detect a delineation error.
The port detected a delineation error. The port received an unaligned
/SC/ or /PD/ or undefined code-group. The capture registers do not
have valid information during this error detection.
1
0
UNSOLICITED_ACK_CNTL_SYM
LINK_TIMEOUT
Unsolicited acknowledge control symbol
0
1
The port did not receive an unexpected acknowledge control symbol.
The port received an unexpected acknowledge control symbol.
Link timeout
0
1
The port did not experience a link timeout.
The port experienced a link timeout. The port did not receive an
acknowledge or link-response control symbol within the specified
time-out interval. The capture registers do not have valid information
during this error detection.
220
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5.83 Port Error Rate Enable CSR n (SPn_RATE_EN)
Each of the four ports is supported by a register of this type (see Table 160). The port error rate enable
Table 160. SPn_RATE_EN Registers and the Associated Ports
Register
Address Offset
2044h
Associated Port
Port 0
SP0_RATE_EN
SP1_RATE_EN
SP2_RATE_EN
SP3_RATE_EN
2084h
Port 1
20C4h
Port 2
2104h
Port 3
Figure 146. Port Error Rate Enable CSR n (SPn_RATE_EN)
31
ERR_IMP_
SPECIFIC
30
24
Reserved
R-00h
R/W-0
23
Reserved
R-0
22
21
20
19
18
17
16
CORRUPT_
CNTL_SYM_
EN
CNTL_SYM_
UNEXPECTED_
ACKID_EN
RCVED_
PKT_NOT_
ACCPT_EN
PKT_
UNEXPECTED_
ACKID_EN
RCVED_PKT_
WITH_BAD_
CRC_EN
RCVED_
PKT_OVER_
276B_EN
Reserved
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
UNSOLICITED_
ACK_CNTL_
SYM_EN
0
NON_
OUTSTANDING_
PROTOCOL_
ERROR_EN
DELINEATION_
ERROR_EN
LINK_
TIMEOUT_EN
Reserved
R-0
Reserved
R-0
ACKID_EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 161. Port Error Rate Enable CSR n (SPn_RATE_EN) Field Descriptions
Bit
Field
Value
Description
31
EN_IMP_SPECIFIC
Rate counting enable for implementation-specific errors
Disable error rate counting of implementation specific errors
Enable error rate counting of implementation specific errors.
These read-only bits return 0s when read.
0
1
0
30–23
22
Reserved
CORRUPT_CNTL_SYM_ENABLE
Rate counting enable for corrupt control symbols
Disable error rate counting of a corrupt control symbol.
Enable error rate counting of a corrupt control symbol.
Rate counting enable for control symbols with unexpected ackIDs
0
1
21
20
CNTL_SYM_UNEXPECTED_ACKID_EN
RCVED_PKT_NOT_ACCPT_EN
0
1
Disable error rate counting of an acknowledge control symbol with
an unexpected ackID.
Enable error rate counting of an acknowledge control symbol with
an unexpected ackID.
Rate counting enable for packet-not-accepted control symbols
0
1
Disable error rate counting of received packet-not-accepted control
symbols.
Enable error rate counting of received packet-not-accepted control
symbols.
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Table 161. Port Error Rate Enable CSR n (SPn_RATE_EN) Field Descriptions (continued)
Bit
Field
Value
Description
19
PKT_UNEXPECTED_ACKID_EN
Rate counting enable for packets with unexpected ackIDs
0
1
Disable error rate counting of packets with
unexpected/out-of-sequence ackIDs
Enable error rate counting of packets with
unexpected/out-of-sequence ackIDs.
18
17
RCVED_PKT_WITH_BAD_CRC_EN
RCVED_PKT_OVER_276B_EN
Rate counting enable for packets with bad CRC
0
1
Disable error rate counting of packets with a bad CRC values.
Enable error rate counting of packets with a bad CRC values.
Rate counting enable for oversize packets
0
1
0
Disable error rate counting of packets that exceed the maximum
allowed size.
Enable error rate counting of packets that exceed the maximum
allowed size.
16–6
5
Reserved
These read-only bits return 0s when read.
NON_OUTSTANDING_ACKID_EN
Rate counting enable for non-outstanding ackIDs
0
1
Disable error rate counting of link-responses received with an
ackID that is not outstanding.
Enable error rate counting of link-responses received with an
ackID that is not outstanding.
4
PROTOCOL_ERROR_EN
Rate counting enable for protocol errors
0
1
0
Disable error rate counting of protocol errors.
Enable error rate counting of protocol errors.
This read-only bit returns 0 when read.
3
2
Reserved
DELINEATION_ERROR_EN
Rate counting enable for delineation errors
Disable error rate counting of delineation errors.
Enable error rate counting of delineation errors.
Rate counting enable for unsolicited acknowledge control symbols
0
1
1
0
UNSOLICITED_ACK_CNTL_SYM_EN
LINK_TIMEOUT_EN
0
1
Disable error rate counting of unsolicited acknowledge control
symbols.
Enable error rate counting of unsolicited acknowledge control
symbols.
Rate counting enable for link time-out errors
Disable error rate counting of link timeout errors.
Enable error rate counting of link timeout errors.
0
1
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5.84 Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0)
Each of the four ports is supported by a register of this type (see ). The port n attributes error capture CSR
Table 162. SPn_ERR_ATTR_CAPT_DBG0 Registers and the Associated Ports
Register
Address Offset
2048h
Associated Port
Port 0
SP0_ERR_ATTR_CAPT_DBG0
SP1_ERR_ATTR_CAPT_DBG0
SP2_ERR_ATTR_CAPT_DBG0
SP3_ERR_ATTR_CAPT_DBG0
2088h
Port 1
20C8h
Port 2
2108h
Port 3
Figure 147. Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0)
31
30
29
Reserved
R-0
28
24 23
INFO_TYPE
R-00
ERROR_TYPE
R-00000
IMP_SPECIFIC
R-00000h
4
3
1
0
IMP_SPECIFIC
R-00000h
Reserved
R-00
CAPTURE_
VALID_INFO
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 163. Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0) Field
Descriptions
Bit
Field
Value
Description
31–30
INFO_TYPE
Type of information logged
00b
01b
10b
Packet
Control symbol (only error capture register 0 is valid)
Implementation specific (capture register contents are
implementation specific)
11b
Reserved
29
Reserved
0
This read-only bit returns 0 when read.
28–24
ERROR_TYPE
00000b–11111b
Encoded value of captured error bit in the Port n Error Detect
Register
23–4
3–1
0
IMP_SPECIFIC
Reserved
00000h–FFFFFh
0
Implementation Dependent Error Information
These read-only bits return 0s when read.
Valid information captured
CAPTURE_VALID_INFO
0
1
The packet/control symbol capture registers do not contain valid
information.
The packet/control symbol capture registers contain valid
information. For control symbols, only capture register 0 contains
meaningful information. A software write of 0 clears this bit and
subsequently unlocks all the capture registers of the port.
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5.85 Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1)
Each of the four ports is supported by a register of this type (see Table 164). SPn_ERR_CAPT_DBG1 is
Table 164. SPn_ERR_CAPT_DBG1 Registers and the Associated Ports
Register
Address Offset
204Ch
Associated Port
Port 0
SP0_ERR_CAPT_DBG1
SP1_ERR_CAPT_DBG1
SP2_ERR_CAPT_DBG1
SP3_ERR_CAPT_DBG1
208Ch
Port 1
20CCh
Port 2
210Ch
Port 3
Figure 148. Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1)
31
0
CAPTURE0
R-00000000h
LEGEND: R = Read only; -n = Value after reset
Table 165. Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1) Field Descriptions
Bit
Field
Value
Description
31–0
CAPTURE0
00000000h
to
In the case of a control-symbol error:
Control character and control symbol that correspond to the error
FFFFFFFFh
In the case of a packet error:
Bytes 0 to 3 of the packet header that corresponds to the error
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5.86 Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2)
Each of the four ports is supported by a register of this type (see Table 166). SPn_ERR_CAPT_DBG2 is
Table 166. SPn_ERR_CAPT_DBG2 Registers and the Associated Ports
Register
Address Offset
2050h
Associated Port
Port 0
SP0_ERR_CAPT_DBG2
SP1_ERR_CAPT_DBG2
SP2_ERR_CAPT_DBG2
SP3_ERR_CAPT_DBG2
2090h
Port 1
20D0h
Port 2
2110h
Port 3
Figure 149. Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2)
31
0
CAPTURE1
R-00000000h
LEGEND: R = Read only; -n = Value after reset
Table 167. Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2) Field Descriptions
Bit
Field
Value
Description
31–0
CAPTURE1
00000000h
to
Bytes 4 to 7 of the packet header that corresponds to the error
FFFFFFFFh
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5.87 Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3)
Each of the four ports is supported by a register of this type (see Table 168). SPn_ERR_CAPT_DBG3 is
Table 168. SPn_ERR_CAPT_DBG3 Registers and the Associated Ports
Register
Address Offset
2054h
Associated Port
Port 0
SP0_ERR_CAPT_DBG3
SP1_ERR_CAPT_DBG3
SP2_ERR_CAPT_DBG3
SP3_ERR_CAPT_DBG3
2094h
Port 1
20D4h
Port 2
2114h
Port 3
Figure 150. Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3)
31
0
CAPTURE2
R-00000000h
LEGEND: R = Read only; -n = Value after reset
Table 169. Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3) Field Descriptions
Bit
Field
Value
Description
31–0
CAPTURE2
00000000h
to
Bytes 8 to 11 of the packet header that corresponds to the error
FFFFFFFFh
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5.88 Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4)
Each of the four ports is supported by a register of this type (see Table 170). The port n packet/control
Table 170. SPn_ERR_CAPT_DBG4 Registers and the Associated Ports
Register
Address Offset
2058h
Associated Port
Port 0
SP0_ERR_CAPT_DBG4
SP1_ERR_CAPT_DBG4
SP2_ERR_CAPT_DBG4
SP3_ERR_CAPT_DBG4
2098h
Port 1
20D8h
Port 2
2118h
Port 3
Figure 151. Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4)
31
0
CAPTURE3
R-00000000h
LEGEND: R = Read only; -n = Value after reset
Table 171. Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4) Field Descriptions
Bit
Field
Value
Description
31–0
CAPTURE3
00000000h
to
Bytes 12 to 15 of the packet header that corresponds to the error
FFFFFFFFh
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5.89 Port Error Rate CSR n (SPn_ERR_RATE)
Each of the four ports is supported by a register of this type (see Table 172). SPn_ERR_RATE is shown
Table 172. SPn_ERR_RATE Registers and the Associated Ports
Register
Address Offset
2068h
Associated Port
Port 0
SP0_ERR_RATE
SP1_ERR_RATE
SP2_ERR_RATE
SP3_ERR_RATE
20A8h
Port 1
20E8h
Port 2
2128h
Port 3
Figure 152. Port Error Rate CSR n (SPn_ERR_RATE)
31
15
24 23
18 17
16
ERROR_RATE_
ERROR_RATE_BIAS
R/W-FFh
Reserved
R-00h
RECOVERY
R/W-00
8
7
0
PEAK_ERROR_RATE
R/W-00h
ERROR_RATE_COUNTER
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 173. Port Error Rate CSR n (SPn_ERR_RATE) Field Descriptions
Bit
Field
Value
Description
31–24
ERROR_RATE_BIAS
These bits provide the error rate bias value.
Do not decrement the error rate counter
Decrement every 1ms (nominal)
Decrement every 10ms (nominal)
Decrement every 100ms
00h
01h
03h
07h
0Fh
1Fh
3Fh
7Fh
FFh
Other
00h
Decrement every 1s (nominal)
Decrement every 10s (nominal)
Decrement every 100s (nominal)
Decrement every 1000s (nominal)
Decrement every 10000s (nominal)
Reserved
23–18
17–16
Reserved
These read-only bits return 0s when read.
ERROR_RATE_RECOVERY
These bits limit the incrementing of the error rate counter above the
failed threshold trigger.
00b
01b
Only count 2 errors above
Only count 4 errors above
10b
Only count 16 errors above
11b
Do not limit incrementing the error rate count
This field contains the peak value attained by the error rate counter.
These bits maintain a count of the number of transmission errors that
15–8
7–0
PEAK_ERROR_RATE
00h–FFh
00h–FFh
ERROR_RATE_COUNTER
have occurred. If this value equals the value contained in the error rate
threshold trigger register, then an error will be reported.
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5.90 Port Error Rate Threshold CSR n (SPn_ERR_THRESH)
Each of the four ports is supported by a register of this type (see ). The port error rate threshold CSR n
Table 174. SPn_ERR_THRESH Registers and the Associated Ports
Register
Address Offset
206Ch
Associated Port
Port 0
SP0_ERR_THRESH
SP1_ERR_THRESH
SP2_ERR_THRESH
SP3_ERR_THRESH
20ACh
Port 1
20ECh
Port 2
212Ch
Port 3
Figure 153. Port Error Rate Threshold CSR n (SPn_ERR_THRESH)
31
15
24 23
16
0
ERROR_RATE_FAILED_THRESH
R/W-FFh
ERROR_RATE_DEGRADED_THRESH
R/W-FFh
Reserved
R-0000h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 175. Port Error Rate Threshold CSR n (SPn_ERR_THRESH) Field Descriptions
Bit
Field
Value
Description
31–24
ERROR_RATE_FAILED_THRESH
These bits provide the threshold value for reporting an error
condition due to a possibly broken link.
00h
01h
02h
...
Disable the error rate register
Set the error reporting threshold to 1
Set the error reporting threshold to 2
...
FFh
Set the error reporting threshold to 255
23–16
ERROR_RATE_DEGRADED_THRESH
These bits provide the threshold value for reporting an error
condition due to a degrading link.
00h
01h
02h
...
Disable the error rate Register
Set the error reporting threshold to 1
Set the error reporting threshold to 2
...
FFh
0000h
Set the error reporting threshold to 255
These read-only bits return 0s when read.
15–0
Reserved
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5.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER)
Figure 154. Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) - Address
Offset 12000h
31
15
28 27
24 23
20 19
16
DISCOVERY_TIMER
R/W-9h
Reserved
R-0h
PW_TIMER
R/W-8h
Reserved
R-0h
0
Reserved
R-0000h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 176. Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) Field
Descriptions
Bit
Field
Value
Description
31–28
DISCOVERY_TIMER
Discovery timer for 4x mode. The discovery timer allows time for the link partner
to enter its DISCOVERY state and if the link partner is supporting 4x mode, for
all 4 lanes to be aligned.
0000b
0001b
0010b
...
Reserved
0.84 ms
0.84 ms x 2 = 1.68 ms
...
1001b
...
0.84 ms x 9= 7.56 ms (default)
...
1111b
0000b
0.84 ms x 15= 12.6 ms
These read-only bits return 0s when read.
27–24
23–20
Reserved
PW_TIMER
Port-write timer. The timer defines a period to repeat sending an error reporting
port-write request for software assistance. The timer is stopped by software
writing to the error detect registers.
0000b
0001b
0010b
0100b
1000b
Other
0000h
Disabled. Port-write is sent once only.
107 ms–214 ms
214 ms–321 ms
428 ms–535 ms
856 ms–963 ms (default)
Reserved
19–0
Reserved
These read-only bits return 0s when read.
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5.92 Port IP Mode CSR (SP_IP_MODE)
programming information, see Section 2.3.13.2 .
Figure 155. Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h
31
SP_MODE
R/W-0
30
29
28
27
26
25
24
16
IDLE_
ERR_
DIS
TX_
FIFO_
BYPASS
PW_
DIS
TGT_
ID_DIS
SELF_
RST
Reserved
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
15
6
5
4
3
2
1
0
MLTC_ MLTC_
EN IRQ
RST_
EN
RST_
CS
PW_
EN
PW_
IRQ
Reserved
R-0
R/W-0 R/W-0
R/W-0
R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 177. Port IP Mode CSR (SP_IP_MODE) Field Descriptions
Bit
Field
Value Description
31–30 SP_MODE
SRIO port IP mode of operation
00b
01b
10b
11b
RapidIO Physical Layer 1x/4x LP-Serial Specification
4 ports (1x mode each)
Reserved
Reserved
29
28
IDLE_ERR_DIS
Idle error checking disable
0
1
Error checking enabled (default), only |K|, |A| and |R| characters are available. If input receives
any other characters in idle sequence, it should enter the Input-Error-stopped state.
Error checking disabled, all not idle or invalid characters during idle sequence are ignored
Transmit FIFO bypass
TX_FIFO_BYPASS
0
1
The TX_FIFO is operational (default)
The TX_FIFO is bypassed. The txbclk and the sys_clk must be locked during operation, but the
phase variation up to 1 clock cycle is allowable. The 4 deep FIFO is used to accommodate the
phase difference.
27
26
PW_DIS
Port-write error reporting disable.
0
1
Enable Port-Write Error reporting (default)
Disable Port-Write Error reporting
TGT_ID_DIS
Destination ID Decode Disable- Definition of packet acceptance by the physical layer.
0
1
Packet accepted if DestID = Base ID. When DestID is not equal to Base ID, the packet is
ignored; i.e., it is accepted by RapidIO port but is not forwarded to logical layer.
Packet accepted with any DestID and forwarded to the logical layer.
Self reset interrupt enable, when 4 link-request reset control symbols are accepted.
Self reset interrupt disabled (default), interrupt signal is asserted
25
SELF_RST
0
1
Self reset interrupt enabled, the reset signal is asserted by the reset controller. When the
SELF_RST is set to 1, the SERDES macro resets and all register values from address offset
1000h and higher are returned to default value. All initialized values are lost.
24–6 Reserved
0
These read-only bits return 0s when read.
5
MLTC_EN
Multicast-Event Interrupt Enable. If enabled, the interrupt signal is High when the
Multicast-Event control symbol is received by any port.
0
1
Multicast interrupt disable
Multicast interrupt enable
4
MLTC_IRQ
Multicast-event interrupt status. Once set, the MLTC_IRQ bit remains set until software writes a
1 to it. The mltc_irq output signal is driven by this bit.
0
1
The multicast event control symbol has not been received by any of the ports.
The multicast-event control symbol has been received by one of the ports.
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Table 177. Port IP Mode CSR (SP_IP_MODE) Field Descriptions (continued)
Bit
Field
Value Description
3
RST_EN
Reset Interrupt Enable. If enabled, the interrupt signal is High when the 4 reset control symbols
are received in a sequence
0
1
Reset interrupt disable
Reset interrupt enable
2
1
0
RST_CS
PW_EN
PW_IRQ
Reset received status bit. It is set when Once set, the RST_CS bit remains set until software
writes a 1 to it. The rst_irq output signal is driven by this bit.
0
1
Four reset control symbols have not been received in a sequence.
Four reset control symbols have been received in a sequence.
Port-Write-In Interrupt Enable. If enabled, the interrupt signal is High when the Port-Write-In
request is received
0
1
Port-Write-In interrupt disable
Port-Write-In interrupt enable
Port-Write-In request interrupt. Once set, the PW_IRQ bit remains set until software writes a 1
to it. The pw_irq output signal is driven by this bit.
0
1
The Port-Write-In request has not been received.
The Port-Write-In request has been received. The payload is captured.
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5.93 Port IP Prescaler Register (IP_PRESCAL)
register defines a prescaler for different frequencies of the DMA clock. The purpose of this register is to
keep the timers of SP_LT_CTL (offset 01120h), SP0_ERR_RATE through SP3_ERR_RATE (offsets
02068h, 020A8h, 020E8, and 02128h), SP_IP_DISCOVERY_TIMER (offset 12000h), and
SP0_SILENCE_TIMER through SP3_SILENCE_TIMER (offsets 14008h, 14108h, 14208h, and 14308h)
within the same range for different frequencies of the DMA clock.
Figure 156. Port IP Prescaler Register (IP_PRESCAL) - Address Offset 12008h
31
15
16
0
Reserved
R-0000h
8
7
Reserved
R-00h
PRESCALE
RW-0Fh
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 178. Port IP Prescaler Register (IP_PRESCAL) Field Descriptions
Bit
31–8
7–0
Field
Value
Description
Reserved
PRESCALE
000000h
These read-only bits return 0s when read.
For different frequencies of the DMA clock, use the following formula to get the prescaler value in
decimal, where the DMA clock frequency is in MHz:
DMA clock frequency x 16
156.25 – 1
06h
...
66.67 MHz
...
09h
...
100 MHz
...
0Fh
10h
...
156.25 MHz
166.67 MHz
...
18h
...
250 MHz
21h
333 MHz
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5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3])
Four registers are used to capture the incoming 128-bit payload of a Port-Write. These four registers are
shown in Figure 157. As can be seen in Table 179, each of the registers captures one of the four 32-bit
words of the payload.
Figure 157. Port-Write-In Capture CSRs
Port-Write-In Capture CSR 0 (SP_IP_PW_IN_CAPT0) - Address Offset 12010h
31
0
0
0
0
PW_CAPT0
R-00000000h
Port-Write-In Capture CSR 1 (SP_IP_PW_IN_CAPT1) - Address Offset 12014h
31
PW_CAPT1
R-00000000h
Port-Write-In Capture CSR 0 (SP_IP_PW_IN_CAPT0) - Address Offset 12018h
31
PW_CAPT2
R-00000000h
Port-Write-In Capture CSR 0 (SP_IP_PW_IN_CAPT0) - Address Offset 1201Ch
31
PW_CAPT3
R-00000000h
LEGEND: R = Read only; -n = Value after reset
Table 179. Port-Write-In Capture CSR Field Descriptions
Field
Value
Description
PW_CAPT0
00000000h
to
Word 0 (bits 0 to 31) of the Port-Write payload.
FFFFFFFFh
PW_CAPT1
PW_CAPT2
PW_CAPT3
00000000h
to
FFFFFFFFh
Word 1 (bits 32 to 63) of the Port-Write payload.
Word 2 (bits 64 to 95) of the Port-Write payload.
Word 3 (bits 96 to 127) of the Port-Write payload.
00000000h
to
FFFFFFFFh
00000000h
to
FFFFFFFFh
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5.95 Port Reset Option CSR n (SPn_RST_OPT)
Each of the four ports is supported by a register of this type (see Table 180). SPn_RST_OPT is shown in
Table 180. SPn_RST_OPT Registers and the Associated Ports
Register
Address Offset
14000h
Associated Port
Port 0
SP0_RST_OPT
SP1_RST_OPT
SP2_RST_OPT
SP3_RST_OPT
14100h
Port 1
14200h
Port 2
14300h
Port 3
Figure 158. Port Reset Option CSR n (SPn_RST_OPT)
31
15
16
0
Reserved
R-0000h
8
7
Reserved
R-00h
PORT_ID
R-imp
LEGEND: R = Read only; -n = Value after reset; -imp = Value after reset is implementation defined.
Table 181. Port Reset Option CSR n (SPn_RST_OPT) Field Descriptions
Bit
31–8 Reserved
7–0 PORT_ID
Field
Value Description
0
These read-only bits return 0s when read.
Port ID defines unique number for port in Switch. The Port ID is used for port-write request. The ID
coincides with ISF port of connection. Example: 00_0000_01 _ port 1 ( Impl.: IP0, port 1)
00_0001_11 _ port 7 ( Impl.: IP1, port 3).
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5.96 Port Control Independent Register n (SPn_CTL_INDEP)
Each of the four ports is supported by a register of this type (see Table 182). The port control independent
Table 182. SPn_CTL_INDEP Registers and the Associated Ports
Register
Address Offset
14004h
Associated Port
Port 0
SP0_CTL_INDEP
SP1_CTL_INDEP
SP2_CTL_INDEP
SP3_CTL_INDEP
14104h
Port 1
14204h
Port 2
14304h
Port 3
Figure 159. Port Control Independent Register n (SPn_CTL_INDEP)
31
30
29
28
27
26
FORCE_REINIT
W-0
25
24
Reserved
R-0
TX_FLW
R/W-0
SOFT_REC
R/W-0
Reserved
R-0
TRANS_MODE
R/W-01
23
22
21
20
19
18
17
16
SEND_DBG_
PKT
ILL_TRANS_
EN
ILL_TRANS_
ERR
MAX_RETRY_ MAX_RETRY_
DEBUG
R/W-0
Reserved
EN
ERR
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
15
8
0
MAX_RETRY_THR
R/W-00h
7
6
5
IRQ_EN
R/W-0
IRQ_ERR
R/W-0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 183. Port Control Independent Register n (SPn_CTL_INDEP) Field Descriptions
Bit
31
30
Field
Value
Description
Reserved
TX_FLW
0
This read-only bit returns 0 when read.
Transmit Link Flow Control enable
Disables transmit flow control (Enables receive link flow control)
Reserved
0
1
29
SOFT_REC
Software controlled error recovery
0
1
Transmission of error recovery sequence is performed by the hardware
Transmission of error recovery sequence is performed by the software. By
default the transmission error recovery sequence is performed by the hardware.
If this bit is set, the hardware recovery is disabled and the hardware
transmission logic must wait until software has written the register Port n Local
ackID Status CSR.
28–27
26
Reserved
0
These read-only bits return 0s when read.
FORCE_REINIT
Force reinitialization process. In 4x mode this bit affects all 4 lanes. This bit is
write only, and reads always return 0.
25–24
TRANS_MODE
Describes the transfer mode for each port.
Reserved (Cut-Through Mode)
Store & Forward Mode
00b
01b
1xb
Reserved
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Table 183. Port Control Independent Register n (SPn_CTL_INDEP) Field Descriptions (continued)
Bit
Field
Value
Description
23
DEBUG
Mode of operation.
Normal mode
0
1
Debug mode. The debug mode unlocks capture registers for write and enable
debug packet generator feature.
22
21
SEND_DBG_PKT
ILL_TRANS_EN
Send debug packet. Write 1 to force the sending of a debug packet. This bit is
set by software and cleared after debug packet is sent. Writes when the bit is set
are ignored. Debug mode only.
Illegal transfer error reporting enable. If enabled, the Port-Write and interrupt are
reported errors.
0
1
Disable illegal transfer error reporting.
Enable illegal transfer error reporting.
20
ILL_TRANS_ERR
Illegal Transfer Error. After being set, the ILL_TRANS_ERR bit remains set until
written with a 1, or until a value of all 0s is written to the register
SP0_ERR_DET.
0
1
No error condition detected
One of the following error conditions has been detected:
•
•
•
The received transaction has a reserved value in the tt field.
A reserved field of Maintenance transaction type is detected.
The destination ID is not defined in look-up table.
This error is also reported in registers SP0_ERR_DET and ERR_DET.
19–18
17
Reserved
0
These read-only bits return 0s when read.
MAX_RETRY_EN
Maximum retry error reporting enable. If enabled, the Port-Write and interrupt are
reported as errors.
0b
1b
Max retry error report disable
Max retry error report enable
16
MAX_RETRY_ERR
MAX_RETRY_THR
Maximum retry error. This bit is ignored if max_retry_threshold is 0. Once set,
the MAX_RETRY_ERR bit remains set until written with a 1, or until a value of
all 0s is written to the register SP0_ERR_DET.
0
1
No error condition detected
max_retry_cnt is equal to max_retry_threshold. The Port-Write request and
interrupt are generated if enabled. This error is also reported in the register
SP0_ERR_DET.
15–8
Maximum Retry Threshold Trigger. These bits provide the threshold value for
reporting an error condition due to possibly broken partner behavior.
00h
01h
02h
...
Disable the max_retry_error reporting
Set the max_retry_threshold to 1
Set the max_retry_threshold to 2
...
FFh
Set the max_retry_threshold to 255
7
6
IRQ_EN
Interrupt error reporting enable. If enabled, the interrupt signal is high when the
IRQ_ERR is set to 1.
0
1
Interrupt error report disable
Interrupt error report enable
IRQ_ERR
Reserved
Interrupt error status
0
1
An error has not occurred and/or there is not a Port-Write condition.
An error occurred and there is a Port-Write condition. IRQ_ERR remains at 1
until software writes a 1 to it.
5–0
0
These read-only bits return 0s when read.
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5.97 Port Silence Timer n Register (SPn_SILENCE_TIMER)
Each of the four ports is supported by a register of this type (see Table 184). The port silence timer n
Table 184. SPn_SILENCE_TIMER Registers and the Associated Ports
Register
Address Offset
14008h
Associated Port
Port 0
SP0_SILENCE_TIMER
SP1_SILENCE_TIMER
SP2_SILENCE_TIMER
SP3_SILENCE_TIMER
14108h
Port 1
14208h
Port 2
14308h
Port 3
Figure 160. Port Silence Timer n Register (SPn_SILENCE_TIMER)
31
15
28 27
Reserved
R-0
16
0
SILENCE_TIMER
R/W-Bh
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 185. Port Silence Timer n Register (SPn_SILENCE_TIMER) Field Descriptions
Bit
Field
Value Description
Silence timer. Defines the time of the port in the SILENT state.
0000b 64 ns for debug
31–28 SILENCE_TIMER
0001b 13.1 µs
0010b 13.1 µs x 2 = 26.2 µs
...
1011b 13.1 µs x 11 = 144.1 µs default
... ...
1111b 13.1 µs x 15= 196.5 µs
These read-only bits return 0s when read.
...
27–0 Reserved
0
238
Serial RapidIO (SRIO)
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SRIO Registers
5.98 Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS)
Each of the four ports is supported by a register of this type (see Table 186). The port multicast-event
Table 186. SPn_MULT_EVNT_CS Registers and the Associated Ports
Register
Address Offset
1400Ch
Associated Port
Port 0
SP0_MULT_EVNT_CS
SP1_MULT_EVNT_CS
SP2_MULT_EVNT_CS
SP3_MULT_EVNT_CS
1410Ch
Port 1
1420Ch
Port 2
1430Ch
Port 3
Figure 161. Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS)
31
0
MULT_EVNT_CS
W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 187. Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS) Field
Descriptions
Bit
Field
Value
Description
31–0
MULT_EVNT_CS
Write to send Control Symbol, data is ignored. Reads return 000000h.
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SRIO Registers
5.99 Port Control Symbol Transmit n Register (SPn_CS_TX)
Each of the four ports is supported by a register of this type (see Table 188). The port control symbol
Table 188. SPn_CS_TX Registers and the Associated Ports
Register
Address Offset
14014h
Associated Port
Port 0
SP0_CS_TX
SP1_CS_TX
SP2_CS_TX
SP3_CS_TX
14114h
Port 1
14214h
Port 2
14314h
Port 3
Figure 162. Port Control Symbol Transmit n Register (SPn_CS_TX)
31
15
29 28
24 23
19 18
16
0
STYPE_0
R/W-0
PAR_0
R/W-0
PAR_1
R/W-0
STYPE_1
R/W-0
13
12
11
CMD
CS_EMB
R/W-0
Reserved
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 189. Port Control Symbol Transmit n Register (SPn_CS_TX) Field Descriptions
Bit
Field
Value
Description
31–29
28–24
23–19
18–16
15–13
12
STYPE_0
PAR_0
PAR_1
STYPE_1
CMD
Encoding for control symbol that makes use of parameters PAR_0 and PAR_1.
Used in conjunction with stype0 encoding.
Used in conjunction with stype0 encoding.
Encoding for control symbol that makes use of parameter CMD.
Used in conjunction with stype1 encoding to define the link maintenance commands.
CS_EMB
When set, forces the outbound flow to insert control symbol into packet. Used in
debug mode.
11–0
Reserved
0
These read-only bits return 0s when read.
240
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Index
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Index
1x/4x LP serial port maintenance block header register
196
next expected ackID field 202
output port next transmitted ackID field 202
output port unacknowledged ackID status field 202
unexpected ackID in control symbol at port n
rate counting enable field 221
status field 219
unexpected ackID in packet at port n
rate counting enable field 222
1x/4x mode selection field for ports 231
1X_MODE field of PER_SET_SNTL 113
2 MSBs of address for LSUn 159
4x/1x mode selection field for ports 231
4x mode
data path in SRIO component block diagram 26
discovery timer period field 230
status field 220
8-bit/10-bit coding and decoding 21
8BIT_DEVID_LOW_BOUND field of PF_8B_CNTL 124
8BIT_DEVID_UP_BOUND field of PF_8B_CNTL 124
8-bit device IDs
adaptive equalizer control field 125
ADDR_CAPT 215
ADDRESS_31_3 field of ADDR_CAPT 215
ADDRESS_63_32 field of H_ADDR_CAPT 214
lower boundary for packet forwarding 124
node ID field to compare to incoming destination ID
122
node ID field to supply outgoing source ID 121
upper boundary for packet forwarding 124
8-bit node ID field
ADDRESS_LSB/CONFIG_OFFSET field of LSUn_REG1
156
ADDRESS_MSB field of LSUn_REG0 155
address associated with logical/transport error
LSBs 215
MSBs 214
to compare to incoming destination ID 122
to supply outgoing source ID 121
8BNODEID field of DEVICEID_REG1 121
8BNODEID field of DEVICEID_REG2 122
16BIT_DEVID_LOW_BOUND field of PF_16B_CNTLn
123
16BIT_DEVID_UP_BOUND field of PF_16B_CNTLn
123
16-bit device IDs
lower boundary for packet forwarding 123
node ID field to compare to incoming destination ID
122
node ID field to supply outgoing source ID 121
upper boundary for packet forwarding 123
16-bit node ID field
to compare to incoming destination ID 122
to supply outgoing source ID 121
16BNODEID field of DEVICEID_REG1 121
16BNODEID field of DEVICEID_REG2 122
address capture CSRs for logical/transport errors 214,
215
address LSBs for LSUn destination 156
address MSBs for LSUn destination 155
ALIGN field of SERDES_CFGRXn_CNTL 125
amplitude reduction (de-emphasis) field 128
ASBLY_ID 184
ASBLY_INFO 185
assembly identity CAR 184
assembly information CAR 185
ASSY_IDENTITY field of ASBLY_ID 184
ASSY_VENDORIDENTITY field of ASBLY_ID 184
ASSYREV field of ASBLY_INFO 185
ATOMIC_CLEAR field of DEST_OP 189
ATOMIC_CLEAR field of SRC_OP 188
ATOMIC_DCRMNT field of DEST_OP 189
ATOMIC_DCRMNT field of SRC_OP 188
ATOMIC_INCRMNT field of DEST_OP 189
ATOMIC_INCRMNT field of SRC_OP 188
ATOMIC_SET field of DEST_OP 189
ATOMIC_SET field of SRC_OP 188
ATOMIC_TEST_AND_SWAP field of DEST_OP 189
ATOMIC_TEST_AND_SWAP field of SRC_OP 188
Atomic operations
A
ACKID_STATUS field of SPn_LM_RESP 201
acknowledge control symbol overdue at port n
rate counting enable field 222
status field 220
overview 65
packet Ftypes and Ttypes 25
acknowledge control symbols in SRIO operation
sequence 22
Atomic operations support for destination device 189
Atomic operations support for source device 188
acknowledge IDs
ackID status field for link response 201
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SRIO Registers
BYTE_COUNT field of LSUn_REG3 158
B
bad CRC in control symbol at port n
rate counting enable field 221
status field 219
bad CRC in packet at port n
rate counting enable field 222
status field 220
C
CAPTURE0 field of SPn_ERR_CAPT_DBG1 224
CAPTURE1 field of SPn_ERR_CAPT_DBG2 225
CAPTURE2 field of SPn_ERR_CAPT_DBG3 226
CAPTURE3 field of SPn_ERR_CAPT_DBG4 227
CAPTURE_VALID_INFO field of
SPn_ERR_ATTR_CAPT_DBG0 223
bandwidth per differential pair based on 1x/4x LP-Serial
specification 18
CBA_TRANS_PRI field of PER_SET_CNTL 113
cc field of RX buffer descriptor 47
cc field of TX buffer descriptor 52
CDR field of SERDES_CFGRXn_CNTL 125
CLASS field of PID 111
BASE_DEVICEID field of BASE_ID 193
BASE_ID 193
base address registers for local configuration space
191, 192
base device ID CSR 193
clearing interrupt conditions 86
clear registers
for CPPI interrupt conditions 135, 137
for doorbell interrupt conditions 133
for error, reset, and special event (port) interrupt
conditions 143
for LSU interrupt conditions 141
clock/data recovery field 125
clock domains 21
clock prescaler field 233
clock recovery 21
CMD field of SPn_CS_TX 240
CM field of SERDES_CFGTXn_CNTL 128
CNTL_SYM_UNEXPECTED_ACKID_EN field of
SPn_RATE_EN 221
CNTL_SYM_UNEXPECTED_ACKID field of
SPn_ERR_DET 219
command control symbol field for port n 240
COMMAND field of SPn_LM_REQ 200
command status (completion code) field for LSUn 161
common mode field 128
common transport large system support field 186
Communications Port Programming Interface. See CPPI
43
base device ID for host PE 194
Big Endian versus Little Endian 68
binary notational convention 14
BLK0_EN_STAT field of GBL_EN_STAT 117
BLK1_EN_STAT field of GBL_EN_STAT 117
BLK2_EN_STAT field of GBL_EN_STAT 117
BLK3_EN_STAT field of GBL_EN_STAT 117
BLK4_EN_STAT field of GBL_EN_STAT 117
BLK5_EN_STAT field of GBL_EN_STAT 117
BLK6_EN_STAT field of GBL_EN_STAT 117
BLK7_EN_STAT field of GBL_EN_STAT 117
BLK8_EN_STAT field of GBL_EN_STAT 117
BLKn_EN 119
BLKn_EN_STAT 120
block 0 enable status bit 118
block 1 enable status bit 117
block 2 enable status bit 117
block 3 enable status bit 117
block 4 enable status bit 117
block 5 enable status bit 117
block 6 enable status bit 117
block 7 enable status bit 117
block 8 enable status bit 117
block diagram of SRIO components 26
block diagram of SRIO peripheral 21
block enable registers 119
block enable status registers 120
BOOT_COMPLETE field of PER_SET_CNTL 113
bootloading
COMP_TAG 195
COMPLETION_CODE field of LSUn_REG6 161
completion pointer for RX queue n 167
completion pointer for TX queue n 165
COMPONENT_TAG field of COMP_TAG 195
configuration offset field for LSUn 156
configuring SERDES macros 28
congestion control 65
access to read-only registers 113
configuration and operation 79
data movement 80
device wakeup afterwards 80
BRIDGE field of PE_FEAT 186
bridge present field 186
BSY field of LSUn_REG6 161
basic scheme 66
congestion control packet (CCP) Ftype and Ttype 25
congestion control packet (CCP) purpose 65
count of Xoff congestion control packets 66
flow control destination IDs 66
buffer_pointer field of RX buffer descriptor 47
buffer_pointer field of TX buffer descriptor 52
BUSWIDTH field of SERDES_CFGRXn_CNTL 125
BUSWIDTH field of SERDES_CFGTXn_CNTL 128
busy (BSY) signal of an LSU 39
busy status field for LSUn 161
flow masks 67
time-out timer 66
control capture CSR for logical/transport errors 217
control information field for port n error capture 224
control symbols
acknowledge or link-response control symbol overdue
242
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SRIO Registers
at port n
rate counting enable field 222
requesting interrupt with INTERRUPT_REQ field 159
CRC errors
bad CRC in control symbol at port n
rate counting enable field 221
status field 219
bad CRC in packet at port n
rate counting enable field 222
status field 220
status field 220
bad CRC in control symbol at port n
rate counting enable field 221
status field 219
detect 4 reset control symbols at port 232
detect multicast-event control symbol at port 231
enable interrupt if 4 reset control symbols received at
port 232
recovery suppression support field 186
CRC in control symbol 24
enable interrupt if multicast-event control symbol
received at port 231
force insertion of control symbol in outbound packet
240
initiate self reset interrupt if 4 link-request control
symbols accepted 231
introduction 24
CRC in packet 23
credit for outbound packets 75
CRF_SUPPORT field of PE_FEAT 186
critical error interrupt to the CPU 85
critical request flow support field 186
CS_EMB field of SPn_CS_TX 240
CTRL_CAPT 217
link maintenance command field for port n 240
link maintenance request control symbol generation
register 200
packet-not-accepted control symbol at port n
rate counting enable field 221
status field 220
parameter0 field for port n 240
parameter1 field for port n 240
port multicast-event control symbol request field 239
stype0 field for port n 240
cut-through mode option for port n 236
D
DATA_MESS field of DEST_OP 189
DATA_MESS field of SRC_OP 188
data flow diagram for Load/Store module 39
data flow overview for SRIO peripheral 21
data message support for destination device 189
data message support for source device 188
data rate select field for SERDES receiver 126
DEBUG field of SPn_CTL_INDEP 236
debug mode selection for port n 237
debug packet field for port n 237
decode registers for interrupt conditions 150
decoding interrupt condition source 97
decrement rate for port error rate counter 228
de-emphasis field 128
stype1 field for port n 240
transmit request field for port n 240
unexpected ackID in control symbol at port n
rate counting enable field 221
status field 219
unexpected acknowledge control symbol at port n
rate counting enable field 222
status field 220
unexpected control symbol at port n
rate counting enable field 222
status field 220
CORRUPT_CNTL_SYM_EN field of SPn_RATE_EN
221
CORRUPT_CNTL_SYM field of SPn_ERR_DET 219
corrupt control symbol at port n
rate counting enable field 221
status field 219
corrupt packet at port n
rate counting enable field 222
status field 220
DE field of SERDES_CFGTXn_CNTL 128
delimiting of control symbols 24
delineation error at port n
rate counting enable field 222
status field 220
dest_id field of TX buffer descriptor 52
DEST_OP 189
DESTID field for LSUn 159
DESTID field of ID_CAPT 216
DESTID field of LSUn_REG4 159
destination IDs
destination ID associated with logical/transport error
216
count down value for interrupt rate control 154
CPPI 43
boundary diagram 50
device ID for port-write target 218
disable base ID match requirement field for ports 231
for control flows
rules for data traffic 43
RX operation 44
description 181
introduction 66
TX operation 51
for LSU transmission 159
CPU
size select field for flow control 181
destination operations CAR 189
DEV_ID 182
in Load/Store module data flow diagram 39
interrupts 85
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SRIO Registers
DEV_INFO 183
doorbell interrupt condition status registers 132
DOORBELLn_ICCR 133
DOORBELLn_ICRR 144
DEVICE_VENDORIDENTITY field of DEV_ID 182
DEVICEID_MSB field of PW_TGT_ID 218
DEVICEID_REG1 121
DOORBELLn_ICRR2 144
DEVICEID_REG2 122
DOORBELLn_ICSR 132
device ID capture CSR for logical/transport errors 216
device identity CAR 182
doorbell operation 63
doorbell packets
DEVICEIDENTITY field of DEV_ID 182
DEVICEID field of PW_TGT_ID 218
device IDs
Ftype and Ttype 25
packet header 64
priority 64
base device ID for host PE 194
base device ID for large common transport system
193
base device ID for small common transport system
193
device ID for port-write target 218
disable base ID match requirement field for ports 231
flow control destination ID size field 181
lower boundary for packet forwarding
8-bit IDs 124
16-bit IDs 123
node ID field to compare to incoming destination ID
122
node ID field to supply outgoing source ID 121
size selection field for LSUn 159
upper boundary for packet forwarding
8-bit IDs 124
used to cause CPU interrupts 85
doorbell-retry response during direct I/O reception 42
doorbell support for destination device 189
doorbell support for source device 188
DRBLL_INFO field of LSUn_REG5 160
drop packet enable for port n 207
DSP address field for LSUn 157
E
EF_ID field of ERR_RPT_BH 209
EF_ID field of SP_MB_HEAD 196
EF_PTR field of ERR_RPT_BH 209
EF_PTR field of SP_MB_HEAD 196
emulation 74
EN_STAT field of BLKn_EN_STAT 120
enable and enable status registers 71
enable bit(s)
16-bit IDs 123
device information CAR 183
device revision field 183
for access to read-only registers during boot loading
113
for adaptive equalizer 125
device type field 182
for entire SRIO peripheral 116
for fixed-phase transmit clocking 128
for flow control 112
device wakeup after bootloading 80
differential signals/pins 25
direct I/O
for logical blocks 119
data path description 39
introduction 35
RX operation 42
TX operation 40
disable error checking for port n 207
disable port n 207
for port idle error checking 231
for port illegal-transfer error reporting 237
for port multicast-event interrupt 231
for port n 207
for port reset interrupt 232
for port self-reset interrupt 231
for port-write error reporting 231
for port-write-in interrupt 232
for SERDES PLLs 115, 131
for SERDES receivers 126
for SERDES transmitters 129
enable input only for port n 207
enable multicast-event participation for port n 207
enable output only for port n 207
enable status bit(s)
for entire SRIO peripheral 117
for logical blocks 0 through 8 117, 120
endianness 68
EN field of BLKn_EN 119
EN field of GBL_EN 116
DISCOVERED field of SP_GEN_CTL 199
DISCOVERY_TIMER field of
SP_IP_DISCOVERY_TIMER 230
DMA bus
considerations regarding CPU interrupts 85
in data path description for LSUs 39
in direct I/O RX operation 42
in Load/Store module data flow diagram 39
in message passing 43
in SRIO component block diagram 26
DMA clock frequency as variable in clock prescaling
233
DMA error status bit for MAU 211
doorbell information field for LSUn 160
doorbell interrupt condition clear registers 133
doorbell interrupt condition routing registers 144
ENFTP field of SERDES_CFGTXn_CNTL 128
ENPLL1 field of PER_SET_CNTL 113
244
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SRIO Registers
ENPLL2 field of PER_SET_CNTL 113
ENPLL3 field of PER_SET_CNTL 113
ENPLL4 field of PER_SET_CNTL 113
ENPLL field of SERDES_CFGn_CNTL 130
ENRX field of SERDES_CFGRXn_CNTL 125
ENTX field of SERDES_CFGTXn_CNTL 128
eop field of RX buffer descriptor 47
eop field of TX buffer descriptor 52
eoq field of RX buffer descriptor 47
eoq field of TX buffer descriptor 52
EQ field of SERDES_CFGRXn_CNTL 125
equalizer control field 125
ERR_DET 210
ERR_EN 212
ERR_MSG_FORMAT_ENABLE field of ERR_EN 212
ERR_MSG_FORMAT field of ERR_DET 210
ERR_RPT_BH 209
register 142
ERROR response
during direct I/O reception 42
during message passing 43
error status interrupt to the CPU 85
error type field for port n error capture 223
EXTENDED_ADDRESSING_CONTROL field of
PE_LL_CTL 190
EXTENDED_ADDRESSING_SUPPORT field of
PE_FEAT 186
EXTENDED_FEATURES field of PE_FEAT 186
extended address 2 MSBs field for LSUn 159
extended address LSB field for LSUn 156
extended address MSB field for LSUn 155
extended features ID field 196
EXTENDEDFEATURESPTR field of ASBLY_INFO 185
extended feature support field 186
external device requirements 20
ERR_RST_EVNT_ICCR 143
ERR_RST_EVNT_ICRR 149
ERR_RST_EVNT_ICRR2 149
F
features not supported in SRIO peripheral 20
features supported in SRIO peripheral 19
FIFOs
in data path description for LSUs 39
in direct I/O RX operation 42
in direct I/O TX operation 40
in Load/Store module data flow diagram 39
in message passing 43
ERR_RST_EVNT_ICRR3 149
ERR_RST_EVNT_ICSR 142
ERROR_CHECK_DISABLE field of SPn_CTL 206
ERROR_RATE_BIAS field of SPn_ERR_RATE 228
ERROR_RATE_COUNTER field of SPn_ERR_RATE
228
ERROR_RATE_DEGRADED_THRESH field of
SPn_ERR_THRESH 229
ERROR_RATE_FAILED_THRESH field of
SPn_ERR_THRESH 229
in SRIO peripheral block diagram 21
TX FIFO bypass field for ports 231
ERROR_RATE_RECOVERY field of SPn_ERR_RATE
228
finding interrupt source with help from interrupt status
decode registers 97
ERROR_TYPE field of SPn_ERR_ATTR_CAPT_DBG0
223
error checking for ports
fixed transmit clock phase enable bit 128
FLOW_CNTL_ID field of FLOW_CNTLn 181
FLOW_CNTLn 181
general error checking disable field 207
idle error checking disable field 231
error handling and logging for logical/transport errors 83
error rate counter for port n
count value 228
decrement rate 228
FLOW_CONTROL_SUPPORT field of PE_FEAT 186
FLOW_MASK field of LSUn_FLOW_MASKS 162
flow control 65
flow control enable bit
for data flow in logical layer of peripheral 112
for port n transmit flow control 236
flow control table entry register 181
flow masks
peak count value 228
threshold 228
error rate counting enable register for port n 221
error rate thresholds for port n
broken link case 229
for CPPI (message) transmission 169
for LSU transmission 162
introduction 67
force insertion of control symbol in outbound packet 240
force reinitialization process for port n 236
format type associated with logical/transport error 217
FREE field of PCR 112
degraded link case 229
error recovery software option for port n 236
error reporting block header register 209
error reporting thresholds for port n
broken link case 229
degraded link case 229
error, reset, and special event interrupt condition clear
register 143
error, reset, and special event interrupt condition routing
registers 149
error, reset, and special event interrupt condition status
free run bit 112
free run emulation mode 75
frequency points of 1x/4x LP-Serial specification 18
frequency prescaler select field 114
frequency range versus MPY value 30
FTYPE field of CTRL_CAPT 217
Ftypes of SRIO packets 25
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SRIO Registers
interrupt condition clearing 86
interrupt condition clear registers
for CPPI interrupt conditions 135, 137
for doorbell interrupt conditions 133
for error, reset, and special event (port) interrupt
conditions 143
for LSU interrupt conditions 141
interrupt condition routing 93
interrupt conditions 85
G
GBL_EN 116
GBL_EN_STAT 117
global enable bit 116
global enable status bit 118
global enabling/disabling of all logical blocks 71
H
H_ADDR_CAPT 214
interrupt condition status checking 86
interrupt condition status registers
for CPPI interrupt conditions 134, 136
head descriptor pointer field for RX queue n 166
head descriptor pointer field for TX queue n 164
header fields
for doorbell interrupt conditions 132
for error, reset, and special event (port) interrupt
conditions 142
interrupt destinations
controlling interrupt pacing with interrupt rate control
registers 99
narrowing down interrupt sources with help from
interrupt status decode registers 97
selecting with interrupt condition routing registers 93
interrupt error at port n
reporting enable field 237
status field 237
doorbell operation 64
message request packet 44
hexadecimal notational convention 14
HOP_COUNT field of LSUn_REG5 160
host base device ID lock CSR 194
host device mode field 199
I
ID_CAPT 216
ID_SIZE field of LSUn_REG4 159
idle error checking disable field for ports 231
ILL_TRANS_EN field of SPn_CTL_INDEP 236
ILL_TRANS_ERR field of SPn_CTL_INDEP 236
illegal transaction at LSU, TXU, MAU, or RXU
reporting enable field 212
status field 210
illegal transfer error at port n
reporting enable field 237
status field 237
INBOUND_ACKID field of SPn_ACKID_STAT 202
INFO_TYPE field of SPn_ERR_ATTR_CAPT_DBG0
223
initialization example for message passing 61
initialization example for the SRIO peripheral 77
INITIALIZED_PORT_WIDTH field of SPn_CTL 206
initialized status bit for ports 205
interrupt generation 99
interrupt handling 100
interrupt pacing (rate control) 99
interrupt rate control registers 154
interrupt request field for LSUn 159
interrupt status decode registers
description 150
introduction 97
mapping example 98
invert polarity bit for SERDES receiver 126
invert polarity bit for SERDES transmitter 128
INVPAIR field of SERDES_CFGRXn_CNTL 125
INVPAIR field of SERDES_CFGTXn_CNTL 128
I/O error response at LSU
reporting enable field 212
status field 210
IP_PRESCAL 233
IRQ_EN field of SPn_CTL_INDEP 236
IRQ_ERR field of SPn_CTL_INDEP 236
initialized width field for port n 206
in-order reception of message packets 49
in-order requirement bits for RX queues 173
INPUT_ERROR_ENC field of SPn_ERR_STAT 203
INPUT_ERROR_STP field of SPn_ERR_STAT 203
INPUT_PORT_ENABLE field of SPnCTL 206
INPUT_RETRY_STP field of SPn_ERR_STAT 203
input enable field for port n 207
input error-stopped status bit for ports 204
input retry-stopped status bit for ports 204
input termination field for SERDES receiver 126
input transmission error status bit for ports 204
INTDSTn_DECODE 150
INTDSTn_RATE_CNTL 154
interconnect architecture for RapidIO 18
interfacing two 1x or 4x devices 18
INTERRUPT_REQ field of LSUn_REG4 159
interrupt approach to messaging protocol 86
L
L2 memory in Load/Store module data flow diagram 39
lane select field for port n 206
large common transport system base device ID 193
large common transport system support field 186
LB field of SERDES_CFGn_CNTL 130
LCL_CFG_BAR 192
LCL_CFG_HBAR 191
LETTER_MASK field of RXU_MAP_Ln 178
LETTER field of RXU_MAP_Ln 178
letter number associated with logical/transport error 217
letter number masking 45
letters and mailboxes 43
246
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SRIO Registers
limiting which devices can access a mailbox 45
line rate versus PLL output clock frequency 29
LINK_STATUS field of SPn_LM_RESP 201
LINK_TIMEOUT_EN field of SPn_RATE_EN 221
LINK_TIMEOUT field of SPn_ERR_DET 219
link maintenance command field for port n 240
link-request control symbol generation register 200
link responses
acknowledge or link-response control symbol overdue
at port n
rate counting enable field 222
status field 220
link-response valid field 201
LSU_ICSR 138
LSU congestion control flow mask register 162
LSU control register 0 155
LSU control register 1 156
LSU control register 2 157
LSU control register 3 158
LSU control register 4 159
LSU control register 5 160
LSU control register 6 161
LSU interrupt condition clear register 141
LSU interrupt condition routing registers 147
LSU interrupt condition status register 138
LSUn_FLOW_MASKS 162
LSUn_REG0 155
link status received 201
non-outstanding ackID at port n
rate counting enable field 222
status field 220
LSUn_REG1 156
LSUn_REG2 157
LSUn_REG3 158
link timeout at port n
LSUn_REG4 159
rate counting enable field 222
status field 220
LSUn_REG5 160
LSUn_REG6 161
Little Endian versus Big Endian 68
Load/Store module
data flow diagram 39
LSUs
data path description 39
enable bit 119
data path description 39
enable bit 119
enable status bits 117, 120
power down state 43
Load/Store units. See LSUs 40
local configuration space base address CSRs 191, 192
lockout field for port n 207
logical blocks of the SRIO peripheral 71
logical layer
content in SRIO data stream 22
definition 16
logical layer buffers
in packet transmission discussion 75
in SRIO component block diagram 26
logical/transport error handling and logging 83
logical/transport layer address capture CSR 215
logical/transport layer control capture CSR 217
logical/transport layer device ID capture CSR 216
logical/transport layer error detect CSR 210
logical/transport layer error enable CSR 212
logical/transport layer high address capture CSR 214
LOG. See logical layer 23
enable status bits 117, 120
handling of unavailable outbound credit 76
in Load/Store module data flow diagram 39
in SRIO component block diagram 26
register introduction 35
register-load timing diagram 37
register programming example 38
RX operation 42
TX operation 40
M
MAILBOX_MASK field of RXU_MAP_Ln 178
mailboxes and letters 43
mailbox field of RX buffer descriptor 47
MAILBOX field of RXU_MAP_Ln 178
mailbox field of TX buffer descriptor 52
mailbox number associated with logical/transport error
217
mailbox number masking 45
mailbox to queue mapping during message reception
introduction 44
register descriptions 177
loopback mode 113
maintenance packets
loop bandwidth field for SERDES PLL 130
LOS field of SERDES_CFGRXn_CNTL 125
loss of signal detection in SERDES receiver 126
LSBs of address associated with logical/transport error
215
LSBs of destination ID associated with logical/transport
error 216
LSBs of source ID associated with logical/transport error
216
Ftypes and Ttypes 25
introduction 63
masking mailbox and letter numbers 45
master device mode field 199
MAU
enable bit 119
enable status bits 117, 120
handling of unavailable outbound credit 76
in SRIO component block diagram 26
MAX_RETRY_EN field of SPn_CTL_INDEP 236
LSU_ICCR 141
LSU_ICRR0 to LSU_ICRR3 147
SPRUE13A–September 2006
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SRIO Registers
MAX_RETRY_ERR field of SPn_CTL_INDEP 236
MAX_RETRY_THR field of SPn_CTL_INDEP 236
maximum packet size exceeded at port n
rate counting enable field 222
status field 220
MMRs enable bit 119
MMRs enable status bits 118, 120
mode selection field for ports 231
MPY field of SERDES_CFGn_CNTL 130
MPY value versus frequency range 30
MSB_DESTID field of ID_CAPT 216
MSB_SOURCEID field of ID_CAPT 216
maximum retry error at port n
reporting enable field 237
MSBs of address associated with logical/transport error
214
reporting threshold field 237
status field 237
MSBs of destination ID associated with logical/transport
error 216
MSBs of source ID associated with logical/transport error
216
MSG_ERR_RESP_ENABLE field of ERR_EN 212
MSG_ERR_RSPNS field of ERR_DET 210
MSG_REQ_TIMEOUT_ENABLE field of ERR_EN 212
MSG_REQ_TIMEOUT field of ERR_DET 210
MSGINFO field of CTRL_CAPT 217
MULT_EVNT_CS field of SPn_MULT_EVNT_CS 239
MULTICAST_PARTICIPANT field of SPn_CTL 206
multicast-event control symbol request field for port n
239
multicast-event interrupt enable field for ports 231
multicast-event interrupt status field for ports 231
multicast-event participant enable field for port n 207
multiple ports with 1x operation 75
memory access unit. See MAU 26
MEMORY field of PE_FEAT 186
memory-mapped registers enable bit 119
memory-mapped registers enable status bits 118, 120
memory present field 186
message_length field of RX buffer descriptor 47
message_length field of TX buffer descriptor 52
message error response at TXU
reporting enable field 212
status field 210
message format error at RXU
reporting enable field 212
status field 210
message packet Ftype and Ttype 25
message passing 43
CPPI reset and power down state 59
ERROR response 43
multiply field for SERDES PLL 131
initialization example 61
interrupting the CPU after reception 86
order of received packets 49
order of response packets during TX operation 58
order of transmitted packets 54
responses to CPPI transmissions 58
RETRY response 43
N
next_descriptor_pointer field of RX buffer descriptor 47
next_descriptor_pointer field of TX buffer descriptor 52
next expected acknowledge ID field 202
next transmitted acknowledge ID field 202
node ID field
to compare to incoming destination ID 122
to supply outgoing source ID 121
NON_OUTSTANDING_ACKID_EN field of
SPn_RATE_EN 221
NON_OUTSTANDING_ACKID field of SPn_ERR_DET
219
non-posted WRITE operations during direct I/O
transmission 41
RX buffer descriptor fields 47
RX buffer descriptor link-list figure 61
RX descriptor pointers 46
RX operation 44
software requirements 60
teardown of RX buffer descriptor queues 50
time-out condition during RX operation 47
time-out condition during TX operation 59
TX buffer descriptor fields 52
TX buffer descriptor link-list figure 62
TX descriptor pointers 51
normal mode selection for port n 237
notational conventions 14
NREAD packet Ftype and Ttype 25
number of data bytes field for LSUn 158
Number of Msgs fields of TX_QUEUE_CNTLn 174
NWRITE_R packet Ftype and Ttype 25
NWRITE packet Ftype and Ttype 25
TX operation 51
weighted round-robin transmission scheme 54
message request packet header fields 44
message request timeout at RXU
reporting enable field 212
status field 211
message segment associated with logical/transport error
217
message support for destination device 189
message support for source device 188
MLTC_EN field of SP_IP_MODE 231
MLTC_IRQ field of SP_IP_MODE 231
O
OK status bit for ports 205
operating rate field
for SERDES receiver 126
for SERDES transmitter 128
operation sequence for SRIO packets 22
OUT_BOUND_ PORT field of PF_8B_CNTL 124
248
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SRIO Registers
OUTBOUND_ACKID field of SPn_ACKID_STAT 202
outbound credit 75
outbound port number for packet forwarding 124
out-of-order reception of message packets 49
packet response timeout at LSU or TXU
reporting enable field 213
status field 211
packets
bad CRC in packet at port n
rate counting enable field 222
status field 220
force insertion of control symbol in outbound packet
240
Ftype and Ttype 25
maintenance packets 63
operation sequence 22
oversize packet at port n
out-of-order responses during message-passing TX
operation 58
OUTPORTID field of LSUn_REG4 159
OUTPUT_DEGRD_ENC field of SPn_ERR_STAT 203
OUTPUT_ERROR_ENC field of SPn_ERR_STAT 203
OUTPUT_ERROR_STP field of SPn_ERR_STAT 203
OUTPUT_FLD_ENC field of SPn_ERR_STAT 203
OUTPUT_PKT_DROP field of SPn_ERR_STAT 203
OUTPUT_PORT_ENABLE field of SPn_CTL 206
OUTPUT_RETRIED field of SPn_ERR_STAT 203
OUTPUT_RETRY_ENC field of SPn_ERR_STAT 203
OUTPUT_RETRY_STP field of SPn_ERR_STAT 203
output amplitude field 128
output degraded status bit for ports 203
output enable field for port n 207
output error-stopped status bit for ports 204
output failed status bit for ports 203
output packet drop status bit for ports 203
output port number field for LSUn 159
output retry control symbol status bit for ports 204
output retry status bit for ports 204
output retry-stopped status bit for ports 204
output swing field 128
rate counting enable field 222
status field 220
send debug packet field for port n 237
streaming-write example 23
unexpected ackID in packet at port n
rate counting enable field 222
status field 220
unexpected packet at port n
rate counting enable field 222
status field 220
PAR_0 field of SPn_CS_TX 240
PAR_1 field of SPn_CS_TX 240
parameter0 control symbol field for port n 240
parameter1 control symbol field for port n 240
payload capture fields for port-write-in 234
PCR 112
output transmission error status bit for ports 204
OUTSTANDING_ACKID field of SPn_ACKID_STAT 202
override memory sleep bit 113
PE_FEAT 186
oversize packet at port n
PE_LL_CTL 190
rate counting enable field 222
status field 220
peak value of error rate counter for port n 228
PER_SET_CNTL 113
ownership field of RX buffer descriptor 47
ownership field of TX buffer descriptor 52
PEREN field of PCR 112
peripheral class field 111
peripheral control register 112
peripheral data flow 21
P
PACKET_TYPE field of LSUn_REG5 160
packet drop status bit for ports 203
packet forwarding registers
8-bit device IDs 124
peripheral flow control enable bit 112
peripheral global enable register 116
peripheral global enable status register 117
peripheral identification register 111
peripheral revision field 111
peripheral settings control register 113
peripheral type field 111
PF_8B_CNTL 124
PF_16B_CNTLn 123
PHY. See physical layer 23
physical layer
content in SRIO data stream 22
control symbols 24
16-bit device IDs 123
packet header capture fields for port n error capture
bytes 0 to 3 224
bytes 4 to 7 225
bytes 8 to 11 226
bytes 12 to 15 227
packet header fields
direct I/O operation 38
doorbell operation 64
message request packet 44
packet-not-accepted control symbol at port n
rate counting enable field 221
status field 220
packet priority field for LSUn 159
packet reordering during transmission 75
definition 16
in Load/Store module data flow diagram 39
specifications 18
Physical Layer 1x/4x LP-Serial specification 18
physical layer buffers
in packet transmission discussion 75
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SRIO Registers
in SRIO component block diagram 26
PID register 111
pins/differential signals 25
port multicast-event control symbol request registers
239
port n error capture
control information field 224
PKT_RESP_TIMEOUT_ENABLE field of ERR_EN 212
PKT_RSPNS_TIMEOUT field of ERR_DET 210
PKT_UNEXPECTED_ACKID_EN field of SPn_RATE_EN
221
PKT_UNEXPECTED_ACKID field of SPn_ERR_DET
219
PLL block for SERDES 21, 28
packet header bytes 0 to 3 field 224
packet header bytes 4 to 7 field 225
packet header bytes 8 to 11 field 226
packet header bytes 12 to 15 field 227
type of error field 223
type of information field 223
valid information field 223
PLL enable bit 131
PLL multiply field for SERDES macro 131
PLL output clock frequency versus line rate 29
pointer to the next block in the data structure 196
polarity inversion bit
for RIORX and RIORX (reception) 126
for RIOTX and RIOTX (transmission) 128
port 0 enable status bit 117
port 1 enable status bits 117
port 2 enable status bits 117
port 3 enable status bits 117
PORT_DISABLE field of SPn_CTL 206
PORT_ERROR field of SPn_ERR_STAT 203
PORT_ID field of SPn_RST_OPT 235
port_id field of TX buffer descriptor 52
PORT_LOCKOUT field of SPn_CTL 206
PORT_OK field of SPn_ERR_STAT 203
PORT_TYPE field of SPn_CTL 206
PORT_UNINITIALIZED field of SPn_ERR_STAT 203
PORT_WIDTH_OVERRIDE field of SPn_CTL 206
PORT_WIDTH field of SPn_CTL 206
PORT_WRITE_PND field of SPn_ERR_STAT 203
PORT_WRITE field of DEST_OP 189
PORT_WRITE field of SRC_OP 188
port attributes error capture CSR 0 223
port control CSR 206
port control independent register 236
port control symbol transmit registers 240
port error and status CSR 203
port error capture CSR 1 224
port error capture CSR 2 225
port error capture CSR 3 226
port error capture CSR 4 227
port error detect CSR 219
port error rate CSR 228
port error rate enable CSR 221
port error rate threshold CSR 229
port general control CSR 199
port ID field for port-write request at port n 235
port IP discovery timer for 4x mode register 230
port IP mode CSR 231
port reset option CSR 235
port response time-out control CSR 198
ports
enable bits 119
enable status bits 120
in SRIO component block diagram 26
port silence timer registers 238
port-write error reporting disable field 231
port-write generation support for destination device 189
port-write generation support for source device 188
port-write-in capture CSR 234
port-write-in capture payload 234
port-write-in interrupt enable field 232
port-write-in interrupt status field 232
port-write maintenance operation 63
port-write pending status field 204
port-write repeat period field 230
port-write request port ID 235
port-write target device ID CSR 218
posted WRITE operations during direct I/O transmission
41
power down state
CPPI module 59
Load/Store module 43
PRESCALE field of IP_PRESCAL 233
PRESCALER_SELECT field of PER_SET_CNTL 113
pri field of RX buffer descriptor 47
pri field of TX buffer descriptor 52
priority arbiter for single-port transmission 76
PRIORITY field of LSUn_REG4 159
priority of doorbell packets 64
priority transmit credit thresholds 113
processing element features CAR 186
processing element logical layer control CSR 190
PROCESSOR field of PE_FEAT 186
processor present field 186
PROMISCUOUS field of RXU_MAP_Hn
description 178
introduction 45
PROTOCOL_ERROR_EN field of SPn_RATE_EN 221
PROTOCOL_ERROR field of SPn_ERR_DET 219
PW_CAPT0 field of SP_IP_PW_IN_CAPT0 234
PW_CAPT1 field of SP_IP_PW_IN_CAPT1 234
PW_CAPT2 field of SP_IP_PW_IN_CAPT2 234
PW_CAPT3 field of SP_IP_PW_IN_CAPT3 234
port IP prescaler register 233
port link maintenance request CSR 200
port link maintenance response CSR 201
port link time-out control CSR 197
port local ackID status CSR 202
250
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SRIO Registers
PW_DIS field of SP_IP_MODE 231
PW_EN field of SP_IP_MODE 231
PW_IRQ field of SP_IP_MODE 231
PW_TGT_ID 218
read support for destination device 189
read support for source device 188
READ transactions during direct I/O transmission 41
receive CPPI control register 173
receive CPPI interrupt condition clear register 135
receive CPPI interrupt condition routing registers 145
receive CPPI interrupt condition status register 134
receive queue teardown register 172
receiver enabling for SERDES macro
introduction 30
PW_TIMER field of SP_IP_DISCOVERY_TIMER 230
Q
QUEUE_ID field of RXU_MAP_Hn 178
QUEUEn_FLOW_MASK fields of
TX_CPPI_FLOW_MASKS[0–7] 169
QUEUEn_IN_ORDER fields of RX_CPPI_CNTL 173
QUEUEn_RXDMA_CP 167
QUEUEn_RXDMA_HDP 166
QUEUEn_TEAR_DWN fields of
RX_QUEUE_TEAR_DOWN 172
QUEUEn_TEAR_DWN fields of
TX_QUEUE_TEAR_DOWN 168
QUEUEn_TXDMA_CP 165
QUEUEn_TXDMA_HDP 164
queue n receive DMA completion pointer register 167
queue n receive DMA head descriptor pointer register
166
queue n transmit DMA completion pointer register 165
queue n transmit DMA head descriptor pointer register
164
Queue Pointer fields of TX_QUEUE_CNTLn 174
queue teardown bits for message reception 172
queue teardown bits for message transmission 168
queue transmission order 54
receiver enable bit 126
receive/transmit lockout field for port n 207
register configuration offset field for LSUn 156
register introduction 102
reinitialization process field for port n 236
related documentation 14
reordering of outbound packets 75
reporting thresholds for port n errors
broken link case 229
degraded link case 229
request packets
Ftypes and Ttypes 25
in SRIO operation sequence 22
requirements for external devices 20
reset and power down 70
CPPI module 59
enable and enable status registers 71
Load/Store module 43
software shutdown details 74
R
reset interrupt enable field for ports 232
reset interrupt status field for ports 232
reset option CSR for port n 235
RESPONSE_VALID field of SPn_LM_RESP 201
response packets
RapidIO
architectural hierarchy 16
external device requirements 20
features 16
Ftypes and Ttypes 25
features supported in SRIO peripheral 19
interconnect architecture 18
standards 20
RapidIO DEVICEID1 register 121
RapidIO DEVICEID2 register 122
RATE fields
in SRIO operation sequence 22
responses to CPPI (message) transmissions 58
response time-out error at LSU or TXU
reporting enable field 213
status field 211
response timer
effect on data rate 30
in direct I/O reception 42
in Load/Store module data flow diagram 39
in message reception 47
RATE field of SERDES_CFGRXn_CNTL 125
RATE field of SERDES_CFGTXn_CNTL 128
rate select field for SERDES receiver 126
rate select field for SERDES transmitter 128
RCVD_PKT_NOT_ACCPT field of SPn_ERR_DET 219
RCVD_PKT_OVER_276B field of SPn_ERR_DET 219
in message transmission 59
RETRANSMIT_SUPPRESS field of PE_FEAT 186
retry_count field of TX buffer descriptor 52
RETRY response in message passing 43
REV field of PID 111
RCVD_PKT_WITH_BAD_CRC field of SPn_ERR_DET
219
RCVED_PKT_NOT_ACCPT_EN field of SPn_RATE_EN
221
RCVED_PKT_OVER_276B_EN field of SPn_RATE_EN
221
RCVED_PKT_WITH_BAD_CRC_EN field of
SPn_RATE_EN 221
READ field of DEST_OP 189
READ field of SRC_OP 188
RIOCLK and RIOCLK signals 25
RIORXn and RIORXn signals 25
RIOTXn and RIOTXn signals 25
round-robin access to TX buffer descriptor queues 54
routing interrupt conditions to interrupt destinations 93
routing registers
for CPPI interrupt conditions 145, 146
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SRIO Registers
SERDES macros
configuration example 35
description 28
for doorbell interrupt conditions 144
for error, reset, and special event (port) interrupt
conditions 149
for LSU interrupt conditions 147
RST_CS field of SP_IP_MODE 231
RST_EN field of SP_IP_MODE 231
rules for CPPI data traffic 43
RX_CP field of QUEUEn_RXDMA_CP 167
RX_CPPI_CNTL 173
RX_CPPI_ICCR 135
RX_CPPI_ICRR 145
RX_CPPI_ICRR2 145
RX_CPPI_ICSR 134
RX_CPPI_SECURITY_ENABLE field of ERR_EN 212
RX_CPPI_SECURITY field of ERR_DET 210
RX_HDP field of QUEUEn_RXDMA_HDP 166
RX_IO_DMA_ACCESS field of ERR_DET 210
RX_IO_SECURITY_ENABLE field of ERR_EN 212
RX_QUEUE_TEAR_DOWN 172
RX buffer descriptor fields 47
RX buffer descriptor link-list figure 61
RX buffer descriptor queue teardown 50
RX CPPI security error
enable bits 115
in SRIO component block diagram 26
in SRIO peripheral block diagram 21
PLL enabling 28
receiver enabling 30
transmitter enabling 33
SERDES receive channel configuration registers 125
SERDES transmit channel configuration registers 128
serialization/deserialization (SERDES) 21
serial port IP prescaler register 233
Serial RapidIO peripheral. See SRIO peripheral 19
shared buffers
in direct I/O RX operation 42
in direct I/O TX READ transaction 41
in direct I/O TX WRITE transaction 40
in Load/Store module data flow diagram 39
in message passing 43
in SRIO component block diagram 26
SILENCE_TIMER field of SPn_SILENCE_TIMER 238
silent state period for port n 238
single-/multi-segment selection field for message
reception 180
single port with 1x or 4x operation 76
small common transport system base device ID 193
SOFT_REC field of SPn_CTL_INDEP 236
SOFT field of PCR 112
reporting enable field 213
status bit 211
RX I/O DMA access error
reporting enable field 213
status field 211
RX shared buffer
in direct I/O RX operation 42
in direct I/O TX READ transaction 41
in SRIO component block diagram 26
RXU
soft stop bit 112
soft stop emulation mode 75
software memory sleep override bit 113
software requirements for message passing 60
software shutdown details 74
enable bit 119
enable status bits 117, 120
handling of unavailable outbound credit 76
in SRIO component block diagram 26
RXU_MAP registers
sop field of RX buffer descriptor 47
sop field of TX buffer descriptor 52
source address field for LSUn 157
source ID associated with logical/transport error 216
description 177
introduction 45
source ID check or ignore field for message reception
180
SOURCEID field of ID_CAPT 216
SOURCEID field of RXU_MAP_Ln 178
source operations CAR 188
SP_GEN_CTL 199
SP_IP_DISCOVERY_TIMER 230
SP_IP_IPW_IN_CAPTn 234
SP_IP_MODE 231
SP_LT_CTL 197
SP_MB_HEAD 196
SP_MODE field of SP_IP_MODE 231
SP_RT_CTL 198
SPn_ACKID_STAT 202
SPn_CS_TX 240
S
security error reporting enable bit for MAU 213
security error reporting enable bit for RXU 213
security error status bit for MAU 211
security error status bit for RXU 211
SEGMENT_MAPPING field of RXU_MAP_Hn 178
segmentation of outbound direct I/O requests 42
SELF_RST field of SP_IP_MODE 231
self reset interrupt enable field for ports 231
SEND_DBG_PKT field of SPn_CTL_INDEP 236
send debug packet field for port n 237
SERDES_CFGn_CNTL 130
SERDES_CFGRXn_CNTL 125
SPn_CTL 206
SERDES_CFGTXn_CNTL 128
SPn_CTL_INDEP 236
SERDES macro configuration register 130
SPn_ERR_ATTR_CAPT_DBG0 223
252
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SRIO Registers
SWING field of SERDES_CFGTXn_CNTL 128
SPn_ERR_CAPT_DBG1 224
SPn_ERR_CAPT_DBG2 225
SPn_ERR_CAPT_DBG3 226
SPn_ERR_CAPT_DBG4 227
SPn_ERR_DET 219
switch capability field 186
SWITCH field of PE_FEAT 186
SWRITE packet Ftype and Ttype 25
symbol alignment field 126
SPn_ERR_RATE 228
T
SPn_ERR_STAT 203
SPn_ERR_THRESH 229
SPn_LM_REQ 200
target IDs. See destination IDs 218
teardown_complete field of RX buffer descriptor 47
teardown_complete field of TX buffer descriptor 52
teardown bits for RX queues 172
teardown bits for TX queues 168
teardown of RX buffer descriptor queues 50
teardown of TX buffer descriptor queues 59
TERM field of SERDES_CFGRXn_CNTL 125
test and swap. See Atomic operations 25
TGT_ID_DIS field of SP_IP_MODE 231
thresholds
for loss of signal detection (LOS field) 126
for port error rate counter 228
for priority 0, 1, and 2 transmit credit 113
for reporting errors
broken link 229
degraded link 229
maximum retry error at port n 237
TIMEOUT_VALUE field of SP_LT_CTL 197
TIMEOUT_VALUE field of SP_RT_CTL 198
time-out condition
during direct I/O reception 42
during message-passing RX operation 47
during message-passing TX operation 59
time-out values for ports
link time-out 197
response time-out 198
trademarks 14
TRANS_MODE field of SPn_CTL_INDEP 236
transaction priority field 114
SPn_LM_RESP 201
SPn_MULT_EVNT_CS 239
SPn_RATE_EN 221
SPn_RST_OPT 235
SPn_SILENCE_TIMER 238
src_id field of RX buffer descriptor 47
SRC_OP 188
SRIO peripheral
component block diagram 26
data flow overview 21
emulation halt behavior 74
initialization example 77
packets 22
packet types 25
peripheral block diagram 21
pins/differential signals 25
RapidIO features not supported 20
RapidIO features supported 19
reset and power down 70
ssize field of TX buffer descriptor 52
status bits for recording interrupt conditions 86
status registers
for CPPI interrupt conditions 134, 136
for doorbell interrupt conditions 132
for error, reset, and special event (port) interrupt
conditions 142
for LSU interrupt conditions 138
STOP_PORT_FLD_ENC_ENABLE field of SPn_CTL
206
stop on output failure at port n 207
stop receiving messages and reclaim buffers (RX
teardown) 50
stop transmitting messages and clear buffers (TX
teardown) 59
store-and-forward mode option for port n 236
STREAM_WRITE field of DEST_OP 189
STREAM_WRITE field of SRC_OP 188
streaming-write packet example 23
streaming-write support for destination device 189
streaming-write support for source device 188
stype0 and stype1 control symbols 24
stype0 control symbol field for port n 240
stype1 control symbol field for port n 240
STYPE_0 field of SPn_CS_TX 240
transaction type associated with logical/transport error
217
transfer mode field for port n 236
transfer type field for flow control destination IDs 181
transmission error count for port n 228
transmission error recovery software option for port n
236
transmission flow control 65
transmit CPPI interrupt condition clear register 137
transmit CPPI interrupt condition routing registers 146
transmit CPPI interrupt condition status register 136
transmit CPPI supported flow mask registers 169
transmit CPPI weighted round robin control registers
174
transmit credit threshold for priorities 0 through 2 113
transmit data rate select field 128
transmit FIFO bypass field for ports 231
transmit flow control enable field for port n 236
transmit queue teardown register 168
STYPE_1 field of SPn_CS_TX 240
suppression support field 186
SW_MEM_SLEEP_OVERRIDE field of PER_SET_CNTL
113
transmit/receive lockout field for port n 207
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SRIO Registers
transmitter enabling for SERDES macro
introduction 33
transmitter enable bit 129
transport error handling and logging 83
transport layer
content in SRIO data stream 22
definition 16
status field 219
unexpected ackID in packet at port n
rate counting enable field 222
status field 220
unexpected acknowledge control symbol at port n
rate counting enable field 222
status field 220
unexpected control symbol at port n
rate counting enable field 222
status field 220
in Load/Store module data flow diagram 39
transport type field for message reception 179
TRA. See transport layer 23
unexpected packet at port n
rate counting enable field 222
status field 220
uninitialized status bit for ports 205
unrecoverable error status bit for ports 204
UNSOLICITED_ACK_CNTL_SYM_EN field of
SPn_RATE_EN 221
UNSOLICITED_ACK_CNTL_SYM field of
SPn_ERR_DET 219
TT field of FLOW_CNTLn 181
tt field of RX buffer descriptor 47
TT field of RXU_MAP_Hn 178
tt field of TX buffer descriptor 52
TTYPE field of CTRL_CAPT 217
Ttypes of SRIO packets 25
TX_CP field of QUEUEn_TXDMA_CP 165
TX_CPPI_FLOW_MASKS[0–7] 169
TX_CPPI_ICCR 137
UNSOLICITED_RESP_ENABLE field of ERR_EN 212
UNSOLICITED_RSPNS field of ERR_DET 210
unsolicited response at LSU or TXU
reporting enable field 213
status field 211
UNSUPPORTED_TRANS_ENABLE field of ERR_EN
212
UNSUPPORTED_TRANS field of ERR_DET 210
unsupported transaction at MAU
reporting enable field 213
status field 211
User Defined Interface. See UDI 40
TX_CPPI_ICRR 146
TX_CPPI_ICRR2 146
TX_CPPI_ICSR 136
TX_FIFO_BYPASS field of SP_IP_MODE 231
TX_FLW field of SPn_CTL_INDEP 236
TX_HDP field of QUEUEn_TXDMA_HDP 164
TX_PRIn_WM fields of PER_SET_CNTL 113
TX_QUEUE_CNTL[0–3] 174
TX_QUEUE_TEAR_DOWN 168
TX buffer descriptor fields 52
TX buffer descriptor link-list figure 62
TX buffer descriptor queue teardown 59
TX buffers, credit, and packet re-ordering 75
TX shared buffer
V
valid information field for port n error capture 223
in direct I/O TX WRITE transaction 40
in SRIO component block diagram 26
TXU
W
weighted round-robin access to TX buffer descriptor
queues 54
enable bit 119
weighted round robin control registers 174
width field for port n 206
width override field for port n 207
WRITE_WITH_RESP field of DEST_OP 189
WRITE_WITH_RESP field of SRC_OP 188
WRITE field of DEST_OP 189
enable status bits 117, 120
handling of unavailable outbound credit 76
in SRIO component block diagram 26
type field for port n 208
TYPE field of PID 111
type of error field for port n error capture 223
type of information field for port n error capture 223
WRITE field of SRC_OP 188
write support for destination device 189
write support for source device 188
WRITE transactions during direct I/O transmission
description 40
U
UDI
definition 40
in Load/Store module data flow diagram 39
in SRIO component block diagram 26
UDI buffering setup field 114
unacknowledged ackID status field 202
unavailable outbound credit 76
undefined Ftypes 25
non-posted 41
posted 41
write-with-response support for destination device 189
write-with-response support for source device 188
X
XAMSB field of LSUn_REG4 159
XAMSBS field of ADDR_CAPT 215
unexpected ackID in control symbol at port n
rate counting enable field 221
254
Index
SPRUE13A–September 2006
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SRIO Registers
Xoff 65
Xon 65
SPRUE13A–September 2006
Index
255
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