TMS320DM646x DMSoC
Asynchronous External Memory Interface
(EMIF)
User's Guide
Literature Number: SPRUEQ7C
February 2010
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Preface ....................................................................................................................................... 6
1
Introduction ........................................................................................................................ 8
1.1
1.2
1.3
Purpose of the Peripheral .............................................................................................. 8
Features .................................................................................................................. 8
Functional Block Diagram .............................................................................................. 9
2
Architecture ........................................................................................................................ 9
2.1
2.2
2.3
2.4
2.5
Clock Control ............................................................................................................. 9
EMIF Requests .......................................................................................................... 9
Signal Descriptions .................................................................................................... 10
Pin Multiplexing ........................................................................................................ 10
Asynchronous Controller and Interface ............................................................................. 10
3
4
Use Cases ........................................................................................................................ 30
3.1
Interfacing to Asynchronous SRAM (ASRAM) ..................................................................... 30
Interfacing to NAND Flash ............................................................................................ 39
3.2
Registers .......................................................................................................................... 48
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Revision Code and Status Register (RCSR) ....................................................................... 49
Asynchronous Wait Cycle Configuration Register (AWCCR) .................................................... 50
Asynchronous n Configuration Registers (A1CR-A4CR) ......................................................... 52
EMIF Interrupt Raw Register (EIRR) ................................................................................ 53
EMIF Interrupt Mask Register (EIMR) ............................................................................... 54
EMIF Interrupt Mask Set Register (EIMSR) ........................................................................ 56
EMIF Interrupt Mask Clear Register (EIMCR) ..................................................................... 58
NAND Flash Control Register (NANDFCR) ........................................................................ 60
NAND Flash Status Register (NANDFSR) ......................................................................... 61
4.10 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) ................................................... 61
Appendix A Revision History ...................................................................................................... 63
3
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Table of Contents
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List of Figures
EMIF Functional Block Diagram ..........................................................................................
1
2
EMIF Asynchronous Interface ........................................................................................... 11
EMIF to 8-bit and 16-bit Memory Interfaces ........................................................................... 11
Timing Waveform of an Asynchronous Read Cycle in Normal Mode .............................................. 15
Timing Waveform of an Asynchronous Write Cycle in Normal Mode .............................................. 17
Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode....................................... 19
Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode....................................... 21
EMIF to NAND Flash Interface .......................................................................................... 23
ECC Value for 8-Bit NAND Flash ....................................................................................... 25
EMIF to 16-Bit Multiplexed HPI16 Interface............................................................................ 26
Connecting the EMIF to the TC55V16100FT-12 ...................................................................... 30
Timing Waveform of an ASRAM Read ................................................................................ 32
Timing Waveform of an ASRAM Write ................................................................................. 33
Timing Waveform of an ASRAM Read with PCB Delays ............................................................ 35
Timing Waveform of an ASRAM Write with PCB Delays ............................................................ 36
Timing Waveform of a NAND Flash Read ............................................................................ 41
Timing Waveform of a NAND Flash Command Write ............................................................... 43
Timing Waveform of a NAND Flash Address Write .................................................................. 43
Timing Waveform of a NAND Flash Data Write ...................................................................... 44
Revision Code and Status Register (RCSR) .......................................................................... 49
Asynchronous Wait Cycle Configuration Register (AWCCR)........................................................ 50
Asynchronous n Configuration Register (ACFGn) .................................................................... 52
EMIF Interrupt Raw Register (EIRR).................................................................................... 53
EMIF Interrupt Mask Register (EIMR) .................................................................................. 54
EMIF Interrupt Mask Set Register (EIMSR)............................................................................ 56
EMIF Interrupt Mask Clear Register (EIMCR) ......................................................................... 58
NAND Flash Control Register (NANDFCR)............................................................................ 60
NAND Flash Status Register (NANDFSR) ............................................................................. 61
NAND Flash n ECC Register (NANDECCn)........................................................................... 62
3
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5
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7
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9
10
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12
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17
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28
29
4
List of Figures
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List of Tables
1
EMIF Pins .................................................................................................................. 10
Behavior of EM_CS Signal Between Normal Mode and Select Strobe Mode..................................... 10
Description of the Asynchronous Configuration Register (ACFGn)................................................. 12
Description of the Asynchronous Wait Cycle Configuration Register (AWCCR).................................. 13
Description of the EMIF Interrupt Mask Set Register (EIMSR)...................................................... 13
Description of the EMIF Interrupt Mast Clear Register (EIMCR).................................................... 13
Asynchronous Read Operation in Normal Mode ...................................................................... 14
Asynchronous Write Operation in Normal Mode ...................................................................... 16
Asynchronous Read Operation in Select Strobe Mode .............................................................. 18
Asynchronous Write Operation in Select Strobe Mode............................................................... 20
Description of the NAND Flash Control Register (NANDFCR)...................................................... 22
Configuration For NAND Flash ......................................................................................... 22
EMIF Interrupt.............................................................................................................. 28
Interrupt Monitor and Control Bit Fields ................................................................................ 28
EMIF Input Timing Requirements ....................................................................................... 31
ASRAM Output Timing Characteristics................................................................................. 31
ASRAM Input Timing Requirement for a Read........................................................................ 31
ASRAM Input Timing Requirements for a Write ...................................................................... 32
ASRAM Timing Requirements With PCB Delays ..................................................................... 34
EMIF Timing Requirements for TC5516100FT-12 Example ........................................................ 37
ASRAM Timing Requirements for TC5516100FT-12 Example ..................................................... 37
Measured PCB Delays for TC5516100FT-12 Example .............................................................. 37
Configuring A2CR for TC5516100FT-12 Example.................................................................... 39
Recommended Margins .................................................................................................. 39
EMIF Read Timing Requirements....................................................................................... 40
NAND Flash Read Timing Requirements .............................................................................. 40
NAND Flash Write Timing Requirements ............................................................................. 42
EMIF Timing Requirements for HY27UA081G1M Example ......................................................... 45
NAND Flash Timing Requirements for HY27UA081G1M Example ................................................ 45
Configuring A1CR for HY27UA081G1M Example .................................................................... 47
Configuring NANDFCR for HY27UA081G1M Example .............................................................. 47
External Memory Interface (EMIF) Registers .......................................................................... 48
Revision Code and Status Register (RCSR) Field Descriptions .................................................... 49
Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions ................................. 50
Asynchronous n Configuration Register (ACFGn) Field Descriptions .............................................. 52
EMIF Interrupt Raw Register (EIRR) Field Descriptions ............................................................. 53
EMIF Interrupt Mask Register (EIMR) Field Descriptions............................................................ 54
EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions ..................................................... 56
EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions................................................... 58
NAND Flash Control Register (NANDFCR) Field Descriptions ..................................................... 60
NAND Flash Status Register (NANDFSR) Field Descriptions....................................................... 61
NAND Flash n ECC Register (NANDECCn) Field Descriptions .................................................... 62
Document Revision History .............................................................................................. 63
2
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5
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Preface
SPRUEQ7C–February 2010
Read This First
About This Manual
This document describes the asynchronous external memory interface (EMIF) in the TMS320DM646x
Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external
devices.
Notational Conventions
This document uses the following conventions.
•
Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
•
Registers in this document are shown in figures and described in tables.
–
Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
–
Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copies
of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the
The current documentation that describes the DM646x DMSoC, related peripherals, and other technical
processor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).
subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem is
designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is
responsible for configuration and control of the device; including the DSP subsystem and a majority
of the peripherals and external memories.
and briefly describes the peripherals available on the TMS320DM646x Digital Media
System-on-Chip (DMSoC).
Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in the
devices that is identical is not included.
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital
signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation
comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of
the C64x DSP with added functionality and an expanded instruction set.
6
Preface
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Related Documentation From Texas Instruments
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
7
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Read This First
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User's Guide
SPRUEQ7C–February 2010
Asynchronous External Memory Interface (EMIF)
1
Introduction
This document describes the operation of the asynchronous external memory interface (EMIF) in the
TMS320DM646x Digital Media System-on-Chip (DMSoC).
1.1 Purpose of the Peripheral
The purpose of this EMIF is to provide a means to connect to a variety of external devices including:
•
•
•
NAND Flash
Asynchronous devices including Flash and SRAM
Host processor interfaces such as the host port interface (HPI) on a Texas Instruments Digital Signal
Processor (DSP)
The most common use for the EMIF is to interface with both flash devices and SRAM devices. The
Example Configuration section contains examples of operating the EMIF in this configuration.
1.2 Features
The EMIF includes many features to enhance the ease and flexibility of connecting to external
asynchronous devices. The EMIF features includes support for:
•
•
•
•
•
•
•
•
4 addressable chip select spaces of up to 32MB each
8-bit and 16-bit data bus widths
Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
Select strobe mode
Extended Wait mode
NAND Flash ECC generation
Connecting as a host to a TI DSP HPI interface
Data bus parking
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Architecture
1.3 Functional Block Diagram
Figure 1 illustrates the connections between the EMIF and its internal requesters, along with the external
EMIF pins. Section 2.2 contains a description of the entities internal to the device that can send requests
to the EMIF, along with their prioritization. Section 2.3 describes the EMIF's external pins and summarizes
their purpose when interfacing with SDRAM and asynchronous devices.
Figure 1. EMIF Functional Block Diagram
EMIF
VICP
EM_CS[5:2]
EM_OE
EM_RW
DSP
ARM
EM_WAIT[5:2]
SCR
EM_WE
EM_BA[1:0]
EM_D[15:0]
EM_A[22:0]
EDMA3
Master peripherals
2
Architecture
This section provides details about the architecture and operation of the EMIF.
2.1 Clock Control
The EMIF's internal clock is sourced from the SYSCLK3 clock domain of PLL controller 0 and cannot be
sourced directly from an external input clock. The frequency of the SYSCLK3 clock domain is the PLL0
frequency divided by 4. Changes to the frequency of the input clock to PLL controller 0 and to the PLL
controller 0 multiplier values alters the operating frequency of the EMIF. See the TMS320DM646x DMSoC
controller.
2.2 EMIF Requests
Four different sources within the device can make requests to the EMIF. These requests consist of
accesses to asynchronous memory and EMIF memory-mapped registers. Because the EMIF can process
only one request at a time, a high performance switched central resource (SCR) exists to provide
prioritized requests from the different sources to the EMIF. Each requester has a programmable priority
value that may be configured in the System Module MSTPRI0 register or in the EDMACC QUEPRI
register. See the device-specific data manual for more information.
If a request is submitted from two or more sources simultaneously, the SCR will forward the highest
priority request to the EMIF first. Upon completion of a request, the SCR again evaluates the pending
requests and forwards the highest priority pending request to the EMIF.
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Architecture
2.3 Signal Descriptions
Table 1 describes the function of each of the EMIF pins.
Table 1. EMIF Pins
Pins(s)
I/O
Description
EM_ A[22:0]
O
EMIF address bus. These pins are used in conjunction with the EM_BA pins to form the address that is
sent to the device.
EM_BA[1:0]
EM_CS[5:2]
O
O
EMIF bank address. These pins are used in conjunction with the EM_A pins to form the address that is
sent to the device.
Active-low chip enable pin for asynchronous devices. These pins are meant to be connected to the
chip-select pin of the attached asynchronous device.
EM_D[15:0]
EM_RW
I/O
O
EMIF data bus.
Read/Write select pin. This pin is high for the duration of an asynchronous read access cycle and low
for the duration of an asynchronous write cycle.
EM_OE
O
O
I
Active-low pin enable for asynchronous devices. This pin provides a signal which is active-low during
the strobe period of an asynchronous read access cycle.
EM_WE
Active-low write enable. This pin provides a signal which is active-low during the strobe period of an
asynchronous write access cycle.
EM_WAIT[5:2]
Wait input with programmable polarity. A connected asynchronous device can extend the strobe period
this functionality, the EW bit in the asynchronous configuration register (ACFGn) must be set to 1. In
addition, the WPn bit in the asynchronous wait cycle configuration register (AWCCR) must be
configured to define the polarity of the EM_WAITn pin.
2.4 Pin Multiplexing
The EMIF pins are multiplexed with other peripherals such as PCI, HPI, GPIO, and ATA. See the
device-specific data manual for instructions on how to select the EMIF pins for proper operation.
2.5 Asynchronous Controller and Interface
The EMIF easily interfaces to a variety of asynchronous devices including Flash and ASRAM. It can be
operated in three major modes:
•
•
•
Normal mode
Select Strobe (SS) mode
NAND Flash mode
The behavior of the EM_CS signal is the single difference between Normal mode and Select Strobe mode
and remains active for the duration of the transfer. In Select Strobe mode, the EM_CS signal functions as
a strobe signal, active only during the strobe period of an access.
In NAND Flash mode, the EMIF hardware is able to calculate the error correction code (ECC) for each
512 byte data transfer. In addition to the three modes of operation, the EMIF also provides configurable
cycle timing parameters and an Extended Wait mode that allows the connected device to extend the
strobe period of an access cycle. The following sections describe the features related to interfacing with
external asynchronous devices.
Table 2. Behavior of EM_CS Signal Between Normal Mode and
Select Strobe Mode
Mode
Operation of EM_CS[5:2]
Normal
Active during the entire asynchronous access cycle
Active only during the strobe period of an access cycle
Select Strobe
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Architecture
2.5.1
Interfacing to Asynchronous Memory
Figure 2 shows the EMIF's external pins used in interfacing with an asynchronous device. Of special note
is the connection between the EMIF and the external device's address bus. The EMIF address pin
EM_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when interfacing to a
16-bit or 8-bit asynchronous device, the EM_BA[1] and EM_BA[0] pins provide the least-significant bits of
and the connected device's data and address pins for various programmed data bus widths. The data bus
width may be configured in the asynchronous configuration register (ACFGn).
Figure 2. EMIF Asynchronous Interface
EMIF
EM_CS[5:2]
EM_WE
EM_OE
EM_RW
EM_WAIT[5:2]
EM_D[15:0]
EM_A[22:0]
EM_BA[1:0]
Figure 3. EMIF to 8-bit and 16-bit Memory Interfaces
EMIF
8−bit
asynchronous
memory
EM_D[7:0]
DQ[7:0]
EM_A[21:0]
EM_BA[1:0]
A[23:2]
A[1:0]
a) EMIF to 8-bit memory interface
EMIF
16−bit
asynchronous
memory
EM_D[15:0]
EM_A[21:0]
EM_BA[1]
DQ[15:0]
A[22:1]
A[0]
b) EMIF to 16-bit memory interface
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Architecture
2.5.2
Programmable Asynchronous Parameters
The EMIF allows a high degree of programmability for shaping asynchronous accesses. The
programmable parameters are:
•
Setup: The time between the beginning of a memory cycle (address valid) and the activation of the
output enable or write enable strobe
•
•
Strobe: The time between the activation and deactivation of output enable or write enable strobe.
Hold: The time between the deactivation of output enable or write enable strobe and the end of the
cycle, which may be indicated by an address change or the deactivation of the EM_CS signal.
Separate parameters are provided for read and write cycles. Each parameter is programmed in terms of
EMIF clock cycles.
2.5.3
Configuring the EMIF for Asynchronous Accesses
The operation of the EMIF's asynchronous interface can be configured by programming the appropriate
memory-mapped registers. The reset value and bit position for each register field can be found in
Section 4. The following tables list the programmable register fields and describe the purpose of each
field. These registers should not be programmed while an asynchronous access is in progress. The
transfer following a write to these registers will use the new configuration.
select space has a dedicated ACFGn. This allows each chip select space to be programmed
independently to interface to different asynchronous memory types.
Table 3. Description of the Asynchronous Configuration Register (ACFGn)
Parameter
Description
SS
Select Strobe mode. This bit selects the EMIF's mode of operation in the following way:
•
•
SS = 0 selects Normal mode. EM_CS is active for duration of access.
SS = 1 selects Select Strobe mode. EM_CS acts as a strobe.
EW
Extended Wait mode enable.
•
EW = 0 disables Extended Wait mode
•
EW = 1 enables Extended Wait mode
When set to 1, the EMIF enables its Extended Wait mode in which the strobe width of an access
cycle can be extended in response to the assertion of the EM_WAIT[5:2] pins. The WPn bit in the
asynchronous wait cycle configuration register (AWCCR) controls the polarity of the EM_WAITn pin.
W_SETUP/R_SETUP
W_STROBE/R_STROBE
W_HOLD/R_HOLD
TA
Read/Write setup widths.
These fields define the number of EMIF clock cycles of setup time for the address pins (EM_A and
EM_BA) and asynchronous chip enable (EM_CS) before the read strobe pin (READ_OE) or write
strobe pin (WRITE_WE) falls, minus 1 cycle. For writes, the W_SETUP field also defines the setup
time for the data pins (EM_D). Refer to the datasheet of the external asynchronous device to
determine the appropriate setting for this field.
Read/Write strobe widths.
These fields define the number of EMIF clock cycles between the falling and rising of the read strobe
pin (READ_OE) or write strobe pin (WRITE_WE), minus 1 cycle. If Extended Wait mode is enabled
by setting the EW bit in the asynchronous configuration register (ACFGn), these fields must be set to
a value greater than zero. Refer to the datasheet of the external asynchronous device to determine
the appropriate setting for this field.
Read/Write hold widths.
These fields define the number of EMIF clock cycles of hold time for the address pins (EM_A and
EM_BA) and asynchronous chip enable (EM_CS) after the read strobe pin (READ_OE) or write
strobe pin (WRITE_WE) rises, minus 1 cycle. For writes, the W_HOLD field also defines the hold
time for the data pins (EM_D). Refer to the datasheet of the external asynchronous device to
determine the appropriate setting for this field.
Minimum turnaround time.
This field defines the minimum number of EMIF clock cycles between the end of one asynchronous
access and the start of another, minus 1 cycle. This delay is not incurred when a read is followed by
a read, or a write is followed by a write to the same chip select space. The purpose of this feature is
to avoid contention on the bus. Refer to the datasheet of the external asynchronous device to
determine the appropriate setting for this field.
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Architecture
Table 3. Description of the Asynchronous Configuration Register (ACFGn) (continued)
Parameter
ASIZE
Description
Asynchronous Device Bus Width.
This field determines the data bus width of the asynchronous interface in the following way:
•
•
ASIZE = 0 selects an 8-bit bus
ASIZE = 1 selects a 16-bit bus
The configuration of ASIZE determines the function of the EM_A and EM_BA pins as described in
Section 2.5.1. This field also determines the number of external accesses required to fulfill a request
would require four external access when ASIZE = 0h. Refer to the datasheet of the external
asynchronous device to determine the appropriate setting for this field.
Table 4. Description of the Asynchronous Wait Cycle Configuration Register (AWCCR)
Parameter
Description
WPn
WAIT Polarity.
•
WPn = 0 selects active-low polarity
•
WPn = 1 selects active-high polarity
When set to 1, the EMIF will wait if the EM_WAITn pin is high. When cleared to 0, the EMIF will wait if the
EM_WAITn pin is low. The EMIF must have the Extended Wait mode enabled (EW bit in the asynchronous
configuration register (ACFGn) is set to 1) for the EM_WAITn pin to affect the width of the strobe period.
MEWC
Maximum Extended Wait Cycles.
This field configures the number of EMIF clock cycles the EMIF will wait for the EM_WAITn pin to be deactivated
during the strobe period of an access cycle. The maximum number of EMIF clock cycles the EMIF will wait is
determined by the following formula:
Maximum Extended Wait Cycles = (MEWC + 1) × 16
If the EM_WAITn pin is not deactivated within the time specified by this field, the EMIF resumes the access cycle,
registering whatever data is on the bus and preceding to the hold period of the access cycle. This situation is
referred to as an asynchronous timeout. An asynchronous timeout generates an interrupt if it has been enabled in
the EMIF interrupt mask set register (EIMSR). Refer to Section 2.5.11 for more information about the EMIF
interrupts.
Table 5. Description of the EMIF Interrupt Mask Set Register (EIMSR)
Parameter
Description
WRMSETn
Wait Rise Mask Set.
Writing a 1 enables an interrupt to be generated when a rising edge on EM_WAITn occurs.
ATMSET
Asynchronous Timeout Mask Set.
Writing a 1 to this bit enables an interrupt to be generated when an asynchronous timeout occurs.
Table 6. Description of the EMIF Interrupt Mast Clear Register (EIMCR)
Parameter
Description
WRMCLRn
Wait Rise Mask Clear.
Writing a 1 to this bit disables the interrupt, clearing the WRMSETn bit in the EMIF interrupt mask set register
(EIMSR).
ATMCLR
Asynchronous Timeout Mask Clear.
Writing a 1 to this bit disables the interrupt, clearing the ATMSET bit in the EMIF interrupt mask set register
(EIMSR).
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Architecture
2.5.4
Read and Write Operations in Normal Mode
Normal mode is the asynchronous interface's default mode of operation. The Normal mode is selected
when the SS bit in the asynchronous configuration register (ACFGn) is cleared to 0. In this mode, the
EM_CS signal operates as a chip enable signal, active throughout the duration of the memory access.
2.5.4.1
Asynchronous Read Operations (Normal Mode)
An asynchronous read is performed when any of the requesters mentioned in Section 2.2 request a read
from the attached asynchronous memory. In the event that the read request cannot be serviced by a
single access cycle to the external device, multiple access cycles will be performed by the EMIF until the
entire request is fulfilled. The details of an asynchronous read operation in Normal mode are described in
NOTE: During the entirety of an asynchronous read operation, the WRITE_WE and EM_RW pins
are driven high.
Table 7. Asynchronous Read Operation in Normal Mode
Time Interval
Pin Activity in WE Strobe Mode
Turnaround
period
Once the EMIF receives a read request, the EMIF waits for the programmed number of turn-around cycles
before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA
field of the asynchronous configuration register (ACFGn). There are two exceptions to this rule:
•
If the current read operation was directly proceeded by another read operation to the same CS space, no
turnaround cycles are inserted.
•
If the current read operation was not directly proceeded by a read operation to the same CS space and the
TA field has been cleared to 0, one turn-around cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.
Start of setup
period
At the beginning of the setup period:
•
The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values
in ACFGn.
•
•
The address pins EM_A and EM_BA become valid
EM_CS falls to enable the external device (if not already low from a previous operation)
Start of strobe
period
At the beginning of the strobe period
READ_OE falls
At the beginning of the hold period:
•
Start of hold
period
•
•
READ_OE rises
The EMIF samples the data on the EM_D bus.
End of hold
period
At the end of the hold period:
•
The address pins EM_A and EM_BA become invalid
•
EM_CS rises (if no more operations are required to complete the current request)
The EMIF will be required to issue additional read operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turn-round cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIF
instead enters directly into the turnaround period for the pending read or write operation.
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Architecture
Figure 4. Timing Waveform of an Asynchronous Read Cycle in Normal Mode
Strobe
Setup
2
Hold
2
3
Internal clock
EM_CS[5:2]
EM_A/EM_BA
EM_D
Address
Data
EM_OE
EM_WE
EM_RW
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Architecture
2.5.4.2
Asynchronous Write Operations (Normal Mode)
An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write
to asynchronous memory. In the event that the write request cannot be serviced by a single access cycle
to the external device, multiple access cycles will be performed by the EMIF until the entire request is
fulfilled. The details of an asynchronous write operation in Normal mode are described in Table 8 and an
NOTE: During the entirety of an asynchronous write operation, the EM_OE pin is driven high.
Table 8. Asynchronous Write Operation in Normal Mode
Time Interval
Pin Activity in WE Strobe Mode
Turnaround
period
Once the EMIF receives a write request, the EMIF waits for the programmed number of turn-around cycles
before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA
field of the asynchronous configuration register (ACFGn). There are two exceptions to this rule:
•
If the current write operation was directly proceeded by another write operation to the same CS space, no
turnaround cycles are inserted.
•
If the current write operation was not directly proceeded by a write operation to the same CS space and the
TA field has been cleared to 0, one turnaround cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.
Start of setup
period
At the beginning of the setup period:
•
The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values
in ACFGn.
•
•
•
The address pins EM_A and EM_BA and the data pins EM_D become valid.
The EM_RW pin falls to indicate a write (if not already low from a previous operation).
EM_CS falls to enable the external device (if not already low from a previous operation).
Start of strobe
period
At the beginning of the strobe period of a write operation:
EM_WE falls
At the beginning of the hold period
EM_WE rises
At the end of the hold period:
•
Start of hold
period
•
End of hold
period
•
•
•
•
The address pins EM_A and EM_BA become invalid
The data pins become invalid
The EM_RW pin rises (if no more operations are required to complete the current request)
EM_CS rises (if no more operations are required to complete the current request)
The EMIF may be required to issue additional write operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the
turnaround period for the pending read or write operation.
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Architecture
Figure 5. Timing Waveform of an Asynchronous Write Cycle in Normal Mode
Strobe
Setup
2
Hold
2
3
Internal clock
EM_CS[5:2]
EM_A/EM_BA
EM_D
Address
Data
EM_OE
EM_WE
EM_RW
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Architecture
2.5.5
Read and Write Operations in Select Strobe Mode
Select Strobe mode is the EMIF's second mode of operation. The SS mode is selected when the SS bit in
the asynchronous configuration register (ACFGn) is set to 1. In this mode, the EM_CS pin functions as a
strobe signal and is therefore only active during the strobe period of an access cycle.
2.5.5.1
Asynchronous Read Operations (Select Strobe Mode)
An asynchronous read is performed when any of the requesters mentioned in Section 2.2 request a read
from the attached asynchronous memory. In the event that the read request cannot be serviced by a
single access cycle to the external device, multiple access cycles will be performed by the EMIF until the
entire request is fulfilled. The details of an asynchronous read operation in Select Strobe mode are
NOTE: During the entirety of an asynchronous read operation, the EM_WE and EM_RW pins are
driven high.
Table 9. Asynchronous Read Operation in Select Strobe Mode
Time Interval
Pin Activity in Select Strobe Mode
Turnaround
period
Once the EMIF receives a read request, the EMIF waits for the programmed number of turnaround cycles before
proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA field of
the asynchronous configuration register (ACFGn). There are two exceptions to this rule:
•
If the current read operation was directly proceeded by another read operation to the same CS space, no
turnaround cycles are inserted.
•
If the current read operation was not directly proceeded by a read operation to the same CS space and the
TA field has been cleared to 0, one turnaround cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.
Start of setup
period
At the beginning of the setup period:
•
•
The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values
in ACFGn.
The address pins EM_A and EM_BA become valid.
Start of strobe
period
At the beginning of the strobe period:
EM_CS and EM_OE fall at the start of the strobe period
At the beginning of the hold period:
•
Start of hold
period
•
•
EM_CS and EM_OE rise
The EMIF samples the data on the EM_D bus
End of hold
period
At the end of the hold period:
The address pins EM_A and EM_BA become invalid
•
The EMIF may be required to issue additional read operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the
turnaround period for the pending read or write operation.
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Architecture
Figure 6. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode
Strobe
3
Setup
2
Hold
2
Internal clock
EM_CS[5:2]
EM_A/EM_BA
EM_D
Address
Data
EM_OE
EM_WE
EM_RW
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Architecture
2.5.5.2
Asynchronous Write Operations (Select Strobe Mode)
An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write
to memory in the asynchronous bank of the EMIF. In the event that the write request cannot be serviced
by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until
the entire request is fulfilled. The details of an asynchronous write operation in Select Strobe mode are
described in Table 10 and an example timing diagram of a basic write operation is shown in Figure 7.
NOTE: During the entirety of an asynchronous write operation, the EM_OE pin is driven high.
Table 10. Asynchronous Write Operation in Select Strobe Mode
Time Interval
Pin Activity in Select Strobe Mode
Turnaround
period
Once the EMIF receives a write request, the EMIF waits for the programmed number of turnaround cycles
before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA
field of the asynchronous configuration register (ACFGn). There are two exceptions to this rule:
•
If the current write operation was directly proceeded by another write operation to the same CS space, no
turnaround cycles are inserted.
•
If the current write operation was directly proceeded by a write operation to the same CS space and the TA
field has been cleared to 0, one turnaround cycle will be inserted.
After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.
Start of setup
period
At the beginning of the setup period:
•
The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values
in ACFGn.
•
•
The address pins EM_A and EM_BA and the data pins EM_D become valid.
The EM_RW pin falls to indicate a write (if not already low from a previous operation).
Start of strobe
period
At the beginning of the strobe period:
EM_CS and EM_WE fall
At the beginning of the hold period:
EM_CS and EM_WE rise
At the end of the hold period:
•
Start of hold
period
•
End of hold
period
•
•
•
The address pins EM_A and EM_BA become invalid
The data pins become invalid
The EM_RW pin rises (if no more operations are required to complete the current request)
The EMIF may be required to issue additional write operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another
operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIF returns to its previous state unless another
asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the
turn-around period for the pending read or write operation.
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Architecture
Figure 7. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode
Strobe
Setup
2
Hold
2
3
Internal clock
EM_CS[5:2]
EM_A/EM_BA
EM_D
Address
Data
EM_OE
EM_WE
EM_RW
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Architecture
2.5.6
NAND Flash Mode
NAND Flash mode is the EMIF's third mode of operation. Each chip select space may be placed in NAND
Flash mode individually by setting the appropriate CSnNAND bit in the NAND Flash control register
When a chip select space is configured to operate in NAND Flash mode, the EMIF hardware can calculate
the error correction code (ECC) for each 512 byte data transfer to that chip select space. The EMIF
hardware will not generate the NAND access cycle, which includes the command, address, and data
phases, necessary to complete a transfer to NAND Flash. All NAND Flash operations can be divided into
single asynchronous cycles and with the help of software, the EMIF can execute a complete NAND
access cycle.
Table 11. Description of the NAND Flash Control Register (NANDFCR)
Parameter
Description
CS5ECC
NAND Flash ECC state for chip select 5.
•
•
Set to 1 to start an ECC calculation.
Cleared to 0 when NAND Flash 4 ECC register (NANDF4ECC) is read.
CS4ECC
CS3ECC
CS2ECC
NAND Flash ECC state for chip select 4.
•
•
Set to 1 to start an ECC calculation.
Cleared to 0 when NAND Flash 3 ECC register (NANDF3ECC) is read.
NAND Flash ECC state for chip select 3.
•
•
Set to 1 to start an ECC calculation.
Cleared to 0 when NAND Flash 2 ECC register (NANDF2ECC) is read.
NAND Flash ECC state for chip select 2.
•
•
Set to 1 to start an ECC calculation.
Cleared to 0 when NAND Flash 1 ECC register (NANDF1ECC) is read.
CS5NAND
CS4NAND
CS3NAND
CS2NAND
NAND Flash mode for chip select 5.
Set to 1 to enable NAND Flash mode.
NAND Flash mode for chip select 4.
Set to 1 to enable NAND Flash mode.
NAND Flash mode for chip select 3.
Set to 1 to enable NAND Flash mode.
NAND Flash mode for chip select 2.
Set to 1 to enable NAND Flash mode.
•
•
•
•
2.5.6.1
Configuring for NAND Flash Mode
Similar to the asynchronous accesses previously described, the EMIF's memory-mapped registers must
be programmed appropriately to interface to a NAND Flash device. Table 12 lists the bit fields that must
be programmed when operating in NAND Flash mode and the values to set each bit. NAND Flash mode
cannot be used with Extended Wait mode.
Table 12. Configuration For NAND Flash
Register
Bit Field
Configuration Value
Asynchronous configuration
SS
0
register (ACFGn)
EW
0
W_SETUP/R_SETUP
W_STROBE/R_STROBE
W_HOLD/R_HOLD
ASIZE
Programmed to equal the width of the NAND Flash device
1
NAND Flash control register
(NANDFCR)
CS2NAND
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Architecture
2.5.6.2
Connecting to NAND Flash
Figure 8 shows the EMIF external pins used to interface with a NAND Flash device. EMIF address lines
are used to drive the NAND Flash device's command latch enable (CLE) and address latch enable (ALE)
signals.
NOTE: The EMIF will not control the NAND Flash device's write protect pin. The write protect pin
must be controlled outside of the EMIF.
Figure 8. EMIF to NAND Flash Interface
EMIF
NAND flash
CLE
CLE_EM_A[16]
ALE_EM_A[17]
EM_CS[n]
ALE
CE
EM_WE
WE
EM_OE
OE
EM_D[7:0]
EM_WAIT[n]
IO[7:0]
R/B
a) Connection to 8-bit NAND device
EMIF
NAND flash
CLE_EM_A[16]
ALE_EM_A[17]
EM_CS[n]
CLE
ALE
CE
EM_WE
WE
EM_OE
OE
EM_D[15:0]
EM_WAIT[n]
IO[15:0]
R/B
b) Connection to 16-bit NAND device
2.5.6.3
Driving CLE and ALE
As stated in Section 2.5.1, the EMIF always drives the least significant bit of a 32-bit word address on
EM_A[0]. This functionality must be considered when attempting to drive the address lines connected to
CLE and ALE to the appropriate state.
For example, if using EM_A[2] and EM_A[1] to connect to CLE and ALE, respectively, the following offsets
should be chosen:
•
00h to drive CLE and ALE low
•
•
10h to drive CLE high and ALE low
0Bh to drive CLE low and ALE high
These offsets should be added to the base address for the chip select space the NAND Flash device is
connected to. For example, if the base address of the CS space the NAND Flash device is connected to is
4200 0000h, then the above list translates to the following memory-mapped addresses: 4200 0000h, 4200
0010h, and 4200 000Bh, respectively. Therefore, when attempting to drive CLE high and ALE low, the
memory-mapped address of 4200 0010h would be written to.
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Architecture
2.5.6.4
NAND Read and Program Operations
A NAND Flash access cycle is composed of a command, address, and data phase. The EMIF will not
automatically generate these three phases to complete a NAND access with one transfer request. To
complete a NAND access cycle, multiple single asynchronous access cycles (as described above) must
be completed by the EMIF. Software must be used to request the appropriate asynchronous accesses to
complete a NAND Flash access cycle. This software must be developed to the specification of the chosen
NAND Flash device.
Since NAND operations are divided into single asynchronous access cycles, the chip select signal will not
remain activated for the duration of the NAND operation. Instead, the chip select signal will deactivate
between each asynchronous access cycle. For this reason, the EMIF does not support NAND Flash
devices that require the chip select signal to remain low during the tR time for a read. See Section 2.5.6.8
for workaround.
Care must be taken when performing a NAND read or write operation via the EDMA. See Section 2.5.6.5
for more details.
NOTE: The EMIF does not support NAND Flash devices that require the chip select signal to
2.5.6.5
NAND Data Read and Write via DMA
When performing NAND accesses, the EDMA is most efficiently used for the data phase of the access.
The command and address phases of the NAND access require only a few words of data to be
transferred and therefore do not take advantage of the EDMA's ability to transfer larger quantities of data
with a single request. In this section we will focus on using the EDMA for the data phase of a NAND
access.
There are two conditions that require care to be taken when performing NAND reads and writes via the
EDMA. These are:
•
CLE_EM_A[2] and ALE_EM_A[1] are lower address lines and must be driven low
•
The EMIF does not support a constant address mode, but only supports linear incrementing address
modes.
Since the EMIF does not support a constant addressing mode, when programming the EDMA, a linear
incrementing address mode must be used. When using a linear incrementing address mode, since the
CLE and ALE are driven by lower address lines, care must be taken not to increase the address into a
range the drives CLE and/or ALE high. To prevent the address from incrementing into a range that drives
CLE and/or ALE high, the EDMA ACNT, BCNT, SIDX, DIDX, and synchronization type must be
programmed appropriately. The proper EDMA configurations are described below.
EDMA setup for a NAND Flash data read:
•
•
•
•
•
ACNT ≤ 8 bytes (this can also be set to less than or equal to the external data bus width)
BCNT = transfer size in bytes/ACNT
SIDX (source index) = 0
DIDX (destination index) = ACNT
AB synchronized
EDMA setup for a NAND Flash data write:
•
•
•
•
•
ACNT ≤ 8 bytes (this can also be set to less than or equal to the external data bus width)
BCNT = transfer size in bytes/ACNT
SIDX (source index) = ACNT
DIDX (destination index) = 0
AB synchronized
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Architecture
2.5.6.6
ECC Generation
If the CSnNAND bit in the NAND Flash control register (NANDFCR) is set to 1, the EMIF supports ECC
calculation for up to 512 bytes for the corresponding chip select care. To perform the ECC calculation, the
CS2ECC bit in NANDFCR must be set to 1. The ECC calculation for each chip select space is
independent of each other. It is the responsibility of the software to start the ECC calculation by writing to
the CS2ECC bit prior to issuing a write or read to NAND Flash. It is also the responsibility of the software
to read the calculated ECC from the NAND Flash 1 ECC register (NANDF1ECC) once the transfer to
NAND Flash has completed. If the software writes or reads more than 512 bytes, the ECC will be
incorrect. There is a NANDECCn for each chip select space and when read, the corresponding CSnECC
bit in NANDFCR is cleared. The NANDF1ECC is cleared upon writing a 1 to the CS2ECC bit. Figure 9
shows the algorithm used to calculate the ECC value for an 8-bit NAND Flash.
For an 8-bit NAND Flash p1e through p4e are column parities and p8e through p2048 are row parities.
Similarly, the algorithm can be extended to a 16-bit NAND Flash. For a 16-bit NAND Flash p1e through
p8e are column parities and p16e through p2048 are row parities. The software must ignore the unwanted
parity bits if ECC is desired for less than 512 bytes of data. For example. p2048e and p2048o are not
required for ECC on 256 bytes of data. Similarly, p1024e, p1024o, p2048e, and p2048o are not required
for ECC on 128 bytes of data.
Figure 9. ECC Value for 8-Bit NAND Flash
Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
p8e
p8o
p8e
p8o
p16e
p16o
p32e
p2048e
p2048o
Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
p8e
p8o
p8e
p8o
p16e
p16o
p32o
p1o
p1e
p1o
p1e
p1o
p1e
p1o
p1e
p2o
p2e
p2o
p2e
p4o
p4e
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Architecture
2.5.6.7
NAND Flash Status Register (NANDFSR)
The NAND Flash status register (NANDFSR) indicates the raw status of the EM_WAITn pin. The
EM_WAITn pin should be connected to the NAND Flash device's R/B signal, so that it indicates whether
or not the NAND Flash device is busy. During a read, the R/B signal will transition and remain low while
the NAND Flash retrieves the data requested. Once the R/B signal transitions high, the requested data is
ready and should be read by the EMIF. During a write/program operation, the R/B signal transitions and
remains low while the NAND Flash is programming the Flash with the data it has received from the EMIF.
Once the R/B signal transitions high, the data has been written to the Flash and the next phase of the
transaction may be performed. From this explanation, you can see that the NAND Flash status register is
useful to the software for indicating the status of the NAND Flash device and determining when to proceed
to the next phase of a NAND Flash operation.
When a rising edge occurs on the EM_WAITn pin, the EMIF sets the WR (wait rise) bit in the EMIF
interrupt raw register (EIRR). Therefore, the EMIF wait rise interrupt may be used to indicate the status of
the NAND Flash device. The WPn bit in the asynchronous wait cycle configuration register (AWCCR)
does not affect the NAND Flash status register (NANDFSR) or the WRn bit in EIRR. See Section 2.5.11.1
for more a detailed description of the wait rise interrupt.
2.5.6.8
Interfacing to a Non-CE Don't Care NAND Flash
select signal to remain low during the tR time for a read. One way to work around this limitation is to use a
GPIO pin to drive the CE signal of the NAND Flash device. If this work around is implemented, software
will configure the selected GPIO to be low, then begin the NAND Flash operation, starting with the
command phase. Once the NAND Flash operation has completed the software will configure the selected
2.5.7
Interfacing to a TI DSP HPI
The EMIF supports connecting as a host to a TI DSP HPI interface. When connecting to a TI DSP HPI
diagram.
Figure 10. EMIF to 16-Bit Multiplexed HPI16 Interface
AEMIF
HPI16
EM_D[15:0]
HD[15:0]
EM_RW
EM_A[1:0]
EM_WAIT
EM_OE
HR/W
HCNTL[1:0]
HRDY
HDS1
EM_WE
EM_CS
HDS2
HCS
EM_BA1
GPIOx
HHWIL
HINT
VCC
VCC
VSS
VSS
HAS
HPIENA
HBEDA
HBE1A
A
HBE signals may not be present on all HPI interfaces.
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Architecture
2.5.8
Extended Wait Mode and the EM_WAIT Pin
The Extended Wait mode is a mode in which the external asynchronous device may assert control over
the length of the strobe period. The Extended Wait mode can be entered by setting the EW bit in the
asynchronous configuration register (ACFGn). When the EW bit is set, the EMIF monitors the
EM_WAIT[5:2] pins to determine if the attached device wishes to extend the strobe period of the current
access cycle beyond the programmed number of clock cycles.
When the EMIF detects that the EM_WAIT pin has been asserted, it will begin inserting extra strobe
cycles into the operation until the EM_WAIT pin is deactivated by the external device. The EMIF will then
return to the last cycle of the programmed strobe period and the operation will proceed as usual from this
point. Refer to the device-specific data manual for details on the timing requirements of the EM_WAIT
signal.
The EM_WAIT pin cannot be used to extend the strobe period indefinitely. The programmable MEWC bit
in the asynchronous wait cycle configuration register (AWCCR) determines the maximum number of EMIF
clock cycles the strobe period may be extended beyond the programmed length. When the number of
cycles programmed in the MEWC bit expires, the EMIF proceeds to the hold period of the operation
regardless of the state of the EM_WAIT pin. The EMIF can also generate an interrupt upon expiration of
For the EMIF to function properly in the Extended Wait mode, the WPn bit in AWCCR must be
programmed to match the polarity of the attached device. When the WPn bit is in its reset state of 1, the
EMIF will insert wait cycles when the EM_WAITn pin is sampled high; when the WPn bit is cleared to 0,
the EMIF will insert wait cycles only when the EM_WAITn pin is sampled low. This programmability allows
for a glueless connection to larger variety of asynchronous devices.
Finally, a restriction is placed on the setup and strobe period timing parameters when operating in
Extended Wait mode. Specifically, the sum of the W_SETUP and W_STROBE fields must be greater than
4, and the sum of the R_SETUP and R_STROBE fields must be greater than 4 for the EMIF to recognize
the EM_WAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields
are in ACFGn.
2.5.9
Data Bus Parking
The EMIF always drives the data bus to the previous write data value when it is idle. This feature is called
data bus parking. Only when the EMIF issues a read command to the external memory does it stop
driving the data bus. After the EMIF latches the last read data, it immediately parks the data bus again.
2.5.10 Reset and Initialization Considerations
The EMIF and its registers will be reset when any of the following events occur:
1. The RESET pin on the device is asserted
2. The EMIF is placed in reset by the Power and Sleep Controller.
When a reset occurs, the EMIF will immediately abandon any access request that is in progress and reset
all registers and internal logic to their default state.
Following device power up and deassertion of the RESET pin, the internal clock to the EMIF is turned on
and the EMIF memory-mapped registers are programmed to their default values.
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Architecture
2.5.11 Interrupt Support
information on the ARM interrupt controller (AINTC), see the TMS320DM646x DMSoC ARM Subsystem
Table 13. EMIF Interrupt
ARM Event
Acronym
Source
60
EMIFAINT
EMIF
The EMIF supports a single interrupt to the CPU. Section 2.5.11.1 details the generation and internal
masking of EMIF interrupts and Section 2.5.11.2 describes how the EMIF interrupts are sent to the CPU.
2.5.11.1 Interrupt Events
There are two conditions that may cause the EMIF to generate an interrupt to the CPU. These two
conditions are:
•
•
A rising edge on the EM_WAIT signal (wait rise interrupt)
An asynchronous time out
The wait rise interrupt is not affected by the WPn bit in the asynchronous wait cycle configuration register
(AWCCR). The asynchronous time out interrupt condition occurs when the attached asynchronous device
fails to deassert the EM_WAIT pin within the number of cycles defined by the MEWC bit in AWCCR.
Only when the interrupt is enabled by setting the appropriate bit (WRMSETn or ATMSET) in the EMIF
interrupt mask set register (EIMSR) to 1, will the interrupt be sent to the CPU. Once enabled, the interrupt
may be disabled by writing a 1 to the corresponding bit in the EMIF interrupt mask clear register (EIMCR).
The bit fields in both the EIMSR and EIMCR may be used to indicate whether the interrupt is enabled.
When the interrupt is enabled, the corresponding bit field in both the EIMSR and EIMCR will have a value
of 1; when the interrupt is disabled, the corresponding bit field will have a value of 0.
The EMIF interrupt raw register (EIRR) and the EMIF interrupt mask register (EIMR) indicate the status of
each interrupt. The appropriate bit (WRn or AT) in EIRR is set when the interrupt condition occurs,
whether or not the interrupt has been enabled. Whereas, the appropriate bit (WRMn or ATM) in EIMR is
set only when the interrupt condition occurs and the interrupt is enabled. Writing a 1 to the bit in EIRR
clears the EIRR bit as well as the corresponding bit in EIMR.
Table 14 contains a brief summary of the interrupt status and control bit fields. See Section 4 for complete
details on the register fields.
Table 14. Interrupt Monitor and Control Bit Fields
Register Name
Bit Name
Description
EMIF interrupt raw register
(EIRR)
WRn
This bit is always set when an rising edge on the EM_WAIT signal occurs.
Writing a 1 clears the WRn bit as well as the WRMn bit in EIMR.
AT
This bit is always set when an asynchronous timeout occurs. Writing a 1
clears the AT bit as well as the ATM bit in EIMR.
EMIF interrupt mask register
(EIMR)
WRMn
This bit is only set when a rising edge on the EM_WAIT signal occurs and
the interrupt has been enabled by writing a 1 to the WRMSETn bit in
EIMSR.
ATM
This bit is only set when an asynchronous timeout occurs and the interrupt
has been enabled by writing a 1 to the ATMSET bit in EIMSR.
EMIF interrupt mask set register
(EIMSR)
WRMSETn
ATMSET
Writing a 1 to this bit enables the wait rise interrupt.
Writing a 1 to this bit enables the asynchronous timeout interrupt.
Writing a 1 to this bit disables the wait rise interrupt.
EMIF interrupt mask clear register
(EIMCR)
WRMCLRn
ATMCLR
Writing a 1 to this bit disables the asynchronous timeout interrupt.
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Architecture
2.5.11.2 Interrupt Multiplexing
The EMIF interrupt is supported by both the ARM and DSP. The interrupt is not multiplexed with another
interrupt and is therefore always available.
2.5.12 Program Execution
Since the EMIF does not have byte enable or data mask pins, byte accesses to memory are not
supported when the data bus width is equal to 16 bits. When performing data accesses on a 16-bit bus,
this may be worked around by performing a write modify read back operation. When executing code from
the EMIF, the bus width must be configured to be an 8-bit data bus.
2.5.13 Power Management
Power dissipation to the EMIF may be managed by gating the input clock to the EMIF off. The input clock
is turned off outside of the EMIF through the use of the Power and Sleep Controller (PSC). When the PSC
sends a clock stop request to the EMIF, the EMIF will complete pending transfers before issuing a clock
stop acknowledge, allowing the PSC to stop the clock. See the TMS320DM646x DMSoC ARM Subsystem
2.5.14 Emulation Considerations
The operation of the EMIF is not affected when a breakpoint is reached or an emulation halt occurs.
29
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3
Use Cases
The EMIF allows a high degree of programmability for shaping asynchronous accesses. As previously
stated, the shape and duration of the asynchronous access is determined by controlling the widths of the
SETUP, STROBE, HOLD, and turnaround periods. The widths of these periods are configured by
programming the asynchronous configuration register (ACFGn) for the corresponding chip select space.
The programmability inherent to the EMIF, provides the EMIF with the flexibility to interface with a variety
of asynchronous memory types. By programming the W_SETUP/R_SETUP, W_STROBE/R_STROBE,
W_HOLD/R_HOLD, TA, and ASIZE fields in ACFGn, the EMIF can be configured to meet the data sheet
specification for most asynchronous memory devices.
This section presents examples describing how to interface the EMIF to asynchronous SRAM and NAND
Flash devices.
3.1 Interfacing to Asynchronous SRAM (ASRAM)
The following example describes how to interface the EMIF to the Toshiba TC55V16100FT-12 device.
3.1.1
Connecting to ASRAM
Figure 11 shows how to connect the EMIF to the TC55V16100FT-12 device. Since the EMIF does not
include data mask or byte enable signals, the LB and UB signals of the ASRAM must be tied high.
Figure 11. Connecting the EMIF to the TC55V16100FT-12
EMIF
EM_CS
TC5516100FT−12
CE
EM_WE
EM_OE
WE
OE
VS S
VSS
LB
UB
A[18:0]
EM_BA[1]
A[19:1]
A[0]
EM_D[15:0]
DQ[15:0]
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3.1.2
Meeting AC Timing Requirements for ASRAM
When configuring the EMIF to interface to ASRAM, you must consider the AC timing requirements of the
ASRAM as well as the AC timing requirements of the EMIF. These can be found in the data sheet for
each respective device. The read and write asynchronous cycles are programmed separately in the
asynchronous configuration register (ACFGn).
Table 15. EMIF Input Timing Requirements
Parameter Description
tSU
tH
Data Setup time, data valid before EM_OE high
Data Hold time, data valid after EM_OE high
Table 16. ASRAM Output Timing Characteristics
Parameter Description
tACC Address Access time
tOH
Output data Hold time for address change
Output Disable time from chip enable
tCOD
Table 17. ASRAM Input Timing Requirement for a Read
Parameter Description
tRC
Read Cycle time
Figure 12 shows an asynchronous read access and describes how the EMIF and ASRAM AC timing
requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD.
From Figure 12, the following equations may be derived. tcyc is the period at which the EMIF operates. The
R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the data
sheet specifications are typically given in nano seconds. This explains the presence of tcyc in the
denominator of the following equations. A minus 1 is included in the equations because each field in
ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to
R_SETUP width in EMIF clock cycles minus 1 cycle.
ǒ
Ǔ
tACC(m) ) tSU
R_SETUP ) R_STROBE w
* 1
tcyc
tRC(m)
tcyc
R_SETUP ) R_STROBE ) R_HOLD w
* 3
ǒ
Ǔ
tH * tOH(m)
R_HOLD w
* 1
tcyc
The EMIF offers an additional parameter, TA, that defines the turnaround time between read and write
cycles. This parameter protects against the situation when the output turn-off time of the memory is longer
than the time it takes to start the next write cycle. If this is the case, the EMIF will drive data at the same
time as the memory, causing contention on the bus. By examining Figure 12, the equation for TA can be
derived as:
tCOD(m)
tcyc
TA w
* 1
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Figure 12. Timing Waveform of an ASRAM Read
Setup
Hold
Strobe
EM_CS
t
(m)
RC
EM_A[21:0]
EM_BA[1:0]
EM_OE
t
(m)
COD
t
t
(m)
SU
OH
t
(m)
t
H
ACC
EM_D[15:0]
Table 18. ASRAM Input Timing Requirements for a Write
Parameter Description
tWP
tAW
tDS
tWR
tDH
tWC
Write Pulse width
Address valid to end of Write
Data Setup time
Write Recovery time
Data Hold time
Write Cycle time
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Figure 13 shows an asynchronous write access and describes how the EMIF and ASRAM AC timing
requirements work together to define values for W_SETUP, W_STROBE, and W_HOLD.
From Figure 13, the following equations may be derived. tcyc is the period at which the EMIF operates. The
W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles where as the data
sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the
denominator of the following equations. A minus 1 is included in the equations because each field in
ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, W_SETUP is equal to
W_SETUP width in EMIF clock cycles minus 1 cycle.
tWP(m)
tcyc
W_STROBE w
* 1
tDS(m)
tcyc
tAW(m)
tcyc
W_SETUP ) W_STROBE w maxǒ
Ǔ* 1
,
tWR(m) tDH(m)
W_HOLD w maxǒ
Ǔ* 1
,
tcyc
tcyc
tWC(m)
tcyc
W_SETUP ) W_STROBE ) W_HOLD w
* 3
Figure 13. Timing Waveform of an ASRAM Write
Setup
Hold
Strobe
EM_CS
t
(m)
WC
t
(m)
WR
EM_A[21:0]
EM_BA[1:0]
t (m)
WP
t (m)
AW
EM_WE
t
(m)
DS
t
(m)
DH
EM_D[15:0]
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3.1.3
Taking Into Account PCB Delays
The equations described in Section 3.1.2 are for the ideal case, when board design does not contribute
delays. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the
device driver behaves. Signals driven by the EMIF will be delayed when they reach the ASRAM and
delays are board specific and must be estimated or determined though the use of IBIS modeling. The
signals denoted (ASRAM) are the signals seen at the ASRAM. For example, EM_CS represents the signal
at the EMIF and EM_CS (ASRAM) represents the delayed signal seen at the ASRAM.
Table 19. ASRAM Timing Requirements With PCB Delays
Parameter Description
Read Access
tEM_CS
tEM_A
tEM_OE
tEM_D
Delay on EM_CS from EMIF to ASRAM. EM_CS is driven by EMIF.
Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.
Delay on EM_OE from EMIF to ASRAM. EM_OE is driven by EMIF.
Delay on EM_D from ASRAM to EMIF. EM_D is driven by ASRAM.
Write Access
tEM_CS
tEM_A
tEM_WE
tEM_D
Delay on EM_CS from EMIF to ASRAM. EM_CS is driven by EMIF.
Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.
Delay on EM_WE from EMIF to ASRAM. EM_WE is driven by EMIF.
Delay on EM_D from EMIF to ASRAM. EM_D is driven by EMIF.
From Figure 14, the following equations may be derived. tcyc is the period at which the EMIF operates. The
R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the data
sheet specifications are typically given in nano seconds. This is explains the presence of tcyc in the
denominator of the following equations. A minus 1 is included in the equations because each field in
ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to
R_SETUP width in EMIF clock cycles minus 1 cycle.
ǒ
Ǔ
tEM_A ) tACC(m) ) tSU ) tEM_D
R_SETUP ) R_STROBE w
* 1
tcyc
tRC(m)
tcyc
R_SETUP ) R_STROBE ) R_HOLD w
* 3
ǒ
Ǔ
tH * tEM_D * tOH(m) * tEM_A
R_HOLD w
* 1
tcyc
ǒ
Ǔ
tEM_CS ) tCOD(m) ) tEM_D
TA w
* 1
tcyc
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Figure 14. Timing Waveform of an ASRAM Read with PCB Delays
Setup
2
Hold
4
Strobe
3
1
EM_CS
t
t
CS
CS
EM_CS (ASRAM)
EM_A[21:0]/
EM_BA[1:0]
t
t
EM_A
EM_A
t
(m)
RC
EM_A[21:0]/
EM_BA[1:0] (ASRAM)
EM_OE
t
t
EM_OE
EM_OE
EM_OE (ASRAM)
EM_D[15:0]
t
H
t
SU
t
EM_D
t
EM_D
t
(m)
t
(m)
COD
ACC
t
(m)
OH
EM_D[15:0]
(ASRAM)
From Figure 15, the following equations may be derived. tcyc is the period at which the EMIF operates. The
W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles where as the data
sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the
denominator of the following equations. A minus 1 is included in the equations because each field in
ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, W_SETUP is equal to
W_SETUP width in EMIF clock cycles minus 1 cycle.
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tWP(m)
tcyc
W_STROBE w
* 1
ǒ
Ǔ ǒ
Ǔ
tEM_A ) tAW(m) * tEM_WE
tEM_D ) tDS(m) * tEM_WE
W_SETUP ) W_STROBE w max
,
* 1
ǒ
Ǔ
tcyc
tcyc
ǒ
Ǔ ǒ
Ǔ
tEM_WE ) tWR(m) * tEM_A
tEM_WE ) tDH(m) * tEM_D
W_HOLD w max
,
* 1
ǒ
Ǔ
tcyc
tcyc
tWC(m)
tcyc
W_SETUP ) W_STROBE ) W_HOLD w
* 3
Figure 15. Timing Waveform of an ASRAM Write with PCB Delays
Setup
2
Hold
4
Strobe
3
1
EM_CS
t
t
EM_CS
EM_CS
EM_CS (ASRAM)
EM_A[21:0]/
EM_BA[1:0]
t
t
EM_A
t
(m)
WC
t
(m)
EM_A
WR
EM_A[21:0]/
EM_BA[1:0] (ASRAM)
EM_WE
t (m)
WP
t
EM_WE
t
EM_WE
t (m)
AW
EM_WE (ASRAM)
EM_D[15:0]
t
(m)
t
DH
EM_D
t
(m)
DS
t
EM_D
EM_D[15:0]
(ASRAM)
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3.1.4
Example Using TC5516100FT-12
This section takes you through the configuration steps required to implement Toshiba’s TC55V1664FT-12
ASRAM with the EMIF. The following assumptions are made:
•
•
ASRAM is connected to chip select space 3 (EM_CS[3])
EMIF clock speed is 100 MHZ (tcyc = 10 nS)
Table 20 lists the data sheet specifications for the EMIF and Table 21 lists the data sheet specifications
for the ASRAM.
Table 20. EMIF Timing Requirements for TC5516100FT-12 Example
Parameter Description
tSU Data Setup time, data valid before EM_OE high
tH Data Hold time, data valid after EM_OE high
Min
5
Max
Units
nS
0
nS
Table 21. ASRAM Timing Requirements for TC5516100FT-12 Example
Parameter Description
Min
Max
Units
nS
tACC
tOH
tRC
Address Access time
12
Output data Hold time for address change
Read cycle time
3
nS
12
8
nS
tWP
tAW
tDS
Write Pulse width
nS
Address valid to end of Write
Data Setup time
9
nS
7
nS
tWR
tDH
tWC
tCOD
Write Recovery time
0
nS
Data Hold time
0
nS
Write Cycle time
12
nS
Output Disable time from chip enable
7
Table 22 lists the values of the PCB board delays. The delays were estimated using the rule that there is
180 pS of delay for every 1 inch of trace.
Table 22. Measured PCB Delays for TC5516100FT-12 Example
Parameter
Description
Delay (ns)
Read Access
tEM_CS
tEM_A
tEM_OE
tEM_D
Delay on EM_CS from EMIF to ASRAM. EM_CS is driven by EMIF.
Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.
Delay on EM_OE from EMIF to ASRAM. EM_OE is driven by EMIF.
Delay on EM_D from ASRAM to EMIF. EM_D is driven by ASRAM.
Write Access
0.36
0.27
0.36
0.45
tEM_CS
tEM_A
tEM_WE
tEM_D
Delay on EM_CS from EMIF to ASRAM. EM_CS is driven by EMIF.
Delay on EM_A from EMIF to ASRAM. EM_A is driven by EMIF.
Delay on EM_WE from EMIF to ASRAM. EM_WE is driven by EMIF.
Delay on EM_D from EMIF to ASRAM. EM_D is driven by EMIF.
0.36
0.27
0.36
0.45
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Inserting these values into the equations defined above allows you to determine the values for SETUP,
STROBE, HOLD, and TA. For a read:
ǒ
Ǔ
tEM_A ) tACC(m) ) tSU ) tEM_D
(
)
0.27 ) 12 ) 5 ) 0.45
R_SETUP ) R_STROBE w
* 1 w
* 1 w 0.78
tcyc
10
tRC(m)
tcyc
12
10
* 3 w ǒ Ǔ* 3 w * 1.8
R_SETUP ) R_STROBE ) R_HOLD w
ǒ
Ǔ
tH * tEM_D * tOH(m) * tEM_A
(
)
0 * 0.45 * 3 * 0.27
R_HOLD w
* 1 w
* 1 w * 1.37
tcyc
10
ǒ
Ǔ
tEM_CS ) TCOD(m) ) tEM_D
(
)
0.36 ) 7 ) 0.45
TA w
* 1 w
* 1 w *0.22
tcyc
10
Therefore if R_SETUP = 0, then R_STROBE = 0, R_HOLD = 0, and TA = 0.
For a write:
tWP(m)
tcyc
8
10
* 1 w ǒ Ǔ* 1 w * 0.2
W_STROBE w
ǒ
Ǔ ǒ
Ǔ
tEM_A ) tAW(m) * tEM_WE
tEM_D ) tDS (m) * tEM_WE
W_SETUP ) W_STROBE w max
,
* 1
ǒ
Ǔ
tcyc
tcyc
(
)
(
)
0.36 ) 0 * 0.45
0.36 ) 0 * 0.27
w maxǒ
Ǔ* 1 w * 0.92
,
10
10
ǒ
Ǔ ǒ
Ǔ
tEM_WE ) tWR(m) * tEM_A
tEM_WE ) tDH(m) * tEM_D
W_HOLD w max
,
* 1
ǒ
Ǔ
tcyc
tcyc
(
)
(
)
0.45 ) 7 * 0.36
0.27 ) 9 * 0.36
w maxǒ
Ǔ* 1 w * 0.1
,
10
10
tWC(m)
tcyc
12
10
* 3 w ǒ Ǔ* 3 w * 1.8
W_SETUP ) W_STROBE ) W_HOLD w
Therefore, W_SETUP = 0, W_STROBE = 0, and W_HOLD = 0.
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Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields
example, the EM_WAIT signal is not implemented; therefore, the asynchronous wait cycle configuration
register (AWCCR) does not need to be programmed.
Table 23. Configuring A2CR for TC5516100FT-12 Example
Parameter
Setting
SS
Select Strobe mode.
•
SS = 0. Places EMIF in Normal Mode.
Extended Wait mode enable.
EW = 0. Disabled Extended wait mode.
Read/Write setup widths.
EW
•
W_SETUP/R_SETUP
•
•
W_SETUP = 0
R_SETUP = 0
W_STROBE/R_STROBE
W_HOLD/R_HOLD
Read/Write strobe widths.
•
•
W_STROBE = 0
R_STROBE = 0
Read/Write hold widths.
•
•
W_HOLD = 0
R_HOLD = 0
TA
Minimum turnaround time.
TA = 0
Asynchronous Device Bus Width.
ASIZE = 1, select a 16-bit data bus width
•
ASIZE
•
3.2 Interfacing to NAND Flash
The following example explains how to interface the EMIF to the Hynix HY27UA081G1M NAND Flash
3.2.1
Margin Requirements
The Flash interface is typically a low-performance interface compared to synchronous memory interfaces,
high-speed asynchronous memory interfaces, and high-speed FIFO interfaces. For this reason, this
example gives little attention to minimizing the amount of margin required when programming the
asynchronous timing parameters. The approach used requires approximately 10 ns of margin on all
parameters, which is not significant for a 100-ns read or write cycle. For additional details on minimizing
Table 24. Recommended Margins
Timing Parameter
Output Setup
Output Hold
Input Setup
Recommended Margin
10 nS
10 nS
10 nS
10 nS
Input Hold
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3.2.2
Meeting AC Timing Requirements for NAND Flash
When configuring the EMIF to interface to NAND Flash, you must consider the AC timing requirements of
the NAND Flash as well as the AC timing requirements of the EMIF. These can be found in the data sheet
for each respective device. The read and write asynchronous cycles are programmed separately in the
asynchronous configuration register (ACFGn).
As described in Section 2.5.6, a NAND Flash access cycle is composed of a command, address, and data
phases. The EMIF will not automatically generate these three phases to complete a NAND access with
one transfer request. To complete a NAND access cycle, multiple single asynchronous access cycles
must be completed by the EMIF. The command and address phases of a NAND Flash access cycle are
asynchronous writes performed by the EMIF where as the data phase can be either an asynchronous
write or a read depending on whether the NAND Flash is being programmed or read.
Therefore, to determine the required EMIF configuration to interface to the NAND Flash for a read
Table 25. EMIF Read Timing Requirements
Parameter Description
tSU
tH
Data Setup time, data valid before EM_OE high
Data Hold time, data valid after EM_OE high
Table 26. NAND Flash Read Timing Requirements
Parameter Description
tRP
Read Pulse width
tREA
tCEA
tCHZ
tRC
Read Enable Access time
Chip Enable low to output valid
Chip Enable high to output High-impedance
Read Cycle time
tRHZ
tCLR
Read enable high to output High-impedance
Command Latch low to Read enable low
Figure 16 shows an asynchronous read access and describes how the EMIF and NAND Flash AC timing
requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD.
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From Figure 16, the following equations may be derived. tcyc is the period at which the EMIF operates. The
R_SETUP, R_STROBE, and R_HOLD fields are programmed in terms of EMIF cycles where as the data
sheet specifications are typically given is nano seconds. This is explains the presence of tcyc in the
denominator of the following equations. A minus 1 is included in the equations because each field in
ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, R_SETUP is equal to
R_SETUP width in EMIF clock cycles minus 1 cycle.
tCLR(m)
tcyc
R_SETUP w
* 1
ǒ
SUǓ
tREA(m) ) t
tRP(m)
tcyc
R_STROBE w maxǒ
Ǔ* 1
,
tcyc
ǒ
Ǔ
tCEA(m) ) tSU
R_SETUP ) R_STROBE w
* 1
tcyc
ǒ
Ǔ
tH * tCHZ(m)
R_HOLD w
* 1
tcyc
tRC(m)
tcyc
R_SETUP ) R_STROBE ) R_HOLD w
* 3
The EMIF offers an additional parameter, TA, that defines the turnaround time between read and write
cycles. This parameter protects against the situation when the output turn-off time of the memory is longer
than the time it takes to start the next write cycle. If this is the case, the EMIF will drive data at the same
time as the memory, causing contention on the bus. By examining Figure 16, the equation for TA can be
derived as:
tRHZ(m) * (R_HOLD ) 1)tcyc
tCHZ(m)
tcyc
TA w maxǒ
Ǔ* 1
,
tcyc
Figure 16. Timing Waveform of a NAND Flash Read
Setup
Hold
Strobe
EM_CS
t
(m)
RC
ALE_EM_A[1]
CLE_EM_A[2]
EM_OE
t
(m)
RP
t
(m)
CLR
t (m)
CHZ
t
(m)
t
H
REA
t
SU
t
(m)
t
(m)
RHZ
CEA
EM_D[7:0]
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To determine the required EMIF configuration to interface to the NAND Flash for a write operation,
Table 27 lists the NAND AC timing parameters for a command latch, address latch, and data input latch
that must be considered.
Table 27. NAND Flash Write Timing Requirements
Parameter Description
tWP
tCLS
tALS
tCS
Write Pulse width
CLE Setup time
ALE Setup time
CS Setup time
Data Setup time
CLE Hold time
ALE Hold time
CS Hold time
tDS
tCLH
tALH
tCH
tDH
Data Hold time
Write Cycle time
tWC
Figure 17 to Figure 19 show the command latch, address latch, and data input latch of the NAND access.
From Figure 17 to Figure 19, the following equations may be derived. tcyc is the period at which the EMIF
operates. The W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIF cycles
where as the data sheet specifications are typically given is nano seconds. This is explains the presence
of tcyc in the denominator of the following equations. A minus 1 is included in the equations because each
field in ACFGn is programmed in terms of EMIF clock cycles, minus 1 cycle. For example, W_SETUP is
equal to W_SETUP width in EMIF clock cycles minus 1 cycle.
tCLS(m) tALS(m) tCS(m)
W_SETUP w maxǒ
Ǔ* 1
,
,
tcyc
tcyc
tcyc
tWP(m)
tcyc
W_STROBE w
* 1
tDS(m)
tcyc
W_SETUP ) W_STROBE w
* 1
tCLH(m)
tcyc
tCH(m)
tcyc
tALH(m)
tcyc
tDH(m)
tcyc
W_HOLD w maxǒ
Ǔ* 1
,
,
,
tWC(m)
tcyc
W_SETUP ) W_STROBE ) W_HOLD w
* 3
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Figure 17. Timing Waveform of a NAND Flash Command Write
Setup
Hold
Strobe
t
(m)
CH
EM_CS
t
(m)
WC
t
(m)
(m)
ALH
ALE_EM_A[1]
CLE_EM_A[2]
t
CLH
t (m)
WP
t
t
t
(m)
CS
(m)
ALS
(m)
CLS
EM_WE
t
(m)
DS
t
(m)
DH
EM_D[7:0]
Figure 18. Timing Waveform of a NAND Flash Address Write
Setup
Hold
Strobe
t
(m)
CH
EM_CS
t
(m)
WC
t
(m)
(m)
ALH
ALE_EM_A[1]
CLE_EM_A[2]
t
CLH
t (m)
WP
t
t
t
(m)
CS
(m)
ALS
(m)
CLS
EM_WE
t
(m)
DS
t
(m)
DH
EM_D[7:0]
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Figure 19. Timing Waveform of a NAND Flash Data Write
Setup
Hold
Strobe
t
(m)
CH
EM_CS
t
(m)
WC
t
(m)
(m)
ALH
ALE_EM_A[1]
CLE_EM_A[2]
t
CLH
t (m)
WP
t
t
t
(m)
CS
(m)
ALS
(m)
CLS
EM_WE
t
(m)
DS
t
(m)
DH
EM_D[7:0]
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3.2.3
Example Using Hynix HY27UA081G1M
This section takes you through the configuration steps required to implement Hynix’s HY27UA081G1M
NAND Flash with the EMIF. The following assumptions are made:
•
•
NAND Flash is connected to chip select space 2 (EM_CS[2])
EMIF clock speed is 100 MHZ (tcyc = 10 nS)
Table 28 lists the data sheet specifications for the EMIF and Table 29 lists the data sheet specifications
for the NAND Flash.
Table 28. EMIF Timing Requirements for HY27UA081G1M Example
Parameter Description
tSU Data Setup time, data valid before EM_OE high
tH Data Hold time, data valid after EM_OE high
Min
5
Max
Units
nS
0
nS
Table 29. NAND Flash Timing Requirements for HY27UA081G1M Example
Parameter Description
Min
Max
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
tRP
Read Pulse width
60
tREA
tCEA
tCHZ
tRC
Read Enable Access time
Chip Enable low to output valid
Chip Enable high to output High-impedance
Read Cycle time
60
75
20
80
tRHZ
tCLR
tWP
tCLS
tALS
tCS
Read Enable high to output High-impedance
Command Latch low to Read enable low
Write Pulse width
30
10
60
0
CLE Setup time
ALE Setup time
0
CS Setup time
0
tDS
Data Setup time
20
10
10
10
10
80
tCLH
tALH
tCH
CLE Hold time
ALE Hold time
CS Hold time
tDH
Data Hold time
tWC
Write Cycle time
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Inserting these values into the equations defined above allows you to determine the values for SETUP,
STROBE, HOLD, and TA. For a read:
tCLR(m)
tcyc
10
10
* 1 w ǒ Ǔ* 1 w 0
R_SETUP w
ǒ
SUǓ
tREA(m) ) t
tRP
tcyc
65
10
* 1 w ǒ Ǔ* 1 w 5.5
R_STROBE w maxǒ
Ǔ
,
tcyc
ǒ
Ǔ
tCEA ) tSU
(75 ) 5)
R_SETUP ) R_STROBE w
* 1 w
* 1 w 7
tcyc
10
ǒ
Ǔ
tH * tCHZ(m)
(0 * 20)
R_HOLD w
* 1 w
* 1 w * 3
tcyc
10
tRC(m)
tcyc
80
10
* 3 w ǒ Ǔ* 3 w 5
R_SETUP ) R_STROBE ) R_HOLD w
Therefore with a 10 nS margin added in, R_SETUP ≥ 1.0, R_STROBE ≥ 6.5, and R_HOLD ≥ 0.
After solving for R_HOLD, TA may be calculated:
tRHZ(m) * (R_HOLD ) 1)tcyc
tCHZ(m)
tcyc
20
10
* 1 w ǒ Ǔ* 1 w 1
TA w maxǒ
Ǔ
,
tcyc
Adding a 10 ns margin, TA ≥ 2.
For a write:
tWP(m)
tcyc
60
10
* 1 w ǒ Ǔ* 1 w 5
W_STROBE w
tCLS(m) tALS(m) tCS(m)
0
10
* 1 w ǒ Ǔ* 1 w * 1
W_SETUP w maxǒ
Ǔ
,
,
tcyc
tcyc
tcyc
tDS(m)
tcyc
20
10
* 1 w ǒ Ǔ* 1 w 1
W_SETUP ) W_STROBE w
tCLH(m)
tcyc
tCH(m)
tcyc
tALH(m)
tcyc
tDH(m)
tcyc
10
10
* 1 w ǒ Ǔ* 1 w 0
W_HOLD w maxǒ
Ǔ
,
,
,
tWC(m)
tcyc
80
10
* 3 w ǒ Ǔ* 3 w 5
W_SETUP ) W_STROBE ) W_HOLD w
Therefore with a 10 nS margin added in, W_SETUP ≥ 0, W_STROBE ≥ 6, and W_HOLD ≥ 1.
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Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields
example, although the EM_WAIT signal is connected to the R/B signal of the NAND Flash the Extended
Wait mode of the EMIF is not used, therefore the asynchronous wait cycle configuration register (AWCCR)
does not need to be programmed.
Table 30. Configuring A1CR for HY27UA081G1M Example
Parameter
Setting
SS
Select Strobe mode.
•
SS = 0. Places EMIF in Normal Mode.
Extended Wait mode enable.
EW = 0. Disabled Extended wait mode.
Read/Write setup widths.
EW
•
W_SETUP/R_SETUP
•
•
W_SETUP = 0
R_SETUP = 2
W_STROBE/R_STROBE
W_HOLD/R_HOLD
Read/Write strobe widths.
•
•
W_STROBE = 6
R_STROBE = 7
Read/Write hold widths.
•
•
W_HOLD = 1
R_HOLD = 0
TA
Minimum turnaround time.
TA = 2
Asynchronous device bus width.
ASIZE = 0, select an 8-bit data bus width.
•
ASIZE
•
Since this is a NAND Flash example, the EMIF must be configured for NAND Flash mode. This is
chip select space 2 must be configured with NAND Flash mode enabled.
Table 31. Configuring NANDFCR for HY27UA081G1M Example
Parameter
Setting
CS5ECC
NAND Flash ECC start for chip select 5.
•
CS5ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
NAND Flash ECC start for chip select 4.
CS4ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
NAND Flash ECC start for chip select 3.
CS3ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
NAND Flash ECC start for chip select 2.
CS2ECC = 0. Not set during configuration. Only set just prior to reading or writing data.
NAND Flash mode for chip select 5.
CS5NAND = 0. NAND Flash mode is disabled.
NAND Flash mode for chip select 4.
CS4NAND = 0. NAND Flash mode is disabled.
NAND Flash mode for chip select 3.
CS3NAND = 0. NAND Flash mode is disabled.
NAND Flash mode for chip select 2.
CS5NAND = 1. NAND Flash mode is enabled.
CS4ECC
•
CS3ECC
•
CS2ECC
•
CS5NAND
CS4NAND
CS3NAND
CS2NAND
•
•
•
•
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Registers
4
Registers
The external memory interface (EMIF) is controlled by programming its internal memory-mapped registers
(MMRs). Table 32 lists the memory-mapped registers for the EMIF. See the device-specific data manual
for the memory address of these registers. All other register offset addresses not listed in Table 32 should
be considered as reserved locations and the register contents should not be modified.
NOTE: The EMIF MMRs only support word (4 byte) accesses. Performing a byte (8 bit) or halfword
(16 bit) write to a register results in unknown behavior.
Table 32. External Memory Interface (EMIF) Registers
Offset
0
Acronym
RCSR
Register Description
Section
Revision Code and Status Register
4h
AWCCR
A1CR
Asynchronous Wait Cycle Configuration Register
Asynchronous 1 Configuration Register (CS2 space)
Asynchronous 2 Configuration Register (CS3 space)
Asynchronous 3 Configuration Register (CS4 space)
Asynchronous 4 Configuration Register (CS5 space)
EMIF Interrupt Raw Register
10h
14h
18h
1Ch
40h
44h
48h
4Ch
60h
64h
70h
74h
78h
7Ch
A2CR
A3CR
A4CR
EIRR
EIMR
EMIF Interrupt Mask Register
EIMSR
EMIF Interrupt Mask Set Register
EIMCR
EMIF Interrupt Mask Clear Register
NANDFCR
NANDFSR
NANDF1ECC
NANDF2ECC
NANDF3ECC
NANDF4ECC
NAND Flash Control Register
NAND Flash Status Register
NAND Flash 1 ECC Register (CS2 Space)
NAND Flash 2 ECC Register (CS3 Space)
NAND Flash 3 ECC Register (CS4 Space)
NAND Flash 4 ECC Register (CS5 Space)
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Registers
4.1 Revision Code and Status Register (RCSR)
Figure 20. Revision Code and Status Register (RCSR)
31
Reserved
R-x
30
29
16
0
MODID
R-Fh
15
8
7
REVMAJ
R-2h
REVMIN
R-2h
LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset
Table 33. Revision Code and Status Register (RCSR) Field Descriptions
Bit
Field
Value
0
Description
31-30 Reserved
29-16 MODID
Reserved
0-3FFFh
Fh
Module identification.
Asynchronous memory interface.
15-8
7-0
REVMAJ
REVMIN
0-FFh
Major Revision. EMIF code revisions are indicated by a revision code taking the format
REVMAJ.REVMIN.
2h
Current major revision.
0-FFh
Minor Revision. EMIF code revisions are indicated by a revision code taking the format
REVMAJ.REVMIN.
2h
Current minor revision.
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Registers
4.2 Asynchronous Wait Cycle Configuration Register (AWCCR)
The asynchronous wait cycle configuration register (AWCCR) is used to configure the parameters for
extended wait cycles. Both the polarity of the EM_WAIT[5:2] pins and the maximum allowable number of
NOTE: The EW bit in the asynchronous configuration register (ACFGn) must be set to allow for the
insertion of extended wait cycles.
Figure 21. Asynchronous Wait Cycle Configuration Register (AWCCR)
31
30
29
28
27
24
23
22
21
20
19
18
17
16
WP3
WP2
WP1
WP0
Reserved
R-0
CS5_WAIT
R/W-3h
CS4_WAIT
R/W-2h
CS3_WAIT
R/W-1
CS2_WAIT
R/W-0
R/W-1 R/W-1 R/W-1 R/W-1
15
8
7
0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
MEWC
R/W-80h
Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions
Bit
Field
Value Description
31
WP3
WAIT polarity bit. This bit defines the polarity of the EM_WAIT[5] pin.
0
1
Insert wait cycles if EM_WAIT[5] pin is low.
Insert wait cycles if EM_WAIT[5] pin is high.
WAIT polarity bit. This bit defines the polarity of the EM_WAIT[4] pin.
Insert wait cycles if EM_WAIT[4] pin is low.
Insert wait cycles if EM_WAIT[4] pin is high.
WAIT polarity bit. This bit defines the polarity of the EM_WAIT[3] pin.
Insert wait cycles if EM_WAIT[3] pin is low.
Insert wait cycles if EM_WAIT[3] pin is high.
WAIT polarity bit. This bit defines the polarity of the EM_WAIT[2] pin.
Insert wait cycles if EM_WAIT[2] pin is low.
Insert wait cycles if EM_WAIT[2] pin is high.
Reserved
30
29
28
WP2
WP1
WP0
0
1
0
1
0
1
27-24 Reserved
23-22 CS5_WAIT
0
0-3h
0
EM_WAIT[5:2] pin map for chip select 5. By default, the EM_WAIT[5] pin is used for chip select 5.
EM_WAIT[2] pin is used.
1h
2h
3h
0-3h
0
EM_WAIT[3] pin is used.
EM_WAIT[4] pin is used.
EM_WAIT[5] pin is used.
21-20 CS4_WAIT
19-18 CS3_WAIT
EM_WAIT[5:2] pin map for chip select 4. By default, the EM_WAIT[4] pin is used for chip select 4.
EM_WAIT[2] pin is used.
1h
2h
3h
0-3h
0
EM_WAIT[3] pin is used.
EM_WAIT[4] pin is used.
EM_WAIT[5] pin is used.
EM_WAIT[5:2] pin map for chip select 3. By default, the EM_WAIT[3] pin is used for chip select 3.
EM_WAIT[2] pin is used.
1h
2h
3h
EM_WAIT[3] pin is used.
EM_WAIT[4] pin is used.
EM_WAIT[5] pin is used.
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Registers
Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions (continued)
Bit
Field
Value Description
17-16 CS2_WAIT
0-3h
0
EM_WAIT[5:2] pin map for chip select 2. By default, the EM_WAIT[2] pin is used for chip select 2.
EM_WAIT[2] pin is used.
EM_WAIT[3] pin is used.
EM_WAIT[4] pin is used.
EM_WAIT[5] pin is used.
Reserved
1h
2h
3h
0
15-8
7-0
Reserved
MEWC
0-FFh Maximum extended wait cycles. The EMIF will wait for a maximum of (MEWC + 1) × 16 clock cycles
before it stops inserting asynchronous wait cycles and proceeds to the hold period of the access.
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Registers
4.3 Asynchronous n Configuration Registers (A1CR-A4CR)
The asynchronous configuration register (ACFGn) is used to configure the shaping of the address and
control signals during an access to asynchronous memory. It is also used to program the width of
asynchronous interface and to select from various modes of operation. This register can be written prior to
any transfer, and any asynchronous transfer following the write will use the new configuration. The ACFGn
is shown in Figure 22 and described in Table 35. There are four ACFGns. Each chip select space has a
dedicated ACFGn. This allows each chip select space to be programmed independently to interface to
different asynchronous memory types.
Figure 22. Asynchronous n Configuration Register (ACFGn)
31
SS
30
EW(A)
29
26
25
24
16
W_SETUP
R/W-Fh
W_STROBE(B)
R/W-3Fh
R/W-0
R/W-0
23
20
19
17
W_STROBE(B)
R/W-3Fh
12
W_HOLD
R/W-7h
R_SETUP
R/W-Fh
15
13
7
6
4
3
2
1
0
R_SETUP
R/W-Fh
R_STROBE(B)
R/W-3Fh
R_HOLD
R/W-7h
TA
ASIZE
R/W-0
R/W-3h
LEGEND: R/W = Read/Write; -n = value after reset
A. The EW bit must be cleared to 0 when operating in NAND Flash mode.
B. The W_STROBE and R_STROBE bits must not be cleared to 0 when operating in Extended Wait mode.
Table 35. Asynchronous n Configuration Register (ACFGn) Field Descriptions
Bit
Field
Value Description
31
SS
Select Strobe bit. This bit defines whether the asynchronous interface operates in Normal mode or
0
1
Normal mode is enabled.
Select Strobe mode is enabled.
30
EW
cycles for details. This bit must be cleared to 0, if the EMIF on your device does not have a
EM_WAIT pin.
0
1
Extended wait cycles are disabled.
Extended wait cycles are enabled.
29-26 W_SETUP
25-20 W_STROBE
19-17 W_HOLD
16-13 R_SETUP
0-Fh
0-7h
0-Fh
12-7
6-4
R_STROBE
R_HOLD
TA
0-7h
0-3h
3-2
Minimum Turn-Around time. This field defines the minimum number of EMIF clock cycles between
the end of one asynchronous access and the start of another, minus 1 cycle. This delay is not
incurred by a read followed by a read or a write followed by a write to the same CS space. See
Section 2.5.3 for details.
1-0
ASIZE
0-3h
0
Asynchronous data bus width. This bit defines the width of the asynchronous device's data bus.
8-bit data bus
16-bit data bus
1h
2h-3h Reserved
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Registers
4.4 EMIF Interrupt Raw Register (EIRR)
The EMIF interrupt raw register (EIRR) is used to monitor and clear the EMIF’s hardware-generated
interrupts. The bits in EIRR are set when an interrupt condition occurs, regardless of the status of the
EMIF interrupt mask set register (EIMSR) and EMIF interrupt mask clear register (EIMCR). Writing a 1 to
a bit clears the bit and the corresponding bit in the EMIF interrupt mask register (EIMR). The EIRR is
Figure 23. EMIF Interrupt Raw Register (EIRR)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
Reserved
R-0
WR3
WR2
WR1
WR0
Reserved
R-0
AT
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 36. EMIF Interrupt Raw Register (EIRR) Field Descriptions
Bit
Field
Value Description
31-6
Reserved
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
5
4
3
2
WR3
WR2
WR1
WR0
Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[5] pin has
occurred.
0
1
Indicates that a rising edge has not occurred on the EM_WAIT[5] pin. Writing a 0 has no effect.
Indicates that a rising edge has occurred on the EM_WAIT[5] pin. Writing a 1 will clear this bit and the
WRM3 bit in the EMIF interrupt mask register (EIMR).
Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[4] pin has
occurred.
0
1
Indicates that a rising edge has not occurred on the EM_WAIT[4] pin. Writing a 0 has no effect.
Indicates that a rising edge has occurred on the EM_WAIT[4] pin. Writing a 1 will clear this bit and the
WRM2 bit in the EMIF interrupt mask register (EIMR).
Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[3] pin has
occurred.
0
1
Indicates that a rising edge has not occurred on the EM_WAIT[3] pin. Writing a 0 has no effect.
Indicates that a rising edge has occurred on the EM_WAIT[3] pin. Writing a 1 will clear this bit and the
WRM1 bit in the EMIF interrupt mask register (EIMR).
Wait Rise. This bit is set to 1 by hardware to indicate that a rising edge on the EM_WAIT[0] pin has
occurred.
0
1
Indicates that a rising edge has not occurred on the EM_WAIT[0] pin. Writing a 0 has no effect.
Indicates that a rising edge has occurred on the EM_WAIT[0] pin. Writing a 1 will clear this bit and the
WRM0 bit in the EMIF interrupt mask register (EIMR).
1
0
Reserved
AT
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
Asynchronous Timeout. This bit is set to 1 by hardware to indicate that during an extended
asynchronous memory access cycle the EM_WAITn pin did not go inactive within the number of cycles
defined by the MEWC field in the asynchronous wait cycle configuration register (AWCCR).
0
1
Indicates that an asynchronous timeout has not occurred. Writing a 0 has no effect.
Indicates that an asynchronous timeout has occurred. Writing a 1 will clear this bit and the ATM bit in
the EMIF interrupt mask register (EIMR).
53
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Registers
4.5 EMIF Interrupt Mask Register (EIMR)
Similar to the EMIF interrupt raw register (EIRR), the EMIF interrupt mask register (EIMR) is used to
monitor and clear the status of the EMIF’s hardware-generated interrupts. The main difference between
the two registers is that when the bits in EIMR are set, an active-high pulse is sent to the CPU interrupt
controller. Also, the bits in EIMR are only set to 1, if the associated interrupt has been enabled in the
Figure 24. EMIF Interrupt Mask Register (EIMR)
31
16
Reserved
R-0
15
7
8
Reserved
R-0
6
5
4
3
2
1
0
Reserved
R-0
WRM3
R/W1C-0
WRM2
WRM1
R/W1C-0
WRM0
R/W1C-0
Reserved
R-0
ATM
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions
Bit
Field
Value Description
31-6
Reserved
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
5
4
3
2
1
WRM3
WRM2
WRM1
WRM0
Reserved
Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
EM_WAIT[5] pin, provided that the WRMSET3 bit is set to 1 in the EMIF interrupt mask set register
(EIMSR).
0
1
Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM3 bit in
the EMIF interrupt raw register (EIRR).
Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
EM_WAIT[4] pin, provided that the WRMSET2 bit is set to 1 in the EMIF interrupt mask set register
(EIMSR).
0
1
Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM2 bit in
the EMIF interrupt raw register (EIRR).
Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
EM_WAIT[3] pin, provided that the WRMSET1 bit is set to 1 in the EMIF interrupt mask set register
(EIMSR).
0
1
Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM1 bit in
the EMIF interrupt raw register (EIRR).
Wait Rise Masked. This bit is set to 1 by hardware to indicate a rising edge has occurred on the
EM_WAIT[2] pin, provided that the WRMSET0 bit is set to 1 in the EMIF interrupt mask set register
(EIMSR).
0
1
Indicates that a wait rise interrupt has not been generated. Writing a 0 has no effect.
Indicates that a wait rise interrupt has been generated. Writing a 1 will clear this bit and the WRM0 bit in
the EMIF interrupt raw register (EIRR).
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
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Registers
Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions (continued)
Bit
Field
ATM
Value Description
0
Asynchronous Timeout Masked. This bit is set to 1 by hardware to indicate that during an extended
asynchronous memory access cycle the EM_WAITn pin did not go inactive within the number of cycles
defined by the MEWC field in the asynchronous wait cycle configuration register (AWCCR), provided
that the ATMSET bit is set to 1 in the EMIF interrupt mask set register (EIMSR).
0
1
Indicates that an asynchronous timeout interrupt has not been generated. Writing a 0 has no effect.
Indicates that an asynchronous timeout interrupt has been generated. Writing a 1 will clear this bit and
the AT bit in the EMIF interrupt raw register (EIRR).
55
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Registers
4.6 EMIF Interrupt Mask Set Register (EIMSR)
The EMIF interrupt mask set register (EIMSR) is used to enable the interrupts. If a bit is set to 1, the
corresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when the
associated interrupt condition occurs. If a bit is cleared to 0, the the corresponding bit in EIMR will always
read 0 and no interrupts are generated when the associated interrupt condition occurs. Writing a 1 to the
Figure 25. EMIF Interrupt Mask Set Register (EIMSR)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
Reserved
R-0
WRMSET3
R/W1S-0
WRMSET2
R/W1S-0
WRMSET1
R/W1S-0
WRMSET0
R/W1S-0
Reserved
R-0
ATMSET
R/W1S-0
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing 0 has no effect); -n = value after reset
Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions
Bit
Field
Value Description
31-6
Reserved
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
5
4
3
2
1
WRMSET3
WRMSET2
WRMSET1
WRMSET0
Reserved
Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the
WRMCLR3 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To
clear this bit, a 1 must be written to the WRMCLR3 bit in EIMCR.
0
1
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR3 bit in
EIMCR.
Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the
WRMCLR2 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To
clear this bit, a 1 must be written to the WRMCLR2 bit in EIMCR.
0
1
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR2 bit in
EIMCR.
Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the
WRMCLR1 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To
clear this bit, a 1 must be written to the WRMCLR1 bit in EIMCR.
0
1
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR1 bit in
EIMCR.
Wait Rise Mask Set. This bit enables the wait rise interrupt. Writing a 1 to this bit sets this bit and the
WRMCLR0 bit in the EMIF interrupt mask clear register (EIMCR), and enables the wait rise interrupt. To
clear this bit, a 1 must be written to the WRMCLR0 bit in EIMCR.
0
1
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
Indicates that the wait rise interrupt is enabled. Writing a 1 sets this bit and the WRMCLR0 bit in
EIMCR.
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
56
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Registers
Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions (continued)
Bit
Field
ATMSET
Value Description
0
Asynchronous Timeout Mask Set. This bit enables the asynchronous timeout interrupt. Writing a 1 to
this bit sets this bit and the ATMCLR bit in the EMIF interrupt mask clear register (EIMCR), and enables
the asynchronous timeout interrupt. To clear this bit, a 1 must be written to the ATMCLR bit in EIMCR.
0
1
Indicates that the asynchronous timeout interrupt is disabled. Writing a 0 has no effect.
Indicates that the asynchronous timeout interrupt is enabled. Writing a 1 sets this bit and the ATMCLR
bit in EIMCR.
57
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Registers
4.7 EMIF Interrupt Mask Clear Register (EIMCR)
The EMIF interrupt mask clear register (EIMCR) is used to disable the interrupts. If a bit is read as 1, the
corresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when the
associated interrupt condition occurs. If a bit is read as 0, the corresponding bit in EIMR will always read 0
and no interrupts are generated when the corresponding interrupt condition occurs. Writing a 1 to the
Figure 26. EMIF Interrupt Mask Clear Register (EIMCR)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
Reserved
R-0
WRMCLR3
R/W1C-0
WRMCLR2
R/W1C-0
WRMCLR1
R/W1C-0
WRMCLR0
R/W1C-0
Reserved
R-0
ATMCLR
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions
Bit
Field
Value Description
31-6
Reserved
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
5
4
3
2
1
WRMCLR3
WRMCLR2
WRMCLR1
WRMCLR0
Reserved
Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. Writing a 1
to this bit clears this bit and the WRMSET3 bit in the EMIF interrupt mask set register (EIMSR), and
disables the wait rise interrupt. To set this bit, a 1 must be written to the WRMSET3 bit in EIMSR.
0
1
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
Indicates that the wait rise interrupt is enabled. Writing a 1 clears this bit and the WRMSET3 bit in
EIMSR.
Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. Writing a 1
to this bit clears this bit and the WRMSET2 bit in the EMIF interrupt mask set register (EIMSR), and
disables the wait rise interrupt. To set this bit, a 1 must be written to the WRMSET2 bit in EIMSR.
0
1
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
Indicates that the wait rise interrupt is enabled. Writing a 1 clears this bit and the WRMSET2 bit in
EIMSR.
Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. Writing a 1
to this bit clears this bit and the WRMSET1 bit in the EMIF interrupt mask set register (EIMSR), and
disables the wait rise interrupt. To set this bit, a 1 must be written to the WRMSET1 bit in EIMSR.
0
1
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
Indicates that the wait rise interrupt is enabled. Writing a 1 clears this bit and the WRMSET1 bit in
EIMSR.
Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. Writing a 1
to this bit clears this bit and the WRMSET0 bit in the EMIF interrupt mask set register (EIMSR), and
disables the wait rise interrupt. To set this bit, a 1 must be written to the WRMSET0 bit in EIMSR.
0
1
Indicates that the wait rise interrupt is disabled. Writing a 0 has no effect.
Indicates that the wait rise interrupt is enabled. Writing a 1 clears this bit and the WRMSET0 bit in
EIMSR.
0
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default
value of 0.
58
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Registers
Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions (continued)
Bit
Field
ATMCLR
Value Description
0
Asynchronous Timeout Mask Clear. This bit determines whether or not the asynchronous timeout
interrupt is enabled. Writing a 1 to this bit clears this bit and the ATMSET bit in the EMIF interrupt mask
set register (EIMSR), and disables the asynchronous timeout interrupt. To set this bit, a 1 must be
written to the ATMSET bit in EIMSR.
0
1
Indicates that the asynchronous timeout interrupt is disabled. Writing a 0 has no effect.
Indicates that the asynchronous timeout interrupt is enabled. Writing a 1 clears this bit and the ATMSET
bit in EIMSR.
59
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Registers
4.8 NAND Flash Control Register (NANDFCR)
Figure 27. NAND Flash Control Register (NANDFCR)
31
16
Reserved
R-0
15
7
12
4
11
10
9
8
Reserved
R-0
CS5ECC
R/W-0
CS4ECC
R/W-0
CS3ECC
R/W-0
CS2ECC
R/W-0
3
2
1
0
Reserved
R-0
CS5NAND
R/W-0
CS4NAND
R/W-0
CS3NAND
R/W-0
CS2NAND
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 40. NAND Flash Control Register (NANDFCR) Field Descriptions
Bit
Field
Value Description
31-12 Reserved
0
Reserved
11
10
9
CS5ECC
CS4ECC
CS3ECC
CS2ECC
NAND Flash ECC start for chip select 5.
Do not start ECC calculation.
0
1
Start ECC calculation on data for NAND Flash on EM_CS5.
NAND Flash ECC start for chip select 4.
Do not start ECC calculation.
0
1
Start ECC calculation on data for NAND Flash on EM_CS4.
NAND Flash ECC start for chip select 3.
Do not start ECC calculation.
0
1
Start ECC calculation on data for NAND Flash on EM_CS3.
NAND Flash ECC start for chip select 2.
Do not start ECC calculation.
8
0
1
0
Start ECC calculation on data for NAND Flash on EM_CS2.
Reserved
7-4
3
Reserved
CS5NAND
NAND Flash mode for chip select 5.
Not using NAND Flash.
0
1
Using NAND Flash on EM_CS5.
NAND Flash mode for chip select 4.
Not using NAND Flash.
2
1
0
CS4NAND
CS3NAND
CS2NAND
0
1
Using NAND Flash on EM_CS4.
NAND Flash mode for chip select 3.
Not using NAND Flash.
0
1
Using NAND Flash on EM_CS3.
NAND Flash mode for chip select 2.
Not using NAND Flash.
0
1
Using NAND Flash on EM_CS2.
60
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Registers
4.9 NAND Flash Status Register (NANDFSR)
Figure 28. NAND Flash Status Register (NANDFSR)
31
16
Reserved
R-0
15
4
3
0
WAITST
R-0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 41. NAND Flash Status Register (NANDFSR) Field Descriptions
Bit
31-4
3-0
Field
Value Description
Reserved
WAITST
0
Reserved
0-Fh
Raw status of the EM_WAITn input pin. The WPn bit in the asynchronous wait cycle configuration
register (AWCCR) has no effect on WAITST.
4.10 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC)
NAND Flash, P1O, P2O, and P4O bits are column parities; P8O to P2048O bits are row parities. For
16-bit NAND Flash, P1O, P2O, P4O, and P8O bits are column parities; P16O to P2048O bits are row
parities.
61
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Registers
Figure 29. NAND Flash n ECC Register (NANDECCn)
31
28
27
P2048O
R-0
26
P1024O
R-0
25
P512O
R-0
24
P256O
R-0
Reserved
R-0
23
P128O
R-0
22
P64O
R-0
21
P32O
R-0
20
P16O
R-0
19
18
17
16
P8O
R-0
P4O
R-0
P2O
R-0
P1O
R-0
15
12
11
P2048E
R-0
10
P1024E
R-0
9
8
Reserved
R-0
P512E
R-0
P256E
R-0
7
6
5
4
3
2
1
0
P128E
R-0
P64E
R-0
P32E
R-0
P16E
R-0
P8E
R-0
P4E
R-0
P2E
R-0
P1E
R-0
LEGEND: R = Read only; -n = value after reset
Table 42. NAND Flash n ECC Register (NANDECCn) Field Descriptions
Bit
Field
Value Description
31-28 Reserved
0
Reserved
27
26
25
24
23
22
21
20
19
18
17
16
P2048O
P1024O
P512O
P256O
P128O
P64O
P32O
P16O
P8O
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
Reserved
P4O
P2O
P1O
15-12 Reserved
11
10
9
P2048E
P1024E
P512E
P256E
P128E
P64E
P32E
P16E
P8E
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
ECC code calculated while reading/writing NAND Flash.
8
7
6
5
4
3
2
P4E
1
P2E
0
P1E
62
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Appendix A Revision History
Table 43 lists the changes made since the previous version of this document.
Table 43. Document Revision History
Reference
Additions/Modifications/Deletions
Changed figure.
Changed table.
Changed figure.
Changed paragraph.
Changed figure.
63
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Revision History
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