Sony Camera Accessories ICX274AQ User Manual

ICX274AQ

Diagonal 8.923mm (Type 1/1.8) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras

Description

The ICX274AQ is a diagonal 8.923mm (Type 1/1.8)

interline CCD solid-state image sensor with a square

pixel array and 2.01M effective pixels. Progressive

scan allows all pixels' signals to be output

independently within approximately 1/15 second,

and output is also possible using various addition

and pulse elimination methods. This chip features an

electronic shutter with variable charge-storage time

which makes it possible to realize full-frame still

images without a mechanical shutter. High resolution

and high color reproductivity are achieved through

the use of R, G, B primary color mosaic filters as the

color filters. Further, high sensitivity and low dark

current are achieved through the adoption of Super

HAD CCD technology.

20 pin DIP (Plastic)

This chip is suitable for applications such as

electronic still cameras, PC input cameras, etc.

Features

• High horizontal and vertical resolution

• Supports the following modes

Progressive scan mode (with/without mechanical shutter)

2/8-line readout mode

Pin 1

2/4-line readout mode

2-line addition mode

Center scan modes (1), (2) and (3)

AF modes (1) and (2)

• Square pixel

• Horizontal drive frequency: 28.6364MHz (typ.), 36.0MHz (max.)

• Reset gate bias are not adjusted

• R, G, B primary color mosaic filters on chip

• High sensitivity, low dark current

• Continuous variable-speed shutter function

• Excellent anti-blooming characteristics

• 20-pin high-precision plastic package

Pin 11

Optical black position

(Top View)

Device Structure

• Interline CCD image sensor

• Image size:

Diagonal 8.923mm (Type 1/1.8)

1688 (H) × 1248 (V) approx. 2.11M pixels

• Total number of pixels:

• Number of effective pixels: 1628 (H) × 1236 (V) approx. 2.01M pixels

• Number of active pixels:

• Recommended number of

recording pixels:

1620 (H) × 1220 (V) approx. 1.98M pixels

1600 (H) × 1200 (V) approx. 1.92M pixels

8.50mm (H) × 6.80mm (V)

• Chip size:

• Unit cell size:

4.40µm (H) × 4.40µm (V)

• Optical black:

Horizontal (H) direction: Front 12 pixels, rear 48 pixels

Vertical (V) direction:

Horizontal 28

Vertical 1

Front 10 pixels, rear 2 pixels

• Number of dummy bits:

• Substrate material:

Silicon

∗

Wfine CCD is trademark of Sony corporation.

Represents a CCD adopting progressive scan, primary color filter and square pixel.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E01410B23-PS

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ICX274AQ

Absolute Maximum Ratings

Item

Ratings

–40 to +12

–50 to +15

–50 to +0.3

–40 to +0.3

–25 to

Unit Remarks

V^DD, VOUT, φRG – φSUB

Vφ^2α, Vφ3α – φSUB (α = A to C)

Vφ1, Vφ4, VL – φSUB

Against φSUB

Hφ1β, Hφ2β, GND – φSUB (β = A, B)

CSUB – φSUB

VDD, VOUT, φRG, CSUB – GND

Vφ1, Vφ2α, Vφ3α, Vφ4 – GND (α = A to C)

Hφ1β, Hφ2β – GND (β = A, B)

–0.3 to +22

–10 to +18

–10 to +6.5

–0.3 to +28

–0.3 to +15

to +15

Against GND

Against VL

Vφ2α, Vφ3α – VL (α = A to C)

Vφ1, Vφ4, Hφ1β, Hφ2β, GND – VL (β = A, B)

Voltage difference between vertical clock input pins

Hφ1β – Hφ2β (β = A, B)

∗²

Between input

clock pins

–6.5 to +6.5

–10 to +16

–30 to +80

–10 to +60

–10 to +75

Hφ1β, Hφ2β – Vφ4 (β = A, B)

Storage temperature

°C

Guaranteed temperature of performance

Operating temperature

∗²

+24V (Max.) is guaranteed when clock width < 10µs, clock duty factor < 0.1%.

+16V (Max.) is guaranteed during power-on or power-off.

– 3 –

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ICX274AQ

Bias Conditions

Item

Symbol

V^DD

Min.

Typ.

Max.

Unit Remarks

Supply voltage

14.55

15.0

15.45

∗³

Protective transistor bias

∗¹

VSUB

VSUB2

Internally generated value

14.4

No line addition

Substrate voltage

adjustment range

∗⁴

∗

2-line addition

8.8

Indicated

voltage – 0.2

Indicated

voltage

Indicated

voltage + 0.2

Substrate voltage adjustment accuracy ∆VSUB

Reset gate clock φRG

∗⁵

∗¹

Progressive scan mode, 2/8-line readout mode, 2/4-line readout mode, center scan modes (1) and (3),

and AF modes (1) and (2)

∗²

∗³

2-line addition mode and center scan mode (2)

VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply

for the V driver should be used.

∗⁴

Substrate voltage (VSUB2) setting value indication

The substrate voltage (VSUB) for modes without line addition is generated internally.

The substrate voltage setting value for use with vertical 2-line addition is indicated by a code on the

bottom surface of the image sensor. Adjust the substrate voltage to the indicated voltage.

VSUB2 code – 1-digit indication

↑

VSUB2 code

The code and the actual value correspond as follows.

VSUB2 code

Actual value 8.8 9.0 9.2 9.4 9.6 9.8 10.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6

VSUB2 code

Actual value 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 13.4 13.6 13.8 14.0 14.2 14.4

[Example] "h" indicates a VSUB2 setting of 11.6V.

∗⁵

Do not apply a DC bias to the reset gate clock pin, because a DC bias is generated within the CCD.

DC characteristics

Item

Symbol

Min.

7.0

Typ.

10.0

Max.

13.0

Unit

Remarks

Supply current

IDD

– 4 –

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ICX274AQ

Clock Voltage Conditions

Waveform

diagram

Item

Symbol

Min.

Typ.

Max. Unit

Remarks

Readout clock

voltage

V^VT

14.55 15.0 15.45

VVH1, VVH2

VVH3, VVH4

–0.05

0.05

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2

–0.2

VVL1, VVL2,

V^VL3, VVL4

–8.0

–7.5

–7.0

VφV

6.8

7.5

8.05

0.1

VφV = VVHn – VVLn (n = 1 to 4)

Vertical transfer

clock voltage

VVH3 – VVH

VVH4 – VVH

VVHH

–0.25

0.1

0.5

High-level coupling

Low-level coupling

VVHL

0.5

VVLH

0.5

VVLL

0.5

VφH

4.75

–0.05

0.8

5.0

5.25

0.05

Horizontal transfer

clock voltage

VHL

VCR

2.5

3.3

Cross-point voltage

VφRG

3.0

5.25

0.4

Reset gate clock

voltage

VRGLH – VRGLL

VRGL – VRGLm

Low-level coupling

0.5

Substrate clock

voltage

VφSUB

21.5

22.5

23.5

– 5 –

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ICX274AQ

Clock Equivalent Circuit Constants

Item

Symbol

Min.

Typ.

3300

1200

2700

1000

1800

6800

120

220

150

270

2700

470

680

1000

820

1800

820

1500

100

Max. Unit Remarks

CφV1

CφV2A, CφV2B

Ω

Capacitance between vertical transfer clock and CφV2C

GND

CφV3A, CφV3B

CφV3C

CφV4

CφV12 (A, B)

CφV12C

CφV13 (A, B)

CφV13C

CφV14

CφV2 (A, B), 3 (A, B)

CφV2 (A, B), 3C

CφV2 (A, B), 4

CφV2C, 3 (A, B)

CφV2C, 3C

CφV2C, 4

Capacitance between vertical transfer clocks

CφV3 (A, B), 4

CφV3C, 4

CφH1

Capacitance between horizontal transfer clock

and GND

CφH2

Capacitance between horizontal transfer clocks

CφHH

Capacitance between reset gate clock and GND CφRG

Capacitance between substrate clock and GND

CφSUB

820

R1, R4

Vertical transfer clock series resistor

R2 (A, B, C), 3 (A, B, C)

RGND

Ω

Vertical transfer clock ground resistor

Horizontal transfer clock series resistor

Horizontal transfer clock ground resistor

Reset gate clock and series resistor

Ω

RφH

Ω

RφH2

kΩ

Ω

RφRG

4.7

Note 1) Expressions using parentheses such as CφV2 (A,B), 3C indicate items which include all combinations of

the pins within the parentheses.

For example, CφV2 (A, B), 3C indicates [CφV2A3C, CφV2B3C].

– 6 –

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ICX274AQ

Vφ1

RφH

Hφ1A

Hφ2A

CφV1

RφH

Hφ1B

Hφ2B

CφHH

CφV14

CφV2α4 (α = A to C)

CφV12α (α = A to C)

RφH2

CφH2

CφH1

Vφ4

Vφ2α (α = A to C)

2α (α = A to C)

RGND

CφV4

CφV3α4 (α = A to C)

CφV2α (α = A to C)

Horizontal transfer clock equivalent circuit

CφV2α3α (α = A to C)

CφV3α (α = A to C)

3α (α = A to C)

CφV13α (α = A to C)

RφRG

RGφ

Vφ3α (α = A to C)

CφRG

Note 2) Cφ^2α2βand Cφ3α3β (α = A to C, β = A to C other than α) are

sufficiently small relative to other capacitance between

other vertical clocks in the equivalent circuit, so these

are omitted from the equivalent circuit diagram.

Vertical transfer clock equivalent circuit

Reset gate clock equivalent circuit

– 7 –

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ICX274AQ

Drive Clock Waveform Conditions

(1) Readout clock waveform

100%

90%

φM

VVT

φM

10%

twh

(2) Vertical transfer clock waveform

Vφ1

Vφ3A, Vφ3B, Vφ3C

VVHH

VVH1

VVHH

VVH

VVHH

VVHL

VVH3

VVHL

VVL1

VVL3

VVLH

VVLL

VVL

Vφ2A, Vφ2B, Vφ2C

VVHH

Vφ4

VVHH

VVH

VVHL

VVH2

VVH4

VVLH

_VL2VVLH

VVLL

VVL

VVL4

VVL

V^VH= (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2

VφV = VVHn – VVLn (n = 1 to 4)

– 8 –

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ICX274AQ

(3) Horizontal transfer clock waveform

twh

Hφ²β

90%

VCR

Vφ^H

twl

VφH

10%

Hφ¹β

VHL

two

Cross-point voltage for the Hφ1β rising side of the horizontal transfer clocks Hφ1β and Hφ2β waveforms is VCR.

The overlap period for twh and twl of horizontal transfer clocks Hφ1β and Hφ2β is two. (β = A, B)

(4) Reset gate clock waveform

twh

VRGH

RG waveform

twl

VφRG

Point A

VRGLH

VRGL

VRGLL

VRGLm

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from

Point A in the above diagram until the rising edge of RG.

In addition, VRGL is the average value of VRGLH and VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL

Negative overshoot level during the falling edge of RG is VRGLm.

(5) Substrate clock waveform

100%

90%

φM

VφSUB

φM

10%

VSUB

(Internally generated bias)

twh

– 9 –

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ICX274AQ

Clock Switching Characteristics (Horizontal drive frequency: 28.6364MHz)

twh

twl

Item

Symbol

V^T

Unit Remarks

Min. Typ. Max.Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

During

Readout clock

3.3 3.5

0.5

µs

readout

Vφ1, Vφ4,

Vφ2α, Vφ3α

(α = A to C)

Vertical transfer

clock

∗¹

∗²

400 ns

Hφ1β (β = A, B) 10 12.5

10 12.5

7.5

Horizontal

transfer clock

Hφ2β (β = A, B) 10 12.5

Reset gate clock φ^RG

During drain

charge

φSUB

µs

0.5

Substrate clock

2.1

0.5

two

Item

Symbol

Unit Remarks

Min. Typ. Max.

Horizontal

transfer clock

Hφ1A, Hφ1B,

Hφ2A, Hφ2B

Clock Switching Characteristics (Horizontal drive frequency: 36MHz)

twh

twl

Item

Symbol

V^T

Unit Remarks

Min. Typ. Max.Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

During

µs

Readout clock

4.0 4.2

0.5

readout

Vφ1, Vφ4,

Vφ^2α, Vφ3α

(α = A to C)

Vertical transfer

clock

∗¹

∗²

400 ns

Hφ1β (β = A, B) 8

Horizontal

transfer clock

Hφ2β (β = A, B) 8

Reset gate clock φ^RG

5.5

During drain

charge

φSUB

µs

0.25

Substrate clock

1.67

0.25

two

Item

Symbol

Unit Remarks

Min. Typ. Max.

Horizontal

transfer clock

Hφ1A, Hφ1B,

Hφ^2A, Hφ2B

∗¹

When two vertical transfer clock drivers CXD3400N are used.

∗²

tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1β (β = A, B) rising side of the Hφ1β and Hφ2β

waveforms must be VφH/2 [V] or more.

– 10 –

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ICX274AQ

Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)

1.0

0.8

0.6

0.4

0.2

400

450

500

550

600

650

700

Wave Length [nm]

– 11 –

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ICX274AQ

Image Sensor Characteristics

(Ta = 25°C)

Measurement

method

Item

Symbol Min.

Typ.

Max. Unit

Remarks

G Sensitivity

335

0.35

0.45

400

420

0.5

0.6

545

0.65

0.75

1/30s accumulation

Sensitivity

comparison

∗

Vsat

Vsat2

No line addition

Saturation signal

Smear

Ta = 60°C

∗

2-line addition

∗⁴

Progressive scan mode

–100

–94

–92

–86

–80

∗

2/4-line readout mode

2/8-line readout mode

Zone 0 and I

∗⁶

–88

Video signal shading SH

Zone 0 to II’

∆Srg

Uniformity between

video signal channels

∆Sbg

Vdt

Dark signal

Dark signal shading

Line crawl G

Line crawl R

Line crawl B

Lag

Ta = 60°C, 14.985 frame/s

∗⁷

∆Vdt

Lcg

Lcr

Ta = 60°C, 14.985 frame/s,

3.8

0.5

Lcb

Lag

∗

Vsat2 is the saturation signal level in 2-line addition mode, and is 200mV per pixel.

∗

Progressive scan mode, 2/8-line readout mode, 2/4-line readout mode, and center scan modes (1) and (3).

2-line addition mode and center scan mode (2).

∗

Same for 2-line addition mode and center scan modes (2) and (3).

Same for center scan mode (1).

∗

Same for AF modes (1) and (2).

∗

Excludes vertical dark signal shading caused by vertical register high-speed transfer.

– 12 –

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ICX274AQ

Zone Definition of Video Signal Shading

1628 (H)

1236 (V)

Zone 0, I

Zone II, II’

Ignored region

Effective pixel region

Measurement System

∗

CCD signal output [ A]

∗

CCD

C.D.S

AMP

Gr/Gb channel signal output [ B]

S/H

∗

R/B channel signal output [ C]

∗

Note) Adjust the amplifier gain so that the gain between [ A] and [ B], and between [ A] and [ C] equals 1.

Image Sensor Characteristics Measurement Method

Color coding of this image sensor & Readout

The primary color filters of this image sensor are arranged in the layout

shown in the figure on the left (Bayer arrangement).

Gr and Gb denote the G signals on the same line as the R signal and the

B signal, respectively.

Horizontal register

Color Coding Diagram

– 13 –

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ICX274AQ

Readout modes

The diagrams below and on the following pages show the output methods for the following nine readout

modes.

Progressive scan mode

2/8-line readout mode

2/4-line readout mode

16 (V2C/V3C)

15 (V2C/V3C)

14 (V2A/V3A)

13 (V2B/V3B)

12 (V2C/V3C)

11 (V2C/V3C)

10 (V2B/V3B)

9 (V2A/V3A)

8 (V2C/V3C)

7 (V2C/V3C)

6 (V2A/V3A)

5 (V2B/V3B)

4 (V2C/V3C)

3 (V2C/V3C)

2 (V2B/V3B)

1 (V2A/V3A)

15 (V2C/V3C)

14 (V2A/V3A)

13 (V2B/V3B)

12 (V2C/V3C)

11 (V2C/V3C)

10 (V2B/V3B)

9 (V2A/V3A)

8 (V2C/V3C)

7 (V2C/V3C)

6 (V2A/V3A)

5 (V2B/V3B)

4 (V2C/V3C)

3 (V2C/V3C)

2 (V2B/V3B)

1 (V2A/V3A)

15 (V2C/V3C)

14 (V2A/V3A)

13 (V2B/V3B)

12 (V2C/V3C)

11 (V2C/V3C)

10 (V2B/V3B)

9 (V2A/V3A)

8 (V2C/V3C)

7 (V2C/V3C)

6 (V2A/V3A)

5 (V2B/V3B)

4 (V2C/V3C)

3 (V2C/V3C)

2 (V2B/V3B)

1 (V2A/V3A)

V^OUT

VOUT

V^OUT

Note) Blacked out portions in the diagram indicate pixels which are not read out.

Output starts from line 1 in 2/8-line decimation mode.

1. Progressive scan mode

In this mode, all pixel signals are output in non-interlace format in 1/14.985s.

All pixel signals within the same exposure period are read out simultaneously, making this mode suitable

for high resolution image capturing.

2. 2/8-line readout mode

All effective area signals are output in approximately 1/30s by reading out the signals for only two out of

eight lines (1st and 6th lines, 9th and 14th lines).

This readout mode emphasizes processing speed over vertical resolution, making it suitable for AE/AF and

other control and for checking images on LCD viewfinders.

3. 2/4-line readout mode

All effective area signals are output in approximately 1/20s by reading out the signals for only two out of

four lines (3rd and 4th lines, 7th and 8th lines, and so on).

– 14 –

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ICX274AQ

2-line addition mode

Center scan mode (1)

Center scan mode (2)

16 (V2C/V3C)

15 (V2C/V3C)

14 (V2A/V3A)

13 (V2B/V3B)

12 (V2C/V3C)

11 (V2C/V3C)

10 (V2B/V3B)

9 (V2A/V3A)

8 (V2C/V3C)

7 (V2C/V3C)

6 (V2A/V3A)

5 (V2B/V3B)

4 (V2C/V3C)

3 (V2C/V3C)

2 (V2B/V3B)

1 (V2A/V3A)

15 (V2C/V3C)

14 (V2A/V3A)

13 (V2B/V3B)

12 (V2C/V3C)

11 (V2C/V3C)

10 (V2B/V3B)

9 (V2A/V3A)

8 (V2C/V3C)

7 (V2C/V3C)

6 (V2A/V3A)

5 (V2B/V3B)

4 (V2C/V3C)

3 (V2C/V3C)

2 (V2B/V3B)

1 (V2A/V3A)

15 (V2C/V3C)

14 (V2A/V3A)

13 (V2B/V3B)

12 (V2C/V3C)

11 (V2C/V3C)

10 (V2B/V3B)

9 (V2A/V3A)

8 (V2C/V3C)

7 (V2C/V3C)

6 (V2A/V3A)

5 (V2B/V3B)

4 (V2C/V3C)

3 (V2C/V3C)

2 (V2B/V3B)

1 (V2A/V3A)

V^OUT

VOUT

Note) Blacked out portions in the diagram indicate pixels which are not read out.

After reading out the pixels indicated by and transferring two lines, the pixels indicated by

are read out and two pixels of the same color are added by the vertical transfer block.

4. 2-line addition mode

In this mode, the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are

read out, the vertical register is shifted by 2 bits, and then the signals of the remaining two out of the four

lines (1st and 2nd lines, 5th and 6th lines, and so on) are read out and added within the vertical register. All

effective area signals are output in approximately 1/20s.

5. Center scan mode (1)

In this mode, the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are

read out. The undesired portions are swept by vertical register high-speed transfer, and the vertical

1136-pixel region in the center of the picture is output by the above readout method. The number of

output lines is 568 lines at 36MHz, and 434 lines at 28.6364MHz. The frame rate is increased

(approximately 30 frames/s) by setting the number of output lines to that of VGA mode, making this

mode suitable for VGA moving pictures. (However, the angle of view decreases.)

6. Center scan mode (2)

In this mode, the signals for only two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are

read out, the vertical register is shifted by 2 bits, and then the signals of the remaining two out of the four

lines (1st and 2nd lines, 5th and 6th lines, and so on) are read out and added within the vertical register.

The undesired portions are swept by vertical register high-speed transfer, and the vertical 1136-pixel region

in the center of the picture is output by the above readout method. The number of output lines is 568 lines

at 36MHz, and 434 lines at 28.6364MHz. The frame rate is increased (approximately 30 frames/s) by

setting the number of output lines to that of VGA mode, making this mode suitable for VGA moving pictures.

(However, the angle of view decreases.)

– 15 –

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ICX274AQ

Center scan mode (3)

AF mode (1)

AF mode (2)

16 (V2C/V3C)

15 (V2C/V3C)

14 (V2A/V3A)

13 (V2B/V3B)

12 (V2C/V3C)

11 (V2C/V3C)

10 (V2B/V3B)

9 (V2A/V3A)

8 (V2C/V3C)

7 (V2C/V3C)

6 (V2A/V3A)

5 (V2B/V3B)

4 (V2C/V3C)

3 (V2C/V3C)

2 (V2B/V3B)

1 (V2A/V3A)

15 (V2C/V3C)

14 (V2A/V3A)

13 (V2B/V3B)

12 (V2C/V3C)

11 (V2C/V3C)

10 (V2B/V3B)

9 (V2A/V3A)

8 (V2C/V3C)

7 (V2C/V3C)

6 (V2A/V3A)

5 (V2B/V3B)

4 (V2C/V3C)

3 (V2C/V3C)

2 (V2B/V3B)

1 (V2A/V3A)

15 (V2C/V3C)

14 (V2A/V3A)

13 (V2B/V3B)

12 (V2C/V3C)

11 (V2C/V3C)

10 (V2B/V3B)

9 (V2A/V3A)

8 (V2C/V3C)

7 (V2C/V3C)

6 (V2A/V3A)

5 (V2B/V3B)

4 (V2C/V3C)

3 (V2C/V3C)

2 (V2B/V3B)

1 (V2A/V3A)

VOUT

Note) Blacked out portions in the diagram indicate pixels which are not read out.

7. Center scan mode (3)

This is the center scan mode using the progressive scan method.

The undesired portions are swept by vertical register high-speed transfer, and the picture center is cut out.

The number of output lines is 580 lines at 36MHz, and 444 lines at 28.6364MHz.

8. AF mode (1)

In this mode, the undesired portions are swept by vertical register high-speed transfer, and the vertical

940-pixel region in the center of the picture is output in approximately 1/60s by reading out the signals for

only two out of eight lines (1st and 6th lines, 9th and 14th lines). The number of output lines is 235 lines at

36MHz, and 170 lines at 28.6364MHz. This mode aims for even faster AF control than 2/8-line readout

mode.

9. AF mode (2)

In this mode, the undesired portions are swept by vertical register high-speed transfer, and the vertical

300-pixel region in the center of the picture is output in approximately 1/120s by reading out the signals for

only two out of eight lines (1st and 6th lines, 9th and 14th lines). The number of output lines is 75 lines at

36MHz, and 43 lines at 28.6364MHz. This mode aims for even faster AF control than 2/8-line readout

mode.

– 16 –

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ICX274AQ

Center scan and AF modes

Undesired portions (Swept by vertical register high-speed transfer)

Picture center cut-out portion

Description of Center Scan and AF Mode Operation

The center scan and AF modes realize high frame rates by sweeping the top and bottom of the picture with

high-speed transfer and cutting out the center of the picture.

The various readout modes during center scan and AF operation are described below.

• AF modes

AF mode (1), (2): The output method is the same as readout in 2/8-line readout mode.

• Center scan modes

Center scan mode (1): The output method is the same as 2/4-line readout mode.

Center scan mode (2): The output method consists of 2-line addition readout whereby the signals for only

two out of four lines (3rd and 4th lines, 7th and 8th lines, and so on) are read out,

the vertical register is shifted by 2 bits, and then the signals of the remaining two

out of the four lines (1st and 2nd lines, 5th and 6th lines, and so on) are read out

and added within the vertical register.

Center scan mode (3): The output method is the same as progressive scan mode.

The readout method, frame rate, number of output lines and other information for each readout mode are

shown in the table below.

Number of output

Frame rate (frame/s) effective pixel data

Addition

method

lines

Mode

Readout method

28.6MHz 36MHz 28.6MHz 36MHz

Progressive scan mode Progressive scan

None

9.99

29.97

19.98

29.97

59.94

119.88

14.985

29.97

19.98

29.97

59.94

119.88

1220

305

610

1220

434

444

170

1220

305

610

1220

568

580

235

2/8-line readout mode

2/4-line readout mode

2-line addition mode

Center scan mode (1)

Center scan mode (2)

Center scan mode (3)

AF mode (1)

2/8-line readout

2/4-line readout

None

Vertical 2-line

None

2-line addition readout Vertical 2-line

Progressive scan

2/8-line readout

None

AF mode (2)

– 17 –

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Measurement conditions

(1) In the following measurements, the device drive conditions are at the typical values of the bias and clock

voltage conditions, and the progressive scan readout mode is used.

(2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical

black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb

signal output or the R/B signal output of the measurement system.

Definition of standard imaging conditions

(1) Standard imaging condition I:

Use a pattern box (luminance: 706cd/m², color temperature of 3200K halogen source) as a subject.

(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR

cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined

as the standard sensitivity testing luminous intensity.

(2) Standard imaging condition II:

Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.

Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted

to the value indicated in each testing item by the lens diaphragm.

1. Sensitivity

Set to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of

1/100s, measure the signal voltages (V^Gr, VGb) at the center of each Gr and Gb channel screen, and

substitute the values into the following formulas.

VG = (VGr + VGb)/2

100

Sg = VG ×

[mV]

2. Saturation signal

Set to the standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with

the average value of the G channel signal output, 150mV, measure the minimum values of the G, R and B

signal outputs.

3. Smear

Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value

of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R

signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times

the intensity with the average value of the Gr signal output, 150mV. After the readout clock is stopped and

the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum

value (Vsm [mV]) independent of the Gr, Gb, R and B signal outputs, and substitute the values into the

following formula.

Smear in modes other than progressive scan mode is calculated from the storage time and signal

addition method. As a result, 2-line addition mode and center scan modes (2) and (3) are the same as

progressive scan mode, 2/4-line readout mode and center scan mode (1) are two times progressive scan

mode, and 2/8-line readout mode and AF modes (1) and (2) are four times progressive scan mode.

Gra + Gba + Ra + Ba

500

Sm = 20 × log Vsm ÷

[dB] (1/10V method conversion value)

(

)

– 18 –

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4. Video signal shading

Set to the standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjusting the luminous

intensity so that the average value of the G channel signal output is 150mV. Then measure the maximum

value (Gmax [mV]) and minimum value (Gmin [mV]) of the G signal output and substitute the values into

the following formula.

SH = (Gmax – Gmin)/150 × 100 [%]

5. Uniformity between video signal channels

After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of the R signal

and the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of the B signal, and substitute the values

into the following formulas.

∆Srg = (Rmax – Rmin)/150 × 100 [%]

∆Sbg = (Bmax – Bmin)/150 × 100 [%]

6. Dark signal

Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60°C

and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.

7. Dark signal shading

After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark

signal output and substitute the values into the following formula.

∆Vdt = Vdmax – Vdmin [mV]

8. Line crawl

Set to the standard imaging condition II. Adjusting the luminous intensity so that the value of the Gr signal

output is 150mV, and then insert R, G and B filters and measure the difference between G signal lines

(∆Glr, ∆Glg, ∆Glb [mV]) as well as the value of the G signal output (Gar, Gag, Gab). Substitute the values

into the following formula.

∆Gli

Gai

Lci =

× 100 [%] (i = r, g, b)

9. Lag

Adjust the Y signal output generated by the strobe light to 150mV. After setting the strobe light so that it

strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value into the

following formula.

Lag = (Vlag/150) × 100 [%]

Light

Strobe light timing

Y signal output 150mV

Vlag (lag)

Output

– 19 –

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O U V T

D D V

R φ G

G N D

1 φ V

2 B φ H

^{1 B}φ H

2 C φ V

2 B φ V

2 A φ V

3 C φ V

3 B φ V

3 A φ V

G N D

S φ U B

S U C B

L V

1 A φ H

2 A φ H

4 φ V

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1 0

1 4

1 3

1 2

1 1

1 0

2 8 . 6 M H z

1 4 9 3

1 4 9 2

3 6 M H z

1 2 5 2

1 2 5 1

1 2 5 0

1 2 4 9

1 2 3 6

1 2 3 5

1 0

1 4

1 3

1 2

1 1

1 0

2 8 . 6 M H z

1 4 9 3

1 4 9 2

3 6 M H z

1 2 5 2

1 2 5 1

1 2 5 0

1 2 4 9

1 2 3 6

1 2 3 5

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2 9 6

1 9 2 0

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2 8 . 6 M H z

3 6 M H z

1 7 4 2

1 5 6 5

1 5 6 4

1 3 2 1

1 2 3 6

1 2 3 5

1 0

7 2

7 0

1 1

1 0

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4 6

4 1

3 8

3 3

3 0

2 5

2 2

1 7

1 4

1 3

1 2

1 1

1 0

3 6 M H z

2 8 . 6 M H z

5 1 1

5 1 0

4 0 7

4 0 6

1 2 3 3

1 2 3 0

1 2 2 5

3 1 2

3 1 1

4 6

1 4

4 1

3 8

3 3

3 0

2 5

2 2

1 7

1 4

1 3

1 2

1 1

1 0

3 6 M H z

5 1 1

5 1 0

2 8 . 6 M H z

4 0 7

4 0 6

1 2 3 3

1 2 3 0

1 2 2 5

3 1 2

3 1 1

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7 2 8

2 3 5 2

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1 0

3 6 M H z

2 8 . 6 M H z

8 7 1

6 9 3

6 5 2

1 2 3 6

1 2 3 5

1 2 3 2

1 2 3 1

1 0

3 6 M H z

2 8 . 6 M H z

8 7 1

6 9 3

6 2 5

1 2 3 6

1 2 3 5

1 2 3 2

1 2 3 1

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4 4 6

2 0 7 0

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1 0

3 6 M H z

2 8 . 6 M H z

8 7 1

6 9 3

6 2 5

1 2 3 6 1 2 3 4

1 2 3 5 1 2 3 3

1 2 3 2 1 2 3 0

1 2 3 1 1 2 2 9

1 0

3 6 M H z

2 8 . 6 M H z

8 7 1

6 9 3

6 2 5

1 2 3 6 1 2 3 4

1 2 3 5 1 2 3 3

1 2 3 2 1 2 3 0

1 2 3 1 1 2 2 9

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4 4 6

2 0 7 0

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1 9 2

1 9 1

1 8 8

1 7

1 5

1 0

4 6 2

4 6 1

4 6 0

4 5 9

4 5 3

4 5 2

4 5 1

4 5 0

1 0 5 5

1 0 5 2

1 0 5 1

1 0 4 8

1 9 5

1 9 2

1 9 1

1 8 8

1 7

1 5

1 0

4 6 2

4 6 1

4 6 0

4 5 9

4 5 8

4 5 3

4 5 2

4 5 1

4 5 0

1 0 5 5

1 0 5 2

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6 0

5 9

5 6

5 5

1 0

5 8 1

5 8 0

5 7 9

5 7 8

5 7 7

5 7 6

1 1 8 8

1 1 8 7

1 1 8 4

1 1 8 3

6 0

5 9

5 6

5 5

1 0

5 8 1

5 8 0

5 7 9

5 7 8

5 7 7

5 7 6

1 1 8 8

1 1 8 7

1 1 8 4

1 1 8 3

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1 9 2

1 9 1

1 8 8

1 9 0

1 8 9

1 8 6

1 8

1 5

1 0

4 6 2

4 6 1

4 6 0

4 5 9

4 5 8

4 5 7

4 5 6

4 5 5

4 5 4

4 5 3

4 5 2

1 0 5 5 1 0 5 3

1 0 5 2 1 0 5 0

1 0 5 1 1 0 4 9

1 0 4 8 1 0 4 6

1 9 5

1 9 2

1 9 1

1 8 8

1 9 3

1 9 0

1 8 9

1 8 6

1 8

1 5

1 0

4 6 2

4 6 1

4 6 0

4 5 9

4 5 8

4 5 7

4 5 6

4 5 5

4 5 4

4 5 3

4 5 2

1 0 5 5 1 0 5 3

1 0 5 2 1 0 5 0

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6 0

5 9

5 6

5 5

5 8

5 7

5 4

5 3

1 0

5 8 1

5 8 0

5 7 9

5 7 8

5 7 7

5 7 6

1 1 8 8 1 1 8 6

1 1 8 7 1 1 8 5

1 1 8 4 1 1 8 2

1 1 8 3 1 1 8 1

6 0

5 8

5 7

5 4

5 3

5 9

5 6

5 5

1 0

5 8 1

5 8 0

5 7 9

5 7 8

5 7 7

5 7 6

1 1 8 8 1 1 8 6

1 1 8 7 1 1 8 5

1 1 8 4 1 1 8 2

1 1 8 3 1 1 8 1

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4 4 6

2 0 7 0

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3 9 8

3 9 7

3 5

3 4

3 3

3 2

4 9 8

4 9 7

4 9 6

4 7 9

4 7 8

8 4 0

8 3 9

3 9 8

3 9 7

3 5

3 4

3 3

3 2

4 9 8

4 9 7

4 9 6

4 7 9

4 7 8

8 4 0

8 3 9

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3 3 0

3 2 9

3 0

2 9

2 8

2 7

6 2 6

6 2 5

6 2 4

6 1 0

6 0 9

9 0 8

9 0 7

3 1

3 3 0

3 2 9

3 0

2 9

2 8

2 7

6 2 6

6 2 5

6 2 4

6 1 0

6 0 9

9 0 8

9 0 7

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2 9 6

1 9 2 0

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2 8 9

2 8 6

2 2

2 1

2 0

1 9

2 0 4

2 0 3

2 0 2

2 0 1

1 9 1

1 9 0

9 5 8

9 5 3

2 8 9

2 8 6

2 2

2 1

2 0

1 9

2 0 4

2 0 3

2 0 2

2 0 1

1 9 1

1 9 0

9 5 8

9 5 3

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1 5 8

1 5 3

1 4

1 3

1 2

1 1

1 0

2 5 6

2 5 5

2 5 4

2 4 9

2 4 8

1 0 8 9

1 0 8 6

1 5 8

1 5 3

1 4

1 3

1 2

1 1

1 0

2 5 6

2 5 5

2 5 4

2 4 9

2 4 8

1 0 8 9

1 0 8 6

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5 4 2

5 3 7

3 8

3 7

3 6

3 5

1 0 2

1 0 1

1 0 0

8 1

7 0 5

7 0 2

8 0

5 4 2

5 3 7

3 8

3 7

3 6

3 5

1 0 2

1 0 1

1 0 0

8 1

8 0

7 0 5

7 0 2

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4 7 8

4 7 3

3 4

3 3

3 2

3 1

1 2 8

1 2 7

1 2 6

1 0 9

1 0 8

7 6 9

7 6 6

4 7 8

4 7 3

3 4

3 3

3 2

3 1

1 2 8

1 2 7

1 2 6

1 0 9

1 0 8

7 6 9

7 6 6

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7 2 8

2 3 5 2

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Notes of Handling

1) Static charge prevention

CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following

protective measures.

a) Either handle bare handed or use non-chargeable gloves, clothes or material.

Also use conductive shoes.

b) When handling directly use an earth band.

c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.

d) Ionized air is recommended for discharge when handling CCD image sensors.

e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Soldering

a) Make sure the package temperature does not exceed 80°C.

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W

soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an image sensor, do not use a solder suction equipment. When using an electric

desoldering tool, use a thermal controller of the zero-cross On/Off type and connect it to ground.

3) Dust and dirt protection

Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and

dirt. Clean glass plates with the following operations as required, and use them.

a) Perform all assembly operations in a clean room (class 1000 or less).

b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized

air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

e) When a protective tape is applied before shipping, just before use remove the tape applied for

electrostatic protection. Do not reuse the tape.

4) Installing (attaching)

a) Remain within the following limits when applying a static load to the package. Do not apply any load

more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to

limited portions. (This may cause cracks in the package.)

Cover glass

50N

1.2Nm

Plastic package

Compressive strength

Torsional strength

b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the

package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for

installation, use either an elastic load, such as a spring plate, or an adhesive.

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c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated

voltage value is indicated on the rear surface.Therefore, the adhesive should not be applied to this area,

and indicated values should be transferred to other locations as a precaution.

d) The notch of the package is used for directional index, and that can not be used for reference of fixing.

In addition, the cover glass and seal resin may overlap with the notch of the package.

e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be

generated by the fragments of resin.

f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-

acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.

(reference)

5) Others

a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high

luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of

the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In

such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the

power-off mode should be properly arranged. For continuous using under cruel condition exceeding the

normal using condition, consult our company.

b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or

usage in such conditions.

c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD

characteristics.

d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength

are the same.

Structure A

Structure B

Package

Chip

Metal plate

(lead frame)

Cross section of

lead frame

The cross section of lead frame can be seen on the side of the package for structure A.

– 71 –

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1 . 7

t o 0 9 ˚ ˚

0 . 2 5

1 2 .

2 . 9 ± 0 . 1 5

0 . 5

3 . 5 ± 0 . 3

1 2 . 0 ± 0 . 1

2 . 4

0 . 8

1 0 . 9

6 . 0

9 . 0

2 . 5

0 . 5

Sony Corporation

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