Silicon Image Computer Drive SSD DXXXI 4210 User Manual

DATA SHEET  
SILICONDRIVE EP 2.5" PATA DRIVE  
SSD-DXXX(I)-4210  
OVERVIEW  
FEATURES  
• RoHS 6 of 6 compliant  
The SiliconDrive EP 2.5" PATA Drive is an  
optimal time-to-market replacement for  
hard drives and flash cards or in host  
systems that require low power and  
scalable storage solutions.  
• Integrated PowerArmor and SiSMART  
technology  
• Capacity range: 16GB to 64GB  
• Supports 5V interface  
SiliconDrive EP technology is engineered  
exclusively for the high performance, high  
reliability and multi-year product lifecycle  
requirements of the Enterprise System  
• MTBF 4,000,000 hours  
• ATA-5 compliant  
• Industry standard 2.5" Drive form factor  
• Supports UDMA modes 0-4  
OEM  
market.  
Typical  
end-market  
applications include broadband data and  
voice networks, military systems, flight  
system avionics, medical equipment,  
industrial  
control  
systems,  
video  
surveillance, storage networking, VoIP,  
wireless infrastructure, and interactive  
kiosks.  
Every SiliconDrive EP is integrated with  
SiliconSystems patented PowerArmor and  
patent-pending SiSMART to virtually  
eliminate storage systems failures.  
PowerArmor prevents data corruption and  
loss from power disturbances by  
integrating patented technology into every  
SiliconDrive EP.  
SiSMART acts as an early warning system  
to eliminate unscheduled downtime by  
constantly monitoring and reporting the  
exact amount of remaining storage system  
useful life.  
Numerous SiliconSystems patented and  
patent-pending  
application-specific  
technology can be integrated into  
SiliconDrive EP to safeguard application  
data and software IP. Application notes  
detailing these performance-enhancing  
options are available under NDA.  
SILICONSYSTEMS PROPRIETARY  
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.  
All unauthorized use and/or reproduction is prohibited.  
26840 ALISO VIEJO PARKWAY, ALISO VIEJO, CA 92656 PHONE: 949.900.9400 FAX: 949.900.9500 http://www.siliconsystems.com  
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TABLE OF CONTENTS  
SSD-DXXX(I)-4210 DATA SHEET  
TABLE OF CONTENTS  
Overview.......................................................................................................................... i  
Features........................................................................................................................... i  
Revision History..............................................................................................................II  
List of Figures ................................................................................................................VI  
List of Tables.................................................................................................................VII  
Physical Specifications................................................................................................. 1  
Product Specifications.................................................................................................. 3  
Electrical Specification.................................................................................................. 6  
ATA and True IDE Register Decoding ........................................................................ 27  
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TABLE OF CONTENTS  
SSD-DXXX(I)-4210 DATA SHEET  
ATA Registers............................................................................................................... 28  
ATA Command Block and Set Description................................................................ 40  
Identify Drive — Drive Attribute Data ............................................................. 46  
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TABLE OF CONTENTS  
SSD-DXXX(I)-4210 DATA SHEET  
Sales and Support ....................................................................................................... 77  
Part Numbering............................................................................................................ 77  
Related Documentation............................................................................................... 79  
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LIST OF FIGURES  
SSD-DXXX(I)-4210 DATA SHEET  
LIST OF FIGURES  
Figure 1: Physical Dimensions......................................................................................... 1  
Figure 2: Pin Locations .................................................................................................... 2  
Figure 3: Jumper Settings................................................................................................ 2  
Figure 5: True IDE Multiword DMA Read/Write Access Timing..................................... 15  
Figure 6: Initiating a UDMA Data-In Burst...................................................................... 17  
Figure 7: Sustained UDMA Data-In Burst...................................................................... 18  
Figure 8: Host Pausing a UDMA Data-In Burst.............................................................. 18  
Figure 9: Device Terminating a UDMA Data-In Burst.................................................... 19  
Figure 10: Host Terminating a UDMA Data-In Burst...................................................... 20  
Figure 11: Initiating a UDMA Data-Out Burst................................................................. 21  
Figure 12: Sustained UDMA Data-Out Burst ................................................................. 21  
Figure 13: Device Pausing a UDMA Data-Out Burst ..................................................... 22  
Figure 14: Host Terminating a UDMA Data-Out Burst................................................... 23  
Figure 15: Device Terminating a UDMA Data-Out Burst ............................................... 24  
Figure 16: Sample Label................................................................................................ 78  
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LIST OF TABLES  
SSD-DXXX(I)-4210 DATA SHEET  
LIST OF TABLES  
Table 1: System Performance ......................................................................................... 3  
Table 2: System Power Requirements ............................................................................ 3  
Table 3: Reliability............................................................................................................ 4  
Table 4: Operational Life Span ........................................................................................ 4  
Table 5: Product Capacity Specifications ........................................................................ 5  
Table 6: Environmental Specifications............................................................................. 5  
Table 7: Pin Assignments ................................................................................................ 6  
Table 8: Signal Descriptions ............................................................................................ 7  
Table 9: Absolute Maximum Ratings ............................................................................. 11  
Table 10: DC Characteristics......................................................................................... 12  
Table 11: True IDE PIO Mode Read/Write Access Timing............................................ 14  
Table 12: True IDE Multiword DMA Read/Write Access Timing.................................... 16  
Table 13: UDMA Data Burst Timing Requirements ....................................................... 24  
Table 14: Task File Register Specification..................................................................... 27  
Table 15: Error Register................................................................................................. 28  
Table 16: Feature Register ............................................................................................ 29  
Table 17: Sector Count Register.................................................................................... 30  
Table 18: Sector Number Register ................................................................................ 31  
Table 19: Cylinder Low Register.................................................................................... 32  
Table 20: Cylinder High Register................................................................................... 33  
Table 21: Drive/Head Register....................................................................................... 34  
Table 22: Status Register .............................................................................................. 35  
Table 23: Command Register........................................................................................ 36  
Table 24: Alternate Status Register............................................................................... 37  
Table 25: Device Control Register................................................................................. 38  
Table 26: Device Address Register ............................................................................... 39  
Table 27: ATA Command Block and Set Description .................................................... 40  
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LIST OF TABLES  
SSD-DXXX(I)-4210 DATA SHEET  
Table 28: ATA Command Set........................................................................................ 40  
Table 29: Check Power Mode — 98h, E5h.................................................................... 42  
Table 30: Executive Drive Diagnostic — 90h................................................................. 43  
Table 31: Format Track — 50h...................................................................................... 44  
Table 32: Identify Drive — ECh ..................................................................................... 45  
Table 33: Identify Drive — Drive Attribute Data............................................................. 46  
Table 34: Idle — 97h, E3h ............................................................................................. 49  
Table 35: Idle Immediate — 95h, E1h ........................................................................... 50  
Table 36: Initialize Drive Parameters — 91h ................................................................. 51  
Table 37: Recalibrate — 1Xh......................................................................................... 52  
Table 38: Read Buffer — E4h........................................................................................ 53  
Table 39: Read DMA — C8h ......................................................................................... 54  
Table 40: Read Multiple — C4h..................................................................................... 55  
Table 41: Read Sector — 20h, 21h ............................................................................... 56  
Table 42: Read Long Sector(s) — 22h, 23h .................................................................. 57  
Table 43: Read Verify Sector(s) — 40h, 41h................................................................. 58  
Table 44: Seek — 7Xh................................................................................................... 59  
Table 45: Set Features — EFh ...................................................................................... 60  
Table 46: Set Features’ Attributes ................................................................................. 60  
Table 47: Set Multiple Mode — C6h.............................................................................. 61  
Table 48: Set Sleep Mode — 99h, E6h ......................................................................... 62  
Table 49: Standby — 96h, E2h...................................................................................... 63  
Table 50: Standby Immediate — 94h, E0h.................................................................... 64  
Table 51: Write Buffer — E8h........................................................................................ 65  
Table 52: Write DMA — CAh......................................................................................... 66  
Table 53: Write Multiple — C5h..................................................................................... 67  
Table 54: Write Sector(s) — 30h, 31h ........................................................................... 68  
Table 55: Write Long Sector(s) — 32h, 33h .................................................................. 69  
Table 56: Erase Sector(s) — C0h.................................................................................. 70  
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LIST OF TABLES  
SSD-DXXX(I)-4210 DATA SHEET  
Table 57: Request Sense — 03h................................................................................... 71  
Table 58: Extended Error Codes ................................................................................... 71  
Table 59: Translate Sector — 87h................................................................................. 72  
Table 60: Wear-Level — F5h......................................................................................... 73  
Table 61: Write Multiple w/o Erase — CDh ................................................................... 74  
Table 62: Write Sector(s) w/o Erase — 38h .................................................................. 75  
Table 63: Write Verify — 3Ch ........................................................................................ 76  
Table 64: Part Numbering Nomenclature ...................................................................... 77  
Table 65: Part Numbers................................................................................................. 77  
Table 66: Related Documentation ................................................................................. 79  
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PHYSICAL SPECIFICATIONS  
SSD-DXXX(I)-4210 DATA SHEET  
PHYSICAL SPECIFICATIONS  
The SiliconDrive EP 2.5" PATA Drive products are offered in an industry-  
standard 2.5" PATA Drive form factor. See "Part Numbering" on page 77 for  
details regarding 2.5" PATA Drive capacities.  
PHYSICAL DIMENSIONS  
This section provides diagrams that describe the physical dimensions for the  
2.5" PATA Drive.  
Figure 1: Physical Dimensions  
Dimension Millimeters Tolerance (mm)  
Dimension Millimeters Tolerance (mm)  
A
B
C
D
E
F
G
H
I
100.00  
90.60  
73.03  
34.93  
14.00  
4.08  
±0.25  
L
69.85  
2.00  
±0.25  
±0.125  
±0.125  
±0.125  
±0.125  
±0.125  
±0.125  
±0.125  
±0.125  
±0.51  
M
N
P
Q
R
S
T
±0.125  
±0.10  
9.40  
6.00  
±0.125  
±0.125  
±0.125  
±0.125  
±0.125  
±0.125  
±0.125  
±0.125  
11.57  
32.10  
14.93  
11.00  
4.65  
61.70  
4.68  
64.42  
10.14  
3.99  
U
V
W
J
4.00  
K
±0.43  
6.15  
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PHYSICAL SPECIFICATIONS  
SSD-DXXX(I)-4210 DATA SHEET  
PIN LOCATIONS  
The following diagram identifies the pin locations of the 2.5" PATA Drive.  
Figure 2: Pin Locations  
JUMPER SETTINGS  
The following diagram defines the SiliconDrive EP 2.5" PATA Drive jumper  
settings.  
Figure 3: Jumper Settings  
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PRODUCT SPECIFICATIONS  
SSD-DXXX(I)-4210 DATA SHEET  
PRODUCT SPECIFICATIONS  
Note: All SiliconDrive EP 2.5" PATA Drive values quoted are typical at  
25°C and nominal supply voltage.  
SYSTEM PERFORMANCE  
Table 1: System Performance  
Reset to Ready Startup Time (Typical/Maximum) 200ms/400ms  
Read Transfer Rate (Typical)  
Write Transfer Rate (Typical)  
Burst Transfer Rate  
50MBps  
50MBps  
66MBps  
Controller Overhead (Command to DRQ)  
2ms (maximum)  
SYSTEM POWER REQUIREMENTS  
Table 2: System Power Requirements  
DC Input Voltage  
Sleep (Standby Current)  
Read (/Peak)  
5.0 ± 10%  
100mA  
200mA  
300mA  
Write (/Peak)  
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PRODUCT SPECIFICATIONS  
SSD-DXXX(I)-4210 DATA SHEET  
RELIABILITY  
Table 3: Reliability  
4,000,000 hours  
<1 non-recoverable error in 10 bits read  
MTBF (@ 25ºC)  
Bit Error Rate  
14  
PROJECTED OPERATIONAL LIFE SPAN  
Table 4: Operational Life Span  
Capacity Service Life*  
64GB 17.9 Years  
SiliconDrive Part#  
GB Written per Day  
@ 978.5GB  
SSD-D64G-4210  
SSD-D32G-4210  
SSD-D16G-4210  
32GB  
16GB  
9.0 Years  
4.5 Years  
@ 978.5GB  
@ 978.5GB  
* There are unlimited read cycles. Service life is determined using  
SiliconSystems’ LifeEst calculation at 100% duty cycle with 25% write cycles.  
LifeEst is a comprehensive measurement that considers numerous factors to  
determine the projected life span of a SiliconDrive. A white paper that  
describes the benefits of LifeEst and how to calculate it can be found at http://  
The actual life of a SiliconDrive is dependant on the customer usage model.  
SiSMART is a patented technology of SiliconSystems that enables host  
systems to monitor actual usage of a SiliconDrive in real time. SiSMART  
measures and reports the remaining life of a SiliconDrive. For more  
information on SiSMART, refer to the Eliminating Unscheduled Downtime by  
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PRODUCT SPECIFICATIONS  
SSD-DXXX(I)-4210 DATA SHEET  
PRODUCT CAPACITY SPECIFICATIONS  
Table 5: Product Capacity Specifications  
Numberof  
Sectors/  
Track  
Product Capacity  
Capacity (Bytes)  
Number of Number of Number  
Sectors Cylinders of Heads  
16GB  
32GB  
64GB  
16,391,208,960 32,014,080 16,383*  
32,782,417,920 64,028,160 16,383*  
65,564,835,840 128,056,320 16,383*  
16  
16  
16  
63  
63  
63  
* = All IDE drives 8GB and larger use 16383 cylinders, 16 heads, and 63 sectors/track due to  
interface restrictions.  
ENVIRONMENTAL SPECIFICATIONS  
Table 6: Environmental Specifications  
Temperature  
0ºC to 70ºC (Commercial)  
-40ºC to 85ºC (Industrial)  
8% to 95% non-condensing  
Humidity  
Vibration  
16.3gRMS, MIL-STD-810F, Method 514.5, Procedure I,  
Category 24  
Shock  
1000G, Half-sine, 0.5ms Duration  
50g Pk, MIL-STD-810F, Method 516.5, Procedure I  
80,000ft, MIL-STD-810F, Method 500.4, Procedure II  
Altitude  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
ELECTRICAL SPECIFICATION  
PIN ASSIGNMENTS  
The following table describes the SiliconDrive EP 2.5" PATA Drive 44-pin IDE  
connector signals.  
Table 7: Pin Assignments  
Pin IDE-ATA Ultra DMA  
RESET# RESET#  
Pin  
IDE-ATA Ultra DMA  
1
2
GND  
D8  
GND  
D8  
3
D7  
D7  
4
5
D6  
D6  
6
D9  
D9  
7
D5  
D5  
8
D10  
D11  
D12  
D13  
D14  
D15  
KEY  
GND  
GND  
D10  
D11  
D12  
D13  
D14  
D15  
KEY  
GND  
GND  
9
D4  
D4  
10  
12  
14  
16  
18  
20  
22  
24  
11  
13  
15  
17  
19  
21  
23  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
GND  
DMARQ  
IOWR#  
GND  
DMARQ#  
STOP  
HDSTROBE  
HDMARDY#  
DDSTROBE  
DDMARDY#  
25  
27  
IORD#  
IORDY  
26  
28  
GND  
GND  
CSEL#  
GND  
CSEL#  
GND  
29  
31  
33  
35  
37  
39  
DMACK# DMACK#  
30  
32  
34  
36  
38  
40  
INTRQ  
A1  
INTRQ  
A1  
IOCS16# IOCS16#  
PDIAG#  
A2  
PDIAG#  
A2  
A0  
A0  
CS0#  
DASP#  
CS0#  
DASP  
CS1#  
GND  
CS1#  
GND  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
SIGNAL DESCRIPTIONS  
Table 8: Signal Descriptions  
Type Description  
Signal Name Pin(s)  
A2-A0  
36, 33,  
35  
I
Address Inputs. These signals are  
asserted by the host to access the task  
registers in the device.  
-CS0,-CS1  
37, 38  
I
In the true IDE mode, -CS0 is the chip  
select for the task file registers while -CS1  
is used to select the Alternate Status  
register and the Device Control register.  
-CSEL  
28  
I
Cable Select. This internally pulled-up  
signal is used to configure this device as a  
master or a slave when the jumper  
configuration is in CSEL mode.  
When this pin is:  
• Grounded by the host, this device is  
configured as a master.  
• Open, this device is configured as a  
slave.  
D15-D0  
18, 16,  
14, 12,  
10, 8, 6,  
4, 3, 5, 7,  
9, 11, 13,  
15, 17  
I/O  
Data Inputs/Outputs. This is the 8-bit or  
16-bit bidirectional interface between the  
host and device. The lower eight bits are  
used for 8-bit register transfers.  
-DMACK  
29  
39  
I
DMA Acknowledge. This signal is used by  
the host in response to DMARQ to initiate  
DMA transfers. The DMARQ/-DMACK  
handshake is used to provide flow control  
during the transfer. When -DMACK is  
asserted, -CS0 and -CS1 are not asserted  
and transfers are 16-bits wide.  
DASP  
I/O  
Disk Active/Slave Present. This open  
drain output signal is asserted low any time  
the drive is active. In a master/slave  
configuration, this signal is used by the  
slave to inform the master that a slave is  
present.  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 8: Signal Descriptions (Continued)  
Signal Name Pin(s) Type Description  
DMARQ 21 DMA Request. This signal is used for DMA  
O
transfers between the host and device.  
DMARQ is asserted by the device when the  
device is ready to transfer data to/from the  
host. The direction of data transfer is  
controller by -IORD and -IOWR. This signal  
is used in a handshake manner with -  
DMACK (i.e., the device waits until the host  
asserts -DMACK before negating DMARQ,  
and reasserts DMARQ if there is more data  
to transfer). The DMARQ/-DMACK  
handshake is used to provide flow control  
during the transfer.  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 8: Signal Descriptions (Continued)  
Signal Name Pin(s) Type Description  
This signal is a DMA request that is used  
DMARQ#  
for DMA data transfers between the host  
and device. This signal is asserted by the  
device when it is ready to transfer data to or  
from the host.  
(UDMA  
protocol  
active)  
For Multiword DMA transfers, the direction  
of data transfer is controlled by -IORD and  
-IOWR. This signal is used in a handshake  
manner with -DMACK (i.e., the device waits  
until the host asserts (-)DMACK before  
negating (-)DMARQ, and reasserts  
(-)DMARQ if there is more data to transfer).  
In PCMCIA I/O mode, the -DMARQ is  
ignored by the host while the host is  
performing an I/O Read cycle to the device.  
The host does not initiate an I/O Read cycle  
while -DMARQ is asserted by the device.  
In True IDE mode, DMARQ is not driven  
when the device is not selected in the  
Drive-Head register.  
While a DMA operation is in progress, -CS0  
(-CE1) and -CS1 (-CE2) are held negated  
and the width of the transfers is 16 bits.  
If there is no hardware support for True IDE  
DMA mode in the host, this output signal is  
not used and should not be connected at  
the host. In this case, the BIOS must report  
that DMA mode is not supported by the  
host so that device drivers do not attempt  
the DMA mode operation.  
GND  
2, 19, 22, -  
24, 26,  
30, 40,  
43  
Ground. The device ground signal.  
INTRQ  
31  
O
Interrupt Request. This signal is an active  
high interrupt request to the host.  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 8: Signal Descriptions (Continued)  
Signal Name Pin(s) Type Description  
IORDY  
27  
I
I/O Channel Ready. The signal is negated  
to extend the host transfer cycle of any host  
register access.  
(True IDE  
mode)  
-IORD  
25  
I
Device I/O Read. This is the read strobe  
signal from the host. The falling edge of  
IORD enables data from the device onto  
the data bus. The rising edge of IORD  
latches data at the host. The host does not  
act on the data until it is latched.  
(True IDE  
mode)  
-DDMARDY  
When UDMA mode DMA write is active in  
all modes, this signal is asserted by the  
device during a data burst to indicate that  
the device is ready to receive UDMA data-  
out bursts.  
(UDMA write  
protocol  
active)  
The device may negate -DDMARDY to  
pause a UDMA transfer.  
DSTROBE  
When UDMA mode DMA read is active in  
all modes, this signal is the data in strobe  
generated by the device. Both the rising  
and falling edge of DSTROBE cause data  
to be latched by the host. The device may  
stop generating DSTROBE edges to pause  
a UDMA data-in burst.  
(UDMA read  
protocol  
active)  
-IOWR  
23  
I
Device I/O Write. This is the write strobe  
signal from the host. The rising edge of  
IOWR# latches data from the data bit  
signals. The device does not act on the  
data until it is latched.  
(True IDE  
mode)  
-HDMARDY  
When UDMA mode DMA read is active in  
all modes, this signal is asserted by the  
host to indicate that the host is ready to  
receive UDMA data-in bursts. The host may  
negate -HDMARDY to pause a UDMA  
transfer.  
(UDMA read  
protocol  
active)  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 8: Signal Descriptions (Continued)  
Signal Name Pin(s) Type Description  
When UDMA mode DMA write is active in  
HDSTROBE  
all modes, this signal is the data-out strobe  
generated by the host. Both the rising and  
falling edge of HSTROBE cause data to be  
latched by the device. The host may stop  
generating HSTROBE edges to pause an  
UDMA data-out burst.  
(UDMA write  
protocol  
active)  
KEY  
20  
-
Key. Reserved for the Connector Key.  
STOP  
While the UDMA mode protocol is active in  
all modes, the assertion of this signal  
causes the termination of the UDMA data  
burst.  
(UDMA  
protocol  
active)  
-PDIAG  
34  
1
I/O  
I
Pass Diagnostic. This open drain signal is  
asserted by the slave to indicate to the  
master that it has passed its diagnostics.  
-RESET  
Device Reset. An active low signal. When  
active, this signal sets all internal registers  
to their default state. This signal is held  
asserted until at least 25μs after power has  
been stabilized during the device power-on.  
V
41, 42  
-
Device Power Supply. The device power  
CC  
+3.3V/5V signal.  
ABSOLUTE MAXIMUM RATINGS  
Table 9: Absolute Maximum Ratings  
Parameter Minimum Maximum Units  
Symbol  
T
Storage Temperature  
-55  
-40  
-0.5  
-0.3  
-
125  
85  
°C  
S
T
Operating Temperature  
°C  
A
V
V
V
V
with Respect to GND  
V
V
+ 0.5 V  
CC  
IN  
CC  
CC  
CC  
Input Voltage  
+ 0.3 V  
V
Output Voltage  
6.0  
OUT  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
DC CHARACTERISTICS  
Table 10: DC Characteristics  
5V ± 10%  
Minimum Maximum  
Symbol  
Parameter  
Units  
I
I
I
I
I
Input Leakage *(1) Current  
-
10  
μA  
LI  
Output Leakage *(1) Current -  
10  
μA  
LO  
I
I
I
Read Current  
Write Current  
Standby Current  
-
-
-
100  
200  
15  
mA  
mA  
mA  
CCR  
CCW  
CCS  
CC  
CC  
CC  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
AC CHARACTERISTICS  
True IDE PIO Mode Read/Write Access Timing  
t0  
ADDR valid  
(A02, A01, A00, -CS0, -CS1)  
((SSeeeennoottee11))  
t1  
t2  
t9  
t2i  
t8  
-IORD / -IOWR  
Write  
Data (D15:D00)  
(See note 2)  
(
t3  
t5  
t4  
t6  
Read  
Data (D15:D00)  
(See note 2)  
(
t7  
t6z  
-IOCS16  
(See note 3)  
IORDY  
(See note 4a)  
(See note 4, 4-1)  
tA  
IORDY  
(See note 4b)  
(See note 4, 4-2)  
tC  
tRD  
IORDY  
(See note 4c)  
(ee oe 4, 4-)  
tC  
tB  
Figure 4: True IDE PIO Mode Read/Write Access Timing Diagram  
Notes:  
1. The device address consists of -CS0, -CS1, and A[02::00].  
2. The data consists of D[15::00] (16-bit) or D[07::00] (8 bit).  
3. -IOCS16 is shown for PIO modes 0, 1, and 2. For other modes, this signal is  
ignored.  
4. The negation of IORDY by the device is used to extend the PIO cycle. The  
determination of whether the cycle is to be extended is made by the host  
after t from the assertion of -IORD or -IOWR. The assertion and negation  
A
of IORDY is described in the following three cases:  
a. The device never negates IORDY; no wait is generated.  
b. The device starts to drive IORDY low before t , but causes IORDY to be  
A
asserted before t ; no wait generated.  
A
c. The device drives IORDY low before t ; wait generated. The cycle  
A
completes after IORDY is reasserted. For cycles where a wait is  
generated and -IORD is asserted, the device places read data on D15-  
D00 for t before causing IORDY to be asserted.  
RD  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 11: True IDE PIO Mode Read/Write Access Timing  
Symbol Item  
Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Note Units  
t
Cycle Time (minimum)  
600  
70  
383  
50  
240  
30  
180  
30  
120  
25  
100  
15  
80  
10  
1
-
ns  
ns  
0
1
t
Address Valid to  
IORD/-IOWR Setup  
(minimum)  
t
t
-IORD/-IOWR(minimum) 165  
125  
290  
100  
290  
80  
80  
70  
70  
65  
65  
55  
55  
1
1
ns  
ns  
2
-IORD/-IOWR(minimum) 290  
register (8 bit)  
2
t
t
t
t
t
t
t
t
t
t
-IORD/-IOWR Recovery  
Time (minimum)  
-
-
-
70  
30  
10  
20  
5
25  
20  
10  
20  
5
25  
20  
5
20  
15  
5
1
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2i  
3
-IOWR Data Setup  
(minimum)  
60  
30  
50  
5
45  
20  
35  
5
30  
15  
20  
5
-IOWR Data Hold  
(minimum)  
-
4
-IORD Data Setup  
(minimum)  
15  
5
10  
5
-
5
-IORD Data Hold  
(minimum)  
-
6
-IORD Data Tristate  
(maximum)  
30  
30  
50  
45  
15  
0
30  
40  
30  
10  
0
30  
N/A  
N/A  
10  
0
30  
N/A  
N/A  
10  
0
20  
N/A  
N/A  
10  
0
20  
N/A  
N/A  
10  
0
2
4
4
-
6Z  
7
Address Valid to IOCS16 90  
Assertion (maximum)  
Address Valid to IOCS16 60  
Released (maximum)  
8
-IORD/-IOWR to  
Address Valid Hold  
20  
9
Read Data Valid to  
IORDY Active  
0
-
RD  
(minimum), if IORDY is  
initially low after t  
A
5
5
5
5
t
t
IORDY Setup Time  
35  
35  
35  
35  
35  
3
ns  
ns  
A
N/A  
N/A  
N/A  
N/A  
IORDY Pulse Width  
(maximum)  
1250  
1250  
1250  
1250  
1250  
-
B
5
5
t
IORDY Assertion to  
Release (maximum)  
5
5
5
5
5
-
ns  
C
N/A  
N/A  
Notes:  
1. The symbol t is the minimum total cycle time, t is the minimum command  
0
2
active time, and t is the minimum command recovery time or command  
2i  
inactive time. The actual cycle time equals the sum of the actual command  
active time and the actual command inactive time. The three timing  
requirements of t , t , and t must be met. The minimum total cycle time  
0
2
2i  
requirement is greater than the sum of t and t . This means a host  
2
2i  
implementation can lengthen either or both t or t to ensure that t is equal  
2
2i  
0
to or greater than the value reported in the device’s identify device data.  
2. This parameter specifies the time from the negation edge of -IORD to the  
time that the data bus is no longer driven by the drive (tristate).  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
3. The delay from the activation of -IORD or -IOWR until the state of IORDY is  
first sampled. If IORDY is inactive, then the host waits until IORDY is active  
before the PIO cycle can be completed. If the drive is not driving IORDY  
negated at t after the activation of -IORD or -IOWR, then t must be met  
A
5
and t is not applicable. If the drive is driving IORDY negated at the time t  
RD  
A
after the activation of -IORD or -IOWR, then t must be met and t is not  
RD  
5
applicable.  
4. The symbols t and t apply only to modes 0, 1, and 2. For other modes,  
7
8
this signal is not valid.  
5. IORDY is not supported in this mode.  
True IDE Multiword DMA Read/Write Access Timing  
This function does not apply to SiliconDrive EPs that have DMA disabled.  
tM  
-CS0, -CS1  
t N  
tO  
DMARQ  
(See Note 1)  
t L  
-DMACK  
(See Note 2)  
tI  
tD  
tK  
tJ  
-IORD  
-IOWR  
tZ  
tE  
Read Data  
(D15:D00)  
tF  
G
t
Write Data  
(D15:D00)  
t H  
tG  
Figure 5: True IDE Multiword DMA Read/Write Access Timing  
Notes:  
1. If the drive cannot sustain continuous, minimum cycle time DMA transfers, it  
may negate DMARQ within the time specified from the start of a DMA  
transfer cycle to suspend the DMA transfers in progress, and reassert the  
signal at a later time to continue the DMA operation.  
2. This signal may be negated by the host to suspend the DMA transfer in  
progress.  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 12: True IDE Multiword DMA Read/Write Access Timing  
Symbol Item  
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Note Units  
tO  
tD  
Cycle Time (minimum) 480  
150  
80  
120  
70  
100  
65  
80  
55  
1
1
ns  
ns  
-IORD/-IOWR  
Asserted Width  
(minimum)  
215  
tE  
tF  
tG  
tH  
tl  
-IORD Data Access  
(maximum)  
150  
5
60  
5
50  
5
50  
5
45  
5
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
-IORD Data Hold  
(minimum)  
-IORD/-IOWR Data  
Setup (minimum)  
100  
20  
0
30  
15  
0
20  
10  
0
15  
5
10  
5
-IOWR Data Hold  
(minimum)  
DMACK to –IORD/-  
IOWR Setup  
0
0
(minimum)  
tJ  
-IORD / -IOWR to -  
DMACK Hold  
(minimum)  
20  
5
5
5
5
-
ns  
tKR  
tKW  
tLR  
tLW  
tM  
-IORD Negated Width 50  
(minimum)  
50  
50  
40  
40  
30  
25  
25  
35  
35  
25  
25  
25  
35  
35  
10  
20  
20  
35  
35  
5
1
1
-
ns  
ns  
ns  
ns  
ns  
-IOWR Negated Width 215  
(minimum)  
-IORD to DMARQ  
Delay (maximum)  
120  
-IOWR to DMARQ  
Delay (maximum)  
40  
-
CS(1:0) Valid to –  
IORD / -IOWR  
50  
-
tN  
tZ  
CS(1:0) Hold  
-DMACK  
15  
20  
10  
25  
10  
25  
10  
25  
10  
25  
-
-
ns  
ns  
Note:  
1. The symbol t is the minimum total cycle time and t is the minimum  
0
D
command active time, while t  
and t  
are the minimum command  
KR  
KW  
recovery times or command inactive times for input and output cycles,  
respectively. The actual cycle time equals the sum of the actual command  
active time and the actual command inactive time. The three timing  
requirements of t , t , t , and t must be met. The minimum total cycle  
0
D
KR  
KW  
time requirement is greater than the sum of t and t , or t for input and  
D
KR  
KW  
output cycles, respectively. This means a host implementation can lengthen  
either or both of t and either of t and t as needed to ensure that t is  
D
KR  
KW  
0
equal to or greater than the value reported in the device’s identify device  
data.  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
Ultra DMA Data Burst Timing Requirements  
The following figures and table describe the requirements for the Ultra DMA  
(UDMA) data burst timing.  
DMARQ  
(device)  
tUI  
DMACK-  
(host)  
tFS  
tACK  
tENV  
tZAD  
STOP  
(host)  
tFS  
tACK  
tENV  
HDMARDY-  
(host)  
tZAD  
tZIORDY  
DSTROBE  
(device)  
tDVS  
tAZ  
tDVH  
DD(15:0)  
tACK  
DA0, DA1, DA2,  
CS0-, CS1-  
Figure 6: Initiating a UDMA Data-In Burst  
Note: The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE,  
and IORDY:DDMARDY-:DSTROBE signal lines are not in effect until  
DMARQ and DMACK are asserted.  
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SSD-DXXX(I)-4210 DATA SHEET  
t2CYC  
tCYC  
tCYC  
t2CYC  
DSTROBE  
at device  
tDVH  
tDVH  
tDVH  
tDVS  
tDVS  
DD(15:0)  
at device  
DSTROBE  
at host  
tDH  
tDH  
tDS  
tDH  
tDS  
DD(15:0)  
at host  
Figure 7: Sustained UDMA Data-In Burst  
Note: DD(15:0) and DSTROBE signals are shown at both the host and the  
device to emphasize that the cable settling time as well as cable  
propagation delay does not allow the data signals to be considered stable  
at the host until some time after they are driven by the device.  
DMARQ  
(device)  
DMACK-  
(host)  
tRP  
STOP  
(host)  
tSR  
HDMARDY-  
(host)  
tRFS  
DSTROBE  
(device)  
DD(15:0)  
(device)  
Figure 8: Host Pausing a UDMA Data-In Burst  
Notes:  
1. The host may assert STOP to request termination of the UDMA burst  
no sooner than t after HDMARDY- is negated.  
RP  
2. If the t timing is not satisfied, the host may receive zero, one, or two  
SR  
more data words from the device.  
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SSD-DXXX(I)-4210 DATA SHEET  
DMARQ  
(device)  
tMLI  
DMACK-  
(host)  
tACK  
tLI  
tLI  
STOP  
(host)  
tACK  
tLI  
HDMARDY-  
(host)  
tSS  
tIORDYZ  
DSTROBE  
(device)  
tZAH  
tAZ  
tDVS  
tDVH  
DD(15:0)  
CRC  
tACK  
DA0, DA1, DA2,  
CS0-, CS1-  
Figure 9: Device Terminating a UDMA Data-In Burst  
Note: The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE,  
and IORDY:DDMARDY-:DSTROBE signal lines are no longer in effect after  
DMARQ and DMACK are negated.  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
DMARQ  
(device)  
tLI  
tMLI  
DMACK-  
(host)  
tZAH  
tAZ  
tRP  
tACK  
STOP  
(host)  
tACK  
HDMARDY-  
(host)  
tRFS  
tMLI  
tLI  
tIORDYZ  
DSTROBE  
(device)  
tDVS  
tDVH  
DD(15:0)  
CRC  
tACK  
DA0, DA1, DA2,  
CS0-, CS1-  
Figure 10: Host Terminating a UDMA Data-In Burst  
Note: The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE,  
and IORDY:DDMARDY-:DSTROBE signal lines are no longer in effect after  
DMARQ and DMACK are negated.  
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SSD-DXXX(I)-4210 DATA SHEET  
DMARQ  
(device)  
tUI  
DMACK-  
(host)  
tACK  
tENV  
STOP  
(host)  
tZIORDY  
tLI  
tUI  
DDMARDY-  
(device)  
tACK  
HSTROBE  
(host)  
tDVS  
tDVH  
DD(15:0)  
(host)  
tACK  
DA0, DA1, DA2,  
CS0-, CS1-  
Figure 11: Initiating a UDMA Data-Out Burst  
Note: The definitions for the DIOW-:STOP, IORDY:DDMARDY-  
:DSTROBE, and DIOR-:HDMARDY-:HSTROBE signal lines are not in  
effect until DMARQ and DMACK are asserted.  
t2CYC  
tCYC  
tCYC  
t2CYC  
HSTROBE  
at host  
tDVH  
tDVH  
tDVH  
tDVS  
tDVS  
DD(15:0)  
at host  
HSTROBE  
at device  
tDH  
tDS  
tDH  
tDS  
tDH  
DD(15:0)  
at device  
Figure 12: Sustained UDMA Data-Out Burst  
Note: DD(15:0) and HSTROBE signals are shown at both the device and  
the host to emphasize that the cable settling time as well as cable  
propagation delay does not allow the data signals to be considered stable  
at the device until some time after they are driven by the host.  
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SSD-DXXX(I)-4210 DATA SHEET  
tRP  
DMARQ  
(device)  
DMACK-  
(host)  
STOP  
(host)  
tSR  
DDMARDY-  
(device)  
tRFS  
HSTROBE  
(host)  
DD(15:0)  
(host)  
Figure 13: Device Pausing a UDMA Data-Out Burst  
Notes:  
1. The device may negate DMARQ to request termination of the UDMA  
burst no sooner than t after DDMARDY- is negated.  
RP  
2. If the t timing is not satisfied, the host may receive zero, one, or two  
SR  
more data words from the host.  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
tLI  
DMARQ  
(device)  
tMLI  
DMACK-  
(host)  
tLI  
tACK  
tSS  
STOP  
(host)  
tLI  
tIORDYZ  
DDMARDY-  
(device)  
tACK  
HSTROBE  
(host)  
tDVS  
tDVH  
DD(15:0)  
(host)  
CRC  
tACK  
DA0, DA1, DA2,  
CS0-, CS1-  
Figure 14: Host Terminating a UDMA Data-Out Burst  
Note: The definitions for the DIOW-:STOP, IORDY:DDMARDY-  
:DSTROBE, and DIOR-:HDMARDY-:HSTROBE signal lines are no longer  
in effect after DMARQ and DMACK are negated.  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
DMARQ  
(device)  
DMACK-  
(host)  
tLI  
tMLI  
tACK  
STOP  
(host)  
tRP  
tIORDYZ  
DDMARDY-  
(device)  
tRFS  
tMLI  
tACK  
tLI  
HSTROBE  
(host)  
tDVS  
tDVH  
DD(15:0)  
(host)  
CRC  
tACK  
DA0, DA1, DA2,  
CS0-, CS1-  
Figure 15: Device Terminating a UDMA Data-Out Burst  
Note: The definitions for the DIOW-:STOP, IORDY:DDMARDY-  
:DSTROBE, and DIOR-:HDMARDY-:HSTROBE signal lines are no longer  
in effect after DMARQ and DMACK are negated.  
Table 13: UDMA Data Burst Timing Requirements  
Mode 0  
Mode 1  
Mode 2  
Mode 3  
Mode 4  
Comment (see Notes 1 and  
2)  
Symbol  
Units  
ns  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
t
t
240  
112  
-
-
160  
73  
-
-
120  
54  
-
-
90  
39  
-
-
60  
25  
-
-
Typical sustained average  
two-cycle time.  
2CYCTYP  
CYC  
Cycle time allowing for  
asymmetry and clock  
ns  
variations (from STROBE  
edge to STROBE edge).  
t
230  
-
-
154  
-
-
115  
-
-
86  
-
-
57  
-
-
Two-cycle time allowing for  
clock variations (from rising  
edge to next rising edge, or  
from falling edge to next  
falling edge of STROBE).  
ns  
2CYC  
t
t
15  
5
10  
5
7
5
7
5
5
5
Data setup time at recipient.  
Data hold time at recipient.  
ns  
ns  
DS  
DH  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 13: UDMA Data Burst Timing Requirements (Continued)  
Mode 0  
Mode 1  
Mode 2  
Mode 3  
Mode 4  
Comment (see Notes 1 and  
2)  
Symbol  
Units  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
t
70  
6
-
-
48  
6
-
-
30  
6
-
-
20  
6
-
-
6
6
-
-
Data valid setup time at  
sender (from data valid until  
STROBE edge) (see Note 4).  
ns  
DVS  
DVH  
t
Data valid hold time at sender ns  
(from STROBE edge until  
data may become invalid)  
(see Note 4).  
t
0
230  
0
200  
0
170  
0
130  
0
120 First STROBE time (for  
device to first negate  
ns  
FS  
DSTROBE from STOP during  
a data-in burst).  
t
t
t
t
0
150  
0
150  
0
150  
0
100  
0
100 Limited interlock time (see  
Note 3).  
ns  
ns  
LI  
20  
0
-
20  
0
-
20  
0
-
20  
0
-
20  
0
-
Interlock time with minimum  
(see Note 3).  
MLI  
UI  
-
-
-
-
-
Unlimited interlock time (see ns  
Note 3).  
-
10  
-
10  
-
10  
-
10  
-
10  
Maximum time allowed for  
output drivers to release  
(from asserted or negated).  
ns  
AZ  
t
t
t
20  
0
-
20  
0
-
20  
0
-
20  
0
-
20  
0
-
Minimum delay time required ns  
for output.  
ZAH  
ZAD  
ENV  
-
-
-
-
-
Drivers to assert or negate  
(from released).  
ns  
20  
70  
20  
70  
20  
70  
20  
55  
20  
55  
Envelope time (from DMACK- ns  
to STOP and HDMARDY-  
during data-in burst initiation,  
and from DMACK to STOP  
during data-out burst  
initiation).  
t
-
-
50  
75  
-
-
30  
70  
-
-
20  
60  
-
-
NA  
60  
-
-
NA  
60  
STROBE to DMARDY- time  
(if DMARDY- is negated  
before this long after  
STROBE edge, the recipient  
receives no more than one  
additional data word).  
ns  
SR  
t
Ready-to-final STROBE time ns  
(no STROBE edges are sent  
this long after negation of  
DMARDY-).  
RFS  
t
t
t
t
160  
-
-
125  
-
-
100  
-
-
100  
-
100  
-
-
Minimum time to assert STOP ns  
or negate DMARQ.  
RP  
20  
-
20  
-
20  
-
20  
-
20  
-
Maximum time before  
releasing IORDY.  
ns  
IORDYZ  
ZIORDY  
ACK  
0
0
0
0
0
Minimum time before driving ns  
STROBE (see note 5).  
20  
-
20  
-
20  
-
20  
-
20  
-
Setup and hold times for  
DMACK- (before assertion or  
negation).  
ns  
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ELECTRICAL SPECIFICATION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 13: UDMA Data Burst Timing Requirements (Continued)  
Mode 0  
Mode 1  
Mode 2  
Mode 3  
Mode 4  
Comment (see Notes 1 and  
2)  
Symbol  
Units  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
50 50 50 50 50  
t
-
-
-
-
-
Time from STROBE edge to  
negation of DMARQ or  
ns  
SS  
assertion of STOP (when the  
sender terminates a burst).  
Notes:  
1. Timing parameters are measured at the connector of the sender or receiver to which the parameter applies.  
Both STROBE and DMARDY- timing measurements are taken at the sender’s connector.  
Example: For example, the sender stops generating STROBE edges t  
after the negation of DMARDY-.  
RFS  
2. All timing measurement switching points (low-to-high and high-to-low) are taken at 1.5V.  
3. The symbols t , t , and t indicate sender-to-recipient or recipient-to-sender interlocks (i.e., either the sender  
UI MLI  
LI  
or recipient is waiting for the other to respond with a signal before proceeding). The symbol t is an unlimited  
UI  
interlock that has no maximum time value, t  
limited time-out that has a defined maximum.  
is a limited time-out that has a defined minimum, and t is a  
MLI  
LI  
4. The test load for t  
and t  
are a lumped capacitor load with no cable or receivers. Timing for t  
and t  
DVS DVH  
DVS  
DVH  
are met for all capacitive loads from 15pF to 40pF where all signals have the same capacitive load value.  
5. The symbol t may be greater than t since the device has a pull-up on IORDY- giving it a known state  
ZIORDY  
ENV  
when released.  
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ATA AND TRUE IDE REGISTER DECODING  
SSD-DXXX(I)-4210 DATA SHEET  
ATA AND TRUE IDE REGISTER DECODING  
SiliconDrive EP can be configured as either a a memory-mapped or an an I/O  
devices. As noted earlier, communication to and from the drive is  
accomplished using the ATA Command Block.  
TASK FILE REGISTER SPECIFICATION  
The Task File registers are used for reading and writing the storage data in the  
SiliconDrive EP. The decoded addresses are as shown in the following table.  
Table 14: Task File Register Specification  
CS0# CS1# DA02 DA01 DA00 DIOR# = L  
DIOW# = L  
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
X
X
0
1
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
0
1
Data  
Data  
Error  
Feature  
Sector Count  
Sector Count  
Sector Number Sector Number  
Cylinder Low  
Cylinder High  
Drive/Head  
Status  
Cylinder Low  
Cylinder High  
Drive/Head  
Command  
Invalid  
Invalid  
High-Z  
Not Used  
High-Z  
Not Used  
High-Z  
Not Used  
Alternate Status Device Control  
Device Address Not Used  
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
ATA REGISTERS  
DATA REGISTER  
The Data register is a 16-bit register used to transfer data blocks between the  
host and drive buffers. The register may set to 8-bit mode by using the Set  
Features Command defined in "Seek — 7Xh" on page 59.  
ERROR REGISTER  
The Error register contains the error status, if any, generated from the last  
executed ATA command. The contents are qualified by the ERR bit being set  
Table 15: Error Register  
D
D
D
D
D
D
D
D
0
Operation  
7
6
5
4
3
2
1
Read  
BBK UNC  
MC  
0
IDNF MCR ABRT TKNOF AMNF  
Default  
Value  
0
0
0
0
0
0
0
Bit(s) Description  
7
6
Bad Block Detected (BBK). Set when a bad block is detected.  
Uncorrectable Data Error (UNC). Set when an uncorrectable error  
is encountered.  
5
4
3
2
Media Changed (MC). Set to 0.  
ID Not Found (IDNF). Set when the sector ID is not found.  
MCR (Media Change Request). Set to 0.  
Aborted Command (ABRT). Set when a command is aborted due  
to a drive error.  
1
0
Track 0 Not Found (TKONF). Set when the execute drive  
diagnostic command is executed.  
Address Mark Not Found (AMNF). Set in the case of a general  
error.  
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
FEATURE REGISTER  
The Feature register is command-specific and used to enable and disable  
interface features. This register supports only either odd or even byte data  
transfers.  
Table 16: Feature Register  
Operation  
D
D
D
D
D
D
D
D
0
7
6
5
4
3
2
1
Read/Write  
Feature Byte  
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
SECTOR COUNT REGISTER  
The Sector Count register is used to read or write the sector count of the data  
for which an ATA transfer has been made.  
Table 17: Sector Count Register  
D
D
D
D
D
D
D
1
Operation  
D
7
6
5
4
3
2
0
Read/Write  
Default Value  
Sector Count  
0
0
0
0
0
0
0
1
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
SECTOR NUMBER REGISTER  
The Sector Number register is set by the host to specify the starting sector  
number associated with the next ATA command to be executed. Following a  
qualified ATA command sequence, the device sets the register value to the  
last sector read or written as a result of the previous AT command.  
When Logical Block Addressing (LBA) mode is implemented and the host  
issues a command, the contents of the register describe the Logical Block  
Number bits A[7:0]. Following an ATA command, the device loads the register  
with the LBA block number resulting from the last ATA command.  
Table 18: Sector Number Register  
D
D
D
D
D
D
D
1
Operation  
D
7
6
5
4
3
2
0
Read/Write  
Sector Number (CHS Addressing)  
Logical Block Number bits A07-A00 (LBA Addressing)  
Default Value  
0
0
0
0
0
0
0
1
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
CYLINDER LOW REGISTER  
The Cylinder Low register is set by the host to specify the cylinder number low  
byte. Following an ATA command, the content of the register is written by the  
device, identifying the cylinder number low byte.  
In LBA mode, the 8-bit register maintains the contents of the Logical Block  
number address bits A15:A08.  
Table 19: Cylinder Low Register  
D
D
D
D
D
D
D
1
Operation  
D
7
6
5
4
3
2
0
Read/Write  
Cylinder Number Low Byte (CHS Addressing)  
Logical Block Number bits A15-A08 (LBA Addressing)  
Default Value  
0
0
0
0
0
0
0
0
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
CYLINDER HIGH REGISTER  
The Cylinder High register is set by the host to specify the cylinder number  
high byte. Following an ATA command, the content of the register is set  
internally by the device, identifying the cylinder number high byte.  
In LBA mode, the 8-bit register maintains the contents of the Logical Block  
number address bits A23:A16.  
Table 20: Cylinder High Register  
D
D
D
D
D
D
D
1
Operation  
D
7
6
5
4
3
2
0
Read/Write  
Cylinder Number Low Byte (CHS Addressing)  
Logical Block Number bits A23-A16 (LBA Addressing)  
Default Value  
0
0
0
0
0
0
0
0
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
DRIVE/HEAD REGISTER  
The Drive/Head register is used by the host and the device to select the type  
of addressing (CHS or LBA), the drive letter, and either bits 3-0 of the head  
number in CHS mode or logical block number bits 27-24 in LBA mode.  
Table 21: Drive/Head Register  
Operation  
D
D
D
D
D
D
D
D
0
7
6
5
4
3
2
1
Read/Write  
1
LBA  
1
DRV  
HS3  
HS2  
HS1  
HS0  
LBA24  
LBA27 LBA26 LBA25  
Default  
Value  
1
0
1
0
0
0
0
0
The Drive/Head register is used by the host to specify one of a pair of ATA  
drives present in the platform.  
Bit(s)  
Description  
6
4
LBA. Selects between CHS (0) and LBA (1) addressing mode.  
Drive Address (DRV). Indicates the drive number selected by the  
host, either 0 or 1.  
3-0  
HS3 to 0. Indicates bits 3-0 of the head number in CHS addressing  
mode or LBA bits 27-24 in LBA mode.  
• CHS to LBA conversion: LBA = (C x HpC + H) x SpH + S -1  
• LBA to CHS conversion:  
C = LBA/(HpC x SpH)  
H = (LBA/SpH) mod (HpC)  
S = (LBA mod(SpH)) + 1  
...where:  
C is the cylinder number  
H is the head number  
S is the sector count  
HpC is the head count per cylinder count  
SpH is the sector count per head count (track)  
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
STATUS REGISTER  
The Status register provides the device’s current status to the host. The status  
register is an 8-bit read-only register. When the contents of the register are  
read by the host, the IREQ# bit is cleared.  
Table 22: Status Register  
D
D
D
D
D
D
D
D
0
Operation  
7
6
5
4
3
2
1
Read/Write  
Default Value  
BSY DRDY DWF DSC DRQ CORR IDX ERR  
0
0
0
0
0
0
0
0
Bit(s) Description  
7
Busy (BSY). Set when the drive is busy and unable to process any  
new ATA commands.  
6
Data Ready (DRDY). Set when the device is ready to accept ATA  
commands from the host.  
5
4
Drive Write Fault (DWF). Always set to 0.  
Drive Seek Complete (DSC). Set when the drive heads have been  
positioned over a specific track.  
3
Data Request (DRQ). Set when a device is ready to transfer a word  
or byte of data to or from the host and the device.  
2
1
0
Corrected Data (CORR). Always set to 0.  
Index (IDX). Always set to 0.  
Error (ERR). Set when an error occurs during the previous ATA  
command.  
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
COMMAND REGISTER  
The Command register specifies the ATA command code being issued to the  
drive by the host. Execution of the command begins immediately following the  
issuance of the command register code by the host.  
Table 23: Command Register  
D
D
D
D
D
D
D
D
0
Operation  
7
6
5
4
3
2
1
Read/Write  
ATA Command Code  
supported ATA commands.  
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
ALTERNATE STATUS REGISTER  
The Alternate Status register is a read-only register indicating the status of the  
device, following the previous ATA command. See "Status Register" on page  
35 for specific details.  
Table 24: Alternate Status Register  
D
D
D
D
D
D
D
D
0
Operation  
7
6
5
4
3
2
1
Read/Write  
Default Value  
BSY DRDY DWF DSC DRQ CORR IDX ERR  
0
0
0
0
0
0
0
0
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
DEVICE CONTROL REGISTER  
The Device Control register is used to control the interrupt request and issue  
ATA software resets.  
Table 25: Device Control Register  
D
D
D
D
D
D
D
D
0
Operation  
7
6
5
4
3
2
1
Write  
-
-
-
-
1
SRST nIEN  
0
Bit(s)  
Description  
7-4  
3
Reserved bits.  
Always set to 1.  
Software Reset (SRST). When set, resets the ATA software.  
2
1
Interrupt Enable (nIEN). When set, device interrupts are disabled.  
There is no function in the memory-mapped mode.  
0
Always set to 0.  
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ATA REGISTERS  
SSD-DXXX(I)-4210 DATA SHEET  
DEVICE ADDRESS REGISTER  
The Device Address register is used to maintain compatibility with ATA disk  
drive interfaces.  
Table 26: Device Address Register  
D
D
D
D
D
D
D
D
0
Operation  
7
6
5
4
3
2
1
Read/Write  
Default Value  
-
nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0  
0
0
1
1
1
1
1
0
Bit(s) Description  
7
Reserved bit.  
6
Write Gate (nWTG). Low when a write to the device is in process.  
5-2  
nHS3 to nHS0. The negated binary address of the currently selected  
head.  
1
0
nDS1. Low when drive 1 is selected and active.  
nDS0. Low when drive 0 is selected and active.  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
ATA COMMAND BLOCK AND SET DESCRIPTION  
In accordance with the ANSI ATA Specification, the device implements seven  
registers that are used to transfer instructions to the device by the host. These  
commands follow the ANSI standard ATA protocol. A description of the ATA  
command block is provided in the following table.  
Table 27: ATA Command Block and Set Description  
D
D
D
D
D
D
D
D
0
Operation  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
1
LBA  
1
Drive  
X
X
ATA COMMAND SET  
Table 28: ATA Command Set  
Registers Used  
FR SC SN CY DH LBA  
Command  
Code  
Class Command Name  
1
1
Check Power Mode  
98h, E5h  
90h  
-
-
-
-
-
-
-
-
D
D
-
-
Execute Drive  
Diagnostics  
1
2
1
1
1
1
Erase Sector  
Format Track  
Identify Drive  
Idle  
C0h  
-
-
-
-
-
-
Y
Y
-
Y
-
Y
Y
-
Y
Y
D
D
D
Y
Y
Y
-
50h  
ECh  
-
97h, E3h  
95h, E1h  
91h  
Y
-
-
-
Idle Immediate  
-
-
-
Initialize Drive  
Parameters  
Y
-
-
-
1
1
1
Read Buffer  
Read DMA*  
Read Multiple  
E4h  
C8h  
C4h  
-
-
-
-
-
-
D
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 28: ATA Command Set (Continued)  
Registers Used  
Command  
Code  
Class Command Name  
FR SC SN CY DH LBA  
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
3
3
Read Long Sector  
Read Sector(s)  
22h, 23h  
20h, 21h  
-
-
-
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
Y
D
Y
D
D
D
D
D
Y
Y
D
Y
Y
Y
Y
Y
Y
Y
-
-
Read Verify Sector(s) 40h, 41h  
Y
-
Recalibrate  
1Xh  
Request Sense  
Seek  
03h  
-
-
-
-
7Xh  
-
Y
-
Y
-
Y
-
Set Features  
Set Multiple Mode  
Set Sleep Mode  
Standby  
EFh  
C6h  
Y
-
-
-
-
99h, E6h  
96h, E2h  
94h, E0h  
87h  
-
-
-
-
-
-
-
Standby Immediate  
Translate Sector  
Wear Level  
-
-
-
-
Y
-
Y
-
Y
-
Y
-
F5h  
Write Buffer  
E8h  
-
-
-
-
Write DMA*  
CAh  
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Write Long Sector  
Write Multiple  
32h, 33h  
C5h  
Y
Y
Write Multiple w/o  
Erase  
CDh  
2
2
Write Sector(s)  
30h, 31h  
38h  
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Write Sector(s) w/o  
Erase  
3
Write Verify  
3Ch  
-
Y
Y
Y
Y
Y
* = This function does not apply to SiliconDrive EPs that have DMA disabled.  
Notes:  
• CY = Cylinder  
• SC = Sector Count  
• DH = Drive/Head  
• SN = Sector Number  
• FR = Feature LBA — LBA bit of the Drive/Head register (D denotes that  
only the drive bit is used)  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Check Power Mode — 98h, E5h  
The Check Power Mode command verifies the device’s current power mode.  
When the device is configured for standby mode or is entering or exiting  
standby, the BSY bit is set, the Sector Count register set to 00h, and the BSY  
bit is cleared. In idle mode, BSY is set and the Sector Count register is set to  
FFh. The BSY bit is then cleared and an interrupt is issued.  
Table 29: Check Power Mode — 98h, E5h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
X
X
X
Drive  
98h or E5h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Executive Drive Diagnostic — 90h  
The Executive Drive Diagnostic performs an internal read write diagnostic test  
using (AA55h and 55AAh). If an error is detected in the read/write buffer, the  
Error register reports the appropriate diagnostic code.  
Table 30: Executive Drive Diagnostic — 90h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
X
X
X
Drive  
90h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Format Track — 50h  
The Format Track command formats the common solid-state memory array.  
Table 31: Format Track — 50h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
1
LBA  
1
Drive Head Number (LBA27-24)  
50h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Identify Drive — ECh  
Issued by the host, the Identify Drive command provides 256 bytes of drive  
attribute data (i.e., sector size, count, and so on) The identify drive data  
structure is detailed in the following table.  
Table 32: Identify Drive — ECh  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
X
X
X
Drive  
ECh  
X
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Identify Drive — Drive Attribute Data  
Table 33: Identify Drive — Drive Attribute Data  
Data Default Bytes Data Description  
Word  
Address  
0
045Ah  
2
General configuration bit information  
• 15: Non-magnetic disk  
• 14: Formatting speed latency  
permissible gap needed  
• 13: Track Offset option supported  
• 12: Data Strobe Offset option supported  
• 11: Over 0.5% rotational speed  
difference  
• 10: Disk transfer rate > 10Mbps  
• 9: 10Mbps >= disk transfer rate > 5Mbps  
• 8: 5Mbps >= disk transfer rate  
• 7: Removable cartridge drive  
• 6: Fixed drive  
• 5: Spindle Motor Control option  
executed  
• 4: Over 15μs changing head time  
• 3: Non-MFM encoding  
• 2: Soft sector allocation  
• 1: Hard sector allocation  
• 0: Reserved  
1
XXXXh  
0000h  
00XXh  
0000h  
XXXXh  
XXXXh  
XXXXh  
0000h  
XXXXh  
2
Number of cylinders  
2
2
Reserved  
3
2
Number of heads  
4
2
Number of unformatted bytes per track  
Number of unformatted bytes per sector  
Number of sectors per track  
Number of sectors per device  
Reserved  
5
2
6
2
7-8  
9
4
2
10-19  
20  
Serial number  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 33: Identify Drive — Drive Attribute Data (Continued)  
Word  
Address  
Data Default Bytes Data Description  
20  
0001h  
2
Buffer type  
• 0000h: Not specified  
• 0001h: A single-ported, single-sector  
buffer  
• 0002h: A dual-ported multisector buffer  
• 0003h: A dual-ported multisector buffer  
with a read caching  
21  
22  
0001h  
0004h  
2
2
Buffer size in 512-byte increments  
Number of ECC bytes passed on read/  
write long commands  
23-26  
27-46  
47  
XXXXh  
XXXXh  
8001h  
8
Firmware revision (eight ASCII characters)  
Model number (40 ASCII characters)  
40  
2
15-8: Maximum number of sectors that can  
be transferred with a Read/Write Multiple  
command per interrupt  
48  
49  
0000h  
0f00h  
2
2
Double word (32 bit) not supported  
• 11: IORDY supported  
• 9: LBA supported  
• 8: DMA supported  
50  
51  
52  
53  
0000h  
0200h  
0000h  
0007h  
2
2
2
2
Reserved  
15-8: PIO data transfer cycle timing  
15-8: DMA data transfer cycle timing  
• 2: Word 88 is valid  
• 1: Words 64-70 are valid  
• 0: Words 54-58 are valid  
54  
XXXXh  
XXXXh  
XXXXh  
XXXXh  
010Xh  
2
2
2
4
2
Current number of cylinders  
Current number of heads  
Current sectors per track  
Current capacity in sectors  
55  
56  
57-58  
59  
7-0: Current sectors can be transferred  
with a Read/Write Multiple command per  
interrupt  
60-61  
XXXXh  
4
Total number of sectors addressable in  
LBA mode  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Table 33: Identify Drive — Drive Attribute Data (Continued)  
Word  
Address  
Data Default Bytes Data Description  
62  
63  
0000h  
0007h  
2
2
Single-word DMA modes supported  
• 2: Multiword DMA mode 2 supported  
• 1: Multiword DMA mode 1 supported  
• 0: Multiword DMA mode 0 supported  
64  
65  
0003h  
0078h  
2
2
7-0: Advanced PIO modes supported  
15-0: Multiword DMA cycle time in  
nanoseconds  
66  
67  
68  
80  
0078h  
0078h  
0078h  
003Eh  
2
2
2
2
15-0: Multiword DMA transfer cycle time in  
nanoseconds  
15-0: PIO mode cycle time without flow  
control  
15-0: PIO mode cycle time with IORDY  
flow control  
• 5: ATA/ATAPI-5 supported  
• 4: ATA/ATAPI-4 supported  
• 3: ATA-3 supported  
• 2: ATA-2 supported  
• 1: ATA-2 supported  
• 0: Reserved  
88  
001Fh  
0002h  
2
2
• 4: UDMA mode 4 supported  
• 3: UDMA mode 3 supported  
• 2: UDMA mode 2 supported  
• 1: UDMA mode 1 supported  
• 0: UDMA mode 0 supported  
163  
2: Multiword DMA mode and PIO mode 6  
supported  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Idle — 97h, E3h  
When issued by the host, the device’s internal controller sets the BSY bit,  
enters the Idle mode, clears the BSY bit, and generates an interrupt. If the  
sector count is non-zero, it is interpreted as a timer count with each count  
being 5ms, and the automatic power-down mode is enabled. If the sector  
count is zero, the automatic power-down mode is disabled.  
Table 34: Idle — 97h, E3h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Timer Count (5ms increments)  
X
X
X
X
X
X
Drive  
X
97h or E3h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Idle Immediate — 95h, E1h  
When issued by the host, the device’s internal controller sets the BSY bit,  
enters Idle Mode, clears the BSY bit, and issues an interrupt. The interrupt is  
issued whether or not the Idle mode is fully entered.  
Table 35: Idle Immediate — 95h, E1h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
X
X
X
Drive  
95h or E1h  
X
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Initialize Drive Parameters — 91h  
Initialize Drive Parameters allows the host to set the sector counts per track  
and the head counts per cylinder to 1 Fixed. Upon issuance of the command,  
the device sets the BSY bit and associated parameters, clears the BSY bit,  
and issues an interrupt.  
Table 36: Initialize Drive Parameters — 91h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Sector Count (Number of Sectors)  
X
X
X
X
0
X
Drive  
Head Number  
(Number of Heads — 1)  
Command  
91h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Recalibrate — 1Xh  
The Recalibrate command sets the cylinder low and high, head number to 0h,  
and sector number to 1h in CHS mode. In LBA mode (i.e., LBA = 1), the sector  
number is set to 0h.  
Table 37: Recalibrate — 1Xh  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
1
LBA  
1
Drive  
1Xh  
X
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Read Buffer — E4h  
The Read Buffer command allows the host to read the contents of the sector  
buffer. When issued, the device sets the BSY bit and sets up the sector buffer  
data in preparation for the read operation. When the data is ready, the DRQ bit  
is set and the BSY bit in the Status register are set and cleared, respectively.  
Table 38: Read Buffer — E4h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
X
X
X
Drive  
E4h  
X
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Read DMA — C8h  
The Read DMA command allows the host to read data using the DMA transfer  
protocol.  
Note: This function does not apply to SiliconDrive EPs that have DMA  
disabled.  
Table 39: Read DMA — C8h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
1
LBA  
1
Drive Head Number (LBA27-24)  
C8h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Read Multiple — C4h  
The Read Multiple command executes similarly to the Read Sector command,  
with the exception that interrupts are issued only when a block containing the  
counts of sectors defined by the Set Multiple command is transferred.  
Table 40: Read Multiple — C4h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
1
LBA  
1
Drive Head Number (LBA27-24)  
C4h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Read Sector — 20h, 21h  
The Read Sector command allows the host to read sectors 1 to 256 as  
specified in the Sector Count register. If the sector count is set to 0h, all 256  
sectors of data are made available. When the command code is issued and  
the first sector of data has been transferred to the buffer, the DRQ bit is set.  
The Read Sector command is terminated by writing the cylinder, head, and  
sector number of the last sector read in the task file. On error, the read  
operation is aborted in the errant sector.  
Table 41: Read Sector — 20h, 21h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
1
LBA  
1
Drive Head Number (LBA27-24)  
20h or 21h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Read Long Sector(s) — 22h, 23h  
The Read Long Sector(s) command operates similarly to the Read Sector(s)  
command, with the exception that it transfers requested data sectors and ECC  
data. The long instruction ECC byte transfer for Long commands is a byte  
transfer at a fixed length of 4 bytes.  
Table 42: Read Long Sector(s) — 22h, 23h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
1
LBA  
1
Drive Head Number (LBA27-24)  
22h or 23h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Read Verify Sector(s) — 40h, 41h  
The Read Verify Sector(s) command operates similarly to the Read Sector(s)  
command, with the exception that is does not set the DRQ bit and does not  
transfer data to the host. When the requested sectors are verified, the onboard  
controller clears the BSY bit and issues an interrupt.  
Table 43: Read Verify Sector(s) — 40h, 41h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
1
LBA  
1
Drive Head Number (LBA27-24)  
40h or 41h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Seek — 7Xh  
The Seek command seeks and picks up the head to the tracks specified in the  
task file. When the command is issued, the solid-state memory chips do not  
need to be formatted. After an appropriate amount of time, the DSC bit is set.  
Table 44: Seek — 7Xh  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
1
LBA  
1
Drive Head Number (LBA27-24)  
7Xh  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Set Features — EFh  
The Set Features command allows the host to configure the feature set of the  
device according to the attributes listed in Table 46.  
Table 45: Set Features — EFh  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
Feature  
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
X
X
X
X
X
X
X
Drive  
EFh  
X
Table 46: Set Features’ Attributes  
Operation  
Enable 8-bit data transfer  
Feature  
01h  
66h  
81h  
BBh  
CCh  
Disable reverting to power on defaults  
Disable 8-bit data transfer  
4 bytes of data apply on Read/Write Long commands  
Enable revert to power on defaults  
On power-up or following a hardware reset, the device is set to the default  
mode 81h.  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Set Multiple Mode — C6h  
The Set Multiple Mode command allows the host to access the drive via Read  
Multiple and Write Multiple ATA commands. Additionally, the command sets  
the block count (i.e., the number of sectors within the block) for the Read/Write  
Multiple command. The sector count per block is set in the Sector Count  
register.  
Table 47: Set Multiple Mode — C6h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
X
X
X
X
X
X
Drive  
C6h  
X
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Set Sleep Mode — 99h, E6h  
The Set Sleep Mode command allows the host to set the device in sleep  
mode. When the onboard controller transitions to sleep mode, it clears the  
BSY bit and issues an interrupt. The device interface then becomes inactive.  
Sleep mode can be exited by issuing either a hardware or software reset.  
Table 48: Set Sleep Mode — 99h, E6h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
X
X
X
Drive  
99h or E6h  
X
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Standby — 96h, E2h  
When the Standby command is issued by the host, it transitions the device into  
standby mode. If the Sector Count register is set to a value other than 0h, the  
Auto Powerdown function is enabled and the device returns to Idle mode.  
Table 49: Standby — 96h, E2h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Timer Count (5ms x Timer Count)  
X
X
X
X
X
X
Drive  
X
96h or E2h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Standby Immediate — 94h, E0h  
When the Standby Immediate command is issued by the host, it transitions the  
device into standby mode.  
Table 50: Standby Immediate — 94h, E0h  
D
D
D
D
D
D
D
D
7
Register  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
X
X
X
Drive  
94h or E0h  
X
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Write Buffer — E8h  
The Write Buffer command allows the host to rewrite the contents of the  
512- byte data buffer with the wanted data.  
Table 51: Write Buffer — E8h  
D
D
D
D
D
D
D
D
7
Register  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
X
X
X
Drive  
E8h  
X
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Write DMA — CAh  
The Write DMA command allows the host to write data using the DMA transfer  
protocol.  
Note: This function does not apply to SiliconDrive EPs that have DMA  
disabled.  
Table 52: Write DMA — CAh  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low(LBA15-8)  
Cylinder High(LBA23-16)  
X
LBA  
X
Drive Head Number(LBA27-24)  
CAh  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Write Multiple — C5h  
The Write Multiple command operates in the same manner as the Write Sector  
command. When issued, the device sets the BSY bit within 400ns and  
generates an interrupt at the completion of a transferred block of sectors. The  
DRQ bit is set at the beginning of a block transfer.  
Table 53: Write Multiple — C5h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low(LBA15-8)  
Cylinder High(LBA23-16)  
X
LBA  
X
Drive Head Number(LBA27-24)  
C5h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Write Sector(s) — 30h, 31h  
The Write Sector(s) command writes from 1 to 256 sectors as specified in the  
Sector Count register. A sector count of 0 requests 256 sectors. When issued,  
the device sets the BSY bit within 400ns and generates an interrupt at the  
completion of a transferred block of sectors. The DRQ bit is set at the  
beginning of a block transfer.  
Table 54: Write Sector(s) — 30h, 31h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
X
LBA  
X
Drive Head Number (LBA27-24)  
30h or 31h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Write Long Sector(s) — 32h, 33h  
The Write Long Sector(s) command operates in the same manner as the Write  
Sector command — when issued, the device sets the BSY bit within 400ns  
and generates an interrupt at the completion of a transferred block of sectors.  
The DRQ bit is set at the beginning of a block transfer.  
Table 55: Write Long Sector(s) — 32h, 33h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
X
LBA  
X
Drive Head Number (LBA27-24)  
32h or 33h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Erase Sector(s) — C0h  
The Erase Sector(s) command is issued prior to the issuance of a Write  
Sector(s) or Write Multiple w/o Erase command.  
Table 56: Erase Sector(s) — C0h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
X
LBA  
X
Drive Head Number (LBA27-24)  
C0h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Request Sense — 03h  
The Request Sense command identifies the extended error codes generated  
by the preceding ATA command. The Request Sense command must be  
issued immediately following the detection of an error via the Error register.  
Table 57: Request Sense — 03h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
X
X
X
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
1
X
1
Drive  
03h  
X
The extended error codes are defined in the following table.  
Table 58: Extended Error Codes  
Extended Error Codes  
Description  
00h  
No error detected  
01h  
Self test is OK (no error)  
Miscellaneous error  
Invalid command  
09h  
20h  
21h  
Invalid address (requested head or sector invalid)  
Address overflow (address too large)  
Supply or generated voltage out of tolerance  
Uncorrectable ECC error  
2Fh  
35h, 36h  
11h  
18h  
Corrected ECC error  
05h, 30h-32h, 37h,3Eh  
Self test of diagnostic failed  
10h, 14h  
3Ah  
ID not found  
Spare sectors exhausted  
1Fh  
Data transfer error/aborted command  
0Ch, 38h, 3Bh, 3Ch, 3Fh Computed media format  
03h  
Write/erase failed  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Translate Sector — 87h  
The Translate Sector command is not currently supported by the  
SiliconSystems’ SiliconDrive EP. If the host issues this command, the device  
responds with 0x00h in the data register.  
Table 59: Translate Sector — 87h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
1
LBA  
1
Drive Head Number (LBA27-24)  
87h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Wear-Level — F5h  
The Wear-Level command is supported as an NOP command for the  
purposes of backward compatibility with the ANSI AT attachment standard.  
This command sets the Sector Count register to 0x00h.  
Table 60: Wear-Level — F5h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Completion Status  
X
X
X
X
X
X
Drive  
F5h  
Flag  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Write Multiple w/o Erase — CDh  
The Write Multiple w/o Erase command functions identically to the Write  
Multiple command, with the exception that the implied pre-erase (i.e., Erase  
Sector(s) command) is not issued prior to writing the sectors.  
Table 61: Write Multiple w/o Erase — CDh  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
X
LBA  
X
Drive Head Number (LBA27-24)  
CDh  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Write Sector(s) w/o Erase — 38h  
The Write Sector(s) w/o Erase command functions similar to the Write Sector  
command, with the exception that the implied pre-erase (i.e., Erase Sector(s)  
command) is not issued prior to writing the sectors.  
Table 62: Write Sector(s) w/o Erase — 38h  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
X
LBA  
X
Drive Head Number (LBA27-24)  
38h  
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ATA COMMAND BLOCK AND SET DESCRIPTION  
SSD-DXXX(I)-4210 DATA SHEET  
Write Verify — 3Ch  
The Write Verify command verifies each sector immediately after it is written.  
This command performs identically to the Write Sector(s) command, with the  
added feature of verifying each sector written.  
Table 63: Write Verify — 3Ch  
D
D
D
D
D
D
D
D
0
Register  
7
6
5
4
3
2
1
Feature  
X
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Drive Head  
Command  
Sector Count  
Sector Number (LBA7-0)  
Cylinder Low (LBA15-8)  
Cylinder High (LBA23-16)  
X
LBA  
X
Drive Head Number (LBA27-24)  
3Ch  
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SALES AND SUPPORT  
SSD-DXXX(I)-4210 DATA SHEET  
SALES AND SUPPORT  
To order or obtain information on pricing and delivery, contact your  
SiliconSystems Sales Representative.  
PART NUMBERING  
NOMENCLATURE  
The following table defines the SiliconDrive EP 2.5" PATA Drive part  
numbering scheme.  
Table 64: Part Numbering Nomenclature  
SSD-  
D
YYY  
I
T
-4210  
Part number suffix —  
contact your  
SiliconSystems’ Sales  
Representative  
Temperature Range:  
Blank = Commercial  
I = Industrial  
Interface:Blank = Parallel ATA (PATA)  
Capacity: 16G = 16GB to 64G = 64GB  
Form Factor: D = 2.5" Drive  
SiliconSystems’ SiliconDrive  
PART NUMBERS  
The following table lists the SiliconDrive EP’s part numbers.  
Table 65: Part Numbers  
Part Number  
Capacity  
SSD-D64G(I)-4210  
SSD-D32G(I)-4210  
SSD-D16G(I)-4210  
64GB  
32GB  
16GB  
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PART NUMBERING  
SSD-DXXX(I)-4210 DATA SHEET  
ROHS 6 OF 6 PRODUCT LABELING — PB-FREE IDENTIFICATION LABEL  
The Pb-free identification label indicates that the enclosed components/  
devices and/or assemblies do not contain any lead (i.e., they are lead-free, as  
defined in RoHS directive 2002/95/ED). The above symbol is on all RoHS 6 of  
6 compliant product labels, as seen in Figure 16.  
SAMPLE LABEL  
Standard Back Label with  
Front Label  
Lot Code Information  
SiliconSystems, Inc.  
SiliconDrive EP  
64GB  
0025/4210  
Figure 16: Sample Label  
SILICONSYSTEMS PROPRIETARY  
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.  
All unauthorized use and/or reproduction is prohibited.  
4210D-03DSR  
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FEBRUARY 2, 2009  
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RELATED DOCUMENTATION  
SSD-DXXX(I)-4210 DATA SHEET  
RELATED DOCUMENTATION  
For more information, visit www.siliconsystems.com or contact your  
SiliconSystems Sales Representative.  
Table 66: Related Documentation  
SiliconDrive EP  
Application-SpecificDescription  
Technology  
Document Number  
PowerArmor  
SiSMART  
Eliminates drive corruption.  
WP-007-0xR  
Calculates remaining useful life.WP-008-0xR  
SiliconSystems' performance tests, ratings, and product specifications are measured using specific computer systems  
and/or components and reflect the approximate performance of SiliconSystems’ products as measured by those tests.  
Any difference in system hardware or software design or configuration, as well as system use, may affect actual test  
results, ratings, and product specifications. SiliconSystems welcomes user comments and reserves the right to revise  
this document and/or make updates to product specifications, products, or programs described without notice at any  
time. SiliconSystems makes no representations or warranties regarding this document. The names of actual  
companies and products mentioned herein are the trademarks of their respective owners.  
®
®
®
®
®
®
®
SiliconSystems , SiliconDrive , SiliconDrive II , SiSecure , SiliconDrive EP , PowerArmor , SiSMART , SiKey™,  
SiZone™, SiProtect™, SiSweep™, SiPurge™, SiScrub™, SiliconDrive USB Blade™, SolidStor™, and the  
SiliconSystems logo are trademarks or registered trademarks of SiliconSystems, Inc. and may be used publicly only  
with the permission of SiliconSystems and require proper acknowledgement. Other listed names and brands are  
trademarks or registered trademarks of their respective owners.  
© Copyright 2009 by SiliconSystems, Inc. All rights reserved. No part of this publication may be reproduced without  
the prior written consent of SiliconSystems.  
SILICONSYSTEMS PROPRIETARY  
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.  
All unauthorized use and/or reproduction is prohibited.  
4210D-03DSR  
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FEBRUARY 2, 2009  
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