TMC2005-JT
ARCNET 5 Port HUB Controller
FEATURES
ƒ
ARCNET HUB Circuit for ARCNET Protocol
ƒ
ƒ
Can Connect with HYC9088 in Normal Mode
Can Connect with RS485 Transceiver,
HYC5000/4000/2000, Opt Module and TTL
Interface in Backplane Mode
Supports both Normal and Backplane Mode at
the Same Time for Media Conversion
+ 5V Single Power
(Data Rate From 156.25Kbps to 10Mbps)
Able to Connect Various Transceivers Directly
Device Includes TX/RX Timing Circuit for 5 Port
Hub and Direction Control Circuit, Jitter Correct
Circuit and Noise Cancel Circuit
ƒ
ƒ
ƒ
ƒ
ƒ
Easy to Design 8 or 12 Port Hub
GENERAL DESCRIPTION
When configuring a network, the maximum number of nodes and the maximum cable length are limited by the electric
capacity of the transceiver. In this case, the network is expanded by an equipment called a “HUB” or “repeater”. It
maybe necessary to have a converter between coax, T/P and the fiber cable. It is easy to design a HUB or a repeater
because the TMC2005 has various features for expanding such network.
It can connect with HYC9088, RS485 transceiver, HYC5000/4000/2000 and TTL interface for optical module. It can
connect with three different transceivers at the same time and convert the media of each. (The data rate cannot be
converted. It is necessary to operate all nodes in the same network at the same data rate). The Hubs can be
expanded by connecting two or more TMC2005 chips. By setting one of 5 ports to open-drain output, the Hub can be
expanded to either 12 or 16 ports.
ORDERING INFORMATION
Order Number(s):
TMC2005-JT for 64 pin, TQFP Lead-Free RoHS Compliant Package
SMSC TMC2005-JT
Revision 1.1 (07-24-07)
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ARCNET 5 Port HUB Controller
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TABLE OF CONTENTS
FEATURES..................................................................................................................................................................1
GENERAL DESCRIPTION.......................................................................................................................................1
PIN CONFIGURATION ............................................................................................................................................4
BLOCK DIAGRAM....................................................................................................................................................4
BLOCK DIAGRAM....................................................................................................................................................5
DESCRIPTION OF PIN FUNCTIONS ....................................................................................................................5
DESCRIPTION OF PIN FUNCTIONS ....................................................................................................................6
TX/RX INTERFACE....................................................................................................................................................7
OPERATING MODE SETUP..........................................................................................................................................8
PLL...........................................................................................................................................................................8
OTHER SIGNALS ........................................................................................................................................................9
OPERATIONAL DESCRIPTION...........................................................................................................................10
DIRECTION DETERMINATION ...................................................................................................................................10
DIRECTION RELEASE ...............................................................................................................................................10
JITTER FILTER..........................................................................................................................................................10
OPTION FEATURE FOR JITTER FILTERING.................................................................................................................11
OPTION FEATURE FOR NOISE CUT MODE .................................................................................................................11
APPLICATION NOTES ........................................................................................................................................12
PORT GROUP...........................................................................................................................................................20
VARIOUS SETUP.......................................................................................................................................................20
EXAMPLE FOR OPERATION MODE SETUP TO EACH PORT........................................................................................20
NOTE FOR UNUSED PORT .........................................................................................................................................20
EXAMPLE FOR POWER-ON RESET CIRCUIT ..............................................................................................................20
CONNECTING THE TMC2005 WITH INTERNAL PLL...................................................................................21
METHOD TO CONNECT A CRYSTAL CLOCK.............................................................................................................22
NPLLTST PIN..........................................................................................................................................................22
CASCADING CONNECTION ................................................................................................................................23
RING NETWORK WITH THE TMC2005.....................................................................................................................26
MAXIMUM GUARANTEED RATINGS*............................................................................................................27
STANDARD OPERATING CONDITION ............................................................................................................27
DC CHARACTERISTIC - INPUT PIN..................................................................................................................27
DC CHARACTERISTIC - OUTPUT PIN..............................................................................................................28
AC CHARACTERISTIC - CLOCK AND RESET...................................................................................................28
AC CHARACTERISTIC – RX WAVEFORMS AND TX WAVEFORMS ........................................................................29
TMC2005-JT 64 PIN TQFP PACKAGE OUTLINE.............................................................................................31
SMSC TMC2005-JT
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PIN CONFIGURATION
64 63 6261 60 59 58 57 56 55 54 53 52 51 50 49
TXENB1
48
1
2
3
4
5
6
7
8
9
VSS7
47
46
45
44
nPULSE1
nPULSE2
nP1BAK
VDD5
nCKOEN
nRST
VSS6
nBJA
nBJB
nBJE
nMBA
nMBB
nMBE
nEXTOD
NC
HM
SE
NC
LE
EXTRX
43
42
41
ME
VSS1
EXTTX
VDD1
CKO
VSS2
CKM2
CKM1
CKM0
NC
TMC2005-JT
40
10
11
12
13
39
38
37
36
35
34
14
15
16
33
17 18 19 20 21
32
22 23 24 25 26 27 28 29 30 31
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BLOCK DIAGRAM
nBJB nMBE nMBA
MB
LB
nBJE nBJA nMBB
ME MA
LE
LA
nEXTOD
SE SB SA
RXINA0
RXINA1
TXENA0
TXENA1
NOT
Circuit
OR
Circuit
NOT
Circuit
RXINB0
RXINB1
TXENB0
TXENB1
NOT
Circuit
OR
Circuit
NOT
Circuit
Direction Control
Circuit
EXTRX
NOT
OR
NOT
Circuit
Circuit
Circuit
HM
RXFLT
Output
Control
Circuit
EXTTX
Tx
Pulse
Gen.
nP1BAK
nPULSE1
nPULSE2
Rx
Buffer
VSS1- 8
VDD1- 6
DPLL
Clock Multiplier
PLL
XTLO
XTLI
AND
Circuit
CKO
AVDD
AVSS
nRST
CKM0 CKM2
AVSS
RO
nCKOEN
CKM1 nPLLTST
LP
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DESCRIPTION OF PIN FUNCTIONS
PIN NO.
NAME
INPUT/OUTPUT
DESCRIPTION
NOTE
1
TXENB1
OUTPUT
Port B-1 Tx output to media transceiver
Setting for traffic release time (It should
be open for normal operation.)
Port EXT. Polar assignment for EXTRX
input (0:active Hi, 1:active Low)
Reserved. It should be open.
Port EXT. Polar assignment of EXTTX
output (0:active Low, 1:active Hi)
Port EXT. RX-Data input from media
transceiver.
2
HM
INPUT
INPUT
Pull-up
3
4
SE
NC
Pull-up
5
6
LE
INPUT
INPUT
Pull-up
Pull-up
EXTRX
Port EXT. Output mode assignment of
EXTTX (0:pulse output, 1:Tx control
output)
7
ME
INPUT
Pull-up
8
9
VSS1
EXTTX
VDD1
CKO
VSS2
CKM2
CKM1
CKM0
NC
Ground
OUTPUT
OUTPUT
Port EXT. Output to media transceiver.
Power Supply
Clock Output
10
11
12
13
14
15
16
17
Ground
INPUT
INPUT
INPUT
Network speed (data rate) setting.
Pull-up
Pull-up
Pull-up
Reserved. It should be open.
Test Pin. It should be open.
Test Pin for PLL.. It should connected to
VDD (Set to high)
Power Supply
X'tal input/External clock input.
X'tal output
Ground
Reserved. It should be open.
Power Supply
Power Supply
Analog Power Supply
VCO output for internal PLL.
Connection pin to loop filter for internal
PLL.
Analog sense pin for internal PLL.
Analog Ground
RXFLT
INPUT
INPUT
Pull-up
18
19
20
21
22
23
24
25
26
27
nPLLTST
VDD2
XTLI
XTLO
VSS4
NC
VDD4
VDD3
AVDD
RO
INPUT
OUTPUT
OUTPUT
28
29
30
31
32
33
LP
OUTPUT
INPUT
AGS
AVSS
VSS3
VSS5
NC
Ground
Ground
Reserved. It should be open.
Port EXT. Open-drain mode (0:open-
drain output, 1:normal output)
Port EXT. Noise cut (0:on, 1:off)
Port A0/A1 Noise cut (0:on, 1:off)
Port B0/B1 Noise cut (0:on, 1:off)
Port EXT. Jitters correct mode (0:big
jitters mode, 1:normal mode)
Port A0/A1 Jitters correct mode (0:big
jitter mode, 1:normal mode)
Port B0/B1 Jitter correct mode (0:big
jitter mode, 1:normal mode)
Ground
34
35
36
37
nEXTOD
nMBE
nMBB
INPUT
INPUT
INPUT
INPUT
Pull-up
Pull-up
Pull-up
Pull-up
nMBA
38
39
nBJE
nBJB
INPUT
INPUT
INPUT
Pull-up
Pull-up
Pull-up
40
41
42
43
nBJA
VSS6
nRST
nCKOEN
INPUT
INPUT
Internal reset signal (active Low)
Enable of CKO output.
Pull-up
Pull-up
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PIN NO.
44
NAME
INPUT/OUTPUT
DESCRIPTION
Power Supply.
NOTE
VDD5
45
46
47
48
nP1BAK
nPULSE2
nPULSE1
VSS7
OUTPUT
OUTPUT
OUTPUT
nPULSE1 output (for backplane mode).
nPULSE2 output (for normal mode).
nPULSE1 output (for normal mode)
Ground
Port A-0 Rx-data input from media
transceiver.
49
RXINA0
INPUT
Pull-up
Pull-up
Port A. Polar assignment for RXINA0/A1
output (0:active Hi, 1:active Low)
Port A-0 Tx output to media transceiver.
Port A. Polar assignment for TXENA0/A1
output (0:active Low, 1:active Hi)
Port A-1 Rx-data input from media
transceiver.
50
51
SA
TXENA0
INPUT
OUTPUT
52
53
LA
INPUT
INPUT
Pull-up
Pull-up
RXINA1
Port A. Mode assignment for
TXENA0/A1 (0:pulse output, 1:Tx control
output)
Port A-1 Tx output to media transceiver.
Power Supply
54
55
56
57
58
MA
INPUT
OUTPUT
Pull-up
TXENA1
VDD6
NC
Reserved. It should be open.
Ground
VSS8
Port B-0 Rx-data input from media
transceiver.
59
RXINB0
INPUT
Pull-up
Pull-up
Port B. Polar assignment for RXINA0/A1
input (0:active Hi, 1:Active Low)
Port B-0 Tx output to media transceiver.
Port B. Polar assignment for TXENA0/A1
output (0:active Low, 1:active Hi)
Port B-1 Rx-data input from media
transceiver.
60
61
SB
TXENB0
INPUT
OUTPUT
62
63
LB
INPUT
INPUT
Pull-up
Pull-up
RXINB1
Port B. Mode assignment for
TXENA0/A1 (0:pulse output, 1:TX control
output)
64
MB
INPUT
Pull-up
Note:
Pull-up: Input with a pull-up resistor 70KΩ ± 30%
TX/RX Interface
FEATURE
NAME
INPUT/OUTPUT
DESCRIPTION
RX Port
RXINA [0:1]
RXINB [0:1]
EXTRX
INPUT
Setup the polarity by SA, SB, SE.
RX Port
TX Port
TX Port
Polar
Assignment
SA, SB, SE
INPUT
Setup the polarity of RXINA [0:1],
RXINB [0:1], EXTTX.
0 : active H
1: active L
TX data pulse (Mx=0) or TX
enable signal (Mx=1).
Setup TX mode by MA, MB, ME.
Setup the polarity by LA, LB, LE
TX pulse data into HYC9068S-
SK/9088S-SK when ARCNET
chip is at normal mode.
TX Control
TXENA [0:1]
TXENB [0:1]
EXTTX
OUTPUT
OUTPUT
TX Data
Output
nPULSE [1:2]
The pulse is always active Low.
TX pulse data into RS485 driver
or HYC2485S/2488S when
ARCNET chip is at backplane
TX Port
nP1BAK
OUTPUT
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FEATURE
NAME
INPUT/OUTPUT
DESCRIPTION
mode.
The pulse is always active Low.
Setup the polarity of TXENA
[0:1], TXENB [0:1], EXTTX.
0 : active L
TX Port
TX Port
Polarity
Setup
LA, LB, LE
INPUT
1: active H
Mode Setup
MA, MB, ME
INPUT
Setup the mode of TXENA [0:1],
TXENB [0:1], EXTTX.
0: Output TX pulse. (It is
equivalent to nTXEN “OR”
nP1BAK)
1: Output TX enable
Operating Mode Setup
INPUT/
OUTPUT
INPUT
FEATURE
Data rate
setup
NAME
CKM [0:2]
DESCRIPTION
Terminal to setup the data rate of TMC2005.
CKM2 CKM1 CKM0 DIVISOR MULTIPLIER SPEED
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
8
4
2
1
x1
x1
x1
x1
x1
x2
156.25 Kbps
312.5 Kbps
625 Kbps
1.25 Mbps
2.5 Mbps
5 Mbps
1
Reserved Reserved
x4
Reserved
10 Mbps
1
External clock is 20MHz.
Refer to “VARIOUS SETUP”
Noise cut
mode
nMBA
nMBB
nMBE
INPUT
INPUT
0: Cut off noise from received data
1: Don’t cut off noise
Setup “0” normally.
Setup a jitter filter feature.
Select a pulse as reference phase used by DPLL.
Big jitter
mode
nBJA
nBJB
nBJE
0: 2nd pulse (big jitter mode)
1: 1st pulse (normal mode)
Setup a the use of EXTTX port.
Open drain
mode
nEXTOD
INPUT
0: Set EXTTX as open drain output and use as Ext.
1: Set EXTTX as normal output and use as 5th port.
PLL
INPUT/
OUTPUT
OUTPUT
FEATURE
NAME
LP
DESCRIPTION
Using PLL: Connect to an external condenser
“C1” for loop filter.
Using no PLL: must be open.
RO
OUTPUT
INPUT
VCO output
Using PLL: Connect to an external resistor “R0” for
loop filter.
Using no PLL: must be open.
AGS
Analog sense input.
Using PLL: Connect to loop filter.
Using no PLL: Connect to ground.
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INPUT/
OUTPUT
INPUT
FEATURE
NAME
nPLLTST
DESCRIPTION
Test pin for PLL.
Must always connect to VDD.
AVDD
Analog power supply
Using PLL: Analog power supply. There are some
limits on PCB pattern.
Using no PLL: Power supply (+5V) same as VDD1~6.
AVSS
Analog ground
Using PLL: Analog ground. There are some limits on
PCB pattern.
Using no PLL: Use a ground same as VSS1~8.
Other Signals
INPUT/
FEATURES
NAME
OUTPUT
DESCRIPTION
CRYSTAL
XTLI
INPUT
Connect a 20MHz crystal.
INTERFACE
When supplying an external clock,
input the clock to this pin.
Connect a 20MHz crystal.
When supplying an external clock, it
must be open.
CRYSTAL
INTERFACE
XTLO
nRST
OUTPUT
INPUT
SYSTEM RESET
INTERFACE
TEST PIN
Reset for initializing TMC2005. (active
Low)
CKO
nCKOEN
OUTPUT
INPUT
Output internal clock of TMC2005.
Output control of CKO.
0: Output internal clock on CKO.
1: Always output Low level on CKO.
Set “1” Normally.
TEST PIN
TEST PIN
TEST PIN
POWER SUPPLY
GROUND
RXFLT
NC [1:2]
VDD [1:6]
VSS [1:8]
INPUT
It must be open
It must be open
Power supply (+5V)
Ground
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OPERATIONAL DESCRIPTION
Direction Determination
All TX ports are set to disable mode in the initial state. When a signal is received from any RX ports, the circuit holds
the port on receiving mode (disable TX) and changes the other ports to sending mode (disable RX). One port stays in
RX and the rest change into TX after all. The circuit initializes the internal DPLL on the timing of received RX pulse,
and the RX buffer circuit stores the RX data and filters its jitter. TX controlling circuit regenerates the stored RX pulse
on nPULSE1, nPULSE2 and nP1BAK. The nPULSE1 and nPULSE2 are pulse output pins for transceivers
(HYC9088A) of ARCNET normal mode. The nP1BAK is a pulse output pin for transceiver (HYC5000/4000/2000 and
RS485 driver) of ARCNET back plane mode. When using optical transceiver, instead of these signals, TXENA [0:1],
TXENB [0:1], EXTTX (MA, MB, ME = 0) must be used as TX data inputs of the optical transceiver.
Direction Release
On ARCNET protocol, each TX message starts with 6-bits of “1” ALERT and each data byte is lead by three bits (1, 1,
0) preamble. To control the HUBs direction, the circuit monitors this bit pattern and holds the state. If the end of the bit
pattern comes, all TX ports return receiving mode (disable TX) again. The interval timer detects the end of the bit
pattern. During data is on line, silent period is less than 4 uS* because at least one bit “1” among 10-bits is received
while receiving the data. The minimum silent interval from the end of received data to the alert of the next data (the
minimum time of changing the direction) is the chip turn around time (12.6 uS*) of ARCNET controller. The interval
timer to detect the data end is set to 5.6uS by adding some margin to the above interval for neglecting the reflection
on a cable.
[Note] Numbers marked * are at 2.5Mbps operation.
Jitter Filter
To build a network with transceivers that introduce big jitter like ones for optical fiber, the old HUB that has direction
control only may cause a transmission error because jitters on each HUB are added when several HUBs were
connected in serial. The TMC2005 fixes that problem with jitter filtering and wave shaping through the following three
steps.
1) Input Sampling
The TMC2005 samples a data on a network by eight times clock of the network data.
2) Jitter Filtering (DPLL)
The TMC2005 filters the jitter (± 100nS at 2.5Mbps) of network data sampled by 8X clock through the internal digital
PLL and stores the data into the buffer.
3) Wave Shaping Output
The TMC2005 re-synchronizes and regenerates the network data at the same clock as the data rate.
The capability of the jitter filtering is shown below.
DATA RATE
10Mbps
CAPABILITY OF JITTER FILTERING
± 25nS
± 50nS
5Mbps
2.5Mbps
± 100nS
± 200nS
± 400nS
± 800nS
± 1.6uS
1.25Mbps
625Kbps
312.5Kbps
156.25Kbps
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Option Feature for Jitter Filtering
When any RX ports receive the bigger jitter than its allowance, the TMC2005 may fail to receive the data
correctly and the network may be down.. However the below method to escape is effective for the case that a
momentary big jitter occurs under a special condition like an optical transceiver.
1) Big jitter (BJ) mode
The reference phase of the internal DPLL is changed from the first pulse to the second pulse by setting “0” to the big
jitter mode pins (nBJX). This setup is effective for the case that a big jitter occurs when rising up from DC state as
same as when using an optical transceiver with ATC function (refer to complement).
Note: The delay time of the TMC2005 becomes 400nS (at 2.5Mbps) longer than the normal mode. The delay time
limits the maximum cable length and maximum node number.
[Complement] The big jitter may occur in the case of using an optical transceiver, especially an optical receiver that
has an ATC circuit that controls threshold level in proportion to received light strength. The first pulse especially after
long time idle has the big jitter but the second pulse is stabilized.
2) Changing polar of RX port
In order to filter the jitter of edge in one side, it is effective to set reverse to pin SA, SB, SE to change the polarity of
RX port.
Note: Changing the polarity of RX port makes the delay time of the TMC2005 circuit a half bit (200nS) longer than
original 2.5Mbps, and the delay time affects the maximum cable length and maximum node number.
Option Feature for Noise Cut mode
The Noise cut mode is enabled by setting pin nMBx sets 0. The noise cut mode is a function to remove the ringing
noise and the reflection noise generated on the leading edge side of the input pulse to receive data input RXINx. The
position and the width of the “dead band” are shown in the figure below.
- Dead band at Normal mode (nMBx=1)
- Dead band at Noise cut mode (nMBx=0)
Period of data rate (Tdr)
Tdr/8 = 1 clock
Period of data rate (Tdr)
Tdr/8 = 1 clock
RXIN
RXIN
(Active High)
(Active High)
Ideal waveform
Ideal waveform
dead band
dead band: Noise cut band
RXIN edge reference position:
RXIN edge reference position:
Generated by adjacent phase of SYNC character (1,1,0)
Generated by adjacent phase of SYNC character (1,1,0)
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APPLICATION NOTES
Example 1: A five ports HUB with HYC4000s in backplane mode.
FIGURE 1 - APPLICATION EXAMPLE
Only the TMC2005 and five transceivers are indicated in the above figure. Connect the other pins adequately.
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Example 2: A five ports HUB with HYC9088s and a optical transceiver(TODX270A) links the two physical layers;
dipulse and fiber optics.
FIGURE 2 - APPLICATION EXAMPLE 2
Only the TMC2005 and five transceivers are indicated in the above figure. Connect the other pins adequately.
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Example 3: A five ports HUB with two optical transceivers, two HYC9088s, and a HYC4000 links three physical
layers; fiber optics, dipulse, and AC-485.
FIGURE 3 - APPLICATION EXAMPLE 3
Only the TMC2005 and five transceivers are indicated in the figure above. Connect the other pins properly.
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Example 4: An on-board type HUB with a COM20020 and four optical transceivers in backplane mode.
FIGURE 4 - APPLICATION EXAMPLE 4
Only the TMC2005 and four transceivers with the COM20020 are indicated in the above figure. Connect the other
pins adequately.
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Example 5: An on-board type HUB with a COM20020 and four RS485 transceivers.
FIGURE 5 - APPLICATION EXAMPLE 5
Only the TMC2005 and four transceivers with the COM20020 are indicated in the above figure. Connect the other
pins adequately.
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Example 6: An on-board type HUB with a COM20020, two HYC4000s, and two HYC9088s links two different physical
layers; dipulse and AC-485.
FIGURE 6 - APPLICATION EXAMPLE 6
Only the TMC2005 and four transceivers with the COM20020 are indicated in the above figure. Connect the other
pins adequately.
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Example 7: An eight ports HUB are composed by using two TMC2005. Two TMC2005 connects the EXTTX signal
with the EXTRX signal.
FIGURE 7 - APPLICATION EXAMPLE 7
Only the two TMC2005s are indicated in the above figure. Connect the other pins adequately.
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Example 8: A sixteen ports HUB are composed by using four TMC2005. The EXT port between TMC2005 is made an
open-drain mode and it connects it (left example). Or put standard logic IC such as 74LS20 outside (right example).
This connected method is excellent in noised respect compared with connected method of open-drain mode.
Data rate: 5Mbps and below
Data rate: 10Mbps and below
or
FIGURE 8 - APPLICATION EXAMPLE 8
Only the four TMC2005s are indicated in the above figure. Connect the other pins adequately.
Note: Use the wiring pattern length that connects between four TMC2005s by five inches or less in open-drain mode.
Four TMC2005s is maximum in open-drain mode.
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PORT GROUP
The five ports can be divided into three groups (group A: two ports, group B: two ports, extension port: one port) and
each group can select TX/RX polar, noise cut mode, and big jitter mode respectively. Select pins for each group are
as follows:
FUNCTION
RECEIVE
TRANSMIT
RX POLARITY
TX POLARITY
TX CONTROL
NOISE CUT
BIG JITTER
EXTENSION
GROUP A
RXINA0, 1
TXENA0, 1
SA
GROUP B
RXINB0, 1
TXENB0, 1
SB
EXTENSION
EXTRX
EXTTX
SE
LE
ME
nMBE
nBJE
nEXTOD
LA
MA
nMBA
nBJA
LB
MB
nMBB
nBJB
Various Setup
Example For Operation Mode Setup To Each Port
SA, SB, SE LA, LB, LE
MA, MB, ME
RX POLAR
Active Low
Active High
Active High
Active Low
TX POLAR
Active Low
Active High
Active Low
Active High
TRANSCEIVER
HYC2485S/HYC2488S
Optical Transceiver
HYC9088/HYC9068
RS485 Transceiver
1
0
0
1
0
1
0
1
1
0
1
1
Note for Unused port
Unused ports can be left open because RX port (RX input), RX polar (S input), TX polar (L input), TX control (M input)
pins have internal pull-up resistors. Because of internal pull-up resistors, select pins for noise cut (nMB input), big
jitter (nBJ input) can be left open when used for setting “OFF”.
Example for Power-On Reset Circuit
FIGURE 9 - POWER-ON RESET
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CONNECTING THE TMC2005 WITH INTERNAL PLL
When using the TMC2005 at data rate 2.5Mbps or lower, it is not necessary to use internal PLL. Leave the loop filter
pins (RO, LP) open and connect AGS to the Ground. The pins for the analog power supply (AVSS, AVDD) may
connect to digital power supply. When using the TMC2005 at data rate 5Mbps or higher, the internal PLL has to be
used as a clock multiplier. PCB layout must follow the guidelines at Figure 10, refer to Notes 1 through 5.
FIGURE 10 - PLL PATTERN LAYOUT
Note 1: Prohibit the patterns for LP and RO from occupying the area of digital power supply. Use the area of analog
power supply between VAA and AVSS.
Note 2: Encircle the pattern between LP, RO and AGS with wide pattern of analog ground.
Note 3: Connect the analog power supply “VAA” with 0.1 uF condenser (a) with in 1/8 inch (~ 3.2mm) from VAA pin.
Note 4: In order to filter the jitter of low frequency, connect a 10 uF condenser (b) in parallel with the condenser (a).
Note 5: Place 0.1 uF bypass condenser (c) within ¼ inch (~ 6.4mm) from VDD3 and VSS3. Connect the ground side
of a condenser (c) at the place (*) where AVSS returns to GND plane.
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Method To Connect A Crystal Clock
Connect with external parts as follows:
FIGURE 11 - CONNECTING THE CRYSTAL CLOCK
Note 1: When designing a printed circuit board, keep the patterns as short as possible and don’t cross with other
patterns.
Note 2: When using an external clock like an oscillator module, connect it to XTLI pin and leave XTLO pin open.
When designing a printed circuit board, wire between XTLI pin and oscillator should be short as possible.
nPLLTST pin
nPLLTST must be connect toVDD. The rest of input pins have pull-up resistors built in, but nPLLTST pin does not
have the pull-up resistor. Clock signal cannot ditributed into the TMC2005 if nPLLTST pin is connected GND or is left
open.
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CASCADING CONNECTION
HUBs can be connected in cascade by using the ports as Fig. 12. In the case of cascade connection, it is necessary
to consider how many HUBs can exist in serial. The maximum delay between input port and output port is 650ns
@2.5Mbps at the TMC2005. It is equivalent to the propagation delay when a cable length is 135m. For example, if
every cable length is 10m in Figure 12, the longest distance is physically 50m but it is electrically 590m because of
multiplying 10m by 5 and 135m by 4, and the total propagation delay becomes 2.8uS. For analyzing the network
timing, consider the delay caused by HUBs. In the ARCNET protocol, it is defined that the longest distance between
nodes is the maximum 6.4Km. For example, if 20 TMC2005s exist between nodes in the longest distance, the actual
cable length is 3.7Km because of deducting 135m by 20 in converting to cable length from 6.4Km.
TMC2005
TMC2005
TMC2005
TMC2005
NODE
NODE
FIGURE 12 - CASCADE CONNECTION OF 4 HUBS
Two examples of eight ports HUBs using two TMC2005s are shown in Fig. 13 and 14. If connecting as in Fig. 13,
eight TMC2005s exist between the nodes at both far ends. On the other hand, when assigning two ports for
cascading connection to the same TMC2005, the number of TMC2005 in serial connection can be down to the
number of HUBs plus two, which can reduce the propagation delay.
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HUB 1
HUB2
HUB 3
HUB4
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
NODE
NODE
FIGURE 13 - CASCADE CONNECTION OF 8 PORT HUB
HUB 1
HUB2
HUB 3
TMC2005 TMC2005
HUB4
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
NODE
NODE
FIGURE 14 - CASCADE CONNECTION OF 8 PORT HUB
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Fig.15 shows a 16 ports HUB with four TMC2005s connected by open–drain ports. When assigning two ports for
cascade connection to the same TMC2005, the number of TMC2005s for serial connection can be reduced to the
number of HUBs plus two.
HUB2
HUB 3
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
HUB 1
HUB 4
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
TMC2005
NODE
NODE
FIGURE 15 - CASCADE CONNECTION OF 16 PORT HUB
Note:
When connecting TMC2005 by open-drain output on a board, connecting TMC2005s must be four or less,
and the data rate must be 5Mbps or slower. The pattern of open-drain output has to be as short as possible
(less than 15cm).
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Ring Network With the TMC2005
The reliability of the network can be improved by connecting every node in a ring, because the communication is
maintained through the reverse route even if the cable is cut at a point. However ARCNET controller alone can not
support ring, because ARCNET is a half-duplex communication system. Using HUBs makes possible for ARCNET to
built a ring network as in Fig.16. This configuration is available only for using fiber optics. (Refer to the application note
for details.)
Optical Transceiver
COM20020
TMC2005
A
B
Optical Fiber
COM20020
TMC2005
TMC2005
COM20020
nRST
TXEN
nRESET
CK
CT
TMC2005
TXEN of any port
COM20020
FIGURE 16 - RING CONFIGURATION
Note 1: Noise may cause an endless loop in a ring system, and the network may hang up. Therefore take care of
designing the patterns between TMC2005 and transceiver or cabling of system.
Example for system hang-up
-
-
-
-
A noise occurs only at “A” point in Figure 16.
The noise propagates clockwise on the network.
TMC2005 detects the noise that came back through the ring.
The noise causes an endless loop in the ring.
Example for no hang-up
-
-
-
Any noise occurs at “A” and “B” points in Figure 16 at the same time.
The noise propagates to both directions in the network.
An endless loop doesn’t occur because TMC2005s in the middle absorb the noise from both sides.
Note 2: Place a watch dog timer on one of the TMC2005 in at least one ring. To protect from hang-up the detecting
time of the watch dog timer should be set to longer than 2.7 mS (@ 2.5Mbps) that is the burst time in the
ARCNET protocol.
Note 3: Consider that a total of each segment delay time (cable delay, TMC2005 delay, driver delay and receiver
delay) between HUBs in a network is less than 5.6uS (@ 2.5Mbps). The maxmimum distance between
HUBs is approximiately 1000m (@ 2.5Mbps).
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OPERATIONAL DESCRIPTION
MAXIMUM GUARANTEED RATINGS*
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this
specification is not implied.
(Note) When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or
“glitches” on their output when the AC power is switch on or off. In addition, voltage transients on the AC power line
may appear on the DC output. If this possibility exists it is suggested that a clamp circuit be used.
Vss = 0V
ITEM
SYMBOL
VDD
VIN
VOUT
Tstg
RATING
-0.3 +7.0
-0.3 VDD +0.3
-0.3 VDD +0.3
-40 +125
UNIT
V
V
V
°C
POWER SUPPLY VOLTAGE
INPUT VOLTAGE
OUTPUT VOLTAGE
AMBIENT TEMPERATURE
STANDARD OPERATING CONDITION
Vss = 0V
ITEM
SYMBOL
VDD
RATING
4.5 – 5.5
0 - +85
UNIT
V
°C
POWER SUPPLY VOLTAGE
AMBIENT TEMPERATURE
Ta
DC CHARACTERISTIC - INPUT PIN
SYMBOL
ITEM
CONDITION
XTLI, nPLLTST
Others
MIN
3.5
2.2
MAX
UNIT
V
V
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
With pull-up
Output Leak Current
Dissipation Current
0.8
10
10
-10
10
100
V
VIL
IIH
IIL
IIL
IOZ
IDD
VIN=VDD
VIN=VSS
Vin=VSS
-10
-10
-200
-10
uA
uA
uA
uA
mA
VOUT=VDD or VSS
Operating
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DC CHARACTERISTIC - OUTPUT PIN
SYMBOL
ITEM
CONDITION
MIN
MAX
UNIT
PIN
VOH
High Level Output Voltage
IOH=-4mA
2.4
V
1,9,46,51,
55,61
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
IOH=-8mA
IOL=4mA
2.4
V
V
11,45,47
1,9,46,51,
55,61
0.4
0.4
VOL
Low Level Output Voltage
IOL=8mA
V
11,45,47
AC CHARACTERISTIC - CLOCK and RESET
ITEM
Generating Static Time
Clock Cycle
Clock Frequency Deflection
Clock Pulse Width
Reset Pulse Width
SYMBOL
MIN
TYP
MAX
4
UNIT
mS
nS
ppm
nS
CONDITION
tx
tCYC
tCDF
tCW
50
Note 1
Note 1
Note 1
Note 1
-100
20
200
100
ttRSW
nS
Note 1: Use only F=20MHz
Note 2: VDD=4.5V
XTLI
t
t
t
CYC
CW
CW
nRST
t
RSW
FIGURE 17 - CLOCK AND RESET
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AC CHARACTERISTIC – Rx waveforms and Tx waveforms
t2
t1
RXINx (S=1)
(Received port)
t3
t4
t5
TXENy (M=1, L=0)
* 4 ports except received port
t6
t8
t10
t15
t7
nP1BAK
/TXENy(M=0,L=0)
* 4 ports except received port
t9
t13
t11
t12
nPULSE1
nPULSE2
t14
t17
t16
t18
t19
FIGURE 18 - RX WAVEFORMS AND TX WAVEFORMS
ITEMS
RXIN Low Pulse Width
RXIN High Pulse Width
MARK
MIN
15
TYP
MAX
UNIT
nS
REMARK
t1
t2
15
nS
Tdr
RXIN Period
(Value at 2.5Mbps)
t3
t4
nS
nS
nS
nS
nS
nS
nS
nS
(400)
2/8Tdr
(100)
3/8Tdr+50
(200)
Note1
(Value at 2.5Mbps)
RXIN First Active Edge to TXEN Active
RXIN Last Active Edge to TXEN Inactive
111/8Tdr
(5,550)
9/8Tdr
(450)
112/8Tdr+50
(5,650)
Note1
(Value at 2.5Mbps)
t5
10/8Tdr+50
(550)
RXIN First Active Edge to
nP1BAK/TXEN First Active Edge
Note2, Note3
(Value at 2.5Mbps)
t6
1/2Tdr
(200)
1/2Tdr
(200)
Tdr
Note2
(Value at 2.5Mbps)
nP1BAK/TXEN Low Pulse Width
nP1BAK/TXEN High Pulse Width
nP1BAK/TXEN Period
t7
Note2
(Value at 2.5Mbps)
t8
Note2
(Value at 2.5Mbps)
t9
(400)
RXIN Active Edge to
nP1BAK/TXEN Active Edge
(Except First Edge of RXIN)
5/8Tdr
(250)
9/8Tdr+50 14/8Tdr+50
(500) (750)
Note2, Note3
(Value at 2.5Mbps)
t10
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ITEMS
MARK
MIN
9/8Tdr
(450)
TYP
MAX
10/8Tdr+50
(550)
UNIT
REMARK
RXIN First Active Edge
to nPULSE1 First Active Edge
Note3
t11
nS
(Value at 2.5Mbps)
1/4Tdr
(100)
3/4Tdr
(300)
Tdr
nPULSE1 Low Pulse Width
nPULSE1 High Pulse Width
nPULSE1 Period
(Value at 2.5Mbps)
t12
t13
t14
t15
nS
nS
nS
nS
(Value at 2.5Mbps)
(Value at 2.5Mbps)
(400)
RXIN Active Edge to
nPULSE1 Active Edge
(Except First Edge of RXIN)
5/8Tdr
(250)
9/8Tdr+50 14/8Tdr+50
Note3
(Value at 2.5Mbps)
(500)
(750)
nPULSE1 to nPULSE2 Overlap
nPULSE2 Low Pulse Width
nPULSE2 High Pulse Width
nPULSE2 Period
t16
t17
t18
t19
-10
0
+10
nS
nS
nS
nS
1/4Tdr
(100)
3/4Tdr
(300)
Tdr
(Value at 2.5Mbps)
(Value at 2.5Mbps)
(Value at 2.5Mbps)
(400)
Tdr: Period of data rate, ex) Tdr=400nS at 2.5Mbps
Note1: Applied to TXENx which is set to Mx=1. (Tx Control mode)
Note2: Applied to TXENx which is set to Mx=0. (Pulse output mode)
Note3: Extra one “Tdr” time to be added at RXINx is set to nBJx=0. (Big Jitter mode)
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TMC2005-JT 64 PIN TQFP PACKAGE OUTLINE
D
D1
Ze
E1 E
64
1
Zd
SYMBOL
MIN (mm)
TYP (mm)
12.0
MAX (mm)
12.2
D
11.8
9.9
D1
E
10.0
10.1
11.8
9.9
12.0
12.2
E1
Ze
Zd
10.0
10.1
1.25 typ
1.25 typ
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A2
A
A1
e
b
bbb M
aaa
SYMBOL
MIN (mm)
TYP (mm)
MAX (mm)
1.6
A
A1
0.95
1.35
0.17
0.1
1.4
0.15
A2
B
1.45
0.27
0.22
E
0.5 BSC
0.08
aaa
bbb
0.08
c
L
SYMBOL
MIN (mm)
0.9
TYP (mm)
0.145
MAX (mm)
0.2
c
L
0.45
0.6
0.75
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