SMSC Switch SCH5617C User Manual

SCH5617C  
Desktop System  
Controller Hub with  
Advanced, 8051µC-Based  
Auto Fan Control  
Data Brief  
PRODUCT FEATURES  
Acoustic enhancement mode  
ProcHot pins modulate Tmin  
Fan PWM duty cycle is a function in linear mode of  
multiple temperatures and ProcHot signals  
PWM Ramp Rate Closed Loop Control  
ACPI 2.0 Compliant  
High Performance 8051  
2.5X average instruction execution speed improvement  
over the entire instruction set; i.e., typical 4-clock  
instruction cycle in high-performance 8051 vs. 12-clock  
instruction cycle in standard 8051.  
Internal Ring Oscillator for VTR Powered Logic  
Low Battery Warning  
Faster clock speed: 32 MHz vs. 16 MHz in standard  
8051.  
LED Control  
Dual Data Pointers  
More Interrupts: Power-Fail, External Interrupt 2,  
External Interrupt 3, etc.  
SMBus Isolation Logic  
Programmable Wake-up Event Interface  
PC2001 Compliant  
A set of External Memory/Mapped Control Registers  
provides the 80C51 core with the ability to directly  
control many functional blocks of the SCH5617C.  
384 Bytes of RAM as part of the 8051 core  
4k Bytes Data RAM (869 bytes may be used to patch  
ROM code)  
General Purpose Input/Output Pins (30 Host  
controlled, 16 8051 controlled)  
21 Dedicated Scratchpad registers  
ISA Plug-and-Play Compatible Register Set  
System Management Interrupt  
GLUE Logic  
Twelve Interrupt Sources  
Watch Dog Timer (WDT)  
PECI Interface  
IDE Reset/Buffered PCI Reset Outputs  
Power OK Signal Generation  
Power Sequencing  
Power Supply Turn On Circuitry  
Resume Reset Signal Generation  
Hard Drive Front Panel LED  
Supports PECI REQUEST# and PECI AVAILABLE  
signalling  
Temperature Monitor  
Monitoring of up to Two Remote Thermal Diodes  
Supports temperature readings from -63 degrees to  
+192 degrees  
2.88MB Super I/O Floppy Disk Controller  
Supports monitoring of discrete diodes (3904 type  
diodes)  
Licensed CMOS 765B Floppy Disk Controller  
Software and Register Compatible with SMSC's  
Proprietary 82077AA Compatible Core  
Supports Two Floppy Drives  
Configurable Open Drain/Push-Pull Output Drivers  
Supports Vertical Recording Format  
16-Byte Data FIFO  
Supports monitoring substrate diodes (45nm &  
65nm processor diodes)  
1/8th degree temperature resolution  
Internal Ambient Temperature Measurement  
Limit Comparison of all Monitored Values  
PROCHOT_IN# Pin  
100% IBM® Compatibility  
Mapped into Temperature monitoring interrupt  
Detects All Overrun and Underrun Conditions  
Sophisticated Power Control Circuitry (PCC) Including  
Multiple Powerdown Modes for Reduced Power  
Consumption  
generation logic  
May be used to adjust fan control limits  
May be configured to force fans on full  
PROCHOT_OUT Pin  
DMA Enable Logic  
Data Rate and Drive Control Registers  
480 Addresses, Up to Eight IRQs, and Four DMA  
Options  
Auto-Fan Control with ProcHot Features  
PWM (Pulse width Modulation) Outputs (3)  
Legacy PWM control dc fan outputs  
Enhanced Digital Data Separator  
High Frequency PWM Options (15kHz up to 30kHz)  
2 second delayed start-up for PWM outputs  
Fan Tachometer or Lock Rotor Inputs (3)  
Programmable linear automatic fan control based on  
temperature  
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps  
Data Rates  
Programmable Pre compensation Modes  
SMSC SCH5617C  
PRODUCT PREVIEW  
Revision 0.7 (12-09-08)  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Desktop System Controller Hub with Advanced, 8051µC-Based Auto Fan Control  
General Description  
The SCH5617C is a 3.3V PC 2001 compliant Super I/O controller with an LPC interface. All legacy  
drivers used for Super I/O components are supported making this interface transparent to the  
supporting software. The LPC bus also supports power management, such as wake-up and sleep  
modes.  
The SCH5617C provides temperature monitoring with auto fan control. The temperature monitor is  
capable of monitoring two external diodes, one internal ambient temperature sensor or retrieving  
temperatures from external processors that implement the PECI Interface. This includes support for  
the PECI REQUEST# and PECI AVAILABLE signals that are used to assure correct operation of PECI  
when processors enter the C3/C4 sleep states. This device offers programmable automatic fan control  
support based on one or more of these measured temperatures. There are three pulse width  
modulation (PWM) outputs with high frequency support as well as three fan tachometer inputs. In  
addition, there is support for a PROCHOT_IN# pin that may be used to generate an interrupt, adjust  
the programmed temperature limits in the auto fan control logic, or force the PWM outputs on full.  
There is also a separate PROCHOT_OUT output pin.  
The GLUE Logic includes various power management logic including generation of RSMRST# and  
Power OK signal generation. There are also four LEDs to indicate power status and hard drive activity.  
Also included is SMBus Isolation logic, which can be used to isolate SMBus signals during power down  
modes.  
The part provides 45 General Purpose I/O control pins, which offer flexibility to the system designer.  
There are 21 Scratchpad read/write runtime registers for custom use.  
The SCH5617C incorporates the following Super I/O components: a parallel port that is compatible  
with IBM PC/AT architecture, as well as the IEEE 1284 EPP and ECP; two serial ports that are  
16C550A UART compatible; a keyboard/mouse controller that uses an 8042 micro controller; two  
floppy controllers, which use SMSC's true CMOS 765B core; one infrared port that is IrDA 1.0  
compliant. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT  
architectures and is software and register compatible with SMSC's proprietary 82077AA core. The part  
also provides a low battery warning circuit.  
The SCH5617C is ACPI 1.0b/2.0 compatible supports multiple low power-down modes. It incorporates  
sophisticated power control circuitry (PCC), which includes keyboard and mouse wake-up events.  
The SCH5617C supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address,  
DMA Channel and hardware IRQ of each logical device in the SCH5617C may be reprogrammed  
through the internal configuration registers. There are up to 480 (960 for Standard Mode Parallel Port)  
I/O address location options, a Serialized IRQ interface, and four DMA channels.  
SMSC SCH5617C  
3
Revision 0.7 (12-09-08)  
PRODUCT PREVIEW  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Desktop System Controller Hub with Advanced, 8051µC-Based Auto Fan Control  
Block Diagram  
IDE_RSTDRV#*, PCI_RST_SYS#*  
PCI_RST_SLOTS#*, PS_ON#*  
PWR_GOOD_3V*, PWRGD_PS, RSMRST#*  
SECONDARY_HD#*  
PRIMARY_HD#*  
SCSI#*  
HD_LED#*  
LED2*  
LED3*  
LED1*  
LEDs  
Glue Logic  
14.318 MHz  
CLOCK  
GEN  
PD[7:0]  
SERIAL  
IRQ  
SER_IRQ  
PCI_CLK  
BUSY,SLCT,PE  
ERROR#, ACK#  
STROBE#, INIT#  
SLCTIN#  
Multi-Mode  
Parallel Port  
with ChiProtectTM  
Internal Bus  
(Data, Address, and Control lines)  
LAD[3:0]  
LFRAME#  
LDRQ#  
LPC  
Bus Interface  
ALF#  
PCI_RESET#  
LPCPD#  
TXD1*,RXD1*  
High-Speed  
16550A  
UART  
CTS1#*, RTS1#*  
DSR1#*, DTR1#*  
DCD1#*, RI1#*  
IO_PME#*  
IO_SMI#*  
SCH5617C  
(128 QFP)  
Power Mgmt  
PORT 1  
GP10*, GP11*, GP15*, GP21*,  
GP22*, GP23*, GP25*, GP26*,  
GP31*, GP33*, GP35*, GP36*,  
GP37*, GP40*, GP41*, GP42*,  
GP52*, GP53*, GP55*, GP57*,  
GO60*, GP61*, GP75*, GP76*,  
GP77*, GP80*, GP81*, GP82,  
GP83*, GP84*, GP8051_[12:1]*,  
GP8051_[17:14]*  
General  
Purpose  
I/O  
TXD2*,RXD2*  
High-Speed  
16550A  
UART  
CTS2#*, RTS2#*  
DSR2#*, DTR2#*  
DCD2#*, RI2#*  
8051  
ROM  
PORT 2  
TACH1  
TACH2  
TACH3  
Auto  
Fan  
WDATA  
HVSS  
Remote1+  
Remote1-  
Remote2+  
Remote2-  
HVTR  
PWM1  
PWM2  
PWM3  
Control  
WCLOCK  
SCLK*, SDAT*  
SCLK_1*, SDAT_1*  
SMBus Isolation  
Circuits  
Analog  
Interface  
DIGITAL DATA  
SMC PROPRIETARY  
82077 COMPATIBLE  
VERTICAL  
FLOPPYDISK  
CONTROLLER CORE  
SEPARATOR  
WITH WRITE  
PRECOM-  
KCLK, MCLK  
PENSATION  
Analog  
Block  
Keyboard/Mouse  
8042  
controller  
KDAT, MDAT,  
KBDRST#, A20M  
P12*,P16*,P17*  
PROCHOT_IN#  
PROCHOT_OUT  
RCLOCK  
RDATA  
PECI VREF  
PECI IO  
PECI AVAILABLE  
PECI REQUEST#  
PECI  
Interface  
RDATA#,  
WDATA#  
Note 1: This diagram does not show power and ground  
connections.  
MRT0#, MRT1#*, TRK0#,  
INDEX#,WRTPRT#,WGATE#,  
HDSEL#,DRVDEN0*,  
Note 2: Functions with "*" are located on multifunctional  
pins. This diagram is designed to show the various  
functions available on the chip (not pin layout).  
DIR#, STEP#, DSKCHG#,DS0#, DS1#*  
Figure 1 SCH5617C Block Diagram  
Revision 0.7 (12-09-08)  
4
SMSC SCH5617C  
PRODUCT PREVIEW  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Package Outline  
Figure 2 128-Pin QFP Package Outline (3.9mm footprint)  
Download from Www.Somanuals.com. All Manuals Search And Download.  

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