SMSC Switch LAN9512 User Manual

LAN9512  
USB Hub with Integrated  
10/100 Ethernet Controller  
Datasheet  
PRODUCT FEATURES  
High-Performance 10/100 Ethernet Controller  
Highlights  
Fully compliant with IEEE802.3/802.3u  
Integrated Ethernet MAC and PHY  
10BASE-T and 100BASE-TX support  
Full- and half-duplex support with flow control  
Preamble generation and removal  
Automatic 32-bit CRC generation and checking  
Automatic payload padding and pad removal  
Loop-back modes  
Two downstream ports, one upstream port  
Two integrated downstream USB 2.0 PHYs  
One integrated upstream USB 2.0 PHY  
Integrated 10/100 Ethernet MAC with full-duplex  
support  
Integrated 10/100 Ethernet PHY with HP Auto-MDIX  
Implements Reduced Power Operating Modes  
Minimized BOM Cost  
TCP/UDP checksum offload support  
Flexible address filtering modes  
One 48-bit perfect address  
64 hash-filtered multicast addresses  
Pass all multicast  
Promiscuous mode  
Inverse filtering  
Single 25 MHz crystal (Eliminates cost of separate  
crystals for USB and Ethernet)  
Built-in Power-On-Reset (POR) circuit (Eliminates  
requirement for external passive or active reset)  
Pass all incoming with status report  
Target Applications  
Wakeup packet support  
Integrated Ethernet PHY  
Desktop PCs  
Auto-negotiation  
Automatic polarity detection and correction  
HP Auto-MDIX  
Notebook PCs  
Printers  
Energy Detect  
Game Consoles  
Embedded Systems  
Docking Stations  
Power and I/Os  
Three PHY LEDs  
Eight GPIOs  
Supports bus-powered and self-powered operation  
Internal 1.8v core supply regulator  
External 3.3v I/O supply  
Key Benefits  
USB Hub  
Miscellaneous features  
Fully compliant with Universal Serial Bus Specification  
Revision 2.0  
HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps)  
compatible  
Two downstream ports, one upstream port  
Port mapping and disable support  
Port Swap: Programmable USB diff-pair pin location  
PHY Boost: Programmable USB signal drive strength  
Select presence of a permanently hardwired USB  
peripheral device on a port by port basis  
Advanced power saving features  
Optional EEPROM  
Optional 24MHz reference clock output for partner hub  
IEEE 1149.1 (JTAG) Boundary Scan  
Software  
Windows 2000/XP/Vista Driver  
Linux Driver  
Win CE Driver  
MAC OS Driver  
EEPROM Utility  
Packaging  
Downstream PHY goes into low power mode when port  
power to the port is disabled  
64-pin QFN, lead-free RoHS compliant  
Environmental  
Full Power Management with individual or ganged  
power control of each downstream port.  
Integrated USB termination Pull-up/Pull-down resistors  
Internal short circuit protection of USB differential signal  
pins  
Commercial Temperature Range (0°C to +70°C)  
±8kV HBM without External Protection Devices  
±8kV contact mode (IEC61000-4-2)  
±15kV air-gap discharge mode (IEC61000-4-2)  
SMSC LAN9512  
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USB Hub with Integrated 10/100 Ethernet Controller  
Datasheet  
Table of Contents  
SMSC LAN9512  
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USB Hub with Integrated 10/100 Ethernet Controller  
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List of Tables  
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USB Hub with Integrated 10/100 Ethernet Controller  
Datasheet  
Chapter 1 Introduction  
1.1  
Block Diagram  
LAN9512  
TAP  
EEPROM  
EEPROM  
JTAG  
Controller  
Controller  
10/100  
Ethernet  
Controller  
USB 2.0  
Hub  
USB  
Upstream  
USB PHY  
Ethernet  
PHY  
Ethernet  
DP/DM  
Downstream  
Downstream  
USB PHY  
USB PHY  
USB  
USB  
DP/DM  
DP/DM  
Figure 1.1 Internal Block Diagram  
1.1.1  
Overview  
The LAN9512 is a high performance Hi-Speed USB 2.0 hub with a 10/100 Ethernet controller. With  
applications ranging from embedded systems, desktop PCs, notebook PCs, printers, game consoles,  
and docking stations, the LAN9512 is targeted as a high performance, low cost USB/Ethernet and  
USB/USB connectivity solution.  
The LAN9512 contains an integrated USB 2.0 hub, two integrated downstream USB 2.0 PHYs, an  
integrated upstream USB 2.0 PHY, a 10/100 Ethernet PHY, a 10/100 Ethernet Controller, a TAP  
controller, and a EEPROM controller. A block diagram of the LAN9512 is provided in Figure 1.1.  
The LAN9512 hub provides over 30 programmable features, including:  
PortMap (also referred to as port remap) which provides flexible port mapping and disabling  
sequences. The downstream ports of the LAN9512 hub can be reordered or disabled in any sequence  
to support multiple platform designs’ with minimum effort. For any port that is disabled, the LAN9512  
automatically reorders the remaining ports to match the USB host controller’s port numbering scheme.  
PortSwap which adds per-port programmability to USB differential-pair pin locations. PortSwap allows  
direct alignment of USB signals (D+/D-) to connectors avoiding uneven trace length or crossing of the  
USB differential signals on the PCB.  
PHYBoost which enables four programmable levels of USB signal drive strength in USB port  
transceivers. PHYBoost attempts to restore USB signal integrity that has been compromised by system  
level variables such as poor PCB layout, long cables, etc..  
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USB Hub with Integrated 10/100 Ethernet Controller  
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1.1.2  
USB Hub  
The integrated USB hub is fully compliant with the USB 2.0 Specification and will attach to a USB host  
as a Full-Speed Hub or as a Full-/High-Speed Hub. The hub supports Low-Speed, Full-Speed, and  
High-Speed (if operating as a High-Speed hub) downstream devices on all of the enabled downstream  
ports.  
A dedicated Transaction Translator (TT) is available for each downstream facing port. This architecture  
ensures maximum USB throughput for each connected device when operating with mixed-speed  
peripherals.  
The hub works with an external USB power distributed switch device to control V  
downstream ports, and to limit current and sense over-current conditions.  
switching to  
BUS  
All required resistors on the USB ports are integrated into the hub. This includes all series termination  
resistors on D+ and D- pins and all required pull-down and pull-up resistors on D+ and D- pins. The  
over-current sense inputs for the downstream facing ports have internal pull-up resistors.  
Two external ports are available for general USB device connectivity.  
1.1.3  
Ethernet Controller  
The 10/100 Ethernet controller provides an integrated Ethernet MAC and PHY which are fully IEEE  
802.3 10BASE-T and 802.3u 100BASE-TX compliant. The 10/100 Ethernet controller also supports  
numerous power management wakeup features, including “Magic Packet”, “Wake on LAN” and “Link  
Status Change”. These wakeup events can be programmed to initiate a USB remote wakeup.  
The 10/100 Ethernet PHY integrates an IEEE 802.3 physical layer for twisted pair Ethernet  
applications. The PHY block includes support for auto-negotiation, full or half-duplex configuration,  
auto-polarity correction and Auto-MDIX. Minimal external components are required for the utilization of  
the integrated PHY.  
The Ethernet controller implements four USB endpoints: Control, Interrupt, Bulk-in, and Bulk-out. The  
Bulk-in and Bulk-out Endpoints allow for Ethernet reception and transmission respectively.  
Implementation of vendor-specific commands allows for efficient statistics gathering and access to the  
Ethernet controller’s system control and status registers.  
1.1.4  
1.1.5  
EEPROM Controller  
The LAN9512 contains an EEPROM controller for connection to an external EEPROM. This allows for  
the automatic loading of static configuration data upon power-on reset, pin reset, or software reset.  
The EEPROM can be configured to load USB descriptors, USB device configuration, and the MAC  
address.  
Peripherals  
The LAN9512 also contains a TAP controller, and provides three PHY LED indicators, as well as eight  
general purpose I/O pins. All GPIOs can serve as remote wakeup events when LAN9512 is in a  
suspended state.  
The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.  
1.1.6  
Power Management  
The LAN9512 features three variations of USB suspend: SUSPEND0, SUSPEND1, and SUSPEND2.  
These modes allow the application to select the ideal balance of remote wakeup functionality and  
power consumption.  
SUSPEND0: Supports GPIO, “Wake On LAN”, and “Magic Packet” remote wakeup events. This  
suspend state reduces power by stopping the clocks of the MAC and other internal modules.  
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SUSPEND1: Supports GPIO and “Link Status Change” for remote wakeup events. This suspend  
state consumes less power than SUSPEND0.  
SUSPEND2: Supports only GPIO assertion for a remote wakeup event. This is the default suspend  
mode for the LAN9512.  
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Chapter 2 Pin Description and Configuration  
49  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
VDD33A  
TCK  
50  
EXRES  
TDO  
SMSC  
LAN9512  
51  
VDD33A  
TDI  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
64 PIN QFN  
RXP  
RXN  
TMS  
(TOP VIEW)  
nTRST  
VDD33A  
TXP  
VDD33IO  
EEDI  
EEDO  
TXN  
VDD33A  
USBDM0  
USBDP0  
XO  
VSS  
EECS  
EECLK  
nSPD_LED/GPIO2  
nLNKA_LED/GPIO1  
nFDX_LED/GPIO0  
VDD33IO  
NC  
XI  
VDD18USBPLL  
USBRBIAS  
VDD33A  
NC  
NOTE: When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa  
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground  
Figure 2.1 LAN9512 64-QFN Pin Assignments (TOP VIEW)  
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Table 2.1 EEPROM Pins  
NUM  
PINS  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
EEPROM Data  
In  
EEDI  
IS  
(PD)  
This pin is driven by the EEDO output of the  
external EEPROM.  
1
1
1
1
EEPROM Data  
Out  
EEDO  
EECS  
O8  
O8  
O8  
This pin drives the EEDI input of the external  
EEPROM.  
EEPROM Chip  
Select  
This pin drives the chip select output of the external  
EEPROM.  
EEPROM Clock  
EECLK  
This pin drives the EEPROM clock of the external  
EEPROM.  
Table 2.2 JTAG Pins  
NUM  
PINS  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
JTAG Test Port  
Reset  
nTRST  
IS  
This active low pin functions as the JTAG test port  
reset input.  
1
Note:  
This pin should be tied high if it is not  
used.  
JTAG Test  
Mode Select  
TMS  
TDI  
IS  
IS  
This pin functions as the JTAG test mode select.  
This pin functions as the JTAG data input.  
This pin functions as the JTAG data output.  
1
1
1
JTAG Test Data  
Input  
JTAG Test Data  
Out  
TDO  
TCK  
O12  
IS  
JTAG Test  
Clock  
This pin functions as the JTAG test clock. The  
maximum operating frequency of this clock is  
25MHz.  
1
Table 2.3 Miscellaneous Pins  
BUFFER  
NUM  
PINS  
NAME  
SYMBOL  
TYPE  
DESCRIPTION  
System Reset  
nRESET  
IS  
This active low pin allows external hardware to  
reset the device.  
1
1
Note:  
This pin should be tied high if it is not  
used.  
Ethernet  
Full-Duplex  
Indicator LED  
nFDX_LED  
GPIO0  
OD12  
(PU)  
This pin is driven low (LED on) when the Ethernet  
link is operating in full-duplex mode.  
General  
Purpose I/O 0  
IS/O12/  
OD12  
(PU)  
This General Purpose I/O pin is fully programmable  
as either a push-pull output, an open-drain output,  
or a Schmitt-triggered input.  
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Table 2.3 Miscellaneous Pins (continued)  
NUM  
PINS  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
Ethernet Link  
ActivityIndicator  
LED  
nLNKA_LED  
OD12  
(PU)  
This pin is driven low (LED on) when a valid link is  
detected. This pin is pulsed high (LED off) for  
80mS whenever transmit or receive activity is  
detected. This pin is then driven low again for a  
minimum of 80mS, after which time it will repeat  
the process if TX or RX activity is detected.  
Effectively, LED2 is activated solid for a link. When  
transmit or receive activity is sensed, LED2 will  
function as an activity indicator.  
1
General  
Purpose I/O 1  
GPIO1  
IS/O12/  
OD12  
(PU)  
This General Purpose I/O pin is fully programmable  
as either a push-pull output, an open-drain output,  
or a Schmitt-triggered input.  
Ethernet Speed  
Indicator LED  
nSPD_LED  
OD12  
(PU)  
This pin is driven low (LED on) when the Ethernet  
operating speed is 100Mbs, or during auto-  
negotiation. This pin is driven high during 10Mbs  
operation, or during line isolation.  
1
General  
Purpose I/O 2  
GPIO2  
GPIO3  
IS/O12/  
OD12  
(PU)  
This General Purpose I/O pin is fully programmable  
as either a push-pull output, an open-drain output,  
or a Schmitt-triggered input.  
General  
Purpose I/O 3  
IS/O8/  
OD8  
(PU)  
This General Purpose I/O pin is fully programmable  
as either a push-pull output, an open-drain output,  
or a Schmitt-triggered input.  
1
1
1
1
1
General  
Purpose I/O 4  
GPIO4  
IS/O8/  
OD8  
(PU)  
This General Purpose I/O pin is fully programmable  
as either a push-pull output, an open-drain output,  
or a Schmitt-triggered input.  
General  
Purpose I/O 5  
GPIO5  
IS/O8/  
OD8  
(PU)  
This General Purpose I/O pin is fully programmable  
as either a push-pull output, an open-drain output,  
or a Schmitt-triggered input.  
General  
Purpose I/O 6  
GPIO6  
IS/O8/  
OD8  
(PU)  
This General Purpose I/O pin is fully programmable  
as either a push-pull output, an open-drain output,  
or a Schmitt-triggered input.  
General  
Purpose I/O 7  
GPIO7  
IS/O8/  
OD8  
(PU)  
This General Purpose I/O pin is fully programmable  
as either a push-pull output, an open-drain output,  
or a Schmitt-triggered input.  
Detect  
Upstream  
VBUS Power  
VBUS_DET  
IS_5V  
This pin detects the state of the upstream bus  
power. The Hub monitors VBUS_DET to determine  
when to assert the USBDP0 pin's internal pull-up  
resistor (signaling a connect event).  
1
For bus powered hubs, this pin must be tied to  
VDD33IO.  
For self powered hubs, refer to the LAN9512  
reference schematics.  
Auto-MDIX  
Enable  
AUTOMDIX_EN  
TEST1  
IS  
-
Determines the default Auto-MDIX setting.  
1
1
0 = Auto-MDIX is disabled.  
1 = Auto-MDIX is enabled.  
Test 1  
Used for factory testing, this pin must always be left  
unconnected.  
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Table 2.3 Miscellaneous Pins (continued)  
NUM  
PINS  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
Test 2  
TEST2  
-
-
Used for factory testing, this pin must always be  
connected to VSS for proper operation.  
1
1
Test 3  
TEST3  
Used for factory testing, this pin must always be  
connected to VDD33IO for proper operation.  
24 MHz Clock  
Enable  
CLK24_EN  
CLK24_OUT  
TEST4  
IS  
08  
-
This pin enables the generation of the 24 MHz  
clock on the CLK_24_OUT pin.  
1
1
24 MHz Clock  
Test 4  
This pin outputs a 24 MHz clock that can be used  
a reference clock for a partner hub.  
Used for factory testing, this pin must always be left  
unconnected.  
1
Table 2.4 USB Pins  
NUM  
PINS  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
Upstream  
USBDM0  
AIO  
AIO  
Upstream USB DPLUS signal.  
1
1
USB DMINUS 0  
Upstream  
USB  
DPLUS 0  
USBDP0  
Downstream  
USBDM2  
USBDP2  
USBDM3  
USBDP3  
PRTCTL2  
AIO  
AIO  
AIO  
AIO  
Downstream USB peripheral 2 DMINUS signal.  
Downstream USB peripheral 2 DPLUS signal.  
Downstream USB peripheral 3 DMINUS signal.  
Downstream USB peripheral 3 DPLUS signal.  
1
1
1
1
USB DMINUS 2  
Downstream  
USB DPLUS 2  
Downstream  
USB DMINUS 3  
Downstream  
USB DPLUS 3  
USB Port Power  
Control 2  
IS/OD12 When used as an output, this pin enables power to  
(PU)  
downstream USB peripheral 2.  
When used as an input, this pin is used to sample  
the output signal from an external current monitor  
for downstream USB peripheral 2. An overcurrent  
condition is indicated when the signal is low.  
1
Refer to Section 2.1 for additional information.  
USB Port Power  
Control 3  
PRTCTL3  
IS/OD12 When used as an output, this pin enables power to  
(PU)  
downstream USB peripheral 3.  
When used as an input, this pin is used to sample  
the output signal from an external current monitor  
for downstream USB peripheral 3. An overcurrent  
condition is indicated when the signal is low.  
1
Refer to Section 2.1 for additional information.  
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Table 2.4 USB Pins (continued)  
NUM  
PINS  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
External USB  
Bias Resistor  
USBRBIAS  
AI  
Used for setting HS transmit current level and on-  
chip termination impedance. Connect to an  
external 12K 1.0% resistor to ground.  
1
1
USB PLL +1.8V  
Power Supply  
VDD18USBPLL  
XI  
P
Refer to the LAN9512 reference schematics for  
additional connection information.  
Crystal Input  
ICLK  
External 25 MHz crystal input.  
Note:  
This pin can also be driven by a single-  
ended clock oscillator. When this method  
is used, XO should be left unconnected  
1
1
Crystal Output  
XO  
OCLK  
External 25 MHz crystal output.  
Table 2.5 Ethernet PHY Pins  
NUM  
PINS  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
Ethernet TX  
Data Out  
Negative  
TXN  
AIO  
AIO  
AIO  
Negative output of the Ethernet transmitter. The  
transmit data outputs may be swapped internally  
with receive data inputs when Auto-MDIX is  
enabled.  
1
1
Ethernet TX  
Data Out  
Positive  
TXP  
RXN  
Positive output of the Ethernet transmitter. The  
transmit data outputs may be swapped internally  
with receive data inputs when Auto-MDIX is  
enabled.  
Ethernet RX  
Data In  
Negative  
Negative input of the Ethernet receiver. The receive  
data inputs may be swapped internally with  
transmit data outputs when Auto-MDIX is enabled.  
1
1
Ethernet RX  
Data In Positive  
RXP  
AIO  
P
Positive input of the Ethernet receiver. The receive  
data inputs may be swapped internally with  
transmit data outputs when Auto-MDIX is enabled.  
+3.3V Analog  
Power Supply  
VDD33A  
Refer to the LAN9512 reference schematics for  
connection information.  
7
1
1
External PHY  
Bias Resistor  
EXRES  
AI  
P
Used for the internal bias circuits. Connect to an  
external 12.4K 1.0% resistor to ground.  
Ethernet PLL  
+1.8V Power  
Supply  
VDD18ETHPLL  
Refer to the LAN9512 reference schematics for  
additional connection information.  
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Table 2.6 I/O Power Pins, Core Power Pins, and Ground Pad  
NUM  
PINS  
BUFFER  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
+3.3V I/O  
Power  
VDD33IO  
P
P
+3.3V Power Supply for I/O Pins.  
Refer to the LAN9512 reference schematics for  
connection information.  
5
2
Digital Core  
+1.8V Power  
Supply Output  
VDD18CORE  
+1.8 V power from the internal core voltage  
regulator. All VDD18CORE pins must be tied  
together for proper operation.  
Refer to the LAN9512 reference schematics for  
connection information.  
1
Ground  
VSS  
P
Ground  
Note 2.1 Exposed pad on package bottom (Figure 2.1).  
Table 2.7 No-Connect Pins  
BUFFER  
NUM  
PINS  
NAME  
SYMBOL  
TYPE  
DESCRIPTION  
No Connect  
NC  
-
These pins must be left floating for normal device  
operation  
6
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Table 2.8 64-QFN Package Pin Assignments  
PIN  
NUM  
PIN  
NUM  
PIN  
NUM  
PIN  
NUM  
PIN NAME  
PIN NAME  
PIN NAME  
PIN NAME  
1
2
3
4
USBDM2  
USBDP2  
USBDM3  
USBDP3  
17  
18  
19  
20  
NC  
NC  
33  
34  
35  
36  
VDD33IO  
TEST2  
GPIO3  
49  
50  
51  
52  
VDD33A  
EXRES  
VDD33A  
RXP  
VDD33IO  
nFDX_LED/  
GPIO0  
GPIO4  
5
6
VDD33A  
NC  
21  
22  
nLNKA_LED/  
GPIO1  
37  
38  
GPIO5  
53  
54  
RXN  
nSPD_LED/  
GPIO2  
VDD18CORE  
VDD33A  
7
8
NC  
NC  
23  
24  
EECLK  
EECS  
39  
40  
VDD33IO  
TEST3  
55  
56  
TXP  
TXN  
9
NC  
25  
26  
27  
28  
29  
30  
31  
EEDO  
EEDI  
41  
42  
43  
44  
45  
46  
47  
AUTOMDIX_EN  
GPIO6  
57  
58  
59  
60  
61  
62  
63  
VDD33A  
USBDM0  
USBDP0  
XO  
10  
11  
12  
13  
14  
15  
VDD33A  
VBUS_DET  
nRESET  
VDD33IO  
nTRST  
TMS  
GPIO7  
CLK24_EN  
CLK24_OUT  
VDD33IO  
TEST4  
TEST1  
XI  
PRTCTL2  
VDD18CORE  
TDI  
VDD18USBPLL  
USBRBIAS  
TDO  
16  
PRTCTL3  
32  
TCK  
48  
VDD18ETHPLL  
64  
VDD33A  
EXPOSED PAD  
MUST BE CONNECTED TO VSS  
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Datasheet  
2.1  
Port Power Control  
This section details the usage of the port power control pins PRTCTL[3:2].  
2.1.1  
Port Power Control Using a USB Power Switch  
The LAN9512 has a single port power control and over-current sense signal for each downstream port.  
When disabling port power the driver will actively drive a ‘0’. To avoid unnecessary power dissipation,  
the internal pull-up resistor will be disabled at that time. When port power is enabled, the output driver  
is disabled and the pull-up resistor is enabled, creating an open drain output. If there is an over-current  
situation, the USB Power Switch will assert the open drain OCS signal. The schmitt trigger input will  
recognize this situation as a low. The open drain output does not interfere. The overcurrent sense filter  
handles the transient conditions, such as low voltage, while the device is powering up.  
5V  
PRTCTL3  
OCS  
USB Power  
Switch  
EN  
USB  
Device  
LAN9512  
5V  
PRTCTL2  
OCS  
USB Power  
Switch  
EN  
USB  
Device  
Figure 2.2 Port Power Control with USB Power Switch  
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2.1.2  
Port Power Control Using a Poly Fuse  
When using theLAN9512 with a poly fuse, an external diode must be used (See Figure 2.3). When  
disabling port power, the driver will drive a ‘0’. This procedure will have no effect since the external  
diode will isolate the pin from the load. When port power is enabled, the output driver is disabled and  
the pull-up resistor is enabled, which creates an open drain output. This means that the pull-up resistor  
is providing 3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will  
open. This will cause the cathode of the diode to go to 0 volts. The anode of the diode will be at 0.7  
volts, and the Schmidt trigger input will register this as a low, resulting in an overcurrent detection. The  
open drain output does not interfere.  
5V  
Poly Fuse  
PRTCTL3  
USB  
Device  
LAN9512  
5V  
Poly Fuse  
PRTCTL2  
USB  
Device  
Figure 2.3 Port Power Control with Poly Fuse  
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Many customers use a single poly fuse to power all their devices. For the ganged situation, all power  
control pins must be tied together.  
5V  
Poly Fuse  
PRTCTL3  
PRTCTL2  
LAN9512  
USB  
Device  
USB  
Device  
Figure 2.4 Port Power with Ganged Control with Poly Fuse  
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USB Hub with Integrated 10/100 Ethernet Controller  
Datasheet  
2.2  
Buffer Types  
Table 2.9 Buffer Types  
DESCRIPTION  
BUFFER TYPE  
IS  
IS_5V  
O8  
Schmitt-triggered Input  
5V Tolerant Schmitt-triggered Input  
Output with 8mA sink and 8mA source  
Open-drain output with 8mA sink  
OD8  
O12  
OD12  
PU  
Output with 12mA sink and 12mA source  
Open-drain output with 12mA sink  
50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-  
ups are always enabled.  
Note:  
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on  
internal resistors to drive signals external to LAN9512. When connected to a load  
that must be pulled high, an external resistor must be added.  
PD  
50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal  
pull-downs are always enabled.  
Note:  
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely  
on internal resistors to drive signals external to LAN9512. When connected to a  
load that must be pulled low, an external resistor must be added.  
AI  
AIO  
ICLK  
OCLK  
P
Analog input  
Analog bi-directional  
Crystal oscillator input pin  
Crystal oscillator output pin  
Power pin  
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USB Hub with Integrated 10/100 Ethernet Controller  
Datasheet  
Chapter 3 EEPROM Controller (EPC)  
LAN9512 may use an external EEPROM to store the default values for the USB descriptors and the  
MAC address. The EEPROM controller supports most “93C46” type EEPROMs. A total of nine address  
bits are used to support 256/512 byte EEPROMs.  
Note: A 3-wire style 2K/4K EEPROM that is organized for 256/512 x 8-bit operation must be used.  
The MAC address is used as the default Ethernet MAC address and is loaded into the MAC’s ADDRH  
and ADDRL registers. If a properly configured EEPROM is not detected, it is the responsibility of the  
Host LAN Driver to set the IEEE addresses.  
After a system-level reset occurs, the device will load the default values from a properly configured  
EEPROM. The device will not accept USB transactions from the Host until this process is completed.  
The EEPROM controller also allows the Host system to read, write and erase the contents of the Serial  
EEPROM.  
3.1  
EEPROM Format  
Table 3.1 illustrates the format in which data is stored inside of the EEPROM.  
Note the EEPROM offsets are given in units of 16-bit word offsets. A length field with a value of zero  
indicates that the field does not exist in the EEPROM. The device will use the field’s HW default value  
in this case.  
Note: For Device Descriptors, the only valid values for the length are 0 and 18.  
Note: For Configuration and Interface Descriptors, the only valid values for the length are 0 and 18.  
Note: The EEPROM programmer must ensure that if a String Descriptor does not exist in the  
EEPROM, the referencing descriptor must contain 00h for the respective string index field.  
Note: If no Configuration Descriptor is present in the EEPROM, then the Configuration Flags affect  
the values of bmAttributes and bMaxPower in the Ethernet Controller Configuration Descriptor.  
Note: If all String Descriptor lengths are zero, then a Language ID will not be supported.  
Table 3.1 EEPROM Format  
EEPROM ADDRESS  
EEPROM CONTENTS  
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
0xA5  
MAC Address [7:0]  
MAC Address [15:8]  
MAC Address [23:16]  
MAC Address [31:24]  
MAC Address [39:32]  
MAC Address [47:40]  
Full-Speed Polling Interval for Interrupt Endpoint  
Hi-Speed Polling Interval for Interrupt Endpoint  
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USB Hub with Integrated 10/100 Ethernet Controller  
Datasheet  
Table 3.1 EEPROM Format (continued)  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
0Fh  
10h  
11h  
Configuration Flags  
Language ID Descriptor [7:0]  
Language ID Descriptor [15:8]  
Manufacturer ID String Descriptor Length (bytes)  
Manufacturer ID String Descriptor EEPROM Word Offset  
Product Name String Descriptor Length (bytes)  
Product Name String Descriptor EEPROM Word Offset  
Serial Number String Descriptor Length (bytes)  
Serial Number String Descriptor EEPROM Word Offset  
Configuration String Descriptor Length (bytes)  
Configuration String Descriptor Word Offset  
Interface String Descriptor Length (bytes)  
Interface String Descriptor Word Offset  
Hi-Speed Device Descriptor Length (bytes)  
Hi-Speed Device Descriptor Word Offset  
Hi-Speed Configuration and Interface Descriptor Length (bytes)  
Hi-Speed Configuration and Interface Descriptor Word Offset  
Full-Speed Device Descriptor Length (bytes)  
Full-Speed Device Descriptor Word Offset  
Full-Speed Configuration and Interface Descriptor Length (bytes)  
Full-Speed Configuration and Interface Descriptor Word Offset  
RESERVED  
12h  
13h  
14h  
15h  
16h  
17h  
18h  
19h  
1Ah  
1Bh  
1Ch  
1Dh  
1Eh-1Fh  
20h  
21h  
22h  
23h  
24h  
25h  
26h  
27h  
28h  
29h  
2Ah  
2Bh  
Vendor ID LSB Register (VIDL)  
Vendor ID MSB Register (VIDM)  
Product ID LSB Register (PIDL)  
Product ID MSB Register (PIDM)  
Device ID LSB Register (DIDL)  
Device ID MSB Register (DIDM)  
Config Data Byte 1 Register (CFG1)  
Config Data Byte 2 Register (CFG2)  
Config Data Byte 3 Register (CFG3)  
Non-Removable Devices Register (NRD)  
Port Disable (Self) Register (PDS)  
Port Disable (Bus) Register (PDB)  
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USB Hub with Integrated 10/100 Ethernet Controller  
Datasheet  
Table 3.1 EEPROM Format (continued)  
2Ch  
2Dh  
2Eh  
2Fh  
30h  
31h  
32h  
33h  
34h  
35h  
36h  
37h  
38h  
39h  
Max Power (Self) Register (MAXPS)  
Max Power (Bus) Register (MAXPB)  
Hub Controller Max Current (Self) Register (HCMCS)  
Hub Controller Max Current (Bus) Register (HCMCB)  
Power-on Time Register (PWRT)  
Boost_Up Register (BOOSTUP)  
RESERVED  
Boost_3:2 Register (BOOST32)  
RESERVED  
Port Swap Register (PRTSP)  
Port Remap 12 Register (PRTR12)  
Port Remap 3 Register (PRTR3)  
RESERVED  
Status/Command Register (STCD)  
Note: EEPROM byte addresses past 39h can be used to store data for any purpose.  
Table 3.2 describes the Configuration Flags  
Table 3.2 Configuration Flags Description  
BIT  
NAME  
RESERVED  
DESCRIPTION  
7:3  
2
00000b  
Remote Wakeup Support  
0 = The device does not support remote wakeup.  
1 = The device supports remote wakeup.  
1
0
RESERVED  
0b  
Power Method  
0 = The device Controller is bus powered.  
1 = The device Controller is self powered.  
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Datasheet  
3.1.1  
Hub Configuration  
EEPROM offsets 20h through 39h comprise the Hub Configuration parameters. Table 3.3 describes  
these parameters and their default ROM values (Values assumed if no valid EEPROM present).  
Table 3.3 Hub Configuration  
EEPROM  
OFFSET  
DESCRIPTION  
DEFAULT  
20h  
21h  
22h  
23h  
24h  
25h  
26h  
27h  
28h  
29h  
Vendor ID LSB Register (VIDL)  
24h  
Least Significant Byte of the Vendor ID. This is a 16-bit value that uniquely identifies  
the Vendor of the user device (assigned by USB-Interface Forum).  
Vendor ID MSB (VIDM)  
Most Significant Byte of the Vendor ID. This is a 16-bit value that uniquely identifies  
the Vendor of the user device (assigned by USB-Interface Forum).  
04h  
12h  
Product ID LSB Register (PIDL)  
Least Significant Byte of the Product ID. This is a 16-bit value that the Vendor can  
assign that uniquely identifies this particular product (assigned by the OEM).  
Product ID MSB Register (PIDM)  
Most Significant Byte of the Product ID. This is a 16-bit value that the Vendor can  
assign that uniquely identifies this particular product (assigned by the OEM).  
95h  
Device ID LSB Register (DIDL)  
Least Significant Byte of the Device ID. This is a 16-bit device release number in BCD  
format (assigned by the OEM).  
00h  
Device ID MSB Register (DIDM)  
Most Significant Byte of the Device ID. This is a 16-bit device release number in BCD  
format (assigned by the OEM).  
9Bh  
Config Data Byte 1 Register (CFG1)  
details.  
Config Data Byte 2 Register (CFG2)  
details.  
18h  
Config Data Byte 3 Register (CFG3)  
details.  
00h  
Non-Removable Devices Register (NRD)  
Indicates which port(s) include non-removable devices.  
02h  
0 = Port is removable  
1 = Port is non-removable  
Informs the host if one of the active ports has a permanent device that is not  
detachable from the Hub.  
Note:  
The device must provide its own descriptor data.  
Bit 7 = RESERVED  
Bit 6 = RESERVED  
Bit 5 = RESERVED  
Bit 4 = RESERVED  
Bit 3 = 1; Port 3 non-removable  
Bit 2 = 1; Port 2 non-removable  
Bit 1 = 1; Port 1 non-removable  
Bit 0 is RESERVED, always = 0b  
Note:  
Bit 1 must be set to 1 by firmware for proper identification of the Ethernet  
Controller as a non-removable device.  
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Datasheet  
Table 3.3 Hub Configuration (continued)  
EEPROM  
OFFSET  
DESCRIPTION  
DEFAULT  
2Ah  
Port Disable (Self) Register (PDS)  
Disables 1 or more ports.  
30h  
0 = Port is available  
1 = Port is disabled  
During Self-Powered operation, this selects the ports which will be permanently  
disabled, and are not available to be enabled or enumerated by a host controller. The  
ports can be disabled in any order, the internal logic will automatically report the  
correct number of enabled ports to the USB host, and will reorder the active ports in  
order to ensure proper function.  
Bit 7 = RESERVED  
Bit 6 = RESERVED  
Bit 5 = RESERVED  
Bit 4 = RESERVED  
Bit 3 = 1; Port 3 disabled  
Bit 2 = 1; Port 2 disabled  
Bit 1 = 1; Port 1 disabled  
Bit 0 is RESERVED, always = 0b  
2Bh  
Port Disable (Bus) Register (PDB)  
Disables 1 or more ports.  
30h  
0 = Port is available  
1 = Port is disabled  
During Bus-Powered operation, this selects the ports which will be permanently  
disabled, and are not available to be enabled or enumerated by a host controller. The  
ports can be disabled in any order, the internal logic will automatically report the  
correct number of enabled ports to the USB host, and will reorder the active ports in  
order to ensure proper function.  
Bit 7 = RESERVED  
Bit 6 = RESERVED  
Bit 5 = RESERVED  
Bit 4 = RESERVED  
Bit 3 = 1; Port 3 disabled  
Bit 2 = 1; Port 2 disabled  
Bit 1 = 1; Port 1 disabled  
Bit 0 is RESERVED, always = 0b  
2Ch  
2Dh  
Max Power (Self) Register (MAXPS)  
01h  
00h  
Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when  
operating as a self-powered hub. This value includes the hub silicon along with the  
combined power consumption (from VBUS) of all associated circuitry on the board.  
This value also includes the power consumption of a permanently attached peripheral  
if the hub is configured as a compound device, and the embedded peripheral reports  
0mA in its descriptors.  
Note:  
The USB2.0 Specification does not permit this value to exceed 100mA.  
Max Power (Bus) Register (MAXPB)  
Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when  
operating as a bus-powered hub. This value includes the hub silicon along with the  
combined power consumption (from VBUS) of all associated circuitry on the board.  
This value also includes the power consumption of a permanently attached peripheral  
if the hub is configured as a compound device, and the embedded peripheral reports  
0mA in its descriptors.  
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Datasheet  
Table 3.3 Hub Configuration (continued)  
EEPROM  
OFFSET  
DESCRIPTION  
DEFAULT  
2Eh  
2Fh  
Hub Controller Max Current (Self) Register (HCMCS)  
01h  
Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when  
operating as a self-powered hub. This value includes the hub silicon along with the  
combined power consumption (from VBUS) of all associated circuitry on the board.  
This value does NOT include the power consumption of a permanently attached  
peripheral if the hub is configured as a compound device.  
Note:  
The USB2.0 Specification does not permit this value to exceed 100mA.  
Hub Controller Max Current (Bus) Register (HCMCB)  
00h  
Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when  
operating as a bus-powered hub. This value includes the hub silicon along with the  
combined power consumption (from VBUS) of all associated circuitry on the board.  
This value does NOT include the power consumption of a permanently attached  
peripheral if the hub is configured as a compound device.  
30h  
31h  
Power-on Time Register (PWRT)  
32h  
00h  
The length of time that it takes (in 2mS intervals) from the time the host initiated  
power-on sequence begins on a port until power is good on that port. System software  
uses this value to determine how long to wait before accessing a powered-on port.  
Boost_Up Register (BOOSTUP)  
32h  
33h  
RESERVED  
00h  
00h  
Boost_3:2 Register (BOOST32)  
34h  
35h  
RESERVED  
00h  
00h  
Port Swap Register (PRTSP)  
Swaps the Upstream and Downstream USB DP and DM pins for ease of board routing  
to devices and connectors.  
0 = USB D+ functionality is associated with the DP pin and D- functionality is  
associated with the DM pin.  
1 = USB D+ functionality is associated with the DM pin and D- functionality is  
associated with the DP pin.  
Bit 7 = RESERVED  
Bit 6 = RESERVED  
Bit 5 = RESERVED  
Bit 4 = RESERVED  
Bit 3 = 1; Port 3 DP/DM is swapped  
Bit 2 = 1; Port 2 DP/DM is swapped  
Bit 1 = RESERVED  
Bit 0 = 1; Upstream Port DP/DM is swapped  
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Datasheet  
Table 3.3 Hub Configuration (continued)  
EEPROM  
OFFSET  
DESCRIPTION  
Port Remap 12 Register (PRTR12)  
DEFAULT  
36h  
21h  
When a hub is enumerated by a USB Host Controller, the hub is only permitted to  
report how many ports it has. The hub is not permitted to select a numerical range or  
assignment. The Host Controller will number the downstream ports of the hub starting  
with the number 1, up to the number of ports that the hub reported having.  
The host’s port number is referred to as “Logical Port Number” and the physical port  
on the hub is the “Physical Port Number”. When remapping mode is enabled, (see  
Format) the hub’s downstream port numbers can be remapped to different logical port  
numbers (assigned by the host).  
Note:  
The OEM must ensure that Contiguous Logical Port Numbers are used,  
starting from #1 up to the maximum number of enabled ports. This ensures  
that the hub’s ports are numbered in accordance with the way a Host will  
communicate with the ports.  
Bit [7:4] =  
0000  
0001  
0010  
0011  
Physical Port 2 is Disabled  
Physical Port 2 is mapped to Logical Port 1  
Physical Port 2 is mapped to Logical Port 2  
Physical Port 2 is mapped to Logical Port 3  
All others RESERVED  
Bit [3:0] =  
0000  
0001  
0010  
0011  
Physical Port 1 is Disabled  
Physical Port 1 is mapped to Logical Port 1  
Physical Port 1 is mapped to Logical Port 2  
Physical Port 1 is mapped to Logical Port 3  
All others RESERVED  
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Datasheet  
Table 3.3 Hub Configuration (continued)  
EEPROM  
OFFSET  
DESCRIPTION  
DEFAULT  
37h  
Port Remap 3 Register (PRTR3)  
03h  
When a hub is enumerated by a USB Host Controller, the hub is only permitted to  
report how many ports it has. The hub is not permitted to select a numerical range or  
assignment. The Host Controller will number the downstream ports of the hub starting  
with the number 1, up to the number of ports that the hub reported having.  
The host’s port number is referred to as “Logical Port Number” and the physical port  
on the hub is the “Physical Port Number”. When remapping mode is enabled (see  
Format), the hub’s downstream port numbers can be remapped to different logical port  
numbers (assigned by the host).  
Note:  
The OEM must ensure that Contiguous Logical Port Numbers are used,  
starting from #1 up to the maximum number of enabled ports, this ensures  
that the hub’s ports are numbered in accordance with the way a Host will  
communicate with the ports.  
Bit [7:4] =  
-
RESERVED  
Bit [3:0] =  
0000  
0001  
0010  
0011  
Physical Port 3 is Disabled  
Physical Port 3 is mapped to Logical Port 1  
Physical Port 3 is mapped to Logical Port 2  
Physical Port 3 is mapped to Logical Port 3  
All others RESERVED  
38h  
39h  
RESERVED  
00h  
01h  
Status/Command Register (STCD)  
details.  
Note 3.1 Default value is dependent on device revision.  
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Table 3.4 Config Data Byte 1 Register (CFG1) Format  
DESCRIPTION  
BITS  
DEFAULT  
7
Self or Bus Power (SELF_BUS_PWR)  
Selects between Self or Bus-Powered operation.  
1b  
0 = Bus-Powered  
1 = Self-Powered  
The Hub is either Self-Powered (draws less than 2mA of upstream bus  
prior to being configured by the host controller).  
When configured as a Bus-Powered device, the SMSC Hub consumes less  
than 100mA of current prior to being configured. After configuration, the Bus-  
Powered SMSC Hub (along with all associated hub circuitry, any embedded  
devices if part of a compound device, and 100mA per externally available  
downstream port) must consume no more than 500mA of upstream VBUS  
current. The current consumption is system dependent, and the OEM must  
ensure that the USB2.0 specifications are not violated.  
When configured as a Self-Powered device, <1mA of upstream VBUS  
current is consumed and all ports are available, with each port being capable  
of sourcing 500mA of current.  
6
5
RESERVED  
0b  
0b  
High Speed Disable (HS_DISABLE)  
Disables the capability to attach as either a High/Full-Speed device, and  
forces attachment as Full-Speed only (no High-Speed support).  
0 = High-/Full-Speed  
1 = Full-Speed-Only (High-Speed disabled)  
4
Multiple TT Enable (MTT_ENABLE)  
Enables one transaction translator per port operation.  
1b  
Selects between a mode where only one transaction translator is available  
for all ports (Single-TT), or each port gets a dedicated transaction translator  
(Multi-TT) {Note: The host may force Single-TT mode only}.  
0 = Single TT for all ports.  
1 = One TT per port (multiple TT's supported)  
3
EOP Disable (EOP_DISABLE)  
1b  
Disables EOP generation of EOF1 when in Full-Speed mode. During FS  
operation only, this permits the Hub to send EOP if no downstream traffic is  
detected at EOF1. See Section 11.3.1 of the USB 2.0 Specification for  
additional details.  
Note:  
Generation of an EOP at the EOF1 point may prevent a Host  
controller (operating in FS mode) from placing the USB bus in  
suspend.  
0 = An EOP is generated at the EOF1 point if no traffic is detected.  
1 = EOP generation at EOF1 is disabled (note: this is normal USB  
operation).  
Note:  
This is a rarely used feature in the PC environment, existing drivers  
may not have been thoroughly debugged with this feature enabled.  
It is included because it is a permitted feature in Chapter 11 of the  
USB specification.  
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Table 3.4 Config Data Byte 1 Register (CFG1) Format (continued)  
DESCRIPTION  
Over Current Sense (CURRENT_SNS)  
BITS  
DEFAULT  
2:1  
01b  
Selects current sensing on a port-by-port basis, all ports ganged, or none  
(only for bus-powered hubs) The ability to support current sensing on a port  
or ganged basis is hardware implementation dependent.  
00 = Ganged sensing (all ports together)  
01 = Individual port-by-port  
1x = Over current sensing not supported (must only be used with Bus-  
Powered configurations!)  
0
Port Power Switching (PORT_PWR)  
1b  
Enables power switching on all ports simultaneously (ganged), or port power  
is individually switched on and off on a port by port basis (individual). The  
ability to support power enabling on a port or ganged basis is hardware  
implementation dependent.  
0 = Ganged switching (all ports together)  
1 = Individual port by port switching  
Table 3.5 Config Data Byte 2 Register (CFG2) Format  
BITS  
7:6  
DESCRIPTION  
DEFAULT  
00b  
RESERVED  
5:4  
Over Current Timer (OC_TIMER)  
Over Current Timer delay  
01b  
00 = 50ns  
01 = 100ns (This is the recommended value)  
10 = 200ns  
11 = 400ns  
3
Compound Device (COMPOUND)  
1b  
Allows the OEM to indicate that the Hub is part of a compound (see the USB  
Specification for definition) device. The applicable port(s) must also be  
defined as having a “Non-Removable Device”.  
0 = No  
1 = Yes, Hub is part of a compound device  
2:0  
RESERVED  
000b  
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Table 3.6 Config Data Byte 3 Register (CFG3) Format  
DESCRIPTION  
BITS  
7:4  
3
DEFAULT  
RESERVED  
0h  
0b  
Port Re-Mapping Enable (PRTMAP_EN)  
Selects the method used by the Hub to assign port numbers and disable  
ports.  
0 = Standard Mode. The following EEPROM addresses are used to define  
which ports are enabled. The ports mapped as Port’n’ on the Hub are  
reported as Port’n’ to the host, unless one of the ports is disabled, then the  
higher numbered ports are remapped in order to report contiguous port  
numbers to the host.  
EEPROM Address 2Ah: Port Disable for Self-Powered operation  
EEPROM Address 2Bh: Port Disable for Bus-Powered operation  
1 = Port Re-Map mode. The mode enables remapping via the following  
EEPROM addresses:  
EEPROM Address 36h: Port Remap 12  
EEPROM Address 37h: Port Remap 3  
2:0  
RESERVED  
000b  
Table 3.7 Boost_Up Register (BOOSTUP) Format  
BITS  
7:2  
DESCRIPTION  
DEFAULT  
000000b  
00b  
RESERVED  
1:0  
Upstream USB Electrical Signaling Drive Strength Boost Bit for  
Upstream Port A (BOOST_IOUT_A)  
00 = Normal electrical drive strength  
01 = Elevated electrical drive strength (+4% boost)  
10 = Elevated electrical drive strength (+8% boost)  
11 = Elevated electrical drive strength (+12% boost)  
Table 3.8 Boost_3:2 Register (BOOST32) Format  
BITS  
7:6  
DESCRIPTION  
DEFAULT  
00b  
RESERVED  
5:4  
Upstream USB Electrical Signaling Drive Strength Boost Bit for  
Downstream Port 3 (BOOST_IOUT_3)  
00b  
00 = Normal electrical drive strength  
01 = Elevated electrical drive strength (+4% boost)  
10 = Elevated electrical drive strength (+8% boost)  
11 = Elevated electrical drive strength (+12% boost)  
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Table 3.8 Boost_3:2 Register (BOOST32) Format (continued)  
BITS  
DESCRIPTION  
DEFAULT  
3:2  
Upstream USB Electrical Signaling Drive Strength Boost Bit for  
Downstream Port 2 (BOOST_IOUT_2)  
00b  
00 = Normal electrical drive strength  
01 = Elevated electrical drive strength (+4% boost)  
10 = Elevated electrical drive strength (+8% boost)  
11 = Elevated electrical drive strength (+12% boost)  
1:0  
RESERVED  
00b  
Table 3.9 Status/Command Register (STCD) Format  
BITS  
7:2  
1
DESCRIPTION  
DEFAULT  
000000b  
0b  
RESERVED  
Reset (RESET)  
Resets the internal memory back to nRESET assertion default settings.  
0 = Normal Run/Idle State  
1 = Force a reset of the registers to their default state  
Note:  
During this reset, this bit is automatically cleared to its default value  
of 0.  
0
USB Attach and Write Protect (USB_ATTACH)  
1b  
0 = Device is in configuration state  
1 = Hub will signal a USB attach event to an upstream device, and the  
internal memory (address range 00h - FEh) is “write-protected” to prevent  
unintentional data corruption.  
Note:  
This bit is write once and is only cleared by assertion of the external  
nRESET or POR.  
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3.2  
EEPROM Defaults  
The signature value of 0xA5 is stored at address 0. A different signature value indicates to the  
EEPROM controller that no EEPROM or an un-programmed EEPROM is attached to the device. In  
this case, the hardware default values are used, as shown in Table 3.10.  
Table 3.10 EEPROM Defaults  
FIELD  
DEFAULT VALUE  
Ethernet Controller  
MAC Address  
FFFFFFFFFFFFh  
Ethernet Controller  
Full-Speed Polling  
Interval (mS)  
01h  
04h  
Ethernet Controller  
Hi-Speed Polling Interval  
(mS)  
Ethernet Controller  
Configuration Flags  
05h  
01h  
Ethernet Controller  
Maximum Power (mA)  
Ethernet Controller  
Vendor ID  
0424h  
EC00h  
Ethernet Controller  
Product ID  
3.3  
EEPROM Auto-Load  
Certain system level resets (USB reset, POR, nRESET, and SRST) cause the EEPROM contents to  
be loaded into the device. After a reset, the EEPROM controller attempts to read the first byte of data  
from the EEPROM. If the value 0xA5 is read from the first address, then the EEPROM controller will  
assume that the external Serial EEPROM is configured for auto-loading. If a value other than 0xA5 is  
read from the first address, the EEPROM auto-load will not commense.  
Note: The EEPROM contents are loaded for both the Hub and the Ethernet Controller as a result of  
a POR or nRESET. The USB reset results only in the loading of the MAC address from the  
EEPROM. A software reset (SRST) or a EEPROM Reload Command causes the EEPROM  
contents related solely to the Ethernet Controller to be loaded.  
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3.4  
An Example of EEPROM Format Interpretation  
Table 3.11 and Table 3.12 provide an example of how the contents of a EEPROM are formatted.  
Table 3.11 is a dump of the EEPROM memory (256-byte EEPROM), while Table 3.12 illustrates, byte  
by byte, how the EEPROM is formatted.  
Table 3.11 Dump of EEPROM Memory  
OFFSET  
BYTE  
VALUE  
0000h  
0008h  
A5 12 34 56 78 9A BC 01  
04 05 09 04 0A 1D 00 00  
00 00 00 00 00 00 12 22  
12 2B 12 34 12 3D 00 00  
24 04 12 95 00 01 9B 18  
00 02 30 30 01 00 01 00  
32 00 00 00 00 00 21 03  
00 01 0A 03 53 00 4D 00  
53 00 43 00 12 01 00 02  
FF 00 01 40 24 04 00 EC  
00 01 01 00 00 01 09 02  
27 00 01 01 00 E0 01 09  
04 00 00 03 FF 00 FF 00  
12 01 00 02 FF 00 FF 40  
24 04 00 EC 00 01 01 00  
00 01 09 02 27 00 01 01  
00 E0 01 09 04 00 00 03  
FF 00 FF 00 ....................  
..........................................  
0010h  
0018h  
0020h  
0028h  
0030h  
0038h  
0040h  
0048h  
0050h  
0058h  
0060h  
0068h  
0070h  
0078h  
0080h  
0088h  
0090h - 00FFh  
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Table 3.12 EEPROM Example - 256 Byte EEPROM  
EEPROM  
EEPROM  
ADDRESS  
CONTENTS  
(HEX)  
DESCRIPTION  
00h  
01h-06h  
07h  
A5  
EEPROM Programmed Indicator  
12 34 56 78 9A BC  
MAC Address 12 34 56 78 9A BC  
01  
04  
05  
Full-Speed Polling Interval for Interrupt Endpoint (1ms)  
Hi-Speed Polling Interval for Interrupt Endpoint (4ms)  
08h  
09h  
Configuration Flags - The device is self powered and supports remote  
wakeup.  
0Ah-0Bh  
0Ch  
09 04  
0A  
Language ID Descriptor 0409h, English  
Manufacturer ID String Descriptor Length (10 bytes)  
0Dh  
1D  
Manufacturer ID String Descriptor EEPROM Word Offset (1Dh)  
Corresponds to EEPROM Byte Offset 3Ah  
0Eh  
0Fh  
10h  
11h  
12h  
13h  
14h  
15h  
16h  
17h  
00  
00  
00  
00  
00  
00  
00  
00  
12  
22h  
Product Name String Descriptor Length (0 bytes - NA)  
Product Name String Descriptor EEPROM Word Offset (Don’t Care)  
Serial Number String Descriptor Length (0 bytes - NA)  
Serial Number String Descriptor EEPROM Word Offset (Don’t Care)  
Configuration String Descriptor Length (0 bytes - NA)  
Configuration String Descriptor Word Offset (Don’t Care)  
Interface String Descriptor Length (0 bytes - NA)  
Interface String Descriptor Word Offset (Don’t Care)  
Hi-Speed Device Descriptor Length (18 bytes)  
Hi-Speed Device Descriptor Word Offset (22h)  
Corresponds to EEPROM Byte Offset 44h  
18h  
19h  
12  
2B  
Hi-Speed Configuration and Interface Descriptor Length (18 bytes)  
Hi-Speed Configuration and Interface Descriptor Word Offset (2Bh)  
Corresponds to EEPROM Byte Offset 56h  
1Ah  
1Bh  
12  
34  
Full-Speed Device Descriptor Length (18 bytes)  
Full-Speed Device Descriptor Word Offset (34h)  
Corresponds to EEPROM Byte Offset 68h  
1Ch  
1Dh  
12  
Full-Speed Configuration and Interface Descriptor Length (18bytes)  
3D  
Full-Speed Configuration and Interface Descriptor Word Offset (3Dh)  
Corresponds to EEPROM Byte Offset 7Ah  
1Eh  
1Fh  
20h  
00  
00  
24  
RESERVED  
RESERVED  
Vendor ID LSB Register (VIDL)  
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USB Hub with Integrated 10/100 Ethernet Controller  
Datasheet  
Table 3.12 EEPROM Example - 256 Byte EEPROM (continued)  
EEPROM  
CONTENTS  
(HEX)  
EEPROM  
ADDRESS  
DESCRIPTION  
Vendor ID MSB Register (VIDM)  
21h  
22h  
04  
12  
95  
00  
01  
9B  
18  
00  
02  
30  
30  
01  
00  
01  
00  
32  
00  
00  
00  
00  
00  
21  
03  
00  
01  
0A  
03  
Product ID LSB Register (PIDL)  
Product ID MSB Register (PIDM)  
Device ID LSB Register (DIDL)  
Device ID MSB Register (DIDM)  
Config Data Byte 1 Register (CFG1)  
Config Data Byte 2 Register (CFG2)  
Config Data Byte 3 Register (CFG3)  
Non-Removable Devices Register (NRD)  
Port Disable (Self) Register (PDS)  
Port Disable (Bus) Register (PDB)  
Max Power (Self) Register (MAXPS)  
Max Power (Bus) Register (MAXPB)  
Hub Controller Max Current (Self) Register (HCMCS)  
Hub Controller Max Current (Bus) Register (HCMCB)  
Power-on Time Register (PWRT)  
Boost_Up Register (BOOSTUP)  
RESERVED  
23h  
24h  
25h  
26h  
27h  
28h  
29h  
2Ah  
2Bh  
2Ch  
2Dh  
2Eh  
2Fh  
30h  
31h  
32h  
33h  
Boost_3:2 Register (BOOST32)  
RESERVED  
34h  
35h  
Port Swap Register (PRTSP)  
36h  
Port Remap 12 Register (PRTR12)  
Port Remap 3 Register (PRTR3)  
RESERVED  
37h  
38h  
39h  
Status/Command Register (STCD)  
Size of Manufacturer ID String Descriptor (10 bytes)  
Descriptor Type (String Descriptor - 03h)  
3A  
3Bh  
3Ch-43h  
44h  
53 00 4D 00 53 00 43 00 Manufacturer ID String (“SMSC” in UNICODE)  
12  
01  
Size of Hi-Speed Device Descriptor in Bytes (18 bytes)  
Descriptor Type (Device Descriptor - 01h)  
45h  
46h-47h  
00 02  
USB Specification Number that the device complies with (0200h)  
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Table 3.12 EEPROM Example - 256 Byte EEPROM (continued)  
EEPROM  
CONTENTS  
(HEX)  
EEPROM  
ADDRESS  
DESCRIPTION  
48h  
49h  
FF  
00  
Class Code  
Subclass Code  
Protocol Code  
4Ah  
FF  
4Bh  
40  
Maximum Packet Size for Endpoint 0  
Vendor ID (0424h)  
4Ch-4Dh  
4Eh-4Fh  
50h-51h  
52h  
24 04  
00 EC  
00 01  
01  
Product ID (EC00h)  
Device Release Number (0100h)  
Index of Manufacturer String Descriptor  
Index of Product String Descriptor  
53h  
00  
54h  
00  
Index of Serial Number String Descriptor  
Number of Possible Configurations  
55h  
01  
56h  
09  
Size of Hi-Speed Configuration Descriptor in bytes (9 bytes)  
Descriptor Type (Configuration Descriptor - 02h)  
Total length in bytes of data returned (0027h = 39 bytes)  
Number of Interfaces  
57h  
02  
58h-59h  
5Ah  
27 00  
01  
5Bh  
01  
Value to use as an argument to select this configuration  
Index of String Descriptor describing this configuration  
Self powered and remote wakeup enabled  
Maximum Power Consumption is 2 mA  
Size of Descriptor in Bytes (9 Bytes)  
Descriptor Type (Interface Descriptor - 04h)  
Number identifying this Interface  
5Ch  
00  
5Dh  
E0  
5Eh  
01  
5Fh  
09  
60h  
04  
61h  
00  
62h  
00  
Value used to select alternative setting  
Number of Endpoints used for this interface (Less endpoint 0)  
Class Code  
63h  
03  
64h  
FF  
65h  
00  
Subclass Code  
66h  
FF  
Protocol Code  
67h  
00  
Index of String Descriptor Describing this interface  
Size of Full-Speed Device Descriptor in Bytes (18 Bytes)  
Descriptor Type (Device Descriptor - 01h)  
USB Specification Number that the device complies with (0200h)  
68h  
12  
69h  
01  
6Ah-6Bh  
00 02  
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Table 3.12 EEPROM Example - 256 Byte EEPROM (continued)  
EEPROM  
CONTENTS  
(HEX)  
EEPROM  
ADDRESS  
DESCRIPTION  
6Ch  
6Dh  
FF  
00  
Class Code  
Subclass Code  
Protocol Code  
6Eh  
FF  
6Fh  
40  
Maximum Packet Size for Endpoint 0  
Vendor ID (0424h)  
70h-71h  
72h-73h  
74h-75h  
76  
24 04  
00 EC  
00 01  
01  
Product ID (EC00h)  
Device Release Number (0100h)  
Index of Manufacturer String Descriptor  
Index of Product String Descriptor  
77h  
00  
78h  
00  
Index of Serial Number String Descriptor  
Number of Possible Configurations  
79h  
01  
7Ah  
09  
Size of Full-Speed Configuration Descriptor in bytes (9 bytes)  
Descriptor Type (Configuration Descriptor - 02h)  
Total length in bytes of data returned (0027h = 39 bytes)  
Number of Interfaces  
7Bh  
02  
7Ch-7Dh  
7Eh  
27 00  
01  
7Fh  
01  
Value to use as an argument to select this configuration  
Index of String Descriptor describing this configuration  
Self powered and remote wakeup enabled  
Maximum Power Consumption is 2 mA  
Size of Full-Speed Interface Descriptor in Bytes (9 Bytes)  
Descriptor Type (Interface Descriptor - 04h)  
Number identifying this Interface  
80h  
00  
81h  
E0  
01  
82h  
83h  
09  
84h  
04  
85h  
00  
86h  
00  
Value used to select alternative setting  
Number of Endpoints used for this interface (Less endpoint 0)  
Class Code  
87h  
03  
88h  
FF  
89h  
00  
Subclass Code  
8Ah  
FF  
Protocol Code  
8Bh  
00  
Index of String Descriptor describing this interface  
Data storage for use by Host as desired  
8Ch-FFh  
-
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Chapter 4 Operational Characteristics  
4.1  
Absolute Maximum Ratings*  
Supply Voltage (VDD33IO, VDD33A) (Note 4.1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +3.6V  
Positive voltage on signal pins, with respect to ground (Note 4.2). . . . . . . . . . . . . . . . . . . . . . . . . . +6V  
Negative voltage on signal pins, with respect to ground (Note 4.3) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V  
Positive voltage on XI, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.6V  
Positive voltage on XO, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.5V  
o
o
Ambient Operating Temperature in Still Air (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C  
A
o
o
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +150 C  
Lead Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020  
HBM ESD Performance per JESD 22-A114-E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+/- 8kV  
Contact Discharge ESD Performance per IEC61000-4-2 (Note 4.4) . . . . . . . . . . . . . . . . . . . . . .+/- 8kV  
Air-Gap Discharge ESD Performance per IEC61000-4-2 (Note 4.4) . . . . . . . . . . . . . . . . . . . . .+/- 15kV  
Latch-up Performance per EIA/JESD 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+/- 200mA  
Note 4.1 When powering this device from laboratory or system power supplies, it is important that  
the absolute maximum ratings not be exceeded or device failure can result. Some power  
supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In  
addition, voltage transients on the AC power line may appear on the DC output. If this  
possibility exists, it is suggested that a clamp circuit be used.  
Note 4.2 This rating does not apply to the following pins: XI, XO, EXRES, USBRBIAS.  
Note 4.3 This rating does not apply to the following pins: EXRES, USBRBIAS.  
Note 4.4 Performed by independant 3rd party test facility.  
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is  
a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect  
device reliability. Functional operation of the device at any condition exceeding those indicated in  
of this specification is not implied. Note, device signals are NOT 5 volt tolerant unless specified  
otherwise.  
4.2  
Operating Conditions**  
Supply Voltage (VDD33A, VDD33BIAS, VDD33IO) . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.3V +/- 300mV  
o
o
Ambient Operating Temperature in Still Air (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C  
A
**Proper operation of LAN9512 is guaranteed only within the ranges specified in this section.  
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4.3  
Power Consumption  
This section details the power consumption of the device as measured during various modes of  
operation. Power dissipation is determined by temperature, supply voltage, and external source/sink  
requirements.  
4.3.1  
Operational Current Consumption & Power Dissipation  
Table 4.1 Operational Current Consumption & Power Dissipation (VDD33IO = VDD33A = 3.3V)  
PARAMETER  
MIN  
TYPICAL  
MAX  
UNIT  
100BASE-TX Full Duplex (USB High-Speed)  
Supply current (VDD33IO, VDD33A)  
Power Dissipation (Device Only)  
231  
763  
mA  
mW  
10BASE-T Full Duplex (USB High-Speed)  
Supply current (VDD33IO, VDD33A)  
Power Dissipation (Device Only)  
188  
621  
mA  
mW  
10BASE-T Full Duplex (USB Full-Speed)  
Supply current (VDD33IO, VDD33A)  
Power Dissipation (Device Only)  
152  
502  
mA  
mW  
Note: All values measured with maximum simultaneous traffic on the Ethernet port and all USB ports.  
Note: Magnetic power consumption:  
100BASE-TX: ~42mA  
10BASE-T: ~104mA  
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4.4  
DC Specifications  
Table 4.2 I/O Buffer Characteristics  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
IS Type Input Buffer  
Low Input Level  
V
-0.3  
V
V
ILI  
IHI  
ILT  
IHT  
High Input Level  
V
V
3.6  
1.35  
1.8  
Negative-Going Threshold  
Positive-Going Threshold  
SchmittTrigger Hysteresis  
1.01  
1.39  
345  
1.18  
1.6  
V
Schmitt trigger  
Schmitt trigger  
V
V
V
420  
485  
mV  
HYS  
(V  
- V  
)
IHT  
ILT  
Input Leakage  
IN  
I
-10  
10  
uA  
pF  
IH  
(V = VSS or VDD33IO)  
Input Capacitance  
C
2.5  
IN  
IS_5V Type Input Buffer  
Low Input Level  
V
-0.3  
V
V
ILI  
IHI  
ILT  
IHT  
High Input Level  
V
V
5.5  
1.35  
1.8  
Negative-Going Threshold  
Positive-Going Threshold  
SchmittTrigger Hysteresis  
1.01  
1.39  
345  
1.18  
1.6  
V
Schmitt trigger  
Schmitt trigger  
V
V
V
420  
485  
mV  
HYS  
(V  
- V  
)
IHT  
ILT  
Input Leakage  
IN  
I
I
-10  
10  
120  
3.5  
uA  
uA  
pF  
IH  
IH  
(V = VSS or VDD33IO)  
Input Leakage  
(V = 5.5V)  
IN  
Input Capacitance  
O8 Type Buffers  
C
IN  
Low Output Level  
V
0.4  
V
V
I
= 8mA  
OL  
OL  
VDD33IO - 0.4  
High Output Level  
OD8 Type Buffer  
V
I
= -8mA  
OH  
OH  
Low Output Level  
O12 Type Buffers  
V
V
0.4  
0.4  
V
I
= 8mA  
OL  
OL  
Low Output Level  
V
V
I
= 12mA  
= -12mA  
OL  
OL  
VDD33IO - 0.4  
High Output Level  
OD12 Type Buffer  
V
I
OH  
OH  
Low Output Level  
V
0.4  
V
I
= 12mA  
OL  
OL  
ICLK Type Buffer (XI Input)  
Low Input Level  
High Input Level  
V
-0.3  
1.4  
0.5  
3.6  
V
V
ILI  
V
IHI  
Note 4.5 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down  
and pull-up resistors add +/- 50uA per-pin (typical)  
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Note 4.6 This is the total 5.5V input leakage for the entire device.  
Note 4.7 XI can optionally be driven from a 25MHz single-ended clock oscillator.  
Table 4.3 100BASE-TX Transceiver Characteristics  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
Peak Differential Output Voltage High  
Peak Differential Output Voltage Low  
Signal Amplitude Symmetry  
Signal Rise and Fall Time  
Rise and Fall Symmetry  
Duty Cycle Distortion  
V
950  
-950  
98  
3.0  
-
-
-
1050  
-1050  
102  
5.0  
mVpk  
mVpk  
%
PPH  
V
PPL  
V
-
SS  
T
-
nS  
RF  
T
-
0.5  
nS  
RFS  
D
35  
-
50  
-
65  
%
CD  
Overshoot and Undershoot  
Jitter  
V
5
%
OS  
1.4  
nS  
Note 4.8 Measured at line side of transformer, line replaced by 100Ω (+/- 1%) resistor.  
Note 4.9 Offset from 16nS pulse width at 50% of pulse peak.  
Note 4.10 Measured differentially.  
Table 4.4 10BASE-T Transceiver Characteristics  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
Transmitter Peak Differential Output Voltage  
Receiver Differential Squelch Threshold  
V
2.2  
2.5  
2.8  
V
OUT  
V
300  
420  
585  
mV  
DS  
Note 4.11 Min/max voltages guaranteed as measured with 100Ω resistive load.  
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USB Hub with Integrated 10/100 Ethernet Controller  
Datasheet  
4.5  
AC Specifications  
This section details the various AC timing specifications of the LAN9512.  
Note: The USBDP and USBDM pin timing adheres to the USB 2.0 specification. Refer to the  
Universal Serial Bus Revision 2.0 specification for detailed USB timing information.  
4.5.1  
Equivalent Test Load  
Output timing specifications assume the 25pF equivalent test load illustrated in Figure 4.1 below.  
OUTPUT  
25 pF  
Figure 4.1 Output Equivalent Test Load  
4.5.2  
Reset Timing  
The nRESET pin input assertion time must be a minimum of 1 μS. Assertion of nRESET is not a  
requirement. However, if used, it must be asserted for the minimum period specified.  
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USB Hub with Integrated 10/100 Ethernet Controller  
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4.5.3  
EEPROM Timing  
The following specifies the EEPROM timing requirements for LAN9512:  
tcsl  
EECS  
tckcyc  
tcklcsl  
tckh  
tckl  
tcshckh  
EECLK  
tckldis  
tdvckh tckhdis  
EEDO  
EEDI  
tdsckh  
tdhckh  
tdhcsl  
tcshdv  
EEDI (VERIFY)  
Figure 4.1 EEPROM Timing  
Table 4.5 EEPROM Timing Values  
SYMBOL  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
t
EECLK Cycle time  
1110  
550  
550  
1070  
30  
1130  
570  
570  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ckcyc  
EECLK High time  
tckh  
EECLK Low time  
tckl  
EECS high before rising edge of EECLK  
EECLK falling edge to EECS low  
EEDO valid before rising edge of EECLK  
EEDO disable after rising edge EECLK  
EEDI setup to rising edge of EECLK  
EEDI hold after rising edge of EECLK  
EECLK low to data disable (OUTPUT)  
EEDIO valid after EECS high (VERIFY)  
EEDIO hold after EECS low (VERIFY)  
EECS low  
tcshckh  
tcklcsl  
tdvckh  
tckhdis  
tdsckh  
tdhckh  
tckldis  
tcshdv  
tdhcsl  
tcsl  
550  
550  
90  
0
580  
600  
0
1070  
SMSC LAN9512  
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4.6  
Clock Circuit  
LAN9512 can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/-  
50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left  
unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle  
is 40% minimum, 50% typical and 60% maximum.  
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal  
input/output signals (XI/XO). See Table 4.6 for the recommended crystal specifications.  
Table 4.6 LAN9512 Crystal Specifications  
PARAMETER  
SYMBOL  
MIN  
NOM  
AT, typ  
Fundamental Mode  
Parallel Resonant Mode  
MAX  
UNITS  
NOTES  
Crystal Cut  
Crystal Oscillation Mode  
Crystal Calibration Mode  
Frequency  
F
-
25.000  
-
MHz  
PPM  
PPM  
PPM  
PPM  
pF  
fund  
o
Frequency Tolerance @ 25 C  
Frequency Stability Over Temp  
Frequency Deviation Over Time  
Total Allowable PPM Budget  
Shunt Capacitance  
F
-
-
+/-50  
tol  
F
-
-
+/-50  
temp  
F
-
+/-3 to 5  
-
age  
-
-
7 typ  
20 typ  
-
+/-50  
C
-
-
O
Load Capacitance  
C
-
-
-
pF  
L
Drive Level  
P
300  
uW  
W
Equivalent Series Resistance  
Operating Temperature Range  
LAN9512 XI Pin Capacitance  
LAN9512 XO Pin Capacitance  
R
-
0
-
-
50  
+70  
-
Ohm  
1
o
-
C
3 typ  
3 typ  
pF  
pF  
-
-
Note 4.12 The maximum allowable values for Frequency Tolerance and Frequency Stability are  
application dependant. Since any particular application must meet the IEEE +/-50 PPM  
Total PPM Budget, the combination of these two values must be approximately +/-45 PPM  
(allowing for aging).  
Note 4.13 Frequency Deviation Over Time is also referred to as Aging.  
Note 4.14 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as  
+/- 50 PPM.  
Note 4.15 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not  
included in this value. The XO/XI pin and PCB capacitance values are required to  
accurately calculate the value of the two external load capacitors. These two external load  
capacitors determine the accuracy of the 25.000 MHz frequency.  
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USB Hub with Integrated 10/100 Ethernet Controller  
Datasheet  
Chapter 5 Package Outline  
5.1  
64-QFN Package  
Figure 5.1 LAN9512 64-QFN Package Definition  
Table 5.1 LAN9512 64-QFN Dimensions  
MIN  
NOMINAL  
MAX  
REMARKS  
A
0.80  
0.00  
-
0.85  
0.02  
1.00  
0.05  
0.80  
9.10  
8.85  
7.40  
0.50  
0.30  
Overall Package Height  
Standoff  
A1  
A2  
0.65  
Mold Cap Thickness  
X/Y Body Size  
D/E  
D1/E1  
D2/E2  
L
8.90  
8.65  
7.20  
0.30  
0.18  
9.00  
8.75  
X/Y Mold Cap Size  
X/Y Exposed Pad Size  
Terminal Length  
7.30  
0.40  
b
0.25  
Terminal Width  
e
0.50 BSC  
-
Terminal Pitch  
K
0.35  
-
Pin to Center Pad Clearance  
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Datasheet  
Notes:  
1. All dimensions are in millimeters unless otherwise noted.  
2. Dimension “b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip.  
3. Details of terminal #1 identifier are optional, but must be located within the area indicated. The terminal #1  
identifier may be either a mold or marked feature.  
Figure 5.2 LAN9512 Recommended PCB Land Pattern  
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