SMSC Switch LAN8720 User Manual

IPD

Input with 67k (typical) internal pull-down.

IOPU

Input/Output with 67k (typical) internal pull-up. Output has 8mA sink and 8mA source.

Input/Output with 67k (typical) internal pull-down. Output has 8mA sink and 8mA source.

IOPD

to Section 5.3.9.1, "Physical Address Bus -

AIO

ICLK

OCLK

Analog input

Analog bi-directional

Crystal oscillator input pin

Crystal oscillator output pin

Power pin

Note 3.1 Unless otherwise noted in the pin description, internal pull-up and pull-down resistors are

always enabled. The internal pull-up and pull-down resistors prevent unconnected inputs

from floating, and must not be relied upon to drive signals external to LAN8720/LAN8720i.

When connected to a load that must be pulled high or low, an external resistor must be

added.

Note: The digital signals are not 5V tolerant.They are variable voltage from +1.6V to +3.6V, as shown

in T a ble 7.1.

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3.1

MAC Interface Signals

Table 3.2 RMII Signals 24-QFN

SIGNAL

NAME

24-QFN

PIN #

TYPE

DESCRIPTION

TXD0

Transmit Data 0: The MAC transmits data to the PHY using this signal in

all modes.

TXD1

TXEN

Transmit Data 1: The MAC transmits data to the PHY using this signal in

all modes

IPD

Transmit Enable: Indicates that valid data is presented on the TXD[1:0]

signals, for transmission.

RXD0/

MODE0

IOPU Receive Data 0: Bit 0 of the 4 data bits that are sent by the PHY in the

receive path.

PHY Operating Mode Bit 0: set the default MODE of the PHY.

„ See Section 5.3.9.2 for information on the MODE options.

RXD1/

MODE1

IOPU Receive Data 1: Bit 1 of the 4 data bits that are sent by the PHY in the

receive path.

PHY Operating Mode Bit 1: set the default MODE of the PHY.

„ See Section 5.3.9.2 for information on the MODE options.

RXER/

PHYAD0

IOPD Receive Error: Asserted to indicate that an error was detected somewhere

in the frame presently being transferred from the PHY.

„ The RXER signal is optional in RMII Mode.

„ This signal is mux’d with PHYAD0

„ See Section 5.3.9.1 for information on the ADDRESS options.

CRS_DV/

MODE2

IOPU RMII Mode CRS_DV (Carrier Sense/Receive Data Valid) Asserted to

indicate when the receive medium is non-idle. When a 10BT packet is

received, CRS_DV is asserted, but RXD[1:0] is held low until the SFD byte

(10101011) is received. In 10BT, half-duplex mode, transmitted data is not

looped back onto the receive data pins, per the RMII standard.

PHY Operating Mode Bit 2: set the default MODE of the PHY.

„ See Section 5.3.9.2 for information on the MODE options.

3.2

LED Signals

Table 3.3 LED Signals 24-QFN

SIGNAL

NAME

24-QFN

PIN #

TYPE

DESCRIPTION

LED1/

REGOFF

IOPD LED1 – Link activity LED Indication.

See Section 5.3.7 for a description of LED modes.

Regulator Off: This pin may be used to configure the internal 1.2V regulator

off. As described in Section 4.11, this pin is sampled during the power-on

sequence to determine if the internal regulator should turn on. When the

regulator is disabled, external 1.2V must be supplied to VDDCR.

„ When LED1/REGOFF is pulled high to VDD2A with an external resistor, the

internal regulator is disabled.

„ When LED1/REGOFF is floating or pulled low, the internal regulator is

enabled (default).

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Table 3.3 LED Signals 24-QFN (continued)

SIGNAL

NAME

24-QFN

PIN #

TYPE

DESCRIPTION

LED2/

nINTSEL

IOPU LED2 – Link speed LED Indication.

See Section 5.3.7 for a description of LED modes.

nINTSEL: On power-up or external reset, the mode of the nINT/REFCLKO

pin is selected.

See Section 4.10 for additional detail.

„ When LED2/nINTSEL is floated or pulled to VDD2A, nINT is selected for

operation on pin nINT/REFCLKO (default).

„ When LED2/nINTSEL is pulled low to VSS through a resistor, REFCLKO is

selected for operation on pin nINT/REFCLKO.

3.3

Management Signals

Table 3.4 Management Signals 24-QFN

SIGNAL

NAME

24-QFN

PIN #

TYPE

DESCRIPTION

MDIO

MDC

IOD8

Management Data Input/OUTPUT: Serial management data input/output.

Management Clock: Serial management clock.

3.4

General Signals

Table 3.5 General Signals 24-QFN

SIGNAL

NAME

24-QFN

PIN #

TYPE

DESCRIPTION

nINT/

REFCLKO

IOPU nINT – Active low interrupt output. Place an external resistor pull-up to

VDDIO.

REFCLKO – 50MHz clock derived from the 25MHz crystal oscillator.

See Section 4.7.2 for additional detail.

„ See DESCRIPTION of pin 2: LED2 – Link speed LED Indication.

„ This signal is mux’d with REFCLKO.

XTAL1/

CLKIN

ICLK

Clock Input: Crystal connection or external clock input.

XTAL2

OCL

Clock Output: Crystal connection.

„ Float this pin when an external clock is driven to XTAL1/CLKIN.

nRST

IOPU External Reset: Input of the system reset. This signal is active LOW.

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3.5

10/100 Line Interface Signals

Table 3.6 10/100 Line Interface Signals 24-QFN

SIGNAL

NAME

24-QFN

PIN #

TYPE

DESCRIPTION

Transmit/Receive Positive Channel 1.

TXP

TXN

RXP

RXN

AIO

Transmit/Receive Negative Channel 1.

Transmit/Receive Positive Channel 2.

Transmit/Receive Negative Channel 2.

3.6

Analog Reference

Table 3.7 Analog References 24-QFN

SIGNAL

NAME

24-QFN

PIN #

TYPE

DESCRIPTION

RBIAS

External 1% Bias Resistor. Requires an 12.1k resistor to ground connected

as described in the Analog Layout Guidelines. The nominal voltage is 1.2V

and therefore the resistor will dissipate approximately 1mW of power.

3.7

Power Signals

Table 3.8 Power Signals 24-QFN

SIGNAL

NAME

24-QFN

PIN #

TYPE

DESCRIPTION

+1.6V to +3.6V Variable I/O Pad Power

VDDIO

VDDCR

+1.2V (Core voltage) - 1.2V for digital circuitry on chip. Supplied by the on-

chip regulator unless configured for regulator off mode using the

RXCLK/REGOFF pin. A 1uF decoupling capacitor to ground should be used

on this pin when using the internal 1.2V regulator.

VDD1A

VDD2A

VSS

+3.3V Analog Port Power to Channel 1.

+3.3V Analog Port Power to Channel 2 and to internal regulator.

FLAG

GND

The flag must be connected to the ground plane with a via array under the

exposed flag. This is the ground connection for the IC.

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Chapter 4 Architecture Details

4.1

Top Level Functional Architecture

Functionally, the transceiver can be divided into the following sections:

„

100Base-TX transmit and receive

10Base-T transmit and receive

RMII interface to the controller

Auto-negotiation to automatically determine the best speed and duplex possible

Management Control to read status registers and write control registers

PLL

MAC

Ref_CLK

4B/5B

Encoder

Scrambler

and PISO

25MHz

by 4 bits

25MHz by

5 bits

RMII 50Mhz by 2 bits

RMII

NRZI

Converter

MLT-3

Converter

Driver

125 Mbps Serial

NRZI

MLT-3

Magnetics

RJ45

CAT-5

Figure 4.1 100Base-TX Data Path

4.2

100Base-TX Transmit

The data path of the 100Base-TX is shown in Figure 4.1. Each major block is explained below.

4.2.1

100M Transmit Data Across the MII/RMII Interface

For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate

valid data. The data is latched by the transceiver’s MII block on the rising edge of TXCLK. The data

is in the form of 4-bit wide 25MHz data.

For RMII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate

valid data. The data is latched by the transceiver’s RMII block on the rising edge of REF_CLK. The

data is in the form of 2-bit wide 50MHz data.

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4.2.2

4B/5B Encoding

The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from

4-bit nibbles to 5-bit symbols (known as “code-groups”) according to T a ble 4.1. Each 4-bit data-nibble

is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for

control information or are not valid.

The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles,

0 through F. The remaining code-groups are given letter designations with slashes on either side. For

example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.

The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is

bypassed the 5 transmit data bit is equivalent to TXER.

Note that encoding can be bypassed only when the MAC interface is configured to operate in MII

mode.

Table 4.1 4B/5B Code Table

CODE

GROUP

RECEIVER

INTERPRETATION

TRANSMITTER

INTERPRETATION

SYM

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

11111

11000

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

DATA

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

DATA

IDLE

Sent after /T/R until TXEN

Sent for rising TXEN

First nibble of SSD, translated to “0101”

following IDLE, else RXER

10001

01101

Second nibble of SSD, translated to

“0101” following J, else RXER

Sent for rising TXEN

Sent for falling TXEN

First nibble of ESD, causes de-assertion

of CRS if followed by /R/, else assertion

of RXER

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Table 4.1 4B/5B Code Table (continued)

CODE

GROUP

RECEIVER

INTERPRETATION

TRANSMITTER

INTERPRETATION

SYM

00111

Second nibble of ESD, causes

deassertion of CRS if following /T/, else

assertion of RXER

Sent for falling TXEN

00100

00110

11001

00000

00001

00010

00011

00101

01000

01100

10000

Transmit Error Symbol

Sent for rising TXER

INVALID

INVALID, RXER if during RXDV

INVALID

4.2.3

Scrambling

Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large

narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power

more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC

regulations to prevent excessive EMI from being radiated by the physical wiring.

The seed for the scrambler is generated from the transceiver address, PHYAD[4:0], ensuring that in

multiple-transceiver applications, such as repeaters or switches, each transceiver will have its own

scrambler sequence.

The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.

4.2.4

4.2.5

NRZI and MLT3 Encoding

The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a

serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a

change in the logic level represents a code bit “1” and the logic output remaining at the same level

represents a code bit “0”.

100M Transmit Driver

The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on

outputs TXP and TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10Base-

T and 100Base-TX signals pass through the same transformer so that common “magnetics” can be

used for both. The transmitter drives into the 100Ω impedance of the CAT-5 cable. Cable termination

and impedance matching require external components.

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4.2.6

100M Phase Lock Loop (PLL)

„

The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125

MHz logic and the 100Base-Tx Transmitter.

PLL

MAC

Ref_CLK

4B/5B

Encoder

Scrambler

and PISO

25MHz

by 4 bits

25MHz by

5 bits

RMII 50Mhz by 2 bits

RMII

NRZI

Converter

MLT-3

Converter

Driver

125 Mbps Serial

NRZI

MLT-3

Magnetics

RJ45

CAT-5

Figure 4.2 Receive Data Path

4.3

100Base-TX Receive

The receive data path is shown in Figure 4.2. Detailed descriptions are given below.

4.3.1

100M Receive Input

The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio

transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second.

Using a 64-level quanitizer it generates 6 digital bits to represent each sample. The DSP adjusts the

gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC

can be used.

4.3.2

Equalizer, Baseline Wander Correction and Clock and Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates

for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,

and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m

and 150m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency

pole of the isolation transformer, then the droop characteristics of the transformer will become

significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the

received data, the transceiver corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD

defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing

unit of the DSP, selects the optimum phase for sampling the data. This is used as the received

recovered clock. This clock is used to extract the serial data from the received signal.

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4.3.3

4.3.4

NRZI and MLT-3 Decoding

The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then

converted to an NRZI data stream.

Descrambling

The descrambler performs an inverse function to the scrambler in the transmitter and also performs

the Serial In Parallel Out (SIPO) conversion of the data.

During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the

incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to

descramble incoming data.

Special logic in the descrambler ensures synchronization with the remote transceiver by searching for

IDLE symbols within a window of 4000 bytes (40us). This window ensures that a maximum packet size

of 1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE-

symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts

the synchronization process.

The descrambler can be bypassed by setting bit 0 of register 31.

4.3.5

4.3.6

Alignment

The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream

Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored

and utilized until the next start of frame.

5B/4B Decoding

The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The

translated data is presented on the RXD[3:0] signal lines. The SSD, /J/K/, is translated to “0101 0101”

as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the transceiver to assert the

RXDV signal, indicating that valid data is available on the RXD bus. Successive valid code-groups are

translated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting of the /T/R/

symbols, or at least two /I/ symbols causes the transceiver to de-assert carrier sense and RXDV.

These symbols are not translated into data.

The decoding process may be bypassed by clearing bit 6 of register 31. When the decoding is

bypassed the 5 receive data bit is driven out on RXER/RXD4/PHYAD0. Decoding may be bypassed

only when the MAC interface is in MII mode.

4.3.7

Receive Data Valid Signal

The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being

presented on the RXD[3:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/

delimiter has been recognized and RXD is aligned to nibble boundaries. It remains active until either

the /T/R/ delimiter is recognized or link test indicates failure or SIGDET becomes false.

RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media

Independent Interface (MII mode).

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Idle

data data data data

CLEAR-TEXT

RX_CLK

RX_DV

data data data data

RXD

Figure 4.3 Relationship Between Received Data and Specific MII Signals

4.3.8

4.3.9

Receiver Errors

During a frame, unexpected code-groups are considered receive errors. Expected code groups are the

DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER

signal is asserted and arbitrary data is driven onto the RXD[3:0] lines. Should an error be detected

during the time that the /J/K/ delimiter is being decoded (bad SSD error), RXER is asserted true and

the value ‘1110’ is driven onto the RXD[3:0] lines. Note that the Valid Data signal is not yet asserted

when the bad SSD error occurs.

100M Receive Data Across the MII/RMII Interface

In MII mode, the 4-bit data nibbles are sent to the MII block. These data nibbles are clocked to the

controller at a rate of 25MHz. The controller samples the data on the rising edge of RXCLK. To ensure

that the setup and hold requirements are met, the nibbles are clocked out of the transceiver on the

falling edge of RXCLK. RXCLK is the 25MHz output clock for the MII bus. It is recovered from the

received data to clock the RXD bus. If there is no received signal, it is derived from the system

reference clock (XTAL1/CLKIN).

When tracking the received data, RXCLK has a maximum jitter of 0.8ns (provided that the jitter of the

input clock, XTAL1/CLKIN, is below 100ps).

In RMII mode, the 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the

controller at a rate of 50MHz. The controller samples the data on the rising edge of XTAL1/CLKIN

(REF_CLK). To ensure that the setup and hold requirements are met, the nibbles are clocked out of

the transceiver on the falling edge of XTAL1/CLKIN (REF_CLK).

4.4

10Base-T Transmit

Data to be transmitted comes from the MAC layer controller. The 10Base-T transmitter receives 4-bit

nibbles from the MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data

stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the

twisted pair via the external magnetics.

The 10M transmitter uses the following blocks:

„

MII (digital)

TX 10M (digital)

10M Transmitter (analog)

10M PLL (analog)

4.4.1

10M Transmit Data Across the MII/RMII Interface

The MAC controller drives the transmit data onto the TXD BUS. For MII, when the controller has driven

TXEN high to indicate valid data, the data is latched by the MII block on the rising edge of TXCLK.

The data is in the form of 4-bit wide 2.5MHz data.

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In order to comply with legacy 10Base-T MAC/Controllers, in Half-duplex mode the transceiver loops

back the transmitted data, on the receive path. This does not confuse the MAC/Controller since the

COL signal is not asserted during this time. The transceiver also supports the SQE (Heartbeat) signal.

See Section 5.3.2, "Collision Detect," on page 50, for more details.

For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TXEN is asserted,

TXD[1:0] are accepted for transmission by the LAN8720/LAN8720i. TXD[1:0] shall be “00” to indicate

idle when TXEN is deasserted. Values of TXD[1:0] other than “00” when TXEN is deasserted are

reserved for out-of-band signalling (to be defined). Values other than “00” on TXD[1:0] while TXEN is

deasserted shall be ignored by the LAN8720/LAN8720i.TXD[1:0] shall provide valid data for each

REF_CLK period while TXEN is asserted.

4.4.2

Manchester Encoding

The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI

data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz

clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted

(TXEN is low), the TX10M block outputs Normal Link Pulses (NLPs) to maintain communications with

the remote link partner.

4.4.3

10M Transmit Drivers

The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before

being driven out as a differential signal across the TXP and TXN outputs.

4.5

10Base-T Receive

The 10Base-T receiver gets the Manchester- encoded analog signal from the cable via the magnetics.

It recovers the receive clock from the signal and uses this clock to recover the NRZI data stream. This

10M serial data is converted to 4-bit data nibbles which are passed to the controller across the MII at

a rate of 2.5MHz.

This 10M receiver uses the following blocks:

„

Filter and SQUELCH (analog)

10M PLL (analog)

RX 10M (digital)

MII (digital)

4.5.1

4.5.2

10M Receive Input and Squelch

The Manchester signal from the cable is fed into the transceiver (on inputs RXP and RXN) via 1:1 ratio

magnetics. It is first filtered to reduce any out-of-band noise. It then passes through a SQUELCH

circuit. The SQUELCH is a set of amplitude and timing comparators that normally reject differential

voltage levels below 300mV and detect and recognize differential voltages above 585mV.

Manchester Decoding

The output of the SQUELCH goes to the RX10M block where it is validated as Manchester encoded

data. The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to

RXN of the remote partner and vice versa), then this is identified and corrected. The reversed condition

is indicated by the flag “XPOL“, bit 4 in register 27. The 10M PLL is locked onto the received

Manchester signal and from this, generates the received 20MHz clock. Using this clock, the

Manchester encoded data is extracted and converted to a 10MHz NRZI data stream. It is then

converted from serial to 4-bit wide parallel data.

The RX10M block also detects valid 10Base-T IDLE signals - Normal Link Pulses (NLPs) - to maintain

the link.

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4.5.3

10M Receive Data Across the MII/RMII Interface

For MII, the 4 bit data nibbles are sent to the MII block. In MII mode, these data nibbles are valid on

the rising edge of the 2.5 MHz RXCLK.

For RMII, the 2bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid

on the rising edge of the RMII REF_CLK.

4.5.4

Jabber Detection

Jabber is a condition in which a station transmits for a period of time longer than the maximum

permissible packet length, usually due to a fault condition, that results in holding the TXEN input for a

long period. Special logic is used to detect the jabber state and abort the transmission to the line, within

45ms. Once TXEN is deasserted, the logic resets the jabber condition.

As shown in T a ble 5.22, bit 1.1 indicates that a jabber condition was detected.

4.6

MAC Interface

The RMII block is responsible for the communication with the controller.

4.6.1

RMII

The SMSC LAN8720 supports the low pin count Reduced Media Independent Interface (RMII)

intended for use between Ethernet transceivers and Switch ASICs. Under IEEE 802.3, an MII

comprised of 16 pins for data and control is defined. In devices incorporating many MACs or

transceiver interfaces such as switches, the number of pins can add significant cost as the port counts

increase. The management interface (MDIO/MDC) is identical to MII. The RMII interface has the

following characteristics:

„

It is capable of supporting 10Mb/s and 100Mb/s data rates

A single clock reference is used for both transmit and receive.

It provides independent 2 bit wide (di-bit) transmit and receive data paths

It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes

The RMII includes 6 interface signals with one of the signals being optional:

„

transmit data - TXD[1:0]

transmit strobe - TXEN

receive data - RXD[1:0]

receive error - RXER (Optional)

carrier sense - CRS_DV

Reference Clock - (RMII references usually define this signal as REF_CLK)

4.6.1.1

CRS_DV - Carrier Sense/Receive Data Valid

The CRS_DV is asserted by the LAN8720/LAN8720i when the receive medium is non-idle. CRS_DV

is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode.

That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous

zeroes in 10 bits are detected, carrier is said to be detected.

Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which

presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble

boundaries). If the LAN8720/LAN8720i has additional bits to be presented on RXD[1:0] following the

initial deassertion of CRS_DV, then the LAN8720/LAN8720i shall assert CRS_DV on cycles of

REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on cycles of

REF_CLK which present the first di-bit of a nibble. The result is: Starting on nibble boundaries

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CRS_DV toggles at 25 MHz in 100Mb/s mode and 2.5 MHz in 10Mb/s mode when CRS ends before

RXDV (i.e. the FIFO still has bits to transfer when the carrier event ends.) Therefore, the MAC can

accurately recover RXDV and CRS.

During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data

on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV

is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal

decoding takes place.

4.7

Reference Clock

The LAN8720 is designed to operate in one of two available modes as shown in T a ble 4.2.

Table 4.2 REFCLK Modes

MODE

REF_CLK DESCRIPTION

REF_CLK In Mode

REF_CLK Out Mode

Sourced externally, driven on the XTAL1/CLKIN pin

Sourced by LAN8720/LAN8720i at the REFCLKO pin

During start-up, the LAN8720 monitors the LED2/nINTSEL pin to determine which mode has been

configured as described in Section 4.10.

In the first mode, the 50MHz REF_CLK is driven on the XTAL1/CLKIN pin. This is the traditional

system configuration when using RMII, and is described in Section 4.7.1. In the second mode, an

advanced feature of the LAN8720 allows a low-cost 25MHz crystal to be used as the reference for

REF_CLK. This configuration may result in reduced system cost and is described in Section 4.7.2.

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4.7.1

REF_CLK In Mode

A 50MHz source of REF_CLK must be available external to the LAN8720 when using this mode. The

clock is driven to both the MAC and PHY as shown in Figure 4.4.

LAN8720

10/100 PHY

24-QFN

MAC

RMII

MDIO

MDC

nINT

Accepts external

50MHz clock

Mag

RJ45

TXD[1:0]

TXP

TXN

TXEN

RXP

RXN

RXD[1:0]

CRS_DV

RXER

REF_CLK

All RMII signals are

synchronous to the supplied

clock

XTAL1/CLKIN

XTAL2

LED[2:1]

nRST

Interface

50MHz

Reference

Clock

Figure 4.4 External 50MHz clock sources the REF_CLK

4.7.2

REF_CLK OUT Mode

To reduce BOM cost, the LAN8720 includes a feature to generate the RMII REF_CLK signal from a

low-cost, 25MHz, fundamental crystal. This type of crystal is inexpensive in comparison to 3 overtone

crystals that would normally be required for 50MHz. The MAC must be capable of operating with an

external clock to take advantage of this feature as shown in Figure 4.5.

The LAN8720 is a small size, low pin count device. In order to optimize package size and cost, the

REFCLKO pin is multiplexed with the nINT pin. Therefore, in this specific mode of operation, the nINT

pin is disabled since REFCLKO is used to provide the 50MHz clock to the MAC.

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nINT not available in this

configuration

MAC

RMII

LAN8720

10/100 PHY

24-QFN

MDIO

MDC

Capable of

accepting 50MHz

clock

TXD[1:0]

RMII

TXEN

Mag

RJ45

RXD[1:0]

TXP

TXN

CRS_DV

RXER

RXP

RXN

REF_CLK

REFCLKO

XTAL1/CLKIN

XTAL2

LED[2:1]

nRST

25MHz

Interface

Figure 4.5 LAN8720 sources REF_CLK from a 25MHz crystal

In some system architectures, a 25MHz clock source is available. The LAN8720 can be used to

generate the REF_CLK to the MAC as shown in Figure 4.6. It is important to note that in this specific

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example, only a 25MHz clock can be used (clock cannot be 50MHz). Similar to the 25MHz crystal

mode, the nINT function is disabled.

nINT not available in this

configuration

LAN8720

10/100 PHY

24-QFN

MAC

RMII

MDIO

MDC

Capable of

accepting 50MHz

clock

TXD[1:0]

Mag

RJ45

TXP

TXN

TXEN

RXD[1:0]

RXP

RXN

CRS_DV

RXER

REF_CLK

REFCLKO

LED[2:1]

25MHz

Clock

XTAL1/CLKIN

XTAL2

nRST

Interface

Figure 4.6 LAN8720 Sources REF_CLK from External 25MHz Source

The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0],

TXEN, TXD[1:0] and RXER. The LAN8720 uses REF_CLK as the network clock such that no buffering

is required on the transmit data path. However, on the receive data path, the receiver recovers the

clock from the incoming data stream, and the LAN8720 uses elasticity buffering to accommodate for

differences between the recovered clock and the local REF_CLK.

4.8

Auto-negotiation

The purpose of the Auto-negotiation function is to automatically configure the transceiver to the

optimum link parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism

for exchanging configuration information between two link-partners and automatically selecting the

highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in

clause 28 of the IEEE 802.3 specification.

Once auto-negotiation has completed, information about the resolved link can be passed back to the

controller via the Serial Management Interface (SMI). The results of the negotiation process are

reflected in the Speed Indication bits in register 31, as well as the Link Partner Ability Register

(Register 5).

The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC

controller.

The advertised capabilities of the transceiver are stored in register 4 of the SMI registers. The default

advertised by the transceiver is determined by user-defined on-chip signal options.

The following blocks are activated during an Auto-negotiation session:

„

Auto-negotiation (digital)

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„

100M ADC (analog)

100M PLL (analog)

100M equalizer/BLW/clock recovery (DSP)

10M SQUELCH (analog)

10M PLL (analog)

10M Transmitter (analog)

When enabled, auto-negotiation is started by the occurrence of one of the following events:

„

Hardware reset

Software reset

Power-down reset

Link status down

Setting register 0, bit 9 high (auto-negotiation restart)

On detection of one of these events, the transceiver begins auto-negotiation by transmitting bursts of

Fast Link Pulses (FLP). These are bursts of link pulses from the 10M transmitter. They are shaped as

Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst

consists of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP

burst. The 16 even-numbered pulses, which may be present or absent, contain the data word being

transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.

The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE

802.3 clause 28. In summary, the transceiver advertises 802.3 compliance in its selector field (the first

5 bits of the Link Code Word). It advertises its technology ability according to the bits set in register 4

of the SMI registers.

There are 4 possible matches of the technology abilities. In the order of priority these are:

„

100M Full Duplex (Highest priority)

100M Half Duplex

10M Full Duplex

10M Half Duplex

If the full capabilities of the transceiver are advertised (100M, Full Duplex), and if the link partner is

capable of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If

the link partner is capable of Half and Full duplex modes, then auto-negotiation selects Full Duplex as

the highest performance operation.

Once a capability match has been determined, the link code words are repeated with the acknowledge

bit set. Any difference in the main content of the link code words at this time will cause auto-negotiation

to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received.

The capabilities advertised during auto-negotiation by the transceiver are initially determined by the

logic levels latched on the MODE[2:0] bus after reset completes. This bus can also be used to disable

auto-negotiation on power-up.

Writing register 4 bits [8:5] allows software control of the capabilities advertised by the transceiver.

Writing register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before

the new abilities will be advertised. Auto-negotiation can also be disabled via software by clearing

The LAN8720/LAN8720i does not support “Next Page” capability.

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4.8.1

Parallel Detection

If the LAN8720/LAN8720i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs

are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or

10M Normal Link Pulses. In this case the link is presumed to be Half Duplex per the IEEE standard.

This ability is known as “Parallel Detection.” This feature ensures interoperability with legacy link

partners. If a link is formed via parallel detection, then bit 0 in register 6 is cleared to indicate that the

Link Partner is not capable of auto-negotiation. The controller has access to this information via the

management interface. If a fault occurs during parallel detection, bit 4 of register 6 is set.

If the Link Partner is not auto-negotiation capable, then register 5 is updated after completion of parallel

detection to reflect the speed capability of the Link Partner.

4.8.2

Re-starting Auto-negotiation

Auto-negotiation can be re-started at any time by setting register 0, bit 9. Auto-negotiation will also re-

start if the link is broken at any time. A broken link is caused by signal loss. This may occur because

of a cable break, or because of an interruption in the signal transmitted by the Link Partner. Auto-

negotiation resumes in an attempt to determine the new link configuration.

If the management entity re-starts Auto-negotiation by writing to bit 9 of the control register, the

LAN8720/LAN8720i will respond by stopping all transmission/receiving operations. Once the

break_link_timer is done, in the Auto-negotiation state-machine (approximately 1200ms) the auto-

negotiation will re-start. The Link Partner will have also dropped the link due to lack of a received

signal, so it too will resume auto-negotiation.

4.8.3

4.8.4

Disabling Auto-negotiation

Auto-negotiation can be disabled by setting register 0, bit 12 to zero. The device will then force its

speed of operation to reflect the information in register 0, bit 13 (speed) and register 0, bit 8 (duplex).

The speed and duplex bits in register 0 should be ignored when auto-negotiation is enabled.

Half vs. Full Duplex

Half Duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect)

protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds

to both transmit and receive activity. In this mode, If data is received while the transceiver is

transmitting, a collision results.

In Full Duplex mode, the transceiver is able to transmit and receive data simultaneously. In this mode,

CRS responds only to receive activity. The CSMA/CD protocol does not apply and collision detection

is disabled.

4.9

HP Auto-MDIX Support

HP Auto-MDIX facilitates the use of CAT-3 (10 Base-T) or CAT-5 (100 Base-T) media UTP interconnect

cable without consideration of interface wiring scheme. If a user plugs in either a direct connect LAN

cable, or a cross-over patch cable, as shown in Figure 4.7, the SMSC LAN8720/LAN8720i Auto-MDIX

transceiver is capable of configuring the TXP/TXN and RXP/RXN pins for correct transceiver operation.

The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX

and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate

the symmetrical magnetics and termination of an Auto-MDIX design.

The Auto-MDIX function can be disabled using the Special Control/Status Indications register (bit

27.15).

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Figure 4.7 Direct Cable Connection vs. Cross-over Cable Connection

4.10

nINTSEL Strapping and LED Polarity Selection

The LED2/nINTSEL pin is used to select between one of two available modes: REF_CLK In Mode

and REF_CLK Out Mode. The configured mode determines the function of the nINT/REFCLK0 pin.

Table 4.3 LED2/nINTSEL Configuration

POLARITY

MODE

REF_CLK DESCRIPTION

LED2/nINTSEL = 0

REF_CLK Out Mode

REF_CLK In Mode

nINT/REFCLK0 is the source of REF_CLK.

LED2/nINTSEL = 1

nINT/REFCLK0 is an active low interrupt output.

When configured for REF_CLK Out Mode, the LAN8720 generates the 50MHz RMII REF_CLK and

the interrupt is not available in this mode.

The nINTSEL pin is shared with the LED2 pin. The LED2 output will automatically change polarity

based on the presence of an external pull-down resistor. If the LED pin is pulled high (by the internal

pull-up resistor) to select a logical high for nINTSEL, then the LED output will be active low. If the LED

pin is pulled low by an external pull-down resistor to select a logical low nINTSEL, the LED output will

then be an active high output.

To set nINTSEL without LEDs, float the pin to set nINTSEL high or pull-down the pin with an external

resistor to GND to set nINTSEL low. See Figure 4.8.

The LED2/nINTSEL pin is latched on the rising edge of the nRST. The default setting is to float the

pin high for nINT mode.

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nINTSEL = 1

nINTSEL = 0

LED output = active low

LED output = active high

VDD2A

LED2/nINTSEL

10K

~270 ohms

LED2/nINTSEL

Figure 4.8 nINTSEL Strapping on LED2

4.11

REGOFF and LED Polarity Selection

The REGOFF configuration pin is shared with the LED1 pin. The LED1 output will automatically

change polarity based on the presence of an external pull-up resistor. If the LED pin is pulled high to

VDD2A by an external pull-up resistor to select a logical high for REGOFF, then the LED output will

be active low. If the LED pin is pulled low by the internal pull-down resistor to select a logical low for

REGOFF, the LED output will then be an active high output.

To set REGOFF without LEDs, pull-up the pin with an external resistor to VDDIO to disable the

regulator. See Figure 4.9.

REGOFF = 1 (Regulator OFF)

LED output = active low

REGOFF = 0

LED output = active high

VDD2A

LED1/REGOFF

10K

~270 ohms

LED1/REGOFF

Figure 4.9 REGOFF Configuration on LED1

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4.12

4.13

PHY Address Strapping

The PHY ADDRESS bit is latched into an internal register at the end of a hardware reset. The address

bit is input on the RXER/PHYAD0 pin. The default setting is PHYAD0=0 as described in

Section 5.3.9.1.

Variable Voltage I/O

The Digital I/O pins on the LAN8720/LAN8720i are variable voltage to take advantage of low power

savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.8V-10% up

to +3.3V+10%. The I/O voltage the System Designer applies on VDDIO needs to maintain its value

with a tolerance of ± 10%. Varying the voltage up or down, after the transceiver has completed power-

on reset can cause errors in the transceiver operation.

4.14

Transceiver Management Control

The Management Control module includes 3 blocks:

„

Serial Management Interface (SMI)

Management Registers Set

Interrupt

4.14.1

Serial Management Interface (SMI)

The Serial Management Interface is used to control the LAN8720/LAN8720i and obtain its status. This

interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as

“vendor-specific” registers 16 to 31 allowed by the specification. Non-supported registers (7 to 15) will

be read as hexadecimal “FFFF”.

At the system level there are 2 signals, MDIO and MDC where MDIO is bi-directional open-drain and

MDC is the clock.

A special feature (enabled by register 17 bit 3) forces the transceiver to disregard the PHY-Address in

the SMI packet causing the transceiver to respond to any address. This feature is useful in multi-PHY

applications and in production testing, where the same register can be written in all the transceivers

using a single write transaction.

The MDC signal is an aperiodic clock provided by the station management controller (SMC). The MDIO

signal receives serial data (commands) from the controller SMC, and sends serial data (status) to the

SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time between

edges.

The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400

ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a

microcontroller.

The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing

of the data is shown in Figure 4.10 and Figure 4.11.

The timing relationships of the MDIO signals are further described in Section 6.1, "Serial Management

Interface (SMI) Timing," on page 55.

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Read Cycle

MDC

MDI0

...

D15 D14

32 1's

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

Start of

Frame

Code

Turn

Around

Preamble

PHY Address

Data

Data To Phy

Data From Phy

Figure 4.10 MDIO Timing and Frame Structure - READ Cycle

Write Cycle

MDC

...

D15 D14

32 1's

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

PHY Address Register Address

...

MDIO

Start of

Frame

Code

Turn

Around

Preamble

Data

Data To Phy

Figure 4.11 MDIO Timing and Frame Structure - WRITE Cycle

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Chapter 5 SMI Register Mapping

Table 5.1 Control Register: Register 0 (Basic)

Reset Loopback

Speed

Select

A/N

Enable

Power

Down

Isolate Restart A/N

Duplex

Mode

Collision

Test

Reserved

Table 5.2 Status Register: Register 1 (Basic)

Link

100Base

-T4

100Base

-TX

100Base

-TX

10Base-

Reserved

A/N

Complete

Remote

Fault

A/N

Jabber Extended

Detect Capability

Ability Status

Full

Duplex

Half

Duplex

Full

Duplex

Half

Duplex

Table 5.3 PHY ID 1 Register: Register 2 (Extended)

PHY ID Number (Bits 3-18 of the Organizationally Unique Identifier - OUI)

Table 5.4 PHY ID 2 Register: Register 3 (Extended)

PHY ID Number (Bits 19-24 of the Organizationally Unique

Identifier - OUI)

Manufacturer Model Number

Manufacturer Revision Number

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Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended)

Page

Reserved Remote Reserved

Fault

Pause

Operation

100Base-

10Base-

IEEE 802.3 Selector

Field

Full

Duplex

Full

Duplex

Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended)

Page

Acknowledge Remote

Fault

Reserved

Pause

100Base-

100Base-TX

Full Duplex

100Base-

10Base-T

Full

10Base-

IEEE 802.3 Selector Field

Duplex

Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended)

Reserved

Parallel

Detect

Fault

Link

Partner

Able

Page

Received

Link

Partner

A/N Able

Table 5.8 Register 15 (Extended)

IEEE Reserved

Table 5.9 Silicon Revision Register 16: Vendor-Specific

Reserved

Silicon Revision

Reserved

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Table 5.10 Mode Control/ Status Register 17: Vendor-Specific

RSVD

EDPWRDOWN RSVD LOWSQEN MDPREBP FARLOOPBACK RSVD ALTINT RSVD PHYADBP Force ENERGYON RSVD

Good

Link

Status

RSVD = Reserved

Table 5.11 Special Modes Register 18: Vendor-Specific

Reserved MIIMODE

Reserved

MODE

PHYAD

Table 5.12 Register 24: Vendor-Specific

Reserved

Table 5.13 Register 25: Vendor-Specific

Reserved

Table 5.14 Symbol Error Counter Register 26: Vendor-Specific

Symbol Error Counter

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Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific

AMDIXCTRL

Reserved

CH_SELECT

Reserved

SQEOFF

Reserved

XPOL

Reserved

Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific

11 10

Reserved

Table 5.17 Interrupt Source Flags Register 29: Vendor-Specific

Reserved

INT7

INT6

INT5

INT4

INT3

INT2

INT1

Reserved

Table 5.18 Interrupt Mask Register 30: Vendor-Specific

Reserved

Mask Bits

Reserved

Table 5.19 PHY Special Control/Status Register 31: Vendor-Specific

Reserved

Autodone Reserved

GPO2

GPO1

GPO0

Enable 4B5B Reserved

Speed Indication

Reserved Scramble Disable

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The following registers are supported (register numbers are in decimal):

Table 5.20 SMI Register Mapping

DESCRIPTION

Group

Basic Control Register

Basic

Basic Status Register

Basic

PHY Identifier 1

Extended

PHY Identifier 2

Extended

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

Auto-Negotiation Expansion Register

Silicon Revision Register

Mode Control/Status Register

Special Modes

Extended

Vendor-specific

Reserved

Symbol Error Counter Register

Control / Status Indication Register

Special internal testability controls

Interrupt Source Register

Interrupt Mask Register

PHY Special Control/Status Register

5.1

SMI Register Format

The mode key is as follows:

„

RW = Read/write,

SC = Self clearing,

WO = Write only,

RO = Read only,

LH = Latch high, clear on read of register,

LL = Latch low, clear on read of register,

NASR = Not Affected by Software Reset

X = Either a 1 or 0.

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Table 5.21 Register 0 - Basic Control

ADDRESS

NAME

DESCRIPTION

MODE

DEFAULT

0.15

Reset

1 = software reset. Bit is self-clearing. For best results,

when setting this bit do not set other bits in this

Section 5.3.9.2) is set from the register bit values,

and not from the mode pins.

RW/

0.14

0.13

Loopback

1 = loopback mode,

0 = normal operation

Speed Select

1 = 100Mbps,

0 = 10Mbps.

Ignored if Auto Negotiation is enabled (0.12 = 1).

Set by

MODE[2:0]

bus

0.12

Auto-

Negotiation

Enable

1 = enable auto-negotiate process

(overrides 0.13 and 0.8)

0 = disable auto-negotiate process

Set by

MODE[2:0]

bus

0.11

0.10

0.9

Power Down

1 = General power down mode,

0 = normal operation

Isolate

1 = electrical isolation of transceiver from MII

0 = normal operation

Restart Auto-

Negotiate

1 = restart auto-negotiate process

0 = normal operation. Bit is self-clearing.

RW/

0.8

Duplex Mode

1 = Full duplex,

Set by

MODE[2:0]

bus

0 = Half duplex.

Ignored if Auto Negotiation is enabled (0.12 = 1).

0.7

Collision Test

Reserved

1 = enable COL test,

0 = disable COL test

0.6:0

Table 5.22 Register 1 - Basic Status

DESCRIPTION

ADDRESS

NAME

MODE

DEFAULT

1.15

100Base-T4

1 = T4 able,

0 = no T4 ability

1.14

1.13

1.12

1.11

100Base-TX Full

Duplex

1 = TX with full duplex,

0 = no TX full duplex ability

100Base-TX Half

Duplex

1 = TX with half duplex,

0 = no TX half duplex ability

10Base-T Full

Duplex

1 = 10Mbps with full duplex

0 = no 10Mbps with full duplex ability

10Base-T Half

Duplex

1 = 10Mbps with half duplex

0 = no 10Mbps with half duplex ability

1.10:6

1.5

Reserved

Auto-Negotiate

Complete

1 = auto-negotiate process completed

0 = auto-negotiate process not completed

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Table 5.22 Register 1 - Basic Status (continued)

ADDRESS

NAME

DESCRIPTION

MODE

DEFAULT

1.4

Remote Fault

1 = remote fault condition detected

0 = no remote fault

RO/

1.3

1.2

1.1

1.0

Auto-Negotiate

Ability

1 = able to perform auto-negotiation function

0 = unable to perform auto-negotiation function

Link Status

1 = link is up,

0 = link is down

RO/

Jabber Detect

1 = jabber condition detected

0 = no jabber condition detected

RO/

Extended

Capabilities

1 = supports extended capabilities registers

0 = does not support extended capabilities registers

Table 5.23 Register 2 - PHY Identifier 1

DESCRIPTION

ADDRESS

NAME

MODE DEFAULT

RW 0007h

2.15:0

PHY ID Number

Assigned to the 3rd through 18th bits of the

Organizationally Unique Identifier (OUI), respectively.

OUI=00800Fh

Table 5.24 Register 3 - PHY Identifier 2

DESCRIPTION

ADDRESS

NAME

MODE DEFAULT

3.15:10

3.9:4

PHY ID Number

Model Number

Assigned to the 19 through 24 bits of the OUI.

30h

0Fh

Six-bit manufacturer’s model number.

3.3:0

Revision Number

Four-bit manufacturer’s revision number.

DEVICE

REV

Table 5.25 Register 4 - Auto Negotiation Advertisement

DESCRIPTION

ADDRESS

NAME

MODE

DEFAULT

4.15

1 = next page capable,

0 = no next page ability

This Phy does not support next page ability.

4.14

4.13

Reserved

Remote Fault

1 = remote fault detected,

0 = no remote fault

4.12

Reserved

4.11:10

Pause Operation

00 = No PAUSE

01= Symmetric PAUSE

R/W

10= Asymmetric PAUSE toward link partner

11 = Both Symmetric PAUSE and Asymmetric

PAUSE toward local device

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Table 5.25 Register 4 - Auto Negotiation Advertisement (continued)

ADDRESS

NAME

DESCRIPTION

MODE

DEFAULT

4.9

100Base-T4

1 = T4 able,

0 = no T4 ability

This Phy does not support 100Base-T4.

4.8

100Base-TX Full

Duplex

1 = TX with full duplex,

0 = no TX full duplex ability

Set by

MODE[2:0]

bus

4.7

4.6

100Base-TX

1 = TX able,

0 = no TX ability

10Base-T Full

Duplex

1 = 10Mbps with full duplex

0 = no 10Mbps with full duplex ability

Set by

MODE[2:0]

bus

4.5

10Base-T

1 = 10Mbps able,

Set by

MODE[2:0]

bus

0 = no 10Mbps ability

4.4:0

Selector Field

[00001] = IEEE 802.3

00001

Table 5.26 Register 5 - Auto Negotiation Link Partner Ability

NAME DESCRIPTION

ADDRESS

MODE DEFAULT

5.15

1 = “Next Page” capable,

0 = no “Next Page” ability

This Phy does not support next page ability.

5.14

5.13

Acknowledge

Remote Fault

1 = link code word received from partner

0 = link code word not yet received

1 = remote fault detected,

0 = no remote fault

5.12:11

5.10

Reserved

Pause Operation

1 = Pause Operation is supported by remote MAC,

0 = Pause Operation is not supported by remote MAC

5.9

100Base-T4

1 = T4 able,

0 = no T4 ability.

This Phy does not support T4 ability.

5.8

5.7

100Base-TX Full

Duplex

1 = TX with full duplex,

0 = no TX full duplex ability

100Base-TX

1 = TX able,

0 = no TX ability

5.6

10Base-T Full

Duplex

1 = 10Mbps with full duplex

0 = no 10Mbps with full duplex ability

5.5

10Base-T

1 = 10Mbps able,

0 = no 10Mbps ability

5.4:0

Selector Field

[00001] = IEEE 802.3

00001

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Table 5.27 Register 6 - Auto Negotiation Expansion

ADDRESS

NAME

DESCRIPTION

MODE DEFAULT

6.15:5

6.4

Reserved

Parallel Detection

Fault

1 = fault detected by parallel detection logic

0 = no fault detected by parallel detection logic

RO/

6.3

6.2

6.1

6.0

Link Partner Next

Page Able

1 = link partner has next page ability

0 = link partner does not have next page ability

Next Page Able

Page Received

1 = local device has next page ability

0 = local device does not have next page ability

1 = new page received

0 = new page not yet received

RO/

Link Partner Auto- 1 = link partner has auto-negotiation ability

Negotiation Able

0 = link partner does not have auto-negotiation ability

Table 5.28 Register 16 - Silicon Revision

DESCRIPTION

ADDRESS

NAME

MODE DEFAULT

16.15:10

16.9:6

Reserved

Silicon Revision

Reserved

0001

Four-bit silicon revision identifier.

16.5:0

Table 5.29 Register 17 - Mode Control/Status

ADDRESS

NAME

DESCRIPTION

MODE DEFAULT

17.15:14

17.13

Reserved

Write as 0; ignore on read.

EDPWRDOWN

Enable the Energy Detect Power-Down mode:

0 = Energy Detect Power-Down is disabled

1 = Energy Detect Power-Down is enabled

17.12

17.11

Reserved

Write as 0, ignore on read

LOWSQEN

The Low_Squelch signal is equal to LOWSQEN AND

EDPWRDOWN.

Low_Squelch = 1 implies a lower threshold

(more sensitive).

Low_Squelch = 0 implies a higher threshold

(less sensitive).

17.10

17.9

MDPREBP

Management Data Preamble Bypass:

0 – detect SMI packets with Preamble

1 – detect SMI packets without preamble

FARLOOPBACK

Force the module to the FAR Loop Back mode, i.e. all

the received packets are sent back simultaneously (in

100Base-TX only). This bit is only active in RMII

mode, as described in Section 5.3.8.2. This mode

works even if MII Isolate (0.10) is set.

17.8:7

Reserved

Write as 0, ignore on read.

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Table 5.29 Register 17 - Mode Control/Status (continued)

ADDRESS

NAME

DESCRIPTION

Alternate Interrupt Mode.

MODE DEFAULT

17.6

ALTINT

0 = Primary interrupt system enabled (Default).

1 = Alternate interrupt system enabled.

See Section 5.2, "Interrupt Management," on page 48.

17.5:4

17.3

Reserved

PHYADBP

Write as 0, ignore on read.

1 = PHY disregards PHY address in SMI access

write.

17.2

17.1

Force

Good Link Status

0 = normal operation;

1 = force 100TX- link active;

Note:

This bit should be set only during lab testing

ENERGYON

Reserved

ENERGYON – indicates whether energy is detected

on the line (see Section 5.3.5.2, "Energy Detect

Power-Down," on page 51); it goes to “0” if no valid

energy is detected within 256ms. Reset to “1” by

hardware reset, unaffected by SW reset.

17.0

Write as 0. Ignore on read.

Table 5.30 Register 18 - Special Modes

DESCRIPTION

ADDRESS

NAME

MODE DEFAULT

18.15

18.14

Reserved

Write as 0, ignore on read.

Write as 1, ignore on read.

RW,

NASR

18.13:8

18.7:5

Reserved

MODE

Write as 0, ignore on read.

RW,

NASR

000000

XXX

Transceiver Mode of operation. Refer to Section

5.3.9.2, "Mode Bus – MODE[2:0]," on page 53 for

more details.

RW,

NASR

18.4:0

PHYAD

PHY Address.

RW,

NASR

PHYAD

The PHY Address is used for the SMI address and for

the initialization of the Cipher (Scrambler) key. Refer

PHYAD[0]," on page 53 for more details.

Table 5.31 Register 26 - Symbol Error Counter

DESCRIPTION

ADDRESS

NAME

MODE DEFAULT

26.15:0

Sym_Err_Cnt

100Base-TX receiver-based error register that

increments when an invalid code symbol is received

including IDLE symbols. The counter is incremented

only once per packet, even when the received packet

contains more than one symbol error. The 16-bit

if incremented beyond that value. This register is

cleared on reset, but is not cleared by reading the

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Table 5.32 Register 27 - Special Control/Status Indications

ADDRESS

NAME

DESCRIPTION

MODE DEFAULT

27.15

AMDIXCTRL

HP Auto-MDIX control

0 - Auto-MDIX enable

1 - Auto-MDIX disabled (use 27.13 to control channel)

27.14

27.13

Reserved

CH_SELECT

Manual Channel Select

0 - MDI -TX transmits RX receives

1 - MDIX -TX receives RX transmits

27.12

27:11

Reserved

SQEOFF

Write as 0. Ignore on read.

Disable the SQE (Signal Quality Error) test

(Heartbeat):

0 - SQE test is enabled.

1 - SQE test is disabled.

RW,

NASR

27.10:5

27.4

Reserved

XPOL

Write as 0. Ignore on read.

000000

Polarity state of the 10Base-T:

0 - Normal polarity

1 - Reversed polarity

27.3:0

Reserved

XXXXb

Table 5.33 Register 28 - Special Internal Testability Controls

ADDRESS

NAME

DESCRIPTION

MODE DEFAULT

RW N/A

28.15:0

Reserved

Do not write to this register. Ignore on read.

Table 5.34 Register 29 - Interrupt Source Flags

ADDRESS

NAME

DESCRIPTION

MODE DEFAULT

29.15:8

Reserved

Ignore on read.

RO/

29.7

29.6

29.5

29.4

29.3

29.2

INT7

INT6

INT5

INT4

INT3

INT2

1 = ENERGYON generated

0 = not source of interrupt

RO/

1 = Auto-Negotiation complete

0 = not source of interrupt

RO/

1 = Remote Fault Detected

0 = not source of interrupt

RO/

1 = Link Down (link status negated)

0 = not source of interrupt

RO/

1 = Auto-Negotiation LP Acknowledge

0 = not source of interrupt

RO/

1 = Parallel Detection Fault

0 = not source of interrupt

RO/

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Table 5.34 Register 29 - Interrupt Source Flags (continued)

ADDRESS

NAME

DESCRIPTION

MODE DEFAULT

29.1

INT1

1 = Auto-Negotiation Page Received

0 = not source of interrupt

RO/

29.0

Reserved

Ignore on read.

RO/

Table 5.35 Register 30 - Interrupt Mask

ADDRESS

NAME

DESCRIPTION

MODE DEFAULT

30.15:8

30.7:1

Reserved

Mask Bits

Write as 0; ignore on read.

1 = interrupt source is enabled

0 = interrupt source is masked

30.0

Reserved

Write as 0; ignore on read

Table 5.36 Register 31 - PHY Special Control/Status

ADDRESS

NAME

DESCRIPTION

MODE DEFAULT

31.15:13

31.12

Reserved

Autodone

Write as 0, ignore on read.

Auto-negotiation done indication:

0 = Auto-negotiation is not done or disabled (or not

active)

1 = Auto-negotiation is done

Note:

This is a duplicate of register 1.5, however

reads to register 31 do not clear status bits.

31.11:10

31.9:7

Reserved

GPO[2:0]

Write as 0, ignore on Read.

General Purpose Output connected to signals

GPO[2:0]

31.6

Enable 4B5B

0 = Bypass encoder/decoder.

1 = enable 4B5B encoding/decoding.

MAC Interface must be configured in MII mode.

31.5

Reserved

Write as 0, ignore on Read.

31.4:2

Speed Indication

HCDSPEED value:

XXX

[001]=10Mbps Half-duplex

[101]=10Mbps Full-duplex

[010]=100Base-TX Half-duplex

[110]=100Base-TX Full-duplex

31.1

31.0

Reserved

Write as 0; ignore on Read

Scramble Disable

0 = enable data scrambling

1 = disable data scrambling,

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5.2

Interrupt Management

The Management interface supports an interrupt capability that is not a part of the IEEE 802.3

specification. It generates an active low asynchronous interrupt signal on the nINT output whenever

certain events are detected as setup by the Interrupt Mask Register 30.

The Interrupt system on the SMSC The LAN8720 has two modes, a Primary Interrupt mode and an

Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask

bit is set, the difference is how they de-assert the output interrupt signal nINT.

The Primary interrupt mode is the default interrupt mode after a power-up or hard reset, the Alternative

interrupt mode would need to be setup again after a power-up or hard reset.

5.2.1

Primary Interrupt System

The Primary Interrupt system is the default interrupt mode, (Bit 17.6 = ‘0’). The Primary Interrupt

System is always selected after power-up or hard reset.

To set an interrupt, set the corresponding mask bit in the interrupt Mask register 30 (see T a ble 5.37).

Then when the event to assert nINT is true, the nINT output will be asserted.

When the corresponding Event to De-Assert nINT is true, then the nINT will be de-asserted.

Table 5.37 Interrupt Management Table

INTERRUPT SOURCE

FLAG

EVENT TO

ASSERT nINT

EVENT TO

DE-ASSERT nINT

MASK

INTERRUPT SOURCE

30.7

29.7

ENERGYON

17.1

ENERGYON

Rising 17.1

(Note 5.1)

Falling 17.1 or

Reading register 29

30.6

30.5

29.6

29.5

Auto-Negotiation

complete

1.5

1.4

Auto-Negotiate

Complete

Rising 1.5

Rising 1.4

Falling 1.5 or

Reading register 29

Remote Fault

Detected

Remote Fault

Falling 1.4, or

Reading register 1 or

Reading register 29

30.4

30.3

30.2

29.4

29.3

29.2

Link Down

1.2

Link Status

Falling 1.2

Rising 5.14

Rising 6.4

Reading register 1 or

Reading register 29

Auto-Negotiation

LP Acknowledge

5.14

6.4

Acknowledge

Falling 5.14 or

Read register 29

Parallel Detection

Fault

Parallel

Detection Fault

Falling 6.4 or

Reading register 6, or

Reading register 29

Re-Auto Negotiate or

Link down

30.1

29.1

Auto-Negotiation

Page Received

6.1

Page Received

Rising 6.1

Falling of 6.1 or

Reading register 6, or

Reading register 29

Re-Auto Negotiate, or

Link Down.

Note 5.1 If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high,

nINT will assert for 256 ms, approximately one second after ENERGYON goes low when

the Cable is unplugged. To prevent an unexpected assertion of nINT, the ENERGYON

interrupt mask should always be cleared as part of the ENERGYON interrupt service

routine.

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Note: The ENERGYON bit 17.1 is defaulted to a ‘1’ at the start of the signal acquisition process,

therefore the Interrupt source flag 29.7 will also read as a ‘1’ at power-up. If no signal is

present, then both 17.1 and 29.7 will clear within a few milliseconds.

5.2.2

Alternate Interrupt System

The Alternative method is enabled by writing a ‘1’ to 17.6 (ALTINT).

To set an interrupt, set the corresponding bit of the in the Mask Register 30, (see T a ble 5.38).

To Clear an interrupt, either clear the corresponding bit in the Mask Register (30), this will de-assert

the nINT output, or Clear the Interrupt Source, and write a ‘1’ to the corresponding Interrupt Source

Flag. Writing a ‘1’ to the Interrupt Source Flag will cause the state machine to check the Interrupt

Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If the Condition to De-

Assert is true, then the Interrupt Source Flag is cleared, and the nINT is also de-asserted. If the

Condition to De-Assert is false, then the Interrupt Source Flag remains set, and the nINT remains

asserted.

For example 30.7 is set to ‘1’ to enable the ENERGYON interrupt. After a cable is plugged in,

ENERGYON (17.1) goes active and nINT will be asserted low.

To de-assert the nINT interrupt output, either.

1. Clear the ENERGYON bit (17.1), by removing the cable, then writing a ‘1’ to register 29.7.

2. Clear the Mask bit 30.1 by writing a ‘0’ to 30.1.

Table 5.38 Alternative Interrupt System Management Table

CONDITION

DE-ASSERT

BIT TO

CLEAR

nINT

INTERRUPT SOURCE

FLAG

EVENT TO

ASSERT nINT

MASK

INTERRUPT SOURCE

30.7

30.6

29.7

29.6

ENERGYON

17.1 ENERGYON

Rising 17.1

Rising 1.5

17.1 low

1.5 low

29.7

Auto-Negotiation

complete

1.5

1.4

1.2

Auto-Negotiate

Complete

29.6

30.5

29.5

Remote Fault

Detected

Remote Fault

Rising 1.4

1.4 low

29.5

30.4

30.3

29.4

29.3

Link Down

Link Status

Falling 1.2

Rising 5.14

1.2 high

5.14 low

29.4

29.3

Auto-Negotiation

LP Acknowledge

5.14 Acknowledge

30.2

30.1

29.2

29.1

Parallel

6.4

6.1

Parallel Detection

Fault

Rising 6.4

Rising 6.1

6.4 low

6.1 low

29.2

29.1

Detection Fault

Auto-Negotiation

Page Received

Note: The ENERGYON bit 17.1 is defaulted to a ‘1’ at the start of the signal acquisition process,

therefore the Interrupt source flag 29.7 will also read as a ‘1’ at power-up. If no signal is

present, then both 17.1 and 29.7 will clear within a few milliseconds.

5.3

Miscellaneous Functions

5.3.1

Carrier Sense

The carrier sense is output on CRS. CRS is a signal defined by the MII specification in the IEEE 802.3u

standard. The LAN8720 asserts CRS based only on receive activity whenever the transceiver is either

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in repeater mode or full-duplex mode. Otherwise the transceiver asserts CRS based on either transmit

or receive activity.

The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It

activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier

sense terminates if a span of 10 consecutive ones is detected before a /J/K/ Start-of Stream Delimiter

pair. If an SSD pair is detected, carrier sense is asserted until either /T/R/ End–of-Stream Delimiter

pair or a pair of IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If

/T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by

some non-IDLE symbol.

5.3.2

Collision Detect

A collision is the occurrence of simultaneous transmit and receive operations. The COL output is

asserted to indicate that a collision has been detected. COL remains active for the duration of the

collision. COL is changed asynchronously to both RXCLK and TXCLK. The COL output becomes

inactive during full duplex mode.

COL may be tested by setting register 0, bit 7 high. This enables the collision test. COL will be asserted

within 512 bit times of TXEN rising and will be de-asserted within 4 bit times of TXEN falling.

In 10M mode, COL pulses for approximately 10 bit times (1us), 2us after each transmitted packet (de-

assertion of TXEN). This is the Signal Quality Error (SQE) signal and indicates that the transmission

was successful. The user can disable this pulse by setting bit 11 in register 27.

5.3.3

5.3.4

Isolate Mode

The LAN8720 data paths may be electrically isolated from the MII by setting register 0, bit 10 to a logic

one. In isolation mode, the transceiver does not respond to the TXD, TXEN and TXER inputs, but does

respond to management transactions.

Isolation provides a means for multiple transceivers to be connected to the same MII without contention

occurring. The transceiver is not isolated on power-up (bit 0:10 = 0).

Link Integrity Test

The LAN8720 performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link

Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the reportable

link status bit in Serial Management Register 1, and is driven to the LINK LED.

The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the

ANSI X3.263 TP-PMD standard, to the Link Monitor state-machine, using internal signal called

DATA_VALID. When DATA_VALID is asserted the control logic moves into a Link-Ready state, and

waits for an enable from the Auto Negotiation block. When received, the Link-Up state is entered, and

the Transmit and Receive logic blocks become active. Should Auto Negotiation be disabled, the link

integrity logic moves immediately to the Link-Up state, when the DATA_VALID is asserted.

Note that to allow the line to stabilize, the link integrity logic will wait a minimum of 330 μsec from the

time DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be

negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state.

When the 10/100 digital block is in 10Base-T mode, the link status is from the 10Base-T receiver logic.

5.3.5

Power-Down modes

There are 2 power-down modes for the LAN8720 described in the following sections.

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5.3.5.1

General Power-Down

This power-down is controlled by register 0, bit 11. In this mode the entire transceiver, except the

management interface, is powered-down and stays in that condition as long as bit 0.11 is HIGH. When

bit 0.11 is cleared, the transceiver powers up and is automatically reset.

5.3.5.2

Energy Detect Power-Down

This power-down mode is activated by setting bit 17.13 to 1. In this mode when no energy is present

on the line the transceiver is powered down, except for the management interface, the SQUELCH

circuit and the ENERGYON logic. The ENERGYON logic is used to detect the presence of valid energy

from 100Base-TX, 10Base-T, or Auto-negotiation signals

In this mode, when the ENERGYON signal is low, the transceiver is powered-down, and nothing is

transmitted. When energy is received - link pulses or packets - the ENERGYON signal goes high, and

the transceiver powers-up. It automatically resets itself into the state it had prior to power-down, and

asserts the nINT interrupt if the ENERGYON interrupt is enabled. The first and possibly the second

packet to activate ENERGYON may be lost.

When 17.13 is low, energy detect power-down is disabled.

5.3.6

Reset

The LAN8720 registers are reset by the Hardware and Software resets. Some SMI register bits are

not cleared by Software reset, and these are marked “NASR” in the register tables. The SMI registers

are not reset by the power-down modes described in Section 5.3.5.

For the first 16us after coming out of reset, the MII will run at 2.5 MHz. After that it will switch to 25

MHz if auto-negotiation is enabled.

5.3.6.1

5.3.6.2

5.3.7

Hardware Reset

Hardware reset is asserted by driving the nRST input low.

When the nRST input is driven by an external source, it should be held LOW for at least 100 us to

ensure that the transceiver is properly reset. During a hardware reset an external clock must be

supplied to the XTAL1/CLKIN signal.

Software Reset

Software reset is activated by writing register 0, bit 15 high. This signal is self- clearing. The SMI

registers are reset except those that are marked “NASR” in the register tables.

The IEEE 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be completed

within 0.5s from the setting of this bit.

LED Description

The LAN8720 provides two LED signals. These provide a convenient means to determine the mode

of operation of the transceiver. All LED signals are either active high or active low as described in

Section 4.10 and Section 4.11.

The LED1 output is driven active whenever the LAN8720 detects a valid link, and blinks when CRS is

active (high) indicating activity.

The LED2 output is driven active when the operating speed is 100Mbit/s. This LED will go inactive

when the operating speed is 10Mbit/s or during line isolation (register 31 bit 5).

5.3.8

Loopback Operation

The LAN8720 may be configured for near-end loopback and far loopback.

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5.3.8.1

Near-end Loopback

Near-end loopback is a mode that sends the digital transmit data back out the receive data signals for

testing purposes as indicated by the blue arrows in Figure 5.1.The near-end loopback mode is enabled

by setting bit register 0 bit 14 to logic one.

A large percentage of the digital circuitry is operational near-end loopback mode, because data is

routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The COL

signal will be inactive in this mode, unless collision test (bit 0.7) is active. The transmitters are powered

down, regardless of the state of TXEN.

TXD

RXD

10/100

Ethernet

MAC

CAT-5

XFMR

Digital

Analog

SMSC

Ethernet Transceiver

Figure 5.1 Near-end Loopback Block Diagram

5.3.8.2

Far Loopback

Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in

Figure 5.3. The far loopback mode is enabled by setting bit register 17 bit 9 to logic one. In this mode,

data that is received from the link partner on the MDI is looped back out to the link partner. The digital

interface signals on the local MAC interface are isolated.

Far-end system

TXD

10/100

Ethernet

MAC

Link

Partner

CAT-5

XFMR

^RXDX

Digital

Analog

SMSC

Ethernet Transceiver

Figure 5.2 Far Loopback Block Diagram

Connector Loopback

5.3.8.3

The LAN8720/LAN8720i maintains reliable transmission over very short cables, and can be tested in

a connector loopback as shown in Figure 5.3. An RJ45 loopback cable can be used to route the

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transmit signals an the output of the transformer back to the receiver inputs, and this loopback will

work at both 10 and 100.

TXD

RXD

10/100

Ethernet

MAC

XFMR

Digital

Analog

RJ45 Loopback Cable.

Created by connecting pin 1 to pin 3

and connecting pin 2 to pin 6.

SMSC

Ethernet Transceiver

Figure 5.3 Connector Loopback Block Diagram

5.3.9

Configuration Signals

The hardware configuration signals are sampled during the power-on sequence to determine the

physical address and operating mode.

5.3.9.1

Physical Address Bus - PHYAD[0]

The PHYAD0 bit is driven high or low to give each PHY a unique address. This address is latched into

an internal register at the end of a hardware reset. In a multi-PHY application (such as a repeater),

the controller is able to manage each PHY via the unique address. Each PHY checks each

management data frame for a matching address in the relevant bits. When a match is recognized, the

PHY responds to that particular frame. The PHY address is also used to seed the scrambler. In a multi-

PHY application, this ensures that the scramblers are out of synchronization and disperses the

electromagnetic radiation across the frequency spectrum.

The LAN8720 SMI address may be configured using hardware configuration to either the value 0 or

1. The user can configure the PHY address using Software Configuration if an address greater than 1

is required. The PHY address can be written (after SMI communication at some address is established)

using the 10/100 Special Modes register (bits18.[4:0]).

The PHYAD0 hardware configuration pin is multiplexed with the RXER pin.

The LAN8720 may be configured to disregard the PHY address in SMI access write by setting the

5.3.9.2

Mode Bus – MODE[2:0]

The MODE[2:0] bus controls the configuration of the 10/100 digital block. When the nRST pin is

deasserted, the register bit values are loaded according to the MODE[2:0] pins. The 10/100 digital

block is then configured by the register bit values. When a soft reset occurs (bit 0.15) as described in

T a ble 5.21, the configuration of the 10/100 digital block is controlled by the register bit values, and the

MODE[2:0] pins have no affect.

The LAN8720 mode may be configured using hardware configuration as summarized in T a ble 5.39.

The user may configure the transceiver mode by writing the SMI registers.

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Table 5.39 MODE[2:0] Bus

DEFAULT REGISTER BIT VALUES

MODE[2:0]

MODE DEFINITIONS

[13,12,10,8]

[8,7,6,5]

000

001

010

10Base-T Half Duplex. Auto-negotiation disabled.

10Base-T Full Duplex. Auto-negotiation disabled.

0000

0001

1000

N/A

100Base-TX Half Duplex. Auto-negotiation

disabled.

CRS is active during Transmit & Receive.

011

100

100Base-TX Full Duplex. Auto-negotiation disabled.

CRS is active during Receive.

1001

1100

N/A

100Base-TX Half Duplex is advertised. Auto-

negotiation enabled.

CRS is active during Transmit & Receive.

0100

101

110

Repeater mode. Auto-negotiation enabled.

100Base-TX Half Duplex is advertised.

CRS is active during Receive.

1100

N/A

0100

N/A

Power Down mode. In this mode the transceiver will

wake-up in Power-Down mode. The transceiver

cannot be used when the MODE[2:0] bits are set to

this mode. To exit this mode, the MODE bits in

to some other value and a soft reset must be

issued.

111

All capable. Auto-negotiation enabled.

X10X

1111

The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in T a ble 5.40.

Table 5.40 Pin Names for Mode Bits

MODE BIT

PIN NAME

MODE[0]

MODE[1]

MODE[2]

RXD0/MODE0

RXD1/MODE1

CRS_DV/MODE2

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Chapter 6 AC Electrical Characteristics

The timing diagrams and limits in this section define the requirements placed on the external signals

of the Phy.

6.1

Serial Management Interface (SMI) Timing

The Serial Management Interface is used for status and control as described in Section 4.14.

T_1.1

Clock -

MDC

T_1.2

Data Out -

Valid Data

MDIO

(Read from PHY)

T_1.3

T_1.4

Valid Data

Data In -

MDIO

(Write to PHY)

Figure 6.1 SMI Timing Diagram

Table 6.1 SMI Timing Values

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

NOTES

T1.1

T1.2

MDC minimum cycle time

400

MDC to MDIO (Read from PHY)

delay

T1.3

T1.4

MDIO (Write to PHY) to MDC setup

MDIO (Write to PHY) to MDC hold

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6.2

RMII 10/100Base-TX/RX Timings (50MHz REF_CLK IN)

The 50MHz REF_CLK IN timing applies to the case when nINTSEL is floated or pulled-high on the

LAN8720. In this mode, a 50MHz clock must be provided to the LAN8720 CLKIN pin. For more

information on REF_CLK IN Mode, see Section 4.7.1.

6.2.1

RMII 100Base-T TX/RX Timings (50MHz REF_CLK IN)

6.2.1.1

100M RMII Receive Timing (50MHz REF_CLK IN)

Clock In -

CLKIN

T_6.1

Data Out -

RXD[1:0]

CRS_DV

Valid Data

Figure 6.2 100M RMII Receive Timing Diagram (50MHz REF_CLK IN)

Table 6.2 100M RMII Receive Timing Values (50MHz REF_CLK IN)

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

NOTES

T6.1

Output delay from rising edge of

CLKIN to receive signals output

valid

CLKIN frequency

MHz

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6.2.1.2

100M RMII Transmit Timing (50MHz REF_CLK IN)

Clock In -

CLKIN

T_8.1

T_8.2

Data In -

TXD[1:0]

TX_EN

Valid Data

Figure 6.3 100M RMII Transmit Timing Diagram (50MHz REF_CLK IN)

Table 6.3 100M RMII Transmit Timing Values (50MHz REF_CLK IN)

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

NOTES

T8.1

Transmit signals required setup to

rising edge of CLKIN

T8.2

Transmit signals required hold

after rising edge of CLKIN

CLKIN frequency

MHz

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6.2.2

RMII 10Base-T TX/RX Timings (50MHz REF_CLK IN)

6.2.2.1

10M RMII Receive Timing (50MHz REF_CLK IN)

Clock In -

CLKIN

T_9.1

Data Out -

RXD[1:0]

CRS_DV

Valid Data

Figure 6.4 10M RMII Receive Timing Diagram (50MHz REF_CLK IN)

Table 6.4 10M RMII Receive Timing Values (50MHz REF_CLK IN)

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

NOTES

T9.1

Output delay from rising edge of

CLKIN to receive signals output

valid

CLKIN frequency

MHz

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6.2.2.2

10M RMII Transmit Timing (50MHz REF_CLK IN)

Clock In -

CLKIN

T_10.1

T_10.2

Data In -

TXD[1:0]

TX_EN

Valid Data

Figure 6.5 10M RMII Transmit Timing Diagram (50MHz REF_CLK IN)

Table 6.5 10M RMII Transmit Timing Values (50MHz REF_CLK IN)

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

NOTES

T10.1

Transmit signals required setup to

rising edge of CLKIN

T10.2

Transmit signals required hold

after rising edge of CLKIN

CLKIN frequency

MHz

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6.3

RMII 10/100Base-TX/RX Timings (50MHz REF_CLK OUT)

The 50MHz REF_CLK OUT timing applies to the case when LED/nINTSEL is pulled-low on the

LAN8720. In this mode, a 25MHz crystal or clock oscillator must be provided to the LAN8720. For

more information on 50MHz REF_CLK OUT mode, see Section 4.7.2

6.3.1

RMII 100Base-T TX/RX Timings (50MHz REF_CLK OUT)

6.3.1.1

100M RMII Receive Timing (50MHz REF_CLK OUT)

REFCLKO

T_11.1

Data Out -

RXD[1:0]

CRS_DV

Valid Data

Figure 6.6 100M RMII Receive Timing Diagram (50MHz REF_CLK OUT)

Table 6.6 100M RMII Receive Timing Values (50MHz REF_CLK OUT)

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

NOTES

T11.1

Output delay from rising edge of

REFCLKO to receive signals

output valid

1.5

REFCLKO frequency

MHz

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6.3.1.2

100M RMII Transmit Timing (50MHz REF_CLK OUT)

REFCLKO

T_12.1T_12.2

Valid Data

Data In -

TXD[1:0]

TX_EN

Figure 6.7 100M RMII Transmit Timing Diagram (50MHz REF_CLK OUT)

Table 6.7 100M RMII Transmit Timing Values (50MHz REF_CLK OUT)

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

NOTES

T12.1

Transmit signals required setup to

rising edge of REFCLKO

T12.2

Transmit signals required hold

after rising edge of REFCLKO

2.5

REFCLKO frequency

MHz

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6.3.2

RMII 10Base-T TX/RX Timings (50MHz REF_CLK OUT)

6.3.2.1

10M RMII Receive Timing (50MHz REF_CLK OUT)

REFCLKO

T_13.1

Data Out -

RXD[1:0]

CRS_DV

Valid Data

Figure 6.8 10M RMII Receive Timing Diagram (50MHz REF_CLK OUT)

Table 6.8 10M RMII Receive Timing Values (50MHz REF_CLK OUT)

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

NOTES

T13.1

Output delay from rising edge of

REFCLKO to receive signals

output valid

1.5

REFCLKO frequency

MHz

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6.3.2.2

10M RMII Transmit Timing (50MHz REF_CLK OUT)

REFCLKO

T_14.1

T_14.2

Data In -

TXD[1:0]

TX_EN

Valid Data

Figure 6.9 10M RMII Transmit Timing Diagram (50MHz REF_CLK OUT)

Table 6.9 10M RMII Transmit Timing Values (50MHz REF_CLK OUT)

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNITS

NOTES

T14.1

Transmit signals required setup to

rising edge of REFCLKO

T14.2

Transmit signals required hold

after rising edge of REFCLKO

2.5

CLKIN frequency

MHz

6.4

RMII CLKIN Requirements

Table 6.10 RMII CLKIN (REF_CLK) Timing Values

PARAMETER

DESCRIPTION

CLKIN frequency

MIN

TYP

MAX

UNITS

MHz

ppm

NOTES

CLKIN Frequency Drift

CLKIN Duty Cycle

CLKIN Jitter

± 50

150

psec

p-p – not RMS

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6.5

Reset Timing

T_11.1

nRST

T_11.2

T_11.3

Configuration

Signals

T_11.4

Output drive

Figure 6.10 Reset Timing Diagram

Table 6.11 Reset Timing Values

PARAMETER

DESCRIPTION

Reset Pulse Width

MIN

TYP

MAX

UNITS

NOTES

T11.1

T11.2

100

200

Configuration input setup to

nRST rising

T11.3

T11.4

Configuration input hold after

nRST rising

Output Drive after nRST rising

800

20 clock cycles for

25 MHz clock

40 clock cycles for

50MHz clock

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6.6

Clock Circuit

LAN8720/LAN8720i can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator

(±50ppm) input. If the single-ended clock oscillator method is implemented, XTAL2 should be left

unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. See T a ble 6.12

for the recommended crystal specifications.

Table 6.12 LAN8720/LAN8720i Crystal Specifications

PARAMETER

SYMBOL

MIN

NOM

AT, typ

Fundamental Mode

Parallel Resonant Mode

MAX

UNITS

NOTES

Crystal Cut

Crystal Oscillation Mode

Crystal Calibration Mode

Frequency

25.000

MHz

PPM

fund

Frequency Tolerance @ 25 C

Frequency Stability Over Temp

Frequency Deviation Over Time

Total Allowable PPM Budget

Shunt Capacitance

±50

Note 6.1

Note 6.2

Note 6.3

tol

±50

temp

+/-3 to 5

age

±50

7 typ

Load Capacitance

20 typ

Drive Level

300

Equivalent Series Resistance

Operating Temperature Range

Note 6.5

Ohm

Note 6.4

LAN8720/LAN8720i

XTAL1/CLKIN Pin Capacitance

3 typ

Note 6.6

LAN8720/LAN8720i XTAL2 Pin

Capacitance

3 typ

Note 6.1 The maximum allowable values for Frequency Tolerance and Frequency Stability are

application dependant. Since any particular application must meet the IEEE ±50 PPM Total

PPM Budget, the combination of these two values must be approximately ±45 PPM

(allowing for aging).

Note 6.2 Frequency Deviation Over Time is also referred to as Aging.

Note 6.3 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as

±100 PPM.

Note 6.4 0 C for extended commercial version, -40 C for industrial version.

Note 6.5 +85 C for extended commercial version, +85 C for industrial version.

Note 6.6 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not

included in this value. The XTAL1/CLKIN pin, XTAL2 pin and PCB capacitance values are

required to accurately calculate the value of the two external load capacitors. The total load

capacitance must be equivalent to what the crystal expects to see in the circuit so that the

crystal oscillator will operate at 25.000 MHz.

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Chapter 7 DC Electrical Characteristics

7.1

DC Characteristics

7.1.1

Maximum Guaranteed Ratings

Stresses beyond those listed in may cause permanent damage to the device. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Table 7.1 Maximum Conditions

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

COMMENT

VDD1A,

VDD2A,

VDDIO

Power pins to all other pins. -0.5

+3.6

Digital IO

VSS

To VSS ground

-0.5

+3.6

+0.5

59.8

T a ble 7.6

VSS to all other pins

Junction to

Ambient (θ

Thermal vias per Layout

Guidelines.

°C/W

)

Junction to

12.6

+85

°C/W

Case (θ

)

Operating

Temperature

LAN8720-AEZG

LAN8720i-AEZG

Extended commercial

temperature components.

Operating

Temperature

-40

-55

+85

Industrial temperature

components.

Storage

Temperature

+150

Table 7.2 ESD and LATCH-UP Performance

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

COMMENTS

ESD PERFORMANCE

All Pins

System

Human Body Model

±5

Device

IED61000-4-2 Contact Discharge

IEC61000-4-2 Air-gap Discharge

±15

3rd party system test

LATCH-UP PERFORMANCE

150

All Pins

EIA/JESD 78, Class II

7.1.1.1

Human Body Model (HBM) Performance

HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and

manufacturing, and is done without power applied to the IC. To pass the test, the device must have

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no change in operation or performance due to the event. All pins on the LAN8720 provide +/-5kV HBM

protection.

7.1.1.2

IEC61000-4-2 Performance

The IEC61000-4-2 ESD specification is an international standard that addresses system-level immunity

to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed

at the device level with the device powered down.

SMSC contracts with Independent laboratories to test the LAN8720 to IEC61000-4-2 in a working

system. Reports are available upon request. Please contact your SMSC representative, and request

information on 3rd party ESD test results. The reports show that systems designed with the LAN8720

can safely dissipate ±15kV air discharges and ±15kV contact discharges per the IEC61000-4-2

specification without additional board level protection.

In addition to defining the ESD tests, IEC 61000-4-2 also categorizes the impact to equipment

operation when the strike occurs (ESD Result Classification). The LAN8720 maintains an ESD Result

Classification 1 or 2 when subjected to an IEC 61000-4-2 (level 4) ESD strike.

Both air discharge and contact discharge test techniques for applying stress conditions are defined by

the IEC61000-4-2 ESD document.

AIR DISCHARGE

To perform this test, a charged electrode is moved close to the system being tested until a spark is

generated. This test is difficult to reproduce because the discharge is influenced by such factors as

humidity, the speed of approach of the electrode, and construction of the test equipment.

CONTACT DISCHARGE

The uncharged electrode first contacts the pin to prepare this test, and then the probe tip is energized.

This yields more repeatable results, and is the preferred test method. The independent test laboratories

contracted by SMSC provide test results for both types of discharge methods.

7.1.2

Operating Conditions

Table 7.3 Recommended Operating Conditions

PARAMETER

CONDITIONS

MIN

TYP

MAX

3.6

UNITS

COMMENT

VDD1A, VDD2A

VDDIO

To VSS ground

3.0

1.6

0.0

3.3

3.6

Input Voltage on

Digital Pins

VDDIO

Voltage on Analog I/O

pins (RXP, RXN)

0.0

+3.6V

+85

Ambient Temperature

T LAN8720-AEZG

For Extended Commercial

Temperature

T LAN8720i-AEZG

-40

+85

For Industrial Temperature

7.1.3

Power Consumption

7.1.3.1

Power Consumption Device Only REF_CLK IN Mode

Power measurements taken over the operating conditions specified. See Section 5.3.5 for a description

of the power down modes. For more information on REF_CLK IN Mode, see Section 4.7.1.

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Table 7.4 Power Consumption Device Only (REF_CLK IN MODE)

VDDA3.3

POWER

PINS(MA)

VDDCR

POWER

PIN(MA)

VDDIO

POWER

PIN(MA)

TOTAL

CURRENT

(MA)

TOTAL

POWER

(MW)

POWER PIN GROUP

Max

Typical

Min

27.1

25.7

22.4

20.4

18.5

17.4

0.6

0.5

0.3

48.1

44.7

40.1

158.7

147.5

100BASE-T /W TRAFFIC

95.3

Max

Typical

Min

9.7

8.9

8.3

0.6

0.5

0.3

23.3

21.2

19.7

76.9

11.8

11.1

10BASE-T /W TRAFFIC

41.3

Max

Typical

Min

4.2

4.1

3.9

0.2

7.4

6.2

5.8

24.4

20.4

ENERGY DETECT POWER

DOWN

1.9

15.2

Max

Typical

Min

0.4

0.3

2.8

1.8

1.7

0.2

3.4

2.3

11.2

7.6

GENERAL POWER DOWN

Note: The current at VDDCR is either supplied by the internal regulator from current entering at

VDD2A, or from an external 1.2V supply when the internal regulator is disabled.

Note 7.1 This is calculated with full flexPWR features activated: VDDIO = 1.8V and internal regulator

disabled.

Note 7.2 Current measurements do not include power applied to the magnetics or the optional

external LEDs.

7.1.3.2

Power Consumption Device Only 50MHz REF_CLK OUT Mode

Power measurements taken over the operating conditions specified. See Section 5.3.5 for a description

of the power down modes. For more information on 50MHz REF_CLK OUT mode, see Section 4.7.2

Table 7.5 Power Consumption Device Only (50MHz REF_CLK OUT MODE)

VDDA3.3

POWER

PINS(MA)

VDDCR

POWER

PIN(MA)

VDDIO

POWER

PIN(MA)

TOTAL

CURRENT

(MA)

TOTAL

POWER

(MW)

POWER PIN GROUP

Max

Typical

Min

27.7

25.8

21.2

6.3

5.8

2.9

178.2

164

18.1

14.1

49.7

38.2

100BASE-T /W TRAFFIC

92.1

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Table 7.5 Power Consumption Device Only (50MHz REF_CLK OUT MODE)

Max

Typical

Min

9.9

8.8

7.1

12.8

11.3

9.7

6.4

5.6

29.1

25.7

19.8

84.8

10BASE-T /W TRAFFIC

40.5

Max

Typical

Min

4.5

2.7

1.5

1.2

0.3

0.2

7.5

5.7

5.1

24.8

18.8

ENERGY DETECT POWER

DOWN

3.9

14.3

Max

Typical

Min

0.4

2.5

1.3

0.2

3.1

1.9

1.4

10.2

6.3

GENERAL POWER DOWN

2.5