LAN9500/LAN9500i
Hi-Speed USB 2.0 to 10/100
Ethernet Controller
Datasheet
PRODUCT FEATURES
Highlights
—
—
—
—
—
—
Preamble generation and removal
Automatic 32-bit CRC generation and checking
Automatic payload padding and pad removal
Loop-back modes
TCP/UDP/IP/ICMP checksum offload support
Flexible address filtering modes
„
„
„
Single Chip Hi-Speed USB 2.0 to 10/100 Ethernet
Controller
Integrated 10/100 Ethernet MAC with Full-Duplex
Support
Integrated 10/100 Ethernet PHY with HP Auto-MDIX
support
–
–
–
–
–
–
One 48-bit perfect address
64 hash-filtered multicast addresses
Pass all multicast
Promiscuous mode
Inverse filtering
„
„
„
Integrated USB 2.0 Hi-Speed Device Controller
Integrated USB 2.0 Hi-Speed PHY
Implements Reduced Power Operating Modes
Pass all incoming with status report
—
—
Wakeup packet support
Integrated Ethernet PHY
–
–
–
–
Auto-negotiation
Automatic polarity detection and correction
HP Auto-MDIX support
Target Applications
„
„
„
„
„
„
„
„
„
Embedded Systems
Set-Top Boxes
Link status change wake-up detection
—
—
Support for 3 status LEDs
External MII and Turbo MII support HomePNA™ and
HomePlug® PHY
PVR’s
CE Devices
Networked Printers
USB Port Replicators
Standalone USB to Ethernet Dongles
Test Instrumentation
Industrial
„
Power and I/Os
—
—
—
—
—
Various low power modes
11 GPIOs
Supports bus-powered and self-powered operation
Integrated power-on reset circuit
External 3.3v I/O supply
–
Internal 1.8v core supply regulator
„
„
Miscellaneous Features
—
—
—
EEPROM Controller
IEEE 1149.1 (JTAG) Boundary Scan
Requires single 25 MHz crystal
Key Benefits
USB Device Controller
„
—
Fully compliant with Hi-Speed Universal Serial Bus
Software
Specification Revision 2.0
—
—
—
—
—
Windows XP/Vista Driver
Linux Driver
Win CE Driver
MAC OS Driver
EEPROM Utility
—
—
—
—
—
Supports HS (480 Mbps) and FS (12 Mbps) modes
Four endpoints supported
Supports vendor specific commands
Integrated USB 2.0 PHY
Remote wakeup supported
„
„
Packaging
„
High-Performance 10/100 Ethernet Controller
—
56-pin QFN (8x8 mm) Lead-Free RoHS Compliant
—
—
—
—
—
Fully compliant with IEEE802.3/802.3u
Integrated Ethernet MAC and PHY
10BASE-T and 100BASE-TX support
Full- and half-duplex support
package
Environmental
—
Commercial Temperature Range (0°C to +70°C)
—
Industrial Temperature Range (-40°C to +85°C)
Full- and half-duplex flow control
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Datasheet
Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ethernet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
EEPROM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 3 EEPROM Controller (EPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 4 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Equivalent Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reset and Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Turbo MII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 5 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 6 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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List of Figures
Figure 1.1 LAN9500/LAN9500i System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW). . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 4.2 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 4.3 nRESET Reset Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 4.4 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 4.1 Turbo MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 4.2 Turbo MII Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 5.1 LAN9500/LAN9500i 56-QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 5.2 LAN9500/LAN9500i 56-QFN Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . 41
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List Of Tables
Table 2.1 MII Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2.2 EEPROM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2.3 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2.4 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.5 USB Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2.6 Ethernet PHY Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2.8 No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2.9 56-QFN Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2.10 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3.1 EEPROM Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3.2 Configuration Flags Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3.3 EEPROM Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3.4 Dump of EEPROM Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3.5 EEPROM Example - 256 Byte EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4.1 SUSPEND0 - Supply and Current @3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4.2 SUSPEND1 - Supply and Current @3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4.3 SUSPEND2 - Supply and Current @3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4.4 Operational Power Consumption - Supply and Current @3.3V. . . . . . . . . . . . . . . . . . . . . . . . 30
Table 4.6 I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 4.7 100BASE-TX Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4.8 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4.9 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 4.10 nRESET Reset Pin Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5.1 LAN9500/LAN9500i 56-QFN Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 6.2 Datasheet Revision History (INTERNAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Chapter 1 Introduction
1.1
Block Diagram
USB 2.0
Device
Controller
10/100
Ethernet
MAC
USB
USB
PHY
FIFO
Controller
Ethernet
PHY
Ethernet
MII: To optional
external PHY
JTAG
TAP
Controller
EEPROM
EEPROM
Controller
SRAM
LAN9500/LAN9500i
Figure 1.1 LAN9500/LAN9500i System Diagram
1.1.1
Overview
The LAN9500/LAN9500i is a high performance Hi-Speed USB 2.0 to 10/100 Ethernet controller. With
applications ranging from embedded systems, set-top boxes, and PVR’s, to USB port replicators, USB
to Ethernet dongles, and test instrumentation, the LAN9500/LAN9500i is a high performance and cost
competitive USB to Ethernet connectivity solution.
The LAN9500/LAN9500i contains an integrated 10/100 Ethernet PHY, USB PHY, Hi-Speed USB 2.0
device controller, 10/100 Ethernet MAC, TAP controller, EEPROM controller, and a FIFO controller with
a total of 30 KB of internal packet buffering.
The internal USB 2.0 device controller and USB PHY are compliant with the USB 2.0 Hi-Speed
standard. The LAN9500/LAN9500i implements Control, Interrupt, Bulk-in, and Bulk-out USB Endpoints.
The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX, and is
compliant with the IEEE 802.3 and IEEE 802.3u standards. An external MII interface provides support
for an external Fast Ethernet PHY, HomePNA, and HomePlug functionality.
Multiple power management features are provided, including various low power modes and "Magic
Packet", "Wake On LAN", and "Link Status Change" wake events. These wake events can be
programmed to initiate a USB remote wakeup.
An internal EEPROM controller exists to load various USB configuration information and the device
MAC address. The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
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1.1.2
USB
The USB portion of the LAN9500/LAN9500i integrates a Hi-Speed USB 2.0 device controller and USB
PHY.
The USB device controller contains a USB low-level protocol interpreter which implements the USB
bus protocol, packet generation/extraction, PID/Device ID parsing, and CRC coding/decoding, with
autonomous error handling. The USB device controller is capable of operating in USB 2.0 Hi-Speed
and Full-Speed compliant modes and contains autonomous protocol handling functions such as
handling of suspend/resume/reset conditions, remote wakeup, and stall condition clearing on Setup
packets. The USB device controller also autonomously handles error conditions such as retry for CRC
and data toggle errors, and generates NYET, STALL, ACK and NACK handshake responses,
depending on the endpoint buffer status.
The LAN9500/LAN9500i implements four USB endpoints: Control, Interrupt, Bulk-in, and Bulk-out. The
Bulk-in and Bulk-out Endpoints allow for Ethernet reception and transmission respectively.
Implementation of vendor-specific commands allows for efficient statistics gathering and access to the
LAN9500/LAN9500i system control and status registers.
1.1.3
1.1.4
FIFO Controller
The FIFO controller uses an internal SRAM to buffer RX and TX traffic. Bulk-out packets from the USB
controller are directly stored into the TX buffer. Ethernet Frames are directly stored into the RX buffer
and become the basis for bulk-in packets.
Ethernet
The LAN9500/LAN9500i integrates an IEEE 802.3 PHY for twisted pair Ethernet applications and a
10/100 Ethernet Media Access Controller (MAC).
The PHY can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet
operation in either full- or half-duplex configurations and includes auto-negotiation, auto-polarity
correction, and Auto-MDIX. Minimal external components are required for the utilization of the
Integrated PHY.
Optionally, an external PHY may be used via the MII (Media Independent Interface) port, effectively
bypassing the internal PHY. This option allows support for HomePNA and HomePlug applications.
The Ethernet MAC/PHY supports numerous power management wakeup features, including “Magic
Packet”, “Wake on LAN”, and “Link Status Change”.
1.1.5
Power Management
The LAN9500/LAN9500i features three variations of USB suspend: SUSPEND0, SUSPEND1, and
SUSPEND2. These modes allow the application to select the ideal balance of remote wakeup
functionality and power consumption.
„
„
„
SUSPEND0: Supports GPIO, “Wake On LAN”, and “Magic Packet” remote wakeup events. This
suspend state reduces power by stopping the clocks of the MAC and other internal modules.
SUSPEND1: Supports GPIO and “Link Status Change” for remote wakeup events. This suspend
state consumes less power than SUSPEND0.
SUSPEND2: Supports only GPIO assertion for a remote wakeup event. This suspend state
consumes less than 1 mA. This is the default suspend mode for the LAN9500/LAN9500i.
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1.1.6
1.1.7
EEPROM Controller
The LAN9500/LAN9500i contains an EEPROM controller for connection to an external EEPROM. This
allows for the automatic loading of static configuration data upon power-on reset, pin reset, or software
reset. The EEPROM can be configured to load USB descriptors, USB device configuration, and MAC
address.
General Purpose I/O
When configured for internal PHY mode, up to eleven GPIOs are supported. All GPIOs can serve as
remote wakeup events when the LAN9500/LAN9500i is in a suspended state.
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Chapter 2 Pin Description and Configuration
43
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TXEN
nSPD_LED/GPIO10
nLNKA_LED/GPIO9
nFDX_LED/GPIO8
VDD33IO
44
RXER
45
CRS/GPIO3
SMSC
LAN9500/LAN9500i
46
COL/GPIO0
56 PIN QFN
47
TXCLK
nRESET
(TOP VIEW)
48
VDD33IO
MDIO/GPIO1
MDC/GPIO2
VDD18CORE
VBUS_DET
XO
49
TEST1
VSS
50
VDD18CORE
51
VDD33IO
52
VDD33IO
53
TXD3/GPIO7/EEP_SIZE
XI
54
TXD2/GPIO6/PORT_SWAP
VDD18USBPLL
USBRBIAS
VDD33A
55
TXD1/GPIO5/RMT_WKP
56
TXD0/GPIO4/EEP_DISABLE
NOTE: When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW)
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Table 2.1 MII Interface Pins
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
Receive Error
(External
PHY Mode)
RXER
IS
(PD)
Receive Error: In external PHY mode, the signal
on this pin is input from the external PHY and
indicates a receive error in the packet. In internal
PHY mode, this pin is not used.
1
Transmit
Enable
(External
PHY Mode)
TXEN
O8
(PD)
Transmit Enable: In external PHY mode, this pin
output to the external PHY and indicates valid
data on TXD[3:0]. In internal PHY mode, this pin
is not used.
1
1
1
Receive Data
Valid
(External
RXDV
IS
(PD)
Receive Data Valid: In external PHY mode, the
signal on this pin is input from the external PHY
and indicates valid data on RXD[3:0]. In internal
PHY mode, this pin is not used.
PHY Mode)
Receive
Clock
(External
PHY Mode)
RXCLK
IS
(PD)
Receive Clock: In external PHY mode, this pin
is the receiver clock input from the external PHY.
In internal PHY mode, this pin is not used.
Carrier Sense
(External
PHY Mode)
CRS
IS
(PD)
Carrier Sense: In external PHY mode, the signal
on this pin is input from the external PHY and
indicates a network carrier.
1
General
GPIO3
IS/O8/
OD8
(PU)
General Purpose I/O 3
Purpose I/O 3
(Internal PHY
Mode Only)
MII Collision
Detect
(External
COL
GPIO0
MDIO
GPIO1
MDC
IS
(PD)
MII Collision Detect: In external PHY mode, the
signal on this pin is input from the external PHY
and indicates a collision event.
PHY Mode)
1
General
IS/O8/
OD8
(PU)
General Purpose I/O 0
Purpose I/O 0
(Internal PHY
Mode Only)
Management
Data
(External
PHY Mode)
IS/O8
(PD)
Management Data: In external PHY mode, this
pin provides the management data to/from the
external PHY.
1
General
IS/O8/
OD8
(PU)
General Purpose I/O 1
Purpose I/O 1
(Internal PHY
Mode Only)
Management
Clock
(External
PHY Mode)
O8
(PD)
Management Clock: In external PHY mode, this
pin outputs the management clock to the external
PHY.
1
General
GPIO2
IS/O8/
OD8
(PU)
General Purpose I/O 2
Purpose I/O 2
(Internal PHY
Mode Only)
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Table 2.1 MII Interface Pins (continued)
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
TransmitData
3
(External
PHY Mode)
TXD3
O8
(PU)
Transmit Data 3: In external PHY mode, this pin
functions as the transmit data 3 output to the
external PHY.
General
GPIO7
IS/O8/
OD8
(PU)
General Purpose I/O 7
Purpose I/O 7
(Internal PHY
Mode Only)
EEPROM
Size
Configuration
EEP_SIZE
IS
(PU)
EEPROM SIZE: The EEP_SIZE strap selects the
size of the EEPROM attached to the
LAN9500/LAN9500i.
1
Strap
0 = 128 byte EEPROM is attached and a total of
seven address bits are used.
1 = 256/512 byte EEPROM is attached and a
total of nine address bits are used.
Note:
A 3-wire style 1K/2K/4K EEPROM that
is organized for 128 x 8-bit or 256/512 x
8-bit operation must be used.
configuration straps.
TransmitData
2
(External
PHY Mode)
TXD2
GPIO6
O8
(PD)
Transmit Data 2: In external PHY mode, this pin
functions as the transmit data 2 output to the
external PHY.
General
IS/O8/
OD8
(PU)
General Purpose I/O 6
Purpose I/O 6
(Internal PHY
Mode Only)
1
USB Port
Swap
PORT_SWAP
IS
(PD)
USB Port Swap Configuration Strap: Swaps
the mapping of USBDP and USBDM.
Configuration
Strap
0 = USBDP maps to the USB D+ line and
USBDM maps to the USB D- line.
1 = USBDP maps to the USB D- line. USBDM
maps to the USB D+ line.
configuration straps.
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Table 2.1 MII Interface Pins (continued)
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
TransmitData
1
TXD1
O8
(PD)
Transmit Data 1: In external PHY mode, this pin
functions as the transmit data 1 output to the
external PHY.
(External
PHY Mode)
General
GPIO5
IS/O8/
OD8
(PU)
General Purpose I/O 5
Purpose I/O 5
(Internal PHY
Mode Only)
1
Remote
Wakeup
Configuration
Strap
RMT_WKP
IS
(PD)
Remote Wakeup Configuration Strap: This
strap configures the default descriptor values to
support remote wakeup.
0 = Remote wakeup is not supported.
1 = Remote wakeup is supported.
configuration straps.
TransmitData
0
(External
PHY Mode)
TXD0
GPIO4
O8
(PD)
Transmit Data 0: In external PHY mode, this pin
functions as the transmit data 0 output to the
external PHY.
General
IS/O8/
OD8
(PU)
General Purpose I/O 4
Purpose I/O 4
(Internal PHY
Mode Only)
1
EEPROM
Disable
Configuration
Strap
EEP_DISABLE
IS
(PD)
EEPROM Disable Configuration Strap: This
strap disables the autoloading of the EEPROM
contents. The assertion of this strap does not
prevent register access to the EEPROM.
0 = EEPROM is recognized if present.
1 = EEPROM is not recognized even if it is
present.
configuration straps.
Transmit
Clock
(External
TXCLK
IS
(PU)
Transmit Clock: In external PHY mode, this pin
is the transmitter clock input from the external
PHY. In internal PHY mode, this pin is not used.
1
PHY Mode)
Note 2.1 Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
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Table 2.2 EEPROM Pins
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
EEPROM
Data In
EEDI
EEDO
IS
(PD)
EEPROM Data In: This pin is driven by the
1
EEDO output of the external EEPROM.
EEPROM
Data Out
O8
(PU)
EEPROM Data Out: This pin drives the EEDI
input of the external EEPROM.
Auto-MDIX
Enable
AUTOMDIX_EN
IS
(PU)
Auto-MDIX Enable Configuration Strap:
Determines the default Auto-MDIX setting.
Configuration
0 = Auto-MDIX is disabled.
1 = Auto-MDIX is enabled.
Strap
1
1
configuration straps.
EEPROM
Chip Select
EECS
EECLK
O8
EEPROM chip select: This pin drives the chip
select output of the external EEPROM.
EEPROM
Clock
O8
(PD)
EEPROM Clock: This pin drives the EEPROM
clock of the external EEPROM.
Power Select
Configuration
Strap
PWR_SEL
IS
(PD)
Power Select Configuration Strap: Determines
the default power setting when no EEPROM is
present.
1
0 = The LAN9500/LAN9500i is bus powered.
1 = The LAN9500/LAN9500i is self powered.
configuration straps.
Note 2.2 Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
Table 2.3 JTAG Pins
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
JTAG Test
Port Reset
(Internal PHY
Mode)
nTRST
IS
(PU)
JTAG Test Port Reset (Active-Low): In internal
PHY mode, this pin functions as the JTAG test
port reset input.
1
Receive Data
0
(External
PHY Mode)
RXD0
TDO
IS
(PD)
Receive Data 0: In external PHY mode, this pin
functions as the receive data 0 input from the
external PHY.
JTAG Test
Data Out
(Internal PHY
Mode)
O8
O8
JTAG Data Output: In internal PHY mode, this
pin functions as the JTAG data output.
1
PHY Reset
(External
nPHY_RST
PHY Reset (Active-Low): In external PHY
mode, this pin functions as the PHY reset output.
PHY Mode)
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Table 2.3 JTAG Pins (continued)
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
JTAG Test
Clock
(Internal PHY
TCK
RXD1
TMS
IS
(PU)
JTAG Test Clock: In internal PHY mode, this pin
functions as the JTAG test clock. The maximum
operating frequency of this clock is 25MHz.
Mode)
1
Receive Data
1
(External
PHY Mode)
IS
(PD)
Receive Data 1: In external PHY mode, this
signal functions as the receive data 1 input from
the external PHY.
JTAG Test
Mode Select
(Internal PHY
Mode)
IS
(PU)
JTAG Test Mode Select: In internal PHY mode,
this pin functions as the JTAG test mode select.
1
Receive Data
2
(External
RXD2
TDI
IS
(PD)
Receive Data 2: In external PHY mode, this
signal functions as the receive data 2 input from
the external PHY.
PHY Mode)
JTAG Test
Data Input
(Internal PHY
Mode)
IS
(PU)
JTAG Data Input: When in internal PHY mode,
this pin functions as the JTAG data input.
1
Receive Data
3
(External
PHY Mode)
RXD3
IS
(PD)
Receive Data 3: In external PHY mode, this pin
functions as the receive data 3 input from the
external PHY.
Table 2.4 Miscellaneous Pins
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
PHY Select
PHY_SEL
IS
(PD)
PHY Select: Selects whether to use the internal
Ethernet PHY or the external PHY connected to
the MII port.
1
0 = Internal PHY is used.
1 = External PHY is used.
System Reset
nRESET
IS
(PU)
System Reset (Active-Low)
1
1
Ethernet
Full-Duplex
Indicator LED
nFDX_LED
OD12
(PU)
Ethernet Full-Duplex Indicator LED (Active-
Low): This signal is driven low (LED on) when
the Ethernet link is operating in full-duplex mode.
General
Purpose I/O 8
GPIO8
IS/O12/
OD12
(PU)
General Purpose I/O 8
Note:
By default this pin is configured as a
GPIO.
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Table 2.4 Miscellaneous Pins (continued)
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
Ethernet Link
Activity
Indicator LED
nLNKA_LED
OD12
(PU)
Ethernet Link Activity Indicator LED (Active-
Low): This signal is driven low (LED on) when a
valid link is detected. This pin is pulsed high (LED
off) for 80mS whenever transmit or receive
activity is detected. This pin is then driven low
again for a minimum of 80mS, after which time it
will repeat the process if TX or RX activity is
detected. Effectively, LED2 is activated solid for a
link. When transmit or receive activity is sensed,
LED2 will function as an activity indicator.
1
General
Purpose I/O 9
GPIO9
IS/O12/
OD12
(PU)
General Purpose I/O 9
Note:
By default this pin is configured as a
GPIO.
Ethernet
Speed
Indicator LED
nSPD_LED
OD12
(PU)
Ethernet Speed Indicator LED (Active-Low):
This pin is driven low (LED on) when the Ethernet
operating speed is 100Mbs, or during auto-
negotiation. This pin is driven high during 10Mbs
operation, or during line isolation.
1
1
General
Purpose I/O
10
GPIO10
IS/O12/
OD12
(PU)
General Purpose I/O 10
Note:
By default this pin is configured as a
GPIO.
Detect
VBUS_DET
IS_5V
(PD)
Detect Upstream VBUS Power: Detects state of
upstream bus power. This pin must be tied to
VDD33IO when operating in bus powered mode.
Upstream
VBUS Power
Test 1
Test 2
Test 3
TEST1
TEST2
TEST3
-
-
-
Test 1: This pin must always be connected to
1
1
1
VDD33IO for proper operation.
Test 2: This pin must always be connected to
VSS for proper operation.
Test 3: This pin must always be connected to
VSS for proper operation.
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Table 2.5 USB Pins
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
USB
DMINUS
USBDM
AIO
AIO
USB DMINUS
Note:
The functionality of this pin may be
swapped to USB DPLUS via the
PORT_SWAP configuration strap.
1
USB
DPLUS
USBDP
USB DPLUS
Note: The functionality of this pin may be
1
1
1
swapped to USB DMINUS via the
PORT_SWAP configuration strap.
External USB
Bias Resistor.
USBRBIAS
AI
P
External USB Bias Resistor: Used for setting
HS transmit current level and on-chip termination
impedance. Connect to an external 12K 1.0%
resistor to ground.
USB PLL
+1.8V Supply
VDD18USBPLL
USB PLL +1.8V Supply: This pin must be
connected to VDD18CORE for proper operation.
Refer to the LAN9500/LAN9500i reference
schematic for additional connection information.
Crystal Input
XI
ICLK
Crystal Input: External 25 MHz crystal input.
Note:
This signal can also be driven by a
single-ended clock oscillator. When this
method is used, XO should be left
unconnected
1
1
Crystal
Output
XO
OCLK
Crystal Output: External 25 MHz crystal output.
Table 2.6 Ethernet PHY Pins
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
Ethernet TX
Data Out
Negative
TXN
TXP
RXN
RXP
AIO
Ethernet Transmit Data Out Negative: The
transmit data outputs may be swapped internally
with receive data inputs when Auto-MDIX is
enabled.
1
Ethernet TX
Data Out
Positive
AIO
AIO
AIO
Ethernet Transmit Data Out Positive: The
transmit data outputs may be swapped internally
with receive data inputs when Auto-MDIX is
enabled.
1
1
1
Ethernet RX
Data In
Negative
Ethernet Receive Data In Negative: The
receive data inputs may be swapped internally
with transmit data outputs when Auto-MDIX is
enabled.
Ethernet RX
Data In
Positive
Ethernet Receive Data In Positive: The receive
data inputs may be swapped internally with
transmit data outputs when Auto-MDIX is
enabled.
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Table 2.6 Ethernet PHY Pins (continued)
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
PHY Interrupt
(Internal PHY
Mode)
nPHY_INT
O8
PHY Interrupt (Active-Low): In internal PHY
mode, this signal can be configured to output the
internal PHY interrupt signal.
Note:
The internal PHY interrupt signal is
active-high.
1
PHY Interrupt
(External
PHY Mode)
nPHY_INT
VDD33A
IS
(PU)
PHY Interrupt (Active-Low): In external PHY
mode, the signal on this pin is input from the
external PHY and indicates a PHY interrupt has
occurred.
+3.3V Analog
Power Supply
P
+3.3V Analog Power Supply
4
1
Refer to the LAN9500/LAN9500i reference
schematic for connection information.
External PHY
Bias Resistor
EXRES
AI
P
External PHY Bias Resistor: Used for the
internal bias circuits. Connect to an external
12.4K 1.0% resistor to ground.
Ethernet PLL
+1.8V Power
Supply
VDD18PLL
Ethernet PLL +1.8V Power Supply: This pin
must be connected to VDD18CORE for proper
operation.
1
Refer to the LAN9500/LAN9500i reference
schematic for additional connection information.
Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
+3.3V I/O
Power
VDD33IO
P
+3.3V Power Supply for I/O Pins
5
Refer to the LAN9500/LAN9500i reference
schematic for connection information.
Digital Core
+1.8V Power
Supply
VDD18CORE
VSS
P
P
Digital Core +1.8V Power Supply Output
2
Refer to the LAN9500/LAN9500i reference
schematic for connection information.
Output
Exposed
pad on
Ground
Common Ground
package
bottom
Table 2.8 No-Connect Pins
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
No Connect
NC
-
No Connect: These pins must be left floating for
normal device operation
1
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Table 2.9 56-QFN Package Pin Assignments
PIN
NUM
PIN
NUM
PIN
NUM
PIN
NUM
PIN NAME
PIN NAME
PIN NAME
PIN NAME
1
nPHY_INT
15
VDD33A
29
EECLK/
PWR_SEL
43
TXEN
2
3
TXN
TXP
16
17
USBRBIAS
30
31
EECS
44
45
RXER
VDD18USBPLL
EEDO/
AUTOMDIX_EN
CRS/GPIO3
4
5
VDD33A
RXN
18
19
XI
32
33
EEDI
46
47
COL/GPIO0
TXCLK
XO
TEST3
6
7
RXP
20
21
VBUS_DET
34
35
PHY_SEL
VDD33IO
48
49
VDD33IO
TEST1
VDD33A
VDD18CORE
8
9
EXRES
22
23
MDC/GPIO2
MDIO/GPIO1
36
37
nTRST/RXD0
50
51
VDD18CORE
VDD33IO
VDD33A
TDO/nPHY_RST
10
11
VDD18PLL
USBDM
24
25
nRESET
38
39
TCK/RXD1
TMS/RXD2
52
53
VDD33IO
VDD33IO
TXD3/GPIO7/
EEP_SIZE
12
13
14
USBDP
TEST2
NC
26
27
28
nFDX_LED/
GPIO8
40
41
42
TDI/RXD3
RXCLK
RXDV
54
55
56
TXD2/GPIO6/
PORT_SWAP
nLNKA_LED/
GPIO9
TXD1/GPIO5/
RMT_WKP
nSPD_LED/
GPIO10
TXD0/GPIO4/
EEP_DISABLE
EXPOSED PAD
MUST BE CONNECTED TO VSS
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2.1
Buffer Types
Table 2.10 Buffer Types
DESCRIPTION
BUFFER TYPE
IS
IS_5V
O8
Schmitt-triggered Input
5V Tolerant Schmitt-triggered Input
Output with 8mA sink and 8mA source
Open-drain output with 8mA sink
OD8
O12
OD12
PU
Output with 12mA sink and 12mA source
Open-drain output with 12mA sink
50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Note:
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the LAN9500/LAN9500i. When
connected to a load that must be pulled high, an external resistor must be added.
PD
50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Note:
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the LAN9500/LAN9500i. When
connected to a load that must be pulled low, an external resistor must be added.
AI
AIO
ICLK
OCLK
P
Analog input
Analog bi-directional
Crystal oscillator input pin
Crystal oscillator output pin
Power pin
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Chapter 3 EEPROM Controller (EPC)
LAN9500/LAN9500i may use an external EEPROM to store the default values for the USB descriptors
and the MAC address. The EEPROM controller supports most “93C46” type EEPROMs. The
EEP_SIZE strap selects the size of the EEPROM attached to LAN9500/LAN9500i. When this strap is
set to “0”, a 128 byte EEPROM is attached and a total of seven address bits are used. When this strap
is set to “1” a 256/512 byte EEPROM is attached and a total of nine address bits are used.
Note: A 3-wire style 1K/2K/4K EEPROM that is organized for 128 x 8-bit or 256/512 x 8-bit operation
must be used.
The MAC address is used as the default Ethernet MAC address and is loaded into the MAC’s ADDRH
and ADDRL registers. If a properly configured EEPROM is not detected, it is the responsibility of the
Host LAN Driver to set the IEEE addresses.
After a system-level reset occurs, LAN9500/LAN9500i will load the default values from a properly
configured EEPROM. LAN9500/LAN9500i will not accept USB transactions from the Host until this
process is completed.
The LAN9500/LAN9500i EEPROM controller also allows the Host system to read, write and erase the
contents of the Serial EEPROM.
3.1
EEPROM Format
Note the EEPROM offsets are given in units of 16-bit word offsets. A length field with a value of zero
indicates that the field does not exist in the EEPROM. The LAN9500/LAN9500i will use the field’s HW
default value in this case.
Note: For the device descriptor, the only valid values for the length are 0 and 18.
Note: For the configuration and interface descriptor, the only valid values for the length are 0 and 18.
Note: The EEPROM programmer must ensure that if a string descriptor does not exist in the
EEPROM, the referencing descriptor must contain 00h for the respective string index field.
Note: If all string descriptor lengths are zero, then a Language ID will not be supported.
Table 3.1 EEPROM Format
EEPROM ADDRESS
EEPROM CONTENTS
00h
01h
02h
03h
04h
05h
06h
07h
08h
0xA5
MAC Address [7:0]
MAC Address [15:8]
MAC Address [23:16]
MAC Address [31:24]
MAC Address [39:32]
MAC Address [47:40]
Full-Speed Polling Interval for Interrupt Endpoint
Hi-Speed Polling Interval for Interrupt Endpoint
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Table 3.1 EEPROM Format (continued)
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
Configuration Flags
Language ID Descriptor [7:0]
Language ID Descriptor [15:8]
Manufacturer ID String Descriptor Length (bytes)
Manufacturer ID String Descriptor EEPROM Word Offset
Product Name String Descriptor Length (bytes)
Product Name String Descriptor EEPROM Word Offset
Serial Number String Descriptor Length (bytes)
Serial Number String Descriptor EEPROM Word Offset
Configuration String Descriptor Length (bytes)
Configuration String Descriptor Word Offset
Interface String Descriptor Length (bytes)
Interface String Descriptor Word Offset
Hi-Speed Device Descriptor Length (bytes)
Hi-Speed Device Descriptor Word Offset
Hi-Speed Configuration and Interface Descriptor Length (bytes)
Hi-Speed Configuration and Interface Descriptor Word Offset
Full-Speed Device Descriptor Length (bytes)
Full-Speed Device Descriptor Word Offset
Full-Speed Configuration and Interface Descriptor Length (bytes)
Full-Speed Configuration and Interface Descriptor Word Offset
Note: EEPROM byte addresses past 1Dh can be used to store data for any purpose.
Table 3.2 Configuration Flags Description
BIT
NAME
RESERVED
DESCRIPTION
7:3
2
-
Remote Wakeup Support
0 = LAN9500/LAN9500i does not support remote wakeup.
1 = LAN9500/LAN9500i supports remote wakeup.
1
0
RESERVED
-
Power Method
0 = LAN9500/LAN9500i is bus powered.
1 = LAN9500/LAN9500i is self powered.
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3.2
EEPROM Defaults
The signature value of 0xA5 is stored at address 0. A different signature value indicates to the
EEPROM controller that no EEPROM or an un-programmed EEPROM is attached to
Table 3.3 EEPROM Defaults
FIELD
DEFAULT VALUE
MAC Address
FFFFFFFFFFFFh
Full-Speed Polling Interval (mS)
Hi-Speed Polling Interval (mS)
Configuration Flags
Maximum Power (mA)
Vendor ID
01h
04h
04h
FAh
0424h
9500h
Product ID
Note: The Configuration Flags are affected by the PWR_SEL and RMT_WKP straps.
3.3
EEPROM Auto-Load
Certain system level resets (USB reset, POR, nRESET, and SRST) cause the EEPROM contents to
be loaded into LAN9500/LAN9500i. After a reset, the EEPROM controller attempts to read the first
byte of data from the EEPROM. If the value 0xA5 is read from the first address, then the EEPROM
controller will assume that an external Serial EEPROM is present.
Note: The USB reset only loads the MAC address.
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3.4
An Example of EEPROM Format Interpretation
byte, how the EEPROM is formatted.
Table 3.4 Dump of EEPROM Memory
OFFSET
BYTE
VALUE
0000h
0008h
A5 12 34 56 78 9A BC 01
04 04 09 04 0A 0F 10 14
10 1C 00 00 00 00 12 24
12 2D 12 36 12 3F 0A 03
53 00 4D 00 53 00 43 00
10 03 4C 00 41 00 4E 00
39 00 35 00 30 00 30 00
10 03 30 00 30 00 30 00
35 00 31 00 32 00 33 00
12 01 00 02 FF 00 01 40
24 04 00 95 00 01 01 02
03 01 09 02 27 00 01 01
00 A0 FA 09 04 00 00 03
FF 00 FF 00 12 01 00 02
FF 00 01 40 24 04 00 95
00 01 01 02 03 01 09 02
27 00 01 01 00 A0 FA 09
04 00 00 03 FF 00 FF 00
..............................................
0010h
0018h
0020h
0028h
0030h
0038h
0040h
0048h
0050h
0058h
0060h
0068h
0070h
0078h
0080h
0088h
0090h - 00FFh
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Table 3.5 EEPROM Example - 256 Byte EEPROM
EEPROM
EEPROM
ADDRESS
CONTENTS
(HEX)
DESCRIPTION
00h
01h - 06h
07h
A5
EEPROM Programmed Indicator
12 34 56 78 9A BC
MAC Address 12 34 56 78 9A BC
01
04
04
Full-Speed Polling Interval for Interrupt Endpoint (1ms)
Hi-Speed Polling Interval for Interrupt Endpoint (4ms)
08h
09h
Configuration Flags - LAN9500/LAN9500i is bus powered and supports
remote wakeup.
0Ah - 0Bh
0Ch
09 04
0A
Language ID Descriptor 0409h, English
Manufacturer ID String Descriptor Length (10 bytes)
0Dh
0F
Manufacturer ID String Descriptor EEPROM Word Offset (0Fh)
Corresponds to EEPROM Byte Offset 1Eh
0Eh
0Fh
10
14
Product Name String Descriptor Length (16 bytes)
Product Name String Descriptor EEPROM Word Offset (14h)
Corresponds to EEPROM Byte Offset 28h
10h
11h
10
Serial Number String Descriptor Length (16 bytes)
1C
Serial Number String Descriptor EEPROM Word Offset (1Ch)
Corresponds to EEPROM Byte Offset 38h
12h
13h
14h
15h
16h
17h
00
00
00
00
12
24
Configuration String Descriptor Length (0 bytes - NA)
Configuration String Descriptor Word Offset (Don’t Care)
Interface String Descriptor Length (0 bytes - NA)
Interface String Descriptor Word Offset (Don’t Care)
Hi-Speed Device Descriptor Length (18 bytes)
Hi-Speed Device Descriptor Word Offset (24h)
Corresponds to EEPROM Byte Offset 48h
18h
19h
12
Hi-Speed Configuration and Interface Descriptor Length (18 bytes)
2D
Hi-Speed Configuration and Interface Descriptor Word Offset (2Dh)
Corresponds to EEPROM Byte Offset 5Ah
1Ah
1Bh
12
36
Full-Speed Device Descriptor Length (18 bytes)
Full-Speed Device Descriptor Word Offset (36h)
Corresponds to EEPROM Byte Offset 6Ch
1Ch
1Dh
12
3F
Full-Speed Configuration and Interface Descriptor Length (18bytes)
Full-Speed Configuration and Interface Descriptor Word Offset (3Fh)
Corresponds to EEPROM Byte Offset 7Eh
1Eh
1Fh
0A
03
Size of Manufacturer ID String Descriptor (10 bytes)
Descriptor Type (String Descriptor - 03h)
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Table 3.5 EEPROM Example - 256 Byte EEPROM (continued)
EEPROM
CONTENTS
(HEX)
EEPROM
ADDRESS
DESCRIPTION
20h-27h
28h
53 00 4D 00 53 00 43 00 Manufacturer ID String (“SMSC” in UNICODE)
10
03
Size of Product Name String Descriptor (16 bytes)
Descriptor Type (String Descriptor - 03h)
29h
2Ah-37h
4C 00 41 00 4E 00 39 00 Product Name String (“LAN9500” in UNICODE)
35 00 30 00 30 00
38h
39h
10
03
Size of Serial Number String Descriptor (16 bytes)
Descriptor Type (String Descriptor - 03h)
3Ah-47h
30 00 30 00 30 00 35 00 Serial Number String (“0005123” in UNICODE)
31 00 32 00 33 00
48h
49h
12
01
Size of Hi-Speed Device Descriptor in Bytes (18 bytes)
Descriptor Type (Device Descriptor - 01h)
USB Specification Number that the device complies with (0200h)
Class Code
4Ah-4Bh
4Ch
00 02
FF
4Dh
00
Subclass Code
4Eh
01
Protocol Code
4Fh
40
Maximum Packet Size for Endpoint 0
Vendor ID (0424h)
50h-51h
52h-53h
54h-55h
56h
24 04
00 95
00 01
01
Product ID (9500h)
Device Release Number (0100h)
Index of Manufacturer String Descriptor
Index of Product String Descriptor
57h
02
58h
03
Index of Serial Number String Descriptor
Number of Possible Configurations
Size of Hi-Speed Configuration Descriptor in bytes (9 bytes)
Descriptor Type (Configuration Descriptor - 02h)
Total length in bytes of data returned (0027h = 39 bytes)
Number of Interfaces
59h
01
5Ah
09
5Bh
02
5Ch-5Dh
5Eh
27 00
01
5Fh
01
Value to use as an argument to select this configuration
Index of String Descriptor describing this configuration
Bus powered and remote wakeup enabled
Maximum Power Consumption is 500 mA
Size of Descriptor in Bytes (9 Bytes)
60h
00
61h
A0
62h
FA
63h
09
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Table 3.5 EEPROM Example - 256 Byte EEPROM (continued)
EEPROM
EEPROM
CONTENTS
ADDRESS
(HEX)
DESCRIPTION
64h
65h
04
00
Descriptor Type (Interface Descriptor - 04h)
Number identifying this Interface
66h
00
Value used to select alternative setting
Number of Endpoints used for this interface (Less endpoint 0)
Class Code
67h
03
68h
FF
69h
00
Subclass Code
6Ah
FF
Protocol Code
6Bh
00
Index of String Descriptor Describing this interface
Size of Full-Speed Device Descriptor in Bytes (18 Bytes)
Descriptor Type (Device Descriptor - 01h)
USB Specification Number that the device complies with (0200h)
Class Code
6Ch
12
6Dh
01
6Eh-6Fh
70h
00 02
FF
71h
00
Subclass Code
72h
01
Protocol Code
73h
40
Maximum Packet Size for Endpoint 0
Vendor ID (0424h)
74h-75h
76h-77h
78h-79h
7Ah
24 04
00 95
00 01
01
Product ID (9500h)
Device Release Number (0100h)
Index of Manufacturer String Descriptor
Index of Product String Descriptor
7Bh
02
7Ch
03
Index of Serial Number String Descriptor
Number of Possible Configurations
Size of Full-Speed Configuration Descriptor in bytes (9 bytes)
Descriptor Type (Configuration Descriptor - 02h)
Total length in bytes of data returned (0027h = 39 bytes)
Number of Interfaces
7Dh
01
7Eh
09
7Fh
02
80h-81h
82h
27 00
01
83h
01
Value to use as an argument to select this configuration
Index of String Descriptor describing this configuration
Bus powered and remote wakeup enabled
Maximum Power Consumption is 500 mA
Size of Full-Speed Interface Descriptor in Bytes (9 Bytes)
84h
00
85h
A0
86h
FA
87h
09
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Table 3.5 EEPROM Example - 256 Byte EEPROM (continued)
EEPROM
CONTENTS
(HEX)
EEPROM
ADDRESS
DESCRIPTION
88h
89h
04
00
00
03
FF
00
FF
00
-
Descriptor Type (Interface Descriptor - 04h)
Number identifying this Interface
Value used to select alternative setting
Number of Endpoints used for this interface (Less endpoint 0)
Class Code
8Ah
8Bh
8Ch
8Dh
Subclass Code
8Eh
Protocol Code
8Fh
Index of String Descriptor Describing this interface
Data storage for use by Host as desired
90h- FFh
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Chapter 4 Operational Characteristics
4.1
Absolute Maximum Ratings*
Supply Voltage (VDD33IO, VDD33A) (Note 4.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.6V
Positive voltage on signal pins, with respect to ground (Note 4.2) . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Negative voltage on signal pins, with respect to ground (Note 4.3) . . . . . . . . . . . . . . . . . . . . . . . .-0.5V
Positive voltage on XI, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6V
Positive voltage on XO, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V
Ambient Operating Temperature in Still Air (T ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 4.4
A
o
o
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +150 C
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
Note 4.1 When powering this device from laboratory or system power supplies, it is important that
the absolute maximum ratings not be exceeded or device failure can result. Some power
supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In
addition, voltage transients on the AC power line may appear on the DC output. If this
possibility exists, it is suggested that a clamp circuit be used.
Note 4.2 This rating does not apply to the following pins: XI, XO, EXRES, USBRBIAS.
Note 4.3 This rating does not apply to the following pins: EXRES, USBRBIAS.
o
o
o
o
Note 4.4 0 C to +70 C for commercial version, -40 C to +85 C for industrial version.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is
a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Functional operation of the device at any condition exceeding those indicated in
Section 4.2, "Operating Conditions**", Section 4.4, "DC Specifications", or any other applicable section
of this specification is not implied. Note, device signals are NOT 5 volt tolerant unless specified
otherwise.
4.2
Operating Conditions**
Supply Voltage (VDD33A, VDD33BIAS, VDD33IO). . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V +/- 300mV
Ambient Operating Temperature in Still Air (T ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 4.4
A
**Proper operation of LAN9500/LAN9500i is guaranteed only within the ranges specified in this section.
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4.3
Power Consumption
This section details the power consumption of LAN9500/LAN9500i as measured during various modes
of operation. Power consumption values are provided for both the device-only, and for the device plus
Ethernet components. Power dissipation is determined by temperature, supply voltage, and external
source/sink requirements.
4.3.1
SUSPEND0
Table 4.1 SUSPEND0 - Supply and Current @3.3V
PARAMETER
MIN
TYPICAL
MAX
MAX
MAX
UNIT
Supply current (VDD33IO, VDD33A)
77.9
257.3
394.6
mA
mW
mW
Power Dissipation (Device Only)
Power Dissipation (Device and Ethernet components)
4.3.2
SUSPEND1
Table 4.2 SUSPEND1 - Supply and Current @3.3V
PARAMETER
MIN
TYPICAL
UNIT
Supply current (VDD33IO, VDD33A)
19.9
65.7
65.7
mA
mW
mW
Power Dissipation (Device Only)
Power Dissipation (Device and Ethernet components)
4.3.3
SUSPEND2
Table 4.3 SUSPEND2 - Supply and Current @3.3V
PARAMETER
MIN
TYPICAL
UNIT
Supply current (VDD33IO, VDD33A)
0.624
2.1
mA
mW
mW
Power Dissipation (Device Only)
Power Dissipation (Device and Ethernet components)
2.1
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4.3.4
Operational Power Consumption
Table 4.4 Operational Power Consumption - Supply and Current @3.3V
PARAMETER
MIN
TYPICAL
MAX
UNIT
100BASE-TX Full Duplex (USB High-Speed)
Supply current (VDD33IO, VDD33A)
137.3
453.0
591.2
mA
mW
mW
Power Dissipation (Device Only)
Power Dissipation (Device and Ethernet components)
10BASE-T Full Duplex (USB High-Speed)
Supply current (VDD33IO, VDD33A)
99.2
327.6
665.7
mA
mW
mW
Power Dissipation (Device Only)
Power Dissipation (Device and Ethernet components)
100BASE-TX Full Duplex (USB Full-Speed)
Supply current (VDD33IO, VDD33A)
135.2
446.4
583.7
mA
mW
mW
Power Dissipation (Device Only)
Power Dissipation (Device and Ethernet components)
10BASE-T Full Duplex (USB Full-Speed)
Supply current (VDD33IO, VDD33A)
97.5
322.1
660.6
mA
mW
mW
Power Dissipation (Device Only)
Power Dissipation (Device and Ethernet components)
4.3.5
Customer Evaluation Board Operational Power Consumption
Table 4.5 Customer Evaluation Board Operational Power Consumption - Supply and Current @3.3V
PARAMETER
MIN
TYPICAL
MAX
UNIT
100BASE-TX Full Duplex (USB High-Speed)
Total SMSC Customer Evaluation Board Current Consumption
208.0
mA
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4.4
DC Specifications
Table 4.6 I/O Buffer Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
IS Type Input Buffer
Low Input Level
V
-0.3
V
V
ILI
IHI
ILT
IHT
High Input Level
V
V
3.6
1.35
1.8
Negative-Going Threshold
Positive-Going Threshold
SchmittTrigger Hysteresis
1.01
1.39
345
1.18
1.6
V
Schmitt trigger
Schmitt trigger
V
V
V
420
485
mV
HYS
(V
- V
)
IHT
ILT
Input Leakage
IN
I
-10
10
3
uA
pF
IH
(V = VSS or VDD33IO)
Input Capacitance
C
IN
IS_5V Type Input Buffer
Low Input Level
V
-0.3
V
V
ILI
IHI
ILT
IHT
High Input Level
V
V
5.5
1.35
1.8
Negative-Going Threshold
Positive-Going Threshold
SchmittTrigger Hysteresis
1.01
1.39
345
1.18
1.6
V
Schmitt trigger
Schmitt trigger
V
V
V
420
485
mV
HYS
(V
- V
)
IHT
ILT
Input Leakage
IN
I
I
-10
10
79
4
uA
uA
pF
IH
IH
(V = VSS or VDD33IO)
Input Leakage
(V = 5.5V)
IN
Input Capacitance
O8 Type Buffers
C
IN
Low Output Level
V
0.4
V
V
I
= 8mA
OL
OL
VDD33IO - 0.4
High Output Level
OD8 Type Buffer
V
I
= -8mA
OH
OH
Low Output Level
O12 Type Buffers
V
V
0.4
0.4
V
I
= 8mA
OL
OL
Low Output Level
V
V
I
= 12mA
= -12mA
OL
OL
VDD33IO - 0.4
High Output Level
OD12 Type Buffer
V
I
OH
OH
Low Output Level
V
0.4
V
I
= 12mA
OL
OL
ICLK Type Buffer (XI Input)
Low Input Level
High Input Level
V
-0.3
1.4
0.5
3.6
V
V
ILI
V
IHI
Note 4.5 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down
and pull-up resistors add +/- 50uA per-pin (typical).
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Note 4.6 This is the total 5.5V input leakage for the entire device.
Note 4.7 XI can optionally be driven from a 25MHz single-ended clock oscillator.
Table 4.7 100BASE-TX Transceiver Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Peak Differential Output Voltage High
Peak Differential Output Voltage Low
Signal Amplitude Symmetry
Signal Rise and Fall Time
Rise and Fall Symmetry
Duty Cycle Distortion
V
950
-950
98
3.0
-
-
-
1050
-1050
102
5.0
mVpk
mVpk
%
PPH
V
PPL
V
-
SS
RF
T
-
nS
T
-
0.5
nS
RFS
D
35
-
50
-
65
%
CD
OS
Overshoot and Undershoot
Jitter
V
5
%
1.4
nS
Note 4.8 Measured at line side of transformer, line replaced by 100Ω (+/- 1%) resistor.
Note 4.9 Offset from 16nS pulse width at 50% of pulse peak.
Note 4.10 Measured differentially.
Table 4.8 10BASE-T Transceiver Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Transmitter Peak Differential Output Voltage
Receiver Differential Squelch Threshold
V
2.2
2.5
2.8
V
OUT
V
300
420
585
mV
DS
Note 4.11 Min/max voltages guaranteed as measured with 100Ω resistive load.
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4.5
AC Specifications
This section details the various AC timing specifications of the LAN9500/LAN9500i.
Note: The MII timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification
for detailed MII timing information.
Note: The USBDP and USBDM pin timing adheres to the USB 2.0 specification. Refer to the
Universal Serial Bus Revision 2.0 specification for detailed USB timing information.
4.5.1
Equivalent Test Load
unless otherwise specified.
OUTPUT
25 pF
Figure 4.1 Output Equivalent Test Load
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4.5.2
Power-On Configuration Strap Valid Timing
Figure 4.2 illustrates the configuration strap valid timing requirement in relation to power-on. In order
for valid configuration strap values to be read at power-on, the following timing requirements must be
met.
2.0V
VDD33IO
tcfg
Configuration Straps
Figure 4.2 Power-On Configuration Strap Valid Timing
Table 4.9 Power-On Configuration Strap Valid Timing
SYMBOL
DESCRIPTION
Configuration strap valid time
MIN
TYP
MAX
UNITS
t
15
mS
cfg
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4.5.3
Reset and Configuration Strap Timing
Figure 4.3 illustrates the nRESET pin timing requirements and its relation to the configuration strap
pins and output drive. Assertion of nRESET is not a requirement. However, if used, it must be asserted
for the minimum period specified.
trstia
nRESET
tcss
tcsh
Configuration
Strap Pins
todad
Output Drive
Figure 4.3 nRESET Reset Pin Timing
Table 4.10 nRESET Reset Pin Timing Values
SYMBOL
DESCRIPTION
nRESET input assertion time
MIN
TYP
MAX
UNITS
t
1
uS
nS
nS
nS
rstia
t
Configuration strap pins setup to nRESET deassertion
Configuration strap pins hold after nRESET deassertion
Output drive after deassertion
200
10
css
csh
t
t
30
odad
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4.5.4
EEPROM Timing
The following specifies the EEPROM timing requirements for LAN9500/LAN9500i:
tcsl
EECS
tckcyc
tcklcsl
tckh
tckl
tcshckh
EECLK
tckldis
tdvckh tckhdis
EEDO
EEDI
tdsckh
tdhckh
tdhcsl
tcshdv
EEDI (VERIFY)
Figure 4.4 EEPROM Timing
Table 4.11 EEPROM Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
EECLK Cycle time
1110
550
550
1070
30
1130
570
570
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ckcyc
EECLK High time
t
ckh
EECLK Low time
t
ckl
EECS high before rising edge of EECLK
EECLK falling edge to EECS low
EEDO valid before rising edge of EECLK
EEDO disable after rising edge EECLK
EEDI setup to rising edge of EECLK
EEDI hold after rising edge of EECLK
EECLK low to data disable (OUTPUT)
EEDIO valid after EECS high (VERIFY)
EEDIO hold after EECS low (VERIFY)
EECS low
t
cshckh
t
cklcsl
dvckh
550
550
90
t
t
ckhdis
t
dsckh
dhckh
0
t
580
t
ckldis
cshdv
600
t
0
t
dhcsl
1070
t
csl
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4.5.5
Turbo MII Interface Timing
The external MII supports Turbo MII and the interface timing is as follows.
toutdly
ttxhold
TXCLK
TXD[3:0]
TXEN
CRS
Figure 4.1 Turbo MII Output Timing
Table 4.12 Turbo MII Output Timing Values
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
NOTES
t
Clock to output delay for TXD and TXEN
TXD and TXEN hold time after TXCLK
12.5
ns
outdly
txhold
t
1.5
ns
Note 4.12 These values satisfy the MII specification requirement of 0 ns to 25 ns clock to output
delay.
Note 4.13 Timing was designed for system load between 5 pf and 15 pf.
trxhold
trxsetup
RXCLK
RXD[3:0]
RXDV
CRS
Figure 4.2 Turbo MII Input Timing
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Table 4.13 Turbo MII Interface Timing Values
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
NOTES
t
RXD and RXDV setup time prior to rising edge
of RXCLK
5.5
ns
rxsetup
t
RXD and RXDV hold time after the rising edge
of RXCLK
0
ns
rxhold
Note 4.14 These values satisfy the 10-ns setup and hold time requirements that are necessary for
the Turbo MII specification.
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4.6
Clock Circuit
LAN9500/LAN9500i can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock
oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be
left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle
is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal
Table 4.14 LAN9500/LAN9500i Crystal Specifications
PARAMETER
SYMBOL
MIN
NOM
AT, typ
Fundamental Mode
Parallel Resonant Mode
MAX
UNITS
NOTES
Crystal Cut
Crystal Oscillation Mode
Crystal Calibration Mode
Frequency
F
-
25.000
-
MHz
PPM
PPM
PPM
PPM
pF
fund
o
Frequency Tolerance @ 25 C
Frequency Stability Over Temp
Frequency Deviation Over Time
Total Allowable PPM Budget
Shunt Capacitance
F
-
-
+/-50
tol
F
-
-
+/-50
temp
F
-
+/-3 to 5
-
age
-
-
+/-50
C
-
7 typ
-
O
Load Capacitance
C
-
20 typ
-
pF
L
Drive Level
P
300
-
-
uW
W
Equivalent Series Resistance
Operating Temperature Range
R
-
-
-
50
Ohm
1
o
-
-
C
LAN9500/LAN9500i XI Pin
Capacitance
3 typ
pF
pF
LAN9500/LAN9500i XO Pin
Capacitance
-
3 typ
-
Note 4.15 The maximum allowable values for Frequency Tolerance and Frequency Stability are
application dependant. Since any particular application must meet the IEEE +/-50 PPM
Total PPM Budget, the combination of these two values must be approximately +/-45 PPM
(allowing for aging).
Note 4.16 Frequency Deviation Over Time is also referred to as Aging.
Note 4.17 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as
+/- 50 PPM.
o
o
Note 4.18 0 C for commercial version, -40 C for industrial version.
o
o
Note 4.19 +70 C for commercial version, +85 C for industrial version.
Note 4.20 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not
included in this value. The XO/XI pin and PCB capacitance values are required to
accurately calculate the value of the two external load capacitors. These two external load
capacitors determine the accuracy of the 25.000 MHz frequency.
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Chapter 5 Package Outline
Figure 5.1 LAN9500/LAN9500i 56-QFN Package
Table 5.1 LAN9500/LAN9500i 56-QFN Dimensions
MIN
NOMINAL
MAX
REMARKS
A
A1
0.70
0.00
-
-
1.00
0.05
0.90
8.15
7.95
6.05
0.50
0.30
Overall Package Height
Standoff
0.02
A2
-
Mold Cap Thickness
X/Y Body Size
D/E
D1/E1
D2/E2
L
7.85
7.55
5.75
0.30
0.18
8.00
-
5.90
X/Y Mold Cap Size
X/Y Exposed Pad Size
Terminal Length
Terminal Width
-
b
0.25
e
0.50 BSC
Terminal Pitch
Notes:
1. All dimensions are in millimeters unless otherwise noted.
2. Position tolerance of each terminal and exposed pad is +/- 0.05 mm at maximum material condition. Dimension
“b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip.
3. The pin 1 identifier may vary, but is always located within the zone indicated.
Revision 1.7 (10-02-08)
SMSC LAN9500/LAN9500i
DATA4S0HEET
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Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
Chapter 6 Revision History
Table 6.1 Customer Revision History
REVISION LEVEL
AND DATE
SECTION/FIGURE/ENTRY
CORRECTION
Rev. 1.6
All
Fixed various typos
(09-09-08)
Fixed typos in example
Fixed typos in example
Added note to GPIO8, GPIO9, and GPIO10 stating
“By default this pin is configured as a GPIO”
Rev. 1.5
All
Fixed various typos
(08-27-08)
Input leakage and input capacitance values added
for IS and IS_5V buffer types.
Added note to EEP_SIZE pin definition: “A 3-wire
style 1K/2K/4K EEPROM that is organized for 128
x 8-bit or 256/512 x 8-bit operation must be used.”
EEPROM Controller section added.
Rev. 1.3
(06-30-08)
Added SUSPEND0 and SUSPEND1 power
consumption tables. Reformatted all power
consumption tables and added typical values,
except for customer evaluation board, for which
maximum value was specified.
Rev. 1.2
(06-18-08)
Added IS buffer type to following pins when
operating in Internal PHY Mode: RXER, TXEN,
RXDV, RXCLK, CRS, COL, MDIO, MDC, TXD3,
TXD2, TXD1, TXD0, TXCLK.
Added PD buffer type to following pins when
operating in Internal PHY Mode: TXEN, RXDV,
COL, MDIO, MDC, TXD3, TXD2, TXD1, TXD0,
TXCLK.
Changed buffer type from PU to PD for following
pins: TXD2 (Internal PHY Mode), TXD1 (Internal
PHY Mode), TXD0 (Internal PHY Mode).
Changed buffer type from PD to PU for following
pins: TXD3 (External PHY Mode).
Rev. 1.2
(06-16-08)
Changed ESR value from 30 ohms max to 50
Rev. 1.2
(06-10-08)
Changed pin 33 from “NC” to “TEST3”
Reduced pin count to one. Removed hidden
TESTMODE entry from the table.
Revision 1.7 (10-02-08)
SMSC LAN9500/LAN9500i
DATA4S2HEET
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Hi-Speed USB 2.0 to 10/100 Ethernet Controller
Datasheet
Table 6.1 Customer Revision History (continued)
REVISION LEVEL
AND DATE
SECTION/FIGURE/ENTRY
CORRECTION
Added new TEST3 entry, which must always be
grounded. Modified buffer types for TEST1 and
TEST2 entries to indicate “-” as buffer type. Buffer
type now hidden. TEST3 corresponds to hidden
TESTMODE pin.
Figure 2.1 LAN9500/LAN9500i 56- Updated figure with Rev B strap changes and pin
33 change from “NC” to “TEST3”
EEP_DISABLE moved from RXER to TXD0,
RMT_WKP moved from RXCLK to TXD1, and
EEP_SIZE moved from TXCLK to TXD3. Moved
Replaced previous “3.5.3 Reset Timing” section
with this section.
Added section.
SMSC LAN9500/LAN9500i
Revision 1.7 (10-02-08)
DATA4S3HEET
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