USB2242/USB2242I
Ultra Fast USB 2.0 Memory
Stick Flash Media Controller
Datasheet
PRODUCT FEATURES
General Description
Mask Programmable Features
The SMSC USB2242/USB2242i is a USB 2.0 compliant,
„
„
„
„
VID/PID/Language ID
high speed Bulk Only Mass Storage Class Peripheral
Controller intended for reading and writing to Memory Stick
Flash Media Cards.
28-character Manufacturer ID and Product string
12-hex digit (max) Serial Number string
Customizable Vendor specific data LED blink interval or
duration
The SMSC USB2242/USB2242i is a fully integrated, single
chip solution capable of ultra high performance operation.
Average sustained transfer rates exceeding 35MB/s are
possible if the media and host can support those rates.
Provisions to read/write secure media formats is also
provided.
Software Features
„
„
„
Optimized for low latency interrupt handling
Reduced memory footprint
Please see the USB2242/USB2242i Software Release
Notes for additional Software Features.
Applications
General Features
„
„
„
„
„
„
Flash Media Card Reader/Writer
Printers
„
36-pin QFN (6x6mm) lead-free RoHS compliant package
Hardware-controlled data flow architecture for all self-
mapped media
„
Desktop and Mobile PCs
Consumer A/V
Media Players/Viewers
Vista ReadyBoost
„
„
„
Pipelined hardware support for access to non-self-
mapped media
TM
„
Compatible with Microsoft Vista, Windows XP, Windows
ME, Windows 2K SP4, Apple OSx, and Linux Mass
Storage Class Drivers
Product name with “i” denotes the version that supports
the industrial temperature range of -40ºC to 85ºC
Support included for secure media format on a licensed,
customized basis
—
Sony MagicGateTM
Hardware Features
„
Single Chip Flash Media Reader/Writer
—
—
—
Memory Stick Specification 1.43
Memory Stick Pro Format Specification 1.02
Memory Stick Pro-HG Duo Format Specification 1.01
–
Memory Stick, MS Duo, HS-MS, MS Pro-HG, MS Pro
„
Extended configuration options
Socket switch polarities, etc.
—
„
„
Media Activity LED
GPIO configuration and polarity
—
Up to 8 GPIOs for special function use: LED indicators,
power control to memory devices, etc. The number of
actual GPIO’s depends on the implementation
configuration used.
—
One GPIO with up to 200 mA drive
„
„
On Board 24MHz Crystal Driver Circuit
Internal Card Power FET
—
—
200mA
"Fold-back" short circuit current protected
„
8051 8-bit microprocessor
—
—
60MHz - single cycle execution
64KB ROM; 14KB RAM
„
„
Internal Regulator for 1.8V core operation
Optimized pinout improves signal routing, easing
implementation and allowing for improved signal integrity
SMSC USB2242/USB2242i
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Table of Contents
Chapter 1 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 3 Pin Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
36-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 6 Pin Reset State Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 7 DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Maximum Guaranteed Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 8 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 10 GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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List of Figures
Figure 2.1 USB2242/USB2242i Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4.1 USB2242/USB2242i 36 Pin QFN Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6.1 Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6.2 Legend for Pin Reset States Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7.1 Supply Rise Time Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8.1 Typical Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8.2 Formula to Find Value of C1 and C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9.1 USB2242/USB2242i 36-QFN, 6x6mm Body, 0.5mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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List of Tables
Table 3.1 USB2242/2242i 36-Pin QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5.2 USB2242/2242i 36-Pin QFN Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5.3 USB2242/USB2242i Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6.1 USB2242/USB2242i Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7.1 Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Chapter 1 Acronyms
MS: Memory Stick
MSC: Memory Stick Controller
PLL: Phase-Locked Loop
QFN: Quad Flat no Leads
RoHS: Restriction of Hazardous Substances Directive
SIE: Serial Interface Engine
*Note: In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made
the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other
intellectual property rights from or through various persons or entities, including without limitation media standard companies,
forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations
include without limitation the following: Sony Corporation (Memory Stick, Memory Stick Pro); SD3 LLC (Secure Digital); MultiMedia
Card Association (MultiMediaCard); the SSFDC Forum (SmartMedia); the Compact Flash Association (Compact Flash); and Fuji
Photo Film Co., Ltd., Olympus Optical Co., Ltd., and Toshiba Corporation (xD-Picture Card). SMSC does not make such licenses
or technical information available; does not promise or represent that any such licenses or technical information will actually be
obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or
with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or
otherwise with respect to, any such technical information.
SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any customer, or otherwise, with
respect to infringement, including without limitation any obligations to defend or settle claims, to reimburse for costs, or to pay
damages, shall not apply to any of the devices made the subject of this document or any software programs related to any of such
devices, or to any combinations involving any of them, with respect to infringement or claimed infringement of any existing or future
patents related to solid state disk or other flash memory technology or applications ("Solid State Disk Patents"). By making any
purchase of any of the devices made the subject of this document, the customer represents, warrants, and agrees that it has
obtained all necessary licenses under then-existing Solid State Disk Patents for the manufacture, use and sale of solid state disk
and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses
under Solid State Disk Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the subject
of this document which may be sold to the customer, and any sale by SMSC of such units to the customer, are valid exercises of
the customer's rights and licenses under such Solid State Disk Patents; that SMSC shall have no obligation for royalties or otherwise
under any Solid State Disk Patents by reason of any such manufacture, use, or sale of such units; and that SMSC shall have no
obligation for any costs or expenses related to the customer's obtaining or having obtained rights or licenses under any Solid State
Disk Patents.
SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER
VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES
AGAINST INFRINGEMENT AND THE LIKE.
No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask
work right, trade secret, or other intellectual property right.
**To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of
these Software License Agreements may be obtained by contacting SMSC.
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Chapter 2 Block Diagram
AUTO_
CBW
PROC
USB
Host
FMI
Media
Interface
SIE
CTL
BUS
INTFC
BUS
INTFC
FMDU
CTL
PHY
MS
EP0 TX
EP0 RX
BUS
INTFC
RAM
4K
total
EP1 RX
EP1 TX
EP2 RX
EP2 TX
XDATA BRIDGE
+ BUS ARBITER
PWR_FET1
GPIO10(CARD_PWR)
GPIOs
7 pins
RAM
10KB
Program
Memory
I/O Bus
ADDR
MAP
ROM
64KB
Clock
Generation and
Control
SFR
RAM
8051
PROCESSOR
Figure 2.1 USB2242/USB2242i Block Diagram
SMSC USB2242/USB2242i
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Chapter 3 Pin Table
3.1
36-Pin Package
Table 3.1 USB2242/2242i 36-Pin QFN Package
MS INTERFACE (11 PINS)
MS_D0
MS_D4
MS_BS
MS_D1
MS_D2
MS_D6
MS_D3
MS_D7
MS_D5
MS_SCLK
GPIO12 (MS_INS)
USB INTERFACE (7 PINS)
USB+
USB-
RBIAS
XTAL1 (CLKIN)
XTAL2
VDDA33
VDD18PLL
MISC (14 Pins)
GPIO1 (LED1)
GPIO2 / RXD / SDA
GPIO4
GPIO7 / TXD / SCK /
MS_SKT_SEL
GPIO10 (CRD_PWR)
TEST
GPIO14
nRESET
GPIO15
(5) NC
DIGITAL, POWER (4 PINS)
(3) VDD33
VDD18
TOTAL 36
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Chapter 4 Pin Configuration
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
nRESET
NC
TEST
GPIO4
NC
MS_SCLK
GPIO7 / TXD / SCK / MS_SKT_SEL
NC
SMSC
USB2242/2242i
(Top View QFN-36)
XTAL2
XTAL1 (CLKIN)
VDD18PLL
RBIAS
VDD33
VDD18
NC
Thermal Slug
(must be connected to VSS)
MS_D0
MS_D1
VDDA33
Indicates pins on the bottom of the device.
Figure 4.1 USB2242/USB2242i 36 Pin QFN Diagram
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Chapter 5 Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional
groups according to their associated interface.
The “n” symbol in the signal name indicates that the active, or asserted, state occurs when the signal
is at a low voltage level. When “n” is not present before the signal name, the signal is asserted at the
high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working
with a mixture of “active low” and “active high” signals. The term assert, or assertion, indicates that a
signal is active, independent of whether that level is represented by a high or low voltage. The term
negate, or negation, indicates that a signal is inactive.
5.1
Pin Descriptions
Table 5.2 USB2242/2242i 36-Pin QFN Pin Descriptions
BUFFER
NAME
SYMBOL
36-PIN QFN
TYPE
DESCRIPTION
MEMORY STICK INTERFACE
MS System Data
In/Out
MS_D[7:0]
8
7
4
I/O12PD These pins are the bi-directional data
signals for the MS device. In serial mode,
the most significant bit (MSB) of each byte
is transmitted first by either MSC or MS
device on MS_D0. MS_D0, MS_D2, and
MS_D3 have weak pull-down resistors.
MS_D1 has a pull down resistor if it is in
parallel mode, otherwise it is disabled. In
4 or 8 bit parallel mode, there is a weak
pull-down resistor on all MS_D7 - 0
5
23
20
10
11
signals. The resistors are controlled by
MSC_SYSTEM_0, MSC_MODE_CTL and
MSC_PRO_HG registers.
MS Bus State
MS_BS
9
O12
This pin is connected to the BS pin of the
MS device.
It is used to control the Bus States 0, 1, 2
and 3 (BS0, BS1, BS2 and BS3) of the MS
device.
MS System CLK
MS_SCLK
30
24
O12
IPU
This pin is an output clock signal to the
MS device.
The clock frequency is software
configurable.
MS Card Insertion
GPIO
GPIO12
(MS_INS)
This is a GPIO designated as the Memory
TM
Stick
card detection pin.
USB INTERFACE
USB Bus Data
USB+
USB-
2
3
I/O-U
These pins connect to the USB bus data
signals.
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Table 5.2 USB2242/2242i 36-Pin QFN Pin Descriptions (continued)
BUFFER
TYPE
NAME
SYMBOL
RBIAS
36-PIN QFN
DESCRIPTION
USB Transceiver
Bias
35
I-R
A 12.0k , 1.0% resistor is attached from
VSSA to this pin in order to set the
transceiver's internal bias currents.
24MHz Crystal or
external clock
input
XTAL1 (CLKIN)
XTAL2
33
32
ICLKx
This pin can be connected to one terminal
of the crystal or it can be connected to an
external 24 clock when a crystal is not
used.
24MHz Crystal
OCLKx
This is the other terminal of the crystal, or
it can be left open when an external clock
source is used to drive XTAL1(CLKIN). It
may not be used to drive any external
circuitry other than the crystal circuit.
3.3V Analog
Power
VDDA33
36
34
3.3V Analog Power
1.8V PLL Power
VDD18PLL
This pin is the 1.8V Power for the PLL.
+1.8V Filtered analog power for internal
PLL. This pin must have a 1.0μF(or
greater) ±20% (ESR <0.1Ω) capacitor to
VSS.
MISC
General Purpose
I/O
GPIO1 (LED1)
1
I/O12
This pin may be used either as input, edge
sensitive interrupt input, or output.
In addition, as an output, the GPIO1 can
use output controlled by the LED1_GPIO1
register.
General Purpose
I/O
GPIO2 / RXD /
SDA
27
I/O12
I
GPIO: This pin may be used either as
input, edge sensitive interrupt input, or
output.
RXD: In addition to the above, the signal
can be used as input to the RXD of UART
in the device, when the TXD_RXD_SEL
bit in UTIL_CONFIG1 register is cleared to
"0".
I/O12
I/O12
SDA: This is the data pin when used with
an external serial EEPROM.
General Purpose
I/O
GPIO4
29
This pin may be used either as input, edge
sensitive interrupt input, or output.
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Table 5.2 USB2242/2242i 36-Pin QFN Pin Descriptions (continued)
BUFFER
TYPE
NAME
SYMBOL
36-PIN QFN
DESCRIPTION
General Purpose
I/O
GPIO7 /
31
I/O12
GPIO: This pin may be used either as
input, edge sensitive interrupt input, or
output.
TXD /
SCK /
MS_SKT_SEL
O12
TXD: In addition, as an output, the GPIO7
can be used as an output TXD of UART in
the device, when the GPIO2/TXD bit in
UTL_CONFIG register is set to "1"
O12
I
SCK: This is the clock output when used
with an external EEPROM.
MS_SKT_SEL: On the positive edge of
nRESET, this pin is sampled to determine
the Memory Stick socket size.
1 = 8 bit
0 = 4 bit
General Purpose
I/O
GPIO10
(CRD_PWR)
21
I/O200
GPIO: This pin may be used either as
input, edge sensitive interrupt input, or
output.
CRD_PWR: Card Power drive of 3.3V @
either 100mA or 200mA.
General Purpose
I/O
GPIO14
GPIO15
nRESET
19
26
18
I/O12
I/O12
IS
This pin may be used either as input, edge
sensitive interrupt input, or output.
General Purpose
I/O
This pin may be used either as input, edge
sensitive interrupt input, or output.
RESET Input
TEST Input
No Connects
This active low signal is used by the
system to reset the chip. The active low
pulse should be at least 1μs wide.
TEST
NC
28
I
This signal is used for testing the chip.
User should normally tie this pin low
externally if the test function is not used.
12
15
16
17
25
No Connect. No trace or signal should be
routed/attached to these pins.
DIGITAL / POWER
+1.8V Core power VDD18
13
+1.8V core power. This pin must have a
1.0μF (or greater) ±20% (ESR <0.1Ω)
capacitor to VSS.
3.3V Power &
VDD33
VSS
6
14
22
3.3V Power & Regulator Input.
Regulator Input.
Ground
SLUG
Ground Reference
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5.2
Buffer Type Descriptions
Table 5.3 USB2242/USB2242i Buffer Type Descriptions
DESCRIPTION
BUFFER
I
Input.
IPU
IS
Input with internal weak pull-up resistor.
Input with Schmitt trigger.
I/O12
I/O200
Input/Output buffer with 12mA sink and 12mA source.
Input/Output buffer 12mA with FET disabled, 100/200mA source only when the FET is
enabled.
I/O12PD
Input/Output buffer with 12mA sink and 12mA source, with an internal weak pull-down
resistor.
O12
Output buffer with 12mA source.
XTAL clock input.
ICLKx
OCLKx
I/O-U
I-R
XTAL clock output.
Analog Input/Output Defined in USB specification.
RBIAS.
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Chapter 6 Pin Reset State Table
Hardware
Firmware
Initialization
Operational
Voltage
Signal (v)
RESET
RESET
VDD33
Time
(t)
VSS
Figure 6.1 Pin Reset States
LEGEND
yes
--
hardware enables function
hardware disables function
hardware disables output driver
hardware enables pullup
z
pu
pd
hardware enables pulldown
hw
hardware controls function, but state is protocol dependent
firmware controls function through registers
hardware supplies power through pin, applicable only to CARD_PWR pins
hardware disables pad
(fw)
VDD
none
Figure 6.2 Legend for Pin Reset States Table
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6.1
36-Pin Reset States
Table 6.1 USB2242/USB2242i Pin Reset States
Post-Reset State
MS Mode
RESET STATE
OUT-
PUT
PU/
PD
IN-
PUT
OUT-
PUT
PU/
PD
IN-
PUT
PIN
PIN NAME
FUNCTION
FUNCTION
8
MS_D7
MS_D6
none
none
none
none
SD_WP
none
none
none
none
none
none
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
z
z
z
z
0
z
z
z
z
z
z
z
z
z
0
0
0
--
--
--
--
MS_D7
MS_D6
MS_D4
MS_D5
MS_SCLK
none
hw
hw
hw
hw
hw
z
pd
pd
pd
hw
hw
--
yes
yes
yes
yes
--
7
5
MS_D4
--
--
4
MS_D5
--
--
30
25
23
20
9
MS_SCLK
NC
--
--
--
--
--
MS_D3
--
--
MS_D3
MS_D2
MS_BS
MS_D1
MS_D0
hw
hw
hw
hw
hw
pd
pd
hw
hw
pd
yes
yes
--
MS_D2
--
--
MS_BS
--
--
10
11
19
26
24
27
29
31
MS_D1
--
--
yes
yes
MS_D0
--
--
GPIO14
pu
pu
pu
--
yes
yes
yes
--
GPIO15
GPIO12 (MS_INS)
GPIO2 / RXD / SDA
GPIO4
--
--
GPIO7 / TXD / SCK /
MS_SKT_SEL
--
--
21
28
18
1
GPIO10 (CARD_PWR)
GPIO
TEST
nRESET
GPIO1
none
z
z
z
0
z
z
z
z
z
z
--
--
--
--
--
--
--
--
--
--
--
yes
yes
--
TEST
nRESET
GPIO1 (LED1)
NC
16
12
17
15
2
--
none
none
none
none
z
z
z
z
--
--
--
--
--
--
--
--
NC
none
--
NC
none
--
NC
none
--
USB+
USB+
USB-
--
3
USB-
--
35
33
32
RBIAS
XTAL1 (CLKIN)
XTAL2
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Chapter 7 DC Parameters
7.1
Maximum Guaranteed Ratings
PARAMETER
SYMBOL
MIN
MAX
UNITS
°C
COMMENTS
Storage
Temperature
T
-55
150
325
4.0
A
Lead
Temperature
°C
V
Soldering < 10 seconds
3.3V supply
voltage
V
V
-0.5
-0.5
DD33,
DDA33
Voltage on
USB+ and
USB- pins
(3.3V supply voltage + 2) ≤ 6
V
Voltage on
GPIO10
-0.5
V
+ 0.3
V
When internal power FET
DD33
operation of this pin is enabled,
this pin may be simultaneously
shorted to ground or any
voltage up to 3.63V indefinitely,
without damage to the device
as long as V
and V
DD33
DDA33
are less than 3.63V and T is
A
o
less than 70 C.
Voltage on any
signal pin
-0.5
-0.5
-0.5
V
+ 0.3
+ 0.3
V
V
V
DD33
Voltage on
XTAL1
4.0
Voltage on
XTAL2
V
DD18
Note 7.1 Stresses above the specified parameters may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at any condition above
those indicated in the operation sections of this specification is not implied.
Note 7.2 When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power
supplies exhibit voltage spikes on their outputs when the AC power is switched on or off.
In addition, voltage transients on the AC power line may appear on the DC output. When
this possibility exists, it is suggested that a clamp circuit be used.
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Voltage
VDD33
tRT
3.3V
100%
90%
10%
VSS
t90%
Time
t10%
Figure 7.1 Supply Rise Time Model
7.2
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
COMMENTS
Operating
Temperature
Commercial Part
Industrial Part
T
0
70
85
3.6
°C
°C
V
A
T
-40
3.0
A
3.3V supply voltage
V
V
DD33,
DDA33
3.3V supply rise time
t
0
400
5.5
μs
RT
Voltage on
USB+ and USB- pins
-0.3
V
If any 3.3V supply voltage drops
below 3.0V, then the MAX
becomes:
(3.3V supply voltage) + 0.5 ≤ 5.5
Voltage on any signal
pin
-0.3
V
V
DD33
Voltage on XTAL1
Voltage on XTAL2
-0.3
-0.3
V
V
V
V
DDA33
DD18
Note 7.3 A 3.3V regulator with an output tolerance of 1% must be used if the output of the internal
power FET’s must support a 5% tolerance.
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7.3
DC Electrical Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
I, IPU, IPD Type Input Buffer
Low Input Level
V
0.8
V
V
TTL Levels
ILI
High Input Level
V
2.0
IHI
Pull Down
PD
PU
72
58
μA
μA
Pull Up
IS Type Input Buffer
Low Input Level
High Input Level
V
0.8
V
V
TTL Levels
ILI
V
2.0
IHI
Hysteresis
V
420
mV
HYSI
ICLK Input Buffer
Low Input Level
High Input Level
Input Leakage
V
0.5
V
V
ILCK
V
1.4
-10
IHCK
I
+10
μA
IL
V
= 0 to V
DD33
IN
Input Leakage
(All I and IS buffers)
Low Input Leakage
I
-10
-10
+10
+10
μA
V
V
= 0
IL
IN
High Input Leakage
I
μA
= V
IH
IN
DD33
O12 Type Buffer
Low Output Level
High Output Level
Output Leakage
V
0.4
V
V
I
V
= 12mA @
OL
OL
OH
OL
= 3.3V
DD33
V
V
- 0.4
I
V
= -12mA @
OH
DD33
= 3.3V
DD33
I
-10
+10
μA
V
= 0 to V
IN DD33
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PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
I/O12, I/O12PU & I/O12PD Type
Buffer
Low Output Level
High Output Level
Output Leakage
V
0.4
V
V
I
V
= 12mA @
OL
OL
OH
OL
= 3.3V
DD33
V
V
- 0.4
I
V
= -12mA @
OH
DD33
= 3.3V
DD33
I
-10
+10
µA
V
= 0 to V
IN DD33
Pull Down
Pull Up
PD
PU
72
58
μA
μA
IO-U
I-R
I/O200
Integrated Power FET for
GPIO10
High Output Current Mode
I
I
200
100
mA
mA
Vdrop
Vdrop
= 0.46V
= 0.23V
OUT
FET
Low Output Current Mode
OUT
FET
On Resistance
R
t
2.1
Ω
I
= 70mA
FET
DSON
Output Voltage Rise Time
Supply Current Unconfigured
Supply Current Active
Full Speed
800
90
μs
C
= 10μF
DSON
LOAD
I
80
mA
CCINIT
I
I
110
135
140
165
mA
mA
CC
CC
High Speed
Supply Current Suspend
Industrial Temperature Suspend
I
350
350
700
900
µA
µA
CSBY
I
CSBYI
Note 7.4 Output leakage is measured with the current pins in high impedance.
Note 7.5 See The USB 2.0 Specification, Chapter 7, for USB DC electrical characteristics
Note 7.6 RBIAS is a 3.3V tolerant analog pin.
Note 7.7 Output current range is controlled by program software, software disables FET during short
circuit condition.
Note 7.8 The assignment of each Integrated Card Power FET to a designated Card Connector is
controlled by both firmware and the specific board implementation. Firmware will default to
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Note 7.9 The 3.3V supply should be at least at 75% of its operating condition before the 1.8V supply
is allowed to ramp up.
7.4
Capacitance
T
= 25°C; fc = 1MHz; V
V
= 1.8V
A
DD, DDP
Table 7.1 Pin Capacitance
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
TEST CONDITION
Clock Input Capacitance
C
2
pF
All pins (except USB pins
and pins under test) are tied
to AC ground.
XTAL
Input Capacitance
Output Capacitance
C
10
20
pF
pF
IN
C
OUT
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Chapter 8 AC Specifications
8.1
Oscillator/Clock
Crystal: Parallel Resonant, Fundamental Mode, 24 MHz ± 100ppm.
External Clock: 50% Duty cycle ± 10%, 24 MHz ± 100ppm, Jitter < 100ps rms.
XTAL1
(CS1 =
CB + CXTAL
)
C1
1Meg
Crystal
CL
C2
XTAL2
(CS2 =
CB + CXTAL
)
Figure 8.1 Typical Crystal Circuit
Note:
C
equals total board/trace capacitance.
B
(C1 + CS1) x (C2 + CS2)
(C1 + CS1 + C2 + CS2)
CL
=
Figure 8.2 Formula to Find Value of C and C
1
2
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Chapter 10 GPIO Usage
Table 10.1 USB2242/USB2242i GPIO Usage (ROM Rev 0x00)
NAME
ACTIVE LEVEL
SYMBOL
DESCRIPTION AND NOTE
LED indicator
GPIO1
GPIO2
H
H
LED1
RXD / SDA
Receive Port of Debugger / Serial
EEPROM Data
GPIO4
GPIO7
USER
H
GPIO
User defined
TXD / SCK / MS_SKT_SEL
Transmit Port of Debugger / Serial
EEPROM Clock / Memory Stick Socket
(1 = 8 bit; 0 = 4 bit)
GPIO10
GPIO12
GPIO14
GPIO15
L
CRD_PWR
MS_INS
GPIO
Card Power Control
Memory Stick Card Insertion
User defined
L
USER
USER
GPIO
User defined
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