AN.No.G1216B1N000-3D0E
LIQUID CRYSTAL DISPLAY MODULE
G 1 2 1 6 B 1 N 0 0 0
USER’S MANUAL
Seiko Instruments Inc.
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AN.No.G1216B1N000-3D0E
CONTENTS
1.
GENERAL
General.....................................................................................................
LC Panel Life Time...................................................................................
Dimensions...............................................................................................
2.
CIRCUIT CONFIGURATION
3.
OPERATING INSTRUCTIONS
Terminal Functions...................................................................................
Timing Characteristics..............................................................................
- ii -
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AN.No.G1216B1N000-3D0E
1. GENERAL
1.1 General
The G1216 is a very thin LCD module on which a full-dot matrix LCD panel and a CMOS IC driver are
integrated. The LCD panel used here features wide viewing angle and high contrast. This full dot
configuration allows a wide variety of patterns to be displayed depending upon the input data. The
display position is the intersection point of the matrix transparent electrodes. This prevents display
distortion and displacement. Incorporating a display RAM and a display timing signal generator into
the G1216 allows for direct connection with the MPU circuit without using an LCD controller.
1.2 Features
128 64 full dot matrix configuration
1/64 duty, 1/9 bias
Two 4096-bit internal display data RAMs
An internal display timing signal generator
8-bit parallel interface
Instructions:
Display Data Read/Write, Display ON/OFF, Display Start Line, X-Address (Page) Set, Y- Address
Set, and Status Read.
Three types of power supply: VDD=+5 V, VLC , LEDA (LED anode)
Transflective, gray mode
Positive display
Display data “H”: Display ON: blue display color
Display data “L”: Display OFF: gray background
A wide operating temperature range
A built-in LED backlight (color: yellow-green)
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AN.No.G1216B1N000-3D0E
1.3 Absolute Maximum Ratings (excluding LED backlight)
Vss = 0 V
Item
Symbol
VDD
Conditions
Min.
0.3
Max.
7.0
Unit
V
Power supply
Ta = 25 C
-
voltage
VLC
VIN
50 10%RH
VDD -19.0
-0.3
VDD + 0.3
VDD+ 0.3
V
V
Input voltage
Operating
Topr
Tstg
65%RH
-20
-30
+70
+80
C
C
temperature
Storage
temperature
Storage
humidity
48 hrs
1000 hrs
+20
+20
+85
+65
%RH
%RH
1.4 Mechanical Characteristics
Item
Standard
Dot configuration
128 64 dot
Module dimensions ( H
Viewing area ( H V )
V
T )
[ mm ] 75.0 52.7 8.9
[ mm ] 60.0 32.5
[ mm ] 55.01 27.49
[ mm ] 0.4 0.4
Active display area ( H V )
Dot dimensions ( H V )
Dot pitch ( H V )
Weight
[ mm ] 0.43 0.43
[ g ] 45 max.
H : Horizontal
V : Vertical
T : Thickness (max.)
1.5 Electrical Characteristics (excluding LED backlight)
VDD = 5 V 5%, VSS = 0 V, Ta = -20 C to +70 C
Item
Symbol
Conditions
Min.
0.7V
Typ.
Max.
Unit
Input
voltage1
High
Low
High
Low
High
Low
VIHC
VILC
VIHT
VILT
VOH
VOL
VDD
VLC
IDD
VDD
0.3VDD
VDD
V
V
DD
0
Input
voltage2
2.0
0
V
0.8
V
IOH =- 205 A
IOL = 1.6 mA
2.4
V
Output
voltage3
0.4
5.25
-3.0
3.0
V
4.75
5.00
-8.0
2.0
V
Power supply voltage
-12.0
V
VDD=5 V, Ta = 25 C
VLC = 8.0
mA
mA
HZ
Current
consumption4
ILC
1.8
3.0
fFRM
71.4
Frame frequency
1
Applied to RST.
2
3
4
Applied to DB0 to DB7, E, R/W, D/I, CS1 and CS2.
Applied to DB0 to DB7.
Display patterns: checkered patterns.
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AN.No.G1216B1N000-3D0E
1.6 Optical Characteristics
1/64 duty, 1/9 bias, fFRM = 71.4 Hz, Vopr = VDD -VLC , LED backlight: OFF
Item
Sym.
Conditions
Temp.
Min.
Typ.
Max.
Unit
Remark
q1
q2
¾
15
30
¾
¾
¾
¾
¾
¾
¾
-15
¾
C ³ 2.0
Æ = 0°
25°C
Vopr=13.0 V
q2-q1
q1
¾
Viewing angle
Degree Refer to notes
1 and 2
-20
¾
C ³ 2.0
Æ = 270°
Vopr=13.0 V
q2
25°C
50
70
q2-q1
¾
q = 0°
Æ = 0°
Contrast
C
25°C
25°C
-20°C
2.5
3.5
¾
¾
Note 3
Note 4
Vopr=13.0 V
q = 0°
ton
toff
ton
toff
¾
¾
¾
¾
40
100
630
2300
100
200
Æ = 0°
Vopr=13.0 V
Response time
ms
q = 0°
1000
3500
Æ = 0°
Vopr=14.0 V
Measuring instrument : Canon illuminometer LC-3S
Note 1: Definition of angle q and Æ
Note 2: Definition of viewing angles q 1
and q 2
Light
(reflective LCD)
Z (q=0°)
Cmax.
Sensor
Contrast C
q2
q
q1
Y’(Æ=180°)
2.0
LCD panel
X’
X (Æ=90°)
q1
Viewing angle
q2
Æ
Z’
Remark: The optimum viewing angle by visual
inspection and angle q at Cmax do
not always match.
Y (Æ=0°)
(q=90°)
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Note 4: Definition of response time
Note 3: Definition of contrast (C)
Vopr
(V)
Brightness of non-selected dot (reflection) B2
C =
Brightness of selected dot (reflection)
B1
Brightness for selected
dot
1/fFRM
B2
(%)
Non-selected
status
Non-selected status
(display OFF)
Selected status
(display ON)
Brightness
curve for non-
selected dot
Light
10%
Brightness
(reflection)
90%
100%
Brightness
Dark
B1
ton
toff
0
Operating
voltage(V)
Vopr : Operating voltage
fFRM : Frame frequency
ton : Response time (rise)
tof : Response time (fall)
Note: Measurement must be made using a transmissive LCD panel.
1.7 LC panel life time
Item
Conditions
Standard
Unit
hrs
25 C 10 C
° ±
°
Life time1
100,000 or more
<65%RH
1
Definition of life time: the time up to occurrence of any of the following:
Contrast reduces to 30% of the initial value.
Current consumption becomes three times the initial value.
Orientation deteriorates significantly.
ž
ž
ž
ž
The display malfunctions.
1.8 LED backlight characteristics
(1) Absolute maximum ratings
Item
Symbol
Standard
Unit
DC forward current
DC reverse voltage
Allowable dissipation
Operating temp. range
Storage temp. range
IF
200*
8
mA
V
VR
PD
860
mW
°C
Topr
Tstg
-20 to +70
-30 to +80
°C
*
Forward current reduction characteristics: The absolute maximum rating of the forward current
varies depending on ambient temperature.
200
IF ( mA )
50
-20
25
70
Ta(°C)
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AN.No.G1216B1N000-3D0E
(2) Electrical and optical characteristics
Ta = 25 C
°
Item
Meas. condition
Min.
3.8
¾
Typ.
4.1
¾
Max.
Unit
Symbol
VF
Forward voltage
Reverse current
IF=90 mA
VR=8 V
4.4
0.9
V
IR
mA
(3) LED backlight connection diagram
LEDA
Number of LED
chips=20
LEDC
(4) Brightness (panel upper side)
Item
Symbol
Min.
1.0
Typ.
2.0
Max.
Unit
nit
Surface brightness
BP
¾
(Center of LCD panel)
Measurement conditions and a measuring instrument are:
Ta=25°C±3°C
30 to 85%RH
ž
ž
ž
ž
ž
ž
ž
ž
IF= 90 mA
fFRM=71.4 Hz
VLC: Optimum LC drive voltage
Display OFF (Entire display data=“L”)
Measured 30 minutes after LED lights
Measuring instrument: BM - 7 (TOPCON)
(5) Life time
Item
Measurement conditions
Standard
Unit
hrs
Ta=25 C 10 C
° ±
°
Life time1
50,000 or more
IF=90 mA
1 Definition of life time: The time until the brightness decreases to one half the initial
brightness.
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AN.No.G1216B1N000-3D0E
1.9 Dimensions
Unit: mm
General dimensional tolerance:±0.5
Figure 1 Dimensions
No. Sym.
I/O terminal functions
No. Sym.
Functions
Functions
1
2
VDD
VSS
Power supply voltage: +5.0 V
GND: 0 V
11
12
13
14
15
16
17
18
19
DB7
CS1
CS2
RST
R/W
D/I
Data bus (MSB)
Chip select (1)
Chip select (2)
Reset
3
VLC
LC drive voltage
Data bus (LSB)
Data bus
4
DB0
DB1
DB2
DB3
DB4
DB5
DB6
5
Read/Write
Data/Instruction
Enable
6
Data bus
7
Data bus
E
8
Data bus
FGND Frame ground1
9
Data bus
LEDA LED anode
10
Data bus
20 LEDC LED cathode
1
FGND is connected to the metallic frame of the module. Use this frame when grounding.
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AN.No.G1216B1N000-3D0E
2. CIRCUIT CONFIGURATION
2.1 Block Diagram
This product consists of two HD61202 segment drivers, an HD61203 common driver and a bias
voltage generator. Figure 2 shows the block diagram.
DB0 to DB7
RST, R/W, D / I, E
CS2
CS1
VLC
Va, Vc, Vd, Vf
Bias Voltage
Generator
Va
Vb
Ve
Vf
VDD
FRM
Segment Driver 1
Segment Driver 2
VSS
M
CL2
1
64
64
2
Common Driver
64
128 64 full dot matrix LCD
LEDA
LEDC
LED Backlight
Figure 2 Block Diagram
2.2 Segment Drivers (HD61202)
The segment driver is a 64 drive output CMOS IC. The G1216 is driven with the panel divided into
two right and left displays. A segment driver controls the divided screen. 8 bits of data transmitted
from the MPU are saved in the internal display RAM, and the segment signal is generated to drive the
LC. 1 bit of display RAM data corresponds to 1 dot lighting or non-lighting on the LC panel.
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AN.No.G1216B1N000-3D0E
2.2.1
RST
Block Diagram (Segment Driver)
CS
DB0 to DB7
R/W
D/I
E
VDD
VSS
VLC
8
Segment Driver
Interface Control
Input and Output Buffer
8
Busy Flag
8
Output
Input
Instruction Register
Register
Register
9
6
8
Display Start Line
Register
X, Y-Address
Counter
Display ON/OFF
8
9
6
Z-Address
Counter
Display Data RAM
4096 bit
6
64
Display Data Latch
64
4
LC Driver
Va
Vc
Vd
Vf
M
1
2
CL
FRM
Y1 Y2
Y64
Figure 3 Segment Driver
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AN.No.G1216B1N000-3D0E
2.2.2 Functions and Operations of Main Blocks
(1) Interface Control Unit
The interface control unit consists of the following blocks:
Input and output buffer
Input and output register
Instruction register
The above blocks are selected according to the following combinations of R/W and D/I signals:
D / I
1
R / W
1
Functions
Output Register Read
Internal Operation (Display Data RAM
Output Register)
1
0
Input Register Write
Internal Operation (Input Resister
Display Data RAM)
0
0
1
0
Busy Check and Status Read
Instruction
Input and output buffer
The data is transmitted through eight data buses (DB0 to DB7).
DB7 ....... MSB (most significant bit)
DB0 ...... LSB (least significant bit)
The data can be input and output only when the Chip Select is selected. Therefore, if the Chip Select
is not selected, the internal condition remains unchanged and instruction will not be executed, even
when changing the signal of the input terminals excluding the RST (reset) terminal.
Note that the RST operates regardless of CS1 and CS2.
Input and output register
This product is provided with an input register and an output register so that the product can interface
with MPUs having speed differing from the internal operation.
Input register
The input register is a register that is used for temporarily storing the data to be written in the display
data RAM. The data to be written from the MPU to the input register will be automatically written in
the display data RAM through internal operation.
When the Chip Select is selected and R / W = 0, D / I =0, the data is written in the register,
synchronized with the fall of signal E.
Output register
The output register is a register that is used for temporarily storing the data to be read from the
display data RAM.
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AN.No.G1216B1N000-3D0E
In order to read the content of the output register, the Chip Select must be selected, D/I must be 1,
and R/W must be 1. When executing the “Read” instruction, the contents of the output register
stored at that time are output during the time that “E” is 1. When “E” falls, display data of the
currently indicated address is written in the output register. After that, the address advances by
one.
The contents of the output register are rewritten by the Read instruction. The data is retained by the
address set or other instructions. Accordingly, when performing the address set, and next executing
the Read instruction, the data of the specified address is not output and the data of the address
which is specified is output at the second data read time. Therefore, when setting the address, a
dummy read is needed once. See Figure 4.
D / I
R/W
E
Address
N+2
N
N+1
Output Register
N+1 address data
N address data
Data Read
(N address
data)
Busy
Check
Address
Set
(Address
N)
Data Read
(dummy)
Data Read
(N+1 address
data)
Busy
Check
Busy
Check
Busy
Check
DB0 to DB7
Figure 4 Read Timing
(2) Busy flag
The status when busy flag is “1” means that the module is operating internally. Instructions other than
he Status Read are not available at this time. The busy flag is output to DB7 by the Status Read
instruction. Ensure that the busy flag is “0” before executing the instruction.
E
BUSY
T BUSY
1
F
3
F
T BUSY
F is frequency of 1 or 2 (1 / 2 the source oscillation frequency of HD61203): 215 kHz typ.
Figure 5 Busy Flag
(3) Display ON/OFF Flip/Flop
The display ON/OFF Flip/Flop is a flip-flop function that determines whether the display data
corresponding to the RAM data is output to the segment on the LCD (ON status ) or goes to all nonlit
status regardless of the RAM data (OFF status). This is controlled by the display ON/OFF instruction.
When the RST signal becomes “0,” the display goes to OFF status. This flip-flop status is output to DB5
by the Status Read instruction.
Even when performing display ON/OFF, the data inside the RAM is not affected.
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AN.No.G1216B1N000-3D0E
(4) Display start line register
The display start line register is a register which determines the line address (see Figure 6) for which
data is displayed on the top line of the LCD screen when displaying the contents of the display data
RAM on the LCD screen. It is also used to scroll the display. The 6 bit (0 to 63) display start line
information is written in this register by the Display Start Line Set Instruction.
The contents of this register are transmitted to address counter Z at “H” level of the FRM signal
(common driver output) which indicates the display start on the screen.
(5) Z-address counter
The Z-address counter generates the address to output the display data synchronized with the
common signal. This is a 6-bit counter which counts at the fall of the CL signal (common driver output).
The contents of the display start line register are preset to the Z-address counter at “H” level of the
FRM signal (common driver output).
(6) Display data RAM
The display data RAM is a RAM that stores the display dot data. 1 bit of RAM data corresponds to
lighting (data=1) or non-lighting (data = 0) of 1 dot of the display on the LCD screen. Figure 6 shows
the relationship between the address and data inside the RAM on either the right or left screen (64 64
dots). In this case, the display start line is 0.
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AN.No.G1216B1N000-3D0E
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
Display pattern
(Display start line: 0)
Common driver
output
X1 to X64
COM62
COM63
COM64
Segment driver output
Y1 to Y64
1 2 3 4 5
62 63 64
Line address
Line 0
DB0(LSB)
DB1
Data inside
display RAM
0 1 1 1 0
1 0 0 0 1
1 0 0 0 1
1 0 0 0 1
1 1 1 1 1
1 0 0 0 1
1 0 0 0 1
0 0 0 0 0
0
0 0 1
0 0 1
Line 1
0 0 1 Line 2
1 0 1
X- address
(page)
DB2
DB3
X=0
DB4
0 1 1
DB5
0 0 1
DB6
0 0 1
DB7(MSB)
0 0 0
0
0 0
X=1
X=2
0 1 0 0
0 1 0 0 0
1 1 1 1 1
0 0 0 0 0
0
0 0 0
0 0 0
0 0 0
X=7
Line 62
Line 63
Y0 Y1 Y2 Y3 Y4
Y61Y62Y63
Y-address
Figure 6 Relationship Between Display and Data Inside Display RAM
(7) X, Y- address counter
X, Y-address counter is a 9-bit counter which gives the address of the internal display data RAM. It is
necessary to set the X-address counter of the three upper bits, and the Y-address counter of the six
lower bits using differing instructions.
X-address counter
Address counter X is a simple register that is not provided with a count function. The address is set
by instruction.
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AN.No.G1216B1N000-3D0E
Y-address counter
This counter sets the address by instruction and is automatically advanced by the read/write
operation. Counting is performed by looping the values 0 to 63.
2.3 Common driver (HD61203)
The common driver is a 64 drive output CMOS IC. Incorporating an oscillation circuit, this driver
generates the common signal and timing signals (LC AC drive control, and one-frame timing signal)
necessary for the LC display, and controls the display by supplying the timing signals to the segment
drivers.
2.4 Bias voltage generator
Six levels of standard voltage Va to Vf are applied to the drivers as a bias voltage. This voltage is
generated by resistance division of Vopr and driven by a voltage follower through an operational
amplifier.
VDD
Va
C
R1
Vb
Vc
Vd
Ve
+
C
C
R1
R2
+
+
Vopr
C
C
R1
R1
+
Operational
Amplifier
Vf
VLC
1 / 9 bias: R2= (9 4) R1= 5 R1
Figure 7 Bias Voltage Generator
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AN.No.G1216B1N000-3D0E
3. OPERATING INSTRUCTIONS
3.1 Terminal Functions
Table 1 Terminal Functions
Signal
I/O
I/O
Functions
QTY
Destination
to
DB0
DB7
8
MPU
MPU
Common terminal for tristate input and output, and data bus.
Enable
E
1
Input
Write (R/W=0):Latches data of DB0 to DB7 at the fall of E.
Read (R/W=1):Outputs data to DB0 to DB7 while “E” keeps a
high level.
Read/Write selection
R/W
1
Input
MPU
R/W=1: When E=1 and CS1=0 or CS2=0, the data is output
to DB0 to DB7 and read is available by MPU.
R/W=0: When CS1=0 or CS2=0, DB0 to DB7 are ready for
receiving the input.
Data/Instruction selection
D/I=1: Indicates that the data in DB0 to DB7 is the display
D/I
1
2
Input
Input
MPU
MPU
data.
D/I=0: Indicates that the data in DB0 to DB7 is the instruction
code.
Chip select input. Data input and output is possible under
the following status:
CS1, CS2
LCM display screen
CS1
0
CS2
0
Terminal No.
CS1
CS2
Status
CS1: Controls the LCM left half display screen (SEG1 to
SEG64).
CS2: Controls the LCM right half display screen (SEG65 to
SEG128).
Reset signal
RST
1
Input
MPU
Setting the RST signal to a low level allows for initial setup.
(1) ON /OFF register: 0 setup (display OFF)
(2) Display start line register: 0 line setup (display starts
from 0 line)
The setup status is retained until the status is changed by an
instruction after reset is released.
VDD
VSS
1
1
1
1
1
1
Power
Power
Power
Power
Power
Power terminal for logic (+5 V)
GND terminal (0 V)
VLC
Power terminal for LC drive
LED backlight anode terminal
LED backlight cathode terminal
Frame ground1
LEDA
LEDC
FGND
1
FGND terminal is connected to the metallic frame of the module. Use this terminal when
grounding the frame.
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3.2 Timing Characteristics
Item
E cycle time
Symbol
tCYC
PWEH
PWEL
tr
Min.
1000
450
Typ. Max. unit
Note
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1
ns
ns
ns
E pulse width (H)
E pulse width (L)
E rise time
450
25
25
ns
ns
ns
ns
ns
ns
ns
ns
tf
E fall time
tAS
140
10
Address setup time
Address hold time
Data setup time
tAH
tDSW
tDDR
tDHW
tDHR
200
320
2, 3
1
Data delay time
10
20
Data hold time during write
Data hold time during read
2
Note 1: When the MPU writes:
Note 2: When the MPU reads:
tCYC
tCYC
2.0V
0.8V
2.0V
0.8V
PWEH
PWEH
tf
E
PWEL
2.0V
E
PWEL
tr
tf
tr
tAH
tAS
tAS
tAS
tAS
2.0V
0.8V
R / W
R / W
tAH
tAH
0.8V
tAH
2.0V
0.8V
CS1, CS2
D/I
2.0V
0.8V
CS1, CS2
D/I
tDSW
tDHW
tDDR
tDHR
2.4V
0.4V
2.0V
0.8V
DB0 to DB7
DB0 to DB7
Note 3: Load circuits (DB0 to DB7)
RL = 2.4 k
R = 11 k
RL
D1
Test point
D2
D3
D4
C = 130 pF (including jig capacity)
Diodes D1 to D4 are 1S2074 H .
C
R
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3.3 Reset Function
Setting the RST terminal to a low level when the power is on allows for initial setup.
Display OFF
Display start line register: Set address 0.
While the RST remains at a low level, instructions other than the status read cannot be accepted.
Execute other instructions after confirming that DB4=0 (reset release) and DB7=0 (ready) , using the
status read instruction.
The power conditions for power-on initial setup are as follows:.
Item
Symbol
tRST
Min
1.0
Typ.
Max
200
unit
s
Reset time
Rise time
ns
tr
4.5V
VDD
tr
tRST
0.7VDD
0.3VDD
RST
If the RESET is executed during operation, retention of the contents of all registers (excluding an
ON/OFF register) and the RAM is not guaranteed. Always set them again.
- 16 -
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3.4 Instructions
3.4.1 General
Instructions are listed on Table 2. Instructions other than the Status Read instruction will not be
executed if they are sent while another instruction is already being executed. The busy flag is “1”
when executing the instruction. Check whether or not the flag is “1” before transmitting the
instructions from the MPU.
Table 2 List of Instructions
Code
Instruction
Function
R/W D / I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Turns ON / OFF total display. Data and
internal status in the display RAM remain
unchanged.
Display
1
2
3
4
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
1
1
1
1
1
1/0
ON / OFF
1: ON 0 : OFF
Determines the RAM line to be displayed on the
top line (COM1) on the display.
Display start
line
Display start lines
( 0 to 63 )
X-address
(page) set
X-address(page) Sets the X-address of the RAM (page) in the
1
1
1
(0 to 7)
X-address (page) register.
Set Y-address of the RAM in the Y-address
counter.
Y-address
set
Y-address
( 0 to 63 )
Reads the status.
R
E
S
E
T
B
U
S
Y
RESET 1: Reset 0: Normal
ON/OFF 1: Display OFF 0: Display ON
ON
/
OFF
Status read
5
6
7
1
0
1
0
1
1
0
0
0
0
0
BUSY
1: during internal operation
0: READY status
0
Writes data DB (LSB) to
Accesses the
RAM in which
DB7 (MSB ) on the data
Display data
write
bus into the display RAM. address has been
specified
Write Data
Read Data
beforehand. After
that the Y-address
Reads data DB0 (LSB) to
DB7 (MSB) from the
display RAM into the data
bus.
advances by one.
Display data
read
BUSY
T
Note: The BUSY time varies depending upon the frequency F (:215 kHz (typ.) ) of 1, 2 (1/F
3/F ).
3.4.2 Detailed explanation
(1) Display ON/OFF
R/W D/I DB7
DB0
D
Code
0
0
0
0
1
1
1
1
1
Turns the display ON when D=1, and OFF when D=0. When the display is turned OFF by D=0, the
original display appears if D is set to 1 because the display data is retained in the display data RAM.
- 17 -
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(2) Display start line
Code
R/W D/I DB7
DB0
A
0
0
1
1
A
A
A
A
A
Lower bits
Upper bits
Sets the display data RAM line address expressed with binary AAAAAA in the display start line
register. When displaying the content of the display data RAM, the display data on the line addresses
which are set in the register is displayed on the top line on the LCD screen. For address configuration
inside the display data, refer to Figure 6. Figure 8 shows display examples of start lines 0 to 3.
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
-
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
-
-
-
-
-
COM59
COM60
COM61
COM62
COM63
COM64
COM59
COM60
COM61
COM62
COM63
COM64
Display start line=0
Display start line=1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
-
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
-
-
-
-
-
COM59
COM60
COM61
COM62
COM63
COM64
COM59
COM60
COM61
COM62
COM63
COM64
Display start line =2
Display start line=3
Figure 8 Relationship Between Display Start Lines and Displays
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(3) X-address (page) set
R/W D/I DB7
DB0
A
Code
0
0
1
0
1
1
1
A
A
Upper bits
Lower bits
The display data RAM “X” address (page) which is expressed with binary AAA is set in the X-address
register. Following write/read operations from the MPU are performed on the specified X-address
(page) until the next X-address (page) set is performed. The configuration of display data RAM and
X-address is shown in Figure 9.
R/W D/I DB7
DB0
A
Code
0
0
0
1
A
A
A
A
A
Upper bits
Lower bits
(4) Y-address set
The display data RAM Y- address which is expressed with binary AAAAAA is set in the Y-address
counter. After that the Y-address counter advances by one each time write/read is performed from
the MPU. The configuration of the display data RAM and Y-address is shown in Figure 9.
Y-address
0
1
2
3
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
61 62 63
DB0
to
Page 0
Page 1
X=0
X=1
DB7
DB0
to
DB7
DB0
to
Page 6
Page 7
X=6
X=7
DB7
DB0
to
DB7
Figure 9 Display Data RAM Address Configuration
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(5) Status read
R/W D/I DB7
DB0
0
Code
1
0
BUSY
0
ON/OFF RESET
0
0
0
BUSY:
When BUSY=1, it means that the the module is operating internally and the next instruction is
not accepted until BUSY=0. After confirming that BUSY=0, it is necessary to perform the
next write.
ON/OFF: Indicates that the display is OFF when ON/OFF=1.
Indicates that the display is ON when ON/OFF=0.
RESET: Indicates that initial setup is performed by the RST signal.
Indicates that the initialization is being performed when RESET=1 and instructions other than
the Status Read instruction are not accepted.
When RESET=0, initialization is completed and operation status is normal.
(6) Display data write
R/W D/I DB7
DB0
D
Code
0
1
D
D
D
D
D
D
D
Upper bits
Lower bits
Writes 8-bit binary data DDDDDDDD in the display data RAM. After the write is completed, the Y-
address is automatically advanced by one
(7) Display data read
R/W D/I DB7
DB0
D
code
1
1
D
D
D
D
D
D
D
Upper bits
Lower bits
Read 8-bit binary data DDDDDDDD from the display data RAM. After read is performed, the Y-
address is automatically advanced by one. A dummy read is necessary once, immediately after the
address set is completed. For details, refer to segment driver output register section.
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AN.No.G1216B1N000-3D0E
3.5 Contrast Adjustment and Power Supply Example
The LC panel viewing angle and display screen contrast are greatly affected by the ambient
temperature. The recommended LC drive voltage (Vopr) at each temperature is given below. Vopr
is a value at which the best display is visually obtained. This value does not always correspond to the
value at which the best contrast (Cmax.) is obtained. A contrast adjustment circuit example is shown
below:
Vopr= VDD - VLC
Temperature ( C)
20
0
25
50
70
°
-
Voltage (Vopr)
13.5
13.0
12.5
11.5
10.5
VDD
VSS
RA=10 kW
C1
5V
RB=1.2 kW
RV (variable resistor)
=10 kW
RA
RV
RB
C2
12 V
VLC
C1, C2=10 mF
G1216
Figure 10 Contrast Adjustment
3.6 LED Backlight Driver Examples
(1) Example 1
A basic LED backlight driver example is shown in Figure 11.
LEDA
R=30W, (³ 1/4W)
VIN = +5V
LEDC
Figure 11 LED Backlight Driver Example 1
G1216
Where resistance “R” is the limit resistance of the LED forward current. The forward current depends
upon the temperature. Especially, it must be decreased at high temperature. For temperature
dependence, refer to forward current reduction characteristics described in 1.8 (1). The operating
temperature for the G1216 ranges from - 20°C to +70°C. It is necessary to determine limit resistance
“R” so that the forward current becomes 50 mA or lower at +70°C.
Forward voltage VF at each temperature of the LED backlight is shown in Table 3.
Table 3 Forward Voltage At Temperatures
Temperature (Ta)
- 20°C
Conditions
IF=90 mA
IF=90 mA
IF=50 mA
VF min.
3.9 V
3.8 V
3.5 V
VF typ.
4.3 V
4.1 V
3.7 V
VF max.
4.6 V
+25°C
4.4 V
+70°C
3.9 V
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Limit resistance “R” is calculated using the following equation. The resistance becomes the value
shown in Figure 11.
VIN =Input voltage (power voltage)(V)
VF =LED forward voltage (V)
IF =Allowable LED forward current (A)
VIN VF
-
R=
( )
W
IF
For this resistance value, the forward current becomes lower than 50 mA at 25°C. The surface
brightness of the LED backlight varies with the forward current. See Figure 12. Compared with 1.8 (4)
brightness (IF=90 mA), the brightness is about 40%.
1.2
1.0
0.8
Relative
brightness
0.6
0.5
0.4
0.2
Forward current:
IF(mA)
30
40 50 60 70 80 90 100 110
Figure 12 Forward Current-Brightness Characteristics (Ta=25°C)
(2) Example 2
When you want to keep the brightness (2 nit) at 25°C, use a thermosensitive element, like a thermistor,
and a transistor as shown in Figure 13. Set the thermosensitive element to about IF=90 mA at 25°C
and configure it so that “IF” will be reduced as the temperature rises.
LEDA
R2
LEDC
Tr
VIN
G1216
R3
Thermistor
R1
R4
Figure 13
LED Backlight Driver Example 2
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AN.No.G1216B1N000-3D0E
3.7 MPU Connection Diagram
Z80A
Z80 PIO
D0 to D7
G1216
D0 to D7
A0 to A7
DB0 to DB7
Decoder
A0 to A15
CE
B0
B1
B2
B3
B4
B5
E
A0
A1
C / D
A / B
R/W
D/I
RD
IORQ
M1
RD
IORQ
M1
RST
CS1
INT
INT
CS2
VDD
VSS
VLC
Figure 14 Example of Connection to Z80A
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4. PRECAUTIONS
Safety
If the LCD panel is damaged, be careful not to get the liquid crystal in your mouth. If the liquid
crystal touches your skin or clothes, promptly wash it off using soap and plenty of water.
Handling
Avoid static electricity, as it will damage the CMOS LSI.
The LCD panel is made of plate glass. Do not hit or crush it.
Do not remove the panel or frame from the module.
The polarizer of the display is very fragile. Handle it very carefully.
Mounting and design
Mount the module by using the specified mounting parts and holes.
To protect the module against external pressure, place a transparent plate (e.g., acrylic or glass)
on the module, leaving a small gap between the display surface and transparent plate.
Small gap
Exterior face
Example
✩
Transparent plate
Module
Screw
Design the system so that no input signal is given unless the power-supply voltage is applied.
Keep the module dry. Avoid condensation to prevent the transparent electrodes from being
damaged.
Storage
Store the module in a dark place, where the temperature is 25 C 10 C and the relative humidity
below 65%.
Do not store the module near organic solvents or corrosive gases.
Keep the module (including accessories) safe from vibration, shock and external pressure.
Cleaning
Do not wipe the polarizer with a dry cloth, as it may scratch the surface.
Wipe the module gently with a soft cloth soaked with a petroleum benzine.
Do not use ketonic (ketone) solvents (ketone and acetone) or aromatic solvents (toluene and
xylene), as they may damage the polarizer.
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AN.No.G1216B1N000-3D0E
INDEX
- A -
- B -
Active display area ............................................................................. 2
Bias voltage generator ................................................................. 7, 13
Block diagram................................................................................. 7, 8
Busy flag....................................................................................... 8, 10
- C -
Chip select................................................................................ 6, 9, 14
Cleaning ........................................................................................... 24
Common driver............................................................................. 7, 13
Contrast........................................................................................ 3, 21
Contrast adjustment ......................................................................... 21
Current consumption.......................................................................... 2
- D -
Definition of contrast........................................................................... 4
Definition of response time................................................................ 4
Definition of viewing angles................................................................ 3
Display data RAM................................... 1, 8, 9, 11, 12, 17, 18, 19, 20
Display data read ....................................................................... 17, 20
Display data write....................................................................... 17, 20
Display ON/OFF........................................................................... 8, 17
Display ON/OFF flip-flop ................................................................. 10
Display start line ........................................................ 8, 11, 12, 17, 18
Display start line register.............................................................. 8, 11
Dot dimensions................................................................................... 2
Dot pitch ............................................................................................. 2
- E -
- F -
Enable .......................................................................................... 6, 14
Frame frequency ................................................................................ 2
- I -
Input and output buffer .................................................................. 8, 9
Input register ................................................................................. 8, 9
Input voltage................................................................................. 2, 22
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- L -
LC drive voltage ........................................................................... 6, 21
LC panel life time................................................................................ 4
LED backlight characteristics............................................................. 4
- O -
Operating temperature ....................................................................... 2
Output register............................................................................... 8, 9
Output voltage.................................................................................... 2
-P -
- R -
Power supply example ..................................................................... 21
Power supply voltage ............................................................... 2, 6, 24
Recommended LC drive voltage...................................................... 21
Reset .................................................................................. 6, 9, 14, 16
Response time ................................................................................... 3
- S -
Segment driver............................................................................... 7, 8
Status read ................................................................ 9, 10, 16, 17, 20
Storage............................................................................................. 24
Storage humidity................................................................................. 2
Storage temperature ......................................................................... 2
- T-
Terminal functions ........................................................................... 14
- V -
Viewing angle..................................................................................... 3
Viewing area....................................................................................... 2
- W -
- X -
Weight ................................................................................................ 2
X-address counter............................................................................ 12
X, Y-address counter.................................................................... 8, 12
- Y -
- Z -
Y-address counter...................................................................... 12, 13
Z-address counter ........................................................................ 8, 11
Z80A................................................................................................. 23
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Seiko Instruments Inc.
Head Office
Components Overseas Marketing & Sales Department
1-8, Nakase, Mihama-ku, Chiba-shi, Chiba 261, Japan
Phone: 043-211-1213 FAX: 043-211-8035
Seiko Instruments U.S.A. Inc.
Electronic Components Division
2990 W. Lomita Blvd., Torrance Calif. 90505, USA Phone: 310-517-7770 FAX: 310- 517-7792
Seiko Instruments GmbH
Siemensstrasse 9b, 63263 Neu-Isenburg, Germany Phone: 49-6102-297-0 FAX: 49-6102-297-222
Seiko Instruments ( H. K. ) Ltd. Sales Division
4-5/F, Wyler Centre 2, 200 Tai Lin Pai Road, Kwai Chung, N.T., Kowloon, Hong Kong
Phone: 852-4218611 FAX: 852-4805479
Seiko Instruments Taiwan Inc.
5F-1 No. 99, SEC.2, Chung Shan N. Rd., Taipei 104, Taiwan, R.O.C.
Phone: 886-2-563-5001 FAX: 886-2-521-9519
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