Rev. 1.0, Jul. 2010
M471B1G73AH0
204pin Unbuffered SODIMM
based on 4Gb A-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
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ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
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Rev. 1.0
Unbuffered SODIMM
datasheet
DDR3 SDRAM
Table Of Contents
204pin Unbuffered SODIMM based on 4Gb A-die
1. DDR3 Unbuffered SODIMM Ordering Information........................................................................................................4
2. Key Features.................................................................................................................................................................4
3. Address Configuration ..................................................................................................................................................4
4. x64 DIMM Pin Configurations (Front side/Back Side)...................................................................................................5
5. Pin Description .............................................................................................................................................................6
6. Input/Output Functional Description..............................................................................................................................7
7. Function Block Diagram:...............................................................................................................................................8
8. Absolute Maximum Ratings ..........................................................................................................................................9
9. AC & DC Operating Conditions.....................................................................................................................................9
10. AC & DC Input Measurement Levels..........................................................................................................................10
10.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 10
Tolerances.................................................................................................................................................... 11
REF
10.3.2. Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS) ................................................ 12
10.4 Slew Rate Definition for Single Ended Input Signals............................................................................................. 14
10.5 Slew rate definition for Differential Input Signals................................................................................................... 14
11. AC & DC Output Measurement Levels .......................................................................................................................15
11.1 Single Ended AC and DC Output Levels............................................................................................................... 15
11.2 Differential AC and DC Output Levels................................................................................................................... 15
12. DIMM IDD specification definition...............................................................................................................................17
13. IDD SPEC Table.........................................................................................................................................................19
14. Input/Output Capacitance ...........................................................................................................................................20
15. Electrical Characteristics and AC timing.....................................................................................................................21
15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin................................................................. 21
16. Timing Parameters by Speed Grade ..........................................................................................................................26
17. Physical Dimensions :.................................................................................................................................................31
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Rev. 1.0
Unbuffered SODIMM
datasheet
DDR3 SDRAM
1. DDR3 Unbuffered SODIMM Ordering Information
Number of
Height
Part Number2
Density
Organization
Component Composition
Rank
M471B1G73AH0-CF8/H9
8GB
1Gx64
512Mx8(K4B4G0846A-HC##)*16
2
30mm
NOTE :
1. "##" - F8/H9
2. F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
2. Key Features
DDR3-800
DDR3-1066
DDR3-1333
9-9-9
1.5
Speed
Unit
6-6-6
7-7-7
1.875
7
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
2.5
6
ns
tCK
ns
9
15
13.125
13.125
37.5
13.5
13.5
36
15
ns
tRAS(min)
tRC(min)
37.5
52.5
ns
50.625
49.5
ns
•
•
JEDEC standard 1.5V ± 0.075V Power Supply
VDDQ = 1.5V ± 0.075V
•
400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin
•
•
•
•
•
8 independent internal bank
Programmable CAS Latency: 5,6,7,8,9
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066) and 7(DDR3-1333)
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
•
•
•
Bi-directional Differential Data Strobe
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
•
Asynchronous Reset
3. Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Precharge
512Mx8(4Gb) based Module
A0-A15
A0-A9
BA0-BA2
A10/AP
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Rev. 1.0
Unbuffered SODIMM
datasheet
DDR3 SDRAM
4. x64 DIMM Pin Configurations (Front side/Back Side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
139
141
143
145
147
Front
Pin
140
142
144
146
148
Back
DQ38
DQ39
V
V
V
V
V
1
2
71
72
REFDQ
SS
SS
SS
SS
V
3
4
DQ4
DQ5
KEY
DQ34
DQ35
SS
V
5
DQ0
DQ1
6
73
75
77
CKE0
74
76
78
CKE1
SS
V
V
V
V
7
8
DQ44
DQ45
SS
DD
DD
SS
3
V
9
10
DQS0
DQS0
NC
DQ40
DQ41
A15
SS
3
149
V
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
DM0
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
79
81
BA2
80
82
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
A14
SS
V
V
V
V
V
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DQS5
DQS5
SS
SS
DD
DD
SS
DQ2
DQ3
DQ6
DQ7
83
A12/BC
A9
84
A11
A7
DM5
V
V
85
86
SS
SS
V
V
V
V
87
88
DQ42
DQ43
DQ46
DQ47
SS
SS
DD
DD
DQ8
DQ9
DQ12
DQ13
89
A8
A5
90
A6
A4
V
V
91
92
SS
SS
V
V
V
V
93
94
DQ48
DQ49
DQ52
DQ53
SS
SS
DD
DD
DQS1
DQS1
DM1
95
A3
A1
96
A2
A0
V
V
RESET
97
98
SS
SS
V
V
V
V
DQS6
DQS6
DM6
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
SS
SS
DD
DD
V
DQ10
DQ11
DQ14
DQ15
101
103
105
107
109
111
113
115
117
119
CK0
CK0
CK1
CK1
SS
V
DQ54
DQ55
SS
V
V
V
V
DQ50
DQ51
SS
SS
DD
DD
V
DQ16
DQ17
DQ20
DQ21
A10/AP
BA0
BA1
RAS
SS
V
DQ60
DQ61
SS
V
V
V
V
DQ56
DQ57
SS
SS
DD
DD
V
DQS2
DQS2
DM2
WE
S0
SS
V
V
CAS
ODT0
DQS7
DQS7
SS
SS
V
V
V
DQ22
DQ23
DM7
SS
DD
DD
3
V
V
DQ18
DQ19
ODT1
NC
A13
SS
SS
V
121
123
125
127
129
S1
DQ58
DQ59
DQ62
DQ63
SS
V
V
V
DQ28
DQ29
SS
DD
DD
V
V
V
DQ24
DQ25
TEST
REFCA
SS
SS
V
V
V
SA0
NC
SDA
SCL
SS
SS
SS
V
V
DQS3
DQS3
DQ32
DQ33
DQ36
DQ37
SS
DDSPD
DM3
131
133
SA1
V
V
V
V
V
V
SS
SS
SS
SS
TT
TT
DQ26
DQ27
DQ30
DQ31
135
137
DQS4
DQS4
DM4
V
SS
NOTE :
1. NC = No Connect, NU = Not Used, RFU = Reserved Future Use
2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
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Rev. 1.0
Unbuffered SODIMM
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DDR3 SDRAM
5. Pin Description
Pin Name
Description
Number
Pin Name
Description
Data Input/Output
Number
CK0, CK1
CK0, CK1
Clock Inputs, positive line
2
DQ0-DQ63
64
Data Masks/ Data strobes,
Termination data strobes
Clock Inputs, negative line
2
DM0-DM7
8
CKE0, CKE1 Clock Enables
2
1
1
DQS0-DQS7 Data strobes
8
8
1
RAS
CAS
Row Address Strobe
DQS0-DQS7 Data strobes complement
Column Address Strobe
Write Enable
RESET
TEST
VDD
Reset Pin
Logic Analyzer specific test pin (No connect
on SODIMM)
WE
1
2
1
S0, S1
Chip Selects
Core and I/O Power
Ground
18
52
A0-A9, A11,
A13-A15
VSS
Address Inputs
14
VREFDQ
VREFCA
A10/AP
Address Input/Autoprecharge
1
1
Input/Output Reference
2
1
VDDSPD
VTT
A12/BC
Address Input/Burst chop
SDRAM Bank Addresses
SPD and Temp sensor Power
BA0-BA2
3
2
1
1
2
Termination Voltage
Reserved for future use
Total
2
3
ODT0, ODT1 On-die termination control
NC
SCL
SDA
Serial Presence Detect (SPD) Clock Input
204
SPD Data Input/Output
SPD Address
SA0-SA1
NOTE:
* The V and V
pins are tied common to a single power-plane on these designs.
DDQ
DD
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Rev. 1.0
Unbuffered SODIMM
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DDR3 SDRAM
6. Input/Output Functional Description
Symbol
Type
Function
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and
falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera-
tions is synchronized to the input clock.
CK0-CK1
CK0-CK1
Input
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,
CKE low initiates the Power Down mode or the Self Refresh mode.
CKE0-CKE1
S0-S1
Input
Input
Input
Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is
selected by S0; Rank 1 is selected by S1.
When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define
the operation to be executed by the SDRAM.
RAS, CAS, WE
BA0-BA2
Input
Input
Selects which DDR3 SDRAM internal bank of eight is activated.
ODT0-ODT1
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.
During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of
CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-
BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre-
charge.A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be
performed (HIGH, no burst chop; LOW, burst chopped)
A0-A9,
A10/AP,
A11
A12/BC
A13-A15
Input
DQ0-DQ63
DM0-DM7
I/O
Data Input/Output pins.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input
data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.
Input
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3
SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS.
DQS0-DQS7
DQS0-DQS7
I/O
VDD,VDDSPD,
VSS
Supply
Supply
I/O
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
Reference voltage for SSTL15 inputs.
VREFDQ,
VREFCA
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be
connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
SDA
SCL
SA0-SA1
TEST
Input
Input
I/O
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
Address pins used to select the Serial Presence Detect and Temp sensor base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules
RESET In Active Low This signal resets the DDR3 SDRAM
RESET
Input
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Rev. 1.0
Unbuffered SODIMM
datasheet
DDR3 SDRAM
7. Function Block Diagram:
7.1 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
V
V
DD
DD
Vtt
Vtt
Vtt
240Ω
240Ω
240Ω
240Ω
DQS3
DQS3
DM3
DQS4
DQS4
DM4
DQ[32:39]
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
± 1%
± 1%
± 1%
± 1%
ZQ
ZQ
ZQ
ZQ
D12
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[24:31]
D11
D3
D4
240Ω
240Ω
240Ω
240Ω
DQS1
DQS1
DM1
DQS6
DQS6
DM6
DQ[48:55]
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
± 1%
± 1%
± 1%
± 1%
ZQ
ZQ
ZQ
D14
ZQ
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[8:15]
D1
D9
D6
240Ω
240Ω
240Ω
240Ω
DQS0
DQS0
DM0
DQS7
DQS7
DM7
DQ[56:63]
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
± 1%
± 1%
± 1%
± 1%
ZQ
ZQ
Rank0
Rank1
ZQ
D15
ZQ
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
D0
D8
D7
240Ω
240Ω
240Ω
240Ω
DQS2
DQS2
DM2
DQS5
DQS5
DM5
DQ[40:47]
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
± 1%
± 1%
± 1%
± 1%
ZQ
ZQ
D10
ZQ
D13
ZQ
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[16:23]
D2
D5
V
V
tt
tt
V2
V1
V1
V8
V
D9
V3
D3
D12
D5
D6
V7
SPD
DDSPD
V9
V5
V
D0 - D15
D0 - D15
D0 - D15
REFCA
V
SCL
SA0
SA1
SCL
A0
A1
REFDQ
D8
D10
D7
(SPD)
WP
SDA
V4
V4
V6
V6
V
DD
V
D0 - D15, SPD
D0 - D7
SS
A2
CK0
CK1
CK0
CK1
D0
D2
D13
D4
D15
V5
tt
D8 - D15
D0 - D7
V3
D1
V7
D14
V
V1
V9
D11
D8 - D15
V2
V8
D0 - D7
RESET
NOTE :
1. DQ wiring may differ from that shown however ,DQ, DM, DQS and DQS relationships are maintained as shown
Address and Controllines
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DDR3 SDRAM
8. Absolute Maximum Ratings
8.1 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
NOTE
VDD
Voltage on VDD pin relative to VSS
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-55 to +100
V
1,3
VDDQ
Voltage on VDDQ pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
V
V
1,3
1
V
IN, VOUT
TSTG
°C
1, 2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. V
and V
must be within 300mV of each other at all times;and V
must be not greater than 0.6 x V
, When V and V
are less than 500mV; V
may be
REF
DD
DDQ
REF
DDQ
DD
DDQ
equal to or less than 300mV.
8.2 DRAM Component Operating Temperature Range
Symbol
Parameter
rating
Unit
NOTE
TOPER
Operating Temperature Range
0 to 95
°C
1, 2, 3
NOTE :
1. Operating Temperature T
is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
OPER
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI
to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
9. AC & DC Operating Conditions
9.1 Recommended DC Operating Conditions (SSTL-15)
Rating
Symbol
Parameter
Units
NOTE
Min.
1.425
1.425
Typ.
1.5
Max.
1.575
1.575
VDD
Supply Voltage
Supply Voltage for Output
V
V
1,2
1,2
VDDQ
1.5
NOTE:
1. Under all conditions V
must be less than or equal to V
.
DDQ
DD
2. V
tracks with V . AC parameters are measured with V and V
tied together.
DDQ
DD
DD
DDQ
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Unbuffered SODIMM
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DDR3 SDRAM
10. AC & DC Input Measurement Levels
10.1 AC & DC Logic Input Levels for Single-ended Signals
[ Table 1 ] Single-ended AC & DC input levels for Command and Address
DDR3-800/1066/1333/1600
Symbol
Parameter
Unit
NOTE
Min.
Max.
VIH.CA(DC100)
VREF + 100
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
1,5
V
IL.CA(DC100)
IH.CA(AC175)
IL.CA(AC175)
IH.CA(AC150)
IL.CA(AC150)
VSS
VREF - 100
1,6
V
VREF + 175
-
1,2,7
1,2,8
1,2,7
1,2,8
V
VREF - 175
-
V
VREF+150
-
V
VREF-150
-
Reference Voltage for ADD,
CMD inputs
V
REFCA(DC)
0.49*VDD
0.51*VDD
V
3,4
NOTE :
1. For input only pins except RESET, V
= V
(DC)
REFCA
REF
2. See ’Overshoot/Undershoot Specification’ on page 18.
3. The AC peak noise on V may not allow V to deviate from V
(DC) by more than ± 1% V (for reference : approx. ± 15mV)
REF
REF
REF
DD
4. For reference : approx. V /2 ± 15mV
DD
5. V (dc) is used as a simplified symbol for V
(DC100)
IH
IH.CA
6. V (dc) is used as a simplified symbol for V
(DC100)
IL
IL.CA
7. V (ac) is used as a simplified symbol for V
(AC175) and V
(AC150); V
(AC175) value is used when V
+ 175mV is referenced and V
(AC150) value is
IH.CA
IH
IH.CA
IH.CA
IH.CA
REF
used when VREF + 150mV is referenced.
8. V (ac) is used as a simplified symbol for V
(AC175) and V
(AC150); V
(AC175) value is used when V
- 175mV is referenced and V
(AC150) value is used
IL.CA
IL
IL.CA
IL.CA
IL.CA
REF
when V
- 150mV is referenced.
REF
[ Table 2 ] Single-ended AC & DC input levels for DQ and DM
DDR3-800/1066
DDR3-1333/1600
Symbol
Parameter
Unit
NOTE
Min.
Max.
Min.
Max.
VIH.DQ(DC100)
VREF + 100
VSS
VDD
VREF + 100
VSS
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
1,5
V
IL.DQ(DC100)
IH.DQ(AC175)
IL.DQ(AC175)
IH.DQ(AC150)
IL.DQ(AC150)
VREF - 100
VREF - 100
1,6
V
VREF + 175
-
-
-
-
1,2,7
1,2,8
1,2,7
1,2,8
V
VREF - 175
-
-
V
VREF + 150
VREF + 150
NOTE 2
NOTE 2
VREF - 150
V
VREF - 150
NOTE 2
NOTE 2
Reference Voltage for DQ,
DM inputs
VREFDQ(DC)
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
NOTE :
1. For input only pins except RESET, V
= V
(DC)
REFDQ
REF
2. See ’Overshoot/Undershoot Specification’ on page 18.
3. The AC peak noise on V
may not allow V
to deviate from V
(DC) by more than ± 1% V (for reference : approx. ± 15mV)
REF
REF
REF DD
4. For reference : approx. V /2 ± 15mV
DD
5. V (dc) is used as a simplified symbol for V
(DC100)
IH
IH.DQ
6. V (dc) is used as a simplified symbol for V
(DC100)
IL
IL.DQ
7. V (ac) is used as a simplified symbol for V
(AC175), V
(AC150) ; V
(AC175) value is used when V
+ 175mV is referenced, V
(AC150) value is used
IH
IH.DQ
IH.DQ
IH.DQ
REF
IH.DQ
when V
+ 150mV is referenced.
REF
8. V (ac) is used as a simplified symbol for V
(AC175), V
(AC150) ; V
(AC175) value is used when V
- 175mV is referenced, V
(AC150) value is used when
IL.DQ
IL
IL.DQ
IL.DQ
IL.DQ
REF
V
- 150mV is referenced.
REF
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10.2 V Tolerances.
REF
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage
REF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
REF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of VREF. Fur-
thermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD
V
V
.
voltage
V
DD
V
SS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF
.
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise.
Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
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10.3 AC and DC Logic Input Levels for Differential Signals
10.3.1 Differential Signals Definition
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
10.3.2 Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS)
DDR3-800/1066/1333/1600
Symbol
Parameter
unit
NOTE
min
+0.2
max
VIHdiff
VILdiff
IHdiff(AC)
ILdiff(AC)
differential input high
differential input low
NOTE 3
-0.2
V
V
V
V
1
1
2
2
NOTE 3
V
2 x (VIH(AC) - VREF)
differential input high ac
differential input low ac
NOTE 3
V
2 x (VIL(AC) - VREF)
NOTE 3
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use V /V (AC) of ADD/CMD and V
IH IL
; for DQS - DQS use V /V (AC) of DQs and V
; if a reduced ac-high or ac-low level is used for a signal group,
REFCA
IH IL
REFDQ
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (V (DC) max, V (DC)min) for single-ended sig-
IH
IL
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"
[ Table 3 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS.
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
min
75
57
50
38
34
29
22
13
0
max
min
175
170
167
163
162
161
159
155
150
150
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
0
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10.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every
half-cycle.
DQS, DQS have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle proceeding and follow-
ing a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD
signals, then these ac-levels apply also for the single-ended signals CK and CK .
V
or V
DDQ
DD
V
min
SEH
V
SEH
V
/2 or V
/2
DDQ
DD
CK or DQS
V
max
SEL
V
SEL
V
or V
SSQ
SS
time
Figure 3. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement
with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
[ Table 4 ] Single-ended levels for CK, DQS, CK, DQS
DDR3-800/1066/1333/1600
Symbol
Parameter
Unit
NOTE
Min
Max
(VDD/2)+0.175
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes
Single-ended low-level for CK, CK
NOTE3
V
V
V
V
1, 2
1, 2
1, 2
1, 2
VSEH
(VDD/2)+0.175
NOTE3
NOTE3
(VDD/2)-0.175
(VDD/2)-0.175
VSEL
NOTE3
NOTE :
1. For CK, CK use V /V (AC) of ADD/CMD; for strobes (DQS, DQS) use V /V (AC) of DQs.
IH IL
IH IL
2. V (AC)/V (AC) for DQs is based on V
; V (AC)/V (AC) for ADD/CMD is based on V
; if a reduced ac-high or ac-low level is used for a signal group, then the
REFCA
IH
IL
REFDQ
IH
IL
reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective
limits (V (DC) max, V (DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
IH
IL
Specification"
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10.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signal to the mid level between of VDD and VSS
.
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
Figure 4. VIX Definition
[ Table 5 ] Cross point voltage for differential input signals (CK, DQS)
DDR3-800/1066/1333/1600
Symbol
Parameter
Unit
NOTE
Min
-150
-175
-150
Max
150
175
150
mV
mV
mV
VIX
VIX
Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS
1
NOTE :
1. Extended range for V is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V
/ V
of at least V /2
SEH DD
IX
SEL
±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
10.4 Slew Rate Definition for Single Ended Input Signals
See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.
10.5 Slew rate definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.
[ Table 6 ] Differential input slew rate definition
Measured
Description
Defined by
From
To
VIHdiffmin - VILdiffmax
Delta TRdiff
VILdiffmax
VIHdiffmin
Differential input slew rate for rising edge (CK-CK and DQS-DQS)
Differential input slew rate for falling edge (CK-CK and DQS-DQS)
VIHdiffmin - VILdiffmax
Delta TFdiff
VIHdiffmin
VILdiffmax
NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
V
IHdiffmin
ILdiffmax
0
V
delta TFdiff
delta TRdiff
Figure 5. Differential input slew rate definition for DQS, DQS and CK, CK
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11. AC & DC Output Measurement Levels
11.1 Single Ended AC and DC Output Levels
[ Table 7 ] Single Ended AC and DC output levels
Symbol Parameter
DDR3-800/1066/1333/1600
Units
NOTE
VOH(DC) DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
V
OM(DC) DC output mid measurement level (for IV curve linearity)
OL(DC) DC output low measurement level (for IV curve linearity)
VOH(AC) AC output high measurement level (for output SR)
0.5 x VDDQ
0.2 x VDDQ
V
V
V
V
V
VTT + 0.1 x VDDQ
VTT - 0.1 x VDDQ
1
1
V
OL(AC) AC output low measurement level (for output SR)
NOTE : 1. The swing of +/-0.1 x V
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
DDQ
load of 25Ω to V =V
/2.
TT
DDQ
11.2 Differential AC and DC Output Levels
[ Table 8 ] Differential AC and DC output levels
Symbol
Parameter
DDR3-800/1066/1333/1600
Units
NOTE
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V
1
V
OLdiff(AC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
NOTE : 1. The swing of +/-0.2xV
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
DDQ
load of 25Ω to V =V
/2 at each of the differential outputs.
TT
DDQ
11.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.
[ Table 9 ] Single ended Output slew rate definition
Measured
Description
Defined by
From
To
VOH(AC)-VOL(AC)
Delta TRse
V
OL(AC)
VOH(AC)
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
VOH(AC)-VOL(AC)
Delta TFse
V
OH(AC)
VOL(AC)
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 10 ] Single ended output slew rate
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Parameter
Symbol
Units
Min
2.5
Max
Min
2.5
Max
Min
2.5
Max
Min
Max
Single ended output slew rate
Description : SR : Slew Rate
SRQse
5
5
5
2.5
5
V/ns
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
V
(AC)
(AC)
OHdiff
V
V
TT
OLdiff
delta TFdiff
delta TRdiff
Figure 6. Single-ended output slew rate definition
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11.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOH-
diff(AC) for differential signals as shown in below.
[ Table 11 ] Differential Output slew rate definition
Measured
Description
Defined by
From
To
VOHdiff(AC)-VOLdiff(AC)
Delta TRdiff
V
OLdiff(AC)
VOHdiff(AC)
Differential output slew rate for rising edge
Differential output slew rate for falling edge
VOHdiff(AC)-VOLdiff(AC)
Delta TFdiff
V
OHdiff(AC)
VOLdiff(AC)
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 12 ] Differential Output slew rate
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
Min
Max
Differential output slew rate
Description : SR : Slew Rate
SRQdiff
5
10
5
10
5
10
5
10
V/ns
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
diff : Differential Signals
For Ron = RZQ/7 setting
V
(AC)
(AC)
OHdiff
V
V
TT
OLdiff
delta TFdiff
delta TRdiff
Figure 7. Differential output slew rate definition
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12. DIMM IDD specification definition
Symbol
Description
Operating One Bank Active-Precharge Current
1)
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between ACT and PRE;
IDD0
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
2)
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
Operating One Bank Active-Read-Precharge Current
1)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between ACT, RD
IDD1
and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
2)
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
Precharge Standby Current
1)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
IDD2N
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
2)
Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Precharge Power-Down Current Slow Exit
1)
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
IDD2P0
2)
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
;
;
3)
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit
Precharge Power-Down Current Fast Exit
1)
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
IDD2P1
IDD2Q
IDD3N
IDD3P
2)
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
3)
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
Precharge Quiet Standby Current
1)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
2)
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0
;
Active Standby Current
1)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode
2)
Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Active Power-Down Current
1)
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
2)
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers ; ODT
Signal: stable at 0
Operating Burst Read Current
1)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between RD; Command, Address,
IDD4R
IDD4W
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
2)
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable
at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Operating Burst Write Current
1)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
2)
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable
at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern
Burst Refresh Current
1)
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between REF; Command,
IDD5B
IDD6
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and
2)
RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Self Refresh Current: Normal Temperature Range
4)
5)
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Normal ; CKE: Low; External clock: Off; CK and CK:
1)
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
2)
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING
6)
Self-Refresh Current: Extended Temperature Range (optional)
4)
5)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Extended ; CKE: Low; External clock: Off; CK and CK:
IDD6ET
1)
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
2)
Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING
Operating Bank Interleave Read Current
1)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: CL-1; CS: High
IDD7
IDD8
between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:
2)
Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
RESET Low Current
RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
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NOTE :
1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
7) IDD current measure method and detail patterns are described on DDR3 component datasheet
8) VDD and VDDQ are merged on module PCB.
9) DIMM IDD SPEC is measured with Qoff condition
(IDDQ values are not considered)
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13. IDD SPEC Table
M471B1G73AH0 : 8GB (1Gx64) Module
CF8
CH9
Symbol
Unit
NOTE
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
IDD0
IDD1
600
720
240
320
400
400
400
520
960
1040
1440
240
1520
240
680
800
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
240
320
480
IDD2Q
400
IDD3P
400
IDD3N
600
IDD4R
1120
1280
1600
240
1
1
1
IDD4W
IDD5B
IDD6
IDD7
1880
240
1
IDD8
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
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DDR3 SDRAM
14. Input/Output Capacitance
14.1 2Rx8 2GB SODIMM
Parameter
M471B1G73AH0
DDR3-1066 DDR3-1333
Symbol
Units
NOTE
Min
Max
Min
Max
Input/output capacitance
CIO
-
TBD
-
TBD
pF
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance (CK and CK)
CCK
CI
-
-
TBD
TBD
-
-
TBD
TBD
pF
pF
Input capacitance (All other input-only pins)
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DDR3 SDRAM
15. Electrical Characteristics and AC timing
(0 °C<T
≤95 °C, V
= 1.5V ± 0.075V; V = 1.5V ± 0.075V)
DDQ DD
CASE
15.1 Refresh Parameters by Device Density
Parameter
Symbol
1Gb
110
7.8
2Gb
160
7.8
4Gb
300
7.8
8Gb
350
7.8
Units
ns
NOTE
All Bank Refresh to active/refresh cmd time
tRFC
0 °C ≤ TCASE ≤ 85°C
μs
Average periodic refresh interval
tREFI
85 °C < TCASE ≤ 95°C
3.9
3.9
3.9
3.9
μs
1
NOTE :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in
this material.
15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR3-800
6-6-6
min
6
DDR3-1066
7-7-7
min
DDR3-1333
9-9-9
min
9
DDR3-1600
11-11-11
min
Bin (CL - tRCD - tRP)
Units
NOTE
Parameter
CL
7
11
tCK
ns
ns
ns
ns
ns
ns
tRCD
tRP
15
13.13
13.13
37.5
13.5
13.5
36
13.75
13.75
35
15
tRAS
tRC
37.5
52.5
10
50.63
7.5
49.5
6.0
48.75
6.0
tRRD
tFAW
40
37.5
30
30
15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 13 ] DDR3-800 Speed Bins
Speed
DDR3-800
6 - 6 - 6
CL-nRCD-nRP
Units
NOTE
Parameter
Symbol
tAA
min
15
max
Internal read command to first data
ACT to internal read or write delay time
PRE command period
20
ns
ns
tRCD
15
-
tRP
15
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
52.5
37.5
3.0
2.5
ns
tRAS
9*tREFI
3.3
ns
CL = 5
CWL = 5
CWL = 5
tCK(AVG)
tCK(AVG)
ns
1,2,3,4,9,10
1,2,3
CL = 6
3.3
ns
Supported CL Settings
Supported CWL Settings
5, 6
5
nCK
nCK
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DDR3 SDRAM
[ Table 14 ] DDR3-1066 Speed Bins
Speed
DDR3-1066
CL-nRCD-nRP
7 - 7 - 7
Units
NOTE
Parameter
Internal read command to first data
ACT to internal read or write delay time
PRE command period
Symbol
tAA
min
13.125
13.125
13.125
50.625
37.5
max
20
ns
ns
tRCD
-
tRP
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
ns
tRAS
9*tREFI
3.3
ns
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
3.0
ns
1,2,3,4,5,9,10
CL = 5
CL = 6
CL = 7
CL = 8
Reserved
ns
4
1,2,3,5
1,2,3,4
4
2.5
3.3
ns
Reserved
Reserved
ns
ns
1.875
1.875
<2.5
<2.5
ns
1,2,3,4,8
4
Reserved
ns
ns
1,2,3
Supported CL Settings
Supported CWL Settings
5, 6,7,8
5,6
nCK
nCK
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DDR3 SDRAM
[ Table 15 ] DDR3-1333 Speed Bins
Speed
DDR3-1333
CL-nRCD-nRP
9 -9 - 9
Units
NOTE
Parameter
Symbol
min
max
13.5
Internal read command to first data
tAA
20
ns
ns
ns
ns
(13.125)8
13.5
ACT to internal read or write delay time
PRE command period
tRCD
tRP
-
-
-
(13.125)8
13.5
(13.125)8
49.5
ACT to ACT or REF command period
ACT to PRE command period
tRC
(49.125)8
tRAS
36
9*tREFI
3.3
ns
ns
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
3.0
1,2,3,4,6,9,10
CL = 5
CWL = 6,7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5,6
CWL = 7
CWL = 5,6
CWL = 7
Reserved
ns
4
1,2,3,6
1,2,3,4,6
4
2.5
3.3
ns
CL = 6
Reserved
Reserved
Reserved
ns
ns
ns
4
CL = 7
CL = 8
1.875
1.875
1.5
<2.5
<2.5
ns
1,2,3,4,6
1,2,3,4
4
Reserved
Reserved
ns
ns
ns
1,2,3,6
1,2,3,4
4
Reserved
Reserved
ns
ns
CL = 9
<1.875
ns
1,2,3,4,8
4
Reserved
Reserved
5,6,7,8,9
5,6,7
ns
CL = 10
ns
1,2,3
Supported CL Settings
Supported CWL Settings
nCK
nCK
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DDR3 SDRAM
[ Table 16 ] DDR3-1600 Speed Bins
Speed
DDR3-1600
CL-nRCD-nRP
11-11-11
Units
NOTE
Parameter
Symbol
min
max
13.75
Internal read command to first data
tAA
20
ns
ns
ns
ns
(13.125)8
13.75
ACT to internal read or write delay time
PRE command period
tRCD
tRP
-
-
-
(13.125)8
13.75
(13.125)8
48.75
ACT to ACT or REF command period
ACT to PRE command period
tRC
(48.125)8
tRAS
35
9*tREFI
3.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
3.0
1,2,3,4,7,9,10
CL = 5
CWL = 6,7,8
CWL = 5
CWL = 6
CWL = 7, 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5,6
CWL = 7
CWL = 8
CWL = 5,6
CWL = 7
CWL = 8
CWL = 5,6,7
CWL = 8
Reserved
4
1,2,3,7
1,2,3,4,7
4
2.5
3.3
CL = 6
Reserved
Reserved
Reserved
4
1.875
1.875
<2.5
<2.5
1,2,3,4,7
1,2,3,4,7
4
CL = 7
Reserved
Reserved
Reserved
4
1,2,3,7
1,2,3,4,7
1,2,3,4
4
CL = 8
CL = 9
Reserved
Reserved
Reserved
1.5
1.5
<1.875
<1.875
<1.5
1,2,3,4,7
1,2,3,4
4
Reserved
Reserved
CL = 10
CL = 11
1,2,3,7
1,2,3,4
4
Reserved
Reserved
1.25
1,2,3,8
Supported CL Settings
Supported CWL Settings
5,6,7,8,9,10,11
5,6,7,8
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DDR3 SDRAM
15.3.1 Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
NOTE :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-
anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next "SupportedCL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or
1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
8. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,
DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte
20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte
18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin
+ tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).
9. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.
10. For CL5 support DIMM SPD include CL5 on supportable CAS Latency(Byte 14-bit1 set HIGH).
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DDR3 SDRAM
16. Timing Parameters by Speed Grade
[ Table 17 ] Timing Parameters by Speed Bin
Speed
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock Timing
tCK(DLL_OF
F)
Minimum Clock Cycle Time (DLL off mode)
8
-
8
-
8
-
8
-
ns
6
Average Clock Period
Clock Period
tCK(avg)
tCK(abs)
See Speed Bins Table
ps
ps
tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
Average high pulse width
tCH(avg)
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
ps
Clock Period Jitter
tJIT(per)
-100
100
-90
90
-80
80
-70
70
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(per, lck)
tJIT(cc)
-90
90
-80
80
-70
70
-60
60
ps
200
180
180
160
160
140
140
120
ps
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
ps
- 147
- 175
- 194
- 209
- 222
- 232
- 241
- 249
- 257
- 263
- 269
147
175
194
209
222
232
241
249
257
263
269
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
132
157
175
188
200
209
217
224
231
237
242
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
118
140
155
168
177
186
193
200
205
210
215
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
103
122
136
147
155
163
169
175
180
184
188
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
ps
24
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
tCH(abs)
tCL(abs)
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
tCK(avg)
tCK(avg)
25
26
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
tDQSQ
tQH
-
200
-
-
150
-
-
125
-
-
100
-
ps
tCK(avg)
ps
13
0.38
-800
-
0.38
-600
-
0.38
-500
-
0.38
-450
-
13, g
tLZ(DQ)
tHZ(DQ)
400
400
300
300
250
250
225
225
13,14, f
13,14, f
ps
tDS(base)
AC175
75
25
75
-
-
-
-
ps
ps
d, 17
d, 17
-
-
-
-
Data setup time to DQS, DQS referenced to
V
(AC)V (AC) levels
IH
IL
tDS(base)
AC150
125
30
10
Data hold time to DQS, DQS referenced to
(AC)V (AC) levels
tDH(base)
DC100
150
600
100
490
65
-
45
ps
ps
d, 17
28
-
-
-
-
V
IH
IL
DQ and DM Input pulse width for each input
Data Strobe Timing
tDIPW
400
360
-
DQS, DQS differential READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS differential output high time
DQS, DQS differential output low time
DQS, DQS differential WRITE Preamble
DQS, DQS differential WRITE Postamble
tRPRE
tRPST
tQSH
0.9
0.3
NOTE 19
0.9
0.3
NOTE 19
0.9
0.3
0.4
0.4
0.9
0.3
NOTE 19
0.9
0.3
0.4
0.4
0.9
0.3
NOTE 19
tCK
tCK
13, 19, g
11, 13, b
13, g
NOTE 11
NOTE 11
NOTE 11
NOTE 11
0.38
0.38
0.9
-
-
-
-
0.38
0.38
0.9
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK
tQSL
13, g
tWPRE
tWPST
0.3
0.3
tCK
DQS, DQS rising edge output access time from rising
CK, CK
tDQSCK
-400
-800
-
400
400
400
-300
-600
-
300
300
300
-255
-500
-
255
250
250
-225
-450
-
225
225
225
ps
ps
ps
13,f
DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS)
13,14,f
12,13,14
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
tHZ(DQS)
DQS, DQS differential input low pulse width
tDQSL
tDQSH
tDQSS
tDSS
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.27
0.18
0.18
0.55
0.55
0.27
-
tCK
29, 31
30, 31
c
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
tCK
tCK(avg)
tCK(avg)
tCK(avg)
c, 32
c, 32
tDSH
0.2
-
0.2
-
0.2
-
-
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DDR3 SDRAM
[ Table 17 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Parameter
Command and Address Timing
DLL locking time
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tDLLK
tRTP
512
-
-
512
-
-
512
-
-
512
-
-
nCK
max
(4nCK,7.5ns
)
internal READ Command to PRECHARGE Command
delay
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
e
max
(4nCK,7.5ns
)
Delay from start of internal write transaction to internal
read command
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
tWTR
-
-
-
-
e,18
e
WRITE recovery time
tWR
15
4
-
-
15
4
-
-
15
4
-
-
15
4
-
-
ns
Mode Register Set command cycle time
tMRD
nCK
max
(12nCK,15n
s)
max
(12nCK,15ns
)
max
(12nCK,15ns
)
max
(12nCK,15ns)
Mode Register Set command update delay
tMOD
-
-
-
-
-
-
-
CAS# to CAS# command delay
tCCD
tDAL(min)
tMPRR
tRAS
4
4
-
4
4
nCK
nCK
nCK
ns
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
WR + roundup (tRP / tCK(AVG))
1
-
1
-
1
-
1
-
22
e
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42
max
(4nCK,10ns)
max
(4nCK,7.5ns)
max
(4nCK,6ns)
max
(4nCK,6ns)
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRD
-
-
-
-
-
-
-
-
e
e
max
(4nCK,10ns)
max
(4nCK,10ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
Four activate window for 1KB page size
Four activate window for 2KB page size
tFAW
tFAW
40
50
-
-
37.5
50
-
-
30
45
-
-
30
40
-
-
ns
ns
e
e
tIS(base)
AC175
200
125
65
-
-
45
-
-
ps
ps
b,16
-
-
-
-
Command and Address setup time to CK, CK referenced
to V (AC) / V (AC) levels
IH
IL
tIS(base)
AC150
200 + 150
125 + 150
65+125
45+125
b,16,27
Command and Address hold time from CK, CK refer-
enced to V (AC) / V (AC) levels
tIH(base)
DC100
275
900
-
-
200
780
-
-
140
620
-
-
120
560
-
-
ps
ps
b,16
28
IH
IL
Control & Address Input pulse width for each input
Calibration Timing
tIPW
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
Reset Timing
tZQinitI
tZQoper
tZQCS
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
nCK
nCK
nCK
23
max(5nCK,
tRFC +
10ns)
max(5nCK,
tRFC + 10ns)
max(5nCK,
tRFC + 10ns)
max(5nCK,
tRFC + 10ns)
Exit Reset from CKE HIGH to a valid command
tXPR
-
-
-
-
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL
max(5nCK,t
RFC + 10ns)
max(5nCK,tR
FC + 10ns)
max(5nCK,tR
FC + 10ns)
max(5nCK,tR
FC + 10ns)
tXS
-
-
-
-
-
-
-
-
-
-
-
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tCKESR
tDLLK(min)
tDLLK(min)
tDLLK(min)
tDLLK(min)
nCK
Minimum CKE low width for Self refresh entry to exit tim-
ing
tCKE(min) +
1tCK
tCKE(min) +
1tCK
tCKE(min) +
1tCK
tCKE(min) +
1tCK
Valid Clock Requirement after Self Refresh Entry (SRE)
or Power-Down Entry (PDE)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
tCKSRE
tCKSRX
-
-
-
-
-
-
-
-
Valid Clock Requirement before Self Refresh Exit (SRX)
or Power-Down Exit (PDX) or Reset Exit
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
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Rev. 1.0
Unbuffered SODIMM
datasheet
DDR3 SDRAM
[ Table 17 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max
(3nCK,
7.5ns)
max
(3nCK,
7.5ns)
max
(3nCK,6ns)
max
(3nCK,6ns)
tXP
tXPDLL
tCKE
-
-
-
-
-
-
-
-
-
-
-
-
max
(10nCK,
24ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
2
max
(3nCK,
7.5ns)
max
(3nCK,
5.625ns)
max
(3nCK,
5.625ns)
max
(3nCK,5ns)
CKE minimum pulse width
Command pass disable delay
tCPDED
tPD
1
-
1
-
1
-
1
-
nCK
tCK
Power Down Entry to Exit Timing
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
15
20
20
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
tACTPDEN
tPRPDEN
tRDPDEN
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
nCK
nCK
RL + 4 +1
RL + 4 +1
RL + 4 +1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRAPDEN
tWRPDEN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nCK
nCK
nCK
nCK
9
10
9
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
WL + 4
+WR +1
WL + 4
+WR +1
WL + 4 +WR
+1
WL + 4 +WR
+1
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
Timing of WR command to Power Down entry
(BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
WL+2 +WR
+1
WL +2 +WR
+1
WL +2 +WR
+1
WL +2 +WR
+1
tWRAPDEN
tREFPDEN
10
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
1
-
-
1
-
-
1
-
-
1
-
-
20,21
tMRSPDEN tMOD(min)
tMOD(min)
tMOD(min)
tMOD(min)
ODT high time without write command or with write
command and BC4
ODTH4
ODTH8
tAONPD
4
6
2
-
-
4
6
2
-
-
4
6
2
-
-
4
6
2
-
-
nCK
nCK
ns
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
8.5
8.5
8.5
8.5
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
tAOFPD
tAON
2
8.5
400
0.7
2
8.5
300
0.7
2
8.5
250
0.7
2
8.5
225
0.7
ns
ps
RTT turn-on
-400
0.3
-300
0.3
-250
0.3
-225
0.3
7,f
8,f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
tCK(avg
)
tAOF
tCK(avg
)
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
f
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining
mode is programmed
tWLMRD
tWLDQSEN
tWLS
40
25
-
-
-
-
40
25
-
-
-
-
40
25
-
-
-
-
40
25
-
-
-
-
tCK
tCK
ps
3
3
DQS/DQS delay after tDQS margining mode is pro-
grammed
Write leveling setup time from rising CK, CK crossing to
rising DQS, DQS crossing
325
325
245
245
195
195
165
165
Write leveling hold time from rising DQS, DQS crossing
to rising CK, CK crossing
tWLH
ps
Write leveling output delay
Write leveling output error
tWLO
0
0
9
2
0
0
9
2
0
0
9
2
0
0
7.5
2
ns
ns
tWLOE
- 28 -
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Rev. 1.0
Unbuffered SODIMM
datasheet
DDR3 SDRAM
16.1 Jitter Notes
Specific Note a
Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the
input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,
another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b
These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition
edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,
these parameters should be met whether clock jitter is present or not.
Specific Note c
These parameters are measured from a data strobe signal (DQS, DQS) crossing to its respective clock signal (CK, CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d
Specific Note e
These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal
(DQS, DQS) crossing.
For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com-
mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
Specific Note f
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input
clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +
193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(der-
ated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to
tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the
min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input
clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has
tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +
tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =
tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/
max usage!)
- 29 -
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Rev. 1.0
Unbuffered SODIMM
datasheet
DDR3 SDRAM
16.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"
8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing
Diagram Datasheet.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by TBD
13. Value is only valid for RON34
14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.
15. tREFI depends on T
OPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
(DC) = V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).
V
REF
REF
REF
REF
See "Address/Command Setup, Hold and Derating" on component datasheet.
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
(DC)= V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).
V
REF
REF
REF
REF
See "Data Setup, Hold and Slew Rate Derating" on component datasheet.
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram
Datasheet"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-
lated as:
0.5
~
~
= 0.133
128ms
(1.5 x 1) + (0.15 x 15)
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-
nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of V
(DC) and the consecutive crossing of V
(DC)
REF
REF
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
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Rev. 1.0
Unbuffered SODIMM
datasheet
DDR3 SDRAM
17. Physical Dimensions :
17.1 512Mx8 based 1Gx64 Module (2 Ranks) - M471B1G73AH0
Units : Millimeters
0.10 M C A B
63.60
67.60
Max 3.8
1.00 ± 0.10
24.80
21.00
A
B
39.00
2X 1.80
0.10 M C A B
(OPTIONAL HOLES)
2X 4.00 ± 0.10
0.10 M C A B
0.60
0.45 ± 0.03
1.65
4.00 ± 0.10
2.55
0.25 MAX
1.00 ± 0.10
Detail A
Detail B
The used device is 512M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B4G0846A - HC**
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
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