Ricoh Computer Hardware R5C841 User Guide

RICOH COMPANY,LTD.

R5C841

PCI-CardBus/IEEE1394/SD Card

/MemoryStick/xD/ExpressCard

Data Sheet

REV. 1.10

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

1 OVERVIEW

The R5C841 is a single chip solution offering five PCI functions (a PCI bus bridge to a PC Card, an IEEE

1394, an SD Card, a Memory Stick and an xD Picture Card) with an ExpressCard (USB Interface Type)

switch.

ꢀ

PC98/99/2001 compliant

ꢁ

PC2001 Design Guide compliant (Subsystem ID, Subsystem Vendor ID)

Compliant with ACPI and PCI Bus Power Management 1.1

Support Global Reset

ꢀ

Low Power consumption

ꢁ

Low operating power consumption due to the improvement of Power Management

Software Suspend mode compliant with ACPI

Hardware Suspend

CLKRUN#, CCLKRUN# support

The core logic - powered at 1.8V, the others – powered at 3.3V

ꢀ

PCI-CardBus/1394 Bridge/SD Card/Memory Stick/xD Picture Card/ExpressCard interface

ꢁ

1-slot PC Card

2 ports of IEEE1394

MDIOxx pins shared by SD Card, Memory Stick and xD Picture Card

−

Providing Ricoh’s proprietary driver for Memory Stick and xD Picture Card

ExpressCard (USB Interface Type) supported by the PC Card passive adapter

ꢁ

PCI Bus Interface

ꢁ

Compliant with PCI Local Bus Specification2.3

The maximum frequency 33MHz

PCI Master/Target protocol support

PCI configuration space for each function

3.3V Interface (5V tolerant)

CardBus PC card Bridge

ꢁ

Compliant with PC Card Standard Release 8.1 Specification

The maximum frequency 33MHz

Support CardBus Master/Target protocol

Support Memory Write Posting/ Read Prefetching

Transfer transactions

−

All memory read/write transaction (bi-direction)

I/O read/write transaction (bi-direction)

Configuration read/write transaction (PCI → Card)

2 programmable memory windows

2 programmable I/O windows

ꢀ

PC Card-16 Bridge

ꢁ

Compliant with PC Card Standard Release 8.1 16-bit Specification

5 programmable memory windows

2 programmable I/O windows

Compliant with i82365SL compatible register set/ExCA

Support Legacy 16-bit mode (3E0, 3E2 I/O ports)

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

ꢀ

IEEE1394 Interface

ꢁ

Compliant with IEEE1394-1995 Standard Specification and IEEE1394a-2000 Standard Specification

Compliant with 1394 OHCI Release 1.1/1.0 Standard Specification

Support Cycle Master

Provide the Asynchronous receive/transmit FIFO and isochronous receive/transmit FIFO

Support Self-ID, physical DMA

Data transmission rate of 100, 200 and 400Mbps

2 ports of 1394 Cable interface

24.576MHz crystal oscillator and Internal 393.216MHz PLL

Support Cable Power monitoring (CPS)

Set Initial values of Power Class and CMC by PCI Configuration registers

ꢀ

Small Card Interface

SD Card

ꢁ

−

Compliant with SD Memory Card Specification Version 1.01

Compliant with SD Input/Output (SDIO) Card Specification Version 1.0

Compliant with SD Host Controller Standard Specification Version 1.0

ꢁ

Memory Stick

−

Compliant with Memory Stick Standard Format Specification Version 1.4

Compliant with Memory Stick PRO Format Specification Version 1.00

−

•

xD Picture Card

−

Compliant with xD Picture Card Specification Version 1.00

Compliant with xD Picture Card Host Guideline Version 1.00

Backward compatible with the Smart Media

ꢀ

ExpressCard Interface

ꢁ

Compliant with EXPRESSCARD STANDARD Draft Release 1.0 (USB Interface Type only)

Pass USB signals from a USB-HOST to a Card Slot

System Interrupt

ꢁ

Support INTA#, INTB# and INTC# for PC system interrupt (Each unit is programmable.)

Support Serialized IRQ

IRQx support for ISA system interrupt

Support Remote Wake Up by CSTSCHG

ꢀ

Support an internal regulator to convert the 3.3V power into the power for the internal core logic

Support Zoomed Video Port (Bypass type)

Support PC Card LED, 1394 LED, SD LED, Memory Stick LED and xD Picture Card LED

Support BAY function with the PC Card passive adapter

ꢀ

Pin Compatible With:

R5C811 (CSP1616-208)

R5C821 (CSP1616-208)

R5C821PA (CSP1616-208)

R5C851 (CSP1616-208)

R5C851PA (CSP1616-208)

ꢀ

Package

ꢁ

208pin CSP (size=16x16mm, pitch=0.8mm, t=1.4mm)

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

2 BLOCK DIAGRAM

R5C841 Block Diagram

REQ#

CCLK

CRST#

CREQ#

Socket (Func#0)

GNT#

IDSEL

AD[31:0]

PCI

Address

Decode

CardBus

Interface

CGNT#

C/BE[3:0]#

PAR

FRAME#

Address

Decode

CCLKRUN#

CAD[31:0]

CC/BE[3:0]#

CPAR

CFRAME#

CDEVSEL#

CIRDY#

PCI

Interface

Master &

Target

DEVSEL#

Mapping

IRDY#

TRDY#

16-bit

Interface

STOP#

PERR#

SERR#

ADDR/DATA

Buffer

CTRDY#

PCI

Config.

Registers

Master

PCI to Card

PCICLK

CPERR#

CSERR#

PCIRST#

RESET

Clock

GBRST#

CLKRUN#

HWSPND#

Buffer

Manage

CCD1,2#

CVS1,2

CSTSCHG

CINT#

Socket

Status &

Control

CardBus

Registers

INTA#

INTB#

ADDR/DAT

Buffer

Interrupt

INTC#

CAUDIO

16-bit

Registers

Socket

Power

Control

SRIRQ#/UDIO0

UDIO1-UDIO5

RI_OUT#/PME#

SPKROUT

Audio

VCC3EN#, VCC5EN#

VPPEN0, VPPEN1

Card to PCI

USBDP,USBDM

1394 I/F (Func#1)

TPAP0

TPAN0

TPBP0

TPBN0

TPBIAS0

1394

OHCI

Controller

Registers

Cable Port 0

Cable Port 1

CPS

PHY

LINK Core

Registers

TPAP1

TPAN1

TPBP1

LINK

Interface

PLL

FIL0

TPBN1

TPBIAS1

Arbitration

& Control

SD I/F (Func#2)

SDCCLK

SDCDAT[3:0]

SDCCMD

SDCD#

SDWP#

Registers

SD Card

Interface

Clock

Control

SDPWR[1:0]

SDEXTCK

SDLED#

Buffer

RAM

Memory Stick I/F (Func#3)

MSCCLK

MSCDAT[3:0]

MSBS

MSCD#

MSPWR

MSEXTCK

MSLED#

Registers

Memory Stick

Interface

MDIO [19:00]

Clock

Buffer

RAM

Control

xD I/F (Func#4)

XDCDAT[7:0]

XDALE

Registers

xD Picture Card

Interface

XDCLE

XDCE#

XDWE#

XDRE#

XDPWR

XDCD[1:0]#

XDLED#

XDR/B#

XDWP#

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

PIN DESCRIPTION

3.1 Pin Assignments (208 pin CSP)

CSP Pin Assignment

ꢀ

Bottom View

{

VCC_

ROUT

MDIO00 NC

NC SPKROUT UDIO5 UDIO1

GND

PCICLK

AD30

AD26

IDSEL

AD21

AD19

AD17

AD16

{

MDIO01

HWSPND#GBRST# UDIO2 INTA#

INTC#

AD31

AD27 C/BE3#

AD22

AD20

AD18

C/BE2#

{

VCC_

PCI3V

MDIO02 MDIO03

FRAME#

{

VCC_

RI_OUT#/

UDIO0/

MDIO04

TEST

UDIO3

INTB# PCIRST# REQ#

AD28

AD24

AD23

IRDY# TRDY#

MD3V

PME#

SRIRQ#

{

MDIO05 MDIO06

MDIO07

VCC_3V VCC_3V UDIO4

GND

GND CLKRUN# GNT#

AD29

AD25

DEVSEL#

STOP# PERR#

{

VCC_

MDIO08 MDIO09

MDIO10 MDIO11

SERR#

PAR

C/BE1#

RIN

{

MDIO12 MDIO13

MDIO14 MDIO15

REGEN# AD15

AD14

AD13

{

MDIO16 MDIO17

MDIO18 MDIO19

AD12

AD11

AD10

AD9

{

AGND

GND

AD8

C/BE0#

AD7

AD6

{

AVCC_

PHY3V

GND

TPAN1 TPAP1

TPBIAS1

GND

{

VCC_

AVCC_

TPBN1 TPBP1

CPS

AD5

AD4

AD3

PCI3V

PHY3V

{

VCC_

TPAN0 TPAP0

TPBIAS0

AD2

AD1

AD0

PCI3V

{

VCC_

TPBN0 TPBP0

VREF

VCC5EN#VCC3EN#

VPPEN0 VPPEN1

RIN

{

VCC_

ROUT

AGND

FIL0

REXT

CDATA3 CD1#

USBDP USBDM

{

AGND AGND

GND

CD2#

CADR2 CADR4 CADR6 CADR24 CADR15

WE# CADR13 CADR8

CDATA4

CDATA11 CDATA5

{

CADR0 REG# WAIT#

VS2#

CADR7 CADR23 CADR22 CADR20 CADR18 CADR17 VS1#

CDATA12 CDATA6

{

AVCC_ AVCC_

PHY3V PHY3V

CDATA13 CDATA7

{

RDY/

IREQ#

{

WP/

CDATA9 CDATA8 BVD1 CADR1 CADR3 CADR5 CADR25 CADR12 CADR21

CADR14 IORD# CARD11 CE2# CDATA15

CDATA14

IOIS16#

{

CDATA10 CDATA2 CDATA1 CDATA0 BVD2 INPACK# RESET VCC_3V VCC_3V CADR16 GND CADR19 IOWR# CADR9

OE#

CADR10 CE1#

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

•

CSP Pin List

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

TEST

STOP#

PERR#

SERR#

PAR

C/BE1#

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

C/BE0#

AD7

AD6

AD5

T19

R16

R18

R19

P18

P19

P15

P16

N15

N16

N18

N19

M15

M16

M18

L16

L18

L19

K15

K16

K18

J15

OE#

VS1#

CADR11

CADR9

IORD#

C19

B19

A18

D15

B16

A16

B14

A14

D13

B13

A13

D12

B12

A12

D11

B11

A11

D10

B10

A10

CDATA2

CDATA10

WP/IOIS16#

CD2#

HWSPND#

SPKROUT

RI_OUT#/PME#

GBRST#

UDIO5

UDIO4

UDIO3

UDIO2

UDIO1

UDIO0/SRIRQ#

INTA#

INTB#

INTC#

CLKRUN#

PCIRST#

PCICLK

GNT#

REQ#

AD31

AD30

AD29

AD28

AD27

AD26

AD25

MDIO19

MDIO18

MDIO17

MDIO16

MDIO15

MDIO14

MDIO13

MDIO12

MDIO11

MDIO10

MDIO09

MDIO08

MDIO07

MDIO06

MDIO05

MDIO04

MDIO03

MDIO02

MDIO01

MDIO00

IOWR#

CADR8

CADR17

CADR13

CADR18

CADR14

CADR19

WE#

CADR20

RDY/IREQ#

CADR22

CADR21

CADR16

CADR15

CADR23

CADR12

CADR24

CADR7

CADR25

CADR6

VS2#

T11

V11

W11 AD3

T12

V12

AD4

AD2

AD1

W12 AD0

R13

T13

V13

VCC5EN#

VCC3EN#

VPPEN0

J16

J18

H15

H16

H18

H19

W13 VPPEN1

V14 USBDP

W14 USBDM

R14

T14

T15

V15 CDATA11

W15 CDATA5

V16 CDATA12

W16 CDATA6

V17 CDATA13

W17 CDATA7

W18 CDATA14

V19 CE1#

REXT

FIL0

VREF

AD24

C/BE3#

IDSEL

AD23

AD22

AD21

AD20

AD19

AD18

CADR5

RESET

CDATA3

CD1#

CDATA4

G15 CADR4

G16 WAIT#

G18 CADR3

G19 INPACK#

TPBP0

TPBN0

TPBIAS0

TPAP0

TPAN0

CPS

TPBP1

TPBN1

TPBIAS1

TPAP1

TPAN1

REGEN#

F15

F16

F18

F19

E16

E18

E19

D18

D19

C18

CADR2

REG#

CADR1

BVD2

CADR0

BVD1

CDATA0

CDATA8

CDATA1

CDATA9

AD17

AD16

C/BE2#

FRAME#

IRDY#

TRDY#

DEVSEL#

U18 CDATA15

U19 CADR10

T18 CE2#

Pin Name

Ball#

Pin Name

Ball#

AGND

GND

A9, B9, D9, D14, A15, B15

VCC_PCI3V

VCC_3V

W3, R11, R12

J1, J5, K5, E9, R10, T10, V10,

W10, L15, M19

F5, G5, J19, K19

VCC_MD3V

VCC_RIN

L2, C1, D1, E1, C2, D2, E2,

E4, E12

R6, E13

VCC_ROUT

AVCC_PHY3V

L1, E14

E10, E11, A17, B17

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

3.2 Pin Characteristics

Data Sheet

16-bit Card Interface

Pin Name Dir

TEST

CardBus Card Interface

Pin Name Dir

TEST

Pin Characteristics

Note

5Vtolerant

PwrRail

Drive

–

HWSPND#

SPKROUT

RI_OUT#/ PME#

GBRST#

UDIO5

HWSPND#

SPKROUT

RI_OUT#/ PME#

GBRST#

UDIO5

ꢁ

I/O

4mA

–

O (OD)

ꢁ

4mA

PCI

UDIO4

I/O

UDIO4

I/O

UDIO3

I/O

UDIO3

I/O

UDIO2

I/O

UDIO2

I/O

UDIO1

I/O

UDIO1

I/O

UDIO0/ SRIRQ#

INTA#

I/O

UDIO0/ SRIRQ#

INTA#

I/O

O (OD)

INTB#

INTC#

CLKRUN#

I/O

CLKRUN#

I/O

ꢁ

PCI

PCIRST#

PCICLK

GNT#

REQ#

AD31

PCIRST#

PCICLK

GNT#

REQ#

AD31

ꢁ

–

O (TS)

I/O

O (TS)

I/O

PCI

–

AD30

AD29

AD28

AD27

AD26

AD25

AD24

C/BE3#

IDSEL

AD23

C/BE3#

IDSEL

AD23

I/O

PCI

AD22

AD21

AD20

AD19

AD18

AD17

AD16

C/BE2#

FRAME#

C/BE2#

FRAME#

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

16-bit Card Interface

Pin Name Dir

IRDY#

CardBus Card Interface

Pin Name Dir

IRDY#

Pin Characteristics

Note

5Vtolerant

PwrRail

Drive

PCI

I/O

O (OD)

I/O

O (OD)

I/O

ꢁ

TRDY#

DEVSEL#

STOP#

PERR#

SERR#

PAR

TRDY#

DEVSEL#

STOP#

PERR#

SERR#

PAR

PCI

4mA

–

C/BE1#

AD15

C/BE1#

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

C/BE0#

AD7

C/BE0#

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

VCC5EN#

VCC3EN#

VPPEN0

VPPEN1

USBDP

USBDM

CDATA3

CD1#

VCC5EN#

VCC3EN#

VPPEN0

VPPEN1

USBDP

USBDM

CAD0

CCD1#

CAD1

CAD2

CAD3

CAD4

CAD5

CAD6

CAD7

–

I/O

I (PU)

I/O

I (PU)

I/O

–

ꢁ

4mA

–

CDATA4

CDATA11

CDATA5

CDATA12

CDATA6

CDATA13

CDATA7

CDATA14

ꢁ

4mA

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

16-bit Card Interface

Pin Name Dir

CE1#

CardBus Card Interface

Pin Name Dir

CC/BE0#

Pin Characteristics

Note

5Vtolerant

PwrRail

Drive

4mA

I/O

ꢁ

CDATA15

CADR10

CE2#

CAD8

CAD9

I/O

4mA

1mA

4mA

–

CAD10

CAD11

CVS1

I/O

OE#

I/O

VS1#

I/O

CADR11

IORD#

CAD12

CAD13

CAD14

CAD15

CC/BE1#

CAD16

CPAR

I/O

ꢁ

I/O

CADR9

IOWR#

I/O

CADR8

CADR17

CADR13

CADR18

CADR14

CADR19

WE#

I/O

ꢁ

I/O

–

CPERR#

–

I/O (PU)

CGNT#

CSTOP#

CINT#

CADR20

RDY/ IREQ#

CADR21

CADR16

CADR22

CADR15

CADR23

CADR12

I/O (PU)

I (PU)

I/O (PU)

O (TS)

I/O (PU)

I/O

I (PU)

CDEVSEL#

CCLK

4mA

O (TS)

CTRDY#

CIRDY#

CFRAME#

CC/BE2#

4mA

I/O

CADR24

CAD17

I/O

ꢁ

4mA

CADR7

CADR25

CADR6

VS2#

CAD18

CAD19

CAD20

CVS2

I/O

ꢁ

4mA

1mA

4mA

2mA

4mA

–

I/O

CADR5

RESET

CADR4

WAIT#

CADR3

INPACK#

CADR2

REG#

CAD21

CRST#

CAD22

CSERR#

CAD23

CREQ#

CAD24

CC/BE3#

CAD25

I/O

ꢁ

O (TS)

I/O

I (PU)

I/O

4mA

–

I (PU)

I/O

4mA

I/O

CADR1

I/O

BVD2/

SPKR#/

LED

I (PU)

CAUDIO

I (PU)

ꢁ

–

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

16-bit Card Interface

Pin Name Dir

CADR0

CardBus Card Interface

Pin Name Dir

CAD26

Pin Characteristics

Note

5Vtolerant

PwrRail

Drive

I/O

ꢁ

4mA

BVD1/

STSCHG#/

RI#

I (PU)

CSTSCHG

I (PD)

ꢁ

–

CDATA0

CDATA8

CDATA1

CDATA9

CDATA2

CDATA10

WP/ IOIS16#

CD2#

I/O

CAD27

CAD28

CAD29

CAD30

–

I/O

ꢁ

4mA

–

I/O

–

I/O

CAD31

CCLKRUN#

CCD2#

MDIO00

MDIO01

MDIO02

MDIO03

MDIO04

I/O

I (PU)

O (PU)

I (PU)

I/O (PU)

I (PU)

O (PU)

I (PU)

—

MDIO00

MDIO01

MDIO02

MDIO03

MDIO04

ꢁ

—

8mA

—

8mA

MDIO05 (SD)

(MS)

—/

O(PD)

MDIO05 (SD)

(MS)

—/

O(PD)

ꢁ

8mA

(xD)

MDIO06

MDIO07

MDIO06

MDIO07

ꢁ

8mA

—

MDIO08 (SD)

(MS)

I/O(PU)/ MDIO08 (SD)

I/O(PU)/

O(TS)/

O(PU)

O(TS)/

O(PU)

(MS)

(xD)

8mA

(xD)

MDIO09 (SD)

(MS)

I/O(PU)/ MDIO09 (SD)

I/O(PU)/

O(PU)

I/O(PU)/

O(PU)

(MS)

(xD)

MDIO10 (SD)

(MS)

I/O(PU)/ MDIO10 (SD)

I/O(PU)/

I/O/

I/O(PD)

I/O/

I/O(PD)

(MS)

(xD)

MDIO11 (SD)

(MS)

I/O(PU)/ MDIO11 (SD)

I/O(PU)/

I/O/

I/O(PD)

I/O/

I/O(PD)

(MS)

(xD)

MDIO12 (SD)

(MS)

I/O(PU)/ MDIO12 (SD)

I/O(PU)/

I/O/

I/O(PD)

I/O/

I/O(PD)

(MS)

(xD)

MDIO13 (SD)

(MS)

I/O(PU)/ MDIO13 (SD)

I/O(PU)/

I/O/

I/O(PD)

I/O/

I/O(PD)

(MS)

(xD)

MDIO14

MDIO15

MDIO16

MDIO17

MDIO18

MDIO19

I/O(PD)

O(PD)

MDIO14

MDIO15

MDIO16

MDIO17

MDIO18

MDIO19

I/O(PD)

O(PD)

8mA

O(PD)

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

16-bit Card Interface

Pin Name Dir

CardBus Card Interface

Pin Name Dir

Pin Characteristics

Note

5Vtolerant

PwrRail

Drive

FIL0

I/O

I(PD)

I/O

FIL0

CPS

I/O

I(PD)

I/O

CPS

1394

VREF

REXT

TPBN0

TPBP0

TPAN0

TPAP0

TPBIAS0

VREF

REXT

TPBN0

TPBP0

TPAN0

TPAP0

TPBIAS0

TPBN1

TPBP1

TPAN1

TPAP1

TPBIAS1

REGEN#

ꢁ

1394

—

TPBN1

TPBP1

ꢁ

TPAN1

TPAP1

TPBIAS1

REGEN#

Pin Type

I: Input Pin,

O: Output Pin,

I/O: Input Output Pin,

I (PU): Input Pin with Internal Pullup Resister,

I (PD): Input Pin with Internal Pulldown Resister,

I/O (PU): Input Output Pin with Internal Pullup Resister,

I/O (PD): Input Output Pin with Internal Pulldown Resister,

O (TS): Three State Output Pin,

O (OD): Open Drain Output Pin

Power Rail

P: VCC_PCI3V AP: AVCC_PHY3V R: VCC_RIN 3V: VCC_3V M: VCC_MD3V

Drive

PCI: PCI Compliant

CB: PCMCIA CardBus PC Card Compliant

1394:

IEEE1394a-2000 Compliant

Note

1: Pullup is attached when PC Card Interface is configured as a CardBus Interface Mode.

2: Pullup or Pulldown is configured according to the type of a card inserted.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

ꢂ

Small Card Pin Assignments

Media I/F

SD Card

Memory Stick

xD Picture Card

MDIO00

MDIO01

MDIO02

MDIO03

MDIO04

MDIO05

MDIO06

MDIO07

MDIO08

MDIO09

MDIO10

MDIO11

MDIO12

MDIO13

MDIO14

MDIO15

MDIO16

MDIO17

MDIO18

MDIO19

SDCD#

—

MSCD#

—

XDCD0#

XDCD1#

XDCE#

—

SDWP#

SDPWR0

SDPWR1

SDLED#

SDEXTCK

SDCCMD

SDCCLK

SDCDAT0

SDCDAT1

SDCDAT2

SDCDAT3

—

XDR/B#

XDPWR

XDWP#

XDLED#

—

MSPWR

—

MSLED#

MSEXTCK

MSBS

MSCCLK

MSCDAT0

MSCDAT1

MSCDAT2

MSCDAT3

—

XDWE#

XDRE#

XDCDAT0

XDCDAT1

XDCDAT2

XDCDAT3

XDCDAT4

XDCDAT5

XDCDAT6

XDCDAT7

XDCLE

—

XDALE

ꢂ

ExpressCard Pin Assignments PC Card Pin

PC CARD PIN 1-68 ASSIGNMENTS

16bit Card

CardBus

ExpressCard

GND

CAD0

GND

—

CAD1

—

CAD3

—

CAD5

—

CAD7

—

CE1#

A10

CCBE0#

CAD9

—

OE#

A11

A13

CAD11

CAD12

CAD14

CCBE1#

CPAR

CPERR#

CGNT#

CINT#

VCC

—

A14

WE#

READY/IREQ#

VCC

VPP

A16

VCC

—

VPP

CCLK

CIRDY#

A15

—

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

16bit Card

CardBus

ExpressCard

A12

CCBE2#

CAD18

CAD20

CAD21

CAD22

CAD23

CAD24

CAD25

CAD26

CAD27

CAD29

RFU

CCLKRUN

GND

CCD1#

CAD2

—

(PERST#)

—

GND

CCD1#

—

WP/IOIS16#

GND

CD1#

D11

D12

D13

D14

D15

CAD4

CAD6

RFU

CAD8

—

CE2#

VS1#

IORD#/RFU

IOWR#/RFU

A17

CAD10

CVS1

CAD13

CAD15

CAD16

RFU

CBLOCK#

CSTOP#

CDEVSEL#

VCC

—

CVS1

USBD+

USBD-

—

A18

A19

A20

A21

VCC

VPP

A22

A23

—

VCC

—

CPUSB#

—

CVS2

—

VPP

CTRDY#

CFRAME#

CAD17

CAD19

CVS2

CRST#

CSERR#

CREQ#

CCBE3#

CAUDIO

CSTSCHG

CAD28

CAD30

CAD31

CCD2#

GND

A24

A25

VS2#

RESET

WAIT#

INPACK#/RFU

REG#

SPKR#/BVD2

STSCHG#/BVD1

—

D10

CD2#

GND

CCD2#

GND

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

ꢂ

Small Card Pin Assignments PC Card Pin (using BAY)

PC CARD PIN 1-68 ASSIGNMENTS

xD Picture

16bit Card

CardBus

SD Card

Memory Stick

Card

GND

—

GND

CAD0

GND

—

GND

—

CAD1

—

CAD3

—

CAD5

—

CAD7

—

CE1#

A10

OE#

A11

CCBE0#

CAD9

—

XDWP#

—

CAD11

CAD12

CAD14

CCBE1#

CPAR

CPERR#

CGNT#

CINT#

VCC

XDCE#

XDALE

XDCLE

SMWP#

—

XDRE#

XDCD#

VCC

—

A13

A14

WE#

READY/IREQ#

VCC

VPP

A16

SDCCLK

—

VCC

MSCCLK

—

VCC

VPP

CCLK

—

A15

A12

CIRDY#

CCBE2#

CAD18

CAD20

CAD21

CAD22

CAD23

CAD24

CAD25

CAD26

CAD27

CAD29

RFU

CCLKRUN

GND

CCD1#

CAD2

CAD4

CAD6

RFU

CAD8

XDCDAT7

XDCDAT6

XDCDAT5

XDCDAT4

XDCDAT3

XDCDAT2

XDCDAT1

XDCDAT0

—

SDCDAT3

SDCDAT2

SDCDAT1

SDCDAT0

MSCDAT3

MSCDAT2

MSCDAT1

MSCDAT0

—

WP/IOIS16#

GND

CD1#

D11

—

GND

CCD1#

—

GND

CCD1#

—

MSBS

CVS1

—

GND

CCD1#

—

D12

D13

D14

D15

—

CE2#

VS1#

IORD#/RFU

IOWR#/RFU

CAD10

CVS1

CAD13

CAD15

SDCCMD

CVS1

—

XDWE#

CVS1

—

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

xD Picture

16bit Card

CardBus

SDCard

Memory Stick

Card

A17

A18

A19

A20

A21

VCC

VPP

A22

A23

CAD16

RFU

CBLOCK#

CSTOP#

CDEVSEL#

VCC

—

VCC

—

CVS2

—

SDCD#

—

VCC

—

CVS2

—

MSCD#

—

VCC

—

CVS2

—

XDR/B#

—

VPP

CTRDY#

CFRAME#

CAD17

CAD19

CVS2

CRST#

CSERR#

CREQ#

CCBE3#

CAUDIO

CSTSCHG

CAD28

CAD30

CAD31

CCD2#

GND

A24

A25

VS2#

RESET

WAIT#

INPACK#/RFU

REG#

SPKR#/BVD2

STSCHG#/BVD1

—

SDWP#

—

D10

CD2#

GND

CCD2#

GND

CCD2#

GND

CCD2#

GND

3.3 Pin Functions Outline

In this chapter, the detailed signal pins in the R5C841 are explained. Every signal is divided

according to their relational interface.

Card Interface signal pin is multi−functional pin. Card Interface mode is configured automatically by

the card insertion; CardBus card or 16-bit card. And the pin function is redefined again.

# mark means the signal is on either active or asserted when the signal is low−level. Otherwise,

no−mark means the signal is asserted when the signal is high−level.

The following the notations are used to describe the signal type.

Input Pin

Output Pin

OUT

Three State Output Pin

Open Drain Output Pin

Input Output Pin

OUT (TS)

OUT (OD)

I/O

Input Output Pin (Output is Open Drain)

I/O (OD)

s/h/z

Sustained Tri−State is an active low tri−state signal owned and driven by one and only one agent

at a time. The agent that drives an s/h/z pin low must drive it high for at least one clock before

letting it float. A new agent cannot start driving an s/h/z signal any sooner than one clock after the

previous owner tri−state is.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

3.3.1 PCI Local Bus interface signals

Data Sheet

Pin Name

Type

Description

PCI Bus Interface Pin Descriptions

PCICLK

CLKRUN#

PCI CLOCK: PCICLK provides timing for all transactions on PCI. All other PCI signals

are sampled on the rising edge of PCICLK.

I/O (OD)

PCI CLOCK RUN: This signal indicates the status of PCICLK and an open drain output

to request the starting or speeding up of PCICLK. This pin complies with Mobile PCI

specification. If CLKRUN# is not implemented, then this pin should be tied low. In this

case, CardBus clock is controlled by setting of StopClock bit included Socket Control

does not support CCLKRUN# and not insert Cards to socket. During PCI bus reset is

asserted, this pin placed in a high-impedance state.

And also, refer to the chapter 4.21 for the LED output.

PCIRST#

PCI RESET: This input is used to initialize all registers, sequences and signals of the

R5C841 to their reset states. PCIRST# causes the R5C841 to place all output buffers in

a high-impedance state. The negation of PCIRST# requires no-bounds.

AD [31:0]

I/O

ADDRESS AND DATA: Address and Data are multiplexed on the same PCI pins.

C/BE [3:0]#

BUS COMMAND AND BYTE ENABLES: Bus Command and Byte Enables are

multiplexed on the same PCI pins. During the address phase of transaction, C/BE [3:0]#

define the bus command. During the data phase C/BE [3:0]# are used as Byte Enables.

The Byte Enables are valid for the entire data phase and determine which byte lanes

carry meaningful data.

PAR

I/O

PARITY: Parity is even parity across AD [31:0] and C/BE [3:0]#. PAR is stable and valid

one clock after the address phase. For data phases, PAR is stable and valid one clock

after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read

transaction. The master drives PAR for address and write data phases; the target drives

PAR for read data phases.

FRAME#

TRDY#

I/O

s/h/z

CYCLE FRAME: This signal is driven by the current master to indicate the beginning

and duration of an access. FRAME# is asserted to indicate a bus transaction is

beginning. While FRAME# is asserted, data transfers continue. When FRAME# is

deasserted, the transaction is in the final data phase or has complete.

I/O

s/h/z

TARGET READY: This signal indicates the initialing agent‘s ability to complete the

current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data

phase is completed on any clock both TRDY# and IRDY# are sampled asserted. During

a read, TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that

valid data is present on AD [31:0]. During a write, it indicates the target is prepared to

accept data. Wait cycles are inserted both IRDY# and TRDY# are asserted together.

IRDY#

I/O

s/h/z

INITIATOR READY: This signal indicates the initiating agent‘s ability to complete the

current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data

phase is completed on any clock both TRDY# and IRDY# are sampled asserted. During

a write, IRDY# indicates that valid data is present on AD [31:0]. During a read, it

indicates the target is prepared to accept data. Wait cycles are inserted both IRDY# and

TRDY# are asserted together.

STOP#

IDSEL

I/O

s/h/z

STOP: This signal indicates the current target is requesting the master to stop the

current transaction.

INITIALIZATION DEVICE SELECT: This signal is used as chips select during

configuration read and write transactions.

DEVSEL#

I/O

s/h/z

DEVICE SELECT: When actively driven, indicates the driving device has decoded its

address as the target of the current access. As an input, DEVSEL# indicates whether

any device on the bus has been selected.

PERR#

I/O

s/h/z

PARITY ERROR: This signal is only for the reporting of data parity errors during all PCI

transactions except a Special Cycle. The R5C841 drives this output active “low” if it

detects a data parity error during a write phase.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

Pin Name

Type

Description

PCI Bus Interface Pin Descriptions (Continued)

SERR#

OUT (OD) SYSTEM ERROR: This signal is pure open drain. The R5C841 actively drives this

output for a single PCI clock when it detects an address parity error on either the primary

bus or the secondary bus.

REQ#

OUT (TS)

REQUEST: This signal indicates to the arbiter that the R5C841 desires use of the bus.

This is a point to point signal.

GNT#

GRANT: This signal indicates the R5C841that access to the bus has been granted. This

is a point to point signal.

GBRST#

GLOBAL RESET: This input is used to initialize registers for control of PME_Context

3.3.2 System Interrupt signals

Pin Name

Type

Description

System Interrupt Pin Descriptions

INTA#

OUT (OD) PCI INTERRUPT REQUEST A: This signal indicates a programmable interrupt request

generated from the PC Card interface. This signal is connected to the interrupt line of the

PCI bus.

INTB#

INTC#

OUT (OD) PCI INTERRUPT REQUEST B: This signal indicates a programmable interrupt request

generated from the IEEE 1394 interface. This signal is connected to the interrupt line of

the PCI bus.

OUT (OD) PCI INTERRUPT REQUEST C: This signal indicates a programmable interrupt request

generated from the Memory Stick interface, the SD Card interface or the xD Picture Card

interface. This signal is connected to the interrupt line of the PCI bus.

I/O (TS)

USER DEFINABLE INPUT/OUTPUT: These signals can be used as user-definable

input/output. Users can define functions such as *GPIO, LED, IRQ and so on for each

pin in the PC Card Misc Control 4 Register. For details, refer to “PCI-CardBus Bridge

Registers Descripion” in the registers description.

UDIO0/SRIRQ#

UDIO1/GPIO0

UDIO2/GPIO1

UDIO3/GPIO2

UDIO4/GPIO3

UDIO5/LED0#

*GPIO : General Purpose I/O

RI_OUT#/

PME#

OUT (OD) RING INDICATE OUTPUT: When 16-bit card is inserted and Ring Indicate Enable bit in

the Interrupt and General Control register is set to one, RI# on the IO Card is forwarded

to RI_OUT#.

POWER MANAGEMENT EVENT: When PME_En bit in Power Management

Control/Status register is set or when Power Status is set to any state mode except D0,

this signal is assigned as PME#.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

3.3.3 16-bit PC Card Interface signals

Data Sheet

Pin Name

Type

Description

16-bit PC Card Interface Pin Descriptions

CDATA [15:0]

CADR [25:0]

IORD#

IOWR#

OE#

I/O

16-bit Card DATA BUS SIGNALS [15:0]: Input buffer is disabled when the card socket

power supply is off or card is not inserted.

OUT (TS)

16-bit Card ADDRESS BUS SIGNALS [25:0]:

16-bit Card I/O READ:

16-bit Card I/O WRITE:

16-bit Card OUTPUT ENABLE:

16-bit Card WRITE ENABLE:

16-bit Card CARD ENABLE 1:

16-bit Card CARD ENABLE 2:

WE#

CE1#

CE2#

REG#

16-bit Card ATTRIBUTE MEMORY SELECT: This signal selects Attribute Memory

access or common memory access during 16bit memory cycle. Attribute memory

access is selected when this signal is “low” and common memory access is selected

when this signal is “high”.

READY/

IREQ#

16-bit Card READY/BUSY or INTERRUPT REQUEST: This signal has two different

functions. READY/BUSY# input on the memory PC card, and IREQ# input on the I/O

card.

WP/

IOIS16#

16-bit Card WRITE PROTECT or CARD IS 16-BIT PORT: This signal has two different

functions. Write Protect Switch input on the memory PC card, and IOIS16 input on the

I/O card.

RESET

WAIT#

OUT (TS)

16-bit Card CARD RESET:

16-bit Card BUS CYCLE WAIT:

BVD1/

STSCHG#/

RI#

16-bit Card BATTERY VOLTAGE DETECT 1 or STATUS CHANGE: This signal has

three different functions. The battery voltage detect input 1 on the memory PC card, and

Card Status Change#/Ring Indicate# input on the I/O card.

BVD2/

SPKR#/

LED

16-bit Card BATTERY VOLTAGE DETECT 2 or DIGITAL AUDIO or LED INPUT: This

signal has three different functions. The battery voltage detect input 2 on the memory

PC card, and SPEAKER# input or LED input on the I/O card.

INPACK#

CD1#

CD2#

VS1

16-bit Card INPUT ACKNOWLEDGE:

16-bit Card CARD DETECT 1: CD [2:1]# pins are used to detect the card insertion. CD

[2:1]# pins are used in conjunction with VS [2:1] to decode card type information.

16-bit Card CARD DETECT 2: CD [2:1]# pins are used to detect the card insertion. CD

[2:1]# pins are used in conjunction with VS [2:1] to decode card type information.

I/O

16-bit Card CARD VOLTAGE CAPABILITY SENSE 1: VS [2:1] pins are used in

conjunction with CD [2:1]# to decode card type information.

VS2

16-bit Card CARD VOLTAGE CAPABILITY SENSE 2: VS [2:1] pins are used in

conjunction with CD [2:1]# to decode card type information.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

3.3.4 CardBus PC Card Interface signals

Data Sheet

Pin Name

Type

Description

CardBus PC Card Interface Pin Descriptions

CCLK

OUT (TS)

CardBus Clock: This signal provides timing for all transactions on the PC Card

Standard interface and it is an input to every PC Card Standard device. All other

CardBus PC Card signals, except CRST# (upon assertion), CCLKRUN#, CINT#,

CSTSCHG, CAUDIO, CCD [2:1]#, and CVS [2:1], are sampled on the rising edge of

CCLK, and all timing parameters are defined with respect to this edge.

CCLKRUN#

I/O

s/h/z

CardBus Clock Run: This signal is used by cards to request starting (or speeding up)

clock; CCLK. CCLKRUN# also indicates the clock status. For PC cards, CCLKRUN# is

an open drain output and it is also an input. The R5C841 indicates the clock status of the

primary bus to the CardBus card.

CRST#

OUT (TS)

I/O

CardBus Card Reset: This signal is used to bring CardBus Card specific registers,

sequencers and signals to a consistent state. Anytime CRST# is asserted, all CardBus

card output signals will be driven to their begin state.

CAD [31:0]

CardBus Address/Data: These signals are multiplexed on the same CardBus card

pins. A bus transaction consists of an address phase followed by one or more data

phases. CardBus card supports both read and write bursts. CAD [31:0] contains a

physical address (32 bits). For I/O, this is a byte address; for configuration and memory

it is a DWORD address. During data phases, CAD [7:0] contains the east significant byte

(LSB) and CAD [31:24] contains the most significant byte (MSB). Write data is stable

and valid when CIRDY# is asserted and read data is stable and valid when CTRDY# is

asserted. Data is transferred during those clocks where both CIRDY# and CTRDY# are

asserted.

CC/BE [3:0]#

I/O

CardBus Command/Bye Enables: These signals are multiplexed on the same

CardBus card pins. During the address phase of a transaction, CC/BE [3:0]# define the

bus command. During the data phase, CC/BE [3:0]# are used as Byte Enables. The Byte

Enables are valid for the entire data phase and determine which byte lanes carry

meaningful data. CC/BE [0]# applies to byte 0 (LSB) and CC/BE [3]# applies to byte 3

(MSB).

CPAR

CardBus Parity: This signal is even parity across CAD [31:0] and CC/BE [3:0]#. All

CardBus card agents require parity generation. CPAR is stable and valid clock after

either CIRDY# is asserted on a write transaction or CTRDY# is asserted on a read

transaction. Once CPAR is valid, it remains valid until one clock after the completion of

the current data phase. (CPAR has the same timing as CAD [31:0] but delayed by one

clock.) The master drives CPAR for address and write data phases; the target drives

CPAR for read data phases.

CFRAME#

CIRDY#

I/O

s/h/z

CardBus Cycle Frame: This signal is driven by the current master to indicate the

beginning and duration of a transaction. CFRAME# is asserted to indicate that a bus

transaction is beginning. While CFRAME# is asserted, data transfers continue. When

CFRAME# is deasserted, the transaction is in the final data phase.

I/O

s/h/z

CardBus Initiator Ready: This signal indicates the initiating agent’s (bus master’s)

ability to complete the current data phase of the transaction. CIRDY# is used in

conjunction with CTRDY#. A data phase is completed on any clock both CIRDY# and

CTRDY# are sampled asserted. During a write, CIRDY# indicates that valid data is

present on CAD [31:0]. During a read, it indicates the master is prepared to accept data.

Wait cycles are inserted until both CIRDY# and CTRDY# are asserted together.

CTRDY#

I/O

s/h/z

CardBus Target Ready: This signal indicates the agent’s (selected target’s) ability to

complete the current data phase of the transaction. CTRDY# is used in conjunction with

CIRDY#. A data phase is completed on any clock both CTRDY# and CIRDY# are

sampled asserted. During a read, CTRDY# indicates that valid data is present on CAD

[31:0]. During a write, it indicates the target is prepared to accept data. Wait cycles are

inserted until both CIRDY# and CTRDY# are asserted together.

CSTOP#

I/O

CardBus Stop: This signal indicates the current target is requesting the master to stop

s/h/z

the current transaction.

CDEVSEL#

I/O

s/h/z

CardBus Device Select: This signal indicates the driving device has decoded its

address as the target of the current access when actively driven. As an input,

CDEVSEL# indicates whether any device on the bus has been selected.

CREQ#

CardBus Request: This signal indicates to the arbiter that this agent desires use of the

bus. Every master has its own CREQ#.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

Pin Name

Type

Description

CardBus PC Card Interface Pin Descriptions (Continued)

CGNT#

OUT

CardBus Grant: This signal indicates to the agent that access to the bus has been

granted. Every master has its own CGNT#.

CPERR#

CSERR#

CINT#

I/O

s/h/z

CardBus Parity Error: This signal is only for the reporting of data parity errors during all

CardBus Card transactions except a Special Cycle. An agent cannot report a CPERR#

until it has claimed the access by asserting CDEVSEL# and completed a data phase.

CardBus System Error: This signal is for reporting address parity errors, data parity

errors on the Special Cycle command, or any other system error where the result could

be catastrophic.

CardBus Interrupt Request: This signal is an input signal from CardBus card. It is level

sensitive, and asserted low (negative true), using an open drain output driver. The

assertion and deassertion of CINT# is asynchronous to CCLK.

CSTSCHG

CardBus Card Status Change: This signal is an input signal used to alert the system to

changes in the READY, WP, or BVD [2:1] conditions of the card. It is also used for the

system and/or CardBus card interface Wake up. CSTSCHG is asynchronous to CCLK.

CAUDIO

CCD1#

CCD2#

CVS1

CardBus Card Audio: This signal is a digital audio input signal from a CardBus Card to

the system’s speaker. CAUDIO has no relationship to CCLK.

CardBus Card Detect 1: CCD [2:1]# pins are used to detect the card insertion. CCD

[2:1]# pins are used in conjunction with CVS [2:1] to decode card type information.

CardBus Card Detect 2: CCD [2:1]# pins are used to detect the card insertion. CCD

[2:1]# pins are used in conjunction with CVS [2:1] to decode card type information.

I/O

CardBus Card Voltage Sense 1: CVS [2:1] pins are used in conjunction with CCD

[2:1]# to decode card type information.

CVS2

CardBus Card Voltage Sense 2: CVS [2:1] pins are used in conjunction with CCD

[2:1]# to decode card type information.

3.3.5 Socket Power Control signals

Pin Name

Type

Description

Socket Power Control Signal Descriptions

VCC5EN#

VCC3EN#

VPPEN0

VPPEN1

OUT

VCC 5V ENABLE:

VCC 3.3V ENABLE:

VPP ENABLE 0:

VPP ENABLE 1:

3.3.6 Other signals

Pin Name

Type

Description

Other Signals Descriptions

SPKROUT

HWSPND#

I/O

SPEAKER OUTPUT: This signal is a digital audio output from SPKR#, and Connecting

this signal to pull-down sets the Serial ROM mode.

Hardware Suspend: This signal works as HWSPND# input. PCIRST# is not accepted

as long as HWSPND# is asserted so that VCC_PCI3V can be powered off. When Serial

IRQ mode is set, HWSPND# must be asserted after Serial IRQ mode on the chip-set

has been deasserted. When Hardware Suspend mode is off, HWSPND# must be

deasserted before Serial IRQ mode is enabled. When a power is on, follow the reset

sequence shown in the chapter 4.10 in order to confirm the input of PCIRST# and PCLK.

TEST

TEST: This signal is a test mode pin. Usually, this pin must be tied low.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

3.3.7 IEEE1394 PHY Interface signals

Data Sheet

Pin Name

Type

Description

IEEE1394 Cable Interface Pin Descriptions

TPAP1

TPAP0

I/O

TPA Positive : Twisted-pair cable A (positive) differential signal terminals.

TPB Positive : Twisted-pair cable B (positive) differential signal terminals.

TPA Negative : Twisted-pair cable A (negative) differential signal terminals.

TPB Negative : Twisted-pair cable B (negative) differential signal terminals.

TPBP1

TPBP0

TPAN1

TPAN0

TPBN1

TPBN0

TPBIAS1

TPBIAS0

TP Bias : Twisted-pair bias output. This pin is compliant with the IEEE1394a-2000, and

also monitors Insertion/desertion of other cables

CPS

Cable Power Status : This pin detects the Cable Power Status. See in Spec.4.22.3 for

details of CPS.

3.3.8 IEEE1394 Control signals

Pin Name

Type

Description

IEEE1394 Control Pin Descriptions

VREF

I/O

Voltage reference Resistance : It is necessary to connect a capacitance of 0.01uF

between this pin and AGND.

REXT

Resistance External: It is necessary to connect a resistor of 10kΩ±1% between this pin

and AGND.

OUT

I/O

X’tal In : 24.576MHz

FIL0

X’tal Out : 24.576MHz

Filter : This pin connects to the PLL Filter. It is necessary to connect a capacitance of

0.01uF between this pin and AGND.

3.3.9 USB Interface signals

Pin Name

Type

Description

USB Interface Pin Descriptions

USBDP

USBDM

I/O

USB Data Port: These signals are differential signals. These signals are connected to HOST

USB D+/D- signals.

PC Card

Pin Name

Type

Description

USB Interface Pin Descriptions

USBD+

USBD-

IORD#

IOWR#

CADR22

I/O

USB Data Port: These signals are differential signals.

CPUSB#

USB ExpressCard Detect: This signal indicates whether the USB ExpressCard

is inserted to a socket.

PERST#

CDATA2

OUT

ExpressCard Reset : This signal is a reset signal to ExpressCard.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

3.3.10 Small Card Interface signals

Data Sheet

ꢃ

SD Card

MDIO Pin

Name

Pin Name

Type

Description

SD Card Control Pin Descriptions

SDCDAT0

SDCDAT1

SDCDAT2

SDCDAT3

SDCCMD

SDCCLK

SDWP#

MDIO10

MDIO11

MDIO12

MDIO13

MDIO08

MDIO09

MDIO03

I/O

OUT

SD Data [3:0] : SD Card 4bit data bus signals.

SD Command : SD Card Command signal.

SD Clock : SD Card Clock signal.

SD Write Protect : This signal indicates the state of SD card’s write protect

switch. This pin is connected to a reserved pin of the SD card socket.

SDCD#

MDIO00

MDIO07

MDIO04

MDIO05

MDIO06

SD Card Detect : This signal indicates whether the SD card is inserted to a

socket. This pin is connected to a reserved pin of the SD card socket.

SDEXTCK

SDPWR0

SDPWR1

SDLED#

SD External Clock : This signal must be connected to GND because the

R5C841 does not support SDEXTCK for the SD Card.

OUT

SD Card Power0 Control : This signal is provided to control the power supply

(3.3V) for an SD card.

SD Card Power1 Control : This signal is provided to control the power supply

(1.8V) for an SD card. R5C841does not support this signal.

SD Card LED Control : This signal indicates an access state to the SD card.

ꢃ

Memory Stick

MDIO Pin

Name

Pin Name

Type

Description

Memory Stick Control Pin Descriptions

MSCDAT0

MSCDAT1

MSCDAT2

MSCDAT3

MSBS

MDIO10

MDIO11

MDIO12

MDIO13

MDIO08

MDIO09

MDIO01

I/O

Memory Stick Data [3:0] : Memory Stick Data signals. Normally, MSCDAT0 only

is used.

I/O

OUT

Memory Stick Bus State : Memory Stick Bus State signal.

MSCCLK

MSCD#

Memory Stick Clock : Memory Stick Clock signal.

Memory Stick Card Detect : This signal indicates whether the Memory Stick is

inserted to a socket. This pin is connected to the INS signal of Memory Stick.

MSEXTCK

MDIO07

Memory Stick External Clock : This signal is input to the Memory Stick block.

This clock supports 0 - 40MHz. If the internal PCICLK is used, this signal can be

connected to GND.

MSPWR

MSLED#

MDIO04

MDIO06

OUT

Memory Stick Power Control : This signal is provided to control the power

supply for the Memory Stick.

Memory Stick LED Control : This signal indicates an access state to the

Memory Stick.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

ꢃ

xD Picture Card

MDIO Pin

Name

Pin Name

Type

Description

xD Picture Card Control Pin Descriptions

xD Picture CardData [7:0] : xD Picture Card Data bus signals.

XDCDAT0

XDCDAT1

XDCDAT2

XDCDAT3

XDCDAT4

XDCDAT5

XDCDAT6

XDCDAT7

XDCLE

MDIO10

MDIO11

MDIO12

MDIO13

MDIO14

MDIO15

MDIO16

MDIO17

MDIO18

MDIO19

MDIO00

MDIO01

MDIO05

I/O

OUT

xD Picture Card CLE : xD Picture Card Command Latch Enable signal.

XDALE

xD Picture Card ALE : xD Picture Card Address Latch Enable signal.

XDCD0#

XDCD1#

XDWP#

xD Picture Card Detect : These signals indicate a detection of the xD Picture

Card when two signals are set to ‘Low’ by insertion of xD Picture Card.

OUT

xD Picture Card Write Protect : This signal indicates the state of xD Picture

Card’s write protect. This pin is connected to the -WP signal of the xD Picture

Card.

XDPWR

XDR/B#

XDLED#

MDIO04

MDIO03

MDIO06

OUT

xD Picture Card Power Control : This signal is provided to control the power

supply for the xD Picture Card.

xD Picture Card R/B : xD Picture Card Ready/Busy signal. When this signal is

low, xD Picture Card is busy.

OUT

xD Picture Card LED Control: This signal indicates an access state to the xD

Picture Card.

XDWE#

XDCE#

XDRE#

MDIO08

MDIO02

MDIO09

OUT

xD Picture Card Write Enable: xD Picture Card Write Enable signal.

xD Picture Card Enable: xD Picture Card Enable signal.

xD Picture Card Read Enable: xD Picture Card Read Enable signal.

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3.3.11 Power and GND signals

Data Sheet

Pin Name

Type

Description

Power Pin Descriptions

Regulator Enable: This pin controls an internal regulator. Setting this pin to ‘Low’ enables

the internal regulator, and setting this pin to ‘High’ disables it.

REGEN#

VCC_PCI3V

VCC_3V

PWR

PCI VCC: Power Supply pins for the PCI interface signals. This pin can be powered at 3.3V.

3V VCC : This supply pin is connected to 3.3V. This pin must not be off on the suspend

mode because of the power supply for PME# and GBRST#. This pin supplies for a socket of

the PC Card Controller also.

VCC_MD3V

VCC_RIN

PWR

Media VCC: Power Supply pins for the Media interface signals. This pin can be powered at

3.3V.

Regulator Input: Power supply input pins for an internal regulator. This pin is connected to

3.3V when an internal regulator is enabled, and to the same power as that of VCC_ROUT

(1.8V) when the regulator is disabled.

VCC_ROUT

PWR

Regulator Output: Power supply output pins for an internal regulator and power supply

pins for the internal core logic. This pin is powered as an output from an internal regulator

and as an input to the core logic when an internal regulator enabled, and connected to 1.8V

as input to the core logic when the regulator disabled. Add bypass condensers between this

pin and GND.

AVCC_PHY3V

1394 PHY VCC: Power supply for PHY analog block. This pin can be powered at 3.3V. This

pin must not be off on the suspend mode because of the power supply for Cable interface

block.

GND

PWR

Digital GND:

Analog GND:

AGND

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

4 FUNCTIONAL DESCRIPTION

4.1 Device Configuration

The R5C841 supports PCI-CardBus Bridge Interface functions for the PC Card socket, the

PCI-IEEE1394 bridge function, the SD Card interface, the Memory Stick interface and the xD

Picture Card interface. Logically the R5C841 looks to the primary PCI as a separate secondary

bus residing in a single device. The PC Card, the IEEE 1394, the SD Card, the Memory Stick and

the xD Picture Card have their own register spaces.

4.1.1 PCI Configuration Register Space

The PCI Configuration registers are used to control the basic operations, as settings and status

control of the PCI device. Each function has 256 byte of configuration space.

4.1.2 CardBus (32-bit) Card Control Register Space

The CardBus Card Control registers are used to manage status changed events, remote wakeup

events and status information about the PC Card in the socket. These registers are used for PC

Card-32 as well as PC Card-16. The PC Card Control Register Base Address register points to

the 4 Kbyte memory mapped I/O space that contains both the PC Card-32 and PC Card-16

Status and Control registers. Socket Status/Control Registers for Card-32 are placed in the lower

2Kbyte of the 4Kbyte and start at offset 000h.

4.1.3 16-bit Card Control Register Space

The Socket Status/Control Registers for the PC Card-16 are placed in the upper 2Kbyte of the

4Kbyte pointed by the PC Card Control Register Base Address register and start at offset 800h.

4.1.4 16-bit Legacy Port

Legacy mode allows all 16-bit Card Control registers to be accessed through the index/data port

at I/O address 3E0/3E2 in order to maintain the backward compatibility like the Ricoh

RF5C396/366 that is the Intel 82365-compatible device.

4.1.5 1394 OHCI-LINK Register Space

The 1394 OHCI-LINK registers are 2Kbyte of register compliant with the 1394 OHCI

specifications. The 1394 OHCI Register Base Address register points to the 2Kbyte memory

mapped I/O space. These registers are used to control OHCI-LINK and to set DMA context.

4.1.6 1394 PHY Register Space

The 1394 PHY registers are compliant with the IEEE1394a-2000 standard specifications. These

registers are used to set the PHY block (ex. the value of Gap count.) and are accessed through

the PHY Control register in the 1394 OHCI-LINK register space.

4.1.7 SD Card Control Register Space

The SD Card Control registers, compliant with the SD Host Controller Standard specification, are

256byte of register assigned to control the SD card. These registers are used to set for access to

the SD card, to give commands and to read/write data. These are placed in the memory mapped

I/O space by the SD Card Register Base Address register.

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4.1.8 Memory Stick Control Register Space

Data Sheet

The Memory Stick Control registers are 256byte of register assigned to control the Memory Stick.

These registers are used to set for access to the Memory Stick, to give commands and to

read/write data. These are placed in the memory mapped I/O space by the Memory Stick

4.1.9 xD Picture Card Control Register Space

The xD Picture Card Control registers are 256byte of register assigned to control the xD Picture

Card. These registers are used to set for access to the xD Picture Card, to give commands and to

read/write data. These are placed in the memory mapped I/O space by the xD Picture Card

4.2 CardBus Card Configuration Mechanism

The R5C841 provides a mechanism to access to configuration spaces of a CardBus Card, which

is compliant with the PCI specifications. The R5C841 supports functions of changing Type 1 PCI

configuration command into Type 0 CardBus configuration command and transferring them.

4.3 Address Window and Mapping Mechanism

The R5C841 supports two kinds of PCI-Card Bridge Interface functions, and determines

automatically whether an inserted card is a CardBus Card or a 16-bit Card. Each interface can be

set independently.

On the CardBus Card interface, the transaction is implemented by two I/O windows and two

memory map I/Os or a prefetchable memory window that defined in the PCI configuration space.

The CardBus Card address and the PCI system address use a flat address in common. So the

address range specified by a base register and a limit register is forwarded from the PCI to the

CardBus Card. The R5C841 supports a CardBus Master also, so the address forwarding

transaction from the CardBus Card to the PCI or to the other card also is enabled. If the address

of the transaction started on the CardBus is out of the address range, it will be forwarded to the

PCI.

On the 16-bit Card interface, the transaction is implemented by two I/O windows and five memory

windows, which are set by the 16-bit Card Status Control register and are compliant with the

PCIC. The address forwarding transaction is enabled only from PCI to CardBus.

4.3.1 ISA Mode

The R5C841 supports ISA mode for PCI-CardBus Bridge function. Setting ISA enable bit of the

Bridge Control register enables the ISA mode. The ISA mode is applied to the I/O transaction of

particular address range specified by the I/O Base registers and the I/O Limit registers, which are

also in the first 64K Byte of PCI I/O space (0000_0000h-0000_FFFFh).

By enabled the ISA mode, the I/O transaction for the first 256-byte of each 1-Kbyte, which start

address are 0000x000h, 0000x400h, 0000x800h and 0000xC00h, are forwarded from PCI to

CardBus. The last 768-byte is blocked. Conversely, the I/O transaction in the last 768-byte is

forwarded from CardBus to PCI.

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4.3.2 VGA Support

Data Sheet

The R5C841 supports accesses to the CardBus interface bridge and the VGA compatible devices

that is downstream of the bridge. When the VGA Enable bit in the Bridge Control register is set,

the R5C841 positively decodes and forwards accesses to VGA frame buffer addresses and I/O

accesses to VGA registers from PCI to CardBus interface. The address range is as follows.

Memory address :

I/O address :

0A0000h to 0BFFFFh

AD[9:0] = 3B0h to 3BBh, and 3C0h to 3DFh

(inclusive of ISA address aliases - AD[15:10] are not decoded.)

And also, the R5C841 can forward only write transaction to the VGA Palette register of the

following ranges.

Palette address :

AD [9:0] = 3C6h, 3C8h, and 3C9h

(Inclusive of ISA address aliases - AD [15:10] are not decoded.)

4.4 16-bit Card Interface Timing Control

The R5C841 generates the timing of address, data, and command for the 16-bit Card interface.

Each timing is set in a timer granularity of PCI clock as shown below. When 16-bit I/O enhanced

Timing or 16-bit Memory Enhanced Timing bit in each socket control register space is cleared,

the default timing is selected regardless of the I/O Win 0-1 Enhanced Timing bit or Memory

Enhanced Timing bit. Default timing is selected when the value smaller than the minimum value is

set.

16-bit Card Signal Timing Example

PCICLK

CADR,REG#

Address Setup Time

Command Active Time

Address Hold Time

OE#, WE#

IOW#, IOR#

CDATA

Data

Symbol

Parameter

Min

Max

Default

Unit

I/O Read/ Write

Tsu

Tpw

Thl

Address Setup Time

Command Active Time

Address Hold Time

Memory Read/ Write

Address Setup Time

Command Active Time

Address Hold Time

PCI Clocks (Typ=30ns)

Tsu

Tpw

Thl

3 (4) Note 1

6 (8or18) Note 2

1(2) Note 3

PCI Clocks (Typ=30ns)

Note1 : 4PCI clocks for 3.3v card attribute memory access.

Note2 : 8 PCI clocks for 5v card attribute memory access.

18 PCI clocks for 3.3v card attribute memory access.

Note3 : 2PCI clocks for 3.3v card attribute memory access.

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4.5 Data Buffers, Posting Write, Prefetching Read

Data Sheet

The R5C841 provides data buffers, address buffers, and command buffers in order to maintain a

high-speed data transfer between the PCI bus and the CardBus. The transaction from the PCI

bus to the CardBus allows 8-DWORD buffers of Posting Write Data and Prefetching Read Data.

Conversely, the transaction from the CardBus to the PCI bus allows 12-DWORD buffers of

Posting Write Data and Prefetching Read Data. Posting of write data is permitted a master to end

writing data before a target’s end of writing data. The transactions that cross the R5C841 in either

direction enable a high-speed transfer.

The R5C841 provides a high-speed data transfer by PCI burst transfers when Prefetching Read

Data or Posting Write Data is implemented on the PCI bus and the 1394 bus. Accesses to the SD

Card, the Memory Stick and the xD Picture Card do not support the PCI burst transfers.

4.6 Error Support

4.6.1 Parity Error

The R5C841 provides the parity generation and the parity error detection on both the primary PCI

bus and the secondary CardBus. Having detected an address parity error, the R5C841 asserts

SERR# and sets the Detected Parity Error bit in the PCI Status register. Having detected a data

parity error, the R5C841 asserts PERR# and sets the Detected Parity Error bit in the PCI Status

parity on to the opposite interface if possible. This enables the parity error recovery mechanisms

outlines in the PCI Local Bus Specification without special considerations for the presence of a

bridge in the path of the transaction.

4.6.2 Master Abort

Having the occurred master abort at the destination, the R5C841 implements one of two

transactions. One is a transaction that is compatible with ISA to invalidate data. (Returns all “1”

when read and invalidates the data when write.) The other way is to assert SERR#.

4.6.3 Target Abort

Having the occurred target abort at the destination, the R5C841 transmits errors as target abort to

the original master as thoroughly as possible. But, if cannot, the R5C841 asserts SERR# and

transmits errors to the system.

4.6.4 CardBus System Error

Having the asserted CSERR# on the secondary CardBus interface, the R5C841 always asserts

SERR# on the primary PCI interface and transmits errors to the system.

4.6.5 PCI Bus Error concerned with 1394 OHCI

On the 1394 OHCI function, the R5C841 provides occurred PCI Bus errors and some information

to recover the errors to system software, via the Context register or the descriptor.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

4.7 Interrupts

Data Sheet

The R5C841 supports PCI interrupt signals INTA#, INTB# and INTC# as well as ISA interrupt

signals IRQx. They transmit to the system the Card Status Change Interrupt as a card

insert/remove event, the Function Interrupt by the PC card, the DMA Interrupt and the Device

Interrupt defined on 1394 OHCI, and interrupts defined on SD Card/Memory Stick/xD Picture

Card interface. INTA# is assigned to the PC Card interface, INTB# is assigned to the 1394 OHCI

and INTC# is assingned to the SD Card/Memory Stick/xD Picture Card interface. Interrupts of the

PC Card interface and the 1394 can be reassigned by the INT Select bits (bit1, 0) of the 1394

Misc Control 2 register, and Interrupts of SD Card/Memory Stick/xD Picture Card interface can be

reassigned by the INT Select bits (bit26, 25) of the SD Misc Control register / the MS Misc Control

INT Select

bit26 bit25

PC Card

1394

SD/MS/xD

bit1

bit0

INTA#

INTB#

INTA#

Reserved

INTC#

INTB#

INTA#

On the PC Card, setting the IRQ-ISA Enable bit of the Bridge Control register enables the IRQx

routing register for PC Card-16/32. On the other hand, setting CINT-ISA Disable bit (Config.A0h

bit6) disables the 32bit Function Interrupt to route into the ISA Interrupt and enables to route into

the INT Interrupt. And also, setting the Card Status Change Interrupt Configuration register on the

16bit Control registers the 16bit Card Status Change Interrupt to route into the ISA Interrupt. But,

the R5C841 doesn’t support IRQ-ISA function on 1394 OHCI.

On the 1394 OHCI, the R5C841 transmits interrupt signals to the host on the end of the DMA

transaction, and also transmits interrupts of the LINK layer and the PHY layer. The IntEvent

enable the selected interrupt. Writing into the IntEventClear by software enables to clear the

interrupt.

On the SD Card interface, the Memory Stick interface and the xD Picture Card interface, the

R5C841 can inform a card insert/remove event or an error as an interrupt to the system. PCI

interrupt signals are open drain outputs. When ISA-IRQ mode is enabled, IRQx signals are

programmable to either positive edge mode or level mode. RI_OUT# can be reassigned to an

interrupt signal such as Remote Wakeup signal.

In addition to primary interrupt functions, the R5C841 supports Serialized IRQ. When SRIRQ

Enable bit (bit 7) of the PC Card Misc Control register is set to ‘1b’, UDIO0 works as SRIRQ#

(default). And GPIO and LED0# are also enabled. SRIRQ# output enables a Wired-OR structure

that simply transfer a state of one or more device’s IRQ to the host controller. Both of a device

and a host controller enables a transferring start.

A transferring, called an IRQSER Cycle, consists of three frame types: one Start Frame, several

IRQ/Data Frames, and one Stop Frame. When the SR_PCI_INT_Disable bit (bit5) of the PC Card

Misc control register is ‘Low’, frames of INTA#, INTB#, INTC# and INTD# (PCI Interrupt signals)

are output following IOCHK# frame are output. When it is ‘High’, IRQx only are output from

SRIRQ#.

All cycle uses PCICLK as its clock source. The IRQSER Start Frame has two operation modes:

Quiet (Active) mode and Continuous (Idle) mode. On the Quiet (Active) mode, any device can

initiate a Start Frame. By occurring of interruptive requests, the R5C841 outputs 1-pulse of

PCICLK (Low) and Serialized IRQ is kept on Hi-Z during the rest of a Start Frame. After that,

IRQ/DATA Frame follows.

In Continuous (Idle) mode, only Host Controller can initiate a Start Frame. The R5C841 becomes

waiting state to detect 4-8 PCICLK of Start Pulse. These modes change automatically by

monitoring the Stop pulse width in a Stop Frame. Quiet (Active) mode is repeated when width of

Stop Pulse is 2PCICLK, and Continuous (Idle) mode is repeated when it is 3PCICLK. After

assertion of the GBRST#, the default is Continuous (Idle) mode.

Timing of the Start Frame and the Stop Frame is as follows.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

Start Frame timing with source sampled a low pulse on IRQ1

START FRAME

IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME

PCICLK

START¹

IRQSER

IRQ1 Host Controller

None

IRQ1

None

Drive Source

1. Start Frame pulse can be 4-8 clocks wide.

Stop Frame Timing with Host using 17 IRQSER sampling period

IRQ14

FRAME

IRQ15

FRAME

IOCHCK#

FRAME

STOP FRAME

NEXT CYCLE

START³

I ²

PCICLK

IRQSER

Driver

STOP¹

None

IRQ15

None

Host Controller

H=Host, SL=Slave Control, R=Recovery, T=Turn-around, S=Sample

1. Stop Pulse is 2 clocks wide for Quiet mode, and 3 clocks wide for Continuous mode.

2. There may be none, one or more Idle states during the Stop Frame.

3. The next IRQSER cycle’s Start Frame pulse may or may not start immediately after the turn-around

clock of the Stop Frame.

IRQSER Sampling Periods

IRQ/Data Frame

Signal Sampled

IRQ0

# of clocks past Start

IRQ1

SMI#

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

IRQ9

32:22

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IOCHCK#

INTA#

INTB#

INTC#

INTD#

Unassigned

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

4.8 Card Type Detection

Data Sheet

If once a valid insertion is detected, the socket state machine in the R5C841 starts to interrogate

the PC Card to determine whether it is a CardBus Card, a 16-bit PC Card or an ExpressCard.

The R5C841 supports VCC values of 5V, 3.3V and combination of them at the socket interface.

Card type can be known by reading the Socket Present State register.

Card Type

CD2#

ground

CD1#

ground

VS2#

open

VS1#

open

Key

Interface

Voltage

5V 16bit PC Card

open

ground

5V 16bit PC Card 5V and 3.3V

ground

5V 16bit PC Card 5V, 3.3V and

X.XV

ground

open

ground

LV 16bit PC Card

3.3V

connect to

CVS1

connect to

CCD1#

CardBus

PC Card

ground

LV 16bit PC Card 3.3V and X.XV

connect to

CVS2

connect to

CCD2#

CardBus

PC Card

3.3V and X.XV

connect to

CVS1

ground

connect to

CCD2#

CardBus

PC Card

3.3V, X.XV and

X.XV

ground

open

LV 16bit PC Card

X.XV

connect to

CVS2

connect to

CCD2#

CardBus

PC Card

ground

connect to connect to

open

CardBus

PC Card

X.XV and Y.YV

Y.YV

CVS2

CCD1#

connect to

CVS1

ground

open

connect to

CCD2#

CardBus

PC Card

ground

connect to

CVS1

ground

connect to

CCD1#

Reserved

ground

connect to connect to

CVS2 CCD1#

connect to connect to connect to

ground

Reserved

open

ExpressCard

CVS2

CCD1#,

CCD2#

Small Card (BAY)

4.9 Mixed Voltage Operation

The R5C841 has 5 independent power rails. The power for Card (VCC_3V) and PCI

(VCC_PCI3V) is powered at 3.3V. The R5C841 can support either 3.3V or 5V for the PCI and the

PC Card, as so the R5C841’s interface has the structure of 5V tolerant. VCC_RIN and

VCC_ROUT are powered at 1.8V when an internal regulator disabled, and VCC_RIN is powered

at 3.3V when an internal regulator enabled. The 1394 OHCI interface (AVCC_PHY3V) is powered

at 3.3V. The SD Card Interface, the Memory Stick interface and the xD Picture Card interface

(VCC_3V and VCC_MD3V) are powered at 3.3V.

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4.10 Reset Event

Data Sheet

Anytime GBRST# is asserted, all R5C841 internal state machines are reset and all registers are

set to their default values (provided that each signals has followed the reset sequence below).

PCIRST# is asserted, all registers are set to their default value except the following. The default

values of each register are described in each register description.

These registers are initialized only by GBRST#, not by PCIRST#. (PCI RESET Resistant register).

PCI-CardBus Bridge Config. Space:

· 40h

· 42h

· 80h

· 82h

· 84h

· 88h

· 8Ah

· 8Dh

· A0h

· A2h

· A4h

· B0h

· B4h

· B7h

· B8h

· C0h

· C2h

Subsystem Vendor ID

Subsystem ID

Bridge Configuration

PC Card Misc Control

16-bit Interface Control

16-bit I/O Timing 0

16-bit Memory Timing 0

Func. Disable Write Key

PC Card Misc Control 2

PC Card Misc Control 3

PC Card Misc Control 4

PC Card Misc Control 5

PC Card Misc Control 6

Function Disable

[15:0]

[31:0]

[23:0]

[7:0]

Serial ROM Control

Writable Subsystem Vendor ID

Writable Subsystem ID

[31:0]

[15:0]

1394 OHCI-LINK Config. Space:

· 2Ch

· 2Eh

· 3Eh

· ACh

· AEh

· 80h

· 9Ch

· 9Eh

· BEh

· 98h

· 99h

Subsystem Vendor ID

Subsystem ID

MIN Grant & MAX Latency

Writable Subsystem Vendor ID

Writable Subsystem ID

1394 Misc Control

1394 Misc Control 2

1394 Misc Control 3

Writable MIN_GNT & MAX_LAT

PHY Power Management

PHY Shadow

[15:0]

[7:0]

[15:0]

[7:0]

SD Card Interface Config Space:

· 2Ch

· 2Eh

· ACh

· AEh

· B0h

· BAh

· BCh

· E0h

· E2h

· E4h

· E8h

· ECh

· F8h

· FCh

Subsystem Vendor ID

Subsystem ID

[15:0]

[23:0]

[7:0]

[23:0]

[15:0]

[31:0]

[7:0]

Writable Subsystem Vendor ID

Writable Subsystem ID

SD Clock Control

PME Trigger Disable

SD Card Detect Control

SD Capabilities 0

SD Capabilities 1

SD Capabilities_RSV

SD Maximum Current Capabilities

SD Maximum Current Capabilities_RSV

SD Misc Control

Key

Memory Stick Interface Config Space:

· 2Ch

· 2Eh

· 40h

Subsystem Vendor ID

Subsystem ID

Memory Stick Clock Control

[15:0]

[23:0]

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Data Sheet

· 4Ah

· ACh

· AEh

· F8h

· FCh

PME Trigger Enable

Writable Subsystem Vendor ID

Writable Subsystem ID

MS Misc Control

[7:0]

[15:0]

[31:0]

[7:0]

Key

xD Picture Card Interface Config Space:

· 2Ch

· 2Eh

· 40h

· 4Ah

· ACh

· AEh

· F8h

· FCh

Subsystem Vendor ID

Subsystem ID

[15:0]

[23:0]

[7:0]

[15:0]

[31:0]

[7:0]

xD Picture Card Clock Control

PME Trigger Enable

Writable Subsystem Vendor ID

Writable Subsystem ID

xD Misc Control

Key

1394 OHCI Register:

· 24h

Global Unique ID High

Global Unique ID Low

[31:0]

· 28h

1394 PHY Register:

·All Registers

SD Card Register:

·All Registers

Memory Stick Register:

·All Registers

xD Picture Card Register:

·All Registers

2. These registers are not initialized by PCIRST# when the power state is D3 and PME Enable

bit is set to ”1”. (PME_Context register)

PC Card Socket Status Control Register Space:

· 000h

· 004h

· 008h

· 010h

· 802h

· 804h

· 805h

· 82Fh

Socket Event

Socket Mask

Socket Present State

Socket Control

Power Control

Card Status Change

Card Status Change interrupt Configuration

Misc Control 1

[3:0]

[11,10,5,4]

[6:4]

[7:2]

[3:0]

[0]

PC Card Bridge Config. Space:

· DEh

· E0h

Power Management Capabilities

Power Management Control/ Status

[15]

[15,8]

1394 OHCI-LINK Config. Space:

· DEh

Power Management Capabilities

[15]

· E0h

Power Management Control/ Status

[15,8]

SD Card Config. Space:

· 82h

· 84h

Power Management Capabilities

Power Management Control/ Status

[15]

[15,8]

Memory Stick Config. Space:

· 82h

· 84h

Power Management Capabilities

Power Management Control/ Status

[15]

[15,8]

xD Picture Card Config. Space:

· 82h

· 84h

Power Management Capabilities

Power Management Control/ Status

[15]

[15,8]

3. Excepting the above registers (PCI RESET Resistant register, PME_Context register) and

the global register, all the registers are initialized by the power state transition from D3 to D0

as long as the power state is D3.

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Data Sheet

≡Reset Sequence≡

Follow the sequence for initialization when a power is on.

1. Supply a power to VCC_3V, AVCC_PHY3V, VCC_MD3V, VCC_RIN and

VCC_ROUT*.

(*: in case of an internal regulator disabled )

2. Supply a power to VCC_PCI3V.

3. Deassert GBRST#.

4. Deassert HWSPND#.

5. Deassert PCIRST#. (PCLK has to be supplied for 100µsec@33MHz before

deasserting PCIRST#.)

Following Step3 by Step2 has no problem.

See the timing a detail of the timing shown in Chapter 5.3.6.

4.11 Power Management

The R5C841 implements two kinds of power management, software suspend mode and

hardware suspend mode, in order to reduce the power consumption on suspend, in addition to

the adoption of circuit to reduce the power consumption when power on. The software suspend

mode conforms to the ACPI (Advanced Configuration and Power Interface) specification and the

PCI Bus Power Management Standard. The R5C841, as a PCI device, implements four power

states of D0, D1, D2, and D3. Each power state on the PC Card is the following.

The power management events for the R5C841 and their sources are listed below. The PME#

source supports the Card Detect Change event only.

When the power state is except D0, the interrupt is disabled and only PME# can be asserted.

Event

Source

R5C841

card

Card Detect Change

Ready/Busy change

Battery Warning

card

Ring Indicate (Card Status Change)

1394 LINKON

SD Card Detect Change

Memory Stick Detect Change

xD Picture Card Detect Change

card

R5C841

4.11.1 Function on PC Card

The maximum powered state. All PCI transactions are acceptable.

Only the PCI Configuration Space access is allowed while the power and clock are provided.

CardBus CLK is output.

Only the PCI Configuration Space access is allowed while the power and clock are provided.

CardBus CLK is stopped by the protocol of CLKRUN.

D3hot

Only the PCI Configuration Space access is allowed while the power and clock are provided.

CardBus CLK is stopped compulsorily. If CardBus card is inserted, CardBus RESET# is

asserted at the same time this state is set. When the function is brought back to the D0 state,

the reset is automatically performed regardless of the assertion of PCIRST#. PCI interface is

disabled when reset. CardBus interface is reset by the assertion of CRST# on CardBus card.

PCI-CardBus Bridge defines D3cold state is to change from VCC_RIN, VCC_ROUT*, VCC_3V

and VCC_MD3V to the auxiliary power source. The R5C841 supports power management

events from D3cold with the auxiliary power source. The R5C841 can generate PME# even in

D3cold state without PCI clock if the event source is Card Detect Change or Ring Indicate.

*: in case of an internal regulator disabled

D3cold

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Data Sheet

On the software suspend mode, the interface signals on the PC Card keep to the following levels

when the card is inserted.

CardBus : CCLK=low, CPAR=low, CAD=high or low, CCBE#=high or low, CRST#=low,

CGNT#=high, Pull-up=high, Pull-down=low

16-bit : CDATA=hi-z, CADR=low

Other pins keep the level before the software suspend mode.

In addition to the Operating system-directed power management like ACPI, the R5C841 can

control to stop or slow the clock by supporting CLKRUN# and CCLKRUN# protocol. Therefore, it

is possible to reduce the power consumption. The state of the card interface signals is the same

as the software suspend mode. The hardware suspend mode is enabled when HWSPND# is

asserted. Once HWSPND# is asserted, all PCI bus interface signals are disabled and

VCC_PCI3V can be powered off. If PCIRST# is asserted, the internal registers of the R5C841

hold the data as long as VCC_RIN, VCC_ROUT*, VCC_3V and VCC_MD3V are on.

(*: in case of an internal regulator disabled)

4.11.2 Function on 1394 OHCI-LINK

Fully function of OHCI device state. Unmasked interrupts generate INTx#. And also,

PME# can be generated by PME_EN after setting PME_STS.

Ack_tardy is returned on accesses from the 1394. The PCI configuration space, the 1394

OHCI register and the GUID register are preserved. Functional interrupts are masked.

Unmasked interrupts can be generated by PME_EN after setting PME_STS. All transmit

contexts must be inactive before it attempts to place the R5C841 into the D1 power state.

IEEE1394 bus manager shall not be placed into D1. Placing the R5C841 into D1 enables

the ack_tardy generation. Software must ensure that IntEve.ack_tardy is 0b and should

unmask wake-up interrupt events such as IntEvent.phy and IntEvent.ack_tardy before

placing the R5C841 into D1.

LPS is deasserted and stopping supply of SCLK is requested to the PHY. The PCI

configuration space is retained and capable of access. The GUID register is retained, but

the1394 OHCI register is lost. Functional interrupts are masked. But when the LinkOn

signal that is occurred by accepting LinkOn packet or PHY.INTERRUPT is accepted from

the PHY, PME# is generated by PME_EN after setting PME_STS.

D3hot

LPS is deasserted and stopping SCLK supply is requested to the PHY. The PCI

configuration Space is capable of access, but all register except the PME context is lost.

The GUID register is retained, but the1394 OHCI register is lost. On transitioning back to

D0, the internal reset is automatically done even if PCIRST# is not asserted. Functional

interrupts are masked. But when the LinkOn signal is accepted from the PHY, PME# is

generated by PME_EN after setting PME_STS.

D3cold

D3cold indicates the state that VCC_RIN, VCC_ROUT*, VCC_3V, VCC_MD3V and

AVCC_PHY3V are changed to the auxiliary power on D3hot state. D3cold supports

functions like D3hot’s.

(*: in case of an internal regulator disabled)

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Data Sheet

PHY function

On D2 and D3 states, the PHY can be set to any one of the following low power consumption by

Software.

Doze Mode

All of Ports status is set to Disconnected, Disabled or Suspended.

less than 200ns less than 10ms

Sleep Mode

Select Condition

Resume Time

Doze Mode: Stopping clock of the PHY digital block and getting the Cable Interface’s power down

enables the low power consumption.

Sleep Mode: In addition to the low power consumption by Doze mode, getting power down of PLL

and the oscillator enables the lower power consumption than on Doze mode.

Setting D2PhyPM bit or D3PhyPM bit on the PHY Power Management register (the 1394

OHCI-LINK Configuration register addr.98h) enables a selection of Doze mode or Sleep mode.

On Doze mode or Sleep mode, LinkOn event enables to resume from the power saving mode

automatically and PME# is asserted. Each power saving modes cannot be set without the above

selected conditions, even if the R5C841 is set to D2 state or D3 state. If the above Ports

conditions are not satisfied, the R5C841 transacts as the Repeater PHY. In this time, setting

D2ForcePM bit or D3ForcePM bit to 1b enables to ignore above conditions and to set Doze mode

or Sleep mode automatically. But, it is disabled LinkOn event to resume from the power

consumption mode automatically and to assert PME#. Writing into Power State bits enables to

return to D0 state.

In addition, don’t the power supply of VCC_RIN, VCC_ROUT*, VCC_3V, VCC_MD3V and

AVCC_PHY3V on the suspend mode in spite of the Software and the Hardware.

(*: in case of an internal regulator disabled)

4.11.3 Function on SD Card / Memory Stick/xD Picture Card

The maximum powered state. All PCI/SD Card/Memory Stick/xD Picture Card transactions

are acceptable.

Only the PCI Configuration Space access is allowed while the power and clock are

provided. SDCCLK and MSCCLK are output.

Only the PCI Configuration Space access is allowed while the power and clock are

provided. SDCCLK and MSCCLK are output.

D3hot

Only the PCI Configuration Space access is allowed while the power and clock are

provided. SDCCLK and MSCCLK are stopped compulsorily. When the function is brought

back to the D0 state, the reset is automatically performed regardless of the assertion of

PCIRST#.

D3cold

PCI-CardBus Bridge defines D3cold state is to change from VCC_RIN, VCC_ROUT*,

VCC_3V and VCC_MD3V to the auxiliary power source. The R5C841 supports power

management events from D3cold with the auxiliary power source. The R5C841 can

generate PME# even in D3cold state without PCI clock if the event source is SD Card

Detect Change or Memory Stick Detect Change or xD Picture Card Detect Change.

(*: in case of an internal regulator disabled)

4.12 GPIO

UDIO1, 2, 3 and 4 pins work as GPIO (General Purpose I/O) pin when GPIO Enable bit of the PC

Card Misc Control 4 register (A4h bit31) is set to “1” on Serialized IRQ (default) mode or on

UDIO_Select mode of the PC Card Misc Control 4 register. When GPIO Enable bit is set to “0”,

GPIO outputs are Hi-Z and GPIO Inputs are disabled. User can change the characteristics of the

GPIO pins to either Input or Output by setting either I/O control bits on the GPIO register (83Ah)

or the General Purpose I/O 1 register of the Config register space (AAh). When GPIO Enable bit

is set to “1”, setting of GPIO is input mode (default). And it is possible to read the states of their

pins through each bit of the GPIO register. On Output mode, the written states of each bit are

output. If GPIO functions are not used on Serialized IRQ mode, no pull-up is required.

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4.13 ZV port Interface

Data Sheet

The R5C841 has the Bypass type ZV port interface. On the 16-bit interface, when ZV port Enable

bit of either the Misc Control 1 register (82Fh) or the PC Card Misc Control 2 register (A0h) is

enabled, CADR [25:6], IOIS16#, INPACK#, SPKR# are assigned to ZV port input signal as shown

in the below diagram.

The R5C841 has no on chip buffer for the ZV port interface. So if ZV port is enabled, the signals

for ZV port such as CADR [25:4] will be “Hi-Z” or “Input disable” and they will be reconfigured for

the ZV port interface. The R5C841 outputs the control signal for the external buffer, which is used

to switch sockets, so that the buffer control for switching sockets is enabled.

16 bit Interface

Signal Name

ZV Port Interface

Signal Name

ZV Port

Comments

card I/O ¹

Horizontal Sync to ZV Port

A10

A11

HREF

VSYNC

Vertical Sync to ZV Port

Video Data to ZV Port YUV:4:2:2 format

Audio SCLK PCM Signal

A13

A14

A16

A15

A12

UV2

UV4

UV6

SCLK

MCLK

RESERVED

Audio MCLK PCM Signal

RFU

Put in three state by Host Adapter

No connection in PC Card

A[5:4]

Used for accessing PC Card

A[3:0]

IOIS16#

A17

ADDRESS[3:0]

PCLK

Pixel Clock to ZV Port

Video Data to ZV Port YUV:4:2:2 format

Audio LRCLK PCM signal

A18

A19

A20

A21

UV0

A22

UV1

A23

UV3

A24

UV5

A25

UV7

INPACK#

SPKR#

LRCLK

SDATA

Audio PCM Data signal

ZV Port Interface Pin Assignments

1. "I" indicates signal is input to PC Card, "O" indicates signal is output from PC Card.

4.14 Subsystem ID, Subsystem Vendor ID

The R5C841 supports Subsystem ID and Subsystem Vendor ID to meet PC98/99/2001 Design

Requirements. There are three ways to write into the Subsystem ID and the Subsystem Vendor

ID registers from the system through BIOS.

1. Write Enable bit (Card: bit6 in the PC Card Misc Control, 1394: bit4 in the 1394 Misc

Control 2, SD: bit0 in the Key, Memory Stick: bit0 in the Key, xD Picture Card: bit0 in the

Key) control method.

The BIOS can turn this bit on, change the Subsystem IDs, and turn it off.

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Data Sheet

2. Copy of the Subsystem ID and the Subsystem Vendor ID in PCI user defined space

method.

Card:

C0h, C2h

1394/SD/MS/xD: ACh, AEh

3. Load the Subsystem IDs from the Serial ROM method.

Connecting SPKROUT to pull-down enables to use the Serial ROM. The R5C841 has

the Serial ROM interface, and load the Subsystem ID and the Subsystem Vendor ID

after PCI reset disabled.

These registers are initialized only by GBRST#.

4.15 Power Up/Down Sequence

Follow the sequence when the power sequence is ON/OFF.

∗ On the power sequence is ON.

1. Supply to VCC_ RIN and VCC_ROUT*.

2. Supply to VCC_3V, VCC_MD3V and AVCC_PHY3V.

3. Supply to VCC_PCI3V.

∗ On the power sequence is OFF.

1. Stop supplying to VCC_PCI3V.

2. Stop supplying to VCC_3V, VCC_MD3V and AVCC_PHY3V.

3. Stop supplying to VCC_RIN and VCC_ROUT*.

*: in case of an internal regulator disabled

On the power sequence is on, sustain to timing of Global Reset (Chapter 5.3.6) in regards to the

control of HWSPND# and GBRST#. GBRST# must be specially asserted on the power supply to

AVCC_PHY3V, because the only GBRST# enables to initialize the Cable interface block.The

rising of VCC_PCI3V should be within HWSPND# asserted time. When the power sequence is

off, the special limit for Delay Time is none.

The R5C841 can operate the PHY as Repeater. Follow the power sequence when the R5C841

operates PHY as Repeater without providing VCC_PCI3V.

∗ On the power sequence is ON.

1. Supply to VCC_ RIN and VCC_ROUT*.

2. Supply to VCC_3V, VCC_MD3V, and AVCC_PHY3V.

∗ On the power sequence is OFF.

1. Stop supplying to VCC_3V, VCC_MD3V, and AVCC_PHY3V.

2. Stop supplying to VCC_ RIN and VCC_ROUT*.

*: in case of an internal regulator disabled

In this case also, the special limit for delay time is none on the power sequence is off. Note the

following.

a. Asserting GBRST# enables to supply power to AVCC_PHY3V, because the only

GBRST# enables to initialize Cable interface. Also, sustain the delay time shown in

the chapter 5.3.6 on use of GBRST#.

b. HWSPND# is always set to ‘Low’.

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Data Sheet

4.16 1394 OHCI

The 1394 OHCI block in the R5C841 employs DMA engines for high-performance data transfer,

host bus interface and FIFO. The R5C841 supports two types of data transfer: asynchronous and

isochronous. Prefer to the 1394 OHCI release 1.1/1.0 specifications for settings and procedures

of the controller.

4.16.1 Asynchronous Functions

The R5C841 supports all of transmission and reception defined in 1394 packet formats.

Transmitted packets are read out of host memory and received packets are written into host

memory, both using DMA. And the R5C841 can be programmed as a bus bridge between the

host bus and the 1394 interface by the direct execution of the 1394 read/write requests to the

host bus memory space.

4.16.2 Isochronous Functions

The R5C841 includes the cycle master function as defined in the 1394 specification. The cycle

start packet is transferred at intervals of 8KHz cycle clock. This cycle master uses the internal

cycle clock. When the R5C841 is not the cycle master, the R5C841 can sustain its internal cycle

timer sychronized with the cycle master node by correcting its own cycle timer with the reload

value from the cycle start packet. The R5C841 supports each DMA controller for each

isochronous transmit and isochronous receive. Each DMA controller supports 4 different DMA

contexts.

4.16.3 DMA

The R5C841 supports seven types of DMA. Each type of DMA has register space and data

stream referred to as a DMA context.

DMA Type

Number of Contexts

Asynchronous Transmit

Asynchronous Receive

Isochronous Transmit

Isochronous Receive

Self-ID Receive

Request x 1, Response x 1

X 4

X 1

Physical Request & Physical Response

No Context

Each asynchronous and isochronous context is composed of buffer descriptor lists called a DMA

context program, which is stored in main memory. The DMA controller finds the necessary data

buffers through the DMA context programs.

The Self-ID receive controller is controlled not by the DMA context program but by the two other

registers. The R5C841 supports the Physical Request DMA and the Physical Response DMA

controllers in order to transmit the receive request, which is to read and write directly to the bus

memory space. These controllers are also controlled not by the DMA context program but by the

other reserved register.

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Data Sheet

4.16.4 LINK

The Link module sends packets which appear at the transmit FIFO interfaces to the PHY, and

places correctly addressed packets into the receive FIFO. The features are as follows.

⋅

Transmits and receives correctly formatted 1394 serial bus packets.

Generates the appropriate acknowledge for all received asynchronous packets.

Performs the cycle master function.

Generates and checks 32-bit CRC.

Detects missing cycle start packets.

Interfaces to PHY.

Receives isochronous packets at all times (Supports of asynchronous streams and cycle start

packets including a CRC error).

⋅

Ignores asynchronous packets received during the isochronous phase.

4.17 SD Card Interface

The R5C841 has one port of SD Card interface, consists of four serial data lines, one serial

command line, card detection, write protection and SD clock.

4.17.1 Protocol

After the SD Card interface block in the R5C841 is initialized, the R5C841 outputs the data

through the serial SDCMD signal by the host’s command (Writing into the SD_CMD register), and

the SD Card’s response to the command is inputted to the SDCMD signal. The contents of this

card’s response are stored into bits [7:0] of the SD_RSP register. The SD Card is initialized after

the SD Card interface block checked CRC, etc. After that, the data is transmitted between the

R5C841 and the SD Card through the data lines. When the data is written into the SD memory

card, the host writes the divided data (default 512byte) into the SD buffer of SD interface block,

and the R5C841 transmits the serialized data from the SDDAT [3:0] of SD Interface block.

Conversely, when the data is read from the SD memory card, the SD Card writes the divided data

(default 512byte) into the SDDAT [3:0] of SD interface block after initialization of the SD Card by

the command response signal.

4.18 Memory Stick Interface

The R5C841 has one port of Memory Stick interface, consists of four serial data lines, one bus

state line, card detection and MS clock.

4.18.1 Protocol

The Memory Stick interface block accesses to the Memory Stick registers and the Page Buffer by

the Transfer Protocol Command (TPC) in compliance with the host. The R5C841 checks

transmission of data between the Page Buffer in the Memory Stick and the Flash Memory and a

status after accepting INT signal of the Memory Stick. After that, the R5C841 starts to read / write

/ erase the data.

4.19 xD Picture Card Interface

The R5C841 has one port of xD Picture Card interface, consists of eight serial data lines, seven

control signals and card detection.

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Data Sheet

4.19.1 Protocol

The R5C841 accesses to the xD Picture Card through the 32-bit Data port register. Writing to the

Data port register can transfer address, command and data to the xD Picture Card. The data

transfer to the xD Picture Card enables in units of 8-bit, 16-bit or 32-bit. On the 16-bit or 32-bit

access, the R5C841 can access to the xD Picture Card by increments of 8-bit unit automatically.

Note that only lower 1byte works when write of address and command data.

4.20 Serial ROM Interface

The R5C841 can load data for Subsystem ID, Subsystem Vendor ID (the PCI Interface) and

some PCI configuration registers default value from the Serial ROM (I²C BUS). After that, the

R5C841 can set them to each register automatically.

•

I²C BUS is registered trademark of PHILIPS ELECTRONICS N.V.

Purchase of Ricoh’s I²C components conveys a license under the Philips I²C patent to use the

components of the I²C system, provided the system conforms to the I²C specifications defined by

Philips.

4.20.1 Outline

The R5C841 supports 100k mode and 7-bit address, and automatically stores the data (See.

Chapter 4.20.3) from the Serial ROM when the first PCI Reset is deasserted after deassertion of

the GBRST#.

4.20.2 User’s Setting

Connecting the SPKROUT pin to a pull-down resistor of 100kΩ enables the use of the Serial

ROM. When the first PCI Reset is deasserted, the R5C841 starts to sample SPKROUT pin.

When SPKROUT pin is connected to a pull-down resistor of 100kΩ, the R5C841 attempts to load

data through the Serial ROM. In this case, UDIO3 is reassigned to SCL (the clock signal) and

UDIO4 is reassigned to SDA (the data signal). The SDA and the SCL must be connected to

VCC_3V through pull-up resistors of 10kΩ. When the SPKROUT pin is connected to VCC_3V

through a pull-up resistor of 100kΩ, the R5C841 does not load data through the Serial ROM. See

the PC Card Misc Control 4 register for setting of UDIO3 and UDIO4.

Without the Serial ROM

With the Serial ROM

100kΩ

10kΩ

R5C841

VCC_3V

SPKROUT

UDIO4

UDIO3

UDIO4

UDIO3

UDIO4

UDIO3

SDA

SCL

100kΩ

Serial ROM

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Data Sheet

4.20.3 Format

The R5C841 starts accesses to the Serial ROM by detecting a pull-down of the SPKROUT when

the first PCI Reset is deasserted after deassertion of the GBRST#. The accessed data is stored

to each register as follows. The retry states don’t allow PCI’s slave access during accesses to the

Serial ROM. Each parts register of 1394 OHCI-LINK Configuration Space, 1394 OHCI Registers

Space, PCI-CardBus Bridge Configuration Space, SD Card Configuration Space, Memory Stick

Configuration Space and xD Picture Card Configuration Space.

4.20.3.1 1394OHCI-LINK Configuration Space

Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Subsystem Vendor ID[7:0]

Subsystem Vendor ID[15:8]

Subsystem ID[7:0]

Subsystem ID[15:8]

LEDRX[0]

LEDTX[1]

OHCI10

LEDTX[0]

LEDRX[1]

―

D2PhyPM[1:0]

CMC

Shadow

D2ForcePM

D3PhyPM[1:0]

D3ForcePM

P1Dis

Shadow

CPSDis

CPSFixVal

P0Dis

Shadow

1Dh

PrwCShadow[2:0]

1Eh

1Fh

―

PMbit15

WrEn

20h

SIDWREN

INTXSel[1:0]

21h

22h

―

1394LED

toLED1#

1394LED

toLED0#

LEDDurationSel[1:0]

23h

24h

25h

Max Latency[3:0]

Min Grant[3:0]

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4.20.3.2 1394 OHCI Register

Data Sheet

Address

26h

Bit7

Bit6

aPhy

EnhanceEn

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

ProgPhyEn

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

MiniROM Address[7:0]

Config ROM Header[7:0]

Config ROM Header[15:8]

Config ROM Header[23:16]

Config ROM Header[31:24]

Bus Option[7:0]

Bus Option[15:8]

Bus Option[23:16]

Bus Option[31:24]

Global Unique ID High[7:0]

Global Unique ID High[15:8]

Global Unique ID High[23:16]

Global Unique ID High[31:24]

Global Unique ID Low[7:0]

Global Unique ID Low[15:8]

Global Unique ID Low[23:16]

Global Unique ID Low[31:24]

4.20.3.3 PCI-CardBus Bridge Configuration Space

Address

38h

39h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Subsystem Vendor ID[7:0]

Subsystem Vendor ID[15:8]

Subsystem ID[7:0]

3Ah

3Bh

Subsystem ID[15:8]

3Ch

16bitMemEnh

Tim

SR_PCIINTDis

16bitIOEnh LegacyIdxSel PrefetchEn

Tim

I/O1AdrMode I/O0AdrMode

3Dh

3Eh

3Fh

SIRQEn

LEDPol

5VDis

VPPENPol

VCCxENPol

―

XDCardDis ExpressCard

Dis

MemoryStick

SDCardDis

1394Dis

Internal_bay

Dis

40h

41h

42h

CSCtoINT

Dis

WPPUPDis External_bay

CINT-ISAEn CCLKRUNPU

Dis

StopClock

LED

toLED1#

CSTSCHGIn

IOMinTim

WaitSel

Dis

MemMinTim

5VReadEn

DecodeDis

SPKROUT

DelatedClr

CBCLKRUN

HiZEn

Dis

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

LEDDurationSel[1:0]

UDIO1[3:0]

UDIO3[3:0]

UDIO5[3:0]

UDIO0[3:0]

UDIO2[3:0]

UDIO4[3:0]

GPIOEn

―

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4.20.3.4 Memory Stick Configuration Space

Data Sheet

Address

50h

51h

Bit7

Counter cut

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Card Detect Mode[1:0]

CLK selection[1:0]

PMETrgIn

(Card

52h

PMETrgRM

(Card

Inserted by

MSCD#)

Removed by

MSCD#)

53h

54h

55h

56h

57h

58h

―

Subsystem Vendor ID[7:0]

Subsystem Vendor ID[15:8]

Subsystem ID[7:0]

Subsystem ID[15:8]

MSLED

toLED1#

MSLED

toLED0#

59h

5Ah

5Bh

Write Enable 0xFD

CLKRUNDis, MSPWRPol

LEDDurationSel[1:0]

INTSEL[1:0]

4.20.3.5 SD Card Configuration Space

Address

5Ch

5Dh

5Eh

5Fh

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

LED Control[2:0]

Class Code[7:0](specific register-level programming interface)

Class Code[15:8](sub-class code)

Class Code[23:16](base class code)

Subsystem Vendor ID[7:0]

60h

61h

Subsystem Vendor ID[15:8]

62h

Subsystem ID[7:0]

63h

Subsystem ID[15:8]

64h

65h

Timeout Clock Select{1:0}

CLKSelection[1:0]

PMETrgDis PMETrgDis

(Card (Card

Removed by Inserted by

PMETrgDis

(Card

Interrupt by

SDCDAT1)

SDCD#)

66h

67h

68h

Card Detect Counter[3:0]

Card Detect Mode[1:0]

Counter cut

SDLED

toLED1#

SDLED

toLED0#

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

71h

72h

73h

Write Enable 0xFC

SDWPPol

CLKRUNDis, SDPWRPol

INTSEL[1:0]

LEDDurationSel[1:0]

Capability0[7:0]

Capability0[15:8]

Capability1[7:0]

Capability1[15:8]

Maximum Current for 3.3V

Maximum Current for 3.0V

Maximum Current for 1.8V

―

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

4.20.3.6 xD Picture Card Configuration Space

Data Sheet

Address

74h

75h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Subsystem Vendor ID[7:0]

Subsystem Vendor ID[15:8]

Subsystem ID[7:0]

76h

77h

Subsystem ID[15:8]

78h

XDLED

toLED1#

XDLED

toLED0#

79h

7Ah

7Bh

7Ch

7Dh

7Eh

Write Enable 0xFD

CLKRUNDis, XDPWRPol

LEDDurationSel[1:0]

INTSEL[1:0]

Counter cut

Card Detect Mode[1:0]

CLK selection

PMETrgIn

(Card

PMETrgRM

(Card

Inserted by

XDCD#)

Removed by

XDCD#)

4.21 LED# Output

The R5C841 can output the activity signals of the PC card, the 1394OHCI, the SD Card, the

Memory Stick and the xD PictureCard, as LED0#, LED1# and LED2#. The R5C841 uses UDIOx

pins as LED0#/1#/2#. See the PC Card Misc Control 4 (Config. (Func.0) A4h) register for use

these pins. The default of the LED signal is ‘Low’ active. But, setting the LED Polarity bit (Config,

(Func.0) 82h bit11) to “1b” enables to set the LED signal to ‘high’ active. This bit is common to the

PC card, the 1394 OHCI, the SD Card, the Memory Stick and the xD Picture Card.

The LED signal is asserted at the same time the trigger of its signal is asserted. And the internal

counter works after the trigger is deasserted. In default, the LED signal is kept for 64msec after

the deassertion of the trigger, and is deasserted. When the trigger is reasserted in operation of

the counter, the counter is cleared and restarted to count up at the same time the deassertion of

the LED signal. See the below chart.

Counter Reset

The LED trigger

Count up

Counter Start

Counter Restart

The LED output

LED Output Duration

Not Count up

The LED Output Duration is selected from among 64msec(default), 1msec and No Duration time

(through the trigger). The card and the 1394 have the different registers for selecting each other

(See the following). The trigger signals for them also are different.

The R5C841 uses a counter operating PCLK for the LED Output Duration and therefore a stop

request of PCLK by the CLKRUN protocol is refused in operation of the counter. When PCLK

must be stopped for 64msec on system, modify the LED Output Duration.

LED0#: PC_Card LED# + 1394 LED# + SD_Card LED# + Memory Stick LED# + xD LED#

LED1#: PC_Card LED# + 1394 LED# + SD_Card LED# + Memory Stick LED# + xD LED#

LED2#: 1394 LED#

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

4.21.1 PC Card LED (CardBus R2)

The trigger signals of the PC Card LED are as follows.

CardBus:

R2:

CFRAM#, CINT#

Card command by IORD#, IOWR#, OE#, WE#, IREQ#

Bit 13 and bit 12 of the Config (Func.0) A2h register can set the counter’s duration.

bit 13 12

the LED Output Duration

64 msec (default)

1 msec

No Duration Time (through)

Test Mode(3.8µsec)

4.21.2 1394 LED

The 1394 LED signal indicates the condition of the IEEE1394 interface block in the R5C841. This

signal is asserted when the R5C841 is on transmission/reception.

Bit 2 and bit 1 of the Config (Func.1) 9Eh register can set the counter’s duration.

bit 2 1

0 0

the LED Output Duration

64 msec (default)

1 1

1 msec

1 0

0 1

No Duration Time (through)

Test Mode(3.8µsec)

4.21.3 SD LED

The SD LED signal indicates conditions of the SD Card interface in the R5C841. This signal is

asserted when the R5C841 is on the transmission, the reception and the debounce duration of

the card detection. Bit 29 and bit 28 of the Config (SD: Func.2) F8h register can set the counter’s

duration.

bit 29 28

the LED Output Duration

64 msec (default)

1 msec

No Duration Time (through)

Test Mode (3.8µsec)

4.21.4 MS LED/xD LED

The MS LED and the xD LED signals indicate conditions of the Memory Stick interface and the

xD Picture Card interface in the R5C841. This signal is asserted when the R5C841 is on the

transmission and the reception. Bit 29 and bit 28 of the Config (MS: Func.3, xD: Func.4) F8h

bit 29 28

the LED Output Duration

64 msec (default)

1 msec

No Duration Time (through)

Test Mode (3.8µsec)

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4.21.5 LED Output Selection

Data Sheet

All LED can be output to LED0#/LED1#. The LED for the 1394 is output by setting Config

(Func.1) 9Eh bit [4:3] to “11b”, the LED for the SD Card is output by setting Config (Func.2) F8h

bit [7:6] to “11b”, the LED for the Memory Stick is output by setting Config (Func.3) F8h bit [7:6]

to ”11b”, and the LED for the xD Picture Card is output by setting Config (Func.4) F8h bit [7:6]

to ”11b”.

Also, the LED for the IEEE1394 is output to LED2# by setting Config (Func.0) B0h bit6 to “0b”.

4.22 1394 Cable Interface

The R5C841 builds in 2 ports of 1394 Cable interface that support the transmission speed of

400/200/100Mbps compliant with the IEEE1394a-2000 standard.

4.22.1 Cable Interface Circuit

AVCC_PHY3V

Boad A

ICD

R5C841

Cable

Boad B

Connect Detect

TpBias Disable

Connect_Detect

TpBias_Disable

TPBIAS*

0.33uF

TPAP*

TPAP

TPAN

TPAP

TPAN

Driver

Strb_Tx

Strb_TX

Strb_Enable

Receipt Signals

Data_Rx

TPAN*

Receipt Signals

Data_Rx

56ohm ±3%

Arb_A_Rx etc

TPBP*

Driver

Data_Tx

TPBP

TPBN

Data_Tx

Data_Enable

Receipt Signals

Strb_Rx

TPBN*

270pF

TPBN

Receipt Signals

Strb_Rx

56ohm ±3%

Arb_B_Rx etc

Arv_B_Rx etc

5.1kohm ±5%

AGND

System A

System B

* means a port number in this figure.

(Example: TPBIAS*→TPBIAS0 or TPBIAS1)

Each port consists of two twist-pairs; TPA and TPB. The TPA and the TPB are used in order to

monitor transmission/reception of a control signal (Arbitration signal) and data, and the state of a

cable line (the insert of a cable).

It is necessary for the TPA and the TPB to be connected to a termination of 55Ω resistances

according to the cable impedance. This termination resistance should be arranged near the

R5C841. On TPA side, TPBIAS should be placed to the center node of the termination resistance

in order to set up a cable’s common-mode DC potential. A capacitor of 0.33µF for decoupling

should be connected to the TPBIAS. On TPB side, a termination of 5.1kΩ and a capacitor of

270pF should be connected to between the center node of the termination resistance and AGND.

See the application manual for the substrate layout.

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

4.22.2 Transaction of Unused Ports

Data Sheet

On no use of ports, TPBP* and TPBN* are directly connected to AGND, and TPAP*, TPAN* and

TPBIAS* are OPEN. After that, set Port Disable bit of the 1394 PHY Register. The PHY Shadow

Read/Write of the 1394PHY register (Ch. 4.22.4).

4.22.3 CPS (Cable Power State)

The R5C841 builds in a function monitoring the state of the cable power. The CPS pin is

connected to the cable power through the external resistor (390kΩ±1%) and detects a condition

that cable power has lowered under the threshold level (Normally 7.5V). When the four pins cable

is used (when the CPS function is not used), it is possible to select two methods: one is the direct

connection of the CPS pin with the AVCC_PHY3V, and the other is with the register’s control of

the CPS pin which is set to ‘Open’. In case of the register’s control, set CPSDis (bit1) and

CPSFixVal (bit0) on the PHY Power Management Register (98h) in the 1394 Configuration

(Chapter 4.20) for details.

On monitoring the state of Cable Power.

Cable power supply

R5C841

390kohm(±1%)

6pin connector

4pin connector

CPS

Out of monitoring the state of Cable Power.

R5C841 AVCC_PHY3V

CPS

4.22.4 Read/Write of 1394 PHY Registers

The R5C841 builds in the 1394 PHY registers compliant with IEEE 1394-1995 and

IEEE1394a-2000 standard. Refer to the 1394PHY Registers for details. Access to these registers

is enabled by the PHY Control register of the 1394 OHCI Registers, and offsetting [31-11] bits of

the 1394 OHCI Register Base Address (10h) in the 1394 Configuration register space enables

access to the PHY Control register (0ECh).

The data of 1394 PHY register is the little endian description. On access of the PHY Control

only in a row without the bit number of data.

PHY Register

PHY Control

rdData

23 22 21 20 19 18 17 16

wrData

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

For example, when 53h is written in wrData of the PHY Control register (bit 6, 4, 1, and 0 are set

to “1”), 53h is written in the PHY Register as they are (bit 1, 3, 6, and 7 are set to “1”). Access to

Contender bit, Power_class field, and Disable bit for Port0/Port1 in the 1394 PHY register is

enabled through the PHY Shadow register (99h) in the 1394 configuration register space. Refer

to the PHY Shadow register in the Registers Description for details.

4.22.5 Clock Circuit

The PHY block of the R5C841 requires 24.576MHz of clock frequency.

Crystal OSC.

R5C841

External Clock Driver

R5C841

10pF

OPEN

(±5%)

Recommended Conditions

Crystal Oscillator

Normal Frequency

: 24.576MHz

Frequency Tolerance

Temperature stability

: ±50ppm(at 25°C)

: ±50ppm(reference to 25°C)

Operating Temperature Range : -20~70°C

Load Capacitance

Driver Level

: 10pF

: 0.1mW

Equivalent Series Resistance

Insulation resistance

Shunt Capacitance

: 50ohm Max

: 500M ohm Min (at DC100V±15V)

: 7.0pF Max

External Clock Driver

Normal Frequency

Frequency Tolerance

: 24.576MHz

: ±50ppm(at 25°C)

4.22.6 PLL

The PHY block of the R5C841 produces 393.216MHz of the internal clock that is 16 times as

long as the 24.576MHz produced by the internal PLL circuit. Setting the Sleep Mode of the PHY

block can stop the PLL circuit. Refer to the Power Management (Ch. 4.11) for settings of the

Sleep Mode.

PLL External Circuit

R5C841

FIL0

0.01uF

AGND

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4.22.7 Reference Voltage Circuit and Reference Current Circuit

Data Sheet

The PHY block of R5C841 supports terminals of the external parts for the Reference voltage

circuit and the Reference current circuit. Each terminal should be connected to indicated

capacitors and resistors.

Reference Voltage Circuit

Reference Current Circuit

R5C841

VREF

R5C841

REXT

0.01uF

AGND

10kohm

±1%

AGND

4.23 Function’s Selection

The R5C841 can make each function disable by UDIO3, UDIO4 and VPPEN0. Setting UDIO3 to

pull-down disables the SD Card interface, setting UDIO4 to pull-down disables the Memory Stick

interface, and setting VPPEN0 to pull-down disables the xD Picture Card interface. Disabled

function cannot detect the corresponding configuration register. (Master Aborts) The function’s

selection is as follows.

On use of the Serial ROM, set the Serial ROM in order to disable each function, because UDIO3,

UIDO4 and VPPEN0 are set to only pull-up.

Function No.

VPPEN0

UDIO3

Pull-up

UDIO4

Pull-up

Pull-up Enable Enable Enable PCCard

Pull-up Disable Enable Enable PCCard

1394

–

Pull-down Pull-up

Pull-up Pull-down Pull-up Enable Disable Enable PCCard

Pull-down Pull-down Pull-up Disable Disable Enable PCCard

–

Pull-up

Pull-up Pull-down Enable Enable Disable PCCard

–

Pull-down Pull-up Pull-down Disable Enable Disable PCCard

Pull-up Pull-down Pull-down Enable Disable Disable PCCard

Pull-down Pull-down Pull-down Disable Disable Disable PCCard

–

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

4.24 Internal Regulator

Data Sheet

The R5C841 has an internal regulator, which converts the single 3.3V power into the power for

the internal core logic. REGEN# signal enables/disables an internal regulator. The following is the

recommended circuit diagram.

Regulator Disable Mode

from Regulator

0.01uF 0.1uF 0.01uF

10uF

(1.8V)

VCC_RIN

R5C841

0.01uF 0.01uF 0.47uF 0.47uF

VCC_ROUT

REGEN#

short

0 ohm

open

Regulator Enable Mode

from Regulator

(3.3V)

0.01uF 0.1uF 0.01uF

10uF

VCC_RIN

VCC_ROUT

REGEN#

R5C841

0.01uF 0.01uF 0.47uF 0.47uF

open

100k ohm

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

4.25 ExpressCard Interface

Data Sheet

Using the external USB host interface enables the R5C841 to connect a USB device to a PC Card

socket. That is, inserting an ExpressCard passive adapter into the PC Card socket can support an

ExpressCard for the USB interface.

R5C841

ExpressCard

Passive Adapter

USBD+

USB

HOST

USBDP

USBDM

IORD#

IOWR#

A22

USBD-

CPUSB#

+3V

ExpressCard

VCC3EN#

Power

S/W

4.26 BAY Function

With the PC Card passive adapter, the Small Card (the SD Card, the Memory Stick, the xD Picture

Card), can be inserted in the PC Card slot. To enable this function, set “1” in PCI-CardBus Bridge

Configuration register B7 [0]. (Internal Bay Mode)

Set PCI-CardBus Bridge Configuration register A0 [14] to “1” in order to use the External BAY

function. (*External Bay Mode)

You can also set these registers by using Serial ROM.

*To use the External Bay Mode, you also need to wire the 6 pins of Pin Name 1 to the 6 pins

of Pin Name 2 respectively.

Pin Name 1

CE2#

WE#

CADR0

CADR1

CADR2

CADR3

Pin Name 2

MDIO08

MDIO09

MDIO10

MDIO11

MDIO12

MDIO13

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

5 ELECTRICAL CHARACTERISTICS

5.1 Absolute Maximum Rating

Symbol

Parameter

Range

Unit

Condition

Note

Vcc 1

Vcc 2

Vte1

Vte2

Topr

Tstg

Supply Voltage Range 1

Supply Voltage Range 2

Voltage on Any Pin

-0.3 ~ 2.5

-0.3 ~ 4.6

-0.3 ~ 5.8

-0.3 ~ 4.6

-40 ~ 85

-55 ~ 125

±2.0

GND=0V

Voltage on Any Pin

Ambient Temperature under bias

Storage Temperature Range

Human Body Model

ºC

C=100pF

R=1.5kΩ

ESD1

ESD2

Charged Device Model

Latch-up

±1.0

LATUP

5ms

±100

Note 1: Applied for VCC_ROUT.

Note 2: Applied for VCC_RIN, VCC_3V, VCC_PCI3V and VCC_MD3V and AVCC_PHY3V.

Note 3: The clamping voltage of the trigger pulse power source should be below a value of Vte.

Note 4: Applied for all of Digital pins

Note: Stresses above those listed may cause permanent damage to system components. These are stress

ratings only. Functional operation at these or any conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect system reliability.

5.2 DC Characteristics

5.2.1 Recommended Operating Conditions for Power Supply

Power Pin

Parameter

Min

Typ

Max

Unit

Note

VCC_PCI3V

VCC_RIN

Supply Voltage for PCI interface

(3.3V Operation)

3.0

3.3

3.6

Supply Voltage for Regulator

3.0

3.3

1.8

3.6

VCC_RIN,

Supply Voltage for Core Logic

1.65

1.95

VCC_ROUT

(Disabled regulator: 1.8V Operation)

VCC_3V

Supply Voltage for System and

Card Interface Signals

3.0

3.3

3.6

VCC_MD3V

AVCC_PHY3V

Supply Voltage for Media interface

block

Supply Voltage for Cable interface

block

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5.2.2 PCI Interface

Data Sheet

For 3.3V signaling

(VCC_ROUT= 1.65~1.95V, VCC_PCI3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit Test Condition

Note

VIH

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Input Leakage Current

0.5xVCC_PCI3V

-0.5

5.75

VIL

0.3xVCC_PCI3V

VOH

VOL

IILk

0.9xVCC_PCI3V

Iout=-500µA

0.1xVCC_PCI3V

Iout=1500µA

Vin=0~

VCC_PCI3V

±10

µA

Cin

Input Pin Capacitance

Cclk

PCICLK Pin Capacitance

Note 1: Applied for PCICLK, CLKRUN#, PCIRST#, AD[31:0], C/BE#[3:0], PAR, FRAME#,

IRDY#, TRDY#,STOP#, DEVSEL#, IDSEL, PERR#, SERR#, REQ#, GNT#,

INTA#, INTB#, INTC# pins

5.2.3 16-bit PC Card Interface

For 3.3V signaling

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Typ

Max

Unit

Test Condition

Note

VIH

Input High Voltage

Input Low Voltage

2.0

-0.3

2.4

5.5

0.6

2,4

VIL

VOH1

VOH2

VOL1

VOL2

IILk

Output High Voltage

Output Low Voltage

Input Leakage Current

Iout=-4mA

Iout=-2mA

Iout=4mA

Iout=2mA

Vin=0~VCC_3V

Vin=0

0.4

±10

µA

IIL1

Input Leakage Current

(Pull-up)

-50

Cin

Input Pin Capacitance

2,4

Note 2: Applied for CADR [25:0], CDATA [15:0], CE [2:1]#, IOR#, IOW#, OE#, WE#, REG#, WAIT#,

if Card interface is configured as a 16-bit Card Socket.

Note 3: Applied for RESET pin

Note 4: Applied for RDY/IREQ#, WAIT#, BVD1/STSCHG#/RI#, BVD2/SPKR#, INPACK#, WP/IOIS16#

pins

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

5.2.4 CardBus PC Card Interface

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Typ

Max

Unit

Test Condition

Note

VIH

VIL

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Input Leakage Current

0.475xVCC_3V

-0.5

VCC_3V +0.5

5,6,7

5,6,8

0.325xVCC_3V

VOH

VOL

IILk

IIL1

0.9xVCC_3V

Iout=-150µA

Iout=700µA

Vin=0~VCC_3V

Vin=0

0.1xVCC_3V

±10

µA

Input Leakage Current

(Pull-up)

-230

µA

Cin

Input Pin Capacitance

5,6,7

IIL2

Input Leakage Current

(Pull-down)

16.5

-70

Vin=VCC_3V

Vin=0

µA

IIL3

Input Leakage Current

(Pull-up)

µA

Note 5: Applied for

Note 6: Applied for

CCLK, CCLKRUN#, CRST#, CAD [31:0], CC/BE#[3:0], CPAR, CFRAME#, CGNT#,

CINT# pins, if Card interface is configured as a CardBus Card Socket.

CIRDY#, CTRDY#,CSTOP#, CDEVSEL#, CPERR#, CSERR#, CREQ#, CINT#,

CAUDIO pins

Note 7: Applied for CSTSCHG pin

Note 8: Applied for CCLKRUN# pin

5.2.5 PC Card Interface Card Detect Pins and System Interface Pins

PC Card Interface Card Detect Pins and System Interface Pins

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Typ

Max

Unit

Test Condition

Note

VIH1

VIL1

VIH2

VIL2

VIH3

VIL3

VOH1

VOH2

VOL1

VOL2

IILk

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Input Leakage Current

0.8xVCC_3V

VCC_3V+0.3

0.3xVCC_3V

VCC_3V+0.3

0.8

-0.3

2.4

11,12

-0.3

2.4

5.75

-0.3

2.4

0.8

Iout=-4mA

Iout=-1mA

Iout=4mA

Iout=1mA

Vin=0~VCC_3V

Vin=0

2.4

0.4

±10

µA

IIL1

Input Leakage Current

(Pull-up)

-80

IOZ

Hi-Z Output Leakage Current

Vout=0~VCC_3V

±10

µA

Note 9: Applied for CD1#(CCD1#), CD2#(CCD2#), MDIO00, MDIO01, MDIO03 pins

Note 10: Applied for RI_OUT#, SPKROUT,VCC5EN#, VCC3EN#, VPPEN0, VPPEN1, MDIO04,

MDIO05, MDIO06 pins

Note 11: Applied for VS1#(CVS1#), VS2#(CVS2#) pins

Note 12: Applied for GBRST#, HWSPND#, MDIO07 pins

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

5.2.6 Cable Interface

(VCC_ROUT= 1.65~1.95V, AVCC_PHY3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Test Condition

Note

VID

Differential Input Voltage

118

260

Cable input, during data

reception

13,14

168

1.165

0.935

0.523

172

265

2.515

265

Cable input, during arbitration

100Mbps speed signaling off

200Mbps speed signaling

400Mbps speed signaling

Cable output, load 56Ω

VICM

TpB Common Mode Input

Voltage

VOD

ICM

Differential Output Voltage

13,14

TpA, TpB Common Mode

Output Current

-0.81

0.44

Driver enable, speed signal off

ISPD2

ISPD4

TpB200Mbps Speed Signal

TpB400Mbps Speed Signal

-4.81

-2.53

-8.10

7.5

-12.40

VTCPWD CPS Threshold Voltage

VTPBIAS TpBias Output Voltage

CPS, R=390kΩ

1.665

2.015

Note 13: Applied for TPAP0/1, TPAN0/1 pins

Note 14: Applied for TPBP0/1, TPBN0/1 pins

Note 15: Applied for TPBIAS0/1 pins

Note 16: Applied for CPS pin

5.2.7 UDIO0-5 pins

For PCI 3.3V signaling

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Test Condition

Note

VOH

Output High Voltage

Output Low Voltage

Hi-Z Output Leakage Current

Input High Voltage

2.4

Iout=-4mA

VOL

IOZ

VIH

VIL

0.4

±10

Iout=4mA

Vout=0~VCC_3V

µA

0.5xVCC_3V

-0.5

5.75

Input Low Voltage

0.3xVCC_3V

±10

IILK

Input Leakage Current

Vin=0~VCC_3V

µA

Note 17: Applied for UDIO0-5 pins

Note 18: Applied for UDIO0-4 pins

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

5.2.8 SD Card Interface

(VCC_ROUT= 1.65~1.95V, VCC_MD3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Typ

Max

Unit

Test Condition

Note

VIH

VIL

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

0.625x

VCC_MD3V

+0.3

-0.3

0.25x

VCC_MD3V

VOH

0.75x

VCC_MD3V

19,20

Iout=-100µA@3V

VOL

IIL

0.125xVCC_MD3V

±10

19,20

Iout=100µA@3V

Input Leakage

Current (Pull-up)

Vin=0

µA

IOZ

HI-Z Output Leakage

Current

Vout=0~

VCC_MD3V

µA

Note 19: Applied for

Note 20: Applied for

SDCDAT [3:0], SDCCMD pins

SDCCLK pin

5.2.9 Memory Stick Interface

(VCC_ROUT= 1.65~1.95V, VCC_MD3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Typ

Max

Unit

Test Condition

Note

VIH

Input High Voltage

0.8x

VCC_MD3V

VIL

Input Low Voltage

0.2xVCC_MD3V

VOH

Output High Voltage

VCC_MD3V

-0.3

Iout=-8mA

Iout=8mA

VOL

IOZ

Output Low Voltage

0.4

HI-Z Output Leakage

Current

±10

µA

Note 21: Applied for

MSCDAT [3:0], MSCCLK, MSBS pins

5.2.10 xD Picture Card Interface

(VCC_ROUT= 1.65~1.95V, VCC_MD3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Typ

Max

Unit

Test Condition

Note

VIH

VIL

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

2.1

-0.3

2.6

VCC_MD3V+0.3

0.7

VOH

VOL

IOZ

Iout=-8mA

Iout=8mA

22,23

0.4

HI-Z Output Leakage

Current

±10

µA

Note 22: Applied for XDDAT [7:0] pins

Note 23: Applied for XDRE#, XDWE#, XDCE#, XDALE, XDCLE, XDWP# pins

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

5.2.11 Serial ROM Interface

Data Sheet

For 3.3V signaling

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Test Condition

Note

VIL

Input Low Voltage

-0.5

0.3xVCC_3V

VCC_3V+0.5

0.4

VIH

VOL1

Tof

Input High Voltage

Output Low Voltage

0.7xVCC_3V

Iout=3mA

Output fall time from V IHmin to V

ILmax with a bus capacitance from

10 pF to 400 pF:

250

ns with up to 3 mA sink

current at V OL1

I I

Input current each I/O pin

Input Pin Capacitance

Vin=0.4~0.9xVCC_3V

±10

µA

Cin

Note 24: Applied for UDIO3-4 (On use of Serial ROM) pins

5.2.12 Power Consumption

Power Supply Current

Power Pin

Parameter

Min

Typ

Max

Unit

Condition

Note

Icc

Power Supply Current,

Operating

150

PCICLK=33MHz

VCC_3V=3.6V

VCC_MD3V=3.6V

VCC_PCI3V=3.6V

AVCC_PHY3V=3.6V

REGEN#=0V

VCC_RIN=3.6V

Vin=0V or VCC

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

5.3 AC Characteristics

5.3.1 PCI Interface signals

PCI Clock

(VCC_ROUT= 1.65~1.95V, VCC_PCI3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

PCICLK

t1a

t1b

t1c

t1d

t1e

Cycle Time, PCICLK

Pulse Width Duration, PCICLK High

Pulse Width Duration, PCICLK Low

Slew Rate, PCICLK Rising Edge

Slew Rate, PCICLK Falling Edge

V/ns

PCICLK Timing

t1a

t1c

t1b

*2.0V(0.5Vcc)

*0.8V(0.3Vcc)

PCICLK

t1e

t1d

*2.0V p-to-p Min.

(0.4Vcc p-to-p Min.)

*5V Signaling ( 3.3V Signaling)

PCICLK Timing

PCI Reset

(VCC_ROUT= 1.65~1.95V, VCC_PCI3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

PCIRST#

t2a

t2b

Pulse Duration, PCIRST#

Setup Time, PCICLK active at PCIRST# Negation

100

µs

PCI Reset Timing

t2a

PCIRST#

PCICLK

t2b

PCI Reset Timing

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

PCI Interface Output Signals

(VCC_ROUT= 1.65~1.95V, VCC_PCI3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

AD [31:0], C/BE#[3:0], PAR, FRAME#, DEVSEL#, IRDY#, TRDY#, STOP#, PERR#, SERR#, CLKRUN#

t3a

Shared Signal Valid delay time from PCICLK

Min: CL=0 pF

Max: CL=50 pF

(10 pF 3.3v)

t3b

t3c

Enable Time, Hi-Z to active delay from PCICLK

Disable Time, Active to Hi-Z delay from PCICLK

REQ#

t3d

Point to Point Signal Valid delay time from PCICLK

Min: CL=0 pF

Max: CL=50 pF

(10 pF 3.3v)

PCI Output Signals Timing

*1.5V(0.4Vcc)

PCICLK

t3a(Shared), t3d(ptp)

OUTPUT

(Shared or ptp)

*1.5V(0.285Vcc:Rise Edge, 0.615Vcc:Fall Edge)

t3b

OUTPUT

t3c

*5.0V Signaling(3.3V Signaling)

PCI Output Signals Timing

PCI Interface Input Signals

(VCC_ROUT= 1.65~1.95V, VCC_PCI3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

AD [31:0], C/BE#[3:0], PAR, FRAME#, DEVSEL#, IRDY#, TRDY#, STOP#, IDSEL, PERR#, SERR#,

CLKRUN#

t4a

t4b

Setup Time, Shared Signal Valid before PCICLK

Hold Time, Shared Signal Hold Time after PCICLK High

GNT#

t4c

Setup Time, Point to Point Signal Valid before PCICLK

PCI Input Signals Timing

*1.5V(0.4Vcc)

PCICLK

t4a (Shared) t4b

t4c (ptp)

INPUT

*1.5V(0.4Vcc)

*5.0V Signaling(3.3V Signaling)

PCI Input Signals Timing

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

5.3.2 System Interface signals

System Interface Signals AC Characteristics

(VCC_ROUT= 1.65~1.95V, VCC_PCI3V=3.0~3.6V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

RI_OUT#, UDIO0-5, INTA#

t5b

t5c

t5d

RI# to RI_OUT# Delay

2Tcyc+0

Card Status Change to UDIO0-5/INTA# Delay

Card IREQ#/CINT# to UDIO0-5/INTA# Delay

SPKROUT

t5e

SPKR#/CAUDIO to SPKROUT Delay

Note1: Tcyc is PCICLK cycle time. (Typically 30ns)

System Signals Timing

t5b

STSCHG#/RI#

t5b

t5d

t5c

Card Status

Change

t5d

IREQ#

CINT#

IRQ3-15

INTA#

RI_OUT#

SPKR#

CAUDIO

t5e

SPKROUT

System Signals Timing

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

5.3.3 16-bit PC Card Interface signals

Data Sheet

Memory Read

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

CADR [25:0], REG#, CE [2:1]#

t6a

Setup Time, CADR [25:0], REG# and CE

[2:1]# before OE# Low

Tsu-20

1,2

Tsu=1~7Tcyc

Programmable

t6c

t6b

t6d

Hold Time, CADR [25:0], REG# and CE

[2:1]# after OE# High

Thl-10

1,2

Thl=1~7Tcyc

Programmable

OE#

Pulse Duration, OE# Low

Tpw-20

1,2

Tpw=3~31Tcyc

Programmable

CDATA [15:0]

Hold Time, CDATA [15:0] after OE# High

WAIT#

t6e

t6f

Hold Time, OE# Low after WAIT# High

Valid Delay, OE# Low to WAIT# Low

1Tcyc+0

Note1: Tcyc is PCICLK cycle time. (Typically 30ns)

Note2: Tsu, Tpw, Thl can be programmed by setting 16-bit Memory Timing 0 register.

16-bit Card Memory Read Timing

PCICLK

CADR,REG#,

CE1#,CE2#

t6c

t6d

t6a

t6b

OE#

CDATA

WAIT#

Data

t6e

t6f

Data Latched

16-bit Card Memory Read Timing

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

Memory Write

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

CADR [25:0], REG#, CE [2:1]#

t7a

Setup Time, CADR [25:0], REG# and CE

[2:1]# before WE# Low

Tsu-20

1,2

Tsu=1~7Tcyc

Programmable

t7c

t7b

Hold Time, CADR [25:0], REG# and CE

[2:1]# after WE# High

Thl-10

1,2

Thl=1~7Tcyc

Programmable

WE#

Pulse Duration, WE# Low

Tpw-20

1,2

Tpw=3~31Tcyc

Programmable

CDATA [15:0]

t7d

t7e

Setup Time, CDATA [15:0] before WE#

Low

Tsu-20

Thl-10

1,2

Tsu=1~7Tcyc

Programmable

Hold Time, CDATA [15:0] after WE# High

1,2

Thl=1~7Tcyc

Programmable

WAIT#

t7f

Hold Time, WE# Low after WAIT# High

Valid Delay, WE# Low to WAIT# Low

Tcyc+0

t7g

Note1: Tcyc is PCICLK cycle time. (Typically 30ns)

Note2: Tsu, Tpw, Thl can be programmed by setting 16-bit Memory Timing 0 register.

16-bit Card Memory Write Timing

PCICLK

CADR,REG#,

CE1#,CE2#

t7a

t7d

t7c

t7e

t7b

WE#

CDATA

WAIT#

Data

t7g

t7f

16-bit Card Memory Write Timing

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

I/O Read

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

CADR [25:0], REG#

t8a

Setup Time, CADR [25:0] and REG# before IORD#

Low

Tsu-20

1,3

Tsu=2~7Tcyc

Programmable

t8c

t8b

Hold Time, CADR [25:0] and REG# after IORD#

High

Thl-10

1,3

Thl=1~7Tcyc

Programmable

IORD#

Pulse Duration, IORD # Low

Tpw-20

1,3

Tpw=3~31Tcyc

Programmable

CE [2:1]#

t8d

t8e

Valid Delay, CADR [25:0] and REG# to CE [2:1]#

CDATA [15:0]

1Tcyc-10

Hold Time, CDATA [15:0] after IORD # High

WAIT#

t8f

Hold Time, IORD # Low after WAIT# High

Valid Delay, IORD # Low to WAIT# Low

IOIS16#

1Tcyc+0

t8g

t8h

Valid Delay, CADR [25:0] to IOIS16# Low

INPACK#

t8k

t8j

Hold Time, INPACK# Low after IORD# High

Valid Delay, IORD # Low to INPACK# Low

Note1: Tcyc is PCICLK cycle time. (Typically 30ns)

Note3: Tsu, Tpw, Thl can be programmed by setting 16-bit I/O Timing 0 register.

16-bit Card I/O Read Timing

PCICLK

CADR

t8d

CE1#,CE2#

t8h

IOIS16#

t8a

t8b

t8c

t8e

IORD#

CDATA

Data

t8f

t8g

WAIT#

t8j

t8k

INPACK#

Data Latched

16-bit Card I/O Read Timing

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

Data Sheet

I/O Write

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

CADR [25:0], REG#

t9a

Setup Time, CADR [25:0] and REG# before

IOWR # Low

Tsu-20

1,3

Tsu=2~7Tcyc

Programmable

t9c

t9b

Hold Time, CADR[25:0], REG# and CE[2:1]#

after IOWR # High

Thl-10

1,3

Thl=1~7Tcyc

Programmable

IOWR#

Pulse Duration, IOWR# Low

Tpw-20

1,3

Tpw=3~31Tcyc

Programmable

CE[2:1]#

t9h

t9d

Valid Delay, CADR [25:0] and REG# to CE [2:1]#

CDATA [15:0]

1Tcyc-10

Setup Time, CDATA [15:0] before IOWR# Low

Tsu-2Tcyc-10

1,3

Tsu=3~7Tcyc

Programmable

t9e

Hold Time, CDATA [15:0] after IOWR# High

Thl-10

1,3

Thl=1~7Tcyc

Programmable

WAIT#

t9f

Hold Time, IOWR# Low after WAIT# High

Valid Delay, IOWR# Low to WAIT# Low

IOIS16#

1Tcyc+0

t9g

t9j

Valid Delay, CADR [25:0] and REG# to IOIS16#

Low

Note1: Tcyc is PCICLK cycle time. (Typically 30ns)

Note3: Tsu, Tpw, Thl can be programmed by setting 16-bit I/O Timing 0 register.

16-bit Card I/O Write Timing

PCICLK

CADR,REG#

t9a

t9c

t9h

CE1#,CE2#

t9j

IOIS16#

t9b

IOWR#

t9e

t9d

t9g

CDATA

t9f

WAIT#

16-bit Card I/O Write Timing

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

5.3.4 CardBus PC Card Interface signals

Data Sheet

Clock and Signal Slew Rate

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

CCLK

t10a

t10b

t10c

t10d

t10e

Cycle Time, CCLK

Pulse Width Duration, CCLK High

Pulse Width Duration, CCLK Low

Slew Rate, CCLK Rising Edge

Slew Rate, CCLK Falling Edge

Other CardBus Signals

V/ns

t10f

Slew Rate, Rising Edge

0.25

V/ns

t10g

Slew Rate, Falling Edge

CCLK Timing and CardBus Signals Slew Rate

t10a

t10c

t10b

0.475Vcc

0.4Vcc

CCLK

0.325Vcc

t10e

t10d

0.475Vcc

0.325Vcc

Other CardBus

Signals

t10g

t10f

CCLK Timing and CardBus Slew Rate

Card Reset

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

CRST#

t11a

t11b

Pulse Duration, CRST#

Setup Time, CCLK active at CRST# Negation

100

µs

CardBus Reset Timing

t11a

CRST#

CCLK

t11b

CardBus Reset Timing

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Data Sheet

Card Output

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

CAD [31:0], CC/BE#[3:0], CPAR, CFRAME#, CDEVSEL#, CIRDY#, CTRDY#, CSTOP#, CPERR#,

CSERR#, CCLKRUN#, CGNT#

t12a

Valid delay time from CCLK

Min: CL=0 pF

Max: CL=30 pF

t12b

t12c

Enable Time, Hi-Z to active delay from CCLK

Disable Time, Active to Hi-Z delay from CCLK

CardBus Interface Output Signals Timing

CCLK

0.4Vcc

t12a(Min.)

0.475Vcc

0.325Vcc

OUTPUT

t12a(Max.)

t12b

0.4Vcc

t12c

CardBus Interface Output Signals Timing

Card Input

(VCC_ROUT=1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

CAD [31:0], CC/BE#[3:0], CPAR, CFRAME#, CDEVSEL#, CIRDY#, CTRDY#, CSTOP#, CPERR#,

CSERR#, CCLKRUN#, CREQ#

t13a

t13b

Setup Time, Signal Valid before CCLK

Hold Time, Signal Hold Time after CCLK High

CardBus Interface Input Signals Timing

CCLK

0.4Vcc

t13b

t13a

0.475Vcc

0.325Vcc

INPUT

CardBus Input Signals Timing

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Data Sheet

5.3.5 Hardware Suspend mode

Timing chart for keeping the value of the internal register on the Suspend mode.

Hardware Suspend Timing

VCC_PCI3V

HWSPND#

PCI RST#

Tpd

Tpu

Symbol

Tpd

Parameter

Min

Typ

Max

Unit

HWSPND# to PCIRST# delay

100*¹

Tpu

PCIRST# Setup time to HWSPND#

*¹: PCICLK=33MHz

5.3.6 Global Reset signals

Timing chart for initializing the internal register on the Power’s on.

Global Reset Timing

1.65V

3.0V

VCC_RIN,VCC_ROUT

(Disabled regulator)

VCC_RIN

(Enabled regulator)

3.0V

VCC_3V,

VCC_MD3V

Tpres

GBRST#

2.4V

PCI RST#

0.5VCC_PCI3V

Tprise

HWSPND#

Tpspnd

3.0V

VCC_PCI3V

Symbol

Parameter

Min

Typ

Max

Unit

Tpres

Tprise

Tpspnd

Power_On to GBRST# delay

GBRST# to PCIRST# delay

HWSPND# to PCIRST# delay

100

60*²

100*²

*²: PCICLK=33MHz

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ExpressCard

5.3.7 Serial ROM Interface signals

Data Sheet

SDA (UDIO4), SCL(UDIO3)

(VCC_ROUT= 1.65~1.95V, VCC_3V=3.0~3.6V, Ta=0~70ºC)

Symbol

Parameter

Min

Max

Unit

Note

SDA (UDIO4), SCL (UDIO3)

f SCL

SCL clock frequency

100

kHz

t BUF

Bus free time between a STOP and START condition

4.7

4.0

t HD;STA

Hold time (repeated) START condition. After this

period, the first clock pulse is generated

t LOW

t HIGH

t SU;STA

t HD;DAT

t SU;DAT

t R

LOW period of the SCL clock

4.7

4.0

4.7

HIGH period of the SCL clock

Set–up time for a repeated START condition

Data hold time for I 2 C–bus devices

Data set–up time

250

1000

300

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set–up time for STOP condition

t F

t SU;STO

t sp

4.0

n/a

Pulse width of spikes which must be suppressed by

the input filter

n/a

C b

Capacitive load for each bus line

400

All values referred to V IHmin and V ILmax levels (see 5.2.11).

Serial ROM if SDA,SCL timing

SDA(UDIO4)

t_F

t_BUF

t_SP

t_LOW

t_R

t_HD;STA

SCL(UDIO3)

t_SU;STA

t_HD;STA

t_SU;STO

t_HD;DAT

t_HIGH

t_SU;DAT

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R5C841 PCI-CardBus/IEEE 1394/SD Card/Memory Stick/xD/ ExpressCard

Data Sheet

NOTICE

1. The products and the product specifications described in this Data Sheet are subject to change or

discontinuation of production without notice for reasons such as improvement. Therefore, before

deciding to use the products, please refer to Ricoh sales representatives for the latest information

thereon.

2. This Data Sheet may not be copied or otherwise reproduced in whole or in part without prior written

consent of Ricoh.

3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting

or otherwise taking out of your country the products or the technical information described herein.

4. The technical information described in this Data Sheet shows typical characteristics of and example

application circuits for the products. The release of such information is not to be construed as a

warranty of or a grant of license under Ricoh’s or any third party’s intellectual property rights or any

other rights.

5. The products listed in this Data Sheet are intended and designed for use as general electronic

components in standard applications (office equipment, computer equipment, measuring

instruments, consumer electronic products, amusement equipment etc.). Those customers intending

to use a product in an application requiring extreme quality and reliability, for example, in a highly

specific application where the failure or miss-operation of the product could result in human injury or

death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and

transportation equipment, combustion equipment, safety devices, life support system etc.) should

first contact us.

6. We are making our continuous effort to improve the quality and reliability of our products, but

semiconductor products are likely to fail with certain probability. In order prevent any injury to

persons or damages to property resulting from such failure, customers should be careful enough to

incorporate safety measures in their design, such as redundancy feature, fire-containment feature,

and fail-safe feature. We do not assume any liability or responsibility for any loss or damage arising

from misuse or inappropriate use of the products.

7. Anti-radiation design is not implemented in the products described in this Data Sheet.

8. Please contact Ricoh sales representatives should you have any questions or comments concerning

the products or the technical information.

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Data Sheet

RICOH Company, Ltd.

Electronic Devices Company

■ Head Office

13-1, Himemurocho, Ikeda-shi, Osaka 563-8501 JAPAN

Phone: +81-72-748-6262, Fax: +81-72-753-2120

■ Yokohama Office

3-2-3, Shinyokohama, Kouhoku-ku, Yokohama-shi,

Kanagawa 222-8530 JAPAN

Phone: +81-45-477-1703, Fax: +81-45-477-1694

RICOH CORPORATION

Electronic Devices Division

■ Cupertino Office

4 Results Way, Cupertino, CA, 95014 USA

Phone: 408-346-4463

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