Renesas Switch HD74CBT1G125 User Guide

HD74CBT1G125  
Single FET Bus Switch  
REJ03D0815-0100  
(Previous: ADE-205-645)  
Rev.1.00  
Apr 07, 2006  
Description  
The HD74CBT1G125 features a single high-speed line switch. The switch is disabled when the output enable (OE)  
input is high.  
Features  
Minimal propagation delay through the switch.  
5 switch connection between two ports.  
TTL-compatible input levels.  
Ultra low quiescent power.  
Ideally suited for notebook applications.  
Ordering Information  
Package Code  
(Previous code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
HD74CBT1G125CME CMPAK–5pin  
PTSP0005ZC-A  
(CMPAK–5V)  
CM  
E (3,000pcs / Reel)  
Outline and Article Indication  
HD74CBT1G125  
Index band  
Marking  
B B  
= Control code  
CMPAK–5  
(
or blank)  
Function Table  
Input OE  
Function  
L
A port = B port  
Disconnect  
H
H:  
L:  
High level  
Low level  
Rev.1.00 Apr 07, 2006 page 1 of 6  
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HD74CBT1G125  
DC Electrical Characteristics  
(Ta = 40 to 85°C)  
Test conditions  
Item  
Clamp diode voltage  
Input voltage  
Symbol VCC (V)  
Min  
Typ *1  
Max  
Unit  
V
VIK  
VIH  
VIL  
4.5  
1.2  
IIN = 18 mA  
4.0 to 5.5  
4.0 to 5.5  
4.0  
2.0  
V
0.8  
20  
On-state switch resistance *2  
RON  
14  
VIN = 2.4 V, IIN = 15 mA  
Typ at VCC = 4.0 V  
4.5  
4.5  
5
5
7
7
VIN = 0 V, IIN = 64 mA  
VIN = 0 V, IIN = 30 mA  
4.5  
10  
15  
VIN = 2.4 V, IIN = 15 mA  
Input current  
IIN  
IOZ  
0 to 5.5  
5.5  
±1.0  
±1.0  
1.0  
2.5  
µA  
µA  
µA  
mA  
VIN = 5.5 V or GND  
0 A, B VCC  
Off-state leakage current  
Quiescent supply current  
Increase in ICC per input *3  
ICC  
5.5  
VIN = VCC or GND, IO = 0 mA  
ICC  
5.5  
One input at 3.4 V,  
other inputs at VCC or GND  
Notes:  
For condition shown as Min or Max use the appropriate values under recommended operating conditions.  
1. All typical values are at VCC = 5 V (unless otherwise noted), Ta = 25°C.  
2. Measured by the voltage drop between the A and B terminals at the indicated current through the switch.  
On-state resistance is determined by the lower voltage of the two (A or B) terminals.  
3. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC  
or GND.  
Capacitance  
(Ta = 25°C)  
Item  
Symbol  
CIN  
VCC (V)  
5.0  
Min  
Typ  
3
Max  
Unit  
pF  
Test conditions  
VIN = 0 or 3 V  
VO = 0 or 3 V, OE = VCC  
Control input capacitance  
Input / output capacitance  
CI/O (OFF)  
5.0  
5
pF  
Note: This parameter is determined by device characterization is not production tested.  
Rev.1.00 Apr 07, 2006 page 3 of 6  
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HD74CBT1G125  
Switching Characteristics  
(Ta = 40 to 85°C)  
V
CC = 4.0 V  
FROM  
(Input)  
A or B  
TO  
(Output)  
Item  
Symbol  
Min  
Max  
Unit  
Test conditions  
Propagation delay time *1  
tPLH  
tPHL  
0.35  
ns  
CL = 50 pF  
RL = 500 Ω  
B or A  
Enable time  
tZH  
tZL  
5.5  
ns  
ns  
CL = 50 pF  
RL = 500 Ω  
CL = 50 pF  
RL = 500 Ω  
OE  
OE  
A or B  
A or B  
Disable time  
tHZ  
tLZ  
4.5  
4.5  
VCC = 5.0±0.5 V  
FROM  
(Input)  
TO  
(Output)  
B or A  
Item  
Symbol  
Min  
Max  
Unit  
Test conditions  
Propagation delay time *1  
tPLH  
tPHL  
0.25  
ns  
CL = 50 pF  
RL = 500 Ω  
A or B  
Enable time  
Disable time  
tZH  
tZL  
1.6  
4.9  
ns  
ns  
CL = 50 pF  
RL = 500 Ω  
CL = 50 pF  
RL = 500 Ω  
OE  
A or B  
A or B  
tHZ  
tLZ  
1.0  
1.0  
4.2  
4.8  
OE  
Note: 1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and  
the specified load capacitance, when driven by an ideal voltage source (zero output impedance).  
Test Circuit  
See under table  
S1  
500 Ω  
OPEN  
GND  
*1  
CL = 50 pF  
500 Ω  
Load circuit for outputs  
Symbol  
tPLH/ tPHL  
tZH / tHZ  
tZL / tLZ  
S1  
OPEN  
OPEN  
7 V  
Note: 1. CL includes probe and jig capacitance.  
Rev.1.00 Apr 07, 2006 page 4 of 6  
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HD74CBT1G125  
Waveforms – 1  
tr  
tf  
3 V  
90 %  
1.5 V  
90 %  
1.5 V  
Input  
10 %  
10 %  
tPHL  
GND  
VOH  
tPLH  
1.5 V  
1.5 V  
Output  
VOL  
Waveforms – 2  
tf  
tr  
3 V  
90 %  
1.5 V  
90 %  
1.5 V  
Output  
Control  
10 %  
tZL  
10 %  
GND  
3.5 V  
tLZ  
Waveform - A  
1.5 V  
VOL + 0.3 V  
VOH - 0.3 V  
VOL  
VOH  
tZH  
tHZ  
Waveform - B  
1.5 V  
GND  
Notes: 1. All input pulses are supplied by generators having the following characteristics :  
PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns.  
2. Waveform - A is for an output with internal conditions such that the output is low except  
when disabled by the output control.  
3. Waveform - B is for an output with internal conditions such that the output is high except  
when disabled by the output control.  
4. The output are measured one at a time with one transition per measurement.  
Rev.1.00 Apr 07, 2006 page 5 of 6  
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HD74CBT1G125  
Package Dimensions  
JEITA Package Code  
SC-88A  
RENESAS Code  
PTSP0005ZC-A  
Previous Code  
MASS[Typ.]  
0.006g  
CMPAK-5 / CMPAK-5V  
D
A
e
Q
c
E
HE  
L
P
L
Reference  
Symbol  
Dimension in Millimeters  
A
A
L
1
A
3
Min  
0.8  
0
Nom  
Max  
1.1  
0.1  
1.0  
b
A
x
S
A
M
A1  
A2  
A3  
e
0.8  
0.9  
0.25  
0.22  
0.2  
b
0.15  
0.1  
0.3  
b
1
A
2
1
A
c
0.13  
0.11  
2.0  
0.15  
c
1
D
E
e
1.8  
2.2  
1.15  
1.25  
0.65  
2.1  
1.35  
A
y
S
S
e
1
H
E
1.8  
0.3  
0.1  
0.2  
2.4  
0.7  
b
L
L
1
0.5  
b
1
L
P
0.6  
l
1
c1  
x
0.05  
0.05  
0.35  
y
c
b
2
1
e
b
2
1.5  
l
1
0.9  
A-A Section  
Pattern of terminal position areas  
Q
0.25  
Rev.1.00 Apr 07, 2006 page 6 of 6  
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Keep safety first in your circuit designs!  
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble  
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.  
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary  
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.  
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RENESAS SALES OFFICES  
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.  
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© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.  
Colophon .6.0  
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