HD151TS207SS
Mother Board Clock Generator
for Intel P4+ Chipset (Springdale)
REJ03D0006-0100Z
Preliminary
Rev.1.00
Apr.25.2003
Description
The HD151TS207SS is Intel CK409T type high-performance, low-skew, low-C motherboard clock
®
generator. It is specifically designed for Intel Pentium 4+ chipset.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3 differential pairs of current mode control CPU clocks
1 differential pair of Serial Reference Clock (SRC), sel100 MHz/200 MHz
6 copies PCI clocks and 3 copies PCIF clocks @3.3MHz
1 copy PCI clock @3.3 V, selectable 33.3 MHzz
1 copy USB clock @3.3 V, selectable 48 MHz
1 copy DOT clock @3.3 V, 48 MHz
4 copies of 3V66 clocks @3.3 V, 66
1 copy of 3V66/VCH clock @3.ctable 66.6 MHz/48 MHz
2 copies of REF clocks @3.3 18 MHz
Power save and clock stoon
I2CTM serial port progg
Programmable Cltrol (Spread Spectrum Percentage, Clock Output Skew, Slew Rate)
Watchdog timeset output
56pin SSOP mils)
Note: I2C is a trademark of Philips Corporation.
Pentium is registered trademark of Intel Corporation
Rev.1.00, Apr.25.2003, page 1 of 38
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HD151TS207SS
Pin Arrangement
FS_B
REF0 1
56
2
3
4
5
6
7
REF1
VDD_REF
XTAL_IN
55 VDD_A
54
53
52
51
50
VSS_A
VSS_IREF
IREF
XTAL_OUT
VSS_REF
FS_A
FS2/PCIF_0
TEST_CLK#
FS4/PCIF_1 8
49 PCI_STO
PCIF_2
9
VDD_
CP
48
47
46
VDD_PCI 10
#
VSS_PCI
MODE/PCI_0
PCI_1
11
12
13
14
15
16
S_CPU
CPU_1
PCI_2
43 CPU_1#
42
41
40
39
VDD_CPU
CPU_0
PCI_3
VDD_PCI
VSS_PCI
CPU_0#
VSS_SRC
17
18
19
SEL100_200/PCI_4
SEL33_25/PCI_5
PCI_6
38 SRC
37 SRC#
2
2
23
24
25
26
27
28
VDD_SRC
PWRDWN#/SAFE_F
3V66_0/RE
1
36
35
34
33
32
31
30
29
VTT_PWRGD#
VDD_48
VSS_48
3V66
S_3V66
3V66_2
FS3/DOT_48
SEL48_24/USB_48
SDATA
3V66_3
SEL66_48/3V66_4/VCH
SCLK
(Top view)
PCI_STOP#, PWRDWN# = 150 kΩ Internal Pull-up
Rev.1.00, Apr.25.2003, page 3 of 38
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HD151TS207SS
Pin Descriptions
Pin name
VSS_A
No.
54
45
53
39
25
11, 17
6
Type
Description
Ground
Ground for PLL
VSS_CPU
VSS_IREF
VSS_SRC
VSS_3V66
VSS_PCI
VSS_REF
VSS_48
Ground for outputs
Ground for current reference
Ground for outputs
33
55
42, 48
36
24
10, 16
3
VDD_A
Power
3.3 V Power Supply for PLL
VDD_CPU
VDD_SRC
VDD_3V66
VDD_PCI
VDD_REF
VDD_48
3.3 V Power Supply for outputs
34
1
REF0
OUTPUT
3.3 V 14.3reference clock.
14z XTAL input.
REF1
2
XTAL_IN
XTAL_OUT
4
INPUT
5
OUTPUT
MHz XTAL output.
’t connect when an external clock is applied at XTAL_IN.
FS2/PCIF_[0:1]
7,8
INPUT
Frequency select latch input pin.
OU
/Free running PCI clock 3.3 V output.
PCIF_2
9
T
Free running PCI clock 3.3 V output.
**MODE/PCI_0
12
UT/
OUTPUT
Function select latch input pin for pin 22,
1 = Reset#, 0 = clock output.
/PCI clock 3.3 V output.
PCI_[1:3]
14, OUTPUT
15
PCI clock 3.3 V outputs.
**SEL100_200/
PCI_4
18
INPUT/
OUTPUT
Latched select input for SRC output.
1 = 200 MHz, 0 = 100 MHz
/PCI clock 3.3 V output.
**SEL33_25/PCI_5 19
INPUT/
OUTPUT
Latched select input for PCI5 output.
1 = 25 MHz, 0 = 33 MHz
/PCI clock 3.3 V output.
PCI_6
20
OUTPUT
PCI clock 3.3 V outputs.
Note: (*):
(**):
Those pins are 150 kΩ internal pulled-UP.
Those pins are 150 kΩ internal pulled-DOWN.
Rev.1.00, Apr.25.2003, page 4 of 38
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HD151TS207SS
Pin Descriptions (cont.)
Pin name
No.
Type
Description
PWRDWN#/
SAFE_F#
21
INPUT
PULL–UP*
PWRDWN# / SAFE_F# selectable input.
Default is PWRDWN# input.
Byte15[5] = “1” : SAFE_F# input.
PWRDWN# is all clocks stop pin.
Asynchronous active “Low” input.
When asserted low, all output clocks are disabled.
SAFE_F# is active “Low” input.
When SAFE_F# is “Low” ,frequency mode is changed to the
predefined frequency mode.
3V66_0/RESET#
22
OUTPUT
3V66 / Watchdog RESET# selectable ou
Default is 3V66 output.
This signal is active low and selectede latch input.
3V66_[1:3]
SCLK
23,26, OUTPUT
27
3V66 clock 3.3V outputs.
28
29
30
31
32
35
INPUT
PULL-UP*
Clock input for I2C logic.
**SEL66_48/
3V66_4/VCH
INPUT/
OUTPUT
Latched select inp66/VCH output 1 = 48 MHz,
0 = 66.66 MHz. r VCH clock output.
SDATA
IN/OUTPUT Data input fgic.
PULL-UP*
**SEL48_24/
USB_48
INPUT/
OUTPUT
Latcct input for 48_24 MHz output
1 z, 0 = 48 MHz / 24_48 MHz clock 3.3 V output.
FS3/DOT_48
INPUT/
OUTPUT
ency select latch input pin.
T_48 clock 3.3 V output.
VTT_PWRGD#
INPUT
Qualifying input that latches FS_A and FS_B.
When asserted low, FS_A and FS_B are latched.
PUL
SRC#
37
38
T
PUT
“Complementary” clock of Differential Serial Reference Clock.
“True” clock of Differential Serial Reference Clock.
“Complementary” clock of differential CPU clock.
SRC
CPU_[0:2]#
4OUTPUT
CPU_[0:2]
44, OUTPUT
47
“True” clock of differential CPU clock.
PCI_STOP#
49
INPUT
PCI clocks stop pin. Active “Low” input.
PULL–UP*
When asserted low, PCI[6:0] and SRC clocks are
synchronously disabled in low state.
Usually this pin does not give to effect PCIF[2:0] clock outputs.
TEST_CLK#
50
INPUT
Test clock mode pin. Active “Low” input.
PULL-UP*
FS_[A:B]
IREF
51,52
52
INPUT
INPUT
CPU clocks frequency select latch input.
A precision resistor is attached to this pin which is connected
to internal current reference.
A resistor is connected between this pin and GNDIREF.
Note: (*):
(**):
Those pins are 150 kΩ internal pulled-UP.
Those pins are 150 kΩ internal pulled-DOWN
Rev.1.00, Apr.25.2003, page 5 of 38
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HD151TS207SS
Block Diagram
3.3 V VDD_48 VSS_48 3.3 V VDD_A VSS_A
VSS_IREF IREF
6× 3.3V VDD 6×VSS
REF[1:0]
(14.318MHz)
XTAL
14.318 MHz
CK2
CK1
CK0
1/M2
SSC2
1/N2
CPU[2:0]
OSC
CPU[2:0]#
PLL2
For
VCO2
SRC
SRC#
CPU
Clock
PCI[6:0]
PWRDWN#/SAFE_F#
PCI_STOP#
Selec
PCIF[2:0]
Input
Clock
Select
1/M1
SSC1
1/N1
PLL1
For
Clock
VTT_PWRGD#
VCO1
SRC
3V66
PCI
Divider
3V66_0/RESET#
3V66[3:1]
rol
Stop
Control
3V66_4/VCH
TEST_CLK#
*MODE
1/M0
1/N0
USB
P
*SEL100_200
*SEL66_48
*SEL48_24
*SEL33_25
*FS_4/3/2A/B
SCLK
USB_48
DOT_48
SDATA
Control Logic
ed Input pin.
Rev.1.00, Apr.25.2003, page 6 of 38
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HD151TS207SS
I2C Controlled Register Bit Map
Byte0 Control Register
Bit Description
Contents
Type
R
Default Note
7
6
5
4
3
Reserved
Reserved
Reserved
Reserved
0
0
0
0
X
R
R
R
PCI_Stop Reflects the current value
of the external PCI_STOP# pin
0 = PCI_STOP# pin is Low
1 = PCI_STOP# pin is High
R
2
1
Reserved
R
FS_B Reflects the value of the
FS_B pin sampled on power up
0 = FS_B Low at power up
1 = FS_B High at power up
X
See
Table
1
0
FS_A Reflects the value of the
FS_A pin sampled on power up
0 = FS_A Low at power u
1 = FS_A High at powe
X
Table1 Clock Frequency Function Table
Byte6
Bit5
FS_A
FS_B
CPU
[MHz]
SRC
[MHz]
3
PCIF
PCI
[MHz]
REF0
REF1
[MHz]
USB
DOT
[MHz]
Note
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
100
200
133
16
0
266
333
1066
0 66
/200 66
100/200 66
100/200 66
100/200 66
100/200 66
100/200 66
33
33
33
33
33
33
33
33
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
48
48
48
48
48
48
48
48
Table2 Test Clock select table
TEST_CLK# CPU
[MHz]
SRC
[MHz]
3V66
[MHz]
PCIF
PCI
[MHz]
REF0
REF1
[MHz]
USB
DOT
[MHz]
REF/2
Hi–Z
Note
1
0
REF/2
Hi–Z
REF/2
Hi–Z
REF/4
Hi–Z
REF/8
Hi–Z
REF
Hi–Z
See Note1,
Table3
Note: 1. REF is a clock over driven on the XIN during test mode.
Rev.1.00, Apr.25.2003, page 7 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Table3 FS_A and FS_B pin Input level
Logic Level
0 (Low)
Min Voltage
Max Voltage
0.35V
1 (High)
0.70V
Byte1 Control Register
Bit
Description
Contents
Type
ault Note
7
Allow control of SCR with assertion 0 = Free running
RW
See
of PCI_STOP#
1 = Stopped with
PCI_STOP#
Table5
6
SRC Output enable
0 = Disabled (tristate)
1 = Enabled
1
5
4
3
2
Reserved
RW
RW
RW
RW
1
1
1
1
Reserved
Reserved
CPU2 Output enable
0 = Disabate)
1 = En
1
0
CPU1 Output enable
CPU0 Output enable
0 = d (tristate)
bled
RW
RW
1
1
Disabled (tristate)
= Enabled
Byte2 Control Register
Bit
Description
Contents
Type
Default Note
7
SRC_Pwrdwn ode
0 = Driven in power down,
1 = Tristate
RW
0
0
0
0
0
See
Table5
6
5
4
3
SRC_Smode
0 = Driven when stopped,
1 = Tristate
RW
RW
RW
RW
CPU2_Pwrdwn drive mode
CPU1_Pwrdwn drive mode
CPU0_Pwrdwn drive mode
0 = Driven in power down,
1 = Tristate
See
Table4
0 = Driven in power down,
1 = Tristate
0 = Driven in power down,
1 = Tristate
2
1
0
Reserved
Reserved
Reserved
RW
RW
RW
0
0
0
Rev.1.00, Apr.25.2003, page 8 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Table4 CPU Clock Power Management Truth Table
Signal
Pin
PWRDWN#
PWRDWN#
Tristate Bit
Byte2[5:3]
Non-Stop
Outputs
Byte1[5:3] = 1
Note
CPU[2:0]
CPU[2:0]
CPU[2:0]
1
0
0
X
0
1
Running
Driven @ Iref x2
Tristate
See Note1
Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA,
Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω)
Table5 SRC Clock Power Management Truth Table
Signal Pin
Pin
PCI_STOP# PWRDWN# Non-
Stoppable Note
Outputs
PWRDWN# PCI_STOP# Tristate Bit Tristate Bit Ou
Byte2[6]
Byte2[7]
] = 1 Byte1[7] = 0
SRC
SRC
1
1
1
0
X
0
X
X
ning
Running
Running
Driven @
Iref x6
See Note1
See Note1
SRC
SRC
1
0
0
1
Running
Tristate
X
X
Driven @
Iref x2
Driven @
Iref x2
SRC
0
X
X
1
Tristate
Tristate
Note: 1. Iref = VDD/(3Rr) = 3.3/(3x32 mA
Iref x6 = 13.9 mA (Voh V @50 Ω)
Iref x2 = 4.6 mA (Voh 23 V @50 Ω)
Byte3 Control Register
Bit
Descript
Contents
Type
Default Note
7
PCI_Stontrol
0 = Enabled, all stoppable PCI
and SRC clocks are stopped.
1 = Disabled
RW
1
6
5
4
3
2
1
0
PCI_6 Output enable
PCI_5 Output enable
PCI_4 Output enable
PCI_3 Output enable
PCI_2 Output enable
PCI_1 Output enable
PCI_0 Output enable
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
Rev.1.00, Apr.25.2003, page 9 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte4 Control Register
Bit
Description
Contents
Type
Default Note
7
USB_48 2x output drive
0 = 2x Drive strength,
1 = Normal
RW
0
6
5
4
3
USB_48MHz Output Enable
0 = Disabled,
1 = Enabled
0 = Free Running
1 = Stopped with PCI_STOP#
0 = Free Running
1 = Stopped with PCI_STOP#
0 = Free Running
1 = Stopped with PCI_STOP#
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
RW
RW
RW
RW
1
0
0
0
Allow control of PCIF_2 with
assertion of PCI_STOP#
Allow control of PCIF_1 with
assertion of PCI_STOP#
Allow control of PCIF_0 with
assertion of PCI_STOP#
PCIF_2 Output enable
2
1
RW
RW
PCIF_1 Output enable
0
PCIF_0 Output enable
0 = Disabled, 1 = Enabled
RW
Byte5 Control Register
Bit
7
Description
Contents
Type
RW
RW
Default Note
DOT_48MHz Output Enable
Reserved
0 = Disabled, 1 = En
1
1
0
6
5
VCH Select 66MHz / 48MHz
0 = 3V66 mo
RW
1 = VCH (mode
4
3V66_4/VCH Output Enable
0 = Ditristate),
1 = d
RW
1
3
2
1
0
3V66_3 Output Enable
3V66_2 Output Enable
3V66_1 Output Enable
3V66_0 Output Enable
abled, 1 = Enabled
Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
RW
RW
RW
RW
1
1
1
1
Byte6 Control Register
Bit
7
Descripti
Contents
Type
RW
RW
RW
RW
RW
RW
Default Note
Test Clde
Reserved
0 = Disabled, 1 = Enabled
0
0
0
0
0
6
5
FS_A & FS_B Operation
SRC Frequency Select
Reserved
0 = Normal, 1 = Test mode
0 = 100MHz, 1 = 200 MHz
4
3
2
Spread Spectrum Mode
0 = Spread OFF
1 = Spread ON
0
See
B9[7:6]
1
0
REF1 Output Enable
REF0 Output Enable
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
RW
RW
1
1
Rev.1.00, Apr.25.2003, page 10 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte7 Vendor Identification Register
Bit
7
Description
Contents
Type
R
Default Note
Revision Code Bit3
Revision Code Bit2
Revision Code Bit1
Revision Code Bit0
Vendor ID Bit3
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
Vendor Specific
0
0
0
1
1
1
6
R
5
R
4
R
3
R
2
Vendor ID Bit2
R
1
Vendor ID Bit1
R
0
Vendor ID Bit0
R
Byte8 Read Back Byte Count Register
Bit
7
Description
Contents
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default Note
Read back byte count Bit7
Read back byte count Bit6
Read back byte count Bit5
Read back byte count Bit4
Read back byte count Bit3
Read back byte count Bit2
Read back byte count Bit1
Read back byte count Bi
Writing to this registefigure
byte Count and hobytes will
be read back.
0
0
0
1
1
1
1
0
6
5
Default is 1Ebytes.
4
3
2
1
0
Rev.1.00, Apr.25.2003, page 11 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte9 Control Register
Bit
Description
Contents
Type
Default Note
7
SSC2 Enable Bit
B6[2] = 0 or B9[7] = 1 : SSC2 =OFF
B6[2] = 1 & B9[7] = 0 : SSC2 = ON
RW
0
6
5
4
3
2
1
0
SSC1 Enable Bit
B6[2] = 0 or B9[6] = 1 : SSC1 = OFF
B6[2] = 1 & B9[6] = 0 : SSC1 = ON
RW
RW
RW
R
RW
RW
0
Clock Frequency Control
Bit4
Latched input PCIF_1 at Power ON
Latched input DOT48 at Power ON
Latched input PCIF_0 at Power ON
Latched input FS_A at Power ON
Latched input FS_B at Power
X
X
X
0
See
Table
6
Clock Frequency Control
Bit3
Clock Frequency Control
Bit2
Clock Frequency Control
Bit1
Clock Frequency Control
Bit0
Frequency Select Mode Bit 0 = Freq. is selected binput
FS_A and FS_B
1 = Freq. is selecC B9[5:1]
Rev.1.00, Apr.25.2003, page 12 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Table6 Clock Frequency Function Table
No.
FS_4
FS_3
FS_2
FS_A
FS_B
CPU
SRC
3V66
PCI
[MHz]
[MHz]
[MHz]
[MHz]
B9[5]
0
B9[4]
0
B9[3]
0
B9[2]
0
B9[1]
0
0
100.02
200.03
133.36
166.69
200.03
400.07
266.71
333.39
138.69
142
.36
152.91
156.47
160.03
163.58
167.14
170.70
174.25
177.81
181.36
184.92
186.70
189.36
192.03
194.70
197.37
200.03
202.70
205.37
208.03
210.70
100.02
100.02
100.02
100.02
100.02
100.02
100.
02
00.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
100.02
66.68
66.68
66.68
66.68
6
6.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
66.68
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
33.34
1
0
0
0
0
1
2
0
0
0
1
0
3
0
0
0
1
1
4
0
0
1
0
0
5
0
0
1
0
1
6
0
0
1
1
0
7
0
0
1
1
1
8
0
1
0
0
0
9
0
1
0
0
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
0
0
0
1
1
0
1
1
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
Rev.1.00, Apr.25.2003, page 13 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte10 Control Register
Bit
7
Description
Contents
Type
RW
Default Note
SSC Spread Select Bit[2:0]
Bit[2:0] =
0
0
0
000 = –0.500%, 100 = ±0.250%
001 = –0.750%, 101 = ±0.375%
010 = –1.000%, 110 = ±0.500%
011 = –1.500%, 111 = ±0.750%
6
RW
5
RW
4
3
2
1
0
Backup of latch Input FS_4 at
Power ON
When SAFE_F# is Enable
(B15[5]=1)
PWRDWN#/SAFE_F# pin to
“Low”, and if B23[1]=0, frequency
selection is changed to these
setting and
PWRDWN#/SAFE_F# pin to
“High”, frequency selection
changed back to the last
R
R
R
R
X
X
X
X
Backup of latch Input FS_3 at
Power ON
Backup of latch Input FS_2 at
Power ON
Backup of latch Input FS_A at
Power ON
Backup of latch Input FS_B at
Power ON
Byte11 Control Register
Bit
7
Description
Co
Type
RW
RW
RW
R
Default Note
PCI_STOP# Enable Control Bit
CPU_STOP# Enable Control B
PWRDWN# Enable Contro
Backup of B9[5] written
Backup of B9[4] wrC
Backup of B9[3by I2C
Backup of tten by I2C
Backup ] written by I2C
able , 1 = Disable
Enable , 1 = Disable
0 = Enable , 1 = Disable
0
6
0
5
0
4
When SAFE_F# is Enable
(B15[5]=1)
PWRDWN#/SAFE_F# pin to
“Low”, and if B23[1]=1,
frequency selection is changed to
these setting and
PWRDWN#/SAFE_F# pin to
“High”, frequency selection is
changed back to the last mode.
X
X
X
X
X
3
R
2
R
1
R
0
R
Rev.1.00, Apr.25.2003, page 14 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte12 Control Register
Bit
7
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Contents
Type
R/W
R/W
R/W
R/W
R/W
R/W
Default Note
0
0
0
0
0
6
5
4
3
2
PLL1 Output (VCO1) Frequency
Control Bit
(M1/N1 Divider Control Bit)
PLL1 : for SRC/3V66/PCI_PLL
0 = Normal mode
See.
Note
1
PLL1 M1[6:0] and N1[9:0] are
changed on Table 5 selection
decided by FS4/3/2/A/B or
B9[5:1]
1 = Over or Down clocking m
PLL1 M1[6:0] and N1[9:0]
changed by B12[1:0], B
and B14[6:0].
B12[1:0], B13[7:04[6:0]
are able to be at B12[2]
= 1.
1
0
PLL1 N1 Divider Control Bit9
PLL1 N1 Divider Control Bit8
N1[9]
N1[
R/W
R/W
0
0
Note: 1. B12[1:0], B13[7:0] and B14[6:0] mritten together (at writing B14) in every case.
Byte13 Control Register
Bit
7
Description
Contents
N1[7]
N1[6]
N1[5]
N1[4]
N1[3]
N1[2]
N1[1]
N1[0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Note
PLL1 N1 Divider Cit7
PLL1 N1 Dividol Bit6
PLL1 N1 ontrol Bit5
PLL1 Ner Control Bit4
PLL1 N1 Divider Control Bit3
PLL1 N1 Divider Control Bit2
PLL1 N1 Divider Control Bit1
PLL1 N1 Divider Control Bit0
0
1
0
0
1
0
1
1
See
Note
1
6
5
4
3
2
1
0
Note: 1. B12[1:0], B13[7:0] and B14[6:0] must be written together (at writing B14) in every case.
Rev.1.00, Apr.25.2003, page 15 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte14 Control Register
Bit
7
Description
Contents
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/
Default Note
Reserved
0
0
0
1
0
0
See
Note
1
6
PLL1 M1 Divider Control Bit6
PLL1 M1 Divider Control Bit5
PLL1 M1 Divider Control Bit4
PLL1 M1 Divider Control Bit3
PLL1 M1 Divider Control Bit2
PLL1 M1 Divider Control Bit1
PLL1 M1 Divider Control Bit0
M1[6]
M1[5]
M1[4]
M1[3]
M1[2]
M1[1]
M1[0]
5
4
3
2
1
0
Note: 1. B12[1:0], B13[7:0] and B14[6:0] must be written together (at writiin every case.
Byte15 Control Register
Bit
Description
Contents
Type
Default Note
7
PCI_5 Output Frequency Select
Bit
0 = 33.3 MH5 MHz
R/W
0
6
5
USB_48 Output Frequency
Select Bit
0 = 4= 24 MHz
R/W
R/W
0
0
SAFE_F# Input mode select Bit
RDWN# input mode
SAFE_F# input mode
efault is PWRDWN# input.
SAFE_F# is active “Low” input.
When SAFE_F# is “Low”,
frequency mode is changed to
the predefined frequency mode.
Predefined frequency mode is
selected by B23[1].
4
Clock Divntrol Bit
0 = Normal mode
R/W
0
Clock dividers are changed by
Table 5 selection decided B9[5:1]
1 = Over or Down clocking mode
Clock dividers are changed by
B15[3:0] and B16[7:0].
B15[3:0] and B16[7:0] are able to
be changed at B15[4] = 1.
3
2
1
0
CPU Divider Control Bit3
CPU Divider Control Bit2
CPU Divider Control Bit1
CPU Divider Control Bit0
0001 = 1/1,
0010 = 1/2,
0011 = 1/3,
0100 = 1/4,
0101 = 1/5,
0110 = 1/6,
0111 = 1/7
1000 = 1/8
1001 = 1/9
1010 = 1/10
1011 = 1/11
R/W
R/W
R/W
R/W
X
X
X
X
Rev.1.00, Apr.25.2003, page 16 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte16 Control Register
Bit
Description
Contents
Type
Default Note
7
3V66 / PCI / PCIF Divider Control 3V66 divider ratio =
Bit3
R/W
X
0010 = 1/2,
0011 = 1/3,
0100 = 1/4,
0101 = 1/5,
0110 = 1/6,
0111 = 1/7
1000 = 1/8
1001 = 1/9
1010 = 1/10
1011 = 1/11
6
3V66 / PCI / PCIF Divider Control
Bit2
R/W
X
5
4
3V66 / PCI / PCIF Divider Control PCI / PCIF divider ratio = 3v66 x
R/W
X
X
Bit1
1/2
3V66 / PCI / PCIF Divider Control
Bit0
3
2
1
0
SRC Divider Control Bit3
SRC Divider Control Bit2
SRC Divider Control Bit1
SRC Divider Control Bit0
0001 = 1/1,
0010 = 1/2,
0011 = 1/3,
0100 = 1/4,
0101 = 1/5,
0110 = 1/6
0111 = 1/7
1000 = 1
1001
101
/11
/W
R/W
R/W
R/W
X
X
X
X
Byte17 Control Register
Bit
7
Description
Reserved
Reserved
Reserved
s
Type
R/W
R/W
R/W
R/W
Default Note
0
0
0
6
5
4
PLL2 Output (VCO2) cy
Control Bit
(M2 / N2 Dividel Bit)
PLL2 : for CP
0 = Normal mode
0
See
Note
1
VCO2 frequency is changed on
Table 5 selection decided by
FS4/3/2/A/B or B9[5:1].
1 = Over or Down clocking mode
VCO2 frequency is changed by
B17[3:0] and B18[7:0] with
decimal.
B17[3:0] and B18[7:0] are able to
be changed at B17[4] = 1.
3
2
1
0
VCO2 Frequency Control Bit11
VCO2 Frequency Control Bit10
VCO2 Frequency Control Bit9
VCO2 Frequency Control Bit8
These bits are 100MHz digit of
VCO2 frequency.
0000 = 0, 0001 = 1 …. 1001 = 9
R/W
R/W
R/W
R/W
0
1
0
0
Note: 1. B17[3:0] and B18[7:0] must be written together (at writing B18) in every case.
Rev.1.00, Apr.25.2003, page 17 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte18 Control Register
Bit
7
Description
Contents
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/
Default Note
VCO2 Frequency Control Bit7
VCO2 Frequency Control Bit6
VCO2 Frequency Control Bit5
VCO2 Frequency Control Bit4
VCO2 Frequency Control Bit3
VCO2 Frequency Control Bit2
VCO2 Frequency Control Bit1
VCO2 Frequency Control Bit0
These bits are 10MHz digit of
VCO2 frequency.
0000 = 0, 0001 = 1 …. 1001 = 9
0
0
0
0
0
0
See
Note
1
6
5
4
3
These bits are 1MHz digit of
VCO2 frequency.
0000 = 0, 0001 = 1 …. 1001 = 9
2
1
0
Note: 1. B17[3:0] and B18[7:0] must be written together (at writing B18) iase.
How to set VCO2 frequency to 666 MHz.
Write
18
0
Byte17
0
0
0
1
0
1
1
0
1
1
0
0
1
1
0
ON
6
6
6
max 720
min 200
How to read actual frequency 2 and CPU clock
Byte17[4] = 1
Actual VCO2 freq. re.
Byte19
Byte20
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
6
6
6
8
Note:
Case of VCO2 = 666.8 MHz.
Other clock frequency are able to read using the same way as shown at upper.
Byte19, Byte20 = Read back of VCO2 actual frequency.
Byte21, Byte22 = Read back of CPU actual frequency.
Rev.1.00, Apr.25.2003, page 18 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte19 Control Register
Bit
7
Description
Contents
Type
R
Default Note
VCO2 Frequency Read Bit15
VCO2 Frequency Read Bit14
VCO2 Frequency Read Bit13
VCO2 Frequency Read Bit12
VCO2 Frequency Read Bit11
VCO2 Frequency Read Bit10
VCO2 Frequency Read Bit9
VCO2 Frequency Read Bit8
Calculation result of VCO2
frequency.
100 MHz digit
0
0
0
0
0
0
6
R
5
R
0000 = 0, 0001 = 1 …. 1001 = 9
4
R
3
Calculation result of VCO2
frequency.
10 MHz digit
R
2
R
1
R
0000 = 0, 0001 = 1 …. 1001 = 9
0
Byte20 Control Register
Bit
7
Description
Contents
Type
R
Default Note
VCO2 Frequency Read Bit7
VCO2 Frequency Read Bit6
VCO2 Frequency Read Bit5
VCO2 Frequency Read Bit4
VCO2 Frequency Read Bit3
VCO2 Frequency Read Bit2
VCO2 Frequency Read Bit1
VCO2 Frequency Read
Calculation resO2
frequency.
1 MHz dig
0
0
0
0
0
0
0
0
6
R
5
R
0000 = = 1 …. 1001 = 9
4
R
3
ion result of VCO2
ency.
MHz digit
R
2
R
1
R
0000 = 0, 0001 = 1 …. 1001 = 9
0
R
Byte21 Control Registe
Bit
7
Descript
Contents
Type
R
Default Note
CPU Frcy Read Bit15
CPU Frequency Read Bit14
CPU Frequency Read Bit13
CPU Frequency Read Bit12
CPU Frequency Read Bit11
CPU Frequency Read Bit10
CPU Frequency Read Bit9
CPU Frequency Read Bit8
Calculation result of CPU
frequency.
100 MHz digit
0
0
0
0
0
0
0
0
6
R
5
R
0000 = 0, 0001 = 1 …. 1001 = 9
4
R
3
Calculation result of CPU
frequency.
10 MHz digit
R
2
R
1
R
0000 = 0, 0001 = 1 …. 1001 = 9
0
R
Rev.1.00, Apr.25.2003, page 19 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte22 Control Register
Bit
7
Description
Contents
Type
R
Default Note
CPU Frequency Read Bit7
CPU Frequency Read Bit6
CPU Frequency Read Bit5
CPU Frequency Read Bit4
CPU Frequency Read Bit3
CPU Frequency Read Bit2
CPU Frequency Read Bit1
CPU Frequency Read Bit0
Calculation result of CPU frequency.
1 MHz digit
0000 = 0, 0001 = 1 …. 1001 = 9
0
0
0
0
0
0
6
R
5
R
4
R
3
Calculation result of CPU frequency.
0.1 MHz digit
0000 = 0, 0001 = 1 …. 1001 = 9
R
2
R
1
R
0
Byte23 Control Register
Bit
Description
Contents
Type
Default Note
7
Watchdog Enable Control Bit 0 = Disable , Pin22 0 output
1 = Enable , PinSET# output
R/W
0
6
5
4
3
2
RESET# Reverse Control Bit 0 = Normal , rse
R/W
R/W
R/W
R/W
R/W
0
1
0
0
0
Watchdog Timer Count Bit3
Watchdog Timer Count Bit2
Watchdog Timer Count Bit1
Watchdog Timer Count Bit0
These 4 sponds to how
many g timer will wait from
beclarm mode” (B23[0] = 1)
ting RESET# pin to “Low”.
t is 586ms x8 = 4.7s at Power
1
Backup Frequency Sel0 = B10[4:0] , 1 = B11[4:0]
When SAFE_F# is “Low” , frequency
R/W
0
mode is changed to the predefined
frequency mode decided by B10[4:0]
or B11[4:0].
0
WatchdoBit
0 = Normal mode, 1 = Alarm mode
R/W
0
Rev.1.00, Apr.25.2003, page 20 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte24 Control Register
Bit
7
Description
Contents
Type
R/W
R/W
Default Note
Reserved
0
0
6
PCI_STOP# Stop PCI_6
Control Bit
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free running
0 = Stoppable, 1 = Free runni
0 = Stoppable, 1 = Free
5
4
3
2
1
0
PCI_STOP# Stop PCI_5
Control Bit
R/W
R/W
R/
R/W
R/W
0
0
0
0
0
PCI_STOP# Stop PCI_4
Control Bit
PCI_STOP# Stop PCI_3
Control Bit
PCI_STOP# Stop PCI_2
Control Bit
PCI_STOP# Stop PCI_1
Control Bit
PCI_STOP# Stop PCI_0
Control Bit
Byte25 Control Register
Bit
Description
Conte
Type
Default Note
7
CPU Clock Skew1 Control
Bit3
elay
Ahead
R/W
1
0
0
0
1
0
0
0
See
Note
1
+0.00ns, 0111 = –0.20ns
= +0.20ns, 0110 = –0.40ns
10 = +0.40ns, 0101 = –0.60ns
1011 = +0.60ns, 0100 = –0.80ns
1100 = +0.80ns, 0011 = –1.00ns
1101 = +1.00ns, 0010 = –1.20ns
1110 = +1.20ns, 0001 = –1.40ns
1111 = +1.40ns, 0000 = –1.60ns
6
5
4
3
2
1
0
CPU Clock Skew1 Control
Bit2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CPU Clock Skew1 C
Bit1
CPU Clock Skntrol
Bit0
CPU Cw2 Control
Bit3
Delay
Ahead
See
Note
1
1000 = +0.00ns, 0111 = –0.15ns
1001 = +0.15ns, 0110 = –0.30ns
1010 = +0.30ns, 0101 = –0.45ns
1011 = +0.45ns, 0100 = –0.60ns
1100 = +0.60ns, 0011 = –0.75ns
1101 = +0.75ns, 0010 = –0.90ns
1110 = +0.90ns, 0001 = –1.05ns
1111 = +1.05ns, 0000 = –1.20ns
CPU Clock Skew2 Control
Bit2
CPU Clock Skew2 Control
Bit1
CPU Clock Skew2 Control
Bit0
Note: 1. Total CPU Clock Skew is Skew1+Skew2.
Rev.1.00, Apr.25.2003, page 21 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte26 Control Register
Bit
Description
Contents
Type
Default Note
7
PCIF / PCI Clock Skew2
Control Bit3
Skew2 is “Late” Skew that is Delay
Time from “Normal” Skew1.
R/W
0
0
0
See
Note
1
0000 = +0.0ns, 1000 = +3.2ns
0001 = +0.4ns, 1001 = +3.6ns
0010 = +0.8ns, 1010 = +4.0ns
0011 = +1.2ns, 1011 = +4.4ns
0100 = +1.6ns, 1100 = +4.8ns
0101 = +2.0ns, 1101 = +5.2ns
0110 = +2.4ns, 1110 = +5.6ns
0111 = +2.8ns, 1111 = +6.0ns
6
5
4
PCIF / PCI Clock Skew2
Control Bit2
R/W
R/W
R/W
PCIF / PCI Clock Skew2
Control Bit1
PCIF / PCI Clock Skew2
Control Bit0
3
2
1
0
PCIF / PCI Clock Skew1
Control Bit3
Skew1 is “Normal” Skew.
R/W
R/W
R/W
1
0
0
0
See
Note
1
Delay
Ahead
1000 = +0.0ns, 0111 = –0.4ns
1001 = +0.4ns, 0110 = –0.8n
1010 = +0.8ns, 0101 = –1
1011 = +1.2ns, 0100 =
1100 = +1.6ns, 0011 s
1101 = +2.0ns, 0.4ns
1110 = +2.4ns, –2.8ns
1111 = +2.8= –3.2ns
PCIF / PCI Clock Skew1
Control Bit2
PCIF / PCI Clock Skew1
Control Bit1
PCIF / PCI Clock Skew1
Control Bit0
Note: 1. PCIF / PCI Clock Skew is Skew1 (= Nr Skew1+Skew2 (= Late).
Byte27 Control Register
Bit
7
Description
ntents
Type
R/W
R/W
R/W
R/W
Default Note
Reserved
0
6
PCIF_2 Skew Sel
PCIF_1 Skew it
PCIF_0 Skct Bit
0 = Normal, 1 = Late
0 = Normal, 1 = Late
0 = Normal, 1 = Late
Delay
1000 = +0.0ns, 0111 = –0.4ns
1001 = +0.4ns, 0110 = –0.8ns
1010 = +0.8ns, 0101 = –1.2ns
1011 = +1.2ns, 0100 = –1.6ns
1100 = +1.6ns, 0011 = –2.0ns
1101 = +2.0ns, 0010 = –2.4ns
1110 = +2.4ns, 0001 = –2.8ns
1111 = +2.8ns, 0000 = –3.2ns
0
See
5
0
0
Note
1
4
3V66 Cew Control
Bit3
Ahead
3
2
1
0
R/W
R/W
R/W
R/W
1
0
0
0
3V66 Clock Skew Control
Bit2
3V66 Clock Skew Control
Bit1
3V66 Clock Skew Control
Bit0
Note: 1. Normal = Skew1(B26[3:0]), Late = Skew1(B26[3:0]) +Skew2 (B26[7:4]).
Rev.1.00, Apr.25.2003, page 22 of 38
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HD151TS207SS
I2C Controlled Register Bit Map (cont.)
Byte28 Control Register
Bit
7
Description
Contents
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/
Default Note
Reserved
0 = Normal, 1 = Late
0 = Normal, 1 = Late
0 = Normal, 1 = Late
0 = Normal, 1 = Late
0 = Normal, 1 = Late
0 = Normal, 1 = Late
0 = Normal, 1 = Late
0 = Normal, 1 = Late
0
6
PCI_6 Skew Select Bit
PCI_5 Skew Select Bit
PCI_4 Skew Select Bit
PCI_3 Skew Select Bit
PCI_2 Skew Select Bit
PCI_1 Skew Select Bit
PCI_0 Skew Select Bit
0
0
0
0
0
See
Note
1
5
4
3
2
1
0
Note: 1. Normal = Skew1(B26[3:0]), Late = Skew1(B26[3:0]) +Skew2 (B2
Byte29 Control Register
Bit
7
Description
Contents
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Note
VCH Slew Rate Control Bit1
VCH Slew Rate Control Bit0
PCI Slew Rate Control Bit1
PCI Slew Rate Control Bit0
00 = Normal, 10
01 = “+“
1
0
1
0
1
0
1
0
,
6
5
00 = Nor= “++”
01 = “11 = “–”
4
3
PCIF Slew Rate Control Bit1 0mal, 10 = “++”
“ , 11 = “–”
2
PCIF Slew Rate Control Bit0
3V66 Slew Rate Control 0 = Normal, 10 = “++”
01 = “+“ , 11 = “–”
1
0
3V66 Slew Rate Con
Rev.1.00, Apr.25.2003, page 23 of 38
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HD151TS207SS
Clock Stop Timing Diagram
PCI_STOP# Assertion/De-assersion
PCI_STOP#
PCI_F
Low
PCI
SRC (Stoppable)
SRC (Stoppable)
SRC# (Stoppable)
6
Iref (Controled by Byte2[6])
Tristate (Controled by Byte2[6])
Tristate
PCI_STOP# Assertion/De-assertion Waveforms
PWRDWN# Assertion/De-assersion
< 1.8 ms
PWRDWN#
2× Iref (Controle[5:3])
6× Iref
CPU (Stoppable)
CPU (Stoppable)
CPU# (Stoppable)
Float (CoByte2[5:3])
6× Iref
Float
N# Assertion/De-assertion Waveforms
PWRDWNality
PWRD
PU
CPU#
SRC
SRC#
3V66 PCIF/PCI USB/DOT
REF
Normal Normal Normal Normal
66MHz 33MHz
Low Low
48MHz
Low
14.318MHz
Iref:2
or Float
Iref:2
or Float
Float
Float
Low
Rev.1.00, Apr.25.2003, page 24 of 38
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HD151TS207SS
Renesas clock generator I2C Serial Interface Operation
1. Write mode
1.1 Controller (host) sends a start bit.
1.2 Controller (host) sends the write address D2 (h).
1.3 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”).
1.4 Controller (host) sends a begin byte M.
1.5 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”).
1.6 Controller (host) sends a byte count N.
1.7 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”).
1.8 Controller (host) sends data from byte M to byte M+N–1.
1.9 Renesas clock generator will acknowledge each byte one at a time.
1.10 Controller (host) sends a stop bit.
1 bit
7 bits
1 bit 1 bit
8 bits
1 bit
bits
1 bit 8 bits
Ack Byte M
Slave
address
R/W
Ack
D2(h)
Start bit
Begin Byte = M
yte Count = N
1 bit
8 bits
1 bit
8 bits
1 bit
1 bit
Ack Byte M+1 Ack
Byte M+N–1 Ack Stop bit
Rev.1.00, Apr.25.2003, page 25 of 38
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HD151TS207SS
Renesas clock generator I2C Serial Interface Operation (cont.)
2. Read mode
2.1 Controller (host) sends a start bit.
2.2 Controller (host) sends the write address D2 (h).
2.3 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”).
2.4 Controller (host) sends a begin byte M.
2.5 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”).
2.6 Controller (host) sends a restart bit.
2.7 Controller (host) sends the read address D3 (h).
2.8 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”
2.9 Renesas clock generator will send the byte count N.
2.10 Controller (host) will acknowledge.
2.11 Renesas clock generator will send data from byte M to byte M+N
2.12 When Renesas clock generator sends the last byte, controller (ll not acknowledge.
2.13 Controller (host) sends a stop bit.
1 bit
7 bits
1 bit 1 bit
R/W
8 bits
t
1 bit
7 bits
Slave
1 bit
R/W
Slave
address
Start bit
Ack Begin M Ack Restart bit
address
D2(h)
D3(h)
1 bit
8 bits
1 bit 8 bits
8 bits
1 bit
8 bits
1 bit
1 bit
Ack Begin Count = N Ack Byck Byte M+1 Ack
Byte M+N–1 Not Ack Stop bit
Notes: 1. Renesas cerator is a slave/receiver, I2C component. It can read back the data stored in
the latcthe verification.
2. The ansfer rate supported by this clock generator is 100k bits/sec or less (standard
mode).
3. The input is operating at 3.3 V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only block-write from
the controller.
6. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The data is loaded until a stop sequence is
issued.
7. At power-on, all registers are set to a default condition, as shown.
Rev.1.00, Apr.25.2003, page 26 of 38
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HD151TS207SS
Absolute Maximum Ratings
Item
Symbol
VDD
VI
Ratings
Unit
V
Conditions
Supply voltage
Input voltage
–0.5 to 4.6
–0.5 to 4.6
V
–0.5 to VDD
+0.5
Output voltage *1
VO
V
Input clamp current
IIK
IOK
IO
–50
–50
±50
mA
mA
mA
VI < 0
Output clamp current
Continuous output current
VO < 0
VO = 0 to VDD
Maximum power dissipation
at Ta = 55°C (in still air)
0.7
W
Storage temperature
Tstg
–65 to +150
°C
Notes:
Stresses beyond those listed under “absolute maximum ratings” se permanent damage
to the device. These are stress ratings only, and functional opof the device at these or
any other conditions beyond those indicated under “recommoperating conditions” is not
implied. Exposure to absolute maximum rated conditionended periods may affect device
reliability.
1. The input and output negative voltage ratings may eded if the input and output clamp
current ratings are observed.
Recommended Operating Conditions
Item
Symbo
Typ
3.3
3.3
—
Max
Unit Conditions
Supply voltage
VD
.135
3.465
3.465
VDD+0.3
VDD+0.3
0.8
V
Supply voltage
3.135
–0.3
2.0
V
DC input signal voltage
High level input voltage
Low level input voltage
Operating tempera
V
VIH
VIL
Ta
—
V
–0.3
0
—
V
—
70
°C
Rev.1.00, Apr.25.2003, page 27 of 38
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HD151TS207SS
DC Electrical Characteristics / Serial Input Port
Ta = 0°C to 70°C, VDD = 3.3 V
Item
Symbol Min
Typ *1 Max
Unit Test Conditions
Input Low Voltage
Input High Voltage
Input Current
VIL
0.8
V
V
VIH
II
2.0
–50
+50
µA
VI = 0 V or 3.465 V,
VDD = 3.465 V
Input capacitance
CI
10
pF
SDATA & SCLK
Note: 1. For conditions shown as Min or Max, use the appropriate value specified undr recommended
operating conditions.
AC Electrical Characteristics / Serial Input port
Ta = 0°C to 70°C, VDD = 3.3 V
Item
Symbol Min
Typ
Max
Test Conditions
Notes
SCLK Frequency
Start Hold Time
SCLK Low Time
SCLK High Time
Data Setup Time
Data Hold Time
Stop Setup Time
FSCLK
1
Hz
µs
µs
µs
ns
ns
µs
µs
Normal Mode
tSTHD
tLOW
tHIGH
tDSU
tDHD
tSTSU
tSP
4.0
4.7
4.0
250
.7
BUS Free Time between
Stop & Start Condition
Rev.1.00, Apr.25.2003, page 28 of 38
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HD151TS207SS
DC Electrical Characteristics CPU/CPU# Clock
Ta = 0°C to 70°C, VDD = 3.3 V, Iref = 475 Ω
Item
Symbol Min
Typ *1
Max
Unit
V
Test Conditions
Rp = 49.9 Ω, VDD = 3.3 V
VDD = 3.3 V
Output voltage
Output Current
Output resistance
VO
1.20
IO
I(nom) *2
mA
Ω
3000
VO = 1.2 V
Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditionaI (nom) is output current(Ioh) shown in below.
2. Ioh = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA,
Ioh x6 = 13.89 mA (Voh @Z: 0.695 V @50 Ω),
Ioh x2 = 4.63 mA (Voh @Z: 0.232 V @50 Ω)
AC Electrical Characteristics CPU/CPU# Clock (CPU at Timing)
Ta = 0°C to 70°C, VDD = 3.3 V, CL = 2 pF, Rs = 33.2 Ω, Rp = 4
Item
Symbol Min
Typ
Unit Test Conditions Notes
Cycle to cycle jitter
tCCS
tskS
|125|
|1
ps
ps
Note1
CPU Group Skew
(CPU clock out to
CPU clock out)
Rise time
tr
tf
17
700
700
ps
ps
VO = 0.175 V
to 0.525 V
200MHz
200MHz
Fall time
VO = 0.175 V
to 0.525 V
Clock Duty Cycle
45
50
55
%
ns
ns
ns
ns
V
200MHz
CPU clock period(100
CPU clock period(
CPU clock perio
CPU clock period(200)
Cross point(0.7V) voltage
9.99
7.49
5.99
4.99
Vcross
0.25
0.55
200MHz
Note: 1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Apr.25.2003, page 29 of 38
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HD151TS207SS
DC Electrical Characteristics SRC/SRC# Clock
Ta = 0°C to 70°C, VDD = 3.3 V, Iref = 475 Ω
Item
Symbol Min
Typ *1 Max
1.20
Unit
V
Test Conditions
Rp = 49.9 Ω, VDD = 3.3 V
VDD = 3.3 V
Output voltage
Output Current
Output resistance
VO
IO
I(nom)
mA
Ω
3000
VO = 1.2 V
Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions
2. I(nom) is output current(Ioh) shown in below.
Ioh = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA,
Ioh x6 = 13.89 mA (Voh @Z: 0.695V @50 Ω),
Ioh x2 = 4.63 mA (Voh @Z: 0.232V @50 Ω)
AC Electrical Characteristics SRC/SRC# Clock (SRC aTiming)
Ta = 0°C to 70°C, VDD = 3.3 V, CL = 2 pF, Rs = 33.2 Ω, Rp =
Item
Symbol Min
Typ
Unit Test Conditions Notes
Cycle to cycle jitter
Rise time
tCCS
|125|
ps
ps
Note1
tr
175
175
700
700
55
VO = 0.175 V
to 0.525 V
100 MHz
Fall time
tf
ps
VO = 0.175 V
to 0.525 V
100 MHz
100 MHz
Clock Duty Cycle
50
%
ns
ns
V
SRC clock period(100)
SRC clock period(200)
9.99
4.99
Cross point(0.7V) voltage
0.25
0.55
100 MHz
Note: 1. Difference time between two adjoining cycles.
Rev.1.00, Apr.25.2003, page 30 of 38
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HD151TS207SS
DC Electrical Characteristics / 3V66 Buffer (CK409T Type5 Buffer)
Ta = 0°C to 70°C, VDD = 3.3 V
Item
Symbol Min
Typ *1 Max
Unit
V
Test Conditions
IOH = –1 mA, VDD = 3.3 V
IOL = 1 mA, VDD = 3.3 V
VOH = 1.0 V
Output Voltage
VOH
VOL
IOH
3.1
50
mV
mA
mA
Output Current
–33
IOL
30
VOL = 1.95 V
Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
AC Electrical Characteristics / 3V66 Buffer
Ta = 0°C to 70°C, VDD = 3.3 V, CL = 30 pF
Item
Symbol Min
Typ
|250|
0
Max
Test Conditions Notes
Cycle to cycle jitter
tCCS
s
ps
Fig.1
Note1
3V66 Buffer (3V66 (4:0)) tskS
Group Skew
Rising edge
@1.5 V to 1.5 V
Fig.2
Slew rate
tSL
1.0
4.0
V/ns
0.4V to
2.4 V
Clock Period
.998
50
ns
%
Clock Duty Cycle
55
3V66 (4:0) leads
33 MHz PCI
3.5
ns
Note: 1. Difference of cycetween two adjoining cycles.
Rev.1.00, Apr.25.2003, page 31 of 38
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HD151TS207SS
DC Electrical Characteristics / PCI & PCIF Clock (CK409T Type5 Buffer)
Ta = 0°C to 70°C, VDD = 3.3 V
Item
Symbol Min
Typ *1 Max
Unit
V
Test Conditions
IOH = –1 mA, VDD = 3.3 V
IOL = 1 mA, VDD = 3.3 V
VOH = 1.0 V
Output Voltage
VOH
VOL
IOH
3.1
50
mV
mA
mA
Output Current
–33
IOL
30
VOL = 1.95 V
Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
AC Electrical Characteristics / PCI & PCIF Clock
Ta = 0°C to 70°C, VDD = 3.3 V, CL = 30 pF
Item
Symbol Min
Typ
Max
Test Conditions Notes
Cycle to cycle jitter
tCCS
|250|
s
Fig.1
Note1
Rising edge
@1.5V to 1.5 V
Fig.2
PCI Group Skew
tskS
0
ps
Clock Period
Slew rate
ns
0.4 V to
2.4 V
tSL
1.0
4.0
55
V/ns
%
Clock Duty Cycle
50
Note: 1. Difference of cycle time n two adjoining cycles.
Rev.1.00, Apr.25.2003, page 32 of 38
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HD151TS207SS
DC Electrical Characteristics / USB & VCH 48MHz Clock
(CK409T Type3A Buffer)
Ta = 0°C to 70°C, VDD = 3.3 V
Item
Symbol Min
Typ *1 Max
Unit
V
Test Conditions
IOH = –1 mA, VDD = 3.3 V
IOL = 1 mA, VDD = 3.3 V
VOH = 1.0 V
Output Voltage
VOH
VOL
IOH
3.1
50
mV
mA
mA
Output Current
–29
IOL
29
VOL = 1.95 V
Note: 1. For conditions shown as Min or Max, use the appropriate value specified unrecommended
operating conditions.
AC Electrical Characteristics / USB & VCH 48MHz Cloc
Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF
Item
Symbol Min
Typ
Ma
nit Test Conditions Notes
Cycle to cycle jitter
Clock Period
Slew rate
tCCS
|350|
20.83
ps
Fig.1
Note1
ns
tSL
1.0
45
2.0
55
V/ns
0.4 V to
2.4 V
Clock Duty Cycle
%
Note: 1. Difference of cycle time betwadjoining cycles.
Rev.1.00, Apr.25.2003, page 33 of 38
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HD151TS207SS
DC Electrical Characteristics / DOT Clock (CK409T Type3B Buffer)
Ta = 0°C to 70°C, VDD = 3.3 V
Item
Symbol Min
Typ *1 Max
Unit
V
Test Conditions
IOH = –1 mA, VDD = 3.3 V
IOL = 1 mA, VDD = 3.3 V
VOH = 1.0 V
Output Voltage
VOH
VOL
IOH
3.1
50
mV
mA
mA
Output Current
–29
IOL
29
VOL = 1.95 V
Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
AC Electrical Characteristics / DOT Clock
Ta = 0°C to 70°C, VDD = 3.3 V, CL = 10 pF
Item
Symbol Min
Typ
Max
Test Conditions Notes
Cycle to cycle jitter
Clock Period
Slew rate
tCCS
|350|
20.831
s
Fig.1
Note1
ns
tSL
2.0
45
55
V/ns
0.4V to
2.4V
Clock Duty Cycle
%
Note: 1. Difference of cycle time between oining cycles.
Rev.1.00, Apr.25.2003, page 34 of 38
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HD151TS207SS
DC Electrical Characteristics / REF Clock (CK409T Type5 Buffer)
Ta = 0°C to 70°C, VDD = 3.3 V
Item
Symbol Min
Typ *1 Max
Unit
V
Test Conditions
IOH = –1 mA, VDD = 3.3 V
IOL = 1 mA, VDD = 3.3 V
VOH = 1.0 V
Output Voltage
VOH
VOL
IOH
3.1
50
mV
mA
mA
Output Current
–33
IOL
30
VOL = 1.95 V
Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
AC Electrical Characteristics / REF Clock
Ta = 0°C to 70°C, VDD = 3.3 V, CL = 30 pF
Item
Symbol Min
Typ
Max
Test Conditions Notes
Cycle to cycle jitter
Clock Period
Slew rate
tCCS
|1000|
69.841
s
Fig.1
Note1
ns
tSL
1.0
45
55
V/ns
0.4 V to
2.4 V
Clock Duty Cycle
%
Note: 1. Difference of cycle time between oining cycles.
Rev.1.00, Apr.25.2003, page 35 of 38
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HD151TS207SS
Clock Out
tcycle n
tcycle n+1
t CCS = (tcycle n) - (tcycle n+1)
Fig.1 Cycle to Cycle Jitter (3.3V Single Ended Clock Output)
Clock Outx
1.5 V
Clock Outy
1.5 V
tskS
Fig.2 Output Clock Skew (3.3V Ended Clock Output)
Z
LT = ZLC = 50 Ω
RS = 33.2
CPU
LT
TS207
CP
33.2 Ω
LC
RI(ref)
=
RP =
RP =
CL = 2 pF
CL = 2 pF
475 Ω
49.9 Ω
49.9 Ω
Fig.3 Load Circuit for CPU/CPU#
Rev.1.00, Apr.25.2003, page 36 of 38
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HD151TS207SS
Package Dimensions
Unit : mm
18.40
56
29
28
1
35
0.25
0.635
0˚– 8˚
0.5
0.76
0.10(0.004)
Rev.1.00, Apr.25.2003, page 37 of 38
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HD151TS207SS
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Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making soducts better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or e.
Remember to give due consideration to safety when making your cirth appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction
Notes regarding these materials
1. These materials are intended as a reference to assist our cselection of the Renesas Technology Corporation product best suited to the customer's application; they
do not convey any license under any intellectual property ther rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responamage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examplehese materials.
3. All information contained in these materials, incluta, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by RenesCorporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may conaccuracies or typographical errors.
Renesas Technology Corporation asnsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to informby Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the iained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before mision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resuformation contained herein.
5. Renesas Technology Cmiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposuch as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Colophon 0.0
Rev.1.00, Apr.25.2003, page 38 of 38
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