Chapter 1. Preface
Cautions
This document may be, wholly or partially, subject to change without notice.
All rights reserved. Duplication of this document, either in whole or part is prohibited without the written permission of Renesas
Technology Europe Limited.
Trademarks
All brand or product names used in this manual are trademarks or registered trademarks of their respective companies or
organisations.
Copyright
© Renesas Technology Europe Ltd. 2007. All rights reserved.
Website:
Glossary
CPU
HEW
USB
PC
Central Processing Unit
High-performance Embedded Workshop
Universal Serial Bus
RTE
RSO
RSK
NIC
Renesas Technology Europe Ltd.
Renesas Solutions Organisation.
Renesas Starter Kit
Program Counter
Network Interface Controller
E10A
‘E10A for Starter Kits’ Emulator
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Chapter 2.Purpose
This RSK Application Board is an evaluation tool for using Renesas microcontrollers with Ethernet and USB interfaces. It is used in
conjunction with the RSK for the microcontroller to be evaluated.
Features include:
•
•
•
•
Mounting connections to allow RSK to be added to top of board.
Interface to standard RSK ‘Application Interface’ connectors.
Interface to Memory Expansion connectors.
Power connector for +5V (reverse polarity protected), with on-board regulated 3.3V conversion and level translation to
allow operation with RSK boards working at either +5V or +3.3V.
•
•
LAN9118-MT NIC and RJ45 Ethernet connector with integral status LEDs.
ISP1761BE USB Hi-Speed 2.0 Host Controller with:
o
o
1 Host/Slave USB (Mini AB) connector and
2 Host USB (Standard A) connectors.
•
512 kByte Static Ram arranged as 256k x 16 bit words.
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3.2.Board Component functions
The following diagram the shows the functions of the components on the board.
+5V DC
Application Board Interface
JA5
JA1
USB
J4
J5
J3
J1
Mini AB
USB
Std A
JA3
RJ45
J2
JA6
JA2
Memory Extension Interface
Application Board Interface
Figure 3-2: Board Layout
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Chapter 4.User Circuitry
4.1.Fitting the Target RSK to the RSK application board
The board is supplied with 2x 24 way sockets, 2x 26 way sockets and 1 x 50 way socket.
These should be soldered on the underside of the host RSK in JA1, JA2, JA5, JA6 and JA3 positions.
The RSK should be plugged into the equivalent connectors on the RSK LCD application board.
A separate application note is available to explain how to configure the host RSK to enable it to connect to this
application board.
The board is designed to be 5V I/O tolerant. Therefore this board can be connected to an RSK with 5V I/O.
4.2.Network Controller
The network functionality is provided by the SMCS LAN9118-MT non-PCI Ethernet controller.
Refer to the manufacturer’s datasheet for more information on this peripheral.
The Ethernet controller is configured to use a 16 bit data bus. It uses single 16 bit read and write strobes.
Byte or long word accesses are not available for this device.
The chip select used for the network controller is CS1 which is on JA3 pin 27.
Please note the timing. This will require programming the bus controller for the Host RSK.
5ns
A[7:1]
0ns
40ns
CSn,RDn
35ns
0ns
Data
Valid
Figure 4-1: Ethernet controller read timing
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5ns
A[7:1]
5ns
35ns
CSn,WRn
10ns
Valid
5ns
Data
Figure 4-2: Ethernet controller write timing
The Ethernet controller can drive two interrupts.
IRQ0 is the IRQ from the Ethernet controller.
IRQ2 is the PME output from the Ethernet controller. PME interrupts can be enabled on the IRQ pin, so this can
be disabled for host RSKs with fewer interrupt lines, if the PME interrupt is required.
Both interrupts are pulled high to 3.3V by 1K resistors.
4.3.USB Controller
The Universal Serial Bus functionality is provided by the Philips ISP1761 controller.
Refer to the manufacturer’s datasheet for more information on this peripheral.
This peripheral provides 2 Host type A and one On the Go Host/Peripheral mini AB type USB controller.
The ISP1761 controller is configured to use a 16 bit data bus. It uses single 16 bit read and write strobes.
Byte or long word accesses are not available for this device.
The chip select used for the USB controller is CS2 which is on JA3 pin 28.
Please note the timing. This will require programming the bus controller for the Host RSK.
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5ns
A[17:1]
5ns
40ns
CSn,RDn
35ns
0ns
Data
Valid
Figure 4-3: USB controller read timing
5ns
A[17:1]
5ns
20ns
CSn,WRn
8ns
5ns
Data
Valid
Figure 4-4: USB controller write timing
The ISP1761 controller can drive two interrupts.
IRQ1 is the HC_IRQ from the ISP1761 controller.
IRQ3 is the DC_IRQ output from the ISP1761 controller. DC_IRQ interrupts can be enabled on the HC_IRQ pin,
so this can be disabled for host RSKs with fewer interrupt lines, if the DC_IRQ interrupt is required.
Both interrupts are pulled high to 3.3V by 1K resistors.
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4.4.SRAM
The board is provided with 512 kilobytes of static RAM arranged as 256k x 16 bit words.
This RAM is byte addressable, provided the host RSK supports this.
The chip select used for the RAM is CS3 which is on JA3 pin 45.
Please note the timing. This will require programming the bus controller for the Host RSK.
5ns
A[18:1]
5ns
20ns
CSn,RDn
15ns
0ns
Data
Valid
Figure 4-5: SRAM read timing
5ns
A[18:1]
5ns
20ns
CSn,WRn
8ns
5ns
Data
Valid
Figure 4-6: SRAM write timing
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4.5.Option Links
Table 4-1 below describes the function of the option links contained on this CPU board. The default configuration is indicated by BOLD
text.
Option Link Settings
Reference
Function
3V power select
Fitted
Alternative (Removed)
Board_3V from RSK
WR1n not connected
WR1n not connected
WR0n not connected
WR0n not connected
Related To
R2
R7
R8
R9
R10
Regulator drives Board_3V3
High Byte writes from WR1n
High Byte writes from WR1n
Low Byte writes from WR0n
Low Byte writes from WR0n
Write Strobe Select
Write Strobe Select
Write Strobe Select
Write Strobe Select
R8, R9, R10
R7, R9, R10
R7, R8, R10
R7, R8, R9
Table 4-1: JA1 Option Link Settings
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Chapter 5.Headers
5.1.Application Headers
This information is supplied for reference. Only pins marked are connected on this board.
These connections are not level translated.
JA1
Pin Generic Header Name
CPU board
Pin
Header Name
CPU board
Signal Name
GROUND
GROUND
AVss
Signal Name
1
Regulated Supply 1
Regulated Supply 2
Analogue Supply
5V
2
Regulated Supply 1
Regulated Supply 2
Analogue Supply
ADTRG
3
3V3
4
5
AVcc
AVref
AD0
6
7
Analogue Reference
8
ADTRG
AD1
9
ADC0
ADC2
DAC0
IOPort
IOPort
IOPort
IOPort
I0
I2
10
12
14
16
18
20
22
24
26
ADC1
ADC3
DAC1
IOPort
IOPort
IOPort
IOPort
I1
I3
11
13
15
17
19
21
23
25
AD2
AD3
DAC0
IO_0
IO_2
IO_4
IO_6
DAC1
IO_1
IO_3
IO_5
IO_7
Open drain IRQAEC IRQ3
I²C Bus
IIC_SDA
I²C Bus - (3rd pin)
I²C Bus
IIC_EX
IIC_SCL
Table 5-1: JA1 Standard Generic Header
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JA2
Pin
Pin Generic Header Name
CPU board
Header Name
CPU board
Signal Name
EXTAL
Vss1
Signal Name
1
3
5
7
9
Open drain
RESn
2
4
6
8
External Clock Input
Regulated Supply 1
Serial Port
Open drain
NMIn
Open drain output
WDT_OVF
IRQ0
SCIaTX
SCIaRX
SCIaCK
CTS/RTS
MO_Un
MO_Vn
MO_Wn
TMR1
Open drain
Open drain
WUP
Serial Port
IRQ1
10 Serial Port
12 Serial Port Handshake
14 Motor control
16 Motor control
18 Motor control
20 Output
11 Up/down
13 Motor control
15 Motor control
17 Motor control
19 Output
MO_UD
MO_Up
MO_Vp
MO_Wp
TMR0
TRIGa
IRQ2
21 Input
22 Input
TRIGb
23 Open drain
25 SPARE
24 Tristate Control
26 SPARE
TRSTn
-
-
Table 5-2: JA2 Standard Generic Header
JA5
Pin Generic Header Name
CPU board
Pin
Header Name
CPU board
Signal Name
Signal Name
1
3
ADC4
ADC6
CAN
CAN
I4
I6
AD4
2
ADC5
ADC7
CAN
CAN
I5
I7
AD5
AD6
4
AD7
5
CAN1TX
CAN2TX
6
CAN1RX
CAN2RX
7
8
9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10
12
14
16
18
20
22
24
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
11
13
15
17
19
21
23
Table 5-3: JA5 Optional Generic Header
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JA6
Pin
Generic Header Name
CPU board Pin
Signal
Header Name
CPU board
Signal Name
Name
1
DMA
DREQ
2
DMA
DACK
3
DMA
TEND
4
Standby (Open drain)
Host Serial SCIdRX
Serial Port
STBYn
5
Host Serial
Serial Port
SCIdTX
RS232TX
SCIbRX
SCIcTX
SCIcCK
6
RS232RX
SCIbTX
SCIbCK
SCIcRX
7
8
9
Serial Port Synchronous
Serial Port Synchronous
Reserved
10
12
14
16
18
20
22
24
Serial Port
11
13
15
17
19
21
23
Serial Port
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Synchronous
Reserved
Reserved
Reserved
Reserved
Reserved
Table 5-4: JA6 Optional Generic Header
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These connections support 5 to 3.3V level translation.
JA3
Pin
Pin Generic Header Name
Signal Name
A(0)
Header Name
Signal Name
A(1)
1
A(0)
2
A(1)
3
A(2)
A(2)
4
A(3)
A(3)
5
A(4)
A(4)
6
A(5)
A(5)
7
A(6)
A(6)
8
A(7)
A(7)
9
A(8)
A(8)
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
A(9)
A(9)
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
A(10)
A(12)
A(14)
D(0)
A(10)
A(12)
A(14)
D(0)
A(11)
A(13)
A(15)
D(1)
A(11)
A(13)
A(15)
D(1)
D(2)
D(2)
D(3)
D(3)
D(4)
D(4)
D(5)
D(5)
D(6)
D(6)
D(7)
D(7)
RDn
RDn
WRn
CS2n
D(9)
WRn
CS2n
D(9)
CS1n
D(8)
CS1n
D(8)
D(10)
D(12)
D(14)
A(16)
A(18)
A(20)
A(22)
CS3n
WR1n
CASn
D(10)
D(12)
D(14)
A(16)
A(18)
A(20)
A(22)
CS3n
WR1n
CASn
D(11)
D(13)
D(15)
A(17)
A(19)
A(21)
D(11)
D(13)
D(15)
A(17)
A(19)
A(21)
SDCLK
ALE
SDCLK
ALE
WR0n
RASn
WR0n
RASn
Table 5-5: JA3 Memory Expansion connector
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Chapter 7.Additional Information
For details on how to use High-performance Embedded Workshop (HEW), refer to the HEW manual available on the CD or from the web
site.
Online technical support and information is available at: http://www.renesas.com/renesas_starter_kits
Technical Contact Details
Europe:
Japan:
General information on Renesas Microcontrollers can be found on the Renesas website at: http://www.renesas.com/
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Renesas Starter Kit Ethernet & USB Application Board
User's Manual
Publication Date
Published by:
17.Jan.2008
Renesas Technology Europe Ltd.
Duke’s Meadow, Millboard Road, Bourne End
Buckinghamshire SL8 5FH, United Kingdom
©2007 Renesas Technology Europe and Renesas Solutions Corp., All Rights Reserved.
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Renesas Starter Ethernet & USB
Application Board User's Manual
Renesas Technology Europe Ltd.
Duke’s Meadow, Millboard Road, Bourne End
Buckinghamshire SL8 5FH, United Kingdom
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