Philips Handheld TV TDA8303 User Manual

INTEGRATED CIRCUITS  
DATA SHEET  
TDA8303  
TDA8303A  
Small signal combination IC for  
black/white TV  
July 1992  
Preliminary specification  
File under Integrated Circuits, IC02  
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
QUICK REFERENCE DATA  
SYMBOL  
Supply  
PARAMETER  
CONDITIONS MIN.  
TYP. MAX. UNIT  
VP  
IP  
positive supply voltage (pin 7)  
supply current (pin 7)  
9.5  
90  
12  
13.2  
160  
9
V
125  
6.5  
mA  
mA  
Istart  
start current (pin 11)  
note 1  
Video  
V8-9(RMS)  
IF sensitivity (RMS value)  
at 38.9 MHz;  
note 2  
20  
40  
65  
µV  
G8-9  
S/N  
IF gain control range  
signal-to-noise ratio  
74  
57  
dB  
dB  
input signal =  
10 mV  
V18(p-p)  
AFC output voltage swing  
(peak-to-peak value)  
10.5  
11.5  
V
Sound  
V12(RMS)  
AMS  
AF output signal (RMS value)  
AM suppression  
note 3  
400  
600  
58  
800  
mV  
dB  
%
at VI = 50 mV  
THD  
total harmonic distortion  
0.5  
Sync  
V25  
I27  
required sync pulse amplitude  
required input current during flyback pulse  
coincidence detector output voltage  
in synchronized condition  
note 4  
200  
0.1  
2
mV  
mA  
V22  
2.9  
9.7  
1.5  
3.3  
1.2  
3.7  
V
V
V
V
in no signal condition  
V22  
vertical feedback for DC voltage  
V22(p-p)  
vertical feedback for AC voltage  
(peak-to-peak value)  
Notes to the quick reference data  
1. Pin 11 has a double function. When during switch-on a current of 9 mA is supplied to this pin, it is used to start the  
horizontal oscillator. The main supply can then be obtained from the horizontal deflection stage. When no current is  
supplied to this pin it can be used as a volume control.  
2. On set AGC.  
3. The output signal is measured at f = 7.5 kHz and maximum volume control.  
4. The minimum value is obtained by connecting a 1.8 kresistor and a 470 nF capacitor in series between the video  
output and pin 25. The slicing level can be varied by changing the value of this resistor (higher resistance value  
results in a larger value of the minimum sync pulse amplitude). The slicing level is independent of the video  
information.  
July 1992  
3
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Philips Semiconductors  
Preliminary specification  
Small signal combination IC for black/white  
TV  
TDA8303  
TDA8303A  
July 1992  
4
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Philips Semiconductors  
Preliminary specification  
Small signal combination IC for black/white  
TV  
TDA8303  
TDA8303A  
PINNING  
PIN  
Sound circuit  
The sound quality of the TDA8303/TDA8303A compared  
with the predecessors has been improved at weak signal  
conditions. The improvement has been achieved by the  
new IF amplifier which is less sensitive for radiation from  
the sound IF amplifier and by change of the ground and  
supply connections in the IC. When out-of-sync condition  
is detected by the coincidence detector the sound output  
is muted. When no mute is required the minimum voltage  
level on pin 22 should be clamped to a high level of 5 V.  
At this level the gating of the AGC is switched off and the  
phase 1 detector has a high output current for reliable  
catching of a new transmitter.  
DESCRIPTION  
1
AGC take-over  
2
vertical ramp generator  
vertical drive  
3
4
vertical feedback  
5
tuner AGC  
6
ground  
7
supply voltage input  
video IF input  
8
9
video IF input  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
IF AGC  
Vertical synchronization  
volume control/start horizontal oscillator  
audio output  
The TDA8303/TDA8303A embodies a synchronized  
divider system for generating the vertical sawtooth at pin 2  
having several advantages and features such as:  
sound demodulator  
sound IF decoupling  
sound IF input  
The vertical frequency is alignment free. The divider  
automatically adapts to a vertical frequency of 50 Hz or  
60 Hz including automatic amplitude correction and its  
operating modes offer maximum  
ground (for some critical parts)  
video amplifier output  
AFC output  
interference/disturbance protection.  
A discriminator-window checks the accuracy of the  
vertical trigger pulse. Internally clock pulses are  
generated by doubling the line frequency. The divider  
operates in the 60 Hz mode when the trigger pulse  
appears before count 576, otherwise the 50 Hz mode  
will be active.  
AFC S/H, AFC switch  
video demodulator tuned circuit  
video demodulator tuned circuit  
coincidence detector  
horizontal oscillator  
phase 1 detector  
The divider system operates with two different reset  
windows for maximum interference/disturbance  
protection. The windows are activated via an up/down  
counter. The counter increases its counter-value by 1 for  
each time the separated vertical sync pulse appears  
within the selected window, otherwise the counter value  
is decreased by 1.  
sync separator input  
horizontal drive output  
horizontal flyback input  
phase 2 detector  
AGC circuit  
Modes of operation  
The AGC circuit of the TDA8303/TDA8303A is a top-sync  
detector. The video signal coming from the video amplifier  
passes a 2nd order low-pass filter before it is compared  
with an internal reference level. The comparator stage is  
gated when the horizontal oscillator is synchronized with  
the video signal, such that interference pulses outside the  
gating time have no influence on the gain control.  
Large search window: divider ratio between 488 and 576.  
This mode is valid for the following conditions:  
Divider is looking for a new transmitter  
Divider ratio found does not comply with the narrow  
window specification limits  
Up/down counter value of the divider system, operating  
in the narrow window mode, drops below count 10  
July 1992  
5
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
Narrow window mode: divider ratio between 522 and 528  
(60 Hz); or 622 and 628 (50 Hz).  
ensures a stable display which is not disturbed by the  
noise in the video signal. When the circuit is not  
synchronized the time constant is fast and not gated to  
ensure a short catching time.  
The divider system switches over to narrow window  
mode when the up/down counter has reached his  
maximum value of 15 approved vertical sync pulses  
Combination of DC volume control and start-up  
feature  
When the divider operates in the narrow window mode  
and a vertical sync pulse is missing within the window,  
the divider is reset at the end of that window and the  
counter value is decreased by 1  
Pin 11 of the IC can be used as a DC volume control or as  
a start-up feature of the horizontal oscillator/output circuit  
dependent on the application.  
Volume control is achieved by connecting a 4.7 kΩ  
potentiometer or a DC voltage of 0 to 3 V to pin 11. When  
a current of 9 mA is supplied to pin 11 the volume control  
is set to a fixed output signal level and the circuit will  
generate drive pulses for the horizontal deflection and the  
main supply can be derived from the deflection.  
At a counter value below 10 the divider system switches  
over to the large window mode  
The divider system also generates an anti-top-flutter  
pulse which inhibits the phase 1 detector during the  
vertical sync pulse. The pulse width is dependent on the  
divider mode. For the large window mode the start is  
generated at the reset of the divider. In the narrow  
window mode the anti-top-flutter pulse starts at the  
beginning of the first equalizing pulse. The  
Application when external video signals require  
synchronization  
anti-top-flutter pulse ends at count 10 for the 50 Hz  
mode and count 12 for the 60 Hz mode  
The input to the sync separator is externally available via  
pin 25. For normal application the video output signal at pin  
17 is AC-coupled to the sync separator input. It is possible  
to interrupt this connection and drive the sync separator  
from other sources.  
When external signals are applied to the sync separator  
the connections between the two parts must be  
interrupted. This can be achieved by connecting pin 22 to  
ground, which results in the following conditions:  
VCR switch  
An extra time constant switch in the horizontal phase  
detector makes an external VCR switch redundant. The  
time constant is automatically switched depending on the  
signal strength of the IF input (pins 8/9) and the  
coincidence detector.  
When a strong signal is detected (V8/9 > 2.2 mV) and the  
circuit is synchronized the time constant of the phase  
detector is optimum for VCR playback, a fast time constant  
during the vertical retrace to correct head errors of the  
VCR and during scan a sufficient time constant to correct  
fluctuations of the horizontal sync  
AGC detector is not gated  
Mute circuit not active, sound channel remains switched  
on  
Phase detector 1 has an optimum time constant for  
external video sources and is not gated  
During weak signal and synchronized conditions the time  
constant is enlarged and the phase detector is gated. This  
LIMITING VALUES  
In accordance with the Absolute Maximum System (IEC 134)  
SYMBOL  
PARAMETER  
MIN.  
MAX.  
13.2  
UNIT  
VP  
supply voltage (pin 7)  
total power dissipation  
V
Ptot  
Tstg  
Tamb  
2.3  
W
storage temperature range  
55  
25  
+150  
+65  
°C  
°C  
operating ambient temperature range  
July 1992  
6
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
CHARACTERISTICS  
VP = 12 V;Tamb = 25 °C; carrier 38.9 MHz negative modulation, unless otherwise specified  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Supply (pin 7)  
VP  
IP  
supply voltage range  
supply current  
9.5  
12  
13.2  
160  
9
V
no input  
note 1  
90  
9.5  
125  
6.5  
mA  
mA  
V
I11  
start current (pin 11)  
V11  
V11  
start voltage horizontal oscillator  
start protection level  
16.5  
I11 = 12 mA  
V
IF Amplifier (pins 8 and 9)  
V8-9(RMS) input sensitivity (RMS value)  
at 38.9 MHz;  
note 2  
25  
25  
40  
40  
65  
65  
µV  
V8-9(RMS)  
input sensitivity (RMS value)  
at 45.75 MHz;  
notes 2 and 25  
µV  
R8-9  
C8-9  
G8-9  
V17  
differential input resistance  
differential input capacitance  
gain control range  
note 3  
note 3  
1300  
5
pF  
dB  
dB  
74  
1
output signal expansion for 46 dB input signal note 4  
variation  
V8-9  
maximum input signal  
100  
170  
mV  
Video Amplifier (note 5)  
V17  
V17  
V17  
V17  
V17  
Z17  
I17  
zero signal output level  
note 6  
note 7  
5.4  
2.5  
2.65  
5.7  
3.8  
25  
V
peak sync level  
2.3  
2.3  
2.7  
3.0  
V
video output signal amplitude  
white spot threshold level  
white spot insertion level  
video output impedance  
V
V
V
mA  
internal bias current of npn emitter follower  
output transistor  
1.4  
1.8  
Isource  
B
maximum source current (pin 17)  
bandwidth of demodulated output signal  
differential gain  
10  
5
7
4
2
2
8
5
5
mA  
MHz  
%
G17  
ϕ
note 8  
note 8  
note 9  
note 10  
differential phase  
deg.  
%
NL  
video non linearity  
intermodulation  
1.1 MHz; blue  
50  
50  
55  
55  
60  
60  
65  
65  
dB  
dB  
dB  
dB  
1.1 MHz; yellow  
3.3 MHz; blue  
3.3 MHz; yellow  
July 1992  
7
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
SYMBOL  
PARAMETER  
signal-to-noise ratio  
CONDITIONS  
MIN.  
50  
TYP.  
57  
MAX.  
UNIT  
dB  
S/N  
10 mV input  
signal  
S/N  
signal-to-noise ratio  
end of gain  
control range  
50  
62  
dB  
V17  
V17  
residual carrier signal  
2
2
10  
10  
mV  
mV  
residual 2nd harmonic of carrier signal  
Tuner AGC  
V8-9(RMS)  
minimum starting point for tuner takeover  
0.2  
mV  
mV  
(RMS value)  
V8-9(RMS)  
maximum starting point for tuner takeover  
(RMS value)  
100  
150  
I5  
maximum tuner AGC output swing  
output saturation voltage  
V5 = 3 V  
4
2
300  
1
mA  
mV  
µA  
dB  
V
V5  
IL  
I5 = 2 mA  
0.2  
leakage current (pin 5)  
VI  
V1  
input signal variation complete tuner control  
minimum voltage tuner takeover  
4
1
AFC circuit  
I19  
IO  
AFC sample-and-hold switch-off current  
output current (pin 19)  
output leakage current (pin 19)  
AFC output voltage swing  
available output current  
control slope  
0.1  
0.1  
0.3  
2
mA  
V19 = 0 V  
mA  
ILO  
V18  
I18  
µA  
V
notes 18 and 19 10.5  
11.5  
6.5  
0.2  
mA  
5.5  
100  
6
mV/kHz  
VO  
RO  
V18  
output voltage (pin 18)  
AFC output resistance  
output voltage swing  
AFC off  
V
40  
11  
80  
2  
kΩ  
V
notes 25 and 26  
notes 25 and 26  
notes 25 and 26  
control slope  
mV/kHz  
V
V18  
output voltage shift with respect to  
VI = 10 mV(RMS)  
July 1992  
8
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Sound circuit (note 12)  
V15  
input limiting voltage  
input resistance  
VO(max) = 3 dB  
400  
800  
µV  
kΩ  
pF  
R15  
2.6  
6
C15  
input capacitance  
AMS  
V12(RMS)  
V12(RMS)  
AM suppression  
note 13  
53  
58  
800  
1500  
dB  
mV  
mV  
AF output signal (RMS value)  
note 14  
400  
500  
600  
900  
AF output signal when pin 11 is used as a  
starting pin or connected to VP  
(RMS value)  
f = 50 kHz  
Z12  
AF output impedance  
total harmonic distortion  
ripple rejection  
25  
0.5  
35  
100  
2
%
dB  
THD  
RR  
note 15  
volume control  
20 dB;  
fk = 100 Hz  
V12  
V12  
output voltage when muted  
2.5  
0.5  
V
output level shift due to muting  
volume control  
20 dB  
dB  
S/N  
V11  
I11  
signal-to-noise ratio  
note 16  
47  
6
dB  
V
voltage with pin 11 disconnected  
current with pin 11 short-circuited to ground  
1
mA  
dB  
V12  
temperature dependence of the output signal Tamb = 20 to 65  
amplitude  
2.5  
°C;  
30 dB volume  
control and  
voltage of pin 11  
fixed;  
note 17  
Volume control (note 17; see Fig.8)  
R11  
external control resistor  
note 17  
60  
4.7  
66  
kΩ  
dB  
OSS  
suppression of output signal during mute  
condition  
Horizontal synchronization circuit (see Fig.9)  
SYNC SEPARATOR  
V25  
I25  
required sync pulse amplitude  
input current (pin 25)  
note 20  
200  
750  
8
mV  
µA  
V25 > 5 V  
V25 = 0 V  
10  
mA  
FIRST CONTROL LOOP  
±∆f  
±∆f  
PLL holding range  
600  
1500  
1500  
2000  
Hz  
Hz  
PLL catching range  
control sensitivity to oscillator  
note 21  
see Fig.10  
2.2  
V8-9  
IF input signal at which the time constant is  
switched (RMS value)  
strong-to-weak  
mV  
July 1992  
9
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
SECOND CONTROL LOOP (POSITIVE EDGE)  
control sensitivity  
control range  
note 22  
100  
δtd  
δto  
-------  
td  
25  
µs  
PHASE ADJUSTMENT (VIA SECOND CONTROL LOOP)  
control sensitivity  
25  
µA/µs  
µs  
α
maximum allowed phase shift  
±2  
HORIZONTAL OSCILLATOR  
ffr  
free running frequency  
R = 34.3 k;  
C = 2.7 nF  
15625  
Hz  
f  
ffr  
spread with fixed external components  
4
2
%
%
frequency variations with supply voltage from  
9.5 to 13.2 V  
fT  
ffr  
frequency variation with temperature  
note 25  
note 25  
1.6  
10  
Hz/°C  
%
maximum frequency deviation at start of  
horizontal output  
f  
frequency variation when only noise is  
received  
500  
Hz  
HORIZONTAL OUTPUT (PIN 26; OPEN COLLECTOR)  
V26  
VOL  
Isink  
output limiting voltage  
LOW level output voltage  
maximum sink current  
duty factor of output signal  
rise time of output pulse  
fall time of output pulse  
10  
0.2  
46  
260  
100  
16.5  
0.5  
V
Isink = 10 mA  
V
mA  
%
ns  
ns  
tr  
tf  
HORIZONTAL FLYBACK INPUT (PIN 27)  
I27  
required input current during flyback pulse  
0.01  
1.0  
mA  
COINCIDENCE DETECTOR  
V22  
V22  
V22  
voltage for in-sync condition  
9.8  
1.5  
6.7  
V
V
V
voltage for no-sync condition  
no signal  
switching level to the phase detector from fast  
to slow  
6.2  
7.2  
V22  
V22  
hysteresis slow to fast  
2.5  
0.6  
2.8  
3.1  
V
V
switching level to activate the mute function  
(transmitter identification)  
V22  
td  
hysteresis mute function  
2
300  
V
delay of mute release after transmitter  
insertion  
µs  
allowable load on pin 22  
external video mode  
current at pin 22  
10  
µA  
V
V22  
I22  
0.7  
0.8  
V22 = 0 V  
mA  
July 1992  
10  
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Vertical circuit (note 24)  
VERTICAL RAMP GENERATOR  
I2  
input current during scan  
2
µA  
mA  
V
I2  
discharge current during retrace  
0.8  
1.9  
32  
V2(pp)  
t
sawtooth amplitude (peak-to-peak value)  
interlace timing of the internal pulses  
30  
34  
µs  
VERTICAL OUTPUT  
I3  
available output current  
maximum available output voltage  
V3 = 4 V  
4.4  
5
3
mA  
V
V3  
I3 = 0.1 mA  
VERTICAL FEEDBACK INPUT  
V4  
DC input voltage  
2.9  
3.3  
1
3.7  
12  
V
V4(pp)  
I4  
AC input voltage (peak-to-peak value)  
input current  
V
3
µA  
%
%
%
tp  
internal pre-correction to sawtooth  
deviation amplitude  
50/60 Hz  
4
temperature dependency of the amplitude  
Tamb = 20 to  
65 °C  
2
Notes to the characteristics  
1. Pin 11 has a double function. When during switch-on a current of 9 mA is supplied to this pin, it is used to start the  
horizontal oscillator. The main supply can then be obtained from the horizontal deflection stage. When no current is  
supplied to this pin it can be used as a volume control.  
2. On set AGC.  
3. The input impedance has been chosen such that a SAW filter can be employed.  
4. Measured with 0 dB = 450 µV.  
5. Measured at 10 mV RMS top sync input signal.  
6. Projected zero point; i.e. with switched demodulator.  
7. White 10% of the top sync amplitude.  
8. Measured according to the test line illustrated by Fig.2. The differential gain is expressed as a percentage of the  
difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking  
level. The differential phase is defined as the difference in degrees between the largest and smallest phase angle.  
The differential gain and phase are measured with a DSB signal.  
9. This figure is valid for the complete video signal amplitude (peak white-to-black); see Fig.3. The nonlinearity is  
expressed as a percentage of the maximum deviation of a luminance step from the mean step, with respect to the  
mean step.  
10. The test setup and input conditions are illustrated by Fig.4. The figures are measured at an input signal of 10 mV  
RMS.  
11. Measured with a source impedance of 75Ω.  
VO black-to-white  
The signal-to-noise ratio = 20 log-----------------------------------------------------------  
Vn (RMS) at B = 5 MHz  
12. The sound circuit is measured (unless otherwise specified) with an input signal of V15 of 50 mV RMS, a carrier  
frequency of 5.5 MHz at a f of 27.5 kHz. The QL of the demodulator tuned circuit is 16 and the volume control is  
July 1992  
11  
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
connected to the supply. The reference circuit must be tuned in such a way that the output is symmetrical clipping at  
maximum volume.  
13. The test set-up is illustrated by Fig.6. The AM rejection curve (typical) is illustrated by Fig.7.  
14. The output signal is measured at a f = 7.5 kHz and maximum volume control.  
15. The demodulator tuned circuit must be tuned at minimum distortion.  
16. Weighted noise, measured in accordance with CCIR 468.  
17. See also note 1. The volume can be controlled by using a potentiometer connected to ground (value 4.7 k) or by  
means of a variable direct voltage. In the latter event the relatively low input impedance must be taken into account.  
18. The AFC control voltage is obtained by multiplying the IF output signal (which is also used to drive the synchronous  
demodulator) with a reference carrier. This reference carrier is obtained from the demodulator tuned circuit via a 90  
degree phase shift network.The IF output signal has an asymmetrical frequency spectrum with respect to the carrier  
frequency. To avoid problems due to this asymmetrical signal the AFC circuit is followed by a sample-and-hold circuit  
which samples during the sync level. As a result the AFC output voltage contains no video information. The specified  
control slope decreases when the AFC output is loaded with two resistors between the voltage supply and ground.  
19. At very weak input signals the drive signal for the AFC circuit will have a high noise content. This noise input has an  
asymmetrical frequency spectrum which will cause an offset of the AFC output voltage. The characteristics given for  
weak signals are measured with a SAW filter (OFW 1956) connected in front of the IC input signal such that the input  
signal of the IC is 150 µV RMS.  
20. The minimum value is obtained by connecting a 1.8 kresistor between pins 17 and 25. The slicing level can be  
varied by changing the value of this resistor (higher resistor value results in larger value of the minimum sync pulse  
amplitude). The slicing level is independent of the video information.  
21. Frequency control is obtained by supplying a correction current to the oscillator RC network via a resistor connected  
between the phase 1 detector output and the oscillator network. The oscillator can be adjusted to the correct  
frequency by short circuiting the sync separator bias network (pin 25) to the voltage supply. To avoid the need of a  
VCR switch the time constant of the phase detector at strong input signals is sufficiently short to obtain a stable  
picture during VCR playback. During the vertical retrace period the time constant is even shorter so that the  
headerrors of the VCR are compensated at the beginning of scan. During conditions of weak signal (information  
derived from the AGC circuit) the time constant is increased to obtain a better noise immunity.  
22. This figure is valid for an external load impedance of 82 kbetween pin 28 and the phase adjustment potentiometer.  
23. The functions in-sync/out-of-sync and transmitter identification have been combined on pin 22. The capacitor is  
charged during the sync pulse and discharged during the time difference between gating (6.5 µs) and the sync pulse.  
24. The vertical scan is synchronized by means of a divider system. Therefore no frequency adjustment is required for  
the ramp generator. The divider detects whether the incoming signal has a vertical frequency of 50 or 60 Hz and  
corrects the vertical amplitude.  
25. These figures are based on test samples.  
26. Measured at an input signal amplitude of 150 µV RMS (pin 18).  
July 1992  
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
MLA667  
100%  
95%  
17.5%  
30%  
Fig.2 Video output signal.  
MBC211  
100%  
86%  
72%  
58%  
44%  
30%  
µs  
10 12  
22 26  
32 36 40 44 48 52 56 60 64  
Fig.3 EBU test signal waveform (line 330).  
13  
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
PC  
38.9 MHz  
SC  
33.4 MHz  
TEST  
CIRCUIT  
SPECTRUM  
ANALYZER  
Σ
ATTENUATOR  
gain setting adjusted  
for blue or yellow  
CC  
34.5 MHz  
MLA666  
3.2 dB  
10 dB  
13.2 dB  
13.2 dB  
30 dB  
30 dB  
SC CC  
PC  
SC CC  
PC  
MBC213  
BLUE  
YELLOW  
Input signal conditions  
SC = Sound carrier  
CC = Chrominance carrier  
PC = Picture carrier  
All with respect to top sync level  
VO at 4.4 MHz  
Value at 1.1 MHz : 20 log -------------------------------------- + 3.6 dB  
VO at 1.1 MHz  
VO at 4.4 MHz  
Value at 3.3 MHz : 20 log --------------------------------------  
VO at 3.3 MHz  
Fig.4 Test set-up intermodulation.  
14  
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
Fig.5 Signal-to-noise ratio as a function of the  
input voltage (0 dB = 100 mV).  
Fig.6 Test set-up AM suppression.  
July 1992  
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Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
Fig.7 AM suppression.  
Fig.8 Volume control characteristics.  
July 1992  
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Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
Fig.9 Timing diagram.  
July 1992  
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Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
Table 1 Switching levels coincidence detector  
CONTROL SENSITIVITY  
HORIZONTAL OSCILLATOR (kHz/µS)  
CONDITION  
V22  
T2 - T1  
T3 = SCAN  
V22 > 6.7 V  
and  
strong signal  
weak signal  
11.3  
1.3  
7.6  
1.3  
1 < V22 < 5.7 V  
and  
strong signal  
weak signal  
V22 < 0.7  
11.3  
11.3  
11.3  
7.6  
7.6  
7.6  
Fig.10 Switching levels coincidence detector.  
Fig.11 Anti-top-flutter pulse.  
18  
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Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
Fig.12 Application diagram.  
July 1992  
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Philips Semiconductors  
Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
PACKAGE OUTLINE  
handbook, full pagewidth  
DIP28: plastic dual in-line package; 28 leads (600 mil)  
SOT117-1  
D
M
E
A
2
A
L
A
1
c
e
w M  
Z
b
1
(e )  
1
b
M
H
28  
15  
pin 1 index  
E
1
14  
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
(1)  
A
max.  
A
A
Z
(1)  
(1)  
1
2
UNIT  
mm  
b
b
c
D
E
e
e
L
M
M
w
1
1
E
H
min.  
max.  
max.  
1.7  
1.3  
0.53  
0.38  
0.32  
0.23  
36.0  
35.0  
14.1  
13.7  
3.9  
3.4  
15.80  
15.24  
17.15  
15.90  
5.1  
0.51  
4.0  
2.54  
0.10  
15.24  
0.60  
0.25  
0.01  
1.7  
0.013  
0.009  
0.066  
0.051  
0.020  
0.014  
1.41  
1.34  
0.56  
0.54  
0.15  
0.13  
0.62  
0.60  
0.68  
0.63  
inches  
0.20  
0.020  
0.16  
0.067  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
92-11-17  
95-01-14  
SOT117-1  
051G05  
MO-015AH  
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Preliminary specification  
TDA8303  
TDA8303A  
Small signal combination IC for black/white TV  
SOLDERING  
Introduction  
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and  
surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for  
surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often  
used.  
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our  
“IC Package Databook” (order code 9398 652 90011).  
Soldering by dipping or by wave  
The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the  
joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.  
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the  
specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may  
be necessary immediately after soldering to keep the temperature within the permissible limit.  
Repairing soldered joints  
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more  
than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to  
10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.  
DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
July 1992  
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