National Instruments Switch PC DIO 24 PnP User Manual

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PC-DIO-24/PnP  
User Manual  
24-bit Digital I/O Board for ISA Computers  
February 1998 Edition  
Part Number 320288C-01  
© Copyright 1989, 1998 National Instruments Corporation. All rights reserved.  
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Important Information  
Warranty  
The PC-DIO-24 and PC-DIO-24PnP boards are warranted against defects in materials and workmanship for a period  
of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at  
its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes  
parts and labor.  
The media on which you receive National Instruments software are warranted not to fail to execute programming  
instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced  
by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do  
not execute programming instructions if National Instruments receives notice of such defects during the warranty  
period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.  
A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside  
of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping  
costs of returning to the owner parts which are covered by warranty.  
National Instruments believes that the information in this manual is accurate. The document has been carefully  
reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves  
the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The  
reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for  
any damages arising out of or related to this document or the information contained in it.  
EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND  
SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  
CUSTOMERS RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL  
INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER. NATIONAL INSTRUMENTS  
WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR  
CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF. This limitation of the liability of National  
Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. Any action  
against National Instruments must be brought within one year after the cause of action accrues. National Instruments  
shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided  
herein does not cover damages, defects, malfunctions, or service failures caused by owner’s failure to follow the  
National Instruments installation, operation, or maintenance instructions; owner’s modification of the product;  
owner’s abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or  
other events outside reasonable control.  
Copyright  
Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical,  
including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part,  
without the prior written consent of National Instruments Corporation.  
Trademarks  
TM  
TM  
TM  
TM  
TM  
TM  
TM  
BridgeVIEW , ComponentWorks , CVI , LabVIEW , Measure , NI-DAQ , and VirtualBench  
trademarks of National Instruments Corporation.  
are  
Product and company names referred to in this document are trademarks or trade names of their respective companies.  
WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS  
National Instruments products are not designed with components and testing intended to ensure a level of reliability  
suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving  
medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the  
part of the user or application designer. Any use or application of National Instruments products for or involving  
medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional  
medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury  
or death should always continue to be used when National Instruments products are being used. National Instruments  
products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to  
monitor or safeguard human health and safety in medical or clinical treatment.  
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FCC/DOC Radio Frequency Interference  
Class A Compliance  
This equipment generates and uses radio frequency energy and, if not installed and used in strict  
accordance with the instructions in this manual, may cause interference to radio and television  
reception. Classification requirements are the same for the Federal Communications Commission  
(FCC) and the Canadian Department of Communications (DOC). This equipment has been tested and  
found to comply with the following two regulatory agencies:  
Federal Communications Commission  
This equipment has been tested and found to comply with the limits for a Class A digital device,  
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against  
harmful interference when the equipment is operated in a commercial environment. This equipment  
generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with  
the instruction manual, may cause harmful interference to radio communications. Operation of this  
equipment in a residential area is likely to cause harmful interference in which case the user will be  
required to correct the interference at his own expense.  
Notice to User:  
Changes or modifications not expressly approved by National Instruments could void  
the user’s authority to operate the equipment under the FCC Rules.  
If necessary, consult National Instruments or an experienced radio/television technician for additional  
suggestions. The following booklet prepared by the FCC may also be helpful: Interference to Home  
Electronic Entertainment Equipment Handbook. This booklet is available from the U.S. Government  
Printing Office, Washington, DC 20402.  
Canadian Department of Communications  
This Class A digital apparatus meets all requirements of the Canadian Interference-Causing Equipment  
Regulations.  
Cet appareil numérique de la classe A respecte toutes les exigences du Règlement sur le matériel  
brouilleur du Canada.  
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Contents  
Conventions Used in This Manual................................................................................x  
National Instruments Documentation ...........................................................................xii  
Chapter 1  
National Instruments Application Software...................................................1-2  
Register-Level Programming .........................................................................1-4  
Optional Equipment......................................................................................................1-5  
Chapter 2  
Installation ....................................................................................................................2-1  
Hardware Configuration ...............................................................................................2-2  
Chapter 3  
I/O Connector ...............................................................................................................3-1  
Signal Descriptions.......................................................................................................3-3  
Port C Pin Assignments ...................................................................3-3  
Digital I/O Signal Connections.....................................................................................3-4  
Power Connections .......................................................................................................3-7  
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Contents  
High DIO Power-up State.............................................................................. 3-7  
Timing Specifications................................................................................................... 3-10  
Mode 1 Input Timing ..................................................................................... 3-12  
Chapter 4  
Functional Overview .................................................................................................... 4-1  
Bus Interface .................................................................................................. 4-2  
82C55A Programmable Peripheral Interface................................................. 4-2  
Mode 0............................................................................................. C-8  
Mode 1............................................................................................. C-8  
Mode 2............................................................................................. C-9  
Single Bit Set/Reset Feature............................................................ C-9  
Mode 0—Basic I/O ........................................................................................ C-9  
Mode 0 Programming Example....................................................... C-10  
PC-DIO-24/PnP User Manual  
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Mode 1—Strobed Output ...............................................................................C-14  
Mode 2—Bidirectional Bus............................................................................C-17  
Configuration................................................................................................................D-2  
Interrupt Selection ..........................................................................................D-5  
Interrupt Level Settings....................................................................D-6  
Customer Communication  
Glossary  
Index  
Figures  
NI-DAQ, and Your Hardware ...............................................................1-4  
Figure 2-1. Jumper W1 Location..............................................................................2-1  
Figure 3-3. DIO Channel Configured for High DIO Power-up State  
with External Load.................................................................................3-8  
Figure 3-4. DIO Channel Configured for Low DIO Power-up State  
with External Load.................................................................................3-9  
Figure 3-5. Mode 1 Timing Specification for Input Transfers.................................3-12  
Figure 3-6. Mode 1 Timing Specification for Output Transfers ..............................3-13  
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Contents  
Figure C-3. Port C Pin Assignments, Mode 1 Output .............................................. C-16  
Figure C-5. Port C Pin Assignments, Mode 2 .......................................................... C-19  
Figure D-4. Interrupt Jumper Setting for IRQ5 (Factory Setting) ............................ D-6  
Tables  
Port C Signal Assignments.................................................................... 3-4  
Table 3-2.  
Table C-1. PC-DIO-24/PnP Address Map .............................................................. C-3  
Table C-3. Mode 0 I/O Configurations ................................................................... C-9  
Table D-1. Comparison of Characteristics .............................................................. D-1  
Table D-2. PC-DIO-24 Factory-Set Jumper and Switch Settings ........................... D-2  
Table D-3. Example Switch Settings with Corresponding Base I/O Address  
and I/O Address Space .......................................................................... D-5  
PC-DIO-24/PnP User Manual  
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About  
This  
Manual  
This manual describes the mechanical and electrical aspects of the  
PC-DIO-24/PnP and contains information concerning its operation and  
programming.  
The PC-DIO-24/PnP is a member of the National Instruments family of  
I/O channel expansion boards for ISA computers. These boards are  
for applications in laboratory testing, production testing, and industrial  
process monitoring and control.  
This manual applies to the PC-DIO-24PnP and to the PC-DIO-24, a  
non-Plug and Play device. The boards are identical except for the  
Board.  
Organization of This Manual  
Chapter 1, Introduction, describes the PC-DIO-24/PnP, lists what  
optional equipment, and custom cables, and explains how to  
unpack the PC-DIO-24/PnP.  
Chapter 2, Installation and Configuration, describes how to install  
and configure the PC-DIO-24/PnP.  
Chapter 3, Signal Connections, includes timing specifications and  
connector.  
Chapter 4, Theory of Operation, contains a functional overview of  
the PC-DIO-24/PnP board and explains the operation of each  
functional unit making up the PC-DIO-24/PnP.  
Appendix A, Specifications, lists the specifications for the  
PC-DIO-24/PnP board.  
Appendix B, OKI 82C55A Data Sheet, contains the manufacturer  
data sheet for the OKI Semiconductor 82C55A CMOS PPI.  
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About This Manual  
Appendix C, Register-Level Programming, describes in detail the  
address and function of each of the PC-DIO-24/PnP control and  
status registers.  
Appendix D, Using Your PC-DIO-24 (Non-PnP) Board, describes  
the differences between the PC-DIO-24 and PC-DIO-24PnP  
boards, the PC-DIO-24 board configuration, and the PC-DIO-24  
installation into your computer.  
Appendix E, Customer Communication, contains forms you can  
use to request help from National Instruments or to comment on  
our products.  
The Glossary contains an alphabetical list and description of terms  
used in this manual, including abbreviations, acronyms, metric  
prefixes, mnemonics, symbols, and terms.  
The Index alphabetically lists the topics in this manual, including  
the page where you can find each one.  
Conventions Used in This Manual  
The following conventions are used in this manual:  
This icon to the left of bold italicized text denotes a note, which alerts  
you to important information.  
This icon to the left of bold italicized text denotes a caution, which  
advises you of precautions to take to avoid injury, data loss, or a  
system crash.  
!
82C55A  
<>  
82C55A refers to the OKI Semiconductor 82C55A CMOS PPI.  
Angle brackets containing numbers separated by an ellipsis represent  
a range of values associated with a bit or signal name (for example,  
PB<7..0>).  
bold  
Bold text denotes the names of menus, menu items, parameters, dialog  
boxes, dialog box buttons or options, icons, windows, Windows 95 tabs,  
or LEDs.  
bold italic  
Bold italic text denotes a note, caution, or warning.  
italic  
Italic text denotes emphasis, a cross reference, or an introduction to  
a key concept.  
PC-DIO-24/PnP User Manual  
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About This Manual  
monospace  
Text in this font denotes text or characters that you should enter literally  
from the keyboard, sections of code, programming examples, and  
syntax examples. This font is also used for the proper names of disk  
drives, paths, directories, programs, subprograms, subroutines, device  
names, functions, operations, variables, filenames and extensions, and  
for statements and comments taken from programs.  
NI-DAQ  
PC  
NI-DAQ refers to the NI-DAQ software for PC compatibles unless  
otherwise noted.  
PC refers to the IBM PC/XT, the IBM PC AT, and compatible ISA bus  
computers unless otherwise noted.  
PC-DIO-24/PnP  
PC-DIO-24/PnP refers to both the Plug and Play and non-Plug and Play  
compatible versions of the board.  
PC-DIO-24PnP  
PC-DIO-24  
PnP  
PC-DIO-24PnP refers to the Plug and Play version of the board.  
PC-DIO-24 refers to the non-Plug and Play version of the board.  
PnP (Plug and Play) refers to a device that is fully compatible with the  
industry standard Plug and Play ISA Specification.  
non-PnP  
Non-PnP refers to a device that requires you to configure the device  
base address and interrupt level with switches and jumpers. You must  
perform this configuration before installing the product in the  
computer.  
PPI  
PPI (programmable peripheral interface) is the DIO chip on the  
PC-DIO-24/PnP board.  
SCXI  
SCXI stands for Signal Conditioning eXtensions for Instrumentation  
and is a National Instruments product line designed to perform  
front-end signal conditioning for National Instruments plug-in DAQ  
boards.  
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About This Manual  
National Instruments Documentation  
The PC-DIO-24/PnP User Manual is one piece of the documentation  
set for your data acquisition (DAQ) system. You could have any of  
several types of manuals, depending on the hardware and software in  
your system. Use the different types of manuals you have as follows:  
Getting Started with SCXI—If you are using SCXI, this is the first  
manual you should read. It gives an overview of the SCXI system  
and contains the most commonly needed information for the  
modules, chassis, and software.  
Your SCXI hardware user manuals—If you are using SCXI,  
read these manuals next for detailed information about signal  
connections and module configuration. They also explain in greater  
detail how the module works and contain application hints.  
Your DAQ hardware user manuals—These manuals have detailed  
information about the DAQ hardware that plugs into or is  
connected to your computer. Use these manuals for hardware  
installation and configuration instructions, specification  
information about your DAQ hardware, and application hints.  
Software documentation—Examples of software documentation  
you may have are the LabVIEW and LabWindows/CVI manual sets  
and the NI-DAQ documentation. After you set up your hardware  
system, use either the application software documentation or the  
NI-DAQ documentation to help you write your application. If you  
have a large and complicated system, it is worthwhile to look  
through the software documentation before you configure your  
hardware.  
Accessory installation guides or manuals—If you are using  
accessory products, read the terminal block and cable assembly  
installation guides or accessory board user manuals. They explain  
how to physically connect the relevant pieces of the system.  
Consult these guides when you are making your connections.  
SCXI Chassis Manual—Read this manual for maintenance  
information on the chassis and for installation instructions.  
PC-DIO-24/PnP User Manual  
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About This Manual  
Related Documentation  
The following documents contain information that you may find helpful  
as you read this manual:  
Your computer technical reference manual  
Plug and Play ISA Specification  
Customer Communication  
National Instruments wants to receive your comments on our products  
and manuals. We are interested in the applications you develop with  
our products, and we want to help if you have problems with them.  
To make it easy for you to contact us, this manual contains comment  
and configuration forms for you to complete. These forms are in  
Appendix E, Customer Communication, at the end of this manual.  
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Chapter  
1
Introduction  
This chapter describes the PC-DIO-24/PnP, lists what you need to get  
started, describes software programming choices, optional equipment,  
and custom cables, and explains how to unpack the PC-DIO-24/PnP.  
About the PC-DIO-24/PnP  
Thank you for purchasing the National Instruments PC-DIO-24/PnP.  
The PC-DIO-24/PnP is a low cost, 24-bit, parallel digital I/O interface  
for ISA computers. An OKI 82C55A programmable peripheral  
interface (PPI) chip controls the 24 bits of digital I/O. The 82C55A chip  
is very flexible and powerful when interfacing with peripheral  
equipment, can operate in either a unidirectional or bidirectional bus  
mode, and can generate interrupt requests to the host computer. You can  
program the 82C55A chip for numerous 8-bit, 16-bit, or 24-bit digital  
I/O applications. All digital I/O communication is through a standard  
compatible with standard 24-channel digital I/O applications.  
PnP refers to the Plug and Play technology used in this board. See the  
definition in the Glossary for an explanation. If you have the non-PnP  
version of the PC-DIO-24/PnP, see Appendix D, Using Your  
PC-DIO-24 (Non-PnP) Board, for the differences between the PnP  
version and the non-PnP version.  
You can use the PC-DIO-24/PnP in a wide range of digital I/O  
applications. With the PC-DIO-24/PnP, you can use your PC as a digital  
I/O system controller for laboratory testing, production testing, and  
industrial process monitoring and control.  
Detailed specifications of the PC-DIO-24/PnP are in Appendix A,  
Specifications.  
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Chapter 1  
Introduction  
To set up and use your PC-DIO-24/PnP, you will need the following:  
PC-DIO-24PnP or PC-DIO-24 board  
PC-DIO-24/PnP User Manual  
One of the following software packages and documentation:  
BridgeVIEW  
ComponentWorks  
LabVIEW for Windows  
LabWindows/CVI  
Measure  
NI-DAQ for PC compatibles  
VirtualBench  
Your computer  
Software Programming Choices  
You have several options to choose from when programming your  
National Instruments DAQ and SCXI hardware. You can use National  
Instruments application software, NI-DAQ, or register-level  
programming.  
National Instruments Application Software  
ComponentWorks contains tools for data acquisition and instrument  
control built on NI-DAQ driver software. ComponentWorks provides  
a higher-level programming interface for building virtual instruments  
through standard OLE controls and DLLs. With ComponentWorks, you  
can use all of the configuration tools, resource management utilities,  
and interactive control utilities included with NI-DAQ.  
LabVIEW features interactive graphics and a state-of-the-art user  
interface and a powerful graphical programming language. The  
LabVIEW Data Acquisition VI Library, a series of VIs for using  
LabVIEW with National Instruments DAQ hardware, is included with  
LabVIEW. The LabVIEW Data Acquisition VI Library is functionally  
equivalent to NI-DAQ software.  
PC-DIO-24/PnP User Manual  
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Chapter 1  
Introduction  
LabWindows/CVI features interactive graphics and a state-of-the-art  
user interface and uses the ANSI standard C programming language.  
The LabWindows/CVI Data Acquisition Library, a series of functions  
for using LabWindows/CVI with National Instruments DAQ hardware,  
is included with the NI-DAQ software kit. The LabWindows/CVI Data  
Acquisition Library is functionally equivalent to the NI-DAQ software.  
VirtualBench features virtual instruments that combine DAQ products,  
software, and your computer to create a stand-alone instrument with the  
added benefit of the processing, display, and storage capabilities of  
your computer. VirtualBench instruments load and save waveform data  
to disk in the same forms that can be used in popular spreadsheet  
programs and word processors.  
Using ComponentWorks, LabVIEW, LabWindows/CVI, or  
VirtualBench software will greatly reduce the development time  
for your data acquisition and control application.  
NI-DAQ Driver Software  
The NI-DAQ driver software is included at no charge with all National  
Instruments DAQ hardware. NI-DAQ has an extensive library of  
functions that you can call from your application programming  
environment. These functions include routines for analog input  
(A/D conversion), buffered data acquisition (high-speed A/D  
conversion), analog output (D/A conversion), waveform generation,  
digital I/O, counter/timer operations, SCXI, RTSI, self-calibration,  
messaging, and acquiring data to extended memory.  
NI-DAQ also internally addresses many of the complex issues between  
the computer and the plug-in device, such as programming interrupts  
and DMA controllers. NI-DAQ maintains a consistent software  
interface among its different versions so that you can change platforms  
with minimal modifications to your code. Figure 1-1 illustrates the  
relationship between NI-DAQ and your National Instruments  
application software.  
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Chapter 1  
Introduction  
ComponentWorks,  
LabVIEW,  
LabWindows/CVI, or  
VirtualBench  
Conventional  
Programming Environment  
NI-DAQ  
Driver Software  
Personal  
Computer or  
Workstation  
DAQ or  
SCXI Hardware  
Figure 1-1. The Relationship between the Programming Environment,  
NI-DAQ, and Your Hardware  
Register-Level Programming  
The final option for programming any National Instruments DAQ  
hardware is to write register-level software. Writing register-level  
programming software can be very time-consuming and inefficient,  
and is not recommended for most users.  
Even if you are an experienced register-level programmer, consider  
using National Instruments application software to program your  
National Instruments DAQ hardware. Using the National Instruments  
application software is easier than, and as flexible as, register-level  
programming, and can save weeks of development time.  
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Chapter 1  
Introduction  
Optional Equipment  
National Instruments offers a variety of products to use with your  
PC-DIO-24/PnP board, including cables, connector blocks, and other  
accessories, as follows:  
Cables and cable assemblies, shielded and ribbon  
Connector blocks, shielded and unshielded 50-pin screw terminals  
SCXI modules and accessories for isolating, amplifying, exciting,  
and multiplexing signals for relays and analog output. With SCXI  
you can condition and acquire up to 3,072 channels.  
Low channel-count signal conditioning modules, boards, and  
accessories, including conditioning for strain gauges and RTDs,  
simultaneous sample and hold, and relays.  
For more specific information about these products, refer to your  
National Instruments catalogue or call the office nearest you.  
Note:  
The PC-DIO-24/PnP can drive the SSR-ODC-5 output module and all SSR  
input modules available from National Instruments, but cannot reliably  
sink sufficient current to drive the SSR-OAC-5 and SSR-OAC-5A output  
modules.  
To drive a SSR-OAC-5 or SSR-OAC-5A, you can either use a non-inverting  
digital buffer chip between the PC-DIO-24/PnP and the SSR backplane, or  
use another National Instruments board with higher drive current.  
Custom Cables  
National Instruments offers cables and accessories for you to prototype  
your application or to use if you frequently change board  
interconnections.  
If you want to develop your own cable, however, the following  
guidelines may be useful.  
The PC-DIO-24/PnP I/O connector is a 50-pin male ribbon-cable  
header. The manufacturer part numbers used by National Instruments  
for this header are as follows:  
Electronic Products Division/3M (part number 2550-5002)  
T&B/Ansley Corporation (part number 609-5007)  
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Chapter 1  
Introduction  
The mating connector for the PC-DIO-24/PnP is a 50-position,  
polarized, ribbon socket connector with strain relief. National  
Instruments uses a polarized (keyed) connector to prevent inadvertent  
upside-down connection to the PC-DIO-24/PnP. Recommended  
manufacturer part numbers for this mating connector are as follows:  
Electronic Products Division/3M (part number 3425-7650)  
T&B/Ansley Corporation (part number 622-5041)  
The standard ribbon cables (50-conductor, 28 AWG, stranded) that can  
be used with these connectors are as follows:  
Electronic Products Division/3M (part number 3365/50)  
T&B/Ansley Corporation (part number 171-50)  
Recommended manufacturer part numbers for the 50-pin edge  
connector for connecting to a module rack with an edge connector are  
as follows:  
Electronic Products Division/3M (part number 3415-0001)  
T&B Ansley Corporation (part number 622-5015)  
A polarizing key can be plugged into these edge connectors to prevent  
inadvertent upside-down connection to the I/O module rack. The  
location of this key varies from rack to rack. Consult the specification  
for the rack you intend to use for the location of any polarizing key. The  
recommended manufacturer part numbers for this polarizing key are as  
follows:  
Electronic Products Division/3M (part number 3439-2)  
T&B Ansley Corporation (part number 622-0005)  
PC-DIO-24/PnP User Manual  
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Chapter 1  
Introduction  
Unpacking  
Your PC-DIO-24/PnP board is shipped in an antistatic package to  
prevent electrostatic damage to the board. Electrostatic discharge can  
damage several components on the board. To avoid such damage in  
handling the board, take the following precautions:  
Ground yourself via a grounding strap or by holding a grounded  
object.  
Touch the antistatic package to a metal part of your PC chassis  
before removing the board from the package.  
Remove the board from the package and inspect the board for loose  
components or any other sign of damage. Notify National  
Instruments if the board appears damaged in any way. Do not  
install a damaged board into your computer.  
Never touch exposed connector pins.  
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Chapter  
Installation and  
Configuration  
2
This chapter describes how to install and configure the  
PC-DIO-24/PnP.  
Installation  
Note:  
Install your driver software before installing your hardware. Refer to your  
NI-DAQ release notes for software installation instructions.  
W1  
Note:  
The PC-DIO-24/PnP uses 100 kresistors for polarity selection at  
power-up. You can use jumper W1 to select whether data signals are pulled  
up to Vcc (+5 VDC), factory default, or pulled down to GND. Figure 2-1  
shows jumper W1. For more information, see the Digital I/O Power-up  
State Selection section in Chapter 3, Signal Connections.  
You can install the PC-DIO-24/PnP in any unused 8- or 16-bit  
expansion slot in your computer. The following are general installation  
instructions, but consult your computer user manual or technical  
reference manual for specific instructions and warnings.  
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Chapter 2  
Installation and Configuration  
1. Turn off and unplug your computer.  
2. Remove the I/O channel top cover or access port.  
3. Remove the expansion slot cover on the computer back panel.  
4. Insert the PC-DIO-24/PnP into any 8- or 16-bit slot. It may be a  
tight fit, but do not force the board into place.  
5. Screw the PC-DIO-24/PnP mounting bracket to the computer back  
panel rail.  
6. Visually verify the installation.  
7. Replace the computer cover.  
8. Plug in and turn on your computer.  
The PC-DIO-24/PnP board is now installed.  
Hardware Configuration  
Plug and Play  
The PC-DIO-24PnP is fully compatible with the industry-standard  
Intel/Microsoft Plug and Play Specification. A Plug and Play system  
arbitrates and assigns resources through software, freeing you from  
manually setting switches and jumpers. These resources include the  
PC-DIO-24PnP base I/O address and interrupt channel.  
The Configuration Manager receives all of the resource requests at  
startup, compares the available resources to those requested, and  
assigns the available resources as efficiently as possible to the Plug and  
Play boards. Application software can query the Configuration  
Manager to determine the resources assigned to each board without  
your involvement. The Plug and Play software is installed as a device  
driver or as an integral component of the computer BIOS.  
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Chapter 2  
Installation and Configuration  
Base I/O Address and Interrupt Selection  
To change base I/O address or interrupt selection, refer to the NI-DAQ  
Configuration Utility Help file. You can configure the PC-DIO-24PnP  
to use base addresses in the range of 100 to 3E0 hex. Each board  
boundary. Therefore, valid addresses include 100, 120, 140…, 3E0 hex.  
The PC-DIO-24PnP can use interrupt channel 3, 4, 5, 7, or 9.  
Note:  
To configure the non-Plug and Play PC-DIO-24 board, refer to  
Appendix D, Using Your PC-DIO-24 (Non-PnP) Board.  
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Chapter  
3
Signal Connections  
This chapter includes timing specifications and signal connection  
instructions for the PC-DIO-24/PnP I/O connector.  
Caution: Connections that exceed any of the maximum ratings of input or output  
signals on the PC-DIO-24/PnP can damage the board and the PC. National  
Instruments is NOT liable for any damages resulting from any such signal  
under the discussion of that signal.  
!
I/O Connector  
Figure 3-1 shows the pin assignments for the PC-DIO-24/PnP digital  
I/O connector.  
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Chapter 3  
Signal Connections  
1
3
5
7
9
2
4
PC7  
PC6  
PC5  
PC4  
PC3  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
6
8
10  
11 12  
13 14  
15 16  
17 18  
19 20  
21 22  
23 24  
25 26  
27 28  
29 30  
31 32  
33 34  
PC2  
PC1  
PC0  
PB7  
PB6  
PB5  
PB4  
PB3  
PB2  
PB1  
PB0  
PA7  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
PA6 35 36  
37 38  
39 40  
41 42  
43 44  
45 46  
47 48  
49 50  
PA5  
PA4  
PA3  
PA2  
PA1  
PA0  
+5 V  
Figure 3-1. Digital I/O Connector Pin Assignments  
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Chapter 3  
Signal Connections  
Signal Descriptions  
Table 3-1 describes the PC-DIO-24/PnP signals.  
Table 3-1. Signal Descriptions  
Signal  
Pin  
Name  
Description  
1, 3, 5, 7, 9, 11,  
13, 15  
PC<7..0>  
Port C—Bidirectional data lines for  
port C. PC7 is the MSB, PC0 the  
LSB.  
17, 19, 21, 23, 25,  
27, 29, 31  
PB<7..0>  
PA<7..0>  
+5 V  
Port B—Bidirectional data lines for  
port B. PB7 is the MSB, PB0 the  
LSB.  
33, 35, 37, 39, 41,  
43, 45, 47  
Port A—Bidirectional data lines for  
port B. PA7 is the MSB, PA0 the  
LSB.  
49  
+5 Volts—This pin is fused for up  
to 1 A at +4.65 to 5.25 V.  
All even-numbered GND  
pins  
Ground—These signals are  
connected to the computer ground  
reference.  
The absolute maximum voltage input rating is –0.5 to +5.5 V with  
respect to GND.  
Port C Pin Assignments  
The signals assigned to port C depend on the mode in which the  
82C55A is programmed. In mode 0, port C is treated as one 8-bit  
I/O port. If port A or B is in mode 1 or 2, then some or all of the port C  
lines are used for status and handshaking signals. Any unused lines are  
available for general-purpose input and output. Table 3-2 summarizes  
the signal assignments of port C for each programmable mode. Ports A  
and B can be in different modes; the table does not show every possible  
combination. See Appendix C, Register-Level Programming, for  
register-level programming information.  
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Chapter 3  
Signal Connections  
Caution: During programming, note that each time you configure any port, output  
!
ports A and C are reset to 0, and output port B is undefined.  
Table 3-2. Port C Signal Assignments  
Group A  
Group B  
Programming  
Mode  
PC7  
I/O  
PC6  
PC5  
PC4  
PC3  
PC2  
I/O  
PC1  
PC0  
I/O  
Mode 0  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Mode 1 Input  
I/O  
IBF  
STB * INTR  
STB * IBFB  
INTR  
A
A
A
A
A
B
B
B
B
Mode 1 Output OBF * ACK * I/O  
I/O  
INTR  
ACK * OBF * INTR  
A
A
B
B
Mode 2  
OBF * ACK * IBF  
STB * INTR  
I/O  
I/O  
I/O  
A
A
A
A
* Indicates that the signal is active low.  
Digital I/O Signal Connections  
The following specifications and ratings apply to the digital I/O lines.  
The maximum input logic high and output logic high voltages assume a  
Vcc supply voltage of 5.0 V.  
The absolute maximum voltage rating is –0.5 to +5.5 V with respect to  
GND.  
Digital input specifications (referenced to GND):  
Input logic high voltage  
Input logic low voltage  
Input high current  
2.2 V min  
5.3 V max  
0.8 V max  
–0.3 V min  
(V = 5 V, W1 set to pullup)  
in  
11.0 µA max  
65 µA max  
–65 µA max  
–11 µA max  
Input high current  
(V = 5 V, W1 set to pulldown)  
in  
Input logic low current  
(V = 0 V, W1 set to pullup)  
in  
Input logic low current  
(V = 0 V, W1 set to pulldown)  
in  
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Chapter 3  
Signal Connections  
Digital output specifications (referenced to GND):  
Output logic high voltage  
3.7 V min  
2.7 V min  
0 V min  
5.0 V max  
(I = –2.5 mA)  
ol  
Output logic high voltage  
5.0 V max  
0.4 V  
(I = –4 mA)  
oh  
(I = 2.5 mA)  
ol  
Output logic low voltage  
0 V min  
0.5 V  
(I = 4 mA)  
ol  
Figure 3-2 depicts signal connections for three typical digital I/O  
applications.  
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Chapter 3  
Signal Connections  
+5 V  
+5 V  
LED  
Jumper  
Selectable (W1)  
100 k  
100 kΩ  
100 kΩ  
100 kΩ  
41  
43  
45  
47  
PPI  
Port A  
PA<3..0>  
100 kΩ  
100 kΩ  
100 kΩ  
100 kΩ  
67  
69  
71  
73  
PPI  
TTL Signal  
Port B  
PB<7..4>  
+5 V  
Switch  
50, 100  
GND  
I/O Connector  
PC-DIO-24/PnP  
Figure 3-2. Digital I/O Connections  
In Figure 3-2, port A is configured for digital output, and port B is  
configured for digital input. Digital input applications include receiving  
TTL signals and sensing external device states such as the state of the  
switch in Figure 3-2. Digital output applications include sending TTL  
signals and driving external devices such as the LED shown in this  
figure.  
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Chapter 3  
Signal Connections  
Power Connections  
Pin 49 of the I/O connector is connected to the +5 V supply from the PC  
power supply. This pin is referenced to GND and can be used to power  
external digital circuitry. This +5 V supply has a 1 A self-resetting  
protection fuse in series. Simply remove the circuit causing the heavy  
current load and the fuse will reset itself.  
Power rating  
1 A at +4.65 to 5.25 V  
Caution: Under no circumstances should this +5 V power pin be connected directly  
to ground or to any other voltage source on the PC-DIO-24/PnP or any  
other device. Doing so may damage the PC-DIO-24/PnP and the PC.  
National Instruments is NOT liable for damage resulting from such a  
connection.  
!
Digital I/O Power-up State Selection  
You can power up the PC-DIO-24/PnP digital I/O lines in a  
user-defined state. The PC-DIO-24/PnP facilitates user-configurable  
pull-up or pull-down. Each DIO channel is connected to a 100 kΩ  
resistor and can be pulled high or low using jumper W1. You can  
use W1 to pull all 24 DIO lines high or low. However, you may want to  
pull individual lines in different directions. To do this properly, you  
must understand the nature of the drive current on those lines and  
adhere to TTL logic levels.  
High DIO Power-up State  
If you select the pulled-high mode, each DIO line will be pulled to Vcc  
(approximately +5 VDC) with a 100 kresistor. If you want to pull a  
specific line low, connect between that line and ground a pull-down  
resistor (R ) whose value will give you a maximum of 0.4 VDC. Using  
L
the largest possible resistor ensures that you do not use more current  
than necessary to perform the pull-down task, and that the DIO can still  
drive the line. The DIO lines provide a maximum of 2.5 mA at 3.7 V in  
the high state.  
Also, make sure the resistor value is not so large that leakage current  
from the DIO line along with the current from the 100 kpull-up  
resistor drives the voltage at the resistor above a TTL low level of  
0.4 VDC.  
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Chapter 3  
Signal Connections  
PC-DIO-24/PnP  
+5 V  
100 k  
82C55A  
Digital I/O Line  
RL  
GND  
Figure 3-3. DIO Channel Configured for High DIO Power-up State with External Load  
Example:  
At power up, the board is configured for input and, by default, all DIO  
lines are high. To pull one channel low, follow these steps:  
1. Install a load (R ). Remember that the smaller the resistance, the  
L
greater the current consumption and the lower the voltage.  
2. Using the following formula, calculate the largest possible load to  
maintain a logic low level of 0.4 V with a minimum reduction to the  
DIO drive current.  
V = I * R R = V / I, where:  
L
L
V= 0.4 V  
; Voltage across R  
L
I = 46 µA + 11 µA  
; 4.6 V across the 100 kpull-up  
resistor and 11 µA max leakage  
current  
Therefore:  
R = 7.0 kΩ  
; 0.4 V / 57 µA  
L
This resistor value, 7.0 k, provides a maximum of 0.4 V on the DIO  
line at power up. You can substitute smaller resistor values to lower the  
voltage or to provide a margin for Vcc variations and other factors.  
However, smaller values will draw more current, leaving less drive  
current for other circuitry connected to this line. The 7.0 kresistor  
reduces the amount of logic high source current by 0.4 mA with a 2.8 V  
output.  
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Chapter 3  
Signal Connections  
Low DIO Power-up State  
If you select pulled-low mode, each DIO line will be pulled to GND  
(0 VDC) using a 100 kresistor. To pull a specific line high, connect  
a pull-up resistor that will give you a minimum of 2.8 VDC. Using the  
largest possible resistance value ensures that you do not to use more  
current than necessary to perform the pull-up task, and that the DIO can  
still drive the line. The DIO lines are capable of sinking a maximum of  
2.5 mA at 0.4 V in the low state.  
Also, make sure the pull-up resistor value is not so large that leakage  
current from the DIO line along with the current from the 100 kΩ  
pull-down resistor brings the voltage at the resistor below a TTL high  
level of 2.8 VDC.  
PC-DIO-24/PnP  
+5 V  
RL  
82C55A  
Digital I/O Line  
100 k  
GND  
Figure 3-4. DIO Channel Configured for Low DIO Power-up State with External Load  
Example:  
At power up, the board is configured for input and jumper W1 is set in  
the low DIO power-up state, which means all DIO lines are pulled low.  
If you want to pull one channel high, follow these steps:  
1. Install a load (R ). Remember that the smaller the resistance, the  
L
greater the current consumption and the higher the voltage.  
2. Using the following formula, calculate the largest possible load to  
maintain a logic high level of 2.8 V and supply the maximum sink  
current.  
V = I * R R = V / I, where:  
L
L
V = 2.2 V  
; voltage across R  
L
I = 28 µA + 11 µA  
; 2.8 V across the 100 kpull-up  
resistor and 11 µA max leakage  
current  
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Chapter 3  
Signal Connections  
Therefore:  
R = 5.6 kΩ  
; 2.2 V / 39 µA  
L
This resistor value, 5.6 k, provides a minimum of 2.8 V on the DIO  
line at power up. You can substitute smaller resistor values but they will  
draw more current, leaving less sink current for other circuitry  
connected to this line. The 5.6 kresistor will reduce the amount of a  
logic low sink current by 0.8 mA with a 0.4 V output.  
Timing Specifications  
This section lists the timing specifications for handshaking with the  
PC-DIO-24/PnP. The handshaking lines STB* and IBF synchronize  
input transfers. The handshaking lines OBF* and ACK* synchronize  
output transfers.  
The signals in Table 3-3 are used in the timing diagrams on the  
subsequent pages.  
Table 3-3. Timing Signal Descriptions  
Signal  
Name  
Direction  
Description  
STB*  
Input  
Strobe Input—A low signal on this  
handshaking line loads data into the input  
latch.  
IBF  
Output  
Input  
Input Buffer Full—A high signal on this  
handshaking line indicates that data has  
been loaded into the input latch. This is an  
input acknowledge signal.  
ACK*  
Acknowledge Input—A low signal on this  
handshaking line indicates that the data  
written from the selected port has been  
accepted. This signal is a response from the  
external device that it has received the data  
from the PC-DIO-24/PnP.  
OBF*  
Output  
Output Buffer Full—A low signal on this  
handshaking line indicates that data has  
been written to the selected port.  
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Chapter 3  
Signal Connections  
Table 3-3. Timing Signal Descriptions (Continued)  
Signal  
Name  
Direction  
Description  
INTR  
Output  
Interrupt Request—This signal becomes  
high when the 82C55A is requesting service  
during a data transfer. The appropriate  
interrupt enable bits must be set to generate  
this signal.  
RD*  
Internal  
Internal  
Read Signal—This signal is the read signal  
generated from the control lines of the PC.  
WR*  
DATA  
Write Signal—This signal is the write signal  
generated from the control lines of the PC.  
Bidirectional Data Lines at the Selected Port—This signal  
indicates when the data on the data lines at a  
selected port is available (output) or should  
be available (input).  
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Chapter 3  
Signal Connections  
Mode 1 Input Timing  
The following figure illustrates the timing specifications for an input  
transfer in mode 1.  
T1  
T2  
T4  
STB*  
IBF  
T7  
T6  
INTR  
RD*  
T5  
T3  
DATA  
Name  
T1  
Description  
Minimum  
Maximum  
100  
20  
50  
STB* pulse width  
T2  
150  
STB* = 0 to IBF* = 1  
Data before STB* = 1  
STB* = 1 to INTR = 1  
Data after STB* = 1  
RD* = 0 to INTR = 0  
RD* = 1 to IBF = 0  
T3  
T4  
150  
T5  
T6  
200  
T7  
150  
All timing values are in nanoseconds.  
Figure 3-5. Mode 1 Timing Specification for Input Transfers  
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Chapter 3  
Signal Connections  
Mode 1 Output Timing  
The following figure illustrates the timing specifications for an output  
transfer in mode 1.  
T3  
WR*  
T4  
OBF*  
T1  
T6  
INTR  
ACK*  
T5  
DATA  
T2  
Name  
T1  
Description  
WR* = 0 to INTR = 0  
Minimum  
Maximum  
250  
T2  
200  
WR* = 1 to output  
T3  
150  
WR* = 1 to OBF* = 0  
ACK* = 0 to OBF* = 1  
ACK* pulse width  
T4  
150  
T5  
100  
T6  
150  
ACK* = 1 to INTR = 1  
All timing values are in nanoseconds.  
Figure 3-6. Mode 1 Timing Specification for Output Transfers  
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Chapter 3  
Signal Connections  
Mode 2 Bidirectional Timing  
The following figure illustrates the timing specifications for  
bidirectional transfers in mode 2.  
T1  
WR*  
T6  
OBF*  
INTR  
T7  
ACK*  
STB*  
T3  
T10  
T4  
IBF  
RD*  
T2  
T5  
T9  
T8  
DATA  
Name  
T1  
Description  
WR* = 1 to OBF* = 0  
Minimum  
Maximum  
150  
20  
T2  
Data before STB*= 1  
STB* pulse width  
T3  
100  
T4  
150  
STB* = 0 to IBF = 1  
Data after STB* = 1  
ACK* = 0 to OBF = 1  
ACK* pulse width  
T5  
50  
T6  
150  
T7  
100  
T8  
150  
250  
150  
ACK* = 0 to output  
ACK* = 1 to output float  
RD* = 1 to IBF = 0  
T9  
20  
T10  
All timing values are in nanoseconds.  
Figure 3-7. Mode 2 Timing Specification for Bidirectional Transfers  
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Chapter  
4
Theory of Operation  
This chapter contains a functional overview of the PC-DIO-24/PnP  
board and explains the operation of each functional unit making up the  
PC-DIO-24/PnP.  
Functional Overview  
The block diagram in Figure 4-1 illustrates the key functional  
components of the PC-DIO-24/PnP board.  
PA  
/
8
Bus  
Transceivers  
PB  
/
8
82C55A  
PPI  
Bus Interface  
(Plug and Play)  
PC  
/
8
Address Interrupt  
Decode Circuitry  
PC3  
PC0  
Interrupt  
Control  
Circuitry  
+5 V  
1 A Fuse  
Figure 4-1. PC-DIO-24/PnP Block Diagram  
The PC I/O channel consists of an address bus, a data bus, interrupt  
lines, and several control and support signals. Control and data transfers  
to the system microprocessor are asynchronous.  
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Chapter 4  
Theory of Operation  
Bus Transceivers  
Bus Interface  
The bus transceivers send and receive data lines and other signals to and  
from the PC I/O channel.  
The PC-DIO-24PnP Plug and Play circuitry automatically arbitrates  
and assigns system resources. Software performs all bus-related  
configuration, such as setting the board base address and interrupt level.  
On the PC-DIO-24 (non-PnP), switches and jumpers set the board base  
address and interrupt level.  
Interrupt Control Circuitry  
The PC-DIO-24PnP interrupt channel is selected by the Plug and Play  
circuitry. Two software-controlled registers determine what sources, if  
any, can generate interrupts. The 82C55A device has two interrupt  
lines, PC3 and PC0, connected to the interrupt circuitry.  
The PC-DIO-24 (non-PnP) uses one of the extra PC lines  
(jumper-selectable) as an interrupt enable.  
82C55A Programmable Peripheral Interface  
The 82C55A PPI chip is the heart of the PC-DIO-24/PnP. This chip has  
24 programmable I/O pins that represent three 8-bit ports—PA, PB, and  
PC. You can program each port as an input or an output port. The  
82C55A has three modes of operation—simple I/O (mode 0),  
strobed I/O (mode 1), and bidirectional I/O (mode 2). In mode 1, the  
group has eight data bits and three control and status bits from port C  
(PC). Group A can also use mode 2. In mode 2, group A has one 8-bit  
bidirectional data port and five control and status bits from port C. You  
can use port A and port B in two different modes. Modes 1 and 2 use  
handshaking signals from port C to synchronize data transfers. Refer to  
Chapter 4, Theory of Operation, or to Appendix B, OKI 82C55A Data  
Sheet, for more detailed information.  
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Theory of Operation  
All digital I/O is transmitted through a standard, 50-pin, male  
connector. Pin 49 is connected to +5 V through a resettable protection  
fuse. You can use this +5 V supply to operate I/O module mounting  
racks. Even-numbered pins are connected to ground. See the Optional  
Equipment section in Chapter 1, Introduction, as well as Chapter 3,  
Signal Connections, for additional information.  
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4-3  
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Appendix  
A
Specifications  
This appendix lists the specifications for the PC-DIO-24/PnP board.  
These specifications are typical at 25° C, unless otherwise stated. The  
operating temperature range is 0° to 70° C.  
Digital I/O  
Number of channels ............................24 I/O  
Compatibility......................................TTL  
Absolute max voltage input rating  
(Vcc = 5.0 V)......................................–0.5 to +5.5 V with  
respect to GND  
Handshaking .......................................Requires one port  
Power-on state ....................................Configured as inputs, pulled  
high or low (jumper-selectable)  
Data transfers......................................Interrupts, programmed I/O  
Digital Logic Levels  
Input Signals  
The maximum input logic high and output logic high voltages assume a  
Vcc supply voltage of 5.0 V.  
Level  
Input logic high voltage  
Input logic low voltage  
Input high current  
Min  
2.2 V  
–0.3 V  
Max  
5.3 V  
0.8 V  
11.0 µA  
(V = 5 V, W1 set to pullup)  
in  
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Appendix A  
Specifications  
Level  
Input high current  
Min  
Max  
65 µA  
(V = 5 V, W1 set to pulldown)  
in  
Input logic low current  
(V = 0 V, W1 set to pullup)  
in  
–65 µA  
Input logic low current  
(V = 0 V, W1 set to pulldown)  
in  
–11 µA  
Output Signals  
Pin 49 (at 4.65 to 5.25 VDC).............. 1.0 A max  
Level  
Min  
Max  
Output logic high voltage  
3.7 V  
2.7 V  
0 V  
5.0 V  
(I = –2.5 mA)  
ol  
Output logic high voltage  
5.0 V  
0.4 V  
0.5 V  
(I = –4 mA)  
oh  
Output logic low voltage  
(I = 2.5 mA)  
ol  
Output logic low voltage  
0 V  
(I = 4 mA)  
ol  
Power Requirement  
Physical  
+5 VDC (±10%)................................. 0.45 A typ, 1 A max  
Dimensions ........................................ 11.7 by 10.6 cm (4.6 by 4.2 in.)  
I/O connector ..................................... 50-pin male ribbon-cable  
connector  
PC-DIO-24/PnP User Manual  
A-2  
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Appendix A  
Specifications  
Environment  
Operating temperature ........................0° to 70° C  
Storage temperature ............................–55° to 150° C  
Relative humidity ...............................5% to 90% noncondensing  
Transfer Rates  
Max with NI-DAQ software................50 kbytes/s  
Constant sustainable rate (typ) ............1 to 10 kbytes/s  
Transfer rates are a function of the speed with which your program  
reads data from or writes data to the board, and therefore vary with your  
system, software, and application. The following primary factors  
control PC-DIO-24/PnP transfer rates:  
Computer system performance  
Programming environment (register-level programming or  
NI-DAQ)  
Programming language and code efficiency  
Execution mode (foreground or background, with background  
execution typically using interrupts)  
Other operations in progress  
Application  
For example, you can obtain higher transfer rates in a handshaking or  
data-transfer application, requiring an average rate, than in a pattern  
generation, data acquisition, or waveform generation application,  
requiring a constant sustainable rate.  
The maximum rate shown was obtained using a 233 MHz Pentium  
computer running NI-DAQ and LabWindows/CVI software, with  
interrupt-based execution, and with no other high-speed operations in  
progress.  
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A-3  
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Appendix  
B
OKI 82C55A Data Sheet  
This appendix contains the manufacturer data sheet for the OKI  
Semiconductor* 82C55A CMOS PPI. This interface is used on the  
PC-DIO-24/PnP board.  
* Copyright © OKI Semiconductor 1995. Reprinted with permission of copyright owner. All rights reserved.  
OKI Semiconductor Data Book Microprocessor, Eighth Edition, January 1995.  
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B-1  
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Appendix B  
OKI 82C55A Data Sheet  
PC-DIO-24/PnP User Manual  
B-2  
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Appendix B  
OKI 82C55A Data Sheet  
© National Instruments Corporation  
B-3  
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Appendix B  
OKI 82C55A Data Sheet  
PC-DIO-24/PnP User Manual  
B-4  
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Appendix B  
OKI 82C55A Data Sheet  
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B-5  
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Appendix B  
OKI 82C55A Data Sheet  
PC-DIO-24/PnP User Manual  
B-6  
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Appendix B  
OKI 82C55A Data Sheet  
© National Instruments Corporation  
B-7  
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Appendix B  
OKI 82C55A Data Sheet  
PC-DIO-24/PnP User Manual  
B-8  
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Appendix B  
OKI 82C55A Data Sheet  
© National Instruments Corporation  
B-9  
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Appendix B  
OKI 82C55A Data Sheet  
PC-DIO-24/PnP User Manual  
B-10  
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Appendix B  
OKI 82C55A Data Sheet  
© National Instruments Corporation  
B-11  
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Appendix B  
OKI 82C55A Data Sheet  
PC-DIO-24/PnP User Manual  
B-12  
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Appendix B  
OKI 82C55A Data Sheet  
© National Instruments Corporation  
B-13  
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Appendix B  
OKI 82C55A Data Sheet  
PC-DIO-24/PnP User Manual  
B-14  
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Appendix B  
OKI 82C55A Data Sheet  
© National Instruments Corporation  
B-15  
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Appendix B  
OKI 82C55A Data Sheet  
PC-DIO-24/PnP User Manual  
B-16  
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Appendix B  
OKI 82C55A Data Sheet  
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B-17  
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Appendix  
Register-Level  
Programming  
C
This appendix describes in detail the address and function of each of the  
PC-DIO-24/PnP control and status registers. This appendix also  
includes important information about register-level programming on  
the PC-DIO-24/PnP along with program examples written in C and  
assembly language.  
Note:  
If you plan to do application-level programming using software such as  
LabVIEW, LabWindows/CVI, or NI-DAQ with your PC-DIO-24/PnP  
board, you need not read this appendix.  
Introduction  
You can configure your PC-DIO-24PnP board to use base addresses in  
the range of 100 to 3E0 hex. Your PC-DIO-24PnP board occupies  
32 bytes of address space and must be located on a 32-byte boundary.  
Therefore, valid addresses include 100, 120, 140..., 3E0 hex. The base  
I/O address is software-configured and does not require you to  
manually change any board settings. For more information on  
configuring the PC-DIO-24PnP, see Chapter 2, Installation and  
Configuration.  
The PC-DIO-24 non-PnP board occupies four bytes of address space  
and must be located on a four-byte boundary. For more information on  
configuring the PC-DIO-24, see Appendix D, Using Your PC-DIO-24  
(Non-PnP) Board.  
In addition to the 82C55A device, the PC-DIO-24PnP has two registers  
that select which interrupt sources are capable of generating interrupts.  
Individual enable bits select whether port A or port B interrupt signals  
from the 82C55A device generate interrupt requests. A master interrupt  
enable bit determines whether the board can actually send interrupt  
requests to the host computer. The configuration bits for these registers  
are defined in the Register Description for the Interrupt Control  
Registers section in this appendix.  
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Appendix C Register-Level Programming  
The PC-DIO-24 (non-PnP) does not have interrupt control registers.  
Instead, it uses one of the port C lines to enable or disable interrupts.  
See Appendix D, Using Your PC-DIO-24 (Non-PnP) Board for more  
information.  
The three 8-bit ports of the 82C55A are divided into two groups of  
12 signals each: group A and group B. One 8-bit control word selects  
the modes of operation for both groups. The group A control bits  
configure port A (A7 through A0) and the upper 4 bits (nibble) of  
port C (C7 through C4). The group B control bits configure port B  
(B7 through B0) and the lower nibble of port C (C3 through C0). These  
configuration bits are defined in the Register Description for the  
82C55A section later in this appendix.  
The 82C55A potentially requires up to 200 ns recovery time between  
consecutive read or write cycles. Certain computers may provide  
slightly less time than this between two back-to-back assembly-  
language reads or writes. If you are programming in assembly language,  
it is therefore recommended that you separate two 82C55A reads or  
writes with at least one other instruction.  
PC-DIO-24/PnP User Manual  
C-2  
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Appendix C Register-Level Programming  
Register Map  
The following table lists the address map for the PC-DIO-24/PnP.  
Table C-1. PC-DIO-24/PnP Address Map  
Offset Address  
Register Name  
82C55A Register Group  
PORTA Register  
(Hex)  
Size  
Type  
00  
01  
02  
03  
8-bit  
8-bit  
8-bit  
8-bit  
Read-and-write  
Read-and-write  
Read-and-write  
Write-only  
PORTB Register  
PORTC Register  
CNFG Register  
Interrupt Control Register Group  
(PC-DIO-24PnP only)  
Register 1  
Register 2  
15  
8-bit  
8-bit  
Write-only  
Write-only  
Register Description for the 82C55A  
Figure C-1 shows the two control word formats used to completely  
program the 82C55A. The control word flag determines which control  
word format is being programmed. When the control word flag is 1,  
bits 6 through 0 select the I/O characteristics of the 82C55A ports.  
These bits also select the mode in which the ports are operating (that is,  
mode 0, mode 1, or mode 2). When the control word flag is 0, bits 3  
through 0 select the bit set/reset format of port C.  
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Appendix C Register-Level Programming  
Group A  
Group B  
D1  
D7  
D6  
D5  
D4  
D3  
D2  
D0  
Control Word  
Flag  
Port C  
(low nibble)  
1 = input  
0 = output  
1 = mode set  
Mode Selection  
00 = mode 0  
01 = mode 1  
1X = mode 2  
Port B  
1 = input  
0 = output  
Mode Selection  
0 = mode 0  
1 = mode 1  
Port A  
1 = input  
0 = output  
Port C  
(high nibble)  
1 = input  
0 = output  
a. Mode Set Word Format  
D7  
D6  
D5  
D3  
D2  
D1  
D0  
D4  
Control Word  
Flag  
Bit Set/Reset  
1 = set  
0 = bit set/reset  
0 = reset  
Bit Select  
(000)  
(001)  
(010)  
:
Unused  
:
(111)  
b. Bit Set/Reset Word Format  
Figure C-1. Control Word Formats for the 82C55A  
Caution: During programming, note that each time any port is configured, output  
!
ports A and C are reset to 0, and output port B is undefined.  
PC-DIO-24/PnP User Manual  
C-4  
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Appendix C Register-Level Programming  
Table C-2 shows the control words for setting or resetting each bit in  
port C. Notice that bit 7 of the control word is cleared when  
programming the set/reset option for the bits of port C.  
Table C-2. Port C Set/Reset Control Words  
Bit Set Control  
Word  
Bit Reset  
Control Word Reset in Port C  
The Bit Set or  
Bit Number  
0
1
2
3
4
5
6
7
0xxx0001  
0xxx0011  
0xxx0101  
0xxx0111  
0xxx1001  
0xxx1011  
0xxx1101  
0xxx1111  
0xxx0000  
0xxx0010  
0xxx0100  
0xxx0110  
0xxx1000  
0xxx1010  
0xxx1100  
0xxx1110  
xxxxxxxb  
xxxxxxbx  
xxxxxbxx  
xxxxbxxx  
xxxbxxxx  
xxbxxxxx  
xbxxxxxx  
bxxxxxxx  
Register Description for the Interrupt Control Registers  
There are two interrupt control registers on the PC-DIO-24PnP. One of  
these registers has individual enable bits for the two interrupt lines from  
the 82C55A device. The other register has a master interrupt enable bit.  
When writing to these registers, set all reserved bits to zero. The bit  
maps and signal definitions are listed as follows.  
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Appendix C Register-Level Programming  
Interrupt Control Register 1 (PnP Board Only)  
D7  
x
D6  
x
D5  
x
D4  
x
D3  
x
D2  
x
D1  
D0  
IRQ1  
IRQ0  
Bit  
2–7  
1
Name  
x
Description  
Reserved bit.  
IRQ1  
PPI Interrupt Request for Port B—If this bit and the  
INTEN bit in Interrupt Control Register 2 are both set,  
the PPI can send an interrupt, INTRB, to the host  
computer. If this bit is cleared, the PPI does not send  
the interrupt INTRB to the host computer, regardless  
of the setting of INTEN.  
0
IRQ0  
PPI Interrupt Request for Port A—If this bit and the  
INTEN bit in Interrupt Control Register 2 are both set,  
the PPI can send an interrupt, INTRA, to the host  
computer. If this bit is cleared, the PPI does not send  
the interrupt INTRA to the host computer, regardless  
of the setting of INTEN.  
PC-DIO-24/PnP User Manual  
C-6  
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Appendix C Register-Level Programming  
Interrupt Control Register 2 (PnP Board Only)  
D7  
X
D6  
X
D5  
X
D4  
X
D3  
X
D2  
D1  
X
D0  
X
INTEN  
Bit  
Name  
Description  
1–0, 3–7  
2
X
Reserved Bit.  
INTEN  
Global Interrupt Enable Bit—If this bit is set, the  
PC-DIO-24PnP can interrupt the host computer. If this  
bit is cleared, the board cannot interrupt the host  
computer.  
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Appendix C Register-Level Programming  
Programming Considerations for the 82C55A  
Modes of Operation for the 82C55A  
The three basic modes of operation for the 82C55A are as follows:  
Mode 0—Basic I/O  
Mode 1—Strobed I/O  
Mode 2—Bidirectional bus  
The 82C55A also has a single bit set/reset feature for port C, which is  
programmed by the 8-bit control word. For additional information, refer  
to Appendix B, OKI 82C55A Data Sheet.  
Mode 0  
Use this mode for simple input and output operations for each of the  
ports. No handshaking is required; simply write data to or read data  
from a specified port.  
Mode 0 has the following features:  
Two 8-bit ports (A and B) and two 4-bit ports (upper and lower  
nibbles of port C).  
Any port can be input or output.  
Outputs are latched, but inputs are not latched.  
Mode 1  
This mode transfers data that is synchronized by handshaking signals.  
Ports A and B use the eight lines of port C to generate or receive the  
handshake signals. This mode divides the ports into two groups  
(group A and group B) and includes the following features:  
Each group contains one 8-bit data port (port A or port B) and one  
3-bit control/status port (upper or lower portion of port C).  
The 8-bit data ports can be either input or output, both of which are  
latched.  
The 3-bit ports are used for control and status of the 8-bit data ports.  
Interrupt generation and enable/disable functions are available.  
PC-DIO-24/PnP User Manual  
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Appendix C Register-Level Programming  
Mode 2  
Use this mode for communication over a bidirectional 8-bit bus.  
Handshaking signals are used in a manner similar to mode 1. Mode 2 is  
available for use in group A only (port A and the upper portion of  
port C). Other features of this mode include the following:  
One 8-bit bidirectional port (port A) and a 5-bit control/status port  
(port C).  
Latched inputs and outputs.  
Interrupt generation and enable/disable functions.  
Single Bit Set/Reset Feature  
You can set or reset any of the eight bits of port C with one control  
word. This feature generates control signals for port A and port B when  
these ports are operating in mode 1 or mode 2.  
Mode 0—Basic I/O  
Use mode 0 for simple I/O functions (no handshaking) for each of the  
three ports. You can assign each port as an input or an output port. The  
16 possible I/O configurations are shown in Table C-3. Notice that bit 7  
of the control word is set when programming the mode of operation for  
each port.  
Table C-3. Mode 0 I/O Configurations  
Control Word  
Group A  
Port C1  
Group B  
Bit  
76543210  
Number  
Port A  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Input  
Port B  
Output  
Output  
Input  
Port C2  
Output  
Input  
0
1
2
3
4
5
6
7
8
10000000  
10000001  
10000010  
10000011  
10001000  
10001001  
10001010  
10001011  
10010000  
Output  
Output  
Output  
Output  
Input  
Output  
Input  
Input  
Output  
Output  
Input  
Output  
Input  
Input  
Input  
Output  
Input  
Input  
Input  
Output  
Output  
Output  
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Appendix C Register-Level Programming  
Table C-3. Mode 0 I/O Configurations (Continued)  
Control Word  
Group A  
Port C1  
Group B  
Bit  
76543210  
Number  
Port A  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Port B  
Output  
Input  
Port C2  
Input  
9
10010001  
10010010  
10010011  
10011000  
10011001  
10011010  
10011011  
Output  
Output  
Output  
Input  
10  
11  
12  
13  
14  
15  
Output  
Input  
Input  
Output  
Output  
Input  
Output  
Input  
Input  
Input  
Output  
Input  
Input  
Input  
1 Upper nibble of port C  
2 Lower nibble of port C  
Mode 0 Programming Example  
The following example shows how to configure the 82C55A for various  
combinations of mode 0 input and output. This code is strictly an  
example and is not intended to be used without modification in a  
practical situation.  
Main() {  
#define BASE_ADDRESS  
#define PORTAoffset  
#define PORTBoffset  
#define PORTCoffset  
#define CNFGoffset  
0x180  
0x00  
0x01  
0x02  
0x03  
/* Board located at address 180 */  
/* Offset for port A */  
/* Offset for port B */  
/* Offset for port C */  
/* Offset for CNFG */  
unsigned int porta, portb, portc, cnfg;  
char valread; /* Variable to store data read from a port */  
/* Calculate register addresses */  
porta = BASE_ADDRESS + PORTAoffset;  
portb = BASE_ADDRESS + PORTBoffset;  
portc = BASE_ADDRESS + PORTCoffset;  
cnfg = BASE_ADDRESS + CNFGoffset;  
/* EXAMPLE 1*/  
outp(cnfg,0x80);  
outp(porta,0x12);  
outp(portb,0x34);  
/* Ports A, B, and C are outputs. */  
/* Write data to port A. */  
/* Write data to port B. */  
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Appendix C Register-Level Programming  
outp(portc,0x56);  
/* EXAMPLE 2*/  
/* Write data to port C. */  
outp(cnfg,0x90);  
/* Port A is input; ports B and C are outputs. */  
/* Write data to port B. */  
/* Write data to port C. */  
outp(portb,0x22);  
outp(portc,0x55);  
valread = inp(porta);  
/* Read data from port A. */  
/* EXAMPLE 3 */  
outp(cnfg,0x82);  
/* Ports A and C are outputs;  
port B is an input. */  
/* EXAMPLE 4 */  
outp(cnfg,0x89);  
/* Ports A and B are outputs;  
port C is an input. */  
}
Mode 1—Strobed Input  
In mode 1, the digital I/O bits are divided into two groups: group A and  
group B. Each of these groups contains one 8-bit port and one 3-bit  
control/data port. The 8-bit port can be either an input or an output port,  
and the 3-bit port is used for control and status information for the 8-bit  
port. The transfer of data is synchronized by handshaking signals in the  
3-bit port.  
The control word written to the CNFG Register to configure port A for  
input in mode 1 is shown as follows. Use bits PC6 and PC7 of port C as  
extra input or output lines.  
D7  
1
D6  
0
D5  
1
D3  
1/0  
D2  
X
D1  
X
D0  
X
D4  
1
Port C bits PC6 and PC7  
1 = input  
0 = output  
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Appendix C Register-Level Programming  
The control word written to the CNFG Register to configure port B for  
input in mode 1 is shown as follows. Notice that port B does not have  
extra input or output lines left from port C when ports A and B are both  
enabled for handshaking.  
D7  
1
D6  
X
D5  
X
D3  
X
D2  
1
D1  
1
D0  
X
D4  
X
During a mode 1 data read transfer, the status of the handshaking lines  
and interrupt signals can be obtained by reading port C. The port C  
status-word bit definitions for an input transfer are shown as follows.  
Port C status-word bit definitions for input (port A and port B):  
D7  
I/O  
D6  
I/O  
D5  
D4  
D3  
D2  
D1  
D0  
IBFA  
INTEA  
INTRA  
INTEB  
IBFB  
INTRB  
Bit  
Name  
Description  
7–6  
I/O  
Input/Output—These bits can be used for general-  
purpose I/O when port A is in mode 1 input. If these  
bits are configured for output, the port C bit set/reset  
function must be used to manipulate them.  
5
4
IBFA  
Input Buffer for Port A—A high setting indicates that  
data has been loaded into the input latch for port A.  
INTEA  
Interrupt Enable Bit for Port A—Setting this bit  
enables interrupts from port A of the 82C55A. This bit  
is controlled by setting/resetting PC4.  
3
2
1
INTRA  
INTEB  
IBFB  
Interrupt Request Status for Port A—When INTEA  
and IBFA are high, this bit is high, indicating that an  
interrupt request is pending for port A.  
Interrupt Enable Bit for Port B—Setting this bit  
enables interrupts from port B of the 82C55A. This bit  
is controlled by setting/resetting PC2.  
Input Buffer for Port B—A high setting indicates that  
data has been loaded into the input latch for port B.  
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Appendix C Register-Level Programming  
0
INTRB  
Interrupt Request Status for Port B—When INTEB  
and IBFB are high, this bit is high, indicating that an  
interrupt request is pending for port B.  
At the digital I/O connector, port C has the following pin assignments  
when in mode 1 input. Notice that the status of STBA* and the status of  
STBB* are not included in the port C status word.  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
I/O  
I/O  
IBFA  
Group A  
Group B  
STBA*  
INTRA  
STBB*  
IBFB  
INTRB  
Figure C-2. Port C Pin Assignments, Mode 1 Input  
Mode 1 Input Programming Example  
The following example shows how to configure PPI A for various  
combinations of mode 1 input. This code is strictly an example and is  
not intended to be used without modification in a practical situation.  
Main() {  
#define BASE_ADDRESS  
#define PORTAoffset  
#define PORTBoffset  
#define PORTCoffset  
#define CNFGoffset  
0x180  
0x00  
0x01  
0x02  
0x03  
/* Board located at address 180 */  
/* Offset for port A */  
/* Offset for port B */  
/* Offset for port C */  
/* Offset for CNFG */  
unsigned int porta, portb, portc, cnfg;  
char valread; /* Variable to store data read from a port */  
/* Calculate register addresses */  
porta = BASE_ADDRESS + PORTAoffset;  
portb = BASE_ADDRESS + PORTBoffset;  
portc = BASE_ADDRESS + PORTCoffset;  
cnfg = BASE_ADDRESS + CNFGoffset;  
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Appendix C Register-Level Programming  
/* EXAMPLE 1–port A input */  
outp(cnfg,0xB0);  
while (!(inp(portc) & 0x20));  
/* Port A is an input in mode 1. */  
/* Wait until IBFA is set,  
indicating that data has been  
loaded in port A. */  
valread = inp(porta);  
/* Read the data from port A. */  
/* EXAMPLE 2–Port B input */  
outp(cnfg,0x86);  
while (!(inp(portc) & 0x02));  
/* Port B is an input in mode 1. */  
/* Wait until IBFB is set,  
indicating that data has been  
loaded in port B. */  
valread = inp(portb);  
}
Mode 1—Strobed Output  
The control word written to the CNFG Register to configure port A for  
output in mode 1 is shown as follows. Bits PC4 and PC5 of port C can  
be used as extra input or output lines.  
D7  
1
D6  
0
D5  
1
D3  
1/0  
D2  
X
D1  
X
D0  
X
D4  
0
Port C bits PC4 and PC5  
1 = input  
0 = output  
The control word written to the CNFG Register to configure port B for  
output in mode 1 is shown as follows. Notice that port B does not have  
extra input or output lines left from port C when ports A and B are both  
enabled for handshaking.  
D7  
1
D6  
X
D5  
X
D3  
X
D2  
1
D1  
1
D0  
X
D4  
X
During a mode 1 data write transfer, the status of the handshaking lines  
and interrupt signals can be obtained by reading port C. Notice that the  
bit definitions are different for a write and a read transfer.  
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Appendix C Register-Level Programming  
Port C status-word bit definitions for output (port A and port B):  
D7  
D6  
D5  
I/O  
D4  
I/O  
D3  
D2  
D1  
D0  
OBFA*  
INTEA  
INTRA  
INTEB  
OBFB*  
INTRB  
Bit  
Name  
Description  
7
OBFA*  
Output Buffer for Port A—A low setting indicates that  
the CPU has written data to port A.  
6
INTEA  
Interrupt Enable Bit for Port A—Setting this bit  
enables interrupts from port A of the 82C55A. This bit  
is controlled by setting/resetting PC6.  
5–4  
I/O  
Input/Output—These bits can be used for general-  
purpose I/O when port A is in mode 1 output. If these  
bits are configured for output, the port C bit set/reset  
function must be used to manipulate them.  
3
2
INTRA  
INTEB  
Interrupt Request Status for Port A—When INTEA  
and OBFA* are high, this bit is high, indicating that an  
interrupt request is pending for port A.  
Interrupt Enable Bit for Port B—Setting this bit  
enables interrupts from port B of the 82C55A. This bit  
is controlled by setting/resetting PC2.  
1
0
OBFB*  
INTRB  
Output Buffer for Port B—A low setting indicates that  
the CPU has written data to port B.  
Interrupt Request Status for Port B—When INTEB  
and OBFB* are high, this bit is high, indicating that an  
interrupt request is pending for port B.  
At the digital I/O connector, port C has the following pin assignments  
when in mode 1 output. Notice that the status of ACKA* and the status  
of ACKB* are not included when port C is read.  
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Appendix C Register-Level Programming  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
OBFA*  
ACKA*  
I/O  
Group A  
Group B  
I/O  
INTRA  
ACKB*  
OBFB*  
INTRB  
Figure C-3. Port C Pin Assignments, Mode 1 Output  
Mode 1 Output Programming Example  
The following example shows how to configure PPI A for various  
combinations of mode 1 output. This code is strictly an example and is  
not intended to be used without modification in a practical situation.  
Main() {  
#define BASE_ADDRESS  
#define PORTAoffset  
#define PORTBoffset  
#define PORTCoffset  
#define CNFGoffset  
0x180  
0x00  
0x01  
0x02  
0x03  
/* Board located at address 180 */  
/* Offset for port A */  
/* Offset for port B */  
/* Offset for port C */  
/* Offset for CNFG */  
unsigned int porta, portb, portc, cnfg;  
char valread; /* Variable to store data read from a port */  
/* Calculate register addresses */  
porta = BASE_ADDRESS + PORTAoffset;  
portb = BASE_ADDRESS + PORTBoffset;  
portc = BASE_ADDRESS + PORTCoffset;  
cnfg = BASE_ADDRESS + CNFGoffset;  
/* EXAMPLE 1–port A output */  
outp(cnfg,0xA0);  
while (!(inp(portc) & 0x80));  
/* Port A is an output in mode 1.*/  
/* Wait until OBFA* is set,  
indicating that the data last  
written to port A has been  
read.*/  
outp(porta,0x12);  
/* Write data to port A. */  
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Appendix C Register-Level Programming  
/* EXAMPLE 2–port B output */  
outp(cnfg,0x84);  
while (!(inp(portc) & 0x02));  
/* Port B is an output in mode 1.*/  
/* Wait until OBFB* is set,  
indicating that the data last  
written to port B has been  
read.*/  
outp(portb,0x34);  
}
/* Write the data to port B. */  
Mode 2—Bidirectional Bus  
Mode 2 has an 8-bit bus that can transfer both input and output data  
without changing the configuration. The data transfers are synchronized  
with handshaking lines in port C. This mode uses only port A; however,  
port B can be used in either mode 0 or mode 1 while port A is configured  
for mode 2.  
The control word written to the CNFG Register to configure port A as  
a bidirectional data bus in mode 2 is shown as follows. If port B is  
configured for mode 0, then PC2, PC1, and PC0 of port C can be used  
as extra input or output lines.  
D7  
1
D6  
1
D5  
X
D3  
X
D2  
1/0  
D1  
1/0  
D0  
1/0  
D4  
X
Port C  
(PC2-PC0)  
1 = input  
0 = output  
Port B  
1 = input  
0 = output  
Group B Mode  
0 = mode 0  
1 = mode 1  
Figure C-4. Port A Configured as a Bidirectional Data Bus in Mode 2  
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Appendix C Register-Level Programming  
During a mode 2 data transfer, the status of the handshaking lines and  
interrupt signals can be obtained by reading port C. The port C status-  
word bit definitions for a mode 2 transfer are shown as follows.  
Port C status-word bit definitions for bidirectional data path (port A  
only):  
D7  
D6  
D5  
D4  
D3  
D2  
I/O  
D1  
I/O  
D0  
I/O  
OBFA*  
INTE1  
IBFA  
INTE2  
INTRA  
Bit  
Name  
Description  
7
OBFA*  
Output Buffer for Port A—A low setting indicates that  
the CPU has written data to port A.  
6
INTE1  
Interrupt Enable Bit for Port A Output Interrupts—  
Setting this bit enables output interrupts from port A  
of the 82C55A. This bit is controlled by  
setting/resetting PC6.  
5
4
IBFA  
Input Buffer for Port A—A high setting indicates that  
data has been loaded into the input latch of port A.  
INTE2  
Interrupt Enable Bit for Port A Input Interrupts—  
Setting this bit enables input interrupts from port A of  
the 82C55A. This bit is controlled by setting/resetting  
PC4.  
3
INTRA  
Interrupt Request Status for Port A—If INTE1 and  
IBFA are high, then this bit is high, indicating that an  
interrupt request is pending for port A input transfers.  
If INTE2 and OBFA* are high, then this bit is high,  
indicating that an interrupt request is pending for  
port A output transfers.  
2–0  
I/O  
Input/Output—These bits can be used for general-  
purpose I/O lines if group B is configured for mode 0.  
If group B is configured for mode 1, refer to the bit  
explanations shown in the preceding mode 1 sections.  
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Appendix C Register-Level Programming  
At the digital I/O connector, port C has the following pin assignments  
when in mode 2. Notice that the status of STBA* and the status of  
ACKA* are not included in the port C status word.  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
OBFA*  
ACKA*  
IBFA  
STBA*  
INTRA  
#
Group A  
Group B  
#
#
#
The three port C lines associated with group B function are based on the mode selected  
for group B; that is, if group B is configured for mode 0, PC2-PC0 function as general-  
purpose input/output, but if group B is configured for mode 1 input or output, PC2-  
PC0 function as handshaking lines as shown in the preceding mode 1 sections.  
Figure C-5. Port C Pin Assignments, Mode 2  
Mode 2 Programming Example  
The following example shows how to configure PPI A for mode 2 input  
and output and how to use the handshaking signals to control data flow.  
This code is strictly an example and is not intended to be used without  
modification in a practical situation.  
Main() {  
#define BASE_ADDRESS  
#define PORTAoffset  
#define PORTBoffset  
#define PORTCoffset  
#define CNFGoffset  
0x180  
0x00  
0x01  
0x02  
0x03  
/* Board located at address 180 */  
/* Offset for port A */  
/* Offset for port B */  
/* Offset for port C */  
/* Offset for CNFG */  
unsigned int porta, portb, portc, cnfg;  
char valread; /* Variable to store data read from a port */  
/* Calculate register addresses */  
porta = BASE_ADDRESS + PORTAoffset;  
portb = BASE_ADDRESS + PORTBoffset;  
portc = BASE_ADDRESS + PORTCoffset;  
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Appendix C Register-Level Programming  
cnfg = BASE_ADDRESS + CNFGoffset;  
/* EXAMPLE 1*/  
outp(cnfg,0xC0);  
while (!(inp(portc) & 0x80));  
/* Port A is in mode 2. */  
/* Wait until OBFA* is set,  
indicating that the data last  
written to port A has been read.  
*/  
outp(porta,0x67);  
while (!(inp(portc) & 0x20));  
/* Write the data to port A. */  
/* Wait until IBFA is set,  
indicating that data is  
available in port A to be read.  
*/  
valread = inp(porta);  
}
/* Read data from port A. */  
Interrupt Programming Examples for the 82C55A  
The following examples show the process required to enable interrupts  
for several different operating modes. The interrupt handling routines  
and interrupt installation routines for the 82C55A are not included.  
Consult your computer technical reference manual for additional  
information. Also, if you generate interrupts with the PC3 or PC0 lines  
of the 82C55A devices, you must maintain the active high level until the  
interrupt service routine is entered. Otherwise, the host computer  
considers the interrupt a spurious interrupt and routes the request to the  
channel responsible for handling spurious interrupts. To prevent this  
problem, try using some other I/O bit to send feedback to the device  
generating the interrupt. In this way, the interrupting device can be  
signaled that the interrupt service routine has been entered. For further  
information on using PC3 and PC0 for interrupts, see the Interrupt  
Handling section later in this appendix.  
Note:  
The following code applies to the PC-DIO-24PnP. To adapt this code to the  
PC-DIO-24 (non-PnP), remove the outp(ireg1)instructions and  
replace outp(ireg2,0x04)with the following (assuming you use PC4  
as your interrupt enable):  
outp (cnfg, 0x08) /* Clear PC4 to enable interrupts */  
You cannot use PC4 as your interrupt enable in examples 1, 5, or 6,  
because these configurations use PC4 for handshaking.  
PC-DIO-24/PnP User Manual  
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Appendix C Register-Level Programming  
Main() {  
#define BASE_ADDRESS  
#define PORTAoffset  
#define PORTBoffset  
#define PORTCoffset  
#define CNFGoffset  
#define IREG1offset  
#define IREG2offset  
0x180  
0x00  
0x01  
0x02  
0x03  
0x14  
0x15  
/* Board located at address 180 */  
/* Offset for port A */  
/* Offset for port B */  
/* Offset for port C */  
/* Offset for CNFG */  
/* Offset for Interrupt Reg. 1 */  
/* Offset for Interrupt Reg. 2 */  
unsigned int porta, portb, portc, cnfg, ireg1, ireg2;  
char valread;  
/* Variable to store data read from a port */  
/* Calculate register addresses */  
porta = BASE_ADDRESS + PORTAoffset;  
portb = BASE_ADDRESS + PORTBoffset;  
portc = BASE_ADDRESS + PORTCoffset;  
cnfg = BASE_ADDRESS + CNFGoffset;  
ireg1 = BASE_ADDRESS + IREG1offset;  
ireg2 = BASE_ADDRESS + IREG2offset;  
/* EXAMPLE 1–Set up interrupts for mode 1 input for port A. Enable the  
appropriate interrupt bits. */  
outp(cnfg,0xB0);  
outp(cnfg,0x09);  
outp(ireg1,0x01);  
outp(ireg2,0x04);  
/* Port A is an input in mode 1. */  
/* Set PC4 to enable interrupts from 82C55A. */  
/* Set IRQ0 to enable port A interrupts. */  
/* Set INTEN bit. */  
/* EXAMPLE 2–Set up interrupts for mode 1 input for port B. Enable the  
appropriate interrupt bits. */  
outp(cnfg,0x86);  
outp(cnfg,0x05);  
outp(ireg1,0x02);  
outp(ireg2,0x04);  
/* Port B is an input in mode 1. */  
/* Set PC2 to enable interrupts from 82C55A. */  
/* Set IRQ1 to enable port B interrupts. */  
/* Set INTEN bit. */  
/* EXAMPLE 3–Set up interrupts for mode 1 output for port A. Enable the  
appropriate interrupt bits. */  
outp(cnfg,0xA0);  
outp(cnfg,0x0D);  
outp(ireg1,0x01);  
outp(ireg2,0x04);  
/* Port A is an output in mode 1. */  
/* Set PC6 to enable interrupts from 82C55A. */  
/* Set IRQ0 to enable port A interrupts. */  
/* Set INTEN bit. */  
/* EXAMPLE 4–Set up interrupts for mode 1 output for port B. Enable the  
appropriate interrupt bits. */  
outp(cnfg,0x84);  
outp(cnfg,0x05);  
/* Port B is an output in mode 1. */  
/* Set PC2 to enable interrupts from 82C55A. */  
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Appendix C Register-Level Programming  
outp(ireg1,0x02);  
outp(ireg2,0x04);  
/* Set IRQ1 to enable port B interrupts. */  
/* Set INTEN bit. */  
/* EXAMPLE 5–Set up interrupts for mode 2 output transfers. Enable the  
appropriate interrupt bits. */  
outp(cnfg,0xC0);  
outp(cnfg,0x0D);  
outp(ireg1,0x01);  
outp(ireg2,0x04);  
/* Mode 2 output. */  
/* Set PC6 to enable interrupts from 82C55A. */  
/* Set IRQ0 to enable port A interrupts. */  
/* Set INTEN bit. */  
/* EXAMPLE 6–Set up interrupts for mode 2 input transfers. Enable the  
appropriate interrupt bits. */  
outp(cnfg,0xD0);  
outp(cnfg,0x09);  
outp(ireg1,0x01);  
outp(ireg2,0x04);  
}
/* Mode 2 input. */  
/* Set PC4 to enable interrupts from 82C55A. */  
/* Set IRQ0 to enable port A interrupts. */  
/* Set INTEN bit. */  
Note:  
This section applies only to the PC-DIO-24PnP. The PC-DIO-24  
(non-PnP) does not implement the IRQ1, IRQ2, or INTEN bits. To enable  
and disable interrupts on the non-PnP board, see Appendix D, Using Your  
PC-DIO-24 (Non-PnP) Board.  
On the PC-DIO-24PnP, the INTEN bit of Interrupt Register 2 must be  
set to enable interrupts. This bit must first be cleared to disable  
unwanted interrupts. After all sources of interrupts have been disabled  
or placed in an inactive state, you can set INTEN.  
To interrupt the host computer, program the selected 82C55A port for  
the I/O mode desired. In mode 1, set either the INTEA or the INTEB bit  
to enable interrupts from port A or port B, respectively. In mode 2, set  
either INTE1 or INTE2 for interrupts on output or input transfers,  
respectively. The INTE1 and INTE2 interrupt outputs are cascaded into  
a single interrupt output for port A. After enabling interrupts from the  
82C55A, set the appropriate enable bit in Interrupt Control Register 1;  
for example, if you selected both mode 2 interrupts for port A, you  
would set IRQ0 in order to interrupt the host computer.  
External signals can be used to interrupt the PC-DIO-24/PnP when  
port A or port B is in mode 0 and the low nibble of port C is configured  
for input. If port A is in mode 0, use PC3 to generate an interrupt; if  
PC-DIO-24/PnP User Manual  
C-22  
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Appendix C Register-Level Programming  
port B is in mode 0, use PC0 to generate an interrupt. Once you have  
configured the 82C55A, set the corresponding interrupt enable bit in  
Interrupt Control Register 1. If you are using PC3, set IRQ0; if you are  
using PC0, set IRQ1. When the external signal becomes logic high, an  
interrupt request occurs. Although the host computer’s interrupt-  
monitoring circuitry is triggered by the positive-going edge of the  
interrupt signal, the signal must remain high until the interrupt routine  
has been entered and interrupts have been masked out. Make sure your  
external interrupt signal meets these qualifications. To disable the  
external interrupt, clear the appropriate IRQ bit or clear the INTEN bit.  
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Appendix  
Using Your PC-DIO-24  
(Non-PnP) Board  
D
This appendix describes the differences between the PC-DIO-24 and  
PC-DIO-24PnP boards, the PC-DIO-24 board configuration, and the  
PC-DIO-24 installation into your computer. Read this appendix only if  
you do not have the Plug and Play version of the board.  
Differences between the PC-DIO-24PnP and  
the PC-DIO-24  
The PC-DIO-24PnP is a Plug and Play upgrade from a legacy board, the  
PC-DIO-24. Legacy board refers to a board with switches and jumpers  
used to set the addresses and interrupt levels. The original legacy board  
was replaced with a backwards-compatible, revised PC-DIO-24 that has  
many of the new features of the Plug and Play version. The following  
list compares the specifications and functionality of the newer boards  
with the original legacy board. This document applies only to the  
revised PC-DIO-24/PnP board.  
Table D-1. Comparison of Characteristics  
Specification  
Original PC-DIO-24  
Revised PC-DIO-24  
PC-DIO-24PnP  
I/O base address  
selection  
Uses switches  
Uses switches  
Plug and Play  
compatible  
Interrupt request  
selection  
Uses jumpers  
Uses jumpers  
Plug and Play  
compatible  
Interrupt request  
enable  
Uses one port C line  
(jumper selectable)  
Uses one port C line  
(jumper selectable)  
Software-controlled  
(uses interrupt control  
registers)  
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Appendix D Using Your PC-DIO-24 (Non-PnP) Board  
Table D-1. Comparison of Characteristics (Continued)  
Specification  
5 V supply fuse  
Power-up state  
Original PC-DIO-24  
Revised PC-DIO-24  
PC-DIO-24PnP  
Nonresettable  
Self-resetting  
Self-resetting  
No pullups or  
pulldowns  
Jumper for pullup  
(factory default)  
or pulldown  
Jumper for pullup  
(factory default)  
or pulldown  
Configuration  
The PC-DIO-24 contains one DIP switch and two jumpers to configure  
Figure D-1 shows the location of DIP switch U9 and jumper  
sets W2 and W3.  
The PC-DIO-24 is configured at the factory to a base I/O address of hex  
settings (shown in Table D-2) are suitable for most systems. However,  
if your system has other hardware at this base I/O address, interrupt  
enable line, or interrupt level, you need to change these settings on the  
PC-DIO-24 (as described in the following pages) or on the other  
hardware. Record your settings in the PC-DIO-24/PnP Hardware and  
Software Configuration Form in Appendix E, Customer  
Communication.  
Table D-2. PC-DIO-24 Factory-Set Jumper and Switch Settings  
Base I/O Address  
Hex 210 (factory setting)  
Interrupt Enable Line  
Interrupt Level  
PC4 (factory setting)  
Interrupt level 5 selected  
(factory setting)  
W2: Row PC4  
W3: IRQ5  
1
2
3
4
5
6
7
8
U9  
PC-DIO-24/PnP User Manual  
D-2  
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Appendix D Using Your PC-DIO-24 (Non-PnP) Board  
2
1
4
3
1
W2  
2
W3  
3
U9  
4
Product Name  
Figure D-1. PC-DIO-24 Parts Locator Diagram  
Base I/O Address Settings  
The base I/O address for the PC-DIO-24 is determined by the switches  
at position U9 (see Figure 2-1). The switches are set at the factory for  
the I/O address hex 210. With this default setting, the PC-DIO-24 uses  
the I/O address space hex 210 through 213.  
Note:  
Verify that this space is not already used by other equipment installed in  
your computer. If any equipment in your computer uses this I/O address  
space, you must change the base I/O address for the PC-DIO-24 or for the  
other device.  
Each switch in U9 corresponds to one of the address lines A9  
through A2. For space reasons, not all address lines are separately  
labeled on the board. The range for possible base I/O address settings is  
hex 000 through 3FC. Base I/O address values hex 000 through 0FF are  
reserved for system use. Base I/O values hex 100 through 3FF are  
available on the I/O channel. A1 and A0 are used by the PC-DIO-24 to  
decode the onboard registers. On the U9 DIP switches, press the side  
marked OFF to select a binary value of 1 for the corresponding address  
bit. Press the other side of the switch to select a binary value of 0 for the  
corresponding address bit. Figure D-2 shows two possible switch  
settings.  
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Appendix D Using Your PC-DIO-24 (Non-PnP) Board  
1
2
3
4
5
6
7
8
U9  
a. Switches Set to Base I/O Address Hex 210 (Default Setting)  
1
2
3
4
5
6
7
8
U9  
b. Switches Set to Base I/O Address Hex 278  
Figure D-2. Example Base I/O Address Switch Settings  
Table D-3 shows some examples of switch settings and their  
corresponding address ranges.  
PC-DIO-24/PnP User Manual  
D-4  
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Appendix D Using Your PC-DIO-24 (Non-PnP) Board  
Table D-3. Example Switch Settings with Corresponding Base I/O Address and I/O Address Space  
Switch Setting  
Base I/O  
I/O Address  
A9 A8 A7 A6 A5 A4 A3 A2 Address (hex)  
Space Used (hex)  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
100  
120  
140  
160  
180  
1A0  
1C0  
1E0  
200  
220  
240  
260  
280  
2A0  
2C0  
2E0  
300  
100–103  
120–123  
140–143  
160–163  
180–183  
1A0–1A3  
1C0–1C3  
1E0–1E3  
200–203  
220–223  
240–243  
260–263  
280–283  
2A0–2A3  
2C0–2C3  
2E0–2E3  
300–303  
Note: Base I/O address values 000 through 0FF hex are reserved for system use. Base I/O address values  
100 through 3FF hex are available on the I/O channel.  
Interrupt Selection  
There are two sets of jumpers for interrupt selection on the PC-DIO-24  
board. W3 is used for selecting the interrupt enable line. W2 is for  
selecting the interrupt level. The location of these jumpers is shown in  
Figure D-1.  
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Appendix D Using Your PC-DIO-24 (Non-PnP) Board  
Interrupt Enable Settings  
jumper W3 to select PC2, PC4, or PC6 as the active low interrupt enable  
line. When the interrupt enable line is logic low, interrupts are enabled  
from the PC-DIO-24 board. Refer to Chapter 4, Theory of Operation,  
for the suggested interrupt enable line setting for each digital I/O mode  
of operation. If W3 is set to N/C, all interrupt requests from the  
PC-DIO-24 are disabled. Figure D-3 shows the possible jumper settings  
for W3. The board ships with this jumper set to PC4; therefore, interrupt  
requests from the board are enabled and controlled by PC4.  
W3  
W3  
W3  
W3  
PC6  
PC4  
PC2  
N/C  
PC6  
PC4  
PC2  
N/C  
PC6  
PC4  
PC2  
N/C  
PC6  
PC4  
PC2  
N/C  
INT  
PC6 Selected  
INT  
INT  
PC2 Selected  
INT  
PC4 Selected  
(Default Factory  
Setting)  
Interrupt  
Disabled  
Figure D-3. Interrupt Enable Jumper Settings  
Interrupt Level Settings  
The PC-DIO-24 board can connect to any one of the six interrupt lines  
of the PC I/O Channel: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, or IRQ9. You  
select the interrupt line by setting a jumper on W2. To use the interrupt  
capability of the board, select an interrupt line and place the jumper in  
the appropriate position. The default interrupt line is IRQ5. To change  
to another line, remove the jumper from IRQ5 and place it on the pins  
for another request line. Figure D-4 shows the default factory setting for  
IRQ5.  
W2  
Figure D-4. Interrupt Jumper Setting for IRQ5 (Factory Setting)  
PC-DIO-24/PnP User Manual  
D-6  
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Appendix D Using Your PC-DIO-24 (Non-PnP) Board  
The PC-DIO-24 uses a tristate driver to drive its selected interrupt line.  
The PC-DIO-24 can therefore share an interrupt line if your system and  
Installation  
Install the PC-DIO-24 as described in Chapter 2, Installation and  
Configuration.  
If you have an ISA-class computer and you are using a configurable  
software package, such as NI-DAQ, you may need to reconfigure your  
software to reflect any changes in jumper or switch settings. If you have  
an EISA-class computer, you need to update the computer resource  
allocation (or configuration) table by reconfiguring your computer. See  
your computer user manual for information about updating the  
configuration table.  
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Appendix  
www.natinst.com/documentation/daq  
E
Customer Communication  
For your convenience, this appendix contains forms to help you gather the information necessary  
to help us solve your technical problems and a form you can use to comment on the product  
documentation. When you contact us, we need the information on the Technical Support Form and  
the configuration form, if your manual contains one, about your system configuration to answer your  
questions as quickly as possible.  
National Instruments has technical assistance through electronic, fax, and telephone systems to quickly  
provide the information you need. Our electronic services include a bulletin board service, an FTP site,  
a fax-on-demand system, and e-mail support. If you have a hardware or software problem, first try the  
electronic support systems. If the information available on these systems does not answer your  
questions, we offer fax and telephone support through our technical support centers, which are staffed  
by applications engineers.  
Electronic Services  
Bulletin Board Support  
National Instruments has BBS and FTP sites dedicated for 24-hour support with a collection of files  
and documents to answer most common customer questions. From these sites, you can also download  
the latest instrument drivers, updates, and example programs. For recorded instructions on how to use  
the bulletin board and FTP services and for BBS automated information, call 512 795 6990. You can  
access these services at:  
United States: 512 794 5422  
Up to 14,400 baud, 8 data bits, 1 stop bit, no parity  
United Kingdom: 01635 551422  
Up to 9,600 baud, 8 data bits, 1 stop bit, no parity  
France: 01 48 65 15 59  
Up to 9,600 baud, 8 data bits, 1 stop bit, no parity  
FTP Support  
To access our FTP site, log on to our Internet host, ftp.natinst.com, as anonymousand use  
your Internet address, such as [email protected], as your password. The support files and  
documents are located in the /supportdirectories.  
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Fax-on-Demand Support  
Fax-on-Demand is a 24-hour information retrieval system containing a library of documents on a wide  
range of technical information. You can access Fax-on-Demand from a touch-tone telephone at  
512 418 1111.  
E-Mail Support (Currently USA Only)  
You can submit technical support questions to the applications engineering team through e-mail at the  
Internet address listed below. Remember to include your name, address, and phone number so we can  
contact you with solutions and suggestions.  
Telephone and Fax Support  
National Instruments has branch offices all over the world. Use the list below to find the technical  
support number for your country. If there is no National Instruments office in your country, contact  
the source from which you purchased your software to obtain support.  
Country  
Telephone  
Fax  
Australia  
Austria  
Belgium  
Brazil  
Canada (Ontario)  
Canada (Québec)  
Denmark  
Finland  
03 9879 5166  
0662 45 79 90 0  
02 757 00 20  
011 288 3336  
905 785 0085  
514 694 8521  
45 76 26 00  
09 725 725 11  
01 48 14 24 24  
089 741 31 30  
2645 3186  
03 6120092  
02 413091  
03 5472 2970  
02 596 7456  
5 520 2635  
03 9879 6277  
0662 45 79 90 19  
02 757 03 11  
011 288 8528  
905 785 0086  
514 694 4399  
45 76 26 02  
09 725 725 55  
01 48 14 24 14  
089 714 60 35  
2686 8505  
France  
Germany  
Hong Kong  
Israel  
Italy  
Japan  
03 6120095  
02 41309215  
03 5472 2977  
02 596 7455  
5 520 3282  
Korea  
Mexico  
Netherlands  
Norway  
Singapore  
Spain  
Sweden  
Switzerland  
Taiwan  
0348 433466  
32 84 84 00  
2265886  
91 640 0085  
08 730 49 70  
056 200 51 51  
02 377 1200  
01635 523545  
512 795 8248  
0348 430673  
32 84 86 00  
2265887  
91 640 0533  
08 730 43 70  
056 200 51 55  
02 737 4644  
01635 523154  
512 794 5678  
United Kingdom  
United States  
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Technical Support Form  
Photocopy this form and update it each time you make changes to your software or hardware, and use  
the completed copy of this form as a reference for your current configuration. Completing this form  
accurately before contacting National Instruments for technical support helps our applications  
engineers answer your questions more efficiently.  
If you are using any National Instruments hardware or software products related to this problem,  
include the configuration forms from their user manuals. Include additional pages if necessary.  
Name __________________________________________________________________________  
Company _______________________________________________________________________  
Address ________________________________________________________________________  
_______________________________________________________________________________  
Fax ( ___ )___________________ Phone ( ___ ) _______________________________________  
Computer brand ________________ Model ________________ Processor___________________  
Operating system (include version number) ____________________________________________  
Clock speed ______MHz RAM _____MB  
Mouse ___yes ___no Other adapters installed _______________________________________  
Hard disk capacity _____MB Brand _____________________________________________  
Display adapter __________________________  
Instruments used _________________________________________________________________  
_______________________________________________________________________________  
National Instruments hardware product model __________ Revision ______________________  
Configuration ___________________________________________________________________  
National Instruments software product ____________________________Version ____________  
Configuration ___________________________________________________________________  
The problem is: __________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
List any error messages: ___________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
The following steps reproduce the problem:____________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
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PC-DIO-24/PnP Hardware and Software Configuration  
Form  
Record the settings and revisions of your hardware and software on the line to the right of each item.  
Complete a new copy of this form each time you revise your software or hardware configuration, and  
use this form as a reference for your current configuration. Completing this form accurately before  
contacting National Instruments for technical support helps our applications engineers answer your  
questions more efficiently.  
National Instruments Products  
DAQ hardware ___________________________________________________________________  
Interrupt level of hardware __________________________________________________________  
Base I/O address of hardware ________________________________________________________  
Programming choice _______________________________________________________________  
National Instruments application software version _______________________________________  
Other boards in system _____________________________________________________________  
Base I/O addresses of other boards ____________________________________________________  
DMA channels of other boards _______________________________________________________  
Interrupt levels of other boards _______________________________________________________  
Other Products  
Computer make and model _________________________________________________________  
Microprocessor ___________________________________________________________________  
Clock frequency or speed ___________________________________________________________  
Type of video board installed ________________________________________________________  
Operating system version ___________________________________________________________  
Operating system mode ____________________________________________________________  
Programming language ____________________________________________________________  
Programming language version ______________________________________________________  
Other boards in system _____________________________________________________________  
Base I/O addresses of other boards ___________________________________________________  
Interrupt enable lines of other boards __________________________________________________  
Interrupt levels of other boards ______________________________________________________  
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Documentation Comment Form  
National Instruments encourages you to comment on the documentation supplied with our products.  
This information helps us provide quality products to meet your needs.  
Click here to comment on this document via the  
National Instruments website at  
Title:  
PC-DIO-24/PnP User Manual  
Edition Date: February 1998  
www.natinst.com/documentation/daq  
Part Number: 320288C-01  
Please comment on the completeness, clarity, and organization of the manual.  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
If you find errors in the manual, please record the page numbers and describe the errors.  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
_______________________________________________________________________________  
Thank you for your help.  
Name _________________________________________________________________________  
Title __________________________________________________________________________  
Company _______________________________________________________________________  
Address ________________________________________________________________________  
_______________________________________________________________________________  
Phone ( ___ )__________________________ Fax ( ___ ) ________________________________  
Mail to: Technical Publications  
National Instruments Corporation  
Fax to: Technical Publications  
National Instruments Corporation  
(512) 794-5678  
6504 Bridge Point Parkway  
Austin, TX 78730-5039  
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Glossary  
Prefix  
µ-  
Meanings  
micro-  
milli-  
Value  
10-6  
10-3  
103  
m-  
k-  
kilo-  
M-  
mega-  
106  
Symbols  
°
degrees  
negative of, or minus  
/
ohms  
per  
%
+
percent  
positive of, or plus  
A
A
ampere  
AC  
alternating current  
address  
character code that identifies a specific location (or series of locations)  
in memory  
AWG  
American Wire Gauge  
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Glossary  
B
b
bit—one binary digit, either 0 or 1  
B
byte—eight related bits of data, an eight-bit binary number. Also used  
to denote the amount of memory required to store one byte of data.  
base address  
a memory address that serves as the starting address for programmable  
registers busthe group of conductors that interconnect individual  
circuitry in a computer. Typically, a bus is the expansion vehicle to  
which I/O or other devices are connected. Examples of PC buses are the  
ISA and PCI bus. All other addresses are located by adding to the base  
address.  
BCD  
binary-coded decimal  
C
C
Celsius  
channel  
pin or wire lead to which you apply or from which you read the analog  
or digital signal. Analog signals can be single-ended or differential. For  
digital signals, you group channels to form ports. Ports usually consist  
of either four or eight digital channels.  
D
D/A  
digital-to-analog data acquisition—(1) collecting and measuring  
electrical signals from sensors, transducers, and test probes or fixtures  
and inputting them to a computer for processing; (2) collecting and  
measuring the same kinds of electrical signals with A/D and/or DIO  
boards plugged into a computer, and possibly generating control signals  
with D/A and/or DIO boards in the same computer  
DC  
direct current  
digital port  
DIO  
See port.  
digital input/output  
direct memory access  
DMA  
PC-DIO-24/PnP User Manual  
G-2  
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Glossary  
F
ft.  
feet  
H
h
hour  
handshaked digital I/O a type of digital acquisition/generation where a device or module  
accepts or transfers data after a digital pulse has been received. Also  
called latched digital I/O.  
hardware  
the physical components of a computer system, such as the circuit  
boards, plug-in boards, chassis, enclosures, peripherals, and cables  
hex  
Hz  
hexadecimal  
hertz—the number of scans read or updates written per second  
I
in.  
inches  
Iin  
input current  
output current  
Iout  
interrupt  
a computer signal indicating that the CPU should suspend its current  
task to service a designated activity  
interrupt level  
I/O  
the relative priority at which a device can interrupt  
input/output—the transfer of data to/from a computer system involving  
communications channels, operator interface devices, and/or data  
acquisition and control interfaces  
IRQ  
interrupt request  
K
3
k
kilo—the standard metric prefix for 1,000, or 10 , used with units of  
measure such as volts, hertz, and meters  
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Glossary  
10  
K
kilo—the prefix for 1,024, or 2 , used with B in quantifying data or  
computer memory  
kbytes  
1,024 bytes  
3
kbytes/s  
a unit for data transfer that means 1,000 or 10 bytes/s  
L
LabVIEW  
LSB  
laboratory virtual instrument engineering workbench  
least significant bit  
M
m
meters  
6
M
(1) Mega, the standard metric prefix for 1 million or 10 , when used  
with units of measure such as volts and hertz; (2) mega, the prefix for  
20  
1,048,576, or 2 , when used with B to quantify data or computer  
memory  
MB  
megabytes of memory  
most significant bit  
MSB  
N
NI-DAQ  
National Instruments driver software for DAQ hardware  
O
operating system  
base-level software that controls a computer, runs programs, interacts  
with users, and communicates with installed hardware or peripheral  
devices  
P
PPI  
programmable peripheral interface  
PC-DIO-24/PnP User Manual  
G-4  
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Glossary  
PnP  
PnP (Plug and Play) refers to a device that is fully compatible with the  
industry standard Plug and Play ISA Specification. All bus-related  
configuration is performed through software, freeing you from  
manually configuring jumpers or switches to set the device base address  
and interrupt level. PnP systems automatically arbitrate and assign  
system resources to a PnP product.  
port  
(1) a communications connection on a computer or a remote controller  
(2) a digital port, consisting of four or eight lines of digital input and/or  
output  
R
RAM  
random-access memory  
resolution  
the smallest signal increment that can be detected by a measurement  
system. Resolution can be expressed in bits, in proportions, or in  
percent of full scale. For example, a system has 12-bit resolution, one  
part in 4,096 resolution, and 0.0244% of full scale.  
REXT  
external resistance  
S
s
seconds  
samples  
S
SCXI  
Signal Conditioning eXtensions for Instrumentation—the National  
Instruments product line for conditioning low-level signals within an  
external chassis near sensors so only high-level signals are sent to DAQ  
boards in the noisy PC environment  
signal conditioning  
S/s  
the manipulation of signals to prepare them for digitizing  
samples per second—used to express the rate at which a DAQ board  
samples an analog signal  
SSR  
solid-state relay  
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Glossary  
V
V
volts  
Vcc  
Supply voltage; for example, the voltage a computer supplies to its  
plug-in devices  
VDC  
VEXT  
VI  
volts direct current  
external volt  
virtual instrument—(1) a combination of hardware and/or software  
elements, typically used with a PC, that has the functionality of a classic  
stand-alone instrument (2) a LabVIEW software module (VI), which  
consists of a front panel user interface and a block diagram program  
PC-DIO-24/PnP User Manual  
G-6  
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Index  
example settings with corresponding  
base I/O address and address space  
(table), D-5  
factory settings (table), D-2  
in use by other equipment (note), D-3  
Special Characters  
+5 V signal  
connection to ground or other voltage source  
(caution), 3-7  
description (table), 3-3  
power connections, 3-7  
self-resetting fuse, 3-7  
82C55A Programmable Peripheral Interface  
capabilities, 1-1  
PC-DIO-24/PnP  
selecting, 2-3  
valid addresses, C-1  
block diagram of PC-DIO-24/PnP, 4-1  
board configuration. See configuration.  
bulletin board support, E-1  
bus interface, 4-2  
data sheet, B-1 to B-17  
modes of operation. See modes of operation,  
82C55A.  
bus transceivers, 4-2  
overview, 4-2  
register description, C-3 to C-5  
control word formats (figure), C-4  
Port C set/reset control words  
(table), C-5  
C
cables, custom, 1-5 to 1-6  
ComponentWorks software, 1-2  
configuration. See also installation.  
PC-DIO-24 (non-PnP), D-2 to D-7  
base I/O address settings, D-3 to D-5  
factory-set jumper and switch settings  
(table), D-2  
A
ACK* signal  
description (table), 3-10  
mode 1 output timing, 3-13  
mode 2 bidirectional timing, 3-14  
Port C signal assignments (table), 3-4  
address, setting. See base I/O address settings.  
application software descriptions, 1-2 to 1-3  
interrupt selection, D-5 to D-7  
parts locator diagram, D-3  
PC-DIO-24/PnP  
base I/O address and interrupt  
selection, 2-3  
general requirements, C-1  
Plug and Play configuration, 2-2  
Configuration Manager, 2-2  
control words  
B
base I/O address settings  
PC-DIO-24 (non-PnP), D-3 to D-5  
example settings (figure), D-4  
control-word formats (figure), C-4  
mode 1 strobed input (figure), C-11 to C-12  
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Index  
mode 1 strobed output (figure), C-13  
mode 2 bidirectional bus (figure), C-17  
Port C set/reset control words (table), C-5  
F
fax and telephone number support, E-2  
Fax-on-Demand support, E-2  
FTP support, E-1  
custom cables, 1-5 to 1-6  
customer communication, xiii, E-1 to E-2  
fuse, self-resetting, for +5 V signal, 3-7  
D
G
DATA signal  
GND signal (table), 3-2  
description (table), 3-11  
mode 1 input timing, 3-12  
mode 1 output timing, 3-13  
mode 2 bidirectional timing, 3-14  
digital I/O connector, 4-3  
digital I/O power-up state selection,  
3-7 to 3-10  
high DIO power-up state, 3-7 to 3-8  
low DIO power-up state, 3-9 to 3-10  
digital I/O signal connections, 3-4 to 3-6  
input specifications (referenced to  
GND), 3-4  
I
IBF signal  
description (table), 3-10  
mode 1 input timing, 3-12  
mode 2 bidirectional timing, 3-14  
Port C signal assignments (table), 3-4  
IBFA bit, Port C, C-12, C-18  
IBFB bit, Port C, C-12  
installation. See also configuration.  
jumper W1 location (figure), 2-1  
PC-DIO-24 (non-PnP), D-7  
PC-DIO-24/PnP, 2-1 to 2-2  
unpacking the PC-DIO-24/PnP, 1-7  
INTE1 bit, Port C, C-18  
output specifications (referenced to  
GND), 3-5  
typical digital I/O applications  
(figure), 3-6  
digital I/O specifications, A-1  
digital logic level specifications  
input signals (table), A-1 to A-2  
output signals (table), A-2  
documentation  
INTE2 bit, Port C, C-18  
INTEA bit, Port C, C-12, C-15  
INTEB bit, Port C, C-12, C-15  
INTEN bit, C-7  
interrupt control circuitry, 4-2  
Interrupt Control Register 1, C-6  
Interrupt Control Register 2, C-7  
interrupt enable  
conventions used in manual, x-xi  
National Instruments documentation, xii  
organization of manual, ix-x  
related documentation, xiii  
PC-DIO-24 (non-PnP)  
factory settings (table), D-2  
jumper settings (figure), D-6  
setting, D-6  
E
electronic support services, E-1  
e-mail support, E-2  
PC-DIO-24/PnP, C-1  
interrupt handling, C-22 to C-23  
environment specifications, A-3  
equipment, optional, 1-5 to 1-6  
PC-DIO-24/PnP User Manual  
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Index  
interrupt level  
PC-DIO-24 (non-PnP)  
jumper W2  
location (figure), D-3  
settings (table), D-2  
jumper W3  
factory settings (table), D-2  
jumper setting (figure), D-6  
setting, D-6 to D-7  
location (figure), D-3  
settings (table), D-2  
PC-DIO-24/PnP, 2-3  
interrupt programming examples,  
C-20 to C-22  
INTR signal  
L
LabVIEW and LabWindows/CVI application  
software, 1-2 to 1-3  
description (table), 3-11  
mode 1 input timing, 3-12  
mode 1 output timing, 3-13  
mode 2 bidirectional timing, 3-14  
Port C signal assignments (table), 3-4  
INTRA bit, Port C, C-12, C-15, C-18  
INTRB bit, Port C, C-13, C-15  
I/O bit, Port C, C-12, C-15, C-18  
I/O connector  
digital I/O connector, 4-3  
pin assignments (figure), 3-2  
I/O signal, Port C signal assignments  
(table), 3-4  
M
manual. See documentation.  
modes of operation, 82C55A  
mode 0 basic I/O, C-9 to C-11  
configurations (table), C-9 to C-10  
overview, C-8  
programming example, C-10 to C-11  
purpose and use, C-8  
mode 1 input timing, 3-12  
mode 1 output timing, 3-13  
mode 1 strobed input, C-11 to C-14  
control words written to CNFG  
register (figures), C-11 to C-12  
Port C pin assignments (figure), C-13  
Port C status-word bit definitions,  
C-12 to C-13  
programming example, C-13 to C-14  
purpose and use, C-8  
mode 1 strobed output, C-14 to C-17  
control words written to CNFG  
register (figure), C-14  
IRQ0 bit, C-6  
IRQ1 bit, C-6  
J
jumper and switch settings  
base I/O address settings, D-3 to D-5  
example settings (figure), D-4  
example settings with corresponding  
base I/O address and address space  
(table), D-5  
in use by other equipment (note), D-3  
factory settings, (table), D-2  
interrupt enable settings, D-6  
interrupt level settings, D-6 to D-7  
jumper W1  
Port C pin assignments (figure), C-16  
Port C status-word bit definitions,  
C-15  
programming example, C-16 to C-17  
purpose and use, C-8  
data signal settings (note), 2-1  
location of (figure), 2-1  
mode 2 bidirectional bus, C-17 to C-20  
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Index  
control word written to CNFG  
Register (figure), C-17  
factory-set jumper and switch  
settings (table), D-2  
Port C pin assignments (figure), C-19  
Port C status-word bit definitions,  
C-18  
programming example, C-19 to C-20  
purpose and use, C-9  
interrupt selection, D-5 to D-7  
parts locator diagram, D-3  
differences between PC-DIO-24/PnP and,  
D-1 to D-2  
comparison of characteristics (table),  
D-1 to D-2  
installation, D-7  
mode 2 bidirectional timing, 3-14  
single bit set/reset feature, C-9  
PC-DIO-24/PnP  
block diagram, 4-1  
N
configuration, 2-2 to 2-3  
custom cables, 1-5 to 1-6  
installation, 2-1 to 2-2  
NI-DAQ driver software, 1-3 to 1-4  
optional equipment, 1-5 to 1-6  
overview, 1-1  
requirements for getting started, 1-2  
software programming choices, 1-2 to 1-4  
National Instruments application  
software, 1-2 to 1-3  
NI-DAQ driver software, 1-3 to 1-4  
register-level programming, 1-4  
specifications, A-1 to A-3  
theory of operation, 4-1 to 4-3  
unpacking, 1-7  
O
OBF* signal  
description (table), 3-10  
mode 1 output timing, 3-13  
mode 2 bidirectional timing, 3-14  
Port C signal assignments (table), 3-4  
OBFA* bit, Port C, C-15, C-18  
OBFB* bit, Port C, C-15  
OKI 82C55A Programmable Peripheral  
Interface. See 82C55A Programmable  
Peripheral Interface.  
physical specifications, A-2  
pin assignments. See I/O connector; Port C.  
Plug and Play configuration, 2-2  
Port C  
optional equipment for PC-DIO-24/PnP,  
1-5 to 1-6  
pin assignments  
P
description, 3-3  
PA<7..0> signal (table), 3-3  
parts locator diagram, PC-DIO-24 (non-PnP)  
board, D-3  
mode 1 input (figure), C-13  
mode 1 output (figure), C-16  
mode 2 bidirectional bus  
(figure), C-19  
PB<7..0> signal (table), 3-3  
PC I/O channel control circuitry, 4-1 to 4-2  
PC<7..0> signal (table), 3-3  
PC-DIO-24 (non-PnP) board  
configuration, D-2 to D-7  
signal assignments (table), 3-4  
set/reset control words (table), C-5  
status-word bit definitions  
mode 1 strobed input, C-12 to C-13  
mode 1 strobed output, C-15  
power connections, 3-7  
base I/O address settings, D-3 to D-5  
PC-DIO-24/PnP User Manual  
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power requirements, A-2  
programming. See register-level  
programming.  
overview, C-1 to C-2  
register descriptions, C-3 to C-7  
82C55A, C-3 to C-5  
control word formats (figure), C-4  
interrupt control registers, C-5 to C-7  
Port C set/reset control words  
(table), C-5  
R
RD* signal  
description (table), 3-11  
register map, C-3  
mode 1 input timing, 3-12  
mode 2 bidirectional timing, 3-14  
register-level programming, C-1 to C-23  
82C55A operation, C-2  
requirements for getting started, 1-2  
S
compared with other software  
options, 1-4  
self-resetting fuse for +5 V signal, 3-7  
signal connections  
interrupt handling, C-22 to C-23  
interrupt programming examples,  
C-20 to C-22  
mode 0 basic I/O, C-9 to C-11  
configurations (table), C-9 to C-10  
overview, C-8  
programming example, C-10 to C-11  
mode 1 strobed input, C-11 to C-14  
control words (figures), C-11 to C-12  
Port C pin assignments (figure), C-13  
Port C status-word bit definitions,  
C-12 to C-13  
programming example, C-13 to C-14  
mode 1 strobed output, C-14 to C-17  
control words written to CNFG  
register (figure), C-14  
digital I/O power-up state selection,  
3-7 to 3-10  
high DIO power-up state, 3-7 to 3-8  
low DIO power-up state, 3-9 to 3-10  
digital I/O signal connections, 3-4 to 3-6  
input specifications (referenced to  
GND), 3-4  
output specifications (referenced to  
GND), 3-5  
typical digital I/O applications  
(figure), 3-6  
I/O connector pin assignments  
(figure), 3-2  
Port C pin assignments  
description, 3-3  
signal assignments (table), 3-4  
power connections, 3-7  
Port C pin assignments (figure), C-16  
Port C status-word bit definitions,  
C-15  
signal descriptions (table), 3-3  
timing specifications, 3-10 to 3-14  
mode 1 input timing, 3-12  
mode 1 output timing, 3-13  
mode 2 bidirectional timing, 3-14  
signals (table), 3-10 to 3-11  
single bit set/reset feature  
overview, C-9  
programming example, C-16 to C-17  
mode 2 bidirectional bus, C-17 to C-20  
control word written to CNFG  
Register (figure), C-17  
Port C pin assignments (figure), C-19  
Port C status-word bit definitions,  
C-18  
Port C set/reset control words (table), C-5  
programming example, C-19 to C-20  
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Index  
software programming choices, 1-2 to 1-4.  
See also register-level programming.  
ComponentWorks, 1-2  
block diagram, 4-1  
bus interface, 4-2  
bus transceivers, 4-2  
LabVIEW and LabWindows/CVI  
application software, 1-2 to 1-3  
NI-DAQ driver software, 1-3 to 1-4  
VirtualBench, 1-3  
digital I/O connector, 4-3  
interrupt control circuitry, 4-2  
PC I/O channel control circuitry,  
4-1 to 4-2  
specifications  
timing specifications, 3-10 to 3-14  
mode 1 input timing, 3-12  
mode 1 output timing, 3-13  
mode 2 bidirectional timing, 3-14  
signals (table), 3-10 to 3-11  
transfer rate specifications, A-3  
digital I/O, A-1  
digital logic levels, A-1 to A-2  
environment, A-3  
physical, A-2  
power requirements, A-2  
transfer rates, A-3  
STB* signal  
U
description (table), 3-10  
mode 1 input timing, 3-12  
mode 2 bidirectional timing, 3-14  
Port C signal assignments (table), 3-4  
switch settings. See jumper and switch  
settings.  
unpacking the PC-DIO-24/PnP, 1-7  
V
VirtualBench software, 1-3  
W
T
WR* signal  
technical support, E-1 to E-2  
telephone and fax number support, E-2  
theory of operation, 4-1 to 4-3  
82C55A Programmable Peripheral  
Interface, 4-2  
description (table), 3-11  
mode 1 output timing, 3-13  
mode 2 bidirectional timing, 3-14  
PC-DIO-24/PnP User Manual  
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