NXP Semiconductors Stereo Amplifier TDA8932B User Manual

TDA8932B  
Class-D audio amplifier  
Rev. 03 — 21 June 2007  
Product data sheet  
1. General description  
The TDA8932B is a high efficiency class-D amplifier with low power dissipation.  
The continuous time output power is 2 × 15 W in stereo half-bridge application (RL = 4 )  
or 1 × 30 W in mono full-bridge application (RL = 8 ). Due to the low power dissipation  
the device can be used without any external heat sink when playing music. Due to the  
implementation of thermal foldback, even for high supply voltages and/or lower load  
impedances, the device remains operating with considerable music output power without  
the need for an external heat sink.  
The device has two full-differential inputs driving two independent outputs. It can be used  
as mono full-bridge configuration (BTL) or as stereo half-bridge configuration (SE).  
2. Features  
I Operating voltage from 10 V to 36 V asymmetrical or ±5 V to ±18 V symmetrical  
I Mono-bridged tied load (full-bridge) or stereo single-ended (half-bridge) application  
I Application without heatsink using thermally enhanced small outline package  
I High efficiency and low-power dissipation  
I Thermally protected and thermal foldback  
I Current limiting to avoid audio holes  
I Full short-circuit proof across load and to supply lines (using advanced current  
protection)  
I Switchable internal or external oscillator (master-slave setting)  
I No pop noise  
I Full-differential inputs  
3. Applications  
I Flat panel television sets  
I Flat panel monitor sets  
I Multimedia systems  
I Wireless speakers  
I Mini and micro systems  
I Home sound sets  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
6. Block diagram  
OSCREF OSCIO  
V
DDA  
8
10  
31  
28  
BOOT1  
OSCILLATOR  
29  
2
V
DDP1  
IN1P  
DRIVER  
HIGH  
27  
26  
PWM  
MODULATOR  
OUT1  
V
SSD  
CTRL  
DRIVER  
LOW  
V
SSP1  
3
IN1N  
INREF  
IN2P  
21  
20  
22  
23  
12  
15  
MANAGER  
BOOT2  
V
DDP2  
DRIVER  
HIGH  
PWM  
MODULATOR  
OUT2  
CTRL  
DRIVER  
LOW  
V
SSP2  
14  
4
IN2N  
DIAG  
PROTECTIONS:  
OVP, OCP, OTP,  
UVP, TF, WP  
V
DDA  
25  
24  
18  
STABILIZER 11 V  
STAB1  
STAB2  
DREF  
V
SSP1  
V
DDA  
STABILIZER 11 V  
V
7
6
CGND  
SSP2  
POWERUP  
REGULATOR 5 V  
V
SSD  
MODE  
5
ENGAGE  
11  
30  
19  
V
V
DDA  
HVPREF  
HVP1  
SSA  
TDA8932B  
13  
TEST  
HVP2  
HALF SUPPLY VOLTAGE  
9
1, 16, 17, 32  
001aaf597  
V
V
SSD(HW)  
SSA  
Fig 1. Block diagram  
TDA8932B_3  
© NXP B.V. 21 June 2007. All rights reserved.  
Product data sheet  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
7. Pinning information  
7.1 Pinning  
1
2
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
V
V
V
V
SSD(HW)  
SSD(HW)  
IN1P  
SSD(HW)  
SSD(HW)  
IN1P  
OSCIO  
HVP1  
OSCIO  
HVP1  
3
3
IN1N  
DIAG  
IN1N  
DIAG  
4
4
V
V
DDP1  
DDP1  
5
5
ENGAGE  
POWERUP  
CGND  
BOOT1  
OUT1  
ENGAGE  
POWERUP  
CGND  
BOOT1  
OUT1  
6
6
7
7
V
V
SSP1  
SSP1  
8
8
V
STAB1  
STAB2  
V
STAB1  
STAB2  
DDA  
DDA  
TDA8932BT  
TDA8932BTW  
9
9
V
SSA  
V
SSA  
V
10  
11  
12  
13  
14  
15  
16  
10  
11  
12  
13  
14  
15  
16  
OSCREF  
HVPREF  
INREF  
TEST  
OSCREF  
HVPREF  
INREF  
TEST  
V
SSP2  
SSP2  
OUT2  
OUT2  
BOOT2  
BOOT2  
V
V
DDP2  
DDP2  
IN2N  
HVP2  
DREF  
IN2N  
HVP2  
DREF  
IN2P  
IN2P  
V
V
V
V
SSD(HW)  
SSD(HW)  
SSD(HW)  
SSD(HW)  
001aaf598  
001aaf599  
Fig 2. Pin configuration SO32  
Fig 3. Pin configuration HTSSOP32  
7.2 Pin description  
Table 3.  
Symbol  
VSSD(HW)  
IN1P  
Pin description  
Pin  
1
Description  
negative digital supply voltage and handle wafer connection  
positive audio input for channel 1  
2
IN1N  
3
negative audio input for channel 1  
DIAG  
4
diagnostic output; open-drain  
ENGAGE  
POWERUP  
CGND  
VDDA  
5
engage input to switch between Mute mode and Operating mode  
power-up input to switch between Sleep mode and Mute mode  
control ground; reference for POWERUP, ENGAGE and DIAG  
positive analog supply voltage  
6
7
8
VSSA  
9
negative analog supply voltage  
OSCREF  
HVPREF  
INREF  
TEST  
10  
11  
12  
13  
14  
15  
16  
17  
18  
input internal oscillator setting (only master setting)  
decoupling of internal half supply voltage reference  
decoupling for input reference voltage  
test signal input; for testing purpose only  
IN2N  
negative audio input for channel 2  
IN2P  
positive audio input for channel 2  
VSSD(HW)  
VSSD(HW)  
DREF  
negative digital supply voltage and handle wafer connection  
negative digital supply voltage and handle wafer connection  
decoupling of internal (reference) 5 V regulator for logic supply  
TDA8932B_3  
© NXP B.V. 21 June 2007. All rights reserved.  
Product data sheet  
Rev. 03— 21 June 2007  
4 of 48  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
Table 3.  
Pin description (Continued)  
Symbol  
Pin  
Description  
HVP2  
19  
half supply output voltage 2 for charging single-ended capacitor for  
channel 2  
VDDP2  
BOOT2  
OUT2  
VSSP2  
STAB2  
STAB1  
VSSP1  
OUT1  
BOOT1  
VDDP1  
HVP1  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
positive power supply voltage for channel 2  
bootstrap high-side driver channel 2  
PWM output channel 2  
negative power supply voltage for channel 2  
decoupling of internal 11 V regulator for channel 2 drivers  
decoupling of internal 11 V regulator for channel 1 drivers  
negative power supply voltage for channel 1  
PWM output channel 1  
bootstrap high-side driver channel 1  
positive power supply voltage for channel 1  
half supply output voltage 1 for charging single-ended capacitor for  
channel 1  
OSCIO  
31  
oscillator input in slave configuration or oscillator output in master  
configuration  
VSSD(HW)  
32  
-
negative digital supply voltage and handle wafer connection  
HTSSOP32 package only[1]  
Exposed die  
pad  
[1] The exposed die pad has to be connected to VSSD(HW)  
.
8. Functional description  
8.1 General  
The TDA8932B is a mono full-bridge or stereo half-bridge audio power amplifier using  
class-D technology. The audio input signal is converted into a Pulse Width Modulated  
(PWM) signal via an analog input stage and PWM modulator. To enable the output power  
Diffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWM  
signal is applied to a control and handshake block and driver circuits for both the high side  
and low side. A 2nd-order low-pass filter converts the PWM signal to an analog audio  
signal across the loudspeakers.  
The TDA8932B contains two independent half-bridges with full differential input stages.  
The loudspeakers can be connected in the following configurations:  
Mono full-bridge: Bridge Tied Load (BTL)  
Stereo half-bridge: Single-Ended (SE)  
The TDA8932B contains common circuits to both channels such as the oscillator, all  
reference sources, the mode functionality and a digital timing manager. The following  
protections are built-in: thermal foldback, temperature, current and voltage protections.  
TDA8932B_3  
© NXP B.V. 21 June 2007. All rights reserved.  
Product data sheet  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
8.2 Mode selection and interfacing  
The TDA8932B can be switched in three operating modes using pins POWERUP and  
ENGAGE:  
Sleep mode: with low supply current.  
Mute mode: the amplifiers are switching idle (50 % duty cycle), but the audio signal at  
the output is suppressed by disabling the Vl-converter input stages. The capacitors on  
pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical  
supply only).  
Operating mode: the amplifiers are fully operational with output signal.  
Fault mode.  
Both pins POWERUP and ENGAGE refer to pin CGND.  
Table 4 shows the different modes as a function of the voltages on the POWERUP and  
ENGAGE pins.  
Table 4.  
Mode  
Mode selection  
Pin  
POWERUP  
ENGAGE  
< 0.8 V  
< 0.8 V[1]  
DIAG  
Sleep  
< 0.8 V  
don’t care  
> 2 V  
Mute  
2 V to 6.0 V[1]  
2 V to 6.0 V[1]  
2 V to 6.0 V[1]  
Operating  
Fault  
2.4 V to 6.0 V[1]  
> 2 V  
don’t care  
< 0.8 V  
[1] In case of symmetrical supply conditions the voltage applied to pins POWERUP and ENGAGE must never  
exceed the supply voltage (VDDA, VDDP1 or VDDP2).  
If the transition between Mute mode and Operating mode is controlled via a time constant,  
the start-up will be pop free since the DC output offset voltage is applied gradually to the  
output between Mute mode and Operating mode. The bias current setting of the  
VI-converters is related to the voltage on pin ENGAGE:  
Mute mode: the bias current setting of the VI-converters is zero (VI-converters  
disabled)  
Operating mode: the bias current is at maximum  
The time constant required to apply the DC output offset voltage gradually between Mute  
mode and Operating mode can be generated by applying a decoupling capacitor on pin  
ENGAGE. The value of the capacitor on pin ENGAGE should be 470 nF.  
TDA8932B_3  
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Product data sheet  
Rev. 03— 21 June 2007  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
V
P
POWERUP  
DREF  
HVPREF  
HVP1, HVP2  
2.0 V (typical)  
1.2 V (typical)  
ENGAGE  
0.8 V  
AUDIO  
AUDIO  
AUDIO  
PWM  
audio  
OUT1, OUT2  
PWM  
PWM  
DIAG  
OSCIO  
operating  
mute  
operating  
fault  
operating  
sleep  
001aaf885  
Fig 4. Start-up sequence  
8.3 Pulse width modulation frequency  
The output signal of the amplifier is a PWM signal with a carrier frequency of  
approximately 320 kHz. Using a 2nd-order low-pass filter in the application results in an  
analog audio signal across the loudspeaker. The PWM switching frequency can be set by  
an external resistor Rosc connected between pins OSCREF and VSSD(HW). The carrier  
frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 k,  
the carrier frequency is set to an optimized value of 320 kHz (see Figure 5).  
If two or more TDA8932B devices are used in the same audio application, it is  
recommended to synchronize the switching frequency of all devices. This can be realized  
by connecting all pins OSCIO together and configure one of the TDA8932B in the  
application as clock master, while the other TDA8932B devices are configured in slave  
mode.  
Pin OSCIO is a 3-state input or output buffer. Pin OSCIO is configured in master mode as  
oscillator output and in slave mode as oscillator input. Master mode is enabled by applying  
a resistor while slave mode is entered by connecting pin OSCREF directly to pin VSSD(HW)  
(without any resistor).  
The value of the resistor also sets the frequency of the carrier which can be estimated by  
the following formula:  
TDA8932B_3  
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Product data sheet  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
12.45 × 109  
---------------------------  
Rosc  
f osc  
=
(1)  
Where:  
fosc = oscillator frequency (Hz)  
Rosc = oscillator resistor (on pin OSCREF) ()  
001aad758  
550  
f
osc  
(kHz)  
450  
350  
250  
25  
30  
35  
40  
45  
Rosc (k)  
Fig 5. Oscillation frequency as a function of resistor Rosc  
Table 5 summarizes how to configure the TDA8932B in master or slave configuration.  
For device synchronization see Section 14.6 “Device synchronization”.  
Table 5.  
Master or slave configuration  
Configuration  
Pin  
OSCREF  
OSCIO  
output  
input  
Master  
Slave  
Rosc > 25 kto VSSD(HW)  
Rosc = 0 ; shorted to VSSD(HW)  
8.4 Protection  
The following protection is included in the TDA8932B:  
Thermal Foldback (TF)  
OverTemperature Protection (OTP)  
OverCurrent Protection (OCP)  
Window Protection (WP)  
Supply voltage protection:  
UnderVoltage Protection (UVP)  
OverVoltage Protection (OVP)  
UnBalance Protection (UBP)  
ElectroStatic Discharge (ESD)  
The reaction of the device to the different fault conditions differs per protection.  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
8.4.1 Thermal Foldback (TF)  
If the junction temperature of the TDA8932B exceeds the threshold level (Tj > 140 °C) the  
gain of the amplifier is decreased gradually to a level where the combination of dissipation  
(P) and the thermal resistance from junction to ambient [Rth(j-a)] results in a junction  
temperature around the threshold level.  
This means that the device will not completely switch off, but remains operational at lower  
output power levels. Especially with music output signals this feature enables high peak  
output power while still operating without any external heat sink other than the  
printed-circuit board area.  
If the junction temperature still increases due to external causes, the OTP shuts down the  
amplifier completely.  
8.4.2 OverTemperature Protection (OTP)  
If the junction temperature Tj > 155 °C, then the power stage will shut down immediately.  
8.4.3 OverCurrent Protection (OCP)  
When the loudspeaker terminals are short-circuited or if one of the demodulated outputs  
of the amplifier is short-circuited to one of the supply lines, this will be detected by the  
OCP.  
If the output current exceeds the maximum output current (IO(ocp) > 4 A), this current will  
be limited by the amplifier to 4 A while the amplifier outputs remain switching (the amplifier  
is NOT shutdown completely). This is called current limiting.  
The amplifier can distinguish between an impedance drop of the loudspeaker and a  
low-ohmic short-circuit across the load or to one of the supply lines. This impedance  
threshold depends on the supply voltage used:  
In case of a short-circuit across the load, the audio amplifier is switched off completely  
and after approximately 100 ms it will try to restart again. If the short-circuit condition  
is still present after this time, this cycle will be repeated. The average dissipation will  
be low because of this low duty cycle.  
In case of a short to one of the supply lines, this will trigger the OCP and the amplifier  
will be shut down. During restart the window protection will be activated. As a result  
the amplifier will not start until 100 ms after the short to the supply lines is removed.  
In case of impedance drop (e.g. due to dynamic behavior of the loudspeaker) the  
same protection will be activated. The maximum output current is again limited to 4 A,  
but the amplifier will NOT switch off completely (thus preventing audio holes from  
occurring). The result will be a clipping output signal without any artifacts.  
8.4.4 Window Protection (WP)  
The WP checks the PWM output voltage before switching from Sleep mode to Mute mode  
(outputs switching) and is activated:  
During the start-up sequence, when pin POWERUP is switched from Sleep mode to  
Mute mode. In the event of a short-circuit at one of the output terminals to VDDP1  
,
VSSP1, VDDP2 or VSSP2 the start-up procedure is interrupted and the TDA8932B waits  
for open-circuit outputs. Because the check is done before enabling the power stages,  
no large currents will flow in the event of a short-circuit.  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
When the amplifier is completely shut down due to activation of the OCP because a  
short-circuit to one of the supply lines is made, then during restart (after 100 ms) the  
window protection will be activated. As a result the amplifier will not start until the  
short-circuit to the supply lines is removed.  
8.4.5 Supply voltage protection  
If the supply voltage drops below 10 V, the UnderVoltage Protection (UVP) circuit is  
activated and the system will shut down directly. This switch-off will be silent and without  
pop noise. When the supply voltage rises above the threshold level, the system is  
restarted again after 100 ms.  
If the supply voltage exceeds 36 V the OverVoltage Protection (OVP) circuit is activated  
and the power stages will shut down. It is re-enabled as soon as the supply voltage drops  
below the threshold level. The system is restarted again after 100 ms.  
It should be noted that supply voltages > 40 V may damage the TDA8932B. Two  
conditions should be distinguished:  
1. If the supply voltage is pumped to higher values by the TDA8932B application itself  
(see also Section 14.3), the OVP is triggered and the TDA8932B is shut down. The  
supply voltage will decrease and the TDA8932B is protected against any overstress.  
2. If a supply voltage > 40 V is caused by other or external causes, then the TDA8932B  
will shut down, but the device can still be damaged since the supply voltage will  
remain > 40 V in this case. The OVP protection is not a supply voltage clamp.  
An additional UnBalance Protection (UBP) circuit compares the positive analog supply  
voltage (VDDA) and the negative analog supply voltage (VSSA) and is triggered if the  
voltage difference between them exceeds a certain level. This level depends on the sum  
of both supply voltages. The unbalance threshold levels can be defined as follows:  
LOW-level threshold: VP(th)(ubp)l < 85 × VHVPREF  
HIGH-level threshold: VP(th)(ubp)h > 83 × VHVPREF  
In a symmetrical supply the UBP is released when the unbalance of the supply voltage is  
within 6 % of its starting value.  
Table 6 shows an overview of all protection and the effect on the output signal.  
Table 6.  
Protection overview  
Restart  
Protection  
When fault is removed  
Every 100 ms  
OTP  
OCP  
WP  
no  
yes  
no  
yes  
yes  
no  
no  
UVP  
OVP  
UBP  
yes  
yes  
yes  
no  
no  
TDA8932B_3  
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NXP Semiconductors  
Class-D audio amplifier  
8.5 Diagnostic input and output  
Whenever a protection is triggered, except for TF, pin DIAG is activated to LOW level (see  
Table 6). An internal reference supply will pull-up the open-drain DIAG output to  
approximately 2.4 V. This internal reference supply can deliver approximately 50 µA.  
Pin DIAG refers to pin CGND. The diagnostic output signal during different short  
conditions is illustrated in Figure 6. Using pin DIAG as input, a voltage < 0.8 V will put the  
device into Fault mode.  
V
V
o
o
2.4 V  
2.4 V  
amplifier  
restart  
no restart  
0 V  
0 V  
50 ms 50 ms  
short to  
shorted load  
supply line  
001aad759  
Fig 6. Diagnostic output for different short-circuit conditions  
8.6 Differential inputs  
For a high common-mode rejection ratio and a maximum of flexibility in the application,  
the audio inputs are fully differential. By connecting the inputs anti-parallel, the phase of  
one of the two channels can be inverted, so that the amplifier can operate as a mono BTL  
amplifier. The input configuration for a mono BTL application is illustrated in Figure 7.  
In SE configuration it is also recommended to connect the two differential inputs in  
anti-phase. This has advantages for the current handling of the power supply at low signal  
frequencies and minimizes supply pumping (see also Section 14.8).  
IN1P  
OUT1  
IN1N  
audio  
input  
IN2P  
OUT2  
IN2N  
001aad760  
Fig 7. Input configuration for mono BTL application  
8.7 Output voltage buffers  
When pin POWERUP is set HIGH, the half supply output voltage buffers are switched on  
in asymmetrical supply configuration. The start-up will be pop free since the device starts  
switching when the capacitor on pin HVPREF and the SE capacitors are completely  
charged.  
Output voltage buffers:  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
Pins HVP1 and HVP2: The time required for charging the SE capacitor depends on its  
value. The half supply voltage output is disabled when the TDA8932B is used in a  
symmetrical supply application.  
Pin HVPREF: This output voltage reference buffer charges the capacitor on pin  
HVPREF.  
Pin INREF: This output voltage reference buffer charges the input reference capacitor  
on pin INREF. Pin INREF applies the bias voltage for the inputs.  
9. Internal circuitry  
Table 7.  
Internal circuitry  
Pin  
1
Symbol  
VSSD(HW)  
VSSD(HW)  
VSSD(HW)  
VSSD(HW)  
Equivalent circuit  
1, 16,  
17, 32  
V
V
DDA  
16  
17  
32  
SSA  
001aad784  
2
IN1P  
IN1N  
INREF  
IN2N  
IN2P  
V
DDA  
3
2 kΩ  
± 20 %  
12  
14  
15  
2, 15  
V/I  
48 kΩ  
± 20 %  
12  
HVPREF  
48 kΩ  
± 20 %  
2 kΩ  
± 20 %  
3, 14  
V/I  
V
SSA  
001aad785  
4
DIAG  
V
2.5 V  
DDA  
50 µA  
500 Ω  
± 20 %  
4
100 kΩ  
± 20 %  
V
CGND  
SSA  
001aaf607  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
Table 7.  
Internal circuitry (Continued)  
Pin  
Symbol  
Equivalent circuit  
5
ENGAGE  
V
2.8 V  
DDA  
I
= 50 µA  
ref  
2 kΩ  
± 20 %  
5
100 kΩ  
± 20 %  
V
CGND  
SSA  
001aaf608  
6
POWERUP  
V
DDA  
6
V
CGND  
001aad788  
SSA  
7
CGND  
V
DDA  
7
V
SSA  
001aad789  
8
VDDA  
8
V
V
SSA  
SSD  
001aad790  
TDA8932B_3  
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NXP Semiconductors  
Class-D audio amplifier  
Table 7.  
Internal circuitry (Continued)  
Pin  
Symbol  
Equivalent circuit  
9
VSSA  
V
DDA  
9
V
SSD  
001aad791  
10  
OSCREF  
V
DDA  
I
ref  
10  
V
001aad792  
SSA  
11  
HVPREF  
V
DDA  
11  
V
SSA  
001aaf604  
13  
TEST  
V
V
DDA  
13  
SSA  
001aad795  
18  
DREF  
V
DD  
18  
V
SSD  
001aag025  
TDA8932B_3  
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NXP Semiconductors  
Class-D audio amplifier  
Table 7.  
Internal circuitry (Continued)  
Pin  
19  
Symbol  
HVP2  
Equivalent circuit  
V
DDA  
30  
HVP1  
19, 30  
V
001aag026  
SSA  
20  
23  
26  
29  
VDDP2  
VSSP2  
VSSP1  
VDDP1  
20, 29  
23, 26  
001aad798  
21  
28  
BOOT2  
BOOT1  
21, 28  
OUT1, OUT2  
001aad799  
22  
27  
OUT2  
OUT1  
V
V
DDP1,  
DDP2  
22, 27  
V
SSP1,  
V
SSP2  
001aag027  
24  
25  
STAB2  
STAB1  
V
DDA  
24, 25  
V
SSP1,  
V
SSP2  
001aag028  
31  
OSCIO  
DREF  
31  
V
SSD  
001aag029  
TDA8932B_3  
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Class-D audio amplifier  
10. Limiting values  
Table 8.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
Max  
Unit  
VP  
Vx  
supply voltage  
asymmetrical supply  
0.3  
+40  
V
voltage on pin x  
IN1P, IN1N, IN2P, IN2N  
OSCREF, OSCIO, TEST  
5  
+5  
V
V
V
VSSD(HW) 0.3 5  
POWERUP, ENGAGE,  
DIAG  
VCGND 0.3  
6
all other pins  
VSS 0.3  
VDD + 0.3 V  
IORM  
repetitive peak output  
current  
maximum output  
current limiting  
4
-
A
Tj  
junction temperature  
storage temperature  
ambient temperature  
power dissipation  
-
150  
°C  
°C  
°C  
W
V
Tstg  
Tamb  
P
55  
40  
-
+150  
+85  
5
Vesd  
electrostatic discharge  
voltage  
HBM  
MM  
2000  
200  
+2000  
+200  
V
[1] VP = VDDP1 VSSP1 = VDDP2 VSSP2  
.
[2] Measured with respect to pin INREF; Vx < VDD + 0.3 V.  
[3] Measured with respect to pin VSSD(HW); Vx < VDD + 0.3 V.  
[4] Measured with respect to pin CGND; Vx < VDD + 0.3 V.  
[5] VSS = VSSP1 = VSSP2; VDD = VDDP1 = VDDP2  
.
[6] Current limiting concept.  
[7] Human Body Model (HBM); Rs = 1500 ; C = 100 pF  
For pins 2, 3, 11, 14 and 15 Vesd = ±1800 V.  
[8] Machine Model (MM); Rs = 0 ; C = 200 pF; L = 0.75 µH.  
11. Thermal characteristics  
Table 9.  
Symbol  
Thermal characteristics  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
SO32 package  
Rth(j-a)  
thermal resistance from junction free air natural convection  
to ambient  
JEDEC test board  
-
-
-
41  
44  
-
44  
-
K/W  
K/W  
K/W  
2 layer application board  
Ψj-lead  
Ψj-top  
thermal characterization  
30  
parameter from junction to lead  
thermal characterization  
parameter from junction to top  
-
-
8
K/W  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
Table 9.  
Symbol  
Thermal characteristics (Continued)  
Parameter Conditions  
Min  
Typ  
Max  
Unit  
HTSSOP32 package  
Rth(j-a)  
thermal resistance from junction free air natural convection  
to ambient  
JEDEC test board  
-
-
-
47  
48  
-
50  
-
K/W  
K/W  
K/W  
2 layer application board  
Ψj-lead  
Ψj-top  
thermal characterization  
30  
parameter from junction to lead  
thermal characterization  
parameter from junction to top  
-
-
-
2
-
K/W  
K/W  
Rth(j-c)  
thermal resistance from junction free air natural convection  
to case  
4.0  
[1] Measured on a JEDEC high K-factor test board (standard EIA/JESD 51-7) in free air with natural convection.  
[2] Two layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection.  
[3] Strongly depends on where the measurement is taken on the package.  
[4] Two layer application board (55 mm × 40 mm), 35 µm copper, FR4 base material in free air with natural convection.  
12. Static characteristics  
Table 10. Static characteristics  
VP = 22 V; fosc = 320 kHz; Tamb = 25 °C; unless otherwise specified.  
Symbol  
Supply  
VP  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
supply voltage  
asymmetrical supply  
symmetrical supply  
Sleep mode; no load  
10  
±5  
-
22  
36  
V
±11  
0.6  
40  
±18  
1.0  
50  
V
IP  
supply current  
mA  
mA  
Iq(tot)  
total quiescent current  
Operating mode; no load, no  
-
snubbers and no filter connected  
Series resistance output power switches  
RDSon  
drain-source on-state  
resistance  
Tj = 25 °C  
-
-
150  
234  
-
-
mΩ  
Tj = 125 °C  
mΩ  
Power-up input: pin POWERUP[1]  
VI  
input voltage  
0
-
-
6.0  
20  
V
II  
input current  
VI = 3 V  
1
-
µA  
V
VIL  
LOW-level input voltage  
0
2
0.8  
6.0  
VIH  
HIGH-level input voltage  
-
V
Engage input: pin ENGAGE[1]  
VO  
VI  
output voltage  
open pin  
VI = 0 V  
2.4  
0
2.8  
3.1  
6.0  
60  
V
input voltage  
-
V
IO  
output current  
-
50  
-
µA  
V
VIL  
VIH  
LOW-level input voltage  
HIGH-level input voltage  
0
0.8  
6.0  
2.4  
-
V
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Class-D audio amplifier  
Table 10. Static characteristics (Continued)  
VP = 22 V; fosc = 320 kHz; Tamb = 25 °C; unless otherwise specified.  
Symbol  
Diagnostic output: pin DIAG[1]  
VO output voltage  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
protection activated; see Table 6  
Operating mode  
-
-
0.8  
3.3  
V
V
2
2.5  
Bias voltage for inputs: pin INREF  
VO(bias) bias output voltage  
with respect to pin VSSA  
-
2.1  
-
V
Half supply voltage  
Pins HVP1 and HVP2  
VO  
output voltage  
half supply voltage to charge SE  
capacitor  
0.5VP 0.5VP  
0.2  
0.5VP +  
0.2  
V
IO  
output current  
output voltage  
VHVP1 = VO 1 V;  
-
50  
-
mA  
VHVP2 = VO 1 V  
Pin HVPREF  
VO  
half supply reference voltage in  
Mute mode  
0.5VP 0.5VP  
0.2  
0.5VP +  
0.2  
V
V
Reference voltage for internal logic: pin DREF  
VO output voltage  
Amplifier outputs: pins OUT1 and OUT2  
|VO(offset) output offset voltage  
4.5  
4.8  
5.1  
|
SE; with respect to pin HVPREF  
Mute mode  
-
-
-
-
15  
mV  
mV  
Operating mode  
BTL  
100  
Mute mode  
-
-
-
-
20  
mV  
mV  
Operating mode  
150  
Stabilizer output: pins STAB1 and STAB2  
VO output voltage  
Mute mode and Operating mode;  
with respect to pins VSSP1 and  
VSSP2  
10  
11  
12  
V
Voltage protection  
VP(uvp)  
undervoltage protection  
supply voltage  
8.0  
36.1  
-
9.2  
9.9  
40  
18  
-
V
V
V
V
VP(ovp)  
overvoltage protection  
supply voltage  
37.4  
VP(th)(ubp)l  
VP(th)(ubp)h  
low unbalance protection  
threshold supply voltage  
VHVPREF = 11 V  
VHVPREF = 11 V  
-
-
high unbalance protection  
threshold supply voltage  
29  
Current protection  
IO(ocp) overcurrent protection  
output current  
Temperature protection  
current limiting  
4
5
-
-
A
Tact(th_prot)  
thermal protection activation  
temperature  
155  
160  
°C  
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Class-D audio amplifier  
Table 10. Static characteristics (Continued)  
VP = 22 V; fosc = 320 kHz; Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Tact(th_fold)  
thermal foldback activation  
temperature  
140  
-
150  
°C  
Oscillator reference; pin OSCIO[2]  
VIH  
HIGH-level input voltage  
LOW-level input voltage  
HIGH-level output voltage  
LOW-level output voltage  
4.0  
0
-
-
-
-
-
5
V
V
V
V
-
VIL  
0.8  
5
VOH  
4.0  
0
VOL  
0.8  
-
Nslave(max)  
maximum number of slaves driven by one master  
12  
[1] Measured with respect to pin CGND.  
[2] Measured with respect to pin VSSD(HW)  
.
13. Dynamic characteristics  
Table 11. Switching characteristics  
VP = 22 V; Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Internal oscillator  
Conditions  
Min  
Typ  
Max  
Unit  
fosc  
oscillator frequency  
Rosc = 39 kΩ  
-
320  
-
-
kHz  
kHz  
range  
300  
500  
Timing PWM output: pins OUT1 and OUT2  
tr  
rise time  
IO = 0 A  
IO = 0 A  
IO = 0 A  
-
-
-
10  
10  
80  
-
-
-
ns  
ns  
ns  
tf  
fall time  
tw(min)  
minimum pulse width  
Table 12. SE characteristics  
VP = 22 V; RL = 2 × 4 ; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 [1]; Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Po = 1 W  
Min  
Typ  
Max  
Unit  
THD+N  
total harmonic  
distortion-plus-noise  
fi = 1 kHz  
-
0.015  
0.08  
30  
0.05  
0.10  
31  
1
%
fi = 6 kHz  
-
%
Gv(cl)  
|Gv|  
αcs  
closed-loop voltage gain  
voltage gain difference  
channel separation  
Vi = 100 mV; no load  
29  
-
dB  
dB  
dB  
0.5  
Po = 1 W; fi = 1 kHz  
Operating mode  
fi = 100 Hz  
70  
80  
-
SVRR  
supply voltage ripple rejection  
-
60  
-
dB  
dB  
kΩ  
µV  
µV  
µV  
fi = 1 kHz  
40  
70  
-
50  
-
|Zi|  
input impedance  
differential  
100  
100  
70  
-
Vn(o)  
noise output voltage  
Operating mode; Rs = 0 Ω  
Mute mode  
150  
100  
-
-
VO(mute)  
mute output voltage  
Mute mode; Vi = 1 V (RMS) and  
fi = 1 kHz  
-
100  
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Class-D audio amplifier  
Table 12. SE characteristics (Continued)  
VP = 22 V; RL = 2 × 4 ; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 [1]; Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
CMRR  
common mode rejection ratio  
Vi(cm) = 1 V (RMS)  
Po = 15 W  
-
75  
-
dB  
ηpo  
output power efficiency  
RMS output power  
VP = 22 V; RL = 4 Ω  
VP = 30 V; RL = 8 Ω  
90  
91  
92  
93  
-
-
%
%
Po(RMS)  
continuous time output power per  
channel  
RL = 4 ; VP = 22 V  
THD+N = 0.5 %; fi = 1 kHz  
THD+N = 0.5 %; fi = 100 Hz  
THD+N = 10 %; fi = 1 kHz  
THD+N = 10 %; fi = 100 Hz  
RL = 8 ; VP = 30 V  
10.9  
12.1  
12.1  
15.3  
15.3  
-
-
-
-
W
W
W
W
-
13.8  
-
THD+N = 0.5 %; fi = 1 kHz  
THD+N = 0.5 %; fi = 100 Hz  
THD+N = 10 %; fi = 1 kHz  
THD+N = 10 %; fi = 100 Hz  
short time output power per channel  
RL = 4 ; VP = 29 V  
11.1  
12.3  
12.3  
15.5  
15.5  
-
-
-
-
W
W
W
W
-
14.0  
-
THD+N = 0.5 %  
19.0  
23.8  
21.1  
26.5  
-
-
W
W
THD+N = 10 %  
[1] Rs is the series resistance of inductor and capacitor of low-pass LC filter in the application.  
[2] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall.  
[3] Maximum Vripple = 2 V (p-p); Rs = 0 .  
[4] B = 20 Hz to 20 kHz, AES17 brick wall.  
[5] Output power is measured indirectly; based on RDSon measurement.  
Two layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection.  
Table 13. BTL characteristics  
VP = 22 V; RL = 8 ; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 [1]; Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Po = 1 W  
fi = 1 kHz  
fi = 6 kHz  
Min  
Typ  
Max  
Unit  
THD+N  
total harmonic  
distortion-plus-noise  
-
0.007 0.1  
%
-
0.05  
36  
0.1  
37  
%
Gv(cl)  
closed-loop voltage gain  
35  
dB  
SVRR  
supply voltage ripple rejection  
Operating mode  
fi = 100 Hz  
-
75  
75  
80  
50  
-
-
-
dB  
dB  
dB  
kΩ  
fi = 1000 Hz  
70  
-
sleep; fi = 100 Hz  
differential  
|Zi|  
input impedance  
35  
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Class-D audio amplifier  
Table 13. BTL characteristics (Continued)  
VP = 22 V; RL = 8 ; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 [1]; Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Rs = 0 Ω  
Min  
Typ  
Max  
Unit  
Vn(o)  
noise output voltage  
Operating mode  
Mute mode  
-
-
-
100  
70  
150  
100  
-
µV  
µV  
µV  
VO(mute)  
mute output voltage  
Mute mode; Vi = 1 V (RMS) and  
fi = 1 kHz  
100  
CMRR  
common mode rejection ratio  
output power efficiency  
Vi(cm) = 1 V (RMS)  
-
75  
90  
92  
-
-
-
dB  
%
ηpo  
Po = 15 W; VP = 12 V and RL = 4 Ω  
Po = 30 W; VP = 22 V and RL = 8 Ω  
continuous time output power  
RL = 4 ; VP = 12 V  
88  
90  
%
Po(RMS)  
RMS output power  
THD+N = 0.5 %; fi = 1 kHz  
THD+N = 0.5 %; fi = 100 Hz  
THD+N = 10 %; fi = 1 kHz  
THD+N = 10 %; fi = 100 Hz  
RL = 8 ; VP = 22 V  
11.8  
13.2  
13.2  
17.2  
17.2  
-
-
-
-
W
W
W
W
-
15.5  
-
THD+N = 0.5 %; fi = 1 kHz  
THD+N = 0.5 %; fi = 100 Hz  
THD+N = 10 %; fi = 1 kHz  
THD+N = 10 %; fi = 100 Hz  
short time output power  
RL = 4 ; VP = 15 V  
23.1  
25.7  
25.7  
32.1  
32.1  
-
-
-
-
W
W
W
W
-
28.9  
-
THD+N = 0.5 %  
18.5  
23.9  
20.6  
26.6  
-
-
W
W
THD+N = 10 %  
RL = 8 ; VP = 29 V  
THD+N = 0.5 %  
36.0  
49.5  
40.0  
55.0  
-
-
W
W
THD+N = 10 %  
[1] Rs is the series resistance of inductor and capacitor of low-pass LC filter in the application.  
[2] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall.  
[3] Maximum Vripple = 2 V (p-p); Rs = 0 .  
[4] B = 20 Hz to 20 kHz, AES17 brick wall.  
[5] Output power is measured indirectly; based on RDSon measurement.  
Two layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection.  
TDA8932B_3  
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Class-D audio amplifier  
14. Application information  
14.1 Output power estimation  
The output power Po at THD+N = 0.5 %, just before clipping, for the SE and BTL  
configuration can be estimated using Equation 2 and Equation 3.  
SE configuration:  
2
RL  
× (1 tw(min) × f osc) × VP  
----------------------------------------------------------  
RL + RDSon + Rs + RESR  
------------------------------------------------------------------------------------------------------------------------------------------  
8 × RL  
Po(0.5%)  
=
(2)  
(3)  
BTL configuration:  
2
RL  
-----------------------------------------------------  
RL + 2 × (RDSon + Rs)  
-------------------------------------------------------------------------------------------------------------------------------------  
2 × RL  
× (1 tw(min) × f osc) × VP  
Po(0.5%)  
=
Where:  
VP = supply voltage VDDP1 VSSP1 (V) or VDDP2 VSSP2 (V)  
RL = load impedance ()  
RDSon = on-resistance power switch (Ω)  
Rs = series resistance output inductor (Ω)  
RESR = equivalent series resistance SE capacitor (Ω)  
tw(min) = minimum pulse width (s); 80 ns typical  
fosc = oscillator frequency (Hz); 320 kHz typical with Rosc = 39 kΩ  
The output power Po at THD+N = 10 % can be estimated by:  
Po(10%) = 1.25 × Po(0.5%)  
(4)  
Figure 8 and Figure 9 show the estimated output power at THD+N = 0.5 % and  
THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at  
different load impedances. The output power is calculated with: RDSon = 0.15 (at  
Tj = 25 °C), Rs = 0.05 , RESR = 0.05 and IO(ocp) = 4 A (minimum).  
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Class-D audio amplifier  
001aad768  
001aad769  
40  
40  
P
o
(W)  
R
L
= 4 Ω  
P
(W)  
o
R
L
= 4  
30  
30  
6 Ω  
6 Ω  
20  
10  
0
20  
10  
0
8 Ω  
8 Ω  
10  
20  
30  
40  
10  
20  
30  
40  
V
(V)  
P
V
(V)  
P
a. THD+N = 0.5 %  
b. THD+N = 10 %  
Fig 8. SE output power as a function of supply voltage  
001aad770  
001aad771  
80  
80  
R
L
= 8 Ω  
P
P
o
o
(W)  
(W)  
R
L
= 8 Ω  
60  
60  
6 Ω  
6 Ω  
40  
20  
0
40  
20  
0
4 Ω  
4 Ω  
10  
20  
30  
40  
10  
20  
30  
40  
V
(V)  
V
(V)  
P
P
a. THD+N = 0.5 %  
b. THD+N = 10 %  
Fig 9. BTL output power as a function of supply voltage  
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NXP Semiconductors  
Class-D audio amplifier  
14.2 Output current limiting  
The peak output current IO(max) is internally limited above a level of 4 A (minimum). During  
normal operation the output current should not exceed this threshold level of 4 A  
otherwise the output signal is distorted. The peak output current in SE or BTL  
configurations can be estimated using Equation 5 and Equation 6.  
SE configuration:  
0.5 × VP  
RL + RDSon + Rs + RESR  
IO(max)  
4 A  
(5)  
(6)  
----------------------------------------------------------  
BTL configuration:  
VP  
IO(max)  
4 A  
-----------------------------------------------------  
RL + 2 × (RDSon + Rs)  
Where:  
VP = supply voltage VDDP1 VSSP1 (V) or VDDP2 VSSP2 (V)  
RL = load impedance ()  
RDSon = on-resistance power switch (Ω)  
Rs = series resistance output inductor (Ω)  
RESR = equivalent series resistance SE capacitor (Ω)  
Example:  
A 4 speaker in the BTL configuration can be used up to a supply voltage of 18 V without  
running into current limiting. Current limiting (clipping) will avoid audio holes but it causes  
a comparable distortion like voltage clipping.  
14.3 Speaker configuration and impedance  
For a flat frequency response (second-order Butterworth filter) it is necessary to change  
the low-pass filter components Llc and Clc according to the speaker configuration and  
impedance. Table 14 shows the practical required values.  
Table 14. Filter component values  
Configuration  
RL ()  
Llc (µH)  
22  
Clc (nF)  
680  
SE  
4
6
8
4
6
8
33  
470  
47  
330  
BTL  
10  
1500  
1000  
680  
15  
22  
14.4 Single-ended capacitor  
The SE capacitor forms a high-pass filter with the speaker impedance. So the frequency  
response will roll-off with 20 dB per decade below f-3dB (3 dB cut-off frequency).  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
The 3 dB cut-off frequency is equal to:  
1
f 3dB  
=
(7)  
----------------------------------  
2π × RL × Cse  
Where:  
-3dB = 3 dB cut-off frequency (Hz)  
f
RL = load impedance ()  
Cse = single-ended capacitance (F); see Figure 36  
Table 15 shows an overview of the required SE capacitor values in case of 60 Hz, 40 Hz  
or 20 Hz 3 dB cut-off frequency.  
Table 15. SE capacitor values  
Impedance ()  
Cse (µF)  
f-3dB = 60 Hz  
680  
f-3dB = 40 Hz  
1000  
f-3dB = 20 Hz  
2200  
4
6
8
470  
680  
1500  
330  
470  
1000  
14.5 Gain reduction  
The gain of the TDA8932B is internally fixed at 30 dB for SE (or 36 dB for BTL). The gain  
can be reduced by a resistive voltage divider at the input (see Figure 10).  
R1  
R2  
470 nF  
470 nF  
100  
kΩ  
R3  
audio in  
001aad762  
Fig 10. Input configuration for reducing gain  
When applying a resistive divider, the total closed-loop gain Gv(tot) can be calculated by  
REQ  
Gv(tot) = Gv(cl) + 20log  
(8)  
-----------------------------------------  
REQ + (R1 + R2)  
Where:  
Gv(tot) = total closed-loop voltage gain (dB)  
Gv(cl) = closed-loop voltage gain, fixed at 30 dB for SE (dB)  
REQ = equivalent resistance, R3 and Zi ()  
R1 = series resistor ()  
R2 = series resistor ()  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
R3 × Zi  
R3 + Zi  
REQ  
=
(9)  
------------------  
Where:  
REQ = equivalent resistance (Ω)  
R3 = parallel resistor ()  
Zi = internal input impedance ()  
Example:  
Substituting R1 = R2 = 4.7 k, Zi = 100 kand R3 = 22 kin Equation 8 and Equation 9  
results in a gain of Gv(tot) = 26.3 dB.  
14.6 Device synchronization  
If two or more TDA8932B devices are used in one application it is recommended that all  
devices are synchronized running at the same switching frequency to avoid beat tones.  
Synchronization can be realized by connecting all OSCIO pins together and configure one  
of the TDA8932B devices as master, while the other TDA8932B devices are configured as  
slaves (see Figure 11).  
A device is configured as master when connecting a resistor between pins OSCREF and  
VSSD(HW) setting the carrier frequency. Pin OSCIO of the master is then configured as an  
oscillator output for synchronization. The OSCREF pins of the slave devices should be  
shorted to VSSD(HW) configuring pin OSCIO as an input.  
master  
slave  
IC1  
IC2  
TDA8932B  
TDA8932B  
OSCREF  
V
OSCIO  
OSCIO  
V
OSCREF  
SSD(HW)  
SSD(HW)  
C
R
osc  
39 kΩ  
osc  
100 nF  
001aaf600  
Fig 11. Master slave concept in two chip application  
14.7 Thermal behavior (printed-circuit board considerations)  
The TDA8932B is available in two different thermally enhanced packages:  
TDA8932BT in a SO32 (SOT287-1) package for reflow and wave solder process  
TDA8932BTW in an HTSSOP32 (SOT549-1) package for reflow solder process only  
The SO32 package has special thermal corner-leads, increasing the power capability  
(reducing the overall Rth(j-a). To benefit from the corner leads pins VSSD(HW) (pins 1, 16, 17  
and 32) should be attached to a copper plane. The SO package is very suitable for  
applications with limited space for a thermal plane (in a single layer PCB design).  
TDA8932B_3  
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Class-D audio amplifier  
The HTSSOP32 package has an exposed die-pad that reduces significantly the overall  
Rth(j-a). Therefore it is required to solder the exposed die-pad (at VSSD level) to a copper  
plane for cooling. The HTSSOP package will have a low thermal resistance when used on  
a multi-layer PCB with sufficient space for one or two thermal planes.  
Increasing the area of the thermal plane, the number of planes or the copper thickness  
can reduce further the thermal resistance Rth(j-a) of both packages.  
Typical thermal resistance Rth(j-a) of the SO32 package soldered at a small 2-layer  
application board (55 mm × 45 mm), 35 µm copper, FR4 base material is 44 K/W.  
Typical thermal resistance Rth(j-a) of the HTSSOP32 package soldered at a small 2-layer  
application board (55 mm × 40 mm), 35 µm copper, FR4 base material is 48 K/W.  
Equation 10 shows the relation between the maximum allowable power dissipation P and  
the thermal resistance from junction to ambient.  
T
j(max) Tamb  
Rth( j a)  
=
(10)  
-----------------------------------  
P
Where:  
Rth(j-a) = thermal resistance from junction to ambient  
Tj(max) = maximum junction temperature  
Tamb = ambient temperature  
P = power dissipation which is determined by the efficiency of the TDA8932B  
The power dissipation is shown in Figure 22 (SE) and Figure 34 (BTL).  
The thermal foldback will limit the maximum junction temperature to 140 °C.  
14.8 Pumping effects  
When the amplifier is used in a SE configuration, a so-called 'pumping effect' can occur.  
During one switching interval, energy is taken from one supply (e.g. VDDP1), while a part of  
that energy is delivered back to the other supply line (e.g. VSSP1) and visa versa. When  
the power supply cannot sink energy, the voltage across the output capacitors of that  
power supply will increase.  
The voltage increase caused by the pumping effect depends on:  
Speaker impedance  
Supply voltage  
Audio signal frequency  
Value of decoupling capacitors on supply lines  
Source and sink currents of other channels  
The pumping effect should not cause a malfunction of either the audio amplifier and/or the  
power supply. For instance, this malfunction can be caused by triggering of the  
undervoltage or overvoltage protection of the amplifier.  
Pumping effects in a SE configuration can be minimized by connecting audio inputs in  
anti-phase and change the polarity of one speaker. This is illustrated in Figure 12.  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
IN1P  
IN1N  
OUT1  
OUT2  
audio  
in1  
IN2N  
IN2P  
audio  
in2  
001aad763  
Fig 12. SE application for reducing pumping effects  
TDA8932B_3  
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NXP Semiconductors  
Class-D audio amplifier  
14.9 SE curves measured in reference design  
001aad772  
001aad773  
2
2
10  
10  
THD+N  
(%)  
THD+N  
(%)  
10  
10  
1
1
(1)  
1  
(1)  
1  
10  
10  
(2)  
(3)  
(2)  
(3)  
2  
2  
10  
10  
3  
10  
3  
10  
10  
10  
2  
1  
2
2  
1  
2
10  
1
10  
10  
(W/channel)  
10  
1
10  
10  
P
(W/channel)  
P
o
o
a. VP = 22 V; RL = 2 × 4 Ω  
b. VP = 30 V; RL = 2 × 8 Ω  
(1) fi = 6 kHz  
(2) fi = 100 Hz  
(3) fi = 1 kHz  
Fig 13. Total harmonic distortion-plus-noise as a function of output power per channel  
001aad774  
001aad775  
2
2
10  
10  
THD+N  
(%)  
THD+N  
(%)  
10  
10  
1
1
(1)  
(2)  
(1)  
(2)  
1  
1  
10  
10  
2  
2  
10  
10  
3  
3  
10  
10  
2
3
4
5
2
3
4
5
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
f (Hz)  
i
f (Hz)  
i
a. VP = 22 V; RL = 2 × 4 Ω  
b. VP = 30 V; RL = 2 × 8 Ω  
(1) Po = 10 W  
(2) Po = 1 W  
Fig 14. Total harmonic distortion-plus-noise as a function of frequency  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
001aad776  
001aad777  
40  
0
SVRR  
(dB)  
G
v
(dB)  
20  
30  
40  
60  
(1)  
(2)  
(1)  
(2)  
20  
10  
80  
100  
2
3
4
5
2
3
4
5
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
f (Hz)  
i
f (Hz)  
i
Vi = 100 mV (RMS); Ri = 0 ; Cse = 1000 µF  
(1) VP = 30 V; RL = 2 × 8 Ω  
Vripple = 500 mV (RMS) referenced to ground;  
Ri = 0 (shorted input)  
(1) VP = 30 V; RL = 2 × 8 Ω  
(2) VP = 22 V; RL = 2 × 4 Ω  
(2) VP = 22 V; RL = 2 × 4 Ω  
Fig 15. Gain as a function of frequency  
Fig 16. Supply voltage ripple rejection as a function of  
frequency  
001aad778  
001aad779  
120  
0
α
cs  
(dB)  
(2)  
(1)  
S/N  
(dB)  
20  
80  
40  
60  
40  
(1)  
80  
(2)  
0
10  
100  
2  
1  
2
2
3
4
5
10  
1
10  
10  
(W/channel)  
10  
10  
10  
10  
10  
f (Hz)  
i
P
o
Ri = 0 ; 20 kHz brick-wall filter AES17  
(1) VP = 22 V; RL = 2 × 4 Ω  
Po = 1 W; CHVPREF = 47 µF  
(1) VP = 22 V; RL = 2 × 4 Ω  
(2) VP = 30 V; RL = 2 × 8 Ω  
(2) VP = 30 V; RL = 2 × 8 Ω  
Fig 17. Signal-to-noise ratio as a function of output  
power per channel  
Fig 18. Channel separation as a function of frequency  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
001aaf889  
001aaf886  
6
4
2
0
32  
P
o
(1)  
(2)  
P
(W)  
(W/channel)  
24  
(1)  
16  
8
(3)  
(4)  
(2)  
0
10  
14  
18  
22  
26  
30  
34  
38  
(V)  
10  
14  
18  
22  
26  
30  
34  
38  
(V)  
V
V
P
P
fi = 1 kHz (short time PO); dashed line will require  
heat sink for continuous time output power  
fi = 1 kHz; power dissipation in junction only; short  
time Po at THD+N = 10 %; dashed line will require  
heat sink for continuous time output power  
(1) RL = 2 × 4 ; THD+N = 10 %  
(2) RL = 2 × 4 ; THD+N = 0.5 %  
(3) RL = 2 × 8 ; THD+N = 10 %  
(4) RL = 2 × 8 ; THD+N = 0.5 %  
(1) RL = 2 × 4 Ω  
(2) RL = 2 × 8 Ω  
Fig 19. Output power per channel as a function of  
supply voltage  
Fig 20. Power dissipation as a function of supply  
voltage  
001aad780  
001aad781  
100  
3.0  
(2)  
η
po  
(%)  
(1)  
P
(W)  
80  
60  
40  
20  
0
2.0  
(2)  
(1)  
1.0  
0
10  
2  
1  
2
0
5
10  
15  
20  
10  
1
10  
10  
(W/channel)  
P
(W/channel)  
P
o
o
fi = 1 kHz; power dissipation in junction only  
(1) VP = 22 V; RL = 2 × 4 Ω  
2 × Po  
2 × Po + p  
fi = 1 kHz; ηPO  
=
------------------------  
(2) VP = 30 V; RL = 2 × 8 Ω  
(1) VP = 22 V; RL = 2 × 4 Ω  
(2) VP = 30 V; RL = 2 × 8 Ω  
Fig 21. Output power efficiency as a function of output  
power per channel  
Fig 22. Power dissipation as a function of output power  
per channel (two channels driven)  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
001aaf887  
001aaf888  
32  
32  
P
P
o
o
(W/channel)  
(W/channel)  
(3)  
24  
24  
(2)  
(1)  
(2)  
(1)  
16  
8
16  
8
0
0
0
0
120  
240  
360  
480  
600  
120  
240  
360  
480  
600  
t (s)  
t (s)  
a. RL = 2 × 4 ; fi = 1 kHz; 2 layer SO32 application  
b. RL = 2 × 8 ; fi = 1 kHz; 2 layer SO32 application  
board (55 mm × 45 mm) without heat sink  
board (55 mm × 45 mm) without heat sink  
(1) VP = 22 V  
(2) VP = 26 V  
(3) VP = 29 V  
(1) VP = 30 V  
(2) VP = 34 V  
Fig 23. Output power per channel as a function of time  
001aaf890  
001aaf891  
4
4
V
V
o
o
(V)  
(V)  
3
2
1
0
3
2
1
0
operating  
operating  
sleep  
0.5  
mute  
0.5  
0
1
1.5  
2
2.5  
3
0
1
1.5  
2
2.5  
3
V
(V)  
V
(V)  
POWERUP  
ENGAGE  
Vi = 100 mV (RMS value); fi = 1 kHz; VENGAGE > 3 V  
Vi = 100 mV (RMS value); fi = 1 kHz;  
VPOWERUP > 2 V  
Fig 24. Output voltage as a function of voltage on pin  
POWERUP  
Fig 25. Output voltage as a function of voltage on pin  
ENGAGE  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
14.10 BTL curves measured in reference design  
001aad782  
001aad783  
2
2
10  
10  
THD+N  
(%)  
THD+N  
(%)  
10  
10  
1
1
(1)  
1  
1  
10  
10  
(1)  
(2)  
(3)  
(2)  
(3)  
2  
2  
10  
10  
3  
10  
3  
10  
10  
10  
2  
1  
2
2  
1  
2
10  
1
10  
10  
10  
1
10  
10  
P
(W)  
P
(W)  
o
o
a. VP = 12 V; RL = 4 Ω  
b. VP = 22 V; RL = 8 Ω  
(1) fi = 6 kHz  
(2) fi = 1 kHz  
(3) fi = 100 Hz  
Fig 26. Total harmonic distortion-plus-noise as a function of output power  
001aae114  
001aae115  
2
2
10  
10  
THD+N  
(%)  
THD+N  
(%)  
10  
10  
1
1
1  
1  
10  
10  
(1)  
(2)  
2  
2  
(1)  
(2)  
10  
10  
3  
3  
10  
10  
2
3
4
5
2
3
4
5
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
f (Hz)  
i
f (Hz)  
i
a. VP = 12 V; RL = 4 Ω  
b. VP = 22 V; RL = 8 Ω  
(1) Po = 10 W  
(2) Po = 1 W  
Fig 27. Total harmonic distortion-plus-noise as a function of frequency  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
001aae116  
(2) (1)  
001aae117  
40  
0
SVRR  
(dB)  
G
v
(dB)  
20  
30  
40  
60  
20  
10  
(1)  
(2)  
80  
100  
2
3
4
5
2
3
4
5
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
f (Hz)  
i
f (Hz)  
i
Vi = 100 mV (RMS); Ri = 0 Ω  
(1) VP = 12 V; RL = 4 Ω  
Vripple = 500 mV (RMS) referenced to ground;  
Ri = 0 (shorted input)  
(1) VP = 22 V; RL = 8 Ω  
(2) VP = 22 V; RL = 8 Ω  
(2) VP = 12 V; RL = 4 Ω  
Fig 28. Gain as a function of frequency  
Fig 29. Supply voltage ripple rejection as a function of  
frequency  
001aae118  
001aaf893  
120  
S/N  
70  
P
o
(W)  
60  
(dB)  
(2)  
(1)  
50  
80  
(3)  
(4)  
40  
30  
20  
10  
0
(1)  
(2)  
40  
0
10  
2  
1  
2
10  
1
10  
10  
10  
14  
18  
22  
26  
30  
V
34  
(V)  
P
(W)  
o
P
Ri = 0 ; 20 kHz brick-wall filter AES17  
(1) RL = 4 ; VP = 12 V  
fi = 1 kHz (short time PO); dashed line will require  
heat sink for continuous time output power  
(1) RL = 4 ; THD+N = 10 %  
(2) RL = 4 ; THD+N = 0.5 %  
(3) RL = 8 ; THD+N = 10 %  
(4) RL = 8 ; THD+N = 0.5 %  
(2) RL = 8 ; VP = 22 V  
Fig 30. Signal-to-noise ratio as a function of output  
power  
Fig 31. Output power as a function of supply voltage  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
001aaf896  
001aaf899  
32  
60  
P
(W)  
50  
o
P
(W)  
o
(3)  
(2)  
(1)  
(3)  
24  
40  
30  
20  
10  
0
(2)  
(1)  
16  
8
0
0
120  
240  
360  
480  
600  
0
120  
240  
360  
480  
600  
t (s)  
t (s)  
a. RL = 4 ; fi = 1 kHz; 2 layer SO32 application  
b. RL = 8 ; fi = 1 kHz; 2 layer SO32 application  
board (55 mm × 45 mm) without heat sink  
board (55 mm × 45 mm) without heat sink  
(1) VP = 12 V  
(2) VP = 13.5 V  
(3) VP = 15 V  
(1) VP = 22 V  
(2) VP = 26 V  
(3) VP = 29 V  
Fig 32. Output power as a function of time  
001aae119  
001aae120  
100  
3.0  
η
po  
(%)  
(1)  
P
(W)  
80  
(2)  
2.0  
60  
40  
20  
0
(2)  
1.0  
(1)  
0
10  
2  
1  
2
0
10  
20  
30  
10  
1
10  
10  
P
(W)  
P
(W)  
o
o
fi = 1 kHz; power dissipation in junction only  
(1) VP = 12 V; RL = 4 Ω  
Po  
fi = 1 kHz; ηPO  
=
--------------------  
(Po + p)  
(2) VP = 22 V; RL = 8 Ω  
(1) VP = 12 V; RL = 4 Ω  
(2) VP = 22 V; RL = 8 Ω  
Fig 33. Output power efficiency as a function of output  
power  
Fig 34. Power dissipation as a function of output power  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
001aaf904  
6
4
2
0
P
(W)  
(1)  
(2)  
10  
14  
18  
22  
26  
30  
34  
V
(V)  
P
fi = 1 kHz; power dissipation in junction only; short time Po at THD+N = 10 %; dashed line will require heat sink for  
continuous time output power  
(1) RL = 4 Ω  
(2) RL = 8 Ω  
Fig 35. Power dissipation as a function of supply voltage  
TDA8932B_3  
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NXP Semiconductors  
Class-D audio amplifier  
14.11 Typical application schematics (simplified)  
VP  
Rvdda  
VP  
VPA  
10 Ω  
Cvdda  
100 nF  
Cvddp  
220 µF  
(35 V)  
GND  
V
V
SSD(HW)  
SSD(HW)  
IN1P  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Cin  
OSCIO  
HVP1  
2
Cin  
470 nF  
470 nF  
IN1N  
3
VP  
V
DDP1  
DIAG  
4
Cvddp  
Chvp  
100 nF  
100 nF  
ENGAGE  
POWERUP  
CGND  
BOOT1  
OUT1  
Cbo  
15  
nF  
MUTE control  
SLEEP control  
5
Cen  
470 nF  
Llc  
6
V
SSP1  
7
Rsn  
10 Ω  
V
DDA  
STAB1  
STAB2  
Cosc  
VPA  
8
U1  
TDA8932B  
Csn  
470 pF  
Clc  
Cse  
V
SSA  
100 nF  
Rosc  
9
Cstab  
100 nF  
V
SSP2  
OSCREF  
HVPREF  
INREF  
TEST  
10  
11  
12  
13  
14  
15  
16  
39 kΩ  
Llc  
OUT2  
Cbo  
15  
nF  
Chvpref  
47 µF (25 V)  
Chvp  
100 nF  
BOOT2  
Rsn  
10 Ω  
Cinref  
100 nF  
V
DDP2  
VP  
Cvddp  
100 nF  
Csn  
470 pF  
Clc  
Cse  
Cin  
470 nF  
IN2N  
HVP2  
DREF  
Cin  
470 nF  
IN2P  
Cdref  
Chvp  
V
V
SSD(HW)  
SSD(HW)  
100 nF  
100 nF  
001aaf601  
Fig 36. Typical simplified application diagram for 2 × SE (asymmetrical supply)  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
VP  
Rvdda  
10 Ω  
VP  
VPA  
Cvdda  
100 nF  
Cvddp  
220 µF  
(35 V)  
GND  
V
V
SSD(HW)  
SSD(HW)  
IN1P  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Rhvp  
470 Ω  
Rhvp  
470 Ω  
Cin  
OSCIO  
HVP1  
2
Cin  
1 µF  
IN1N  
3
VP  
1 µF  
V
DDP1  
DIAG  
4
Cvddp  
100 nF  
Chvp  
100 nF  
ENGAGE  
POWERUP  
CGND  
BOOT1  
OUT1  
Cbo  
15 nF  
MUTE  
control  
5
Cen  
470 nF  
Llc  
6
V
SSP1  
SLEEP  
control  
7
Rsn  
10 Ω  
Clc  
Clc  
V
DDA  
STAB1  
STAB2  
Cosc  
VPA  
8
U1  
TDA8932B  
Csn  
470 pF  
V
SSA  
100 nF  
Rosc  
9
Cstab  
100 nF  
V
SSP2  
OSCREF  
HVPREF  
INREF  
TEST  
10  
11  
12  
13  
14  
15  
16  
39 kΩ  
Llc  
OUT2  
Cbo  
BOOT2  
15 nF  
Rsn  
10 Ω  
Chvp  
100 nF  
Cinref  
V
DDP2  
100 nF  
VP  
Cvddp  
100 nF  
Csn  
470 pF  
IN2N  
HVP2  
DREF  
IN2P  
Cdref  
Chvp  
V
V
SSD(HW)  
SSD(HW)  
100 nF  
100 nF  
001aaf602  
Fig 37. Typical simplified application diagram for 1 × BTL (asymmetrical supply)  
TDA8932B_3  
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NXP Semiconductors  
Class-D audio amplifier  
VDD  
Rvdda  
VDD  
GND  
VSS  
VDDA  
VSSA  
10 Ω  
Cvddp  
220 µF  
(25 V)  
Cvdda  
100 nF  
Cvssp  
220 µF  
(25 V)  
Cvssa  
100 nF  
Rvssa  
10 Ω  
VSS  
V
V
SSD(HW)  
SSD(HW)  
IN1P  
VSSA  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
VSSA  
Cin  
OSCIO  
HVP1  
2
Cin  
470 nF  
470 nF  
IN1N  
3
VDD  
V
DDP1  
DIAG  
4
Cvddp  
100 nF  
ENGAGE  
POWERUP  
CGND  
BOOT1  
OUT1  
Cbo  
15 nF  
MUTE control  
SLEEP control  
5
Cen  
470 nF  
Llc  
6
V
SSP1  
Rsn  
10 Ω  
7
VSS  
Cvssp  
100 nF  
V
DDA  
STAB1  
STAB2  
Cosc  
Csn  
470 pF  
VDDA  
VSSA  
8
U1  
TDA8932B  
Clc  
V
SSA  
VSS  
100 nF  
Rosc  
9
Cstab  
100 nF  
Cvssp  
V
SSP2  
OSCREF  
HVPREF  
INREF  
VSSA  
10  
11  
12  
13  
14  
15  
16  
39 kΩ  
100 nF  
Llc  
OUT2  
Cbo  
15 nF  
BOOT2  
Rsn  
10 Ω  
Cinref  
100 nF  
V
DDP2  
TEST  
VDD  
Cin  
Cvddp  
100 nF  
Csn  
470 pF  
IN2N  
HVP2  
DREF  
Clc  
Cin  
470 nF  
470 nF  
IN2P  
Cdref  
100 nF  
V
V
SSD(HW)  
SSD(HW)  
VSSA  
VSSA  
001aaf603  
Fig 38. Typical simplified application diagram for 2 × SE (symmetrical supply)  
TDA8932B_3  
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NXP Semiconductors  
Class-D audio amplifier  
VDD  
Rvdda  
VDD  
GND  
VSS  
VDDA  
VSSA  
10 Ω  
Cvddp  
220 µF  
(25 V)  
Cvdda  
100 nF  
Cvssp  
220 µF  
(25 V)  
Cvssa  
100 nF  
Rvssa  
10 Ω  
VSS  
V
V
SSD(HW)  
SSD(HW)  
IN1P  
VSSA  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
VSSA  
Cin  
OSCIO  
HVP1  
2
Cin  
1 µF  
IN1N  
3
VDD  
1 µF  
V
DDP1  
DIAG  
4
Cvddp  
100 nF  
ENGAGE  
POWERUP  
CGND  
BOOT1  
OUT1  
Cbo  
15 nF  
MUTE  
control  
5
Cen  
470 nF  
Llc  
6
V
SSP1  
Rsn  
10 Ω  
SLEEP  
control  
7
VSS  
Cvssp  
100 nF  
Clc  
V
DDA  
STAB1  
STAB2  
Cosc  
VDDA  
VSSA  
8
Csn  
470 pF  
U1  
TDA8932B  
V
SSA  
VSS  
100 nF  
Rosc  
9
Cstab  
100 nF  
Cvssp  
100 nF  
V
SSP2  
OSCREF  
HVPREF  
INREF  
TEST  
Clc  
VSSA  
10  
11  
12  
13  
14  
15  
16  
39 kΩ  
Llc  
OUT2  
Cbo  
15 nF  
BOOT2  
Rsn  
10 Ω  
Cinref  
V
DDP2  
100 nF  
VDD  
IN2N  
HVP2  
DREF  
Cvddp  
100 nF  
Csn  
470 pF  
IN2P  
Cdref  
100 nF  
V
V
SSD(HW)  
SSD(HW)  
VSSA  
VSSA  
001aaf606  
Fig 39. Typical simplified application diagram for 1 × BTL (symmetrical supply)  
15. Test information  
15.1 Quality information  
The General Quality Specification for Integrated Circuits, SNW-FQ-611 is applicable.  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
16. Package outline  
SO32: plastic small outline package; 32 leads; body width 7.5 mm  
SOT287-1  
D
E
A
X
c
y
H
v
M
A
E
Z
17  
32  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
16  
1
w M  
detail X  
b
p
e
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.  
0.3  
0.1  
2.45  
2.25  
0.49  
0.36  
0.27 20.7  
0.18 20.3  
7.6  
7.4  
10.65  
10.00  
1.1  
0.4  
1.2  
1.0  
0.95  
0.55  
mm  
2.65  
0.25  
0.01  
1.27  
0.05  
1.4  
0.25  
0.01  
0.25  
0.01  
0.1  
8o  
0o  
0.012 0.096  
0.004 0.089  
0.02 0.011 0.81  
0.01 0.007 0.80  
0.30  
0.29  
0.419  
0.394  
0.043 0.047  
0.016 0.039  
0.037  
0.022  
inches  
0.1  
0.004  
0.055  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
00-08-17  
03-02-19  
SOT287-1  
MO-119  
Fig 40. Package outline SOT287-1 (SO32)  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;  
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad  
SOT549-1  
E
A
X
D
c
H
v
M
y
A
exposed die pad side  
E
D
h
Z
32  
17  
A
(A )  
3
2
E
A
h
A
1
pin 1 index  
θ
L
p
L
detail X  
1
16  
w
M
b
e
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions).  
A
(1)  
(2)  
UNIT  
A
A
A
b
c
D
D
E
E
e
H
L
L
p
v
w
y
Z
θ
1
2
3
p
h
h
E
max.  
8o  
0o  
0.15 0.95  
0.05 0.85  
0.30 0.20 11.1  
0.19 0.09 10.9  
5.1  
4.9  
6.2  
6.0  
3.6  
3.4  
8.3  
7.9  
0.75  
0.50  
0.78  
0.48  
mm  
1.1  
0.65  
1
0.2  
0.25  
0.1  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
03-04-07  
05-11-02  
SOT549-1  
MO-153  
Fig 41. Package outline SOT549-1 (HTSSOP32)  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
17. Soldering  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
17.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
17.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
Through-hole components  
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
Board specifications, including the board finish, solder masks and vias  
Package footprints, including solder thieves and orientation  
The moisture sensitivity level of the packages  
Package placement  
Inspection and repair  
Lead-free soldering versus PbSn soldering  
17.3 Wave soldering  
Key characteristics in wave soldering are:  
Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
Solder bath specifications, including temperature and impurities  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
17.4 Reflow soldering  
Key characteristics in reflow soldering are:  
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 42) than a PbSn process, thus  
reducing the process window  
Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 16 and 17  
Table 16. SnPb eutectic process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (°C)  
Volume (mm3)  
< 350  
235  
350  
220  
< 2.5  
2.5  
220  
220  
Table 17. Lead-free process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (°C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 42.  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 42. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
18. Abbreviations  
Table 18. Abbreviations  
Acronym  
BTL  
Description  
Bridge Tied Load  
DMOS  
ESD  
OCP  
OTP  
OVP  
PWM  
SE  
Double diffused Metal Oxide Semiconductor  
ElectroStatic Discharge  
OverCurrent Protection  
OverTemperature Protection  
OverVoltage Protection  
Pulse Width Modulation  
Single-Ended  
TF  
Thermal Foldback  
UBP  
UVP  
WP  
UnBalance Protection  
UnderVoltage Protection  
Window Protection  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
19. Revision history  
Table 19. Revision history  
Document ID  
TDA8932B_3  
Modifications:  
TDA8932B_2  
TDA8932B_1  
Release date  
20070621  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
TDA8932B_2  
Status upgraded to Product data sheet  
20070329  
Preliminary data sheet  
-
-
TDA8932B_1  
-
20070214  
Objective data sheet  
TDA8932B_3  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
20. Legal information  
20.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of a NXP Semiconductors product can reasonably be expected to  
20.2 Definitions  
result in personal injury, death or severe property or environmental damage.  
NXP Semiconductors accepts no liability for inclusion and/or use of NXP  
Semiconductors products in such equipment or applications and therefore  
such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
20.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
20.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
21. Contact information  
For additional information, please visit: http://www.nxp.com  
For sales office addresses, send an email to: [email protected]  
TDA8932B_3  
© NXP B.V. 21 June 2007. All rights reserved.  
Product data sheet  
Rev. 03 — 21 June 2007  
47 of 48  
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TDA8932B  
NXP Semiconductors  
Class-D audio amplifier  
22. Contents  
considerations) . . . . . . . . . . . . . . . . . . . . . . . . 26  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 21 June 2007.  
All rights reserved.  
For sales office addresses, please send an email to: [email protected]  
Date of release: 21 June 2007  
Document identifier: TDA8932B_3  
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