Intel Tablet Accessory LXD381 User Manual

LXD381 — Evaluation Board for  
Octal E1 Applications  
Developer Manual  
January 2001  
As of January 15, 2001, this document replaces the Level One document  
Order Number: 249213-001  
LXD381 — Evaluation Board for Octal E1 Applications User Guide.  
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Contents  
General Description ..................................................................................................5  
Evaluation Board Set-Up.........................................................................................7  
Evaluation Board Schematics.............................................................................10  
Figures  
Tables  
LXD381 Evaluation Board for Octal E1 Applications Developer Manual  
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Evaluation Board for Octal E1 Applications LXD381  
1.0  
General Description  
The LXD381 evaluation board is a versatile tool for engineers designing E1 short haul applications  
using the LXT381.  
The evaluation board operates in Hardware mode only. All device and channel controls are set  
using jumper blocks and DIP switches.  
The board provides banana jacks for both power and line interface connections. Connectors are  
provided for each framer or back-end ASIC interface. An E1 pattern generator/analyzer may be  
used to provide external signals for evaluation.  
1.1  
Features  
Hardware controllable  
ZIF LQFP socket for easy swapping of LXT381  
Banana jacks for power and line interfaces  
10-pin connectors for framer/ASIC interface  
Socketed termination components for easy experimentation  
Built-in overvoltage protection for line interface and power supply  
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LXD381 Evaluation Board for Octal E1 Applications  
Figure 1. LXD381 Evaluation Board  
6
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Evaluation Board for Octal E1 Applications LXD381  
2.0  
Evaluation Board Set-Up  
Caution: CMOS devices are static (ESD) sensitive. Take all industry standard precautions when handling the  
evaluation board, the LXT381 chip and other sensitive electronic components.  
Before proceeding with any evaluation board operations, review the specifications for the LXT381  
transceiver.  
2.1  
LXD381 Packing List  
The evaluation board kit contains the following components:  
LXD381 board with LXT381 device installed.  
LXD381 User Guide.  
LXT381 Data Sheet.  
2.2  
Equipment Requirements  
The evaluation board kit includes all the circuit components needed for a successful evaluation.  
However, the following lab equipment is required:  
Power Supply (+3.3 VDC).  
Telecom cable or cable simulator (optional).  
E1 pattern generator/analyzer  
2.3  
2.4  
Power Connections  
The evaluation board has two power planes (VCC and TVCC) each of which is tied to a separate  
red colored banana jack. Connect the +3.3 VDC power supply to both the VCC (B1) and TVCC  
(B3) banana jacks. Connect the power supply ground lead to the black banana jack (B2).  
Loopback Mode Selection  
The LXT381 LOOP signals for channels 0 through 7 are set by the switches in switch block S1. As  
shown in Table 1, these switches have three positions to select Remote Loopback, Analog  
Loopback or No Loopback.  
Table 1. LOOP0 - 7 Switch Settings  
S1 Switch Position  
Operation  
High  
Center  
Low  
Analog Loopback  
No Loopback  
Remote Loopback  
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LXD381 Evaluation Board for Octal E1 Applications  
2.5  
2.6  
2.7  
Receive Polarity Selection  
The polarity of RPOS/RNEG is determined by the CLKE switch in switch block S2. When the  
CLKE switch is OFF, RPOS/RNEG are active Low. When set to the ON position, RPOS/RNEG  
are active High. Note that the CLKE switch controls the LXT381s RPOL pin.  
Output Enable Selection  
The OE switch in switch block S3 controls the operation of the LXT381 output drivers. For normal  
operation (driver outputs enabled), set the OE switch to the ON position. Setting the OE switch to  
OFF forces the output drivers to the high impedance state.  
Unused Switches  
Switches 3 and 4, in switch block S2, have no function on the LXD381 and should be set to the  
OFF position. Figure 2 shows the factory default settings for switch block S2.  
Figure 2. S2 Factory Switch Settings  
S2  
CLKE  
OE  
NOTE: OFF position = Low  
2.8  
Back-End Interface Connection  
Eight 10 pin connectors (JP1 - JP8) provide access to the LXT381 digital signals to allow  
interfacing the back-end Framer/Mapper or ASIC with an external pattern generator. Figure 3  
shows a typical connector (JP1 for channel 0) with the factory installed jumper connecting RCLK  
to TCLK. This jumper is normally installed when feeding analog test data from the line interface  
(TIP and RING).  
8
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Evaluation Board for Octal E1 Applications LXD381  
Figure 3. Typical Back-End Connector  
JP1  
1
3
2
TCLK 0  
GND  
4
RCLK 0  
TCLK 0  
5
7
6
8
TPOS 0  
TNEG 0  
LOS 0  
RPOS 0  
RNEG 0  
GND  
10  
9
2.9  
Line Interface Connection  
Access to the line interface is provided through the green and white banana jacks. The TIP signal is  
routed to the white jacks for both transmit and receive directions. The RING signal is routed to the  
green jacks for both directions.  
2.10  
Line Interface Circuit  
Two octal transformers are used for channels 0 to 3 and 4 to 7. Transformers, resistors and  
capacitors for channels 0 and 4 are socketed for easy swapping (see the LXT381 data sheet for line  
interface information). Jumper blocks are provided to configure the receive transformer operation  
for 1:1 or 1:2 turns ratio (see Evaluation Board Schematicson page 10). Factory installed  
jumpers configure the transformers for a 1:1 ratio.  
2.11  
Board Protection  
The evaluation board provides line surge protection for both the power supply and the line. Two  
transient voltage suppressors (TVS) are included for power supply protection. The E1 line interface  
transmitters are protected with Schottky diodes and the receivers are protected by series input  
resistors. This protection is sufficient for G.703 Annex B compliance.  
Developer Manual  
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LXD381 Evaluation Board for Octal E1 Applications  
3.0  
Evaluation Board Schematics  
Figure 4. Evaluation Board Schematic Data/Control  
G N D I O 1  
9 1  
V C C I O 1  
G N D 1  
8 9  
9 2  
V C C I O 0  
G N D I O 0  
1 8  
1 7  
V C C 1  
9 0  
G N D 0  
2 0  
V C C 0  
1 9  
10  
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Evaluation Board for Octal E1 Applications LXD381  
Figure 5. Evaluation Board Schematic Digital I/O  
Developer Manual  
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LXD381 Evaluation Board for Octal E1 Applications  
Figure 6. Evaluation Board Schematic Analog 1  
2
2
2
2
12  
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Evaluation Board for Octal E1 Applications LXD381  
Figure 7. Evaluation Board Schematic Analog 2  
2
2
2
2
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