Intel Server STL2 User Manual

STL2 Server Board

Technical Product Specification

Revision 1.0

September 22, 2000

Enterprise Platforms Group

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STL2 Server Board TPS

Table of Contents

1. Introduction .....................................................................................................................1-1

1.1 Purpose......................................................................................................................1-1

1.2 Audience ....................................................................................................................1-1

1.3 STL2 Server Board Feature Overview........................................................................1-1

1.4 STL2 Server Board Block Diagram.............................................................................1-2

2. STL2 Server Board Architecture Overview ...................................................................2-5

2.1 Intel® Pentium® III Processor Subsystem..................................................................2-5

1.1.1 Supported Processor Types....................................................................................2-5

1.1.2 Dual Processor Operation.......................................................................................2-6

1.1.3 PGA370 Socket.......................................................................................................2-6

1.1.4 Processor Bus Termination / Regulation / Power....................................................2-6

1.1.5 Termination Package ..............................................................................................2-6

1.1.6 APIC Bus.................................................................................................................2-6

1.1.7 Boxed Processors ...................................................................................................2-6

1.2 ServerWorks ServerSet III LE Chipset........................................................................2-7

1.3 Memory.......................................................................................................................2-7

1.4 PCI I/O Subsystem .....................................................................................................2-8

1.4.1 64-bit / 66 MHz PCI Subsystem...............................................................................2-8

1.4.2 32-bit/33 MHz PCI Subsystem...............................................................................2-10

1.5 Chipset Support Components ..................................................................................2-15

1.5.1 Legacy I/O (Super I/O) National* PC97317VUL....................................................2-15

1.5.2 BIOS Flash............................................................................................................2-17

1.1.3 External Device Connectors..................................................................................2-17

1.6 Interrupt Routing.......................................................................................................2-17

1.6.1 Default I/O APIC....................................................................................................2-17

1.6.2 Extended I/O APIC................................................................................................2-17

1.6.3 PCI Ids...................................................................................................................2-20

1.6.4 Relationship between PCI IRQ and PCI Device ....................................................2-20

3. Server Management ......................................................................................................3-23

3.1 Baseboard Management Controller..........................................................................3-23

3.2 Hardware Sensors....................................................................................................3-24

3.3 ACPI.........................................................................................................................3-27

3.4 AC Link Mode...........................................................................................................3-28

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3.5 Wake On LAN Function............................................................................................3-28

4. Basic Input Output System (BIOS)...............................................................................4-29

4.1 BIOS Overview.........................................................................................................4-29

4.1.1 System BIOS.........................................................................................................4-30

4.1.2 Flash Update Utility ...............................................................................................4-30

4.2 Setup Utility ..............................................................................................................4-31

4.2.1 Configuration Utilities Overview.............................................................................4-31

4.2.2 Setup Utility Operation ..........................................................................................4-31

4.3 CMOS Memory Definition .........................................................................................4-42

4.4 CMOS Default Override............................................................................................4-43

4.5 Flash Update Utility ..................................................................................................4-43

4.5.1 Loading the System BIOS.....................................................................................4-43

4.5.2 OEM Customization...............................................................................................4-44

4.5.3 Language Area......................................................................................................4-47

4.5.4 Recovery Mode .....................................................................................................4-47

4.6 Error Messages and Error Codes .............................................................................4-48

4.6.1 POST Codes.........................................................................................................4-48

4.6.2 POST Error Codes and Messages........................................................................4-52

4.7 Identifying BIOS and BMC Revision Levels..............................................................4-55

4.7.1 BIOS Revision Level Identification ........................................................................4-55

4.7.2 BMC Revision Level Identification.........................................................................4-55

4.8 Adaptec SCSI Utility .................................................................................................4-56

4.8.1 Running the SCSI Utility........................................................................................4-56

4.8.2 Adaptec SCSI Utility Configuration Settings..........................................................4-56

4.8.3 Exiting Adaptec SCSI Utility ..................................................................................4-58

5. Jumpers and Connectors .............................................................................................5-61

5.1 Jumper Blocks..........................................................................................................5-63

5.1.1 Setting CMOS/Password Clear Jumper Block 1J15..............................................5-63

5.1.2 Setting Configuration Jumper Block 1L4...............................................................5-66

5.1.3 Setting Configuration Jumper Block 6A.................................................................5-67

5.2 Connectors...............................................................................................................5-67

5.2.1 Main ATX Power Connector (P33) ........................................................................5-68

5.2.2 Auxilary ATX Power Connector (P34) ...................................................................5-68

5.2.3 I²C Power Connector (P37) ...................................................................................5-68

5.2.4 System Fan Connectors (P29, P27, P11) .............................................................5-69

5.2.5 Processor Connectors (P12, P36).........................................................................5-69

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5.2.6 Speaker Connector (P31)......................................................................................5-69

5.2.7 Speaker Connector (P25)......................................................................................5-69

5.2.8 Diskette Drive Connector (P20).............................................................................5-70

5.2.9 SVGA Video Port ..................................................................................................5-70

5.2.10 Keyboard and Mouse Connectors.......................................................................5-71

5.2.11 Parallel Port ........................................................................................................5-71

5.2.12 Serial Ports COM1 and COM2............................................................................5-71

5.2.13 RJ-45 LAN Connector.........................................................................................5-72

5.2.14 USB Connectors .................................................................................................5-72

5.2.15 Ultra SCSI Connector (P9)..................................................................................5-73

5.2.16 Ultra160 SCSI Connector (P8)............................................................................5-73

5.2.17 IDE Connector (P19)...........................................................................................5-74

5.2.18 32-Bit PCI Connector ..........................................................................................5-75

5.2.19 64-Bit PCI Connector ..........................................................................................5-76

5.2.20 Front Panel 24-pin Connector Pinout (P23)........................................................5-77

6. Power Consumption......................................................................................................6-81

6.1 Calculated Power Consumption ...............................................................................6-81

6.2 Measured Power Consumption ................................................................................6-82

7. Mechanical Specifications............................................................................................7-83

8. Regulatory and Integration Information.......................................................................8-85

8.1 Regulatory Compliance ............................................................................................8-85

8.2 Installation Instructions .............................................................................................8-86

8.2.1 Ensure EMC..........................................................................................................8-86

8.2.2 Ensure Host Computer and Accessory Module Certifications ...............................8-86

8.2.3 Prevent Power Supply Overload ...........................................................................8-87

8.2.4 Place Battery Marking on Computer......................................................................8-87

8.2.5 Use Only for Intended Applications.......................................................................8-88

8.2.6 Installation Precautions .........................................................................................8-88

8.3 Environmental Limits ................................................................................................8-88

8.3.1 System Office Environment...................................................................................8-88

8.3.2 System Environmental Testing..............................................................................8-89

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List of Figures

STL2 Server Board TPS

List of Figures

Figure 1-1. STL2 Server Board Block Diagram .......................................................................1-3

Figure 2-1. Embedded NIC PCI Signals ................................................................................2-11

Figure 2-2. Video Controller PCI Signals...............................................................................2-12

Figure 2-3. STL2 Baseboard Interrupt Routing Diagram (PIC mode) ....................................2-18

Figure 2-4. STL2 Baseboard Interrupt Routing Diagram (Symmetric mode) .........................2-19

Figure 5-1. STL2 Server Board Jumper and Connector Locations........................................5-61

Figure 5-2. I/O Back Panel Connectors.................................................................................5-62

Figure 5-3. Diskette Drive Connector Pin Diagram................................................................5-70

Figure 5-4. IDE Connector Pin Diagram ................................................................................5-74

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List of Tables

Table 2-1. STL2 Server Board Supported Processors ............................................................2-5

Table 2-2. SCSI Transfer Speeds ...........................................................................................2-9

Table 2-3. Embedded SCSI Supported PCI Commands.........................................................2-9

Table 2-4. Video Controller Supported PCI Commands........................................................2-13

Table 2-5. Standard VGA Modes ..........................................................................................2-13

Table 2-6. STL2 PCI IDs........................................................................................................2-20

Table 4-1. Setup Utility Screen..............................................................................................4-31

Table 4-2. Main Menu Selections ..........................................................................................4-34

Table 4-3. Primary Master and Slave Adapters Submenu Selections ...................................4-35

Table 4-4. Processor Settings Submenu Selections .............................................................4-35

Table 4-5. Advanced Menu Selections..................................................................................4-36

Table 4-6. Memory Reconfiruation Submenu Selections.......................................................4-36

Table 4-7. Peripheral Configuration Submenu Selections.....................................................4-37

Table 4-8. PCI Device Submenu Selections..........................................................................4-38

Table 4-9. Option ROM Submenu Selections........................................................................4-38

Table 4-10. Numlock Submenu Selections............................................................................4-38

Table 4-11. Security Menu Selections...................................................................................4-39

Table 4-12. Secure Mode Submenu Selections ....................................................................4-40

Table 4-13. Server Menu Selections .....................................................................................4-40

Table 4-14. Wake On Events Submenu Selections ..............................................................4-40

Table 4-15. Console Redirection Submenu Selections .........................................................4-41

Table 4-16. Boot Menu Selections ........................................................................................4-41

Table 4-17. Boot Device Priority Selections ..........................................................................4-41

Table 4-18. Hard Drive Selections.........................................................................................4-42

Table 4-19. Removable Devices Selections..........................................................................4-42

Table 4-20. Exit Menu Selections..........................................................................................4-42

Table 4-21. User Binary Area Scan Point Definitions............................................................4-46

Table 4-22. Format of the User Binary Information Structure................................................4-47

Table 4-23. Port-80h Code Definition....................................................................................4-48

Table 4-24. Standard BIOS Port-80 Codes ...........................................................................4-49

Table 4-25. Recovery BIOS Port-80 Codes...........................................................................4-52

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Table 4-26. POST Error Messages and Codes .....................................................................4-52

Table 4-27. Adaptec SCSI Utility Setup Configurations.........................................................4-57

Table 5-1. Jumper Block 1J15 Settings.................................................................................5-64

Table 5-2. Jumper Block 5E1 Settings ..................................................................................5-66

Table 5-3. Jumper Block 1J15 Default Settings.....................................................................5-66

Table 5-4. Jumper Block 1L4 Settings...................................................................................5-67

Table 5-5. Jumper Block 6A Settings ....................................................................................5-67

Table 5-6. Main ATX Power Connector Pinout......................................................................5-68

Table 5-7. Auxiliary ATX Power Connector Pinout ................................................................5-68

Table 5-8. I²C Power Connector Pinout.................................................................................5-68

Table 5-9. Board Fan Connector Pinout................................................................................5-69

Table 5-10. Processor Fan Connector Pinout .......................................................................5-69

Table 5-11. Speaker Connector Pinout .................................................................................5-69

Table 5-12. Speaker Connector Pinout .................................................................................5-69

Table 5-13. Diskette Drive Connector Pinout ........................................................................5-70

Table 5-14. Video Port Connector Pinout..............................................................................5-70

Table 5-15. Keyboard and Mouse Connector Pinouts...........................................................5-71

Table 5-16. Parallel Port Connector Pinouts .........................................................................5-71

Table 5-17. Serial Ports COM1 and COM2 Connector Pinouts.............................................5-71

Table 5-18. RJ-45 LAN Connector Signals............................................................................5-72

Table 5-19. USB Connectors.................................................................................................5-72

Table 5-20. Ultra SCSI Connector Pinout..............................................................................5-73

Table 5-21. Ultra160 SCSI Connector...................................................................................5-73

Table 5-22. IDE Connector Pinout.........................................................................................5-74

Table 5-23. 32-Bit PCI Connector Pinout ..............................................................................5-75

Table 5-24. 64-Bit PCI Connctor Pinout ................................................................................5-76

Table 5-25. Front Panel 24-pin Connector Pinout .................................................................5-77

Table 6-1. STL2 Server Board Calculated Power Consumption............................................6-81

Table 6-2. STL2 Server Board Measured Power Consumption.............................................6-82

Table 8-1. Safety Regulations...............................................................................................8-85

Table 8-2. Office System Environment Summary..................................................................8-88

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STL2 Server Board TPS

Introduction

1. Introduction

1.1 Purpose

This document provides an architectural overview of the STL2 server board, including the

board layout of major components and connectors, and an overview of the server board’s

feature set.

1.2 Audience

This document is written for technical personnel who want a technical overview of the STL2

server board. Familiarity with the personal computer, Intel server architecture and the PCI local

bus architecture is assumed.

1.3 STL2 Server Board Feature Overview

The STL2 server board provides the following features:

Dual Intel® Pentium® III processor support.

Support for one or two identical Intel Pentium III processors for the PGA370 socket,

which utilizes a new package technology called the Flip Chip Pin Grid Array (FC-

PGA) package.

One embedded VRM for support of the primary processor, and one VRM connector

for support of the secondary processor.

ServerWorks* ServerSet* III LE chipset.

133 MHz Front Side Bus Capability.

NB6635 North Bridge 3.0 LE.

IB6566 South Bridge.

Support for four 3.3V, registered ECC SDRAM DIMMs that are compliant with the

JEDEC PC133 specification.

Support for DIMM sizes 64 MB to 1GB. Four DIMM slots allow a maxiumum installed

memory of 4GB.

ECC single-bit correction, and multiple-bit detection.

64-bit, 66 MHz, 3.3V keyed PCI segment with two expansion connectors and one

embedded device.

Two 64-bit, 66 MHz, 3.3V keyed PCI expansion slots.

Integrated on-board Adaptec* AIC7899 PCI dual-port SCSI controller that provides

separate Ultra160 and Ultra Wide SCSI channels.

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32-bit, 33 MHz, 5V keyed PCI segment with four expansion connectors and three

embedded devices.

Four 32-bit, 33 MHz, 5V keyed PCI expansion slots.

IB6566 South Bridge, which provides IDE and USB controller functions.

Integrated on-board Intel® EtherExpress™ PRO100+ 10/100megabit PCI Ethernet

controller (Intel® 82559) with an RJ-45 Ethernet connector.

Integrated on-board ATI Rage* IIC video controller with 4 MB of on-board SGRAM

video memory.

Compatibility bus segment with three embedded devices.

Super I/O Controller (PC97317) that provides all PC-compatible I/O (floppy, parallel,

serial, keyboard, mouse, and Real-Time Clock).

Baseboard Management Controller (BMC) (DS80CH11) that provides monitoring,

alerting, and logging of critical system information including thermal, voltage, fan,

and chassis intrusion information obtained from embedded sensors on the server

board.

8 MB Flash device for system BIOS.

Dual Universal Serial Bus (USB) ports.

One IDE connector.

Flash BIOS support for all of the above.

Extended ATX board form factor (12” x 13”).

1.4 STL2 Server Board Block Diagram

The STL2 server board offers a “flat” design, with the processors and memory subsystems

residing on the board. The following figure shows the major functional blocks of the STL2

server board. The following section describes the major components of the server board.

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Introduction

STL2 Server Board Block Diagram

133 MHz System Bus

PC133 Registered ECC

SDRAM DIMMs

2 64bit/66Mhz, 3.3V PCI

NB6635

North Bridge

3.0 LE

PCI 64bit/66MHz

SCSI Adaptec*

AIC7899

2 32bit/33MHz, 5V PCI

2 USB

IB6566

South

Bridge

ServerSet*

3.0 LE

PCI 32bit/33MHz

IDE

STL2

Features

ISA Bus

PCI Video

10/100 LAN

ATI* Rage IIC

Intel 82559

Floppy

BIOS

FLASH

BMC

80CH11

Keyboard, Mouse

2 Serial Ports

Parallel Port

Super I/O

PC97317VUL

SGRAM

4MB

RTC

Figure 1-1. STL2 Server Board Block Diagram

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STL2 Server Board Architecture Overview

2. STL2 Server Board Architecture Overview

The architecture of the STL2 server board is based on a design that supports dual-processor

operation with Intel Pentium III processors and the ServerWorks ServerSet III LE chipset.

The STL2 server contains embedded devices for video, NIC, SCSI, and IDE. The STL2 server

board also provides support for server management and monitoring hardware, and interrupt

control that supports dual-processor and PC/AT compatible operation.

The section provides an overview of the following STL2 subsystems:

Pentium III processor subsystem

SeverWorks ServerSet III LE chipset

Memory

PCI Subsystem

Chipset Support Components

BMC server management controller

2.1 Intel® Pentium® III Processor Subsystem

The STL2 server board is designed to accommodate one or two Intel Pentium III processors for

the PGA370 socket. The Pentium III processor for the PGA370 socket is the next member of

the P6 family in the Intel IA-32 processor line. This processor uses the same core and offers

the same performance as the Intel Pentium III processor for the SC242 connector, but utilizes

a new package technology called flip chip pin grid array, or FC-PGA. This package utilizes the

same 370-pin zero-insertion force socket (PGA370) used by the Intel® Celeron™ processor.

The STL2 server board utilizes Pentium III PGA370 socket processors, which interface with the

front side bus at 133 MHz.

2.1.1

Supported Processor Types

The table below summarizes the processors that are planned to be supported on the STL2

server board:

Table 2-1. STL2 Server Board Supported Processors

Speed

FSB Frequency Cache Size

Core

1 GHz

133 MHz

256K

CuMine

933 MHz

866 MHz

800 MHz

733 MHz

667 MHz

CuMine

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2.1.2

Dual Processor Operation

The Pentium III processor interface is designed to be MP-ready. Each processor contains a

local APIC section for interrupt handling. When two processors are installed, both processors

must be of identical revision, core voltage, and bus/core speeds.

2.1.3

PGA370 Socket

The STL2 server board provides two PGA370 sockets. These are 370-pin zero-insertion force

(ZIF) sockets that a flip chip pin grid array (FC-PGA) package technology processor plugs into.

2.1.4

Processor Bus Termination / Regulation / Power

The termination circuitry required by the Intel Pentium III processor bus (AGTL+) signaling

environment, and the circuitry to set the AGTL+ reference voltage, are implemented directly on

the processor. The STL2 server board provides VRM 8.4 compliant DC-to-DC converters to

provide processor power (VCCP) at each PGA370 socket. The server board provides an

embedded VRM for the primary processor and a VRM socket for the secondary processor.

These are powered from the +5V supply.

2.1.5

Termination Package

If a processor is not installed in a PGA370 socket, a termination package must be installed in

the vacant socket to ensure reliable termination.

2.1.6

APIC Bus

Interrupt notification and generation for the processors is done using an independent path

between local APICs in each processor and the I/O APIC located in the IB6566 South Bridge

component.

2.1.7

Boxed Processors

The Intel Pentium III processor for the PGA370 socket is offered as an Intel boxed processor.

Intel boxed processors are intended for system integrators who build systems from a server

board and standard components.

2.1.7.1

Boxed Process Fan Heatsinks

The boxed Pentium III processor for the PGA370 socket will be supplied with an unattached

fan heatsink that has an integrated clip. Clearance is required around the fan heatsink to

ensure unimpeded airflow for proper cooling. Note that the airflow of the fan heatsink is into

the center and out of the sides of the fan heatsink. The boxed processor thermal solution must

be installed by a system integrator to secure the thermal cooling solution to the processor after

it is installed in the 370-pin ZIF socket.

The boxed processor’s fan heatsink requires a +12V power supply. A fan power cable is

attached to the fan and connects to processor fan headers on the STL2 server board.

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The boxed processor fan heatsink will keep the processor core at the recommended junction

temperature, as long as airflow through the fan heatsink is unimpeded. It is recommended that

the air temperature entering the fan inlet be below 45 C (measured at 0.3 inches above the

fan hub).

2.2 ServerWorks ServerSet III LE Chipset

The ServerWorks ServerSet III LE chipset provides an integrated I/O bridge and memory

controller and a flexible I/O subsystem core (PCI), targeted for multiprocessor systems and

standard high-volume servers that are based on the Intel Pentium III processor. The

ServerWorks ServerSet III LE chipset consists of two components:

NB6635 North Bridge 3.0LE

The NB6635 North Bridge 3.0LE is responsible for accepting access requests from the

host (processor) bus and for directing those accesses to memory or to one of the PCI

buses. The NB6635 North Bridge 3.0LE monitors the host bus, examining addresses

for each request. Accesses may be directed to a memory request queue for

subsequent forwarding to the memory subsystem, or to an outbound request queue for

subsequent forwarding to one of the PCI buses. The NB6635 North Bridge 3.0LE is

reponsible for controlling data transfers to and from the memory. The NB6635 North

Bridge 3.0LE provides the interface for both the 64-bit/66 MHz, Revision 2.2-compliant

PCI bus and the 32-bit/33 MHz, Revision 2.2-compliant PCI bus. The NB6635 North

Bridge 3.0LE is both a master and target on both PCI buses.

IB6566 South Bridge

The IB6566 South Bridge controller has several components. It can be both a master

and a target on the 32-bit/33 MHz PCI bus. The IB6566 South Bridge also includes a

USB controller and an IDE controller. The IB6566 South Bridge is responsible for many

of the power management functions, with ACPI control registers built in. The IB6566

South Bridge provides a number of GPIO pins.

2.3 Memory

The STL2 server board contains four 168-pin DIMM sockets. Memory is partitioned as four

banks of registered SDRAM DIMMs, each of which provides 72 bits of noninterleaved memory

(64-bit main memory plus ECC).

The STL2 server board supports up to four 3.3V, registered ECC SDRAM DIMMs that are

compliant with the JEDEC PC133 specification. A wide range of DIMM sizes are supported,

including 64 MB, 128 MB, 256 MB, 512 MB, and 1GB DIMMs. The minimum supported

memory configuration is 64 MB using one DIMM. The maximum configurable memory size is 4

GB using four DIMMs.

Note: Neither PC100 DIMMs nor non-ECC DIMMs can be used.

DIMMs may be installed in one, two, three, or four DIMM slots and must be populated starting

with the lowest numbered slot and filling the slots in consecutive order. Empty memory slots

between DIMMs are not supported. Although the STL2 server board architecture allows the

user to mix various sizes of DIMMS, Intel recommends that module and DRAM vendors not be

mixed in the same server system.

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System memory begins at address 0 and is continuous (flat addressing) up to the maximum

amount of DRAM installed (exception: system memory is noncontiguous in the ranges defined

as memory holes using configuration registers). The server board supports both base

(conventional) and extended memory.

2.4 PCI I/O Subsystem

The expansion capabilities of the STL2 server board meet the needs of file and application

servers for high performance I/O by providing two PCI bus segments in the form of one 64-bit /

66 MHz bus segment and one 32-bit / 33 MHz bus segment. Each of the PCI buses comply

with Revision 2.2 of the PCI Local Bus Specification.

2.4.1

64-bit / 66 MHz PCI Subsystem

The 64-bit, 66 MHz, 3.3V keyed PCI segment includes the following embedded devices and

connectors:

Two 64-bit, 66 MHz, 3.3V keyed PCI expansion slots that can support 66 MHz, 64/32-

bit cards or 33 MHz, 64/32-bit cards.

Integrated Adaptec AIC-7899 PCI dual-port SCSI controller providing separate Ultra160

and Ultra Wide SCSI channels

64-bit PCI features include:

Bus speed up to 66 MHz

3.3 V signaling environment

Burst transfers up to a peak of 528 Megabytes per second (MBps)

8-, 16-, 32-, or 64-bit data transfers

Plug-and-Play ready

Parity enabled

Note: If a 33 MHz PCI board is installed into one of the 64-bit PCI slots, the bus speed for the

66 MHz PCI slots and SCSI controller is decreased to 33 MHz.

2.4.1.1

Ultra160 / Ultra WideSCSI Controller

The STL2 server board includes an Adaptec AIC7899. This is an embedded dual-function, PCI

SCSI host adapter on the 64-bit/66 MHz PCI bus. The AIC7899 contains two independent

SCSI controllers that share a single PCI bus master interface as a multi-function device.

Internally, each controller is identical, capable of operations using either 16-bit SE or LVD

SCSI providing 40 MBps (Ultra-wide SE) or 160 MBps (Ultra160). The STL2 server board

provides the ability to disable the embedded Ultra160 SCSI Controller in the BIOS Setup

option. When disabled, it will not be visible to the operating system.

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Table 2-2. SCSI Transfer Speeds

SCSI Port Asynchronous Fast-5

Fast-10

yes

Fast-20

yes

Fast-40 Fast-80/Ultra160

Yes

yes

LVD

yes

In the STL2 server board implementation, channel A provides a 68-pin, 16-bit LVD Ultra160

SCSI interface. Channel B provides a 68-pin, 16-bit Single Ended Ultra Wide SCSI interface.

Each controller has its own set of PCI configuration registers and SCSI I/O registers. As a PCI

2.1/2.2 bus master, the AIC-7899 supports burst data transfers on PCI up to the maximum rate

of 133 MBps using on-chip buffers.

Refer to the AIC-7899 PCI-Dual Channel SCSI Multi-Function Controller Data Manual for more

information on the internal operation of this device and for descriptions of SCSI I/O registers.

2.4.1.1.1

AIC-7899 Supported PCI Commands

The AIC-7899 supports PCI commands as shown in the following table:

Table 2-3. Embedded SCSI Supported PCI Commands

AIC-7899 Support

C/BE [3::0] _L

0000

Command

Interrupt Acknowledge

Special Cycle

Target

Master

No¹

Yes²

No¹

0001

0010

I/O Read

0011

I/O Write

0100

Reserved

0101

Reserved

Yes^{2, 3}

Yes²

No¹

Yes⁴

0110

Memory Read

0111

Memory Write

1000

Reserved

No¹

1001

Reserved

1010

Configuration Read

Configuration Write

Memory Read Multiple

Dual Address Cycle

Memory Read Line

Memory Write and Invalidate

Yes

1011

Yes

Yes⁴

Yes⁵

Yes⁶

Yes⁵

Yes⁷

1100

1101

Yes

Yes⁴

Yes

1110

1111

Notes:

1. Ignored after checking address parity.

2. Support for 8-bit transfers only for all registers in its device register space.

3. Support for 32-bit transfers only for the external ROM/ EEPROM.

4. Support for transfers from system memory.

5. Defaults to Memory Read.

6. Will respond to DAC if PCI Address matches the MBAR[63:12].

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7. Defaults to Memory Write.

The extensions to memory commands (memory read multiple, memory read line, and memory

write and invalidate) work with the cache line size register to give the cache controller advance

knowledge of the minimum amount of data to expect. The decision to use either the memory

read line or memory read multiple commands is determined by a bit in the configuration space

command register for this device.

2.4.1.1.2

SCSI Bus

The SCSI data bus is 8 or 16 bits wide with odd parity generated per byte. SCSI control signals

are the same for either bus width. To accommodate 8-bit devices on the 16-bit Wide SCSI

connector, the AIC-7899 assigns the highest arbitration priority to the low byte of the 16-bit

word. This way, 16-bit targets can be mixed with 8-bit if the 8-bit devices are placed on the low

data byte. For 8-bit mode, the unused high data byte is self-terminated and does not need to

be connected. During chip power-down, all inputs are disabled to reduce power consumption.

2.4.2

32-bit/33 MHz PCI Subsystem

The 32-bit, 33 MHz, 5V keyed PCI includes the following embedded devices and connectors:

Four 32-bit, 33 MHz, 5V keyed PCI expansion slots

Integrated Intel® EtherExpress™ PRO100+ 10/100 megabit PCI Ethernet controller

(Intel® 82559)

Integrated ATI Rage* IIC video controller with 4 MB of on-board SGRAM

IB6566 South Bridge I/O APIC, PCI-to-ISA bridge, IDE controller, USB controller, and

power management.

32-bit PCI features include:

Bus speed up to 33 MHz

5 V signaling environment

Burst transfers up to a peak of 132 MBps

8-, 16-, or 32-bit data transfers

Plug-and-Play ready

Parity enabled

2.4.2.1

Network Interface Controller (NIC)

The STL2 server board includes a 10Base-T / 100Base-TX network controller that is based on

the Intel^®82559 Fast Ethernet PCI Bus Controller. This device is similar in architecture to its

predecessor (Intel^®82558). No external devices are required to implement an embedded

network subsystem, other than TX/RX magnetics, two status LEDs, and a connector.

Status LEDs are not included on the external NIC connector, but there is a jumper head (6A)

where status LEDs may be connected. The STL2 server board provides the ability to disable

the embedded NIC in the BIOS Setup option. When disabled it is not visible to the operating

system.

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The 82559 is a highly integrated PCI LAN controller for 10 or 100 Mbps Fast Ethernet

networks. As a PCI bus master, the 82559 can burst data at up to 132 MBps. This high-

performance bus master interface can eliminate the intermediate copy step in RX/TX frame

copies, resulting in faster frame processing.

The network OS communicates with the 82559 using a memory-mapped I/O interface, PCI

interrupt connected directly to the ICH, and two large receive and transmit FIFOs. The receive

and transmit FIFOs prevent data overruns or underruns while waiting for access to the PCI

bus, and also enable back-to-back frame transmission within the minimum 960ns inter-frame

spacing. The figure below shows the PCI signals supported by the 82559:

AD[31::0]

C/BE[3::0]_L

PAR

FRAME_L

TRDY_L

IRDY_L

STOP_L

DEVSEL_L

i82559 NIC

IDSEL

REQ_L

GNT_L

PCI_CLK

RST_L

PERR_L

SERR_L

PCI_INT_L

Figure 2-1. Embedded NIC PCI Signals

2.4.2.1.1

Supported Network Features

The 82559 contains an IEEE MII compliant interface to the components necessary to

implement an IEEE 802.3 100Base TX network connection. The STL2 supports the following

features of the 82559 controller:

Glueless 32-bit PCI Bus Master Interface (Direct Drive of Bus), compatible with PCI Bus

Specification, revision 2.1 / 2.2.

Chained memory structure, with improved dynamic transmit chaining for enhanced

performance.

Programmable transmit threshold for improved bus utilization.

Early receive interrupt for concurrent processing of receive data.

On-chip counters for network management.

Autodetect and autoswitching for 10 or 100 Mbps network speeds.

Support for both 10 Mbps and 100 Mbps networks, full or half duplex-capable, with

back-to-back transmit at 100 Mbps.

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Integrated physical interface to TX magnetics.

The magnetics component terminates the 100Base-TX connector interface. A flash

device stores the network ID.

Support for Wake-on-LAN (WOL).

2.4.2.2

Video Controller

The STL2 server board includes an ATI Rage IIC video controller, 4 MB video SGRAM, and

support circuitry for an embedded SVGA video subsystem. The Rage IIC, 64-bit VGA Graphics

Accelerator contains a SVGA video controller, clock generator, BitBLT engine, and RAMDAC.

Two 512K x 32 SGRAM chips provide 4 MB of 10ns video memory.

The SVGA subsystem supports a variety of modes: up to 1280 X 1024 resolution, and up to

16.7 Million colors. It also supports analog VGA monitors, single- and multi-frequency,

interlaced and non-interlaced, up to 100 Hz vertical refresh frequency. The STL2 server board

provides a standard 15-pin VGA connector, and external video blanking logic for server

management console redirection support.

2.4.2.2.1

Video Controller PCI Signals

The Rage IIC supports a minimal set of 32-bit PCI signals because it never acts as a PCI

master. As a PCI slave, the device requires no arbitration or interrupts.

AD[31::0]

C/BE[3::0]_L

PAR

FRAME_L

TRDY_L

IRDY_L

STOP_L

DEVSEL_L

Rage IIC

IDSEL

PCI_CLK

RST_L

PERR_L

SERR_L

PCI_INT_L

Figure 2-2. Video Controller PCI Signals

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2.4.2.2.2

Video Controller PCI Commands

The Rage IIC supports the following PCI commands:

Table 2-4. Video Controller Supported PCI Commands

Rage II C Support

Target Master

C/BE[3::0]_L

0000

Command Type

Interrupt Acknowledge

Special Cycle

0001

0010

I/O Read

Yes

0011

I/O Write

0100

Reserved

0101

Reserved

0110

Memory Read

Yes

0111

Memory Write

1000

Reserved

1001

Reserved

1010

Configuration Read

Configuration Write

Memory Read Multiple

Dual Address Cycle

Memory Read Line

Memory Write and Invalidate

Yes

1011

1100

1101

1110

1111

2.4.2.2.3

Video Modes

The Rage IIC supports all standard IBM VGA modes. The following tables show the standard

resolutions that this implementation supports, including the number of colors and the refresh

rate.

Table 2-5. Standard VGA Modes

Resolution Refresh Rate (Hz) Colors

640x480

800x600

1024x768

1152x864

1280x1024

1600x1200

640x480

800x600

1024x768

1152x864

640x480

800x600

200

150

120

100

256

200

150

120

200

160

65K

16.7M

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2.4.2.3

IB6566 South Bridge

The IB6566 South Bridge is a PCI device that provides multiple PCI functions in a single

package: PCI-to-ISA bridge, PCI IDE interface, PCI USB controller, and power management

controller. Each function within the IB6566 South Bridge has its own set of configuration

registers. Once configured, each appears to the system as a distinct hardware controller

sharing the same PCI bus interface.

On the STL2 baseboard, the primary role of the IB6566 South Bridge is to provide the gateway

to all PC-compatible I/O devices and features. The STL2 server board uses the following

IB6566 South Bridge features:

PCI interface

IDE interface

USB interface

PC-compatible timer/counters and DMA controllers

Baseboard Plug-and-Play support

General purpose I/O

Power management

APIC and 82C59 interrupt controller

Host interface for AT compatible signaling

Internal only ISA bus (no ISA expansion connectors) bridge for communication with

Super I/O, BIOS flash and BMC

The following sections describe each supported feature as used on the STL2 server board.

2.4.2.3.1

PCI Interface

The IB6566 South Bridge fully implements a 32-bit PCI master/slave interface, in accordance

with Revision 2.2 of the PCI Local Bus Specification. On the STL2 server board, the PCI

interface operates at 33 MHz, using the 5V-signaling environment.

2.4.2.3.2

PCI Bus Master IDE Interface

The IB6566 South Bridge acts as a PCI-based enhanced IDE 32-bit interface controller for

intelligent disk drives that have disk controller electronics on-board. The server board includes

a single IDE connector, featuring 40 pins (2 x 20) that support a master and a slave device.

The IDE controller provides support for an internally mounted CD-ROM.

The IDE controller has the following features:

PIO and DMA transfer modes

Mode 4 timings

Transfer rates up to 33 MBps

Buffering for PCI/IDE burst transfers

Master/slave IDE mode

Support for up to two devices

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2.4.2.3.3

USB Interface

The IB6566 South Bridge contains a USB controller and USB hub. The USB controller moves

data between main memory and the two USB connectors provided.

The STL2 server board provides a dual external USB connector interface. Both ports function

identically and with the same bandwidth. The external connector is defined by Revision 1.0 of

the USB Specification.

2.4.2.4

Compatibility Interrupt Control

The IB6566 South Bridge provides the functionality of two 82C59 Programmable Interrupt

Controller (PIC) devices, for ISA-compatible interrupt handling.

2.4.2.5

APIC

The IB6566 South Bridge integrates a 16-entry I/O APIC that is used to distribute 16 PCI

interrupts. It also includes an additional 16-entry I/O APIC for distribution of legacy ISA

interrupts.

2.4.2.6

Power Management

One of the embedded functions of IB6566 South Bridge is a power management controller.

The STL2 server board uses this to implement ACPI-compliant power management features.

STL2 supports sleep states s0, s1, s4, and s5.

2.5 Chipset Support Components

2.5.1

Legacy I/O (Super I/O) National* PC97317VUL

The National* PC97317VUL Super I/O Plug-and-Play Compatible with ACPI-Compliant

Controller/Extender is used on the STL2 server board. This device provides the system with:

Real-time Clock (RTC)

Two serial ports

One parallel port

Floppy disk controller (FDC)

PS/2-compatible keyboard and mouse controller

General purpose I/O pins

Plug-and-Play functions

A power management controller

The STL2 server board provides the connector interface for the floppy, dual serial ports,

parallel port, PS/2 mouse and the PS/2 keyboard. Upon reset, the SIO reads the values on

strapping pins to determine the boot-up address configuration.

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2.5.1.1

Serial Ports

Two 9-pin connectors in D-Sub housing are provided for serial port A and serial port B. Both

ports are compatible with 16550A and 16450 modes, and both are re-locatable. Each serial

port can be set to one of four different COM-x ports, and each can be enabled separately.

When enabled, each port can be programmed to generate edge- or level-sensitive interrupts.

When disabled, serial port interrupts are available to add-in cards.

2.5.1.2

Parallel Port

The STL2 baseboard provides a 25-pin parallel port connector. The SIO provides an IEEE

1284-compliant 25-pin bi-directional parallel port. BIOS programming of the SIO registers

enables the parallel port and determines the port address and interrupt. When disabled, the

interrupt is available to add-in cards.

2.5.1.3

Floppy Port

The FDC in the SIO is functionally compatible with floppy disk controllers CMOS 765B and

82077AA. The baseboard provides the 24- MHz clock, termination resistors, and chip selects.

All other FDC functions are integrated into the SIO, including analog data separator and 16-

byte FIFO.

2.5.1.4

Keyboard and Mouse Connectors

The keyboard controller is functionally compatible with the 8042A. The keyboard and mouse

connectors are PS/2-compatible.

2.5.1.5

Real-time Clock

The PC97317VUL contains an MC146818-compatible real-time clock with external battery

backup. The device also contains 242 bytes of general purpose battery-backed CMOS RAM.

The real-time clock provides system clock and calendar information stored in non-volatile

memory.

2.5.1.6

Plug-and-Play Functions / ISA Data Transfers

The PC97317VUL contains all signals for ISA compatible interrupts and DMA channels. It also

provides ISA control, data, and address signals to transfer data to/from the BMC and the BIOS

flash device. This ISA subsystem transfers all SIO peripheral control data to the IB6566 South

Bridge as well.

2.5.1.7

Power Management Controller

The PC97317VUL component contains functionality that allows various events to allow the

power-on and power-off of the system. This can be from PCI Power Management Events, the

BMC, or the front panel. This circuitry is powered from stand-by voltage, which is present

anytime the system is plugged into the AC outlet.

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2.5.2

BIOS Flash

The STL2 baseboard incorporates an Intel^®5V FlashFile™ 28F008SA Flash Memory

component. The 28F008SA is a high-performance 8 Mbit memory that is organized as 1 MB of

8 bits each. There are 16 64-KB blocks.

The 8-bit flash memory provides 1024K x 8 of BIOS and nonvolatile storage space. The flash

device is directly addressed as 8-bit ISA memory. For more information, see the 5 Volt

FlashFile™ Memory (28F008SA x8) Datasheet.

2.5.3

External Device Connectors

The external I/O connectors provide support for a PS/2 compatible mouse and keyboard, an

SVGA monitor, two serial port connectors, a parallel port connector, a LAN port, and two USB

connections.

2.6 Interrupt Routing

The STL2 server board interrupt architecture implements two I/O APICs and two PICs through

the use of the integrated components in the IB6566 South Bridge component. The STL2

server board interrupt architecture allows first and second PCI interrupts to be mapped to

compatible interrupt through the PCI Interrupt Address Index Register (I/O Address 0C00h) in

the IB6566 South Bridge.

The STL2 server board supports three interrupt modes:

PIC Mode

Virtual Wire Mode

Symmetric Mode

The IB6566 South Bridge uses integrated logic to map 16 PCI interrupts to EISA/ISA. In

default or Extended APIC configurations, each PCI interrupt can be independently routed to

one of the 11 EISA interrupts. The interrupt mapping logic for PCI interrupts is disabled when

the make bit in the corresponding I/O APIC redirection table entry is disabled (clear). This

interrupt routing mechanism allows a clean transition from PIC mode to an APIC during

operating system boot.

2.6.1

Default I/O APIC

The IB6566 South Bridge integrates a 16-entry I/O APIC which is used to distribute 16 PCI

interrupts.

2.6.2

Extended I/O APIC

An additional 16-entry I/O APIC is integrated in the IB6566 South Bridge to distribute EISA/ISA

interrupts. This additional I/O APIC is enabled only when the IB6566 South Bridge is

configured to the Extended APIC configuration.

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IRQ0/INTR

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

PIC

IRQ7

IB6566

South

Bridge

IRQ8

IRQ9/SCI

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

PCIIRQ0#

PCIIRQ1#

PCIIRQ2#

PCIIRQ3#

PCIIRQ4#

PCIIRQ5#

PCIIRQ6#

PCIIRQ7#

PCIIRQ8#

PCIIRQ9#

PCIIRQ10#

PCIIRQ11#

PCIIRQ12#

PCIIRQ13#

PCIIRQ14#

PCIIRQ15#

PCI

Interrupt

Router

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ9

IRQ10

IRQ11

IRQ12

IRQ14

IRQ15

Figure 2-3. STL2 Baseboard Interrupt Routing Diagram (PIC mode)

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Timer

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

Keyboard

Cascade

Serial Port2/ISA

Serial Port1/ISA

ISA

Floppy/ISA

Parallel/ISA

RTC

SCI/ISA

ISA

Mouse/ISA

Coprocessor Err

P_IDE/ISA

Not Used

PIRQ0(16)

PIRQ1(17)

PIRQ2(18)

PIRQ3(19)

PIRQ4(20)

PIRQ5(21)

PIRQ6(22)

PIRQ7(23)

PIRQ8(24)

PIRQ9(25)

PIRQ10(26)

PIRQ11(27)

PIRQ12(28)

PIRQ13(29)

PIRQ14(30)

PIRQ15(31)

SCSI PORT A

SCSI PORT B

LAN

VGA

Slot02 INTA

Slot03 INTA

Slot04 INTA

Slot05 INTA

Slot06 INTA

Slot01 INTA

SLOT 02

05 06

Figure 2-4. STL2 Baseboard Interrupt Routing Diagram (Symmetric mode)

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2.6.3

PCI Ids

The STL2 server board PCI Ids are defined as follows:

Table 2-6. STL2 PCI IDs

Device

Bus Number

[23:16]

Device Number

[15:11]

Slot ID Signal

NB6635 North Bridge 3.0LE

ATI* Rage IIC

00h

00000b

00010b

00011b

00100b

00110b

00111b

01000b

01001b

01111b

01010b

01011b

P32_AD18

P32_AD19

P32_AD20

P32_AD22

P32_AD23

P32_AD24

P32_AD25

P32_AD31

P32_AD26

P32_AD27

Intel 82559

Adaptec* AIC-7899

Slot 1 (32 bit)

Slot 2 (32 bit)

IB6566 South Bridge

Slot 2 (32 bit)

Note:

Do not change the BUSNUM register (Offset 44h) in the NB6635 North Bridge 3.0LE from the default value.

2.6.4

Relationship between PCI IRQ and PCI Device

The relationship between PCI IRQ and PCI devices are defined as follows on the STL2 server

board:

PCI IRQ

PCI Device

PCI IRQ 0

Adaptec AIC-7899 SCSI Channel A

Adaptec AIC-7899 SCSI Channel B

Intel 82559

PCI IRQ 1

PCI IRQ 2

PCI IRQ 3

PCI IRQ 4

PCI IRQ 5

PCI IRQ 6

PCI IRQ 7

PCI IRQ 8

PCI IRQ 9

PCI IRQ 10

PCI IRQ 11

ATI Rage IIC

PCI Slot 2 (INTA)

PCI Slot 3 (INTA)

Not Used

PCI Slot 4 (INTA)

PCI Slot 5 (INTA)

PCI Slot 6 (INTA)

PCI Slot 1 (INTA)

PCI Slot 1 (INTB), PCI Slot 2 (INTB), PCI Slot 3 (INTC), PCI Slot 4 (INTB), PCI Slot 5 (INTC), PCI

Slot 6 (INTD)

PCI IRQ 12

PCI IRQ 13

PCI Slot 1 (INTC), PCI Slot 2 (INTC), PCI Slot 3 (INTD), PCI Slot 4 (INTC), PCI Slot 5 (INTD), PCI

Slot 6 (INTB)

PCI Slot 1 (INTD), PCI Slot 2 (INTD), PCI Slot 3 (INTB), PCI Slot 4 (INTC), PCI Slot 5 (INTD), PCI

Slot 6 (INTB)

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Server Management

3. Server Management

This section describes the features of the server management subsystem for the STL2 server

board. The server management subsystem consists of the BIOS, hardware, and firmware

features built into the server board. These features provide hardware monitoring, control, and

logging to improve the reliability, availability, and serviceability of the server system.

The server management subsystem conforms to the IPMI (Intelligent Platform Management

Interface) v1.0 specification. IPMI defines a standardized, abstracted, message-based

interface between system management software and the platform management hardware.

The following comprise the major elements of the server management architecture for the

STL2 server board.

Baseboard Management Controller (BMC)

Sensors

Sensor Data Record (SDR) Repository & System Event Log (SEL)

Field Replaceable Unit (FRU) Information

3.1 Baseboard Management Controller

The STL2 server management functionality is concentrated in the Baseboard Management

Controller (BMC). The BMC is comprised of a Dallas* Semiconductor DS80CH11 (or

equivalent) microcontroller and associated circuitry located on the STL2 server board. The

BMC and associated circuits are powered from a 5V DC standby voltage, which remains active

when system power is switched off, but the AC power source is still on and connected.

A major function of the BMC is to autonomously monitor system management events and log

the occurrence in the nonvolatile System Event Log (SEL). The events being monitored

include over/under temperature and over/under voltage conditions, fan failure, or chassis

intrusion. To enable accurate monitoring, the BMC maintains the nonvolatile Sensor Data

Record (SDR) from which sensor information can be retrieved. The BMC provides an ISA host

interface to SDR sensor information, so that software running on the server can poll and

retrieve the server’s current status. The BMC also provides the interface to the monitored

information and SEL that System Management Software, such as Intel® Server Control, uses

to poll and retrieve the platform status.

The BMC performs the following functions:

Monitors server boad temperature and voltage

Monitors processor presence and controls Fault Resilient Boot (FRB)

Detects and indicates baseboard fan failure

Manages the SEL interface

Manages the SDR Repository interface

Monitors the SDR/SEL timestamp clock

Monitors the system management watchdog timer

Monitors the periodic SMI timer

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Monitors the event receiver

Controls secure mode, inlucluding video blanding, diskett write-protect monitoring, and

fornt panel lock/unlock initiation

Controls Wake-on-Lan via Magic Packet* support

3.2 Hardware Sensors

The following table lists the hardware sensors present on the STL2 server board.

Sensor Number

01h

Sensor Type

Monitoring Device

ADM1024 Temperature

Temperature

02h

Processor 1 internal

Processor 2 internal

3.3V

03h

20h

Voltage

21h

22h

12V

23h

3.3V Standby

24h

Processor 1

25h

Processor 2

29h

1.5V

2Ah

2Ch

2Dh

2Eh

2Fh

30h

2.5V

SCSI-A 2.85V

SCSI-B 2.85V

SCSI-A Vref1

SCSI-A Vref2

SCSI-A Vref3

31h

SCSI-B Vref1

32h

SCSI-B Vref2

33h

SCSI-B Vref3

34h

Voltage (Discrete)

Fan

Performance Lags

Baseboard Fan 1

Baseboard Fan 2

Baseboard Fan 3

Processor 1 State

Processor 2 State

Soft Power Control Failure (bit 5) Interlock Power

Power supply Failure detected (bit 1)

40h

41h

42h

60h

Processor

61h

70h

Power Distribution Board

71h

Power Distribution Board Supply 1

Power Distribution Board Supply 2

Power Redundancy Lost

72h

7Fh

Redundancy Lost (bit 1)

Redundancy Regained (bit 0)

90h

Chassis Intrusion ID

Drive Bay Intrusion (bit 1)

LAN Leash Lost (bit 4)

91h

92h

Security Violation

Memory Error

Secure Mode Violation Attempt (bit 0)

ECC multiple bit error (bit 1)

ECC single bit error (bit 0)

93h

POST Memory Resize

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Sensor Number

Server Management

Sensor Type

Monitoring Device

94h

95h

BIOS POST (Error) Code

Log Disable

Log Area Reset / Cleared (bit 2)

ECC single bit Error Disable (bit 0)

96h

97h

System Event

OEM System Event (Hard Reset) (bit 1) System

Critical Interrupt

PCI SERR (bit 5)

PCI PERR (bit 4)

Front Panel NMI (Dump SW) (bit 0)

98h

Button

Reset Button (bit 2)

Sleep Button (bit 1)

Power Button (bit 0)

99h

9Ah

No Processor or Termination Board

Boot Init

User requested PXE boot (bit 3)

Initiated by power up (bit 0)

9Bh

Boot Error

PXE Server not found (bit 2)

No bootable media (bit 0)

9Ch

9Dh

9Eh

OS Boot

OS Stop

ACPI State

Sleeping in S1 state (bit 8)

G3/Mechanical Off (bit 7)

S5 / G2 Soft Off (bit 5)

S4 (bit 4)

A0h

C0h

C1h

F3h

BMC Watchdog

BMC WDT Timeout

Chassis Intrusion ID (Disable)

Chassis Intrusion ID

SMI State

Processor Area Intrusion (bit 4)

Drive Bay Intrusion (bit 1)

SMI Stall State

The following table provides a list of System Event Log (SEL) events supported by the STL2

server board.

Sensor Type

Sensor Type Sensor-Specific Event

Remarks

Code

Offset

Reserved

Temperature

Voltage

00h

–

Reserved

01h

–

Temperature

Voltage

An error occurred at thermal sensors

An error occurred at voltage sensors

02h

–

01h

Performance Lags

In the single-end event mode, even if

SCSI is available for a different

mode event.

Fan

04h

05h

–

Fan

An error occurred at fan sensors.

Physical Security

01h

Drive Bay Intrusion

Front cover has been opened or

closed

03h

04h

Processor area intrusion

LAN Connection Lost

Side (Chassis) cover has been

opened or closed.

(System has been

LAN cable has

unplugged from LAN) been plugged

in or

unplugged.

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Sensor Type

Sensor Type Sensor-Specific Event

Remarks

Code

Offset

Platform Security

Violation Attempt

06h

00h

Secured Mode Violation

Attempt

Power/sleep switch has been

activated while in Secure Mode

03h

Pre-boot Password Violation

(network boot Password)

Bad Password at PXE Boot

Processor

07h

00h

01h

02h

04h

IERR

CPU IERR has occurred

Thermal Trip

FRB1/BIST Failure

CPU Thermal Trip has occurred

BIST Error has occurred

FRB3/Processor

FRB3 Timeout has been detected

Startup/Initialization failure

(CPU didn’t start)

08h

00h

01h

Processor disabled

Correctable ECC

A processor has been Disabled

ECC 1-bit error occurred

ECC 2-bit error occurred

Memory

0Ch

Uncorrectable ECC

POST Memory Resize

POST Memory Resize 0Eh

Displays the total amount of memory

after memory failure

POST Error

0Fh

10h

POST Error

POST Error occurred

Event Logging

Disabled

00h

01h

Correctable Memory Error

Logging Disabled

Displays ECC single bit error

monitoring disabled

Event ‘Type’ Logging Disabled Monitoring of a certain event type

has been disabled

02h

03h

Log Area Reset/Cleared

Displays the SEL area cleared.

All Event Logging Disabled

Monitor for the entire BMC has been

disabled.

System Event

12h

13h

00h

01h

System Reconfigured

Setup change has occurred

OEM System Boot Event (Hard Cold reset has been issued

Reset)

Critical Interrupt

00h

02h

04h

05h

00h

01h

02h

Front Panel NMI Dump Switch Dump switch has been activated

I/O channel check NMI

PCI SERR

ISA I/O Check has occurred.

PCI SERR occurred

PCI PERR

PCI PERR occurred

Button

14h

15h

Power Button

Power switch has been activated

Sleep switch has been activated

Reset switch has been activated

Sleep Button

Reset Button

Module / Board

CPU / Terminator Missing

CPU / Terminator is not mounted

correctly

System Boot Initiated 1Dh

03h

04h

User requested PXE boot

PXE (Network) Booted

Automatic boot to diagnostic

When the maintenance Utility

Booted

Boot Error

1Eh

00h

02h

00h

No bootable media

PXE Server not found

C: boot completed

Boot Media does not exist.

PXE Server is not found

ESM Pro installed OS has been

booted

02h

03h

PXE boot completed

PXE boot for the express server is

finished (not supported)

Diagnostic boot completed

Maintenance Utility has been booted

(not supported)

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STL2 Server Board TPS

Server Management

Sensor Type

Sensor Type Sensor-Specific Event

Remarks

Code

Offset

04h

CD-ROM boot completed

The server has been booted (not

supported)

OS Critical Stop

20h

00h

Stop during OS load /

Initialization

OS stalled during startup

01h

00h

Run-time Stop

OS stalled during startup

DC is ON

System ACPI Power 22h

State

S0 / G0 Working

01h

04h

S1 “sleeping with system H/W S1 Sleep State

& processor context

Maintained”

S4 “non-volatile sleep /

suspend-to disk”

S4 Sleep State

05h

07h

08h

S5 / G2 “soft-off”

DC is OFF

AC is OFF

G3 / Mechanical Off

Sleeping (cannot differentiate SUSC# OS has been asserted

between S1-S3)

without the instruction to sleep

Watchdog 2

23h

01h

02h

Hard Reset

POST/Boot monitor timed out

Power Down

OS WDT shut down after the

monitor timeout

08h

Timer Interrupt

SMI Timeout

OS WDT monitor timed out

SMI Timeout

EMP

F3h

F5h

SMI# has been asserted for more

than ten seconds

00h

Communication Error

Communication is unavailable even

though the BMC is in communication

status

Sensor Failure

OEM Reserved

F6h

I²C Bus Device Address Not

Acknowledged

I²C Bus Device Error Detected Other access errors

I²C Bus Timeout

SMBus Timeout error

SMBus Device does not answer.

01h

02h

F7h - FFh

3.3 ACPI

The Advance Configuration and Power Interface (ACPI)-aware operating system can place the

system into a state where the hard drives spin down, the sytem fans stop, and all processing is

halted. In this state the power supply is still on and the processors still dissipate some power,

such that the power supply fan and processor fans are still running.

Note: ACPI requires an operating system that supports this feature.

The ACPI sleep states discussed below are defined as:

s0: Normal running state

s1: Processor sleep state. No content is lost in this state and the processor caches

maintain coherency.

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Server Management

STL2 Server Board TPS

s4: Hibernate or Save to Disk. The memory and machine state are saved to disk.

Pressing the power button or another wakeup event restores the system state from the

disk and resumes normal operation. This assumes that no hardware changes were

made to the system while it was off.

s5: Soft off. Only the RTC section of the chip set and the BMC are running in this state.

The STL2 server board supports sleep states s0, s1, s4, and s5. When the server board is

operating in ACPI mode, the OS retains control of the system and the OS policy determines

the entry methods and wake up sources for each sleep state – sleep entry and wake up event

capabilites are provided by the hardware but are enabled by the OS.

With future versions of Microsoft* Windows* 9X that support ACPI, the system BIOS supports

only sleep states s0, s1, and s5. With future versions of Microsoft Windows NT* that support

ACPI, the system BIOS will support sleep states s0, s1, s4, and s5.

3.4 AC Link Mode

The AC link mode allows the system to monitor its AC input power so that if AC input power is

lost and then restored, the system returns to one of the following preselected settings:

Power On

Last State (Factory Default Setting)

Stay Off

The AC link mode settings can be changed by running the BIOS Setup Utility.

3.5 Wake On LAN Function

The remote power-on function turns on the system power by way of a network or modem. If

the system power is set to Off, it can be turned on remotely by sending a specific packet from

the main computer to the remote system.

Note: The standard default value of the remote power-on function is “Disabled”. The Wake-on-

LAN / Ring function can changed by setting the option to “Enabled” in the BIOS Setup Utility.

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STL2 Server Board TPS

Basic Input Output System (BIOS)

4. Basic Input Output System (BIOS)

This section describes BIOS embedded software for the STL2 board set. The BIOS contains

standard PC-compatible basic input/output (I/O) services, standard Intel^®server features, plus

the STL2 system-specific hardware configuration routines and register default settings,

embedded in Flash read-only memory (ROM). This section also describes BIOS support

utilities (not ROM-resident) that are required for system configuration and flash ROM update.

The BIOS is implemented as firmware that resides in the flash ROM. Support for applicable

baseboard peripheral devices (SCSI, NIC, and video adapters), which is also loaded into the

baseboard flash ROM, is not specified in this document. Hooks are provided to support adding

BIOS code for these adapters; the binaries must be obtained from the peripheral device

manufacturers and loaded into the appropriate locations.

4.1 BIOS Overview

The term BIOS, as used in the context of this section, refers to the system BIOS, the BIOS

Setup and option ROMs for on-board peripheral devices that are contained in the system flash.

System BIOS controls basic system functionality using stored configuration values. The terms

flash ROM, system flash, and BIOS flash may be used interchangeably in this section.

The term BIOS Setup refers to the flash ROM-resident setup utility that provides the user with

control of configuration values stored in battery-backed CMOS configuration RAM. The System

Setup Utility (SSU), which also provides this functionality, is discussed in a separate document.

BIOS Setup is closely tied with the system BIOS and is considered a part of BIOS.

Phoenix Phlash* (PHLASH.EXE) is used to load predefined areas of flash ROM with Setup,

BIOS, and other code/data.

The following is the break-down of the STL2 product ID string:

4 byte board ID, ‘STL2’

1 byte board revision, starting from ‘0’

3 byte OEM ID, ‘86B’ for standard BIOS

4 byte build number

1-3 byte describing build type (D for development, A for Alpha, B for Beta, Pxx for

production version xx)

6 byte build date in yymmdd format

4 bytes time in hhmm format

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Basic Input Output System (BIOS)

STL2 Server Board TPS

4.1.1

System BIOS

The system BIOS is the core of the flash ROM-resident portion of the BIOS. The system BIOS

provides standard PC-BIOS services and support for some new industry standards, such as

the Advanced Configuration and Power Interface Specification, Revision 1.0 and Wired For

Management Baseline Specification, Revision 2.0. In addition, the system BIOS supports

certain features that are common across all the Intel servers. These include:

Security

MPS support

Server management and error handling

CMOS configuration RAM management

OEM customization

PCI and Plug and Play (PnP) BIOS interface

Console redirection

Resource allocation support

BIOS setup is embedded in flash ROM and provides the means to configure on-board

hardware devices and add-in cards. For more information, refer to Section 4.2, Setup Utility.

4.1.2

Flash Update Utility

The system BIOS and the setup utility are resident in partitioned flash ROM. The device is in-

circuit reprogrammable. On the STL2 platform, 1 MB of flash ROM is provided. The STL2 BIOS

does not support a SecureBIOS feature like some server products from Intel. This is because

the addition of SecureBIOS increases boot time, and complexities, and does not provide

compelling benefits for the STL2 platform.

The Phoenix Phlash Utility may be used to reprogram the BIOS operational code located in the

flash ROM. A BIOS image is provided on a diskette in the form of a binary file that is read by

the Phoenix Phlash Utility. Baseboard revisions may create hardware incompatibilities and may

require different BIOS code.

4.1.2.1

System Flash ROM Layout

The flash ROM contains system initialization routines, BIOS strings, BIOS Setup, and run-time

support routines. The exact layout is subject to change, as determined by Intel. A 16 KB user

block is available for user ROM code and another 128KB block is available for custom logos.

The flash ROM also contains compressed initialization code for on-board peripherals such as

SCSI, NIC, and video controllers. The BIOS image contains all the BIOS components at

appropriate locations. The Phoenix Phlash Utility can be used to reprogram the BIOS

operational code areas.

At run time, none of the flash blocks is visible at the aliased addresses below 1 MB due to

shadowing. Intel reserves the right to change the flash map without notice.

A 64 KB parameter block in the flash ROM is dedicated to storing configuration data that

controls extended system configuration data (ESCD), on-board SCSI configuration, OEM

configuration areas, etc. The block is partitioned into separate areas for logically different data.

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STL2 Server Board TPS

Basic Input Output System (BIOS)

Application software must use standard advanced programmable interrupts (APIs) to access

these areas and may not access the data directly.

4.2 Setup Utility

This section describes the ROM resident setup utility that provides the means to configure the

platform. The setup utility is part of the system BIOS and allows limited control over on-board

resources such as the parallel port and mouse. The following topics are covered below:

Setup utility operation

Configuration CMOS RAM definition

Function of the CMOS clear jumper

4.2.1

Configuration Utilities Overview

Configuration of on-board devices is done using the setup utility that is embedded in flash

ROM. Setup provides sufficient configuration functionality to boot a system diskette or

CDROM. The SSU, which is discussed in a separate document, is released on diskette or

CDROM. Setup is always provided in flash for basic system configuration.

The configuration utilities modify CMOS RAM and NVRAM under direction of the user. The

BIOS POST routines and the BIOS Plug-N-Play Auto-configuration Manager accomplish the

actual hardware configuration. The configuration utilities always update a checksum for both

areas, so that any potential data corruption is detectable by the BIOS before the hardware

configuration takes place. If data is corrupted, the BIOS requests that the user reconfigure the

system and reboot.

4.2.2

Setup Utility Operation

The ROM-resident setup utility configures only on-board devices. The setup utility screen is

divided into four functional areas. Table 4-1 describes each area:

Table 4-1. Setup Utility Screen

Functional Area

Description

Located at the bottom of the screen. This bar displays the keyboard commands

supported by the setup utility.

Keyboard Command Bar

Located at the top of the screen. Displays the various major menu selections

available to the user. The server setup utility major menus are: Main Menu,

Advanced Menu, Security Menu, System Menu, Boot Menu, and the Exit Menu.

Menu Selection Bar

Options Menu

Each Option Menu occupies the left and center sections of the screen. Each menu

contains a set of features. Selecting certain features within a major Option Menu

drops you into submenus.

Located at the right side of the screen is an item-specific Help screen.

Item Specific Help Screen

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Basic Input Output System (BIOS)

STL2 Server Board TPS

4.2.2.1

Entering Setup Utility

During POST operation, the user is prompted to enter Setup using the F2 function key as

follows:

Press <F2> to enter Setup

After the F2 key is pressed, a few seconds might pass before Setup is entered while POST

finishes test and initialization functions that must be completed before Setup can be entered.

When Setup is entered, the Main Menu options page is displayed.

4.2.2.2

Keyboard Command Bar

The bottom portion of the screen provides a list of commands that are used for navigating the

Setup utility. These commands are displayed at all times, for every menu and submenu.

Each Setup menu page contains a number of features. Except those used for informative

purposes, each feature is associated with a value field. This field contains user-selectable

parameters. Depending on the security option chosen and in effect via password, a menu

feature’s value can be changeable or not. If a value is cannot be changed due to insufficient

security privileges or other reasons, the feature’s value field is inaccessible. The Keyboard

Command Bar supports the following:

Help

Pressing F1 on any menu invokes the general Help window. This window describes the Setup

key legend. The up arrow, down arrow, Page Up, Page Down, Home, and End keys scroll the

text in this window.

Enter Execute Command

The Enter key is used to activate submenus when the selected feature is a submenu, or to

display a pick list if a selected feature has a value field, or to select a subfield for multi-valued

features like time and date. If a pick list is displayed, the Enter key will undo the pick list, and

allow another selection in the parent menu.

ESC Exit

The ESC key provides a mechanism for backing out of any field. This key will undo the

pressing of the Enter key. When the ESC key is pressed while editing any field or selecting

features of a menu, the parent menu is re-entered. When the ESC key is pressed in any

submenu, the parent menu is re-entered. When the ESC key is pressed in any major menu,

the exit confirmation window is displayed and the user is asked whether changes can be

discarded.

•

Select Item

The up arrow is used to select the previous value in a pick list, or the previous feature in a

menu item’s option list. The selected item must then be activated by pressing the Enter key.

Select Item

The down arrow is used to select the next value in a menu item’s option list, or a value field’s

pick list. The selected item must then be activated by pressing the Enter key.

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STL2 Server Board TPS

Basic Input Output System (BIOS)

Select Menu

The left and right arrow keys are used to move between the major menu pages. The keys have

no affect if a submenu or pick list is displayed.

F5/– Change Value

The minus key and the F5 function key are used to change the value of the current item to the

previous value. These keys scroll through the values in the associated pick list without

displaying the full list.

F6/+ Change Value

The plus key and the F6 function key are used to change the value of the current menu item to

the next value. These keys scrolls through the values in the associated pick list without

displaying the full list. On 106-key Japanese keyboards, the plus key has a different scan code

than the plus key on the other keyboard, but it still has the same effect.

Setup Defaults

Pressing the F9 key causes the following to appear:

Setup Confirmation

Load default configuration now?

[Yes] [No]

If “Yes” is selected and the Enter key is pressed, all Setup fields are set to their default values.

If “No” is selected and the Enter key is pressed, or if the ESC key is pressed, the user is

returned to where s/he was before the F9 key was pressed, without affecting any existing

values.

F10

Save and Exit

Pressing F10 causes the following message to appear:

Setup Confirmation

Save Configuration changes and exit now?

[Yes] [NO]

If “Yes” is selected and the Enter key is pressed, all changes are saved and Setup is exited. If

“No” is selected and the Enter key is pressed, or the ESC key is pressed, the user is returned

to where s/he was before the F10 key was pressed, without affecting any existing values.

4.2.2.3

Menu Selection Bar

The Menu Selection Bar is located at the top of the screen. It displays the various major menu

selections available to the user:

Main Menu

Advanced Menu

Security Menu

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Basic Input Output System (BIOS)

STL2 Server Board TPS

System Menu

Boot Menu

Exit Menu

These and associated submenus are described below.

4.2.2.4

Main Menu Selections

The following tables describe the available functions on the Main Menu, and associated

submenus. Default values are highlighted.

Table 4-2. Main Menu Selections

Feature

System Time

Choices or Display Only

HH:MM:SS

Description

User Setting

Sets the system time (hour,

minutes, seconds, on 24 hour

clock).

System Date

Diskette A

MM/DD/YYYY

Sets the system date (month, day,

year).

Selects the diskette type.

1.44 / 1.25 MB 3.5" / Disabled

Note: 1.25 MB, 3.5 inch references

a 1024 byte/sector Japanese media

format. To support this type of

media format requires a 3.5 inch,

3-mode diskette drive.

Diskette B

Selects the diskette type.

1.44 / 1.25 MB 3.5" / Disabled

Note: 1.25 MB, 3.5 inch references

a 1024 byte/sector Japanese media

format. To support this type of

media format requires a 3.5 inch,

3-mode diskette drive.

Hard Disk Pre-Delay

Delays first access to disk to

ensure the disk is initialized by the

BIOS before any accesses.

Disabled

3 Seconds

6 Seconds

9 Seconds

12 Seconds

15 Seconds

21 Seconds

30 Seconds

Primary Master

Primary Slave

Processor

Displays IDE device selection.

Enters submenu if selected.

Displays IDE device selection.

Enters submenu if selected.

Enters Processor Settings

submenu if selected.

Language

Selects which language BIOS

displays.

English (US)

French

German

Spanish

Italian

Note: This feature immediately

changes to the language BIOS

selected.

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Basic Input Output System (BIOS)

Table 4-3. Primary Master and Slave Adapters Submenu Selections

Choices or Display

Only

Feature

Description

User Setting

Type

Auto

None

Select the type of device that is attached to the

IDE channel

CD-ROM

ATAPI Removable

IDE Removable

Other ATAPI

User

If User is selected, the user will need to enter the

parameters of the IDE device (cylinders, heads

and sectors).

Mult-Sector Transfers

Disable

Specifies the number of sectors that are

transferred per block during multiple sector

transfers.

2 Sectors

4 Sectors

8 Sectors

16 Sectors

LBA Mode Control

32 Bit I/O

Disabled

Enabled

Enable/Disable Logical Block Addressing instead

of cylinder, head, sector addressing.

Disabled

Enabled

Enable/Disable 32Bit IDE data transfers

Transfer Mode

Standard

Fast PIO 1

Fast PIO 2

Select the method of moving data to and from

the hard drive. (If Type: Auto is select, optimum

transfer mode will be selected)

Fast PIO 3

Fast PIO 4

FPIO 3/ DMA 1

FPIO 4 / DMA 2

Ultra DMA Mode

Disabled

Enabled

Enable/Disable Ultra DMA mode (If Type: Auto is

select, optimum transfer mode will be selected)

Table 4-4. Processor Settings Submenu Selections

Choices or Display

Feature

Only

Description

User Setting

Processor Speed

XXX

(Display Only). Indicates the processor

speed.

Processor 1 Type

Cache Ram

XXX

(Display Only). Indicates the CPUID of the

installed processor.

XXXKB

XXX

(Display Only). Indicates the cache RAM

size.

Processor 2 Type

Cache Ram

(Display Only). Indicates the CPUID of the

installed processor.

XXXKB

(Display Only). Indicates the cache RAM

size.

Processor #1 Status

Processor #2 Status

Clear Processor Errors

Processor Error Pause

Normal¹

(Display Only)

Press Enter

Clears the processor error information.

Enabled

Disabled

If enabled, the POST operation pauses if a

processor error occurs.

Processor Serial Number

Disabled

Enabled

Disables/Enables Processor Serial Number.

Note:

1. Possible Values: Normal, None, or Error.

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Basic Input Output System (BIOS)

STL2 Server Board TPS

4.2.2.5

Advanced Menu Selections

The following tables describe the menu options and associated submenus available on the

Advanced Menu. Please note that MPS 1.4 / 1.1 selection is no longer configurable. The BIOS

will always build MPS 1.4 tables.

Table 4-5. Advanced Menu Selections

Choices or Display

Feature

Only

Description

User Setting

Memory Reconfiguration

Peripheral Configuration

Refer to Memory Reconfiguration Submenu.

Refer to Peripheral Reconfiguration

Submenu.

PCI Device

Refer to PCI Device Submenu.

Option ROM

Refer to Option ROM Submenu. It

Disables/Enables the Option ROM BIOS on

the PCI Bus.

Numlock

Refer to Numlock Submenu.

Reset Configuration Data

Yes

Clears the Extended System Configuration

Data if selected.

Installed O/S

Other

PnP O/S

Selects the type of operating system that will

be used most.

Table 4-6. Memory Reconfiruation Submenu Selections

Choices or Display

Only

Feature

Description

User Setting

System Memory

XXX KB

(Display Only). Indicates the total capacity of the

basic memory.

Extended Memory

XXXXXX KB

(Display Only). Indicates the total capacity of the

extended memory.

DIMM #1 Status

DIMM #2 Status

DIMM #3 Status

DIMM #4 Status

Clear DIMM Errors

DIMM Error Pause

Normal¹

Press Enter

(Display Only)

Clears the DIMM group error status information.

Enabled

Disabled

If enabled, the POST operation pauses if a DIMM

error occurs.

Note:

1. Possible Values: Normal, None, or Error (DIMM Row Error).

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STL2 Server Board TPS

Basic Input Output System (BIOS)

Table 4-7. Peripheral Configuration Submenu Selections

Feature

Choices or Display Only

Description

User Setting

Serial Port 1: (COM 1)

Disabled

Disables serial port 1 or selects the base

3F8, IRQ3

3F8, IRQ4

2F8, IRQ3

2F8, IRQ4

3E8, IRQ3

3E8, IRQ4

2E8, IRQ3

2E8, IRQ4

Auto

address and interrupt (IRQ) for serial port

Serial Port 2: (COM 2)

Disabled

Disables serial port 2 or selects the base

3F8, IRQ3

3F8, IRQ4

2F8, IRQ3

2F8, IRQ4

3E8, IRQ3

3E8, IRQ4

2E8, IRQ3

2E8, IRQ4

Auto

address and interrupt (IRQ) for serial port

Parallel Port

Disabled

378, IRQ5

378, IRQ7

278, IRQ5

278, IRQ7

3BC, IRQ5

3BC, IRQ7

Auto

Disables the parallel port or selects the

base address and interrupt (IRQ) for the

Parallel port.

Parallel Mode

Output only

Bi-directional

EPP

ECP, DMA1

ECP, DMA3

Selects the parallel port operation mode.

Disables/Enables the floppy disk controller.

Diskette Controller

Mouse

Disabled

Enabled

Disabled

Enabled

Auto Detect

Disabled prevents any installed PS/2

mouse from functioning, but frees up

IRQ12.

Enabled forces the PS/2 mouse port to be

enabled regardless if a mouse is present.

Auto Detect enables the PS/2 mouse only if

present.

OS Controlled is displayed if the OS

controls the mouse.

SCSI Controller

LAN Controller

VGA Controller

USB Controller

Disabled

Enabled

Disables/Enables on-board SCSI controller.

Frees resources.

Disabled

Enabled

Disables/Enables on-board LAN controller.

Frees resources.

Disables/Enables on-board Video

controller. Frees resources.

Enabled

Disabled

Enables/Disables on-board USB controller.

Frees resources.

Disabled

Enabled

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STL2 Server Board TPS

Table 4-8. PCI Device Submenu Selections

Choices or Display Only Description

PCI IRQ1 through Disabled

Feature

User Setting

Specify which PIC IRQ a certain PCI IRQ

maps to.

PCI IRQ14

Auto Select

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ9

IRQ10

IRQ11

IRQ12

Table 4-9. Option ROM Submenu Selections

Feature

Choices or

Description

User Setting

Display Only

Onboard SCSI

Disables/Enables option ROM expansion for the on-board

SCSI option ROM. This must be enable if a boot device is

connected to the on-board device.

Enabled

Disabled

Onboard LAN

PCI Slot 1

PCI Slot 2

PCI Slot 3

PCI Slot 4

PCI Slot 5

PCI Slot 6

PCI Slot 7

Disables/Enables option ROM expansion for the on-board LAN

option ROM.

Enabled

Disabled

Disables/Enables the expansion of the option ROM for devices

in PCI slot 1

Enabled

Disabled

Disables/Enables the expansion of the option ROM for devices

in PCI slot 2

Enabled

Disabled

Disables/Enables the expansion of the option ROM for devices

in PCI slot 3

Enabled

Disabled

Disables/Enables the expansion of the option ROM for devices

in PCI slot 4

Enabled

Disabled

Disables/Enables the expansion of the option ROM for devices

in PCI slot 5

Enabled

Disabled

Disables/Enables the expansion of the option ROM for devices

in PCI slot 6

Enabled

Disabled

Disables/Enables the expansion of the option ROM for devices

in PCI slot 7

Enabled

Disabled

Table 4-10. Numlock Submenu Selections

Feature

Choices or

Description

User

Display Only

Setting

Numlock

Key Click

Auto

Off

Selects the power-on state for Numlock.

Disables or enables keyclick.

Disabled

Enabled

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STL2 Server Board TPS

Basic Input Output System (BIOS)

Feature

Choices or

Description

User

Display Only

Setting

Keyboard Auto-repeat Rate

2/sec

Selects key repeat rate.

6/sec

10/sec

13.3/sec

18.5/sec

21.8/sec

26.7/sec

30/sec

Keyboard Auto-repeat Delay

0.25 sec

0.5 sec

0.75 sec

1 sec

Selects delay before key repeat.

4.2.2.6

Security Menu Selections

Table 4-11. Security Menu Selections

Feature

Choices or

Description

User Setting

Display Only

Supervisor Password is

User Password is

Clear

(Display only). Once set, this can be disabled by

setting it to a null string, or by clearing password

jumper on system board.

Clear

(Display only). Once set, this can be disabled by

setting it to a null string, or by clearing password

jumper on system board

Set Supervisor Password

Press Enter

Supervisor password controls access to the

setup utility.

When the <Enter> key is pressed, the user is

prompted for a password; press ESC key to

abort. Once set, this can be disabled by setting it

to a null string, or by clearing password jumper

on system board.

Set User Password

Press Enter

When the <Enter> key is pressed, the user is

prompted for a password; press ESC key to

abort. Once set, this can be disabled by setting it

to a null string, or by clearing password jumper

on system board.

Password on Boot

Fixed Disk Boot Sector

Diskette Access

Disables or enables password entry on boot.

Write protects boot sector on hard disk.

Controls access to diskette drives.

Disabled

Enabled

Normal

Write Protect

User

Supervisor

Secure Mode

See Secure Mode Submenu. Submenu can only

be entered if supervisor and user password is

set.

Power Switch Mask

Masked

Unmasked

Determines whether power switch will function

from front panel

Option ROM Menu Mask

Determines whether on-board SCSI Option ROM

will allow the user to enter adapter configuration

with <CTRL>-A

Unmasked

Masked

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Table 4-12. Secure Mode Submenu Selections

Feature

Choices or

Description

User Setting

Display Only

Secure Mode Timer

Period of keyboard and mouse inactivity before secure

mode is activated and a password is required gain

access.

Disabled

1 Min

2 Min

5 Min

10 min

30 min

1 hr

2 hr

Secure Mode HotKey

Enables/Disables the ability to lock the system with a

<CTRL>+<ALT> + <key> combination. The key can be

selected and submenu appears when enabled. A

password is required to gain access.

Disabled

Enabled

Secure Mode Boot

Enables/Disables secure boot. The system will boot as

normal, but a password is required to access the system

using any PS/2 device

Disabled

Enabled

Floppy Write Protect

Enables/Disables floppy drive write protection. If

enabled, a password is required to write to a floppy.

Disabled

Enable

4.2.2.7

System Hardware Menu Selections

Table 4-13. Server Menu Selections

Feature

Choices or

Description

User Setting

Display Only

Wake On Events

AC Link

See Wake On Events submenu.

Power On

Last State

Stay Off

Selects power retention mode if AC power is lost a

regained.

Error Log Initialization

Press Enter

Select to clear the system Error Log.

If Clear OK, then display “System Event Log Cleared!”

If Clear failed, then display “System Event Log Not

Cleared!”

Console Redirection

Assert NMI on PERR

See Console Redirection Submenu.

Enables PCI PERR support.

Disabled

Enabled

Table 4-14. Wake On Events Submenu Selections

Feature

Choices or

Display Only

Description

Enables/Disables Wake-on-LAN support.

Enables/Disables Wake-on-Ring support.

User

Setting

Wake On LAN

Wake On Ring

Enabled

Disabled

Enabled

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Disabled

Table 4-15. Console Redirection Submenu Selections

Feature

Choices or Display Only

Description

User Setting

Serial Port Address

If enabled, the console will be redirected

to this port.

Disabled

Serial Port 2 (3F8h/IRQ4)

Serial Port 2 (2F8h/IRQ3)

If console redirection is enabled, this

address must match the settings of serial

port 2.

Baud Rate

57.6K

Enables the specified baud rate.

19.2K

Flow Control

No Flow Control

Selects flow control.

XON/OFF

Console Connection

Indicate whether the console is connected

directly to the system or if a modem is

used to connect.

Direct

Via Modem

4.2.2.8

Boot Menu Selections

Boot Menu options allow the user to select the boot device. The following table is an example

of a list of devices ordered in priority of the boot invocation. Items can be re-prioritized by using

the up and down arrow keys to select the device. Once the device is selected, use the plus (+)

key to move the device higher in the boot priority list. Use the minus (-) key to move the device

lower in the boot priority list.

Table 4-16. Boot Menu Selections

Feature

Boot-Time Diagnostic Screen

Enabled

Choices or Display Only

Disabled

Description

User Setting

Enable/Disable boot-time

diagnostic screen. Splash

screen is displayed over the

diagnostic screen when is

option is Disabled.

Boot Device Priority

See Boot Device Priority

Submenu

Hard Drive

See Hard Drive Submenu

Removable Devices

See Removable Devices

Submenu

Table 4-17. Boot Device Priority Selections

Boot Priority Device

Description

User Setting

ATAPI CD-ROM Drive

Removable Devices

Attempts to boot from an ATAPI CD-ROM drive.

Attempts to boot from a removable device.

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STL2 Server Board TPS

Hard Drive

Attempts to boot from a hard drive device.

Attempts to boot from a PXE server.

Intel UNDI, PXE-2.0

Table 4-18. Hard Drive Selections

Boot Priority Device

Description

User Setting

AIC-7899,CH B ID 1¹

Select the order in which each drive is attempted to be

used as the boot device.

AIC-7899, CH A, ID 9¹

AIC-7899, CH B, ID 4¹

Bootable Add-in Cards

Note:

1. These selections will change depending on the system configuration

Table 4-19. Removable Devices Selections

Boot

Device

Description

User Setting

Priority

Legacy Floppy Drives

Select the order in which each removable device is

attempted to be used as the boot device.¹

Note:

1. These selections will change depending on the system configuration

4.2.2.9

Exit Menu Selections

The following menu options are available on the Exit menu. Use the up and down arrow keys

to select an option, then press the Enter key to execute the option.

Table 4-20. Exit Menu Selections

Option

Description

Exit Saving Changes

Exit Discarding Changes

Exit after writing all modified Setup item values to NVRAM.

Exit leaving NVRAM unmodified. User is prompted if any of the setup fields were

modified.

Load Setup Defaults

Discard Changes

Save Changes

Load default values for all SETUP items.

Read previous values of all Setup items from NVRAM.

Write all Setup item values to NVRAM.

4.3 CMOS Memory Definition

Only the BIOS needs to know the CMOS map. The CMOS map is not defined in the BIOS

EPS. The CMOS map is available in the NVRAM.LST file generated for every BIOS release.

The CMOS map is subject to change without notice.

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4.4 CMOS Default Override

The BIOS detects the state of the CMOS default switch. If the switch is set to “CMOS Clear”

prior to power-on or a hard reset, the BIOS changes the CMOS and NVRAM settings to a

default state. This guarantees the system’s ability to boot from floppy.

Password settings are not affected by CMOS clear. The BIOS clears the ESCD parameter

block and loads a null ESCD image. The boot order information is also cleared when CMOS is

cleared via jumper. The configuration data for the on-board SCSI controllers is not cleared

during a clear CMOS event as each device controls its own default settings

If the Reset Configuration Data option is enabled in Setup, ESCD data and BIOS Boot

specification data is cleared and reinitialized in next boot.

4.5 Flash Update Utility

The BIOS update utility (Phoenix* Phlash.exe) loads a fresh copy of the BIOS into flash ROM.

The loaded code and data include the following:

On-board video BIOS, network controller BIOS, and SCSI BIOS.

BIOS Setup utility.

User-definable flash area (user binary area).

OEM logo (splash screen).

When running Phoenix* Phlash in interactive mode, the user may choose to update a

particular flash area. Updating a flash area takes a file or series of files from a hard or floppy

disk, and loads it in the specified area of flash ROM.

Note: The Phoenix Phlash utility must be run without the presence of a 386 protected mode

control program, such as Windows* or EMM386*. Phoenix* Phlash uses the processor’s flat

addressing mode to update the flash part.

4.5.1

Loading the System BIOS

The BIOS update utility (PHLASH) loads a new copy of the BIOS into Flash ROM. The loaded

code and data include the following:

On-board Video BIOS and SCSI BIOS

BIOS Setup Utility

Quiet Boot Logo Area

When running PHLASH in interactive mode, the user may choose to update a particular Flash

area. Updating a flash area loads a file or a series of files from a hard or floppy disk into the

specified area of Flash ROM.

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To manually load a portion of the BIOS, the user must specify which data file(s) to load. The

choices include

PLATCBLU.BIN

PLATCXLU.BIN

PLATCXXX.BIN

PLATCXLX.BIN

PLATCXXU.BIN

The last three letters specify the functions to perform during the flash process:

C = Rewrite BIOS

B = Rewrite Bootblock

L = Clear LOGO area

U = Clear user binary

X = place hold

This file is loaded into the PHLASH program with the /b=<bin file>.

The disk created by the BIOS.EXE program will automatically run phlash /s

/b=PLATCXLU.BIN commandin non-interactive mode. For a complete list of phlash switches,

run phlash /h.

Once an update of the system BIOS is complete, the user is prompted for a reboot. The user

binary area is also updated during a system BIOS update. User binary can be updated

independently of the system BIOS. CMOS is cleared when the system BIOS is updated.

4.5.2

OEM Customization

An OEM can customize the STL2 BIOS for product differentiation. The extent of customization

is limited to what is stated in this section. OEMs can change the BIOS look and feel by adding

their own splash screen/logo. OEMs can manage OEM-specific hardware, if any, by executing

their own code during POST by using the “User-supplied BIOS Code Support.”

4.5.2.1

User-supplied BIOS Code Support

A 16 KB region of flash ROM is available to store a user binary. The Phoenix* Phlash utility

allows the OEM or end user to update the user binary region with OEM supplied code and/or

data. At several points throughout POST, control is passed to this user binary. Intel provides

tools and reference code to help OEMs create a user binary. The user binary must adhere to

the following requirements:

To allow detection by BIOS and protection from run time memory managers, the user

binary must have an option ROM header (i.e., 55AAh, size).

The system BIOS performs a scan of the user binary area at predefined points during

POST. Mask bits must be set within the user binary to inform the BIOS which entry

points exist.

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The system state must be preserved by the user binary (all registers, including

extended and MMX, stack contents, and nonuser binary data space, etc.).

The user binary code must be relocatable. The user binary is located within the first 1

MB of memory. The user binary code must not make any assumptions about the value

of the code segment.

The user binary code is always executed from RAM and never from flash.

The user binary must not hook critical interrupts, must not reprogram the chip set, and

must not take any action that affects the correct functioning of the system BIOS.

The user binary ROM must be checksummed. The checksum byte must be placed in

the last byte position of the 16K ROM.

The BIOS copies the user binary into system memory before the first scan point. If the user

binary reports that it does not contain run time code, it is located in conventional memory (0-

640 KB). Reporting that the user binary has no run time code has the advantage of not using

limited option ROM space (therefore, more option ROMs may be executed in a large system

configuration). If user binary code is required at run time, it is copied into and executed from

option ROM space (0C8000H – 0E7fffH).

At each scan-point during POST, the system BIOS determines if the scan-point has a

corresponding user binary entry point to transfer control to the user binary. Presence of a valid

entry point in the user binary is determined by examining the bitmap at byte 4 of the user

binary header; each entry point has a corresponding “presence” bit in this bitmap. If the bitmap

has the appropriate bit set, an entry point ID is placed in the “AL” register and execution is

passed to the address computed by (ADR(Byte 5)+5*scan sequence #).

During execution, the user binary may access 11 bytes of extended BIOS data area RAM

(EBDA). The segment of EBDA can be found at address 40:0e. Offset 18h through offset 22h

is available for the user binary. The BIOS also reserves 8 CMOS bits for the user binary.

These bits are in an unchecksummed region of CMOS with default values of zero, and will

always be located in the first bank of CMOS. These bits are contiguous, but are not in a fixed

location. Upon entry into the user binary, DX contains a ‘token’ that points to the reserved bits.

This token is of the following format:

MSB

LSB

# of bit available –1

Bit offset from start of CMOS of first bit

The most significant four bits are equal to the number of CMOS bits available minus one. This

field is equal to seven, since eight CMOS bits are available. The 12 least significant bits define

the position of the CMOS bit in the real-time clock (RTC). This is a bit address rather than a

byte address. The CMOS byte location is 1/8th of the 12-bit number, and the remainder is the

starting bit position within that byte. For example, if the 12-bit number is 0109h, user binary

can use bit 1 of CMOS byte 0108h/8 or 021h. It should be noted that the bits available to the

user binary may span more than one byte of CMOS (i.e., a value of 07084h indicates that the

upper nibble of byte 10h and the lower nibble of byte 11h are reserved for the user binary).

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The following code fragment shows the header and format for a user binary:

55h, 0AAh, 20h

; 16KB USER Area

MyCode

PROC FAR

; MUST be a FAR procedure

; Far return instruction

CBh

04h

; Bit map to define call points, a 1

; in any bit specifies

; that the BIOS is called at that

; scan point in POST

CBh

; First transfer address used to

; point to user binary extension

; structure

; Word Pointer to extension

; structure

; Reserved

JMP

ErrRet

Start

; This is a list of 7 transfer

; addresses, one for each

; bit in the bitmap.

; 5 Bytes must be used for each

; JMP to maintain proper offset for

; each entry. Unused entry JMP’s

; should be filled with 5 byte

; filler or JMP to a RETF

;

JMP

ErrRet

4.5.2.2

Scan Point Definitions

The table below defines the bitmap for each scan point, indicating when the scan point occurs

and which resources are available (RAM, stack, binary data area, video, and keyboard).

Table 4-21. User Binary Area Scan Point Definitions

Scan Point

Mask RAM/Stack/BDA Video/Keyboard

01h

Not applicable

Near pointer to the user binary extension structure, mask bit is 0 if

this structure is not present. Instead of a jump instruction the scan

address (offset 5) contains an 0CB followed by a near pointer.

Obsolete. No action taken.

02h

04h

08h

10h

Yes

This scan occurs immediately after video initialization.

This scan occurs immediately before video initialization.

Yes

This scan occurs on POST error. On entry, BX contains the

number of the POST error.

Yes

This final scan occurs immediately prior to the INT 19 for normal

boot and allows one to completely circumvent the normal INT 19

boot if desired.

20h

Yes

This scan occurs immediately before the normal option ROM

scan.

40h

80h

Yes

This scan occurs immediately following the option ROM area

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scan.

Table 4-22. Format of the User Binary Information Structure

Bit Definition

Offset

Bit 0 = 1 if mandatory user binary, 0 if not mandatory. If

a user binary is mandatory, it will always be executed. If

a platform supports a disabling of the user binary scan

through Setup, this bit will override Setup setting.

Bit 1 - 1 if runtime presence required (other than SMM

user binary portion, SMM user binary will always be

present in runtime irrespective of setting of this bit).

0, if not required in runtime, and can be discarded at

boot time.

Bit 7:2 – reserved for future expansion.

Reserved for future expansion.

1 - 0fh

If this structure is not present (bit 0 of the scan point structure is not set), the system BIOS

assumes that the user binary is not mandatory (bit 0 in User Binary Information Structure

assumed cleared), and it is required in run time (bit 1 in User Binary Information Structure

assumed set).

4.5.2.3

OEM Splash Screen

A 128 KB region of Flash ROM is available to store the OEM logo in compressed format. The

BIOS will contain the standard Intel logo. Using the Phoenix Phlash utility, this region can be

updated with an OEM supplied logo image. The OEM logo must fit within 640 X 480 size. If an

OEM logo is flashed into the system, it will override the built in Intel logo.

Intel supplies utilities that will compress and convert a 16 color bitmap file into a logo file

suitable for Phoenix8 Phlash.

4.5.3

Language Area

The system BIOS language area can be updated only by updating the entire BIOS. The STL2

platform supports English, Spanish, French, German, and Italian. Intel provides translations for

all the strings in five languages. These languages are selectable using Setup.

4.5.4

Recovery Mode

In the case of a corrupt or an unsuccessful update of the system BIOS, the STL2 can boot in

recovery mode. To place STL2 into recovery mode, move the boot option jumper (jumper block

1J15 pins 9-10) to the recovery boot position. By default and for normal operation, pins 9 and

10 are not jumpered.

Recovery mode requires at least 8 MB of RAM in the first DIMM socket, and drive A: must be

set up to support a 3.5” 1.44 MB floppy drive. (Note: the system requires 64 MB to boot). This

is the mode of last resort, used only when the main system BIOS will not come up. In recovery

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mode operation, PHLASH (in non-interactive mode only) automatically updates only the main

system BIOS. PHLASH senses that STL2 is in recovery mode and automatically attempts to

update the system BIOS

Before powering up the system, the user must obtain a bootable diskette that contains a copy

of the BIOS recovery files. This is created by running the “crisdisk.bat” from the compressed

recovery file distributed with the BIOS.

Note: During recovery mode, video will not be initialized and many high-pitched beep tones will

be heard. The entire process takes two to four minutes. When the process is completed, the

tones will stop. The user may see a “Checksum error” on the first boot after updating the BIOS.

This is normal and should correct itself after the first boot.

If a failure occurs, it is most likely that of the system BIOS .ROM file is corrupt or missing.

After a successful update, power down the system and remove the jumper from pins 9-10.

Power up the system. Verify that the BIOS version number matches the version of the entire

BIOS used in the original attempt to update.

4.6 Error Messages and Error Codes

The system BIOS displays error messages on the video screen. Prior to video initialization,

beep codes inform the user of errors. POST error codes are logged in the event log. The BIOS

displays POST error codes on the video monitor.

Following are definitions of POST error codes, POST beep codes, and system error

messages.

4.6.1

POST Codes

The BIOS indicates the current testing phase during POST after the video adapter has been

successfully initialized by writing a 2-digit hex code to I/O location 80h. If a Port-80h card

(Postcard*) is installed, it displays this 2-digit code on a pair of hex display LEDs.

Table 4-23. Port-80h Code Definition

Code

Meaning

Phoenix* check point (port-80) code

The table below contains the port-80 codes displayed during the boot process. A beep code is

a series of individual beeps on the PC speaker, each of equal length. The following table

describes the error conditions associated with each beep code and the corresponding POST

check point code as seen by a ‘port 80h’ card. For example, if an error occurs at checkpoint

22h, a beep code of 1-3-1-1 is generated. The “-“ means there is a pause between the

sequence that delimits the sequence.

Some POST codes occur prior to the video display being initialized. To assist in determining

the fault, a unique beep-code is derived from these checkpoints as follows:

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The 8-bit test point is broken down to four 2-bit groups.

Each group is made one-based (1 through 4)

One to four beeps are generated based on each group’s 2-bit pattern.

Example:

Checkpoint 04Bh will be broken down to: 01 00 10 11

And the beep code will be:

2 – 1 – 3 – 4

Table 4-24. Standard BIOS Port-80 Codes

Beeps

Reason

Verify Real Mode

Get Processor type

Initialize system hardware

Initialize chipset registers with initial POST values

Set in POST flag

Initialize Processor registers

Enable Processor cache

Initialize caches to initial POST values

Initialize I/O

Initialize the local bus IDE

Initialize Power Management

Load alternate registers with initial POST values

Restore Processor control word during warm boot

Initialize keyboard controller

BIOS ROM checksum

1-2-2-3

8254 timer initialization

8237 DMA controller initialization

Reset Programmable Interrupt Controller

Test DRAM refresh

1-3-1-1

1-3-1-3

Test 8742 Keyboard Controller

Set ES segment register to 4GB

1-3-3-1

1-3-4-1

Autosize DRAM, system BIOS stops execution here if the BIOS does not detect any usable

memory DIMMs

Clear 8 MB base RAM

Base RAM failure, BIOS stops execution here if entire memory is bad

Test Processor bus-clock frequency

Test CMOS

RAM Initialize alternate chipset registers

Warm start shut down

Reinitialize the chipset

Shadow system BIOS ROM

Reinitialize the cache

Autosize cache

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Beeps

Reason

Configure advanced chipset registers

Load alternate registers with CMOS values

Set Initial Processor speed new

Initialize interrupt vectors

Initialize BIOS interrupts

2-1-2-3

Check ROM copyright notice

Initialize manager for PCI Option ROMs

Check video configuration against CMOS

Initialize PCI bus and devices

Initialize all video adapters in system

Display QuietBoot screen

Shadow video BIOS ROM

Display copyright notice

Display Processor type and speed

Test keyboard

Set key click if enabled

USB initialization

Enable keyboard

2-2-3-1

Test for unexpected interrupts

Display prompt "Press F2 to enter SETUP"

Test RAM between 512 and 640k

Test extended memory

Test extended memory address lines

Jump to UserPatch1

Configure advanced cache registers

Enable external and processor caches

Display external cache size

Load custom defaults if required

Display shadow message

Display non-disposable segments

Display error messages

Check for configuration errors

Test real-time clock

Check for keyboard errors

Test for key lock on

Set up hardware interrupt vectors

Intelligent system monitoring

Test coprocessor if present

Detect and install external RS232 ports

Initialize PC-compatible PnP ISA devices

Re-initialize on board I/O ports

Initialize BIOS Data Area

Initialize Extended BIOS Data Area

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Beeps

Reason

Initialize floppy controller

Initialize hard disk controller

Initialize local bus hard disk controller

Jump to UserPatch2

Build MPTABLE for multi-processor boards

Disable A20 address line

Install CD-ROM for boot

Clear huge ES segment register

1-2

Search for option ROMs. One long, two short beeps on checksum failure

Shadow option ROMs

Set up Power Management

Enable hardware interrupts

Set time of day

Check key lock

Initialize typematic rate

Erase F2 prompt

Scan for F2 key stroke

Enter SETUP

Clear in-POST flag

Check for errors

POST done – prepare to boot Operating System

One short beep before boot

Display MultiBoot menu

Check password, password is checked before option ROM scan

ACPI initialization

Clear global descriptor table

Clear parity checkers

Clear screen (optional)

Check virus and backup reminders

Try to boot with INT 19

Forced shutdown

Flash recovery

Interrupt handler error

Unknown interrupt error

Pending interrupt error

Initialize option ROM error

Shutdown error

Extended Block Move

Shutdown 10 error

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Table 4-25. Recovery BIOS Port-80 Codes

Reason

Beeps

Initialize chip set

Initialize bridge

Initialize processor

Initialize timer

Initialize system I/O

Check forced recovery boot

Validate checksum

Go to BIOS

Initialize processors

Set 4 GB segment limits

Perform platform initialization

Initialize PIC and DMA

Initialize memory type

Initialize memory size

Shadow boot block

Test system memory

Initialize interrupt services

Initialize real time clock

Initialize video

Initialize beeper

Initialize boot

Restore segment limits to 64 KB

Boot mini DOS

Boot full DOS

4.6.2

POST Error Codes and Messages

The following table defines POST error codes and their associated messages. The BIOS

prompts the user to press a key in case of a serious error. Some error messages are preceded

by the string "Error” to highlight that the system might be malfunctioning. All POST errors and

warnings are logged in the system event log unless it is full.

Table 4-26. POST Error Messages and Codes

Code

0200:

0210:

0211:

0212:

0213:

0220:

Error Message

Failure Description

hard disk error

Failure Fixed Disk

Stuck Key

Keyboard connection error

Keyboard failure

Keyboard error

Keyboard Controller Failed

Keyboard locked

Keyboard locked– Unlock key switch

Monitor type does not match CMOS– Run SETUP

Monitor type does not match CMOS

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Code

Basic Input Output System (BIOS)

Failure Description

Error Message

0230:

0231:

0232:

System RAM Failed at offset

System RAM error

Offset address

Shadow RAM Failed at offset

Shadow RAM Failed

Offset address

Extend RAM Failed at address line

Extended RAM failed

Offset address

0233:

0234:

0235:

0250:

0251:

Memory type mixing detected

Single – bit ECC error

Memory type mixing detected

Memory 1 bit error detected

Memory multiple-bit error detected

NVRAM battery dead

Multiple- bit ECC error

System battery is dead – Replace and run SETUP

System CMOS checksum bad – Default configuration

used

CMOS checksum error

0252:

0260:

0270:

0271:

02B0:

02B2:

02D0:

0B00:

0B1B:

0B1C:

0B50:

0B51:

0B5F:

0B60:

0B61:

0B62:

0B63:

0B6F:

0B70:

0B71:

0B74:

0B75:

0B7C:

Password checksum bad - Passwords cleared

System timer error

RTC error

Real time clock error

Check date and time setting

RTC time setting error

Diskette drive A error

Incorrect Drive A type – run SETUP

System cache error – Cache disabled

Rebooted during BIOS boot at Post Code

PCI System Error on Bus/Device/Function

PCI Parity Error in Bus/Device/Function

CPU#1 with error taken offline

Incorrect Drive A type

CPU cache error

PCI system error in Bus/device/Function

Failed CPU#1 because an error was detected

Failed CPU#2 because an error was detected

An error detected in the entire CPU

Memory error, memory group #1 failed

Memory error, memory group #2 failed

Memory error, memory group #3 failed

Memory error, memory group #4 failed

An error detected in all the memory

Error while detecting a temperature failure.

Temperature error detected.

CPU#2 with error taken offline

Forced to use CPU with error

DIMM group #1 has been disabled

DIMM group #2 has been disabled

DIMM group #3 has been disabled

DIMM group #4 has been disabled

DIMM group with error is enabled

The error occurred during temperature sensor reading

System temperature out of the range

The error occurred during voltage sensor reading

System voltage out of the range

Error while detecting voltage

System voltage error

The error occurred during redundant power module

confirmation

The error occurred while retrieving the power

information

0B80:

0B81:

0B82:

0B83:

0B90:

0B91:

0B92:

BMC Memory Test Failed

BMC device (chip) failed

BMC Firmware Code Area CRC check failed

BMC core Hardware failure

BMC IBF or OBF check failed

Access to BMC address failed

BMC device(chip) failed

BMC Platform Information Area corrupted.

BMC update firmware corrupted.

Internal Use Area of BMC FRU corrupted.

SROM storing chassis information failed

(Available for use except for FRU command

and EMP function)

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Code

0B93:

0B94:

Error Message

Failure Description

BMC device (chip) failed

BMC SDR Repository empty.

IPMB signal lines do not respond.

SMC(Satellite Management Controller) failed

(Available for use except for the access

function to SMC via IPMB)

0B95

BMC FRU device failure.

SROM storing chassis information failed

(Available for use except for FRU command

and EMP function.)

0B96

BMC SDR Repository failure.

BMC device (chip) failed

0B97

BMC SEL device failure.

0BB0:

0BB1:

0BD0:

0BD1:

0BD2:

SMBIOS – SROM data read error

SMBIOS – SROM data checksum bad

1st SMBus device address not acknowledged.

1st SMBus device Error detected.

1st SMBus timeout.

SROM data read error

Bad checksum of SROM data

Some SMBus device (chip) failed

Expansion ROM not initialized.

Invalid System Configuration Data

System Configuration Data Read Error

Resource Conflict

PCI Expansion ROM card not initialized

System configuration data destroyed

System configuration data read error

PCI card resource is not mapped correctly.

System configuration data write error

PCI interrupt is not configured correctly.

System Configuration Data Write error

Warning: IRQ not configured

8503:

Incorrect memory speed in location: XX, XX, …

Non-PC133 DIMMs have been installed in slots

XX, XX, …

A beep code is a series of individual beeps on the PC speaker, each of equal length. The

following table describes the error conditions associated with each beep code and the

corresponding POST check point code as seen by a port 80h card. For example, if an error

occurs at checkpoint 22h, a beep code of 1-3-1-1 is generated. The beep codes 1-1-1-1, 1-5-

1-1, 1-5-2-1 and 1-5-3-1 are reserved for BMC usage.

Beeps

1-2-2-3

1-3-1-1

1-3-1-3

1-3-3-1

Error

Cause

Recommended Action

Change system board

Change memory DIMM's

Change system board

Verify DIMM installation.

Change memory DIMM's

Verify DIMM installation.

Change memory DIMM's

Change DIMM or M/B

—

ROM Checksum Error

DRAM Refresh Test Error

Keyboard Controller Test Error

Memory Not Detected

—

No memory.

Can not write to memory

No memory.

Memory Capacity Check Error

Can not write to memory

Memory address signal failure

Memory data signal failure (low)

Memory data signal failure (high)

—

1-3-4-1

1-3-4-3

1-4-1-1

1-4-3-3

2-1-2-3

2-2-3-1

2-3-1-3

DRAM Address Test Error

DRAM Test low byte Error

DRAM Test high byte Error

All Memory Group Errors

BIOS ROM Copy-Write Test Error Error with Shadow RAM

Change system board

Change CPU or system board

Change DIMM or M/B

Unexpected Interrupt Test Error

All Memory Group Errors

Unexpected interrupt

Memory address signal failure

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Basic Input Output System (BIOS)

3-3-1-4

1-2

Memory Not Detected

—

Option ROM Initialization Error

Failure to initialize Option ROM

BIOS

Change system board or option

board

1-2

Video configuration fails

Failure to initialize VGA BIOS

Change option video board or

system board

OPTION ROM Checksum Error

Failure to initialize Option BIOS

Change M/B or option board

4.7 Identifying BIOS and BMC Revision Levels

The following sections provide information to help identify a system's current BIOS and BMC

revision levels.

4.7.1

BIOS Revision Level Identification

During system POST, which runs automatically when the system is powered on, the monitor

displays several messages, one of which identifies the BIOS revision level currently loaded on

the system (see the following example).

Phoenix BIOS 4.0 Release 6.0.250A

In the example above, BIOS 6.0.250A is the current BIOS revision level loaded on the system.

Note: Press the Esc key to see the diagnostic messages.

Note: The BIOS Revision Level stated in the example might not reflect the actual BIOS setting

in any particular system.

4.7.2

BMC Revision Level Identification

During system POST, which runs automatically when the system is powered on, system

diagnostics are run. Following the memory test diagnostic, several messages appear to inform

the user that the mouse was detected and system configuration data updated. The BMC

messages follow these.

To identify the system's current BMC revision level, see the following example.

Base Board Management Controller

Device ID :01 Device Revision :00

IPMI Version

:1.0 Firmware Revision

:00.60

Self Test Result:

In the example above, Firmware Revision 00.60 is the current BMC revision level loaded on

the system.

Note: Press the Esc key to see the diagnostic messages.

Note: The Firmware Revision level in the example might not reflect the actual BMC revision

level in any particular system.

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STL2 Server Board TPS

4.8 Adaptec SCSI Utility

The Adaptec SCSI Utility detects the SCSI host adapters on the server board. The Adaptec

SCSI Utility is used to:

Change default values

Check and/or change SCSI device settings that may conflict with those of other devices

in the server.

4.8.1

Running the SCSI Utility

The user can access the Adaptec SCSI Utility when the system is powered on or rebooted. To

run the Adaptec SCSI utility, perform the following procedure.

1. Power-on or reboot the system.

2. At the message to “Press Ctrl-A to run SCSI Utility”, press Ctrl+A.

3. Choose the host adapter that needs to be configured.

4. The SCSI utility starts. When the Adaptec SCSI Utility detects more than one AIC-78xx

host adapter, it displays a selection menu listing the bus and device number of each

adapter. When the selection menu appears, select the channel that should be configured

as follows.

Bus: Device: Channel

01: 04: A¹

Selected SCSI Adapter

AIC7899

01: 04: B

AIC7899

Note:

Internal SCSI Connector

When the adapter is selected, the following options display.

Description

Configure/View Host Adapter Settings

SCSI Disk Utilities

Configure host adapter and device settings.

The utility scans the SCSI bus for SCSI devices and reports a description

of each device. Run these utilities before configuring SCSI devices.

To format a disk, verify disk media, or display a list of devices and their SCSI IDs, select “SCSI

Disk Utilities”. To configure the adapter or a device, select “Configure/View Host Adapter

Settings.”

4.8.2

Adaptec SCSI Utility Configuration Settings

The following keys are active for all Adaptec SCSI Utility screens.

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Key

Arrows

ENTER

ESC

Action

Up and down arrows move from one parameter to another within a screen.

Displays options for a configurable parameter. Selects an option.

Moves back to previous screen or parameter or EXIT if at the Main menu.

Switches between color and monochrome.

Resets to host adapter defaults.

The following table shows the normal settings for the Adaptec SCSI Utility and provides a

place to record any changes made to these settings.

Table 4-27. Adaptec SCSI Utility Setup Configurations

Option

Recommended Setting or

Display Only

User Setting

SCSI Bus Interface Definitions

Host Adapter SCSI ID

SCSI Parity Checking

Enabled

Host Adapter SCSI Termination

Additional Options

Boot Device Options

Press Enter for menu

Boot Channel

A First

Boot SCSI ID

Boot LUN Number

SCSI Device Configuration

Sync Transfer Rate (MBps)

Initiate Wide Negotiation

Enable Disconnection

Press Enter for menu

160

Yes

Send Start Unit Command

Enable Write Back Cache

BIOS Multiple LUN Support

Include in BIOS Scan

Yes

No ¹

Yes ¹

Advanced Configuration Options

Plug-and-Play SCAM Support

Reset SCSI Bus at IC Initialization

Display <Ctrl-A> Messages During BIOS Initialization

Extended BIOS Translation for DOS Drives >1 Gbyte

Verbose/Silent Mode

Press Enter for menu.

Disabled

Enabled

Verbose

Enabled¹

Host Adapter BIOS (Configuration Utility Reserves BIOS

Space)

Domain Validation

Enabled

Support Removable Disks Under BIOS as Fixed Disks

BIOS Support for Int13 Extensions

Notes:

Disabled^{1, 2}

Enabled¹

No effect if BIOS is disabled.

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Do not remove media from a removable media drive if it is under BIOS control.

4.8.3

Exiting Adaptec SCSI Utility

To exit the Adaptec SCSI Utility, the user presses the Esc key several times, until a message

prompts him / her to exit. If changes have been made, the user is prompted to save them

before exiting.

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Jumpers and Connectors

5. Jumpers and Connectors

STL2 Server Board Jumper and Connector Locations

The following figure shows the location of the jumper blocks and connectors on the STL2

Server board.

Figure 5-1. STL2 Server Board Jumper and Connector Locations

Jumper and connector location key for Figure 5-1:

A. Main power connector (P33)

B. VRM socket (P32)

C. Auxiliary power connector (P34)

D. Primary processor (P13)

E. Secondary processor (P14)

F. Secondary processor heatsink fan connector (P36)

G. Power supply signal connector (P37)

H. DIMM slots (P15-P18)

I. IDE connector (P19)

J. Floppy drive connector (P20)

K. Two pin speaker connector (P31)

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L. System fan connector FAN3A (P29)

M. Battery

N. System fan connector FAN2A (P27)

O. Front panel connector(P23)

P. Four pin speaker connector (P25)

Q. Ultra Single Ended (SE) SCSI connector (P9)

R. Ultra160 LVD SCSI connector (P8)

S. Configuration jumper block (1L4)

T. Configuration jumper block (1J15)

U. CPU speed jumper block (5E1)

V. 33 MHz/32-bit PCI connectors

W. 66 MHz/64-bit PCI connectors

X. Chassis intrusion connector (pins 1-2 of 6A)

Y. System fan connector FAN1 (P11)

Z. I/O ports

AA. Primary processor heatsink fan connector (P12)

The following diagram shows the location of the connectors on the STL2 server board I/O

panel.

Figure 5-2. I/O Back Panel Connectors

I/O Back Panel location key for Figure 5-1:

A. USB connectors

B. Serial port 2 connector

C. Serial port 1 connector

D. NMI switch

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E. Parallel port connector

F. Keyboard connector

G. Mouse connector

H. Video connector

I. Network connector

5.1 Jumper Blocks

Jumpers on several jumper blocks of the STL2 server board are used to set the system

configuration. The jumpers are small plastic-encased conductors (shorting plugs) that slip over

two jumper pins on a jumper block.

On the STL2 server board, the following jumper blocks are user-configurable. The figure below

shows the default settings for the STL2 jumper blocks.

1J15 (CMOS and Password Clear)

5E1 (Processor Frequency)

1L4 (Configuration)

6A (Chassis Intrusion)

CMOS / Password Clear

(Location 1J15)

Chassis Intrusion

(Location 6A)

10 12

CPU Clock Frequency

(Location 5E1)

Configuration Jumper

(Location 1L4)

5.1.1

Setting CMOS/Password Clear Jumper Block 1J15

Setting a jumper on system board jumper block 1J15 enables the user to clear the CMOS or to

clear a forgotten password. See the above figure for the location of the jumper block location.

The following table lists the factory default settings for jumper block 1J15, which are indicated

in bold typeface. Procedures for setting the jumper on the block follow the table.

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Table 5-1. Jumper Block 1J15 Settings

Jumper Pin

Numbers

Function

Jumper Position

What it does at system reset

1 - 2

CMOS clear

Preserves the contents of CMOS

Open, Protect

Closed, Erase

Open, Normal

Closed, Disable

Open, Not Used

Open, Normal

Clears CMOS

3 - 4

Password protected

Preserves the password

Disables the password

No function

5 - 6

7 - 8

9 - 10

Reserved

No function

BIOS Recovery Boot

BIOS Recovery Boot disabled. Normal

operation.

Closed, Recovery Boot

If this jumper is set, BIOS recovery will be

attempted from a bootable BIOS recovery

floppy diskette.

11 - 12

Spare

Provides a spare jumper

Closed, Spare

5.1.1.1

Clearing and Changing a Password

Clear and change a password as follows.

1. Power off the system, unplug the power cord, and remove the chassis panel.

2. Use needle nose pliers or your fingers to remove the spare jumper from pins 11-12 on

jumper block 1J15.

3. Reinstall the jumper on pins 3-4 (Password Disable) of jumper block 1J15.

4. Reinstall the chassis panel, plug in the power cord(s), and power on the system.

5. While waiting for POST to complete, press the F2 key to enter BIOS setup.

6. This automatically clears all passwords, provided you save and exit the BIOS setup.

7. Power off the system, unplug the power cord(s), and remove the chassis panel.

8. Remove the Password Disable jumper from pins 3-4 and store the jumper on pins 11-12.

9. Replace the chassis panel, plug in the power cord(s), and power on the system.

10. To specify a new password run the BIOS Setup Utility as described earlier in this section.

5.1.1.2

Clearing CMOS

Clear CMOS as follows.

1. Power off the system, unplug the power cord, and remove the chassis panel.

2. Use needle-nose pliers or your fingers to remove the spare jumper from pins 11-12 on

jumper block 1J15.

3. Position the jumper over pins 1-2 on jumper block 1J15.

4. Replace the chassis panel, plug in the power cable(s), and power on the system.

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5. After POST completes, power down the system, unplug the power cable(s), and remove

the chassis panel.

6. Remove the jumper from pins 1-2 and store the jumper on pins 11-12.

7. Replace the chassis panel and connect system cables.

8. Power on the system, press F2 at the prompt to run the BIOS Setup utility, and select “Get

Default Values” at the Exit menu.

5.1.1.3

Perfoming a BIOS Recovery Boot

In the event of BIOS corruption, the following procedure may be used to perform a BIOS

Recovery.

1. Obtain the BIOS update file package from Intel’s iBL or http://support.intel.com web site.

2. A file called “crisis.zip” is one of the files included with each STL2 BIOS release file

package. Unzip the “crisis.zip” file to a directory on your hard drive.

3. Obtain a blank formatted floppy diskette (the floppy diskette should not be a bootable DOS

diskette). Insert the blank formatted floppy diskette in the floppy drive.

4. From a MS-DOS prompt or from the MS-DOS prompt window, run the “crisdisk.bat” file

from the directory you created on your hard drive. Follow the instructions on the screen to

create the BIOS recovery floppy diskette.

5. Power off the STL2 system, unplug the power cord, and remove the chassis panel.

6. Remove the spare jumper from pins 11-12 on jumper block 1J15.

7. Reinstall the jumper on pins 9-10 (BIOS Recovery) of jumper block 1J15.

8. Insert the BIOS recovery floppy diskette into the diskette drive.

9. Reinstall the chassis panel, plug in the power cord(s), and power on the system.

10. The screen will remain blank while the BIOS Recovery is performed. A number of beeps

will occur during the BIOS update. The floppy drive access light will not turn off when the

BIOS recovery is completed. Allow four minutes for the BIOS recovery to complete. If a

POST card is installed in a PCI slot during the BIOS recovery, you can tell that the BIOS

recovery is complete when code “EC” is displayed. When the BIOS Recovery is complete,

it is safe to power off the system.

11. Power off the system, unplug the power cord(s), and remove the chassis panel.

12. Remove the BIOS Recovery jumper from pins 9-10 and store the jumper on pins 11-12.

13. Replace the chassis panel, plug in the power cord(s), and power on the system.

14. Perform a CMOS clear following the BIOS recovery.

5.1.1.4

Setting Processor Frequency Jumper Block 5E1

The jumpers on block 5E1 set the processor speed for the installed processor(s). The following

table lists the settings for jumper block 5E1. Procedures for setting the jumpers follow the

table.

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Table 5-2. Jumper Block 5E1 Settings

Processor Frequency (

MHz)

Jumper Settings

1-2

Not Jumpered

Jumpered

3-4

5-6

7-8

667

733

800

867

933

1000

Not Jumpered

Jumpered

Not Jumpered

Jumpered

Not Jumpered

Jumpered

Not Jumpered

Jumpered

Not Jumpered

Jumpered

Not Jumpered

Set the processor frequency jumpers as follows.

1. Power off the system, unplug the power cord.

2. From the “Jumper Block 5E1 Settings” table, select the processor frequency matching the

installed processor.

3. Move the jumpers to the settings shown in the “Jumper Block 5E1 Settings” table.

4. Reinstall the left panel, plug in the power cord(s), and power on the system.

The following table lists the factory default settings for jumper block 5E1, which are indicated in

bold typeface.

Table 5-3. Jumper Block 1J15 Default Settings

Jumper Pin

Numbers

Function

Jumper Position

What it does at system reset

1 - 2

3 - 4

5 - 6

7 - 8

9 - 10

Processor Frequency Select

133 MHz FSB

Open

Enables 133 MHz FSB

Open, Enabled

Closed, Disabled

Open, Disabled

Closed, Enabled

Disables 133 MHz FSB

11 - 12

Spread Spectrum

Disables FCC (Spread Spectrum)

Enables FCC (Spread Spectrum)

5.1.2

Setting Configuration Jumper Block 1L4

Setting the jumpers on system board jumper block 1L4 enables the user to configure chassis

intrusion sensors, or enable/disable BMC FRB (see the above figure for jumper block location).

The following table lists the factory default settings for jumper block 1L4.

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Table 5-4. Jumper Block 1L4 Settings

Jumper Pin

Numbers

Function

Jumper Position

Function

Enables FRB

1 – 2

FRB

Open, Enabled

Closed, Disabled

Open, Enabled

Disables FRB

3 – 4

Front Cover Chassis Intrusion

Sensor

Enables Chassis Intrusion

sensing. This jumper may be

under as a chassis intrusion

switch connector.

5 – 6

Side Cover Chassis Intrusion

Sensor

Disables Chassis Intrusion

sensing

Closed, Disabled

Open, Enabled

Enables Chassis Intrusion

sensing

7 – 8

No Function

Reserved

No Function

Spare

No Function

Open, Not Used

Closed, Spare

9 – 10

11 – 12

9 – 11

No Function

Provides a spare jumper

5.1.3

Setting Configuration Jumper Block 6A

Setting the jumpers on system board jumper block 6A enables the user to configure the front

cover chassis intrusion sensing. Jumper 6A pins 1-2 may also be used as a chassis intrusion

switch connector. The following table lists the factory default settings for jumper block 6A.

Table 5-5. Jumper Block 6A Settings

Jumper Pin

Numbers

Function

Jumper Position

Open, Enabled

Function

1 – 2

Front Cover Chassis

Intrusion Sensor

Enables Chassis Intrusion sensing. This

jumper may be under as a chassis intrusion

switch connector.

Closed, Disabled

Open, Enabled

Closed, Disabled

Open, Not Used

Disables Chassis Intrusion sensing

Enables Chassis Intrusion sensing

Disables Chassis Intrusion sensing

No Function

3 – 4

5 – 6

7 – 8

Reserved

No Function

Reserved

5.2 Connectors

This section provides pin information about the connectors on the STL2 server board.

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5.2.1

Main ATX Power Connector (P33)

Table 5-6. Main ATX Power Connector Pinout

Signal

+3.3 VDC

COM

Wire color

Orange

Black

Signal

+3.3 VDC

-12 VDC

COM

Wire Color

Orange

Blue

Black

Green

Black

N.C.

+5 VDC

COM

Red

PS-ON_L

COM

Black

+5 VDC

COM

Red

COM

Black

COM

PWR-GD

5 VSB

Grey

N.C.

Purple

Yellow

Orange

+5 VDC

COM

Red

+12 VDC

+3.3 VDC

Red

Black

5.2.2

Auxilary ATX Power Connector (P34)

Table 5-7. Auxiliary ATX Power Connector Pinout

Signal

+5 VDC

+3.3 VDC

COM

Wire Color

Red

Orange

Black

COM

Black

COM

Black

5.2.3

I²C Power Connector (P37)

Table 5-8. I²C Power Connector Pinout

Signal

N.C.

Signal

N.C.

+3.3 VDC

N.C.

I²C Data

I²C Clock

N.C.

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5.2.4

System Fan Connectors (P29, P27, P11)

System Fan 1: P11

System Fan 2: P27

System Fan 3: P29

Table 5-9. Board Fan Connector Pinout

Signal

Fan Sense

+ 12 VDC

COM

5.2.5

Processor Connectors (P12, P36)

Primary Processor Fan 1: P36

Secondary Processor Fan 2: P12

Table 5-10. Processor Fan Connector Pinout

Signal

N.C.

+ 12 VDC

COM

5.2.6

Speaker Connector (P31)

Table 5-11. Speaker Connector Pinout

Signal

SPEAKER

GND

5.2.7

Speaker Connector (P25)

Table 5-12. Speaker Connector Pinout

Signal

SPEAKER

GND

N.C.

GND

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5.2.8

Diskette Drive Connector (P20)

Figure 5-3. Diskette Drive Connector Pin Diagram

Table 5-13. Diskette Drive Connector Pinout

Signal

GND

Signal

FD_DENSEL

No Connection

FD_MDAID

FD_INDEX_L

FD_MON0_L

FD_SEL1_L

FD_SEL0_L

FD_MON1_L

FD_DIR_L

FD_STEP_L

FD_WDATA_L

FD_WGATE_L

FD_TRK0_L

FD_WPT_L

FD_RDATA_L

FD_SIDE_L

FD_DCHG_L

5.2.9

SVGA Video Port

Table 5-14. Video Port Connector Pinout

Signal

Red

Signal

Green

Blue

GND

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Signal

DDCDAT

HSYNC

VSYNC

GND

DDCCLK

5.2.10

Keyboard and Mouse Connectors

The keyboard and mouse connectors are functionally equivalent.

Table 5-15. Keyboard and Mouse Connector Pinouts

Keyboard Signal

KEYDAT

Mouse Signal

MSEDAT

GND

FUSED_VCC (+5 V)

KEYCLK

FUSED_VCC (+5 V)

MSECLK

5.2.11

Parallel Port

Table 5-16. Parallel Port Connector Pinouts

Signal

STROBE_L

Data bit 0

Data bit 1

Data bit 2

Data bit 3

Data bit 4

Data bit 5

Data bit 6

Data bit 7

Signal

ACK_L

Busy

SLCT

AUTO_L

ERROR_L

INIT_L

SLCTIN_L

GND

18 25

5.2.12

Serial Ports COM1 and COM2

Table 5-17. Serial Ports COM1 and COM2 Connector Pinouts

Signal

Description

DCD

Data carrier detected

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Signal

RXD

TXD

DTR

GND

DSR

RTS

CTS

RIA

Description

Receive data

Transmit data

Data terminal ready

Ground

Data set ready

Return to send

Clear to send

Ring indication active

5.2.13

RJ-45 LAN Connector

Table 5-18. RJ-45 LAN Connector Signals

Signal

Description

TX+

Transmit data plus—the positive signal for the TD differential pair contains the serial output data

stream transmitted onto the network

TX-

Transmit data minus—the negative signal for the TD differential pair contains the same output as

pin 1

RX+

Receive data plus—the positive signal for the RD differential pair contains the serial input data

stream received from the network

RX-

Receive data minus—the negative signal for the RD differential pair contains the same input as

pin 3

5.2.14

USB Connectors

Table 5-19. USB Connectors

USB 1 Pin

Signal

+5 VDC

USB 2 Pin

Signal

+5 VDC

USB_P1_N

USB_P1_P

GND

USB_P0_N

USB_P0_P

GND

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5.2.15

Ultra SCSI Connector (P9)

Table 5-20. Ultra SCSI Connector Pinout

1-16

Signal

GND

49-50

Signal

GND

TERMPWR

20-34

GND

SCD12_L

SCD13_L

SCD14_L

SCD15_L

SCDPH_L

SCD0_L

SCD1_L

SCD2_L

SCD3_L

SCD4_L

SCD5_L

SCD6_L

SCD7_L

SCDP_L

SATN_L

GND

SBSY_L

SACK_L

RESET_L

SMSG_L

SSEL_L

SCD_L

SREQ_L

SI/O_L

SCD8_L

SCD9_L

SCD10_L

SCD11_L

5.2.16

Ultra160 SCSI Connector (P8)

Table 5-21. Ultra160 SCSI Connector

Signal

SCDAP12

SCDAP13

SCDAP14

SCDAP15

SCDAPHP

SCDAP0

SCDAP1

SCDAP2

SCDAP3

SCDAP4

SCDAP5

SCDAP6

SCDAP7

SCDAPLP

Signal

SCDAN12_L

SCDAN13_L

SCDAN14_L

SCDAN15_L

SCDAPHN_L

SCDAN0_L

SCDAN1_L

SCDAN2_L

SCDAN3_L

SCDAN4_L

SCDAN5_L

SCDAN6_L

SCDAN7_L

SCDAPLN_L

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Signal

GND

Signal

GND

DIFFSENSA

TRMPWRA

No Connection

GND

TRMPWRA

No Connection

GND

ATNAP

ATNAN_L

GND

BSY

BSYAN_L

ACKAN_L

RSTAN_L

MSGAN_L

SELAN_L

CDAN_L

ACK

RSTAP

MSGAP

SELAP

CDAP

REQAP

IOAP

REQAN_L

IOAN_L

SCDAP8

SCDAP9

SCDAP10

SCDAP11

SCDAN8_L

SCDAN9_L

SCDAN10_L

SCDAN11_L

5.2.17

IDE Connector (P19)

Figure 5-4. IDE Connector Pin Diagram

If no IDE drives are present, no IDE cable should be connected. If a single IDE drive is

installed, it must be connected at the end of the cable.

Table 5-22. IDE Connector Pinout

Signal

RESET_L

DD7

Signal

GND

DD8

DD9

DD10

DD6

DD5

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Signal

DD4

Signal

DD11

DD3

DD12

DD2

DD13

DD1

DD14

DD0

DD15

GND

No Connection

GND

IDEDRQ

DIOW_L

DIOR_L

IORDY

IDEDAK_L

IDEIRQ

IDESA1

IDESA0

IDECS0_L

Keyed

GND

No Connection

IDESA2

IDECS1_L

GND

5.2.18

32-Bit PCI Connector

Table 5-23. 32-Bit PCI Connector Pinout

Signal

TRST_L

+12 V

TMS

Signal

-12 V

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

Signal

AD16

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B50

B51

Signal

AD17

TCK

+3.3 V

FRAME_L

GND

CBE2_L

GND

TDI

TD0 (NC)

+5 V

IRDY_L

+3.3 V

DEVSEL_L

GND

+5 V

TRDY_L

GND

INTA_L

INTC_L

+5 V

INTB_L

INTD_L

PRSNT1_L

Reserved

PRSNT2_L

GND

STOP_L

+3.3 V

SDONE

SBO_L

GND

LOCK_L

PERR_L

+3.3 V

SERR_L

+3.3 V

CBE1_L

AD14

Reserved

+5 V

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

Reserved

GND

PARITY

AD15

GND

Reserved

RST_L

+5 V

Reserved

GND

+3.3 V

AD13

GND

PCICLK

GND

AD11

AD12

GNT_L

GND

AD10

REQ_L

+5 V

AD9

GND

PME_L

AD30

KEY

AD31

KEY

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A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

+3.3 V

AD28

AD26

GND

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

AD29

GND

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

CBE0_L

+3.3 V

AD6

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

AD8

AD7

AD27

AD25

+3.3 V

CBE3_L

AD23

GND

+3.3 V

AD5

AD4

AD24

IDSEL

+3.3 V

AD22

AD20

GND

AD3

AD2

GND

AD1

AD0

+5 V

AD21

AD19

+3.3 V

REQ64_L

+5 V

ACK64_L

+5 V

AD18

+5 V

5.2.19

64-Bit PCI Connector

Table 5-24. 64-Bit PCI Connctor Pinout

Signal

TRST_L

+12 V

TMS

Signal

-12 V

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

A67

A68

A69

A70

A71

A72

A73

Signal

GND

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

B63

B64

B65

B66

B67

B68

B69

B70

B71

B72

B73

Signal

AD10

M66EN

KEY

TCK

AD9

GND

KEY

TDI

TD0 (NC)

+5 V

KEY

+5 V

CBE0_L

+3.3 V

AD6

AD8

INTA_L

INTC_L

+5 V

AD7

INTB_L

INTD_L

PRSNT1_L

Reserved

PRSNT2_L

GND

+3.3 V

AD5

AD4

Reserved

+5 V

GND

AD3

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

AD2

GND

Reserved

GND

AD0

AD1

+5 V

GND

REQ64_L

+5 V

ACK64_L

+5 V

Reserved

RST_L

+5 V

Reserved

GND

+5 V

PCICLK

GND

Reserved

GND

GNT_L

GND

CBE7_L

CBE5_L

+3.3 V

Parity

AD62

GND

REQ_L

+5 V

CBE6_L

CBE4_L

GND

PME_L

AD30

AD31

+3.3 V

AD28

AD29

AD63

AD61

+3.3 V

AD59

AD57

GND

AD26

AD27

AD60

AD58

GND

AD25

AD24

+3.3 V

CBE3_L

IDSEL

AD56

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A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

Signal

+3.3 V

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

Signal

AD23

A74

A75

A76

A77

A78

A79

A80

A81

A82

A83

A84

A85

A86

A87

A88

A89

A90

A91

A92

A93

A94

Signal

AD54

B74

B75

B76

B77

B78

B79

B80

B81

B82

B83

B84

B85

B86

B87

B88

B89

B90

B91

B92

B93

B94

Signal

AD55

AD22

GND

+3.3 V

AD52

AD50

GND

AD53

GND

AD20

AD21

GND

AD19

AD51

AD49

+3.3 V

AD47

AD45

GND

AD18

+3.3 V

AD17

AD16

AD48

AD46

GND

+3.3 V

FRAME_L

GND

CBE2_L

GND

IRDY_L

+3.3 V

DEVSEL_L

GND

AD44

AD42

+3.3 V

AD40

AD38

GND

TRDY_L

GND

AD43

AD41

GND

STOP_L

+3.3 V

SDONE

SBO_L

GND

LOCK_L

PERR_L

+3.3 V

SERR_L

+3.3 V

CBE1_L

AD14

AD39

AD37

+3.3 V

AD35

AD33

GND

AD36

AD34

GND

PARITY

AD15

AD32

Reserved

GND

+3.3 V

AD13

Reserved

GND

AD11

AD12

Reserved

5.2.20

Front Panel 24-pin Connector Pinout (P23)

Table 5-25. Front Panel 24-pin Connector Pinout

Description

Power LED Anode

Reserved

Key

Fan Fault LED Anode

Power LED Cathode

Fan Fault LED Cathode

Hard Drive Activity LED Anode

Power Fault LED Anode

Hard Drive Activity LED Cathode

Power Fault LED Cathode

Power Switch (Low True)

NIC Activity LED Anode

Power Switch (GND)

NIC Activity LED Cathode

Reset Switch (Low True)

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Reserved

Reset Switch (GND)

Reserved

ACPI Sleep Switch (Low True)

Chassis Intrusion

ACPI Sleep Switch (GND)

Reserved

NMI to CPU Switch (Low True)

Reserved

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STL2 Server Board TPS

Power Consumption

6. Power Consumption

6.1 Calculated Power Consumption

The following table shows the calculated power consumption for each of the power supply

voltage rails for the STL2 server board. These values were calculated using the specifications

for the on-board components and processors. Assumptions for add-in card power and other

peripherals powered from the server board are included in the table. Customers will need to

modify the calculated power consumption numbers based on their anticipated usage – watts

per PCI slot, etc.

Note: The following numbers are provided only as an example. Actual power consumption will

vary depending on the exact configuration, temperature, voltage level, etc. Refer to the

appropriate system chassis document for more information.

Table 6-1. STL2 Server Board Calculated Power Consumption

Device(s)

Server Board

3.3V

4.6A

+5V

+12V

-12V

5V Standby

Totals

12.5A

0.06A

0.0A

0.18A

Processors (87% VRM

efficiency, 100% utilization)

1 x 667 MHz/256K

processor

4.02A

4.21A

4.78A

5.26A

5.63A

6.0A

1 x 733 MHz/256K

processor

1x 800EB MHz/256K

processor

1x 866 MHz/256K

processor

1x 933 MHz/256K

processor

1x 1 GHz/256K processor

5.5A

Memory (Four PC133

Registered GB SDRAM

DIMMs)

PCI Connectors

32 bit PCI slots (10W per slot

on 5V)

8.0A

0.4A

0.2A

64 bit PCI slots (10W per slot 6.06A

on 3.3V)

1.00A

0.50A

USB (500mA per connector)

Keyboard/Mouse

SCSI term power

Included in board spec.

1.32A

Fans (3 chassis and 2

processor)

16.16A 34.0A

53.33W 170.0W

1.38A

0.0A

0.78A

3.9W

Total

Total Current

Total Power

16.6W

0.0W

243.83W

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Power Consumption

STL2 Server Board TPS

The total power calculation assumes a system configuration containing dual Pentium® III 1

GHz processors with the VRM for both processors supplied by the 5V source, four 1 GHz

DIMMs, all PCI slots containing 10W cards, two USB devices, keyboard & mouse, three

chassis fans, and two processor fan heat sinks.

6.2 Measured Power Consumption

A STL2 FAB 2 server board was configured with dual 866 MHz processors, both supplied by

the 5V voltage regulation modules (VRMs), and four 1GB PC133 SDRAM DIMMs (Infineon part

number HYS72V128320GR).

The system was configured with Microsoft Windows NT 4.0. Test software utilized during the

power consumption measurement consisted of the Hipower test suite, used to simulate

medium processor activity, and the WinMTA memory stress test suite, used to simulate high

memory activity.

The STL2 server board measured power consumption including the memory and processor

power is listed in the following table.

Table 6-2. STL2 Server Board Measured Power Consumption

Device(s)

3.3V

+5V

+12V

Total Wattage

Server Board

6.0A

8.5A

0.01A

63.5W

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Mechanical Specifications

7. Mechanical Specifications

The diagram on the following page shows the mechanical specifications of the STL2 server

board. All dimensions are in inches. Connectors are dimensioned to pin 1.

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Regulatory and Integration Information

8. Regulatory and Integration Information

8.1 Regulatory Compliance

The STL2 server board complies with the following safety standard requirements.

Table 8-1. Safety Regulations

Regulation

UL 1950/CSA950

Title

Bi-National Standard for Safety of Information Technology Equipment

including Electrical Business Equipment. (USA and Canada)

EN 60950

The Standard for Safety of Information Technology Equipment including

Electrical Business Equipment. (European Community)

IEC60 950

The Standard for Safety of Information Technology Equipment including

Electrical Business Equipment. (International)

EMKO-TSE (74-SEC) 207/94

EU Low Voltage Directive 73/23/ECC

Summary of Nordic deviations to EN 60950. (Norway, Sweden, Denmark,

and Finland)

Compliance to EU LV Directive via EN60 950 / IEC 60950

The STL2 server board has been tested and verified to comply with the following EMC

regulations when installed in a compatible Intel host system. For information on Intel

compatible host system(s), refer to Intel’s Server Builder website, or contact your local Intel

representative.

Regulation

FCC – Class A

Title

Title 47 of the Code of Federal Regulations, Parts 2 and 15, Subpart B, pertaining

to unintentional radiators. (USA)

ICES-003 – Class A

CISPR 22

Interference-Causing Equipment Standard, Digital Apparatus, Class A (including

CRC c. 1374) (Canada).

Limits and methods of measurement of Radio Interference Characteristics of

Information Technology Equipment. (International)

VCCI – Class A

EN55022

Implementation Regulations for Voluntary Control of Radio Interference by Data

Processing Equipment and Electronic Office Machines. (Japan)

Limits and methods of measurement of Radio Interference Characteristics of

Information Technology Equipment. (Europe)

EN55024

Generic Immunity Standard; currently compliance is determined via testing to IEC

801-2, -3, and -4. (Europe)

EU EMC Directive

89/336/EEC

Compliance to EU EMC Directive via EN55022 & EN55024

Taiwan EMC Regulations based on CISPR 22

BSMI (CNS13438) – Class A

C-tick (AS/NZS 3548)

Australia & New Zealand EMS Regulations based on CISPR 22

This server board assembly has the following required certification type markings:

UL Joint Recognition Mark: Consists of small c (for Canada) followed by a stylized

backward UR and followed by a small US (USA) (on component side).

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Intel’s UL File Number E139761 (Component side).

Battery “+” marking: located on the component side of the board in close proximity to

the battery holder.

CE Mark: (Component side)

Australian C-Tick Mark: Consists of solid circle with white check mark and supplier code

N232.

Russian GOST (Open letter “C” with the letter “P” inside the “C” and the letter “T” in the

mouth of the “C”.

Taiwan BSMI Certification mark. Two Chinese characters and an 8 digit number.

8.2 Installation Instructions

CAUTION: Follow these guidelines to meet safety and regulatory requirements when installing

this board assembly.

Read and adhere to these instructions and to the instructions supplied with the host computer

and associated modules. If the instructions for the host computer are inconsistent with these

instructions or the instructions for associated modules, contact the supplier’s technical support

to find out how to ensure that the system meets safety and regulatory requirements. If the

instructions are not followed, the user increases safety risk and the possibility of

noncompliance with regional laws and regulations.

8.2.1

Ensure EMC

Before computer integration, the host chassis, power supply, and other modules should pass

EMC certification testing.

In the installation instructions for the host chassis, power supply, and other modules, pay close

attention to the following:

Certifications.

External I/O cable shielding and filtering.

Mounting, grounding, and bonding requirements.

Keying connectors when mismating of connectors could be hazardous.

If the host chassis, power supply, and other modules have not passed applicable EMC

certification testing before integration, EMC testing must be conducted on a representative

sample of the newly completed computer.

8.2.2

Ensure Host Computer and Accessory Module Certifications

The host computer and any added subassembly (such as a board or drive assembly, including

internal or external wiring) should be certified for the region(s) where the end product will be

used. Marks on the product are proof of certification. Certification marks are as follows:

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Regulatory and Integration Information

8.2.2.1

In Europe

The CE marking signifies compliance with all relevant European requirements. If the host

computer does not bear the CE marking, obtain a supplier’s Declaration of Conformity to the

appropriate standards required by the European EMC Directive and Low Voltage Directive.

Other directives, such as the Machinery and Telecommunications Directives, may also apply

depending on the type of product. No regulatory assessment is necessary for low voltage DC

wiring used internally or wiring used externally when provided with appropriate overcurrent

protection. Appropriate protection is provided by a maximum 8 Amp current limiting circuit or a

maximum 5 Amp fuse or positive temperature coefficient (PTC) resistor. This Intel server board

has PTCs on all external ports that provide DC power externally.

8.2.2.2

In the United States

A certification mark by a Nationally Recognized Testing Laboratory (NRTL) such as UL, CSA,

or ETL signifies compliance with safety requirements. External wiring must be UL Listed and

suitable for the intended use. Internal wiring must be UL Listed or Recognized and rated for

applicable voltages and temperatures. The FCC mark (Class A for commercial or industrial

only or Class B for residential) signifies compliance with electromagnetic interference

requirements.

8.2.2.3

In Canada

A nationally recognized certification mark such as CSA or cUL signifies compliance with safety

requirements. No regulatory assessment is necessary for low voltage DC wiring used internally

or wiring used externally when provided with appropriate overcurrent protection. Appropriate

protection is provided by a maximum 8 Amp current limiting circuit or a maximum approved

5 Amp fuse or positive temperature coefficient (PTC) resistor. This server board has PTCs on

all external ports that provide DC power externally.

8.2.3

Prevent Power Supply Overload

The power supply output must not be overloaded. To avoid overloading the power supply, the

calculated total current load of all the modules within the computer should be less than the

maximum output current rating of the power supply. If this is not adhered to, the power supply

may overheat, catch fire, or damage the insulation that separates hazardous AC line circuitry

from low voltage user accessible circuitry and result in a shock hazard. If the load drawn by a

module cannot be determined by the markings and instructions supplied with the module,

contact the module supplier’s technical support.

8.2.4

Place Battery Marking on Computer

There is insufficient space on this server board to provide instructions for replacing and

disposing of the battery. The following warning must be placed permanently and legibly on the

host computer as near as possible to the battery.

WARNING: Danger of explosion if battery is incorrectly replaced.

Replace with only the same or equivalent type recommended by the manufacturer. Dispose of

used batteries according to the manufacturer’s instructions.

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8.2.5

Use Only for Intended Applications

This product was evaluated for use in ITE computers that will be installed in offices, schools,

computer rooms and similar locations. The suitability of this product for other product

categories other than ITE applications, (such as medical, industrial, alarm systems, and test

equipment) may require further evaluation.

8.2.6

Installation Precautions

During the installation and testing of the board, the user should observe all warnings and

cautions in the installation instructions. To avoid injury, be aware of the following:

Sharp pins on connectors.

Sharp pins on printed circuit assemblies.

Rough edges and sharp corners on the chassis.

Hot components (like processors, voltage regulators, and heat sinks).

Damage to wires that could cause a short circuit.

Observe all warnings and cautions that instruct you to refer computer servicing to

qualified technical personnel.

WARNING: Do not open the power supply. There is risk of electric shock and burns from high

voltage and rapid overheating. Refer servicing of the power supply to qualified technical

personnel.

8.3 Environmental Limits

8.3.1

System Office Environment

Table 8-2. Office System Environment Summary

+10°C to +35°C with the maximum rate of change not to exceed

Operating Temperature

10°C per hour

Non-Operating Temperature

Non-Operating Humidity

-40°C to +70°C

95%, non-condensing @ 30°C

0.5° per 1000 feet

Altitude De-rate

Acoustic noise

< 47 dBA with one power supply @ 28+-2°C

< 50 dBA with two power supplies @ 28+-2°C

< 55 dBA with three power supplies @ 28+-2°C

Operating Shock

No errors with a half sine wave shock of 2G (with 11 millisecond

duration)

Package Shock

ESD

System operational after a 30" free fall, cosmetic damage may

be present

20KV per Intel Environmental Test Specification

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Regulatory and Integration Information

8.3.2

System Environmental Testing

The system environmental tests include the following:

Temperature Operating and Non-Operating

Humidity Non-Operating

Shock Packaged and Unpackaged

Vibration Packaged and Unpackaged

AC Voltage, Freq. & Source Interrupt

AC Surge

Acoustics

ESD

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Glossary

Term

Definition

ASIC

ASR

BMC

BSP

Application Specific Integrated Circuit

Asynchronous Reset

Baseboard Management Controller

Bootstrap Processor

EMP

ESCD

FRB

Emergency Management Port

Extended System Configuration Data

Fault Resilient Booting

FRU

HPIB

IMB

Field Replaceable Unit

Hot-plug Indicator Board

Intra Module Bus

IPMB

MADP

MBE

MEC

MECC

Intelligent Platform Management Bus

Memory Address and Data Path

Multiple Bit Error

Memory Expansion Card

Memory Expansion Card Connector

Multiprocessor

MSR

MTTR

NIC

Model Specific Register

Mean Time To Repair

Network Interface Card

Non-maskable Interrupt

Operating System

NMI

PHP

PHPC

PME

POST

RAMDAC

RTC

SBE

PCI Hot-plug

PCI Hot-plug Controller

Power Management Event

Power On Self Test

Random Access Memory Digital-to-Analog Converter

Real Time Clock

Single Bit Error

SEC

SEL

Single Edge Contact

System Event Log

SGRAM

SHV

Synchronous Graphics RAM

Standard High Volume

Server Management

SMM

SSU

TAP

Server Management Module

System Setup Utility

Test Access Port

TBD

To Be Determined

USB

ZCR

Universal Serial Bus

Zero Channel RAID

Revision 1.0

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Reference Documents

STL2 Server Board TPS

Reference Documents

ServerWorks ServerSet* III LE North Bridge Specification.

ServerWorks ServerSet* III LE South Bridge Specification.

PCI Local Bus Specification, Revision 2.2.

USB Specification, Revision 1.0.

5-Volt Flash File (28F008SAx8) Datasheet.

AIC-7899 PCI-Dual Channel SCSI Multi-function Controller Data Manual.

ATI Rage IIC Technical Reference Manual.

I²C Bus Specification.

Intelligent Platform Management Bus Communications Protocol Specification.

VRM 8.4 DC-DC Converter Specification.

Adaptec AIC-7899 PCI Bus Master Dual-channel Ultra160 SCSI Host Adapter Chip

Data Book.

Intel 82559 Fast Ethernet Multifunction PCI/CardBus Controller Datasheet.

Intelligent Platform Management Interface (IPMI) Specification.

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STL2 Server Board EPS

Index

ACPI, 2-7, 3-23, 3-25, 3-26, 4-49, 5-73

Adaptec* AIC7899, 1-1, 2-8

ECC, 1-1, 2-7, 3-22, 3-23, 3-24, 4-50, 8-79

EEPROM, 2-9

Address, 2-9, 2-13, 2-17, 3-25, 4-39, 4-52

AIC-7899, 2-8, 2-9, 2-10, 2-20, 4-40

APIC, 2-6, 2-10, 2-14, 2-15, 2-17

Architecture, 2-5

Emergency Management Port, See EMP

EMP, 3-25, 4-51

Environmental Limits, 8-82

Error, 3-22, 3-23, 3-24, 3-25, 4-33, 4-34, 4-38, 4-46, 4-50,

4-51, 4-52

ATI* Rage IIC, 2-12, 2-13, 2-20

ESM, See Enterprise System Management Console, 3-24

Ethernet, 1-2, 2-10

Exit Menu, 4-29, 4-32, 4-40

Baseboard Management Controller. See BMC

BIOS, 1-2, 2-8, 2-10, 2-14, 2-16, 2-17, 3-21, 3-22, 3-26,

4-27, 4-28, 4-29, 4-32, 4-34, 4-40, 4-41, 4-42, 4-43,

4-44, 4-45, 4-46, 4-47, 4-48, 4-49, 4-50, 4-51, 4-52,

4-53, 4-55, 5-60, 5-61

Fan, 3-23, 6-75

Fan, 2-6, 3-22, 3-23, 5-65, 5-73

Fan, System, 5-65

BIST, 3-24

BMC, 1-2, 2-5, 2-14, 2-16, 3-21, 3-23, 3-24, 3-25, 4-51,

4-52, 4-53, 5-62, I

Fault Resilient Booting, See FRB

FC-PGA, 1-1, 2-5, 2-6

Bridge, 1-1, 2-6, 2-7, 2-10, 2-14, 2-15, 2-17, 2-20

Built-in Self Test, 3-24

Field Replaceable Unit, See FRU

Flash ROM, 4-28, 4-41, 4-45

Flip Chip Pin Grid Array, 1-1

FRB, 3-21, 5-62, 5-63

Front Panel, 3-23, 3-24, 5-73

Front Panel reset, 3-23, 3-24, 3-25, 4-34, 4-41, 4-47, 4-55,

5-73

Front Side Bus, 1-1

FRU, 3-21, 4-51

Certification, 8-80

Chassis Intrusion, 3-22, 3-23, 5-59, 5-63, 5-73

Checksum, 4-46, 4-52

CMOS, 2-16, 4-27, 4-28, 4-29, 4-40, 4-41, 4-42, 4-43,

4-47, 4-48, 4-50, 5-59, 5-60, 5-61

CMOS Clear Jumper, 5-59

Configuration, 2-9, 2-13, 3-25, 4-28, 4-29, 4-31, 4-34,

4-35, 4-41, 4-52, 4-54, 4-55, 5-58, 5-59, 5-62, 5-63

Connection, 3-23, 4-39, 5-66, 5-69, 5-70, 5-71

Connector, Drive, 5-66

GPIO, 2-7

Connector, Fan, 5-65

Connector, PCI, 5-71, 5-72, 6-75

Connector, Power, 5-64

I²C, 3-25, 5-64

Console Redirect, 4-38, 4-39

IB6566 South Bridge, 1-1, 1-2, 2-6, 2-7, 2-10, 2-14, 2-15,

2-16, 2-17, 2-20

Console Redirection, 4-28, 4-38, 4-39

Controller, 1-2, 2-8, 2-9, 2-10, 2-12, 2-13, 2-15, 3-21,

4-35, 4-47, 4-50, 4-52

ICH, 2-11

Initialization, 3-24, 4-38, 4-52, 4-55

Install, 4-48

Core Component, 2-5

Intel^®82559, 1-2, 2-10, 2-11, 2-20

Intel® Celeron™ processor, 2-5

Intelligent Platform Management Bus, See IPMB

Interrupt Controller, 2-15, 4-47

IPMB, 4-51

DC-to-DC converter, 2-6

DIMM, 1-1, 2-7, 4-34, 4-45, 4-51, 4-52, 5-57

IRQ 12, 2-20

Revision 1.0

III

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Index

STL2 Server Board TPS

ISA, 2-14, 2-15, 2-16, 2-17, 3-21, 3-24, 4-48

4-42, 4-43, 4-44, 4-46, 4-47, 4-49, 4-50,

4-52, 4-53, 5-60, 5-61

PXE, 3-23, 3-24, 4-39

JEDEC, 1-1, 2-7

Real Time Clock, See RTC

Recovery, 4-45, 4-49, 5-60, 5-61

Redirection, 4-38

LED, 5-73

Legacy, 2-15, 4-40

Logo, 4-41

Reset Button, 3-23, 3-24

RTC, 2-15, 3-25, 4-43, 4-51

LUN, 4-55

SC242, 2-5

SC242 connector, 2-5

Magic Packet, 3-22

SCSI, 1-1, 2-5, 2-8, 2-9, 2-10, 2-20, 3-23, 4-27, 4-28, 4-

35, 4-36, 4-37, 4-41, 4-53, 4-54, 4-55, 5-58, 5-68, 5-69,

6-75

SCSI Connector, 4-54, 5-68, 5-69

SDR, 3-21, 4-51

Main Menu, 4-29, 4-30, 4-31, 4-32

Management Controller, 4-51, 4-53

Memory, 2-5, 2-7, 2-9, 2-13, 2-17, 3-22, 3-24, 4-34, 4-40,

4-50, 4-51, 4-52, 6-75

Message, 4-50

SDR Repository, 3-21, 4-51

Modem, 4-39

MPS, 4-28, 4-34

Multi-Processor Specification, 4-28, 4-34

SDRAM, 1-1, 2-7, 6-75, 6-76

Secure Mode, 3-22, 3-23, 4-37, 4-38

SecureBIOS, 4-28

Security, 3-22, 3-23, 4-28, 4-29, 4-31, 4-37

Processor, 2-5, 2-6, 3-22, 3-23, 3-24, 3-25, 4-32, 4-33,

4-47, 4-48, 5-59, 5-61, 5-62, 5-65

SEL, 3-21, 3-23, 3-24, 4-51

Sensor, 3-21, 3-22

NB6635 North Bridge, 1-1, 2-7, 2-20

NMI, 3-23, 3-24, 4-38, 5-58, 5-73

North Bridge, 1-1, 2-7, 2-20

Sensor Data Record, See SDR

Sensor Event, 3-21, 3-23, 3-24, 4-38

Sensor, Chassis Intrusion, 5-58

Sensor, Fan, 2-6, 3-22, 3-23, 5-65, 5-73

Sensor, Processor, 2-5, 2-6, 3-22, 3-23, 3-24, 3-25, 4-32,

4-33, 4-47, 4-48, 5-59, 5-61, 5-62, 5-65

Sensor, Temperature, 3-22, 3-23, 4-51, 8-82

Sensor, Type, 3-22, 3-23

NVRAM, 4-29, 4-40, 4-41, 4-50

Password, 3-23, 4-37, 4-41, 4-51, 5-59, 5-60

Password Clear, 5-59

PERR, 3-23, 3-24, 4-38, 5-71, 5-72

PGA370, 1-1, 2-5, 2-6

PIC, 2-15, 2-17, 2-18, 4-36, 4-50

POST, 3-22, 3-24, 3-25, 4-29, 4-30, 4-33, 4-34, 4-42, 4-

43, 4-44, 4-46, 4-47, 4-49, 4-50, 4-52, 4-53, 5-60, 5-61

POST Code, 4-46

Power Button, 3-23, 3-24

Power Control, 3-22

Power Distribution Board, 3-22

Power Down, 3-25

Power state, 3-25

Sensor, Type Code, 3-23

Sensor, Voltage, 3-22, 3-23, 8-79, 8-80, 8-82

Serial, 1-2, 2-16, 4-33, 4-35, 4-39, 5-58, 5-67

SERR, 3-23, 3-24, 5-71, 5-73

Server Management, 3-21

Server Menu, 4-38

ServerWorks ServerSet III LE chipset, 1-1, 2-5, 2-7

Setup Utility, 3-26, 4-27, 4-28, 4-29, 4-30, 4-41, 5-60

SGRAM, 1-2, 2-10, 2-12

Shadow, 4-47, 4-48, 4-49, 4-50, 4-52

Shutdown, 4-49

SMBIOS, 4-51

SMI, 3-21, 3-23, 3-25

SMM, 4-45

Power Supply, 3-22, 5-57

Power-on Self-Test

South Bridge, 1-1, 1-2, 2-6, 2-7, 2-10, 2-14, 2-15, 2-17,

2-20

Speaker, 5-65

See POST, 3-22, 3-24, 3-25, 4-29, 4-

30, 4-33, 4-34,

SSU, 4-27, 4-29

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STL2 Server Board EPS

Index

Super I/O Controller, 1-2

USB, 1-2, 2-7, 2-10, 2-14, 2-15, 2-17, 4-35, 4-48, 5-58,

5-68, 6-75, 6-76

User Binary, 4-44, 4-45

System Event Log, See SEL

System Management Software, 3-21

System Setup Utility, See SSU

Voltage, See also Sensor, Voltage, 3-22, 3-23, 8-79, 8-80,

8-82

Temperature, 3-22, 3-23, 4-51, 8-82

termination circuitry, 2-6

Third-party instrumentation, 1-1, 2-8, 2-20, 4-53, 4-54,

4-55

VRM, 1-1, 2-6, 5-57, 6-75, 6-76

Timeout, 3-23, 3-24, 3-25

Transfer Mode, 4-33

Type Code 3-23

Warning, 4-52

Windows NT, 3-26, 6-76

Ultra160 LVD, 5-58

Universal Serial Bus, 1-2, 2-7, 2-10, 2-14, 2-15, 2-17,

4-35, 4-48, 5-58, 5-68, 6-75, 6-76

zero-insertion force socket, 2-5, 2-6

ZIF socket, 2-6

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