Intel® Server Boards S5000PSL
and S5000XSL
Technical Product Specification
Intel order number: D41763-003
Revision 1.2
September 2006
Enterprise Platforms and Services Division – Marketing
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Table of Contents
Intel® Server Boards S5000PSL and S5000XSL TPS
Table of Contents
1. Introduction ........................................................................................................................12
Chapter Outline......................................................................................................12
Server Board Use Disclaimer ................................................................................12
2. Server Board Overview......................................................................................................14
Server Board Feature Set......................................................................................14
Server Board Layout..............................................................................................17
Server Board Mechanical Drawings ......................................................................20
Server Board ATX I/O Layout ................................................................................26
3. Functional Architecture.....................................................................................................27
System Bus Interface.............................................................................................29
Processor Support.................................................................................................29
Memory Sub-system..............................................................................................32
Snoop Filter (5000X MCH only).............................................................................41
Enterprise South Bridge (ESB2-E) ........................................................................41
PCI Sub-system.....................................................................................................42
Serial ATA Support................................................................................................44
Parallel ATA (PATA) Support ................................................................................45
USB 2.0 Support....................................................................................................45
Video Support........................................................................................................45
Video Modes..........................................................................................................47
Video Memory Interface.........................................................................................47
Dual Video .............................................................................................................47
SAS Controller.......................................................................................................48
SAS RAID Support ................................................................................................48
SAS / SATA Connector Sharing ............................................................................48
Network Interface Controller (NIC) ........................................................................48
Intel® I/O Acceleration Technolgy ..........................................................................49
MAC Address Definition.........................................................................................49
Super I/O ...............................................................................................................49
Serial Ports ............................................................................................................50
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Table of Contents
Floppy Disk Controller ...........................................................................................50
Keyboard and Mouse Support...............................................................................50
Wake-up Control....................................................................................................50
System Health Support..........................................................................................50
4. Platform Management........................................................................................................51
5. Connector / Header Locations and Pin-outs....................................................................53
Board Connector Information.................................................................................53
Power Connectors .................................................................................................54
System Management Headers ..............................................................................56
LCP / AUX IPMB Header.......................................................................................57
IPMB Header .........................................................................................................58
HSBP Header ........................................................................................................58
SGPIO Header.......................................................................................................58
SES I2C..................................................................................................................58
HDD Activity LED Header......................................................................................59
Front Panel Connector...........................................................................................59
I/O Connectors.......................................................................................................59
VGA Connector......................................................................................................59
NIC Connectors .....................................................................................................60
IDE Connector .......................................................................................................60
SATA / SAS Connectors........................................................................................63
Serial Port Connectors...........................................................................................63
Keyboard and Mouse Connector...........................................................................64
USB Connector......................................................................................................65
Fan Headers..........................................................................................................66
6. Jumper Blocks....................................................................................................................68
BMC Force Update Procedure ..............................................................................69
BIOS Select Jumper ..............................................................................................70
7. Intel® Light Guided Diagnostics........................................................................................71
5 Volt Standby LED ...............................................................................................71
Fan Fault LEDs......................................................................................................72
System ID LED and System Status LED ...............................................................73
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Table of Contents
Intel® Server Boards S5000PSL and S5000XSL TPS
System Status LED – BMC Initialization................................................................74
DIMM Fault LEDs ..................................................................................................76
Processor Fault LEDs............................................................................................77
Post Code Diagnostic LEDs ..................................................................................78
8. Design and Environmental Specifications.......................................................................79
Server Board Power Requirements .......................................................................80
Processor Power Support......................................................................................81
Power Supply Output Requirements .....................................................................81
Grounding..............................................................................................................82
Standby Outputs....................................................................................................82
Remote Sense.......................................................................................................82
Voltage Regulation ................................................................................................83
Dynamic Loading...................................................................................................83
Capacitive Loading ................................................................................................84
Ripple / Noise ........................................................................................................84
Timing Requirements.............................................................................................84
9. Regulatory and Certification Information.........................................................................88
Product Regulatory Compliance............................................................................88
Product Safety Compliance ...................................................................................88
Certifications / Registrations / Declarations...........................................................89
Product Regulatory Compliance Markings ............................................................89
Electromagnetic Compatibility Notices ..................................................................90
FCC Verification Statement (USA) ........................................................................90
ICES-003 (Canada) ...............................................................................................90
Europe (CE Declaration of Conformity) .................................................................91
VCCI (Japan).........................................................................................................91
BSMI (Taiwan).......................................................................................................91
RRL (Korea)...........................................................................................................91
CNCA (CCC-China)...............................................................................................92
Appendix A: Integration and Usage Tips................................................................................93
Appendix B: BMC Sensor Tables............................................................................................94
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Table of Contents
Appendix C: POST Code Diagnostic LED Decoder .............................................................109
Appendix D: POST Code Errors ............................................................................................114
Appendix E: Supported Intel® Server Chassis.....................................................................117
Glossary...................................................................................................................................118
Reference Documents............................................................................................................121
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List of Figures
Intel® Server Boards S5000PSL and S5000XSL TPS
List of Figures
Figure 1. Server Board Photograph............................................................................................17
Figure 2. Major Board Components............................................................................................19
Figure 3. Mounting Hole Positions..............................................................................................20
Figure 4. Component Positions...................................................................................................21
Figure 5. Restricted Areas on Side 1..........................................................................................22
Figure 6. Restricted Areas on Side 2..........................................................................................23
Figure 7. Restricted Areas on Side 2, “Detail B”.........................................................................24
Figure 8. CPU and Memory Duct Keepout .................................................................................25
Figure 9. ATX I/O Layout ............................................................................................................26
Figure 10. Functional Block Diagram..........................................................................................28
Figure 11. CEK Processor Mounting ..........................................................................................31
Figure 12. Memory Layout..........................................................................................................32
Figure 13. Minimum Two DIMM Memory Configuration..............................................................37
Figure 14. Recommended Four DIMM Configuration.................................................................38
Figure 15. Single Branch Mode Sparing DIMM Configuration....................................................40
Figure 16. SMBUS Block Diagram..............................................................................................52
Figure 17. Jumper Blocks (J1C3, J1D1, J1D2, J1E32) ..............................................................68
Figure 18. 5 Volt Standby Status LED Location..........................................................................71
Figure 19. Fan Fault LED Locations ...........................................................................................72
Figure 20. System ID LED and System Status LED Locations...................................................73
Figure 21. DIMM Fault LED Locations........................................................................................76
Figure 22. Processor Fault LED Locations .................................................................................77
Figure 23. POST Code Diagnostic LED Location.......................................................................78
Figure 24. Power Distribution Block Diagram .............................................................................80
Figure 25. Output Voltage Timing...............................................................................................85
Figure 26. Turn On/Off Timing (Power Supply Signals)..............................................................86
Figure 27. Diagnostic LED Placement Diagram .......................................................................109
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Intel® Server Boards S5000PSL and S5000XSL TPS
List of Tables
List of Tables
Table 1. Server Board Features..................................................................................................14
Table 2. Processor Support Matrix .............................................................................................29
Table 3. I2C Addresses for Memory Module SMB ......................................................................33
Table 6. PCI Bus Segment Characteristics.................................................................................42
Table 7. Video Modes.................................................................................................................47
Table 8. NIC2 Status LED...........................................................................................................48
Table 9. Serial B Header Pin-out ................................................................................................50
Table 10. Board Connector Matrix..............................................................................................53
Table 11. Power Connector Pin-out (J9B5) ................................................................................54
Table 12. 12 V Power Connector Pin-out (J3J2) ........................................................................55
Table 13. Power Supply Signal Connector Pin-out (J9D1).........................................................55
Table 14. P12V4 Power Connector Pin-out (J5A2) ....................................................................55
Table 15. RMM Connector Pin-out (J5B1)..................................................................................56
Table 16. LPC / AUX IPMB Header Pin-out (J2J1).....................................................................57
Table 17. IPMB Header Pin-out (J4J1).......................................................................................58
Table 18. HSBP Header Pin-out (J1J7, J1J2) ............................................................................58
Table 19. SGPIO Header Pin-out (J2H1, J1J5)..........................................................................58
Table 20. SES I2C Header Pin-out (J1J3)...................................................................................58
Table 21. HDD Activity LED Header Pin-out (J2J3)....................................................................59
Table 22. Front Panel SSI Standard 24-pin Connector Pin-out (J1E4) ......................................59
Table 23. VGA Connector Pin-out (J7A1)...................................................................................59
Table 24. RJ-45 10/100/1000 NIC Connector Pin-out (JA6A1, JA6A2)......................................60
Table 25. IDE 40-pin Connector Pin-out (J2J2)..........................................................................60
Table 26. 40-pin RMM NIC Module Connector Pin-out (J3B2)...................................................61
Table 28. External DB9 Serial A Port Pin-out (J7A1)..................................................................63
Table 29. Internal 9-pin Serial B Header Pin-out (J1B1).............................................................64
Table 30. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1) ...........................................64
Table 31. External USB Connector Pin-out (JA6A1, JA6A2)......................................................65
Table 32. Internal USB Connector Pin-out (J3J1).......................................................................65
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List of Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Table 33. SSI 4-pin Fan Header Pin-out (J9J1, J5J1, J9B3, J9B4)............................................66
Table 34. SSI 6-pin Fan Header Pin-out (J3H1, J3H2, J3H3, J3H4)..........................................66
Table 35. Server Board Jumpers (J1C3, J1D1, J1D2, J1E3) .....................................................68
Table 36. System Status LED.....................................................................................................74
Table 37. Server Board Design Specifications ...........................................................................79
Table 38. Intel® Xeon® Processor Dual Processor TDP Guidelines ...........................................81
Table 39. 550 W Load Ratings ...................................................................................................81
Table 40. Voltage Regulation Limits ...........................................................................................83
Table 41. Transient Load Requirements.....................................................................................83
Table 42. Capacitive Loading Conditions ...................................................................................84
Table 43. Ripple and Noise.........................................................................................................84
Table 44. Output Voltage Timing ................................................................................................85
Table 45. Turn On/Off Timing .....................................................................................................86
Table 46. BMC Sensors..............................................................................................................96
Table 47. POST Progress Code LED Example ........................................................................110
Table 48. Diagnostic LED POST Code Decoder ......................................................................110
Table 49. POST Error Messages and Handling........................................................................114
Table 50. POST Error Beep Codes ..........................................................................................116
Table 51. BMC Beep Codes .....................................................................................................116
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List of Tables
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Server Board Overview
Intel® Server Boards S5000PSL and S5000XSL TPS
1. Introduction
This Technical Product Specification (TPS) provides board-specific information about the features, functionality, and high-level
architecture of the Intel® Server Boards S5000PSL and S5000XSL. See the Intel® S5000 Server Board Family Datasheet for details
about board sub-systems, including the chipset, BIOS, and server management.
In addition, design level information for specific sub-systems can be obtained by ordering the External Product Specifications (EPS)
for a given sub-system. EPS documents are not publicly available and must be ordered through your local Intel representative.
1.1 Chapter Outline
This document is divided into the following chapters
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Chapter 1 – Introduction
Chapter 2 – Server Board Overview
Chapter 3 – Functional Architecture
Chapter 4 – Platform Management
Chapter 5 – Connector and Header Location and Pin-out
Chapter 6 – Configuration Jumpers
Chapter 7 – Light-Guided Diagnostics
Chapter 8 – Power and Environmental specifications
Chapter 9 – Regulatory and Certification Information
Appendix A – Integration and Usage Tips
Appendix B – BMC Sensor Tables
Appendix C – POST Code Diagnostic LED Decoder
Appendix D – POST Code Errors
Appendix E – Supported Intel® Server Chassis
1.2 Server Board Use Disclaimer
Intel Corporation server boards support add-in peripherals and contain a number of high-density VLSI and power delivery
components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server
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Intel® Server Boards S5000PSL and S5000XSL TPS
List of Tables
building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is
the responsibility of the system integrator who chooses not to use Intel-developed server building blocks to consult vendor
datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental
conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used
outside any of their published operating or non-operating limits.
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Server Board Overview
Intel® Server Boards S5000PSL and S5000XSL TPS
2. Server Board Overview
The Intel® Server Boards S5000PSL and S5000XSL are monolithic printed circuit boards with features that support the pedestal
server markets.
2.1 Server Board Feature Set
Table 1. Server Board Features
Feature
Processors
Description
Socket J (771-pin LGA sockets) supporting one or two Dual-Core Intel® Xeon®
processors 5000 sequence, with system bus speeds of 667 MHz, 1066 MHz, and
1333 MHz.
Memory
Chipset
Eight DIMM sockets supporting fully buffered DIMM technology (FBDIMM) memory.
240-pin DDR2-533 and DDR2-677 FBDIMMs can be used.
Intel® 5000P Memory Controller Hub (Server Board S5000PSL only)
Intel® 5000X Memory Controller Hub (Server Board S5000XSL only)
Intel® ESB2-E I/O Controller
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Intel® Server Boards S5000PSL and S5000XSL TPS
Feature
List of Tables
Description
On-board
External connections:
Connectors/Headers
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Stacked PS/2* ports for keyboard and mouse
Stacked video / DB9 serial port A connector
Two RJ45 / 2xUSB connectors for 10 / 100 / 1000 Mb and USB 2.0 support
One USB 2x5 pin header, which supports two USB ports
One USB port Type A connector
One DH10 serial port B header
Six SATA-2 connectors with integrated RAID 0, 1, and 10 support
(order code S5000PSLSATA only)
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Software RAID 5 support through an optional SATA RAID KEY (this feature is
currently not supported and will be made available after production launch)
Two SATA-2 connectors and four SATA-2 / SAS connectors with integrated RAID
0, 1, and 10 support (order code S5000PSLSAS only)
Software RAID 5 support through an optional SAS RAID KEY (order code
S5000PSLSAS only; this feature is currently not supported and will be made
available after production launch)
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One ATA100 40-pin connector
One RMM connector to support the optional Intel® Remote Management Module
One I/O connector supporting an optional RMM NIC I/O module
SSI-compliant front panel header
SSI-compliant 24-pin main power connector, supporting the ATX-12 V standard
on the first 20 pins
Add-in PCI, PCI-X*, PCI
Express* Cards
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One full-length / full-height PCI-X 64-bit slot with up to 133-MHz support when
only one PCI-X slot is populated
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One full-length / full-height PCI-X 64-bit slot with up to 100 MHz support
One full-length / full-height PCI Express* x8 (x4 throughput); x8 (x8 throughput)
with order code S5000PSLSATA) slot
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One half-length / full-height PCI Express* x8 (x8 throughput) slot
Two full-length / full-height PCI Express* x16 (x8 throughput) slots
Video
On-board ATI* ES1000 video controller with 16-MB DDR SDRAM
Support for six SATA-2 hard drives
Hard Drive
Support for four SAS hard drives (order code S5000PSLSAS only)
LAN
Two 10 / 100 / 1000 Intel® 82563EB PHYs supporting Intel® I/O Acceleration
Technology
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Server Board Overview
Intel® Server Boards S5000PSL and S5000XSL TPS
Feature
Description
Fans
Support for
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Two processor fans
Four front hot-swap fans
Two rear system fans
Server Management
Support for Intel® System Management Software
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Server Board Overview
Intel® Server Boards S5000PSL and S5000XSL TPS
2.2.1
Server Board Connector and Component Layout
The following figure shows the board layout of the server board. Each connector and major component is identified by a letter. A
table of component descriptions follows the figure.
G I
H J
K
L
A B C DE F
UU
TT
M
N
O
P
SS
RR
QQ
PP
OO
NN
MM
LL
Q
R
S
U
KK
T
JJ
II
HH
FF DD BB Z X V
GG EE CC AA Y W
AF000247
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Intel® Server Boards S5000PSL and S5000XSL TPS
List of Tables
A. PCI-X 64-bit, 100-MHz slot 1
B. PCI-X 64-bit, 133-/100-MHz slot 2
C. PCI Express* x4 / x8 slot 3
Q. DIMM sockets
GG. Enclosure management SAS
SGPIO header (order code
S5000PSLSAS only)
R. Processor 1 socket
HH. Enclosure management SAS
SES I2C (order code S5000PSLSAS
only)
S. Processor 2 socket
II. Hot-swap backplane A header
JJ. SATA 0
D. Advanced Server Management
Interface NIC connector
T. Processor 2 fan header
E. PCI Express* x4 slot 4 (ROMB
Slot)
U. Processor 1 fan header
V. System fan 4 header
W. System fan 3 header
X. IPMB connector
KK. SATA 1
F. PCI Express x8 slot 5
G. PCI Express x8 slot 6
H. CMOS battery
LL. SATA 2 or SAS 0 (SAS 0 on
order code S5000PSLSAS only)
MM. SATA 3 or SAS 1 (SAS 1 on
order code S5000PSLSAS only)
NN. SATA 4 or SAS 2 (SAS 2 on
order code S5000PSLSAS only)
I. P12V4 connector
Y. System fan 2 header
Z. System fan 1 header
OO. SATA 5 or SAS 3 (SAS 3 on
order code S5000PSLSAS only)
J. RMM connector (connector for
PP. USB port
Intel® Remote Management Module)
K. Back panel I/O ports
AA. Processor power connector
BB. USB header
QQ. Front control panel header
L. Diagnostic and identify LEDs
RR. SATA software RAID 5 key
connector
M. System fan 6 header
CC. IDE connector
SS. SAS software RAID 5 key
connector (order code
S5000PSLSAS only)
N. System fan 5 header
DD. Enclosure management SATA
SGPIO header
TT. Serial B / emergency
management port header
O. Main power connector
EE. Intel® Local Control Panel
header
UU. Chassis intrusion header
P. Auxilliary power signal connector
FF. Hot-swap backplane B header
Figure 2. Major Board Components
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Server Board Overview
Intel® Server Boards S5000PSL and S5000XSL TPS
304.80
[
12.000
]
11.20
0.441
[
]
HEATSINK DISSASEMBLY AREA,
.275" [8.26mm] MAX COMPONENT
HEIGHT RESTRICTION, 4 PLACES
116.000
60.100
2.3661
[
4.5669
]
[
]
18.72
0.737
TYP
20.32
[
]
[
0.800
]
TYP
IMM3 COMPONENT
HEIGHT 3.6 MM
Ø
10.160
0.4000
[
]
GROUND PAD BOTH SIDES
NO COMPONENT
8 PLCS
72.800
2.8661
[
]
.433" [14mm] MAX COMPONENT
HEIGHT RESTRICTION
301.50
[
11.870
TYP
]
SOCKET AREA, NO COMPONENT
PLACEMENT ALLOWED, 2 PLACES
311.66
[
12.270
TYP
]
322.40
[
12.693
TYP
]
326.57
[
12.857
TYP
]
330.20
13.000
[
]
93.98
[
3.700
]
6.35
0.250
[
]
60.96
22.86
[
2.400
]
5.33
3
[
0.210
]
TYP
7.92
0.312
[
]
.118" [3.81mm] MAX COMPONENT
HEIGHT RESTRICTION, 2 PLACES
TYP
16.05
0.632
[
]
TYP
HEATSINK AREA. .325" [8.26mm] MAX
COMPONENT HEIGHT RESTRICTIO, 2 PLACES
MAX HEIGHT OF COMPONENTS AND MATING COMPONENTS
SHALL NOT EXCEED 15.24mm [.600"]
Figure 5. Restricted Areas on Side 1
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Intel® Server Boards S5000PSL and S5000XSL TPS
List of Tables
LIMITED COMPONENT HEIGHT
.058" MAXIMUM 13 PLACES
2X 3.120
0.1228
[
]
78.74
[
3.100
]
7.620
TYP
20.320
[
0.3000
]
[
0.8000
]
SEE DETAIL B
20.320
[
0.8000
11 PLCS
]
3
2X 8.000
R 25.40
1.000
TYP
2X 0.350
0.0138
[
0.3150
]
[
]
[
]
NO COMPONENTS ALLOWED
TRACES OKAY IN THIS REGION
66.554
2.6202
5.08
[
]
[
0.200
]
TYP
R 14.730
TYP
[
0.5799
]
177.80
7.000
[
]
Ø
10.160
GROUND PAD
[
0.4000
]
NO COMPONENT
1 PLACE
.100 [2.54<<] MAX COMPONENT
HEIGHT IN THESE ZONES
2
96.52
[
3.800
]
57.15
[
2.250
]
12.07
[
0.475
]
7.62
0.300
[
]
12.70
5.08
[
0.500
]
[
0.200
]
5.08
17.78
0.700
NO COMPONENTS
THIS ZONE 16 PLCS
[
0.200
]
[
]
CEK HEATSINK SPRING PLATE ZONE
NO COMPONENT PLACEMENT OR
THROUGH HOLE LEADS ALLOWED
Figure 6. Restricted Areas on Side 2
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Server Board Overview
Intel® Server Boards S5000PSL and S5000XSL TPS
5.00
5.00
[ 0.197
]
[ 0.197
]
3X 4.00
[ 0.157
]
3X 3.00
[ 0.118
]
3X 10.13
[ 0.399
]
CHASSIS ID PADS
Figure 7. Restricted Areas on Side 2, “Detail B”
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Intel® Server Boards S5000PSL and S5000XSL TPS
List of Tables
10.160 [0.4000]
0.000 [0.0000]
14.0mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
26.635
[1.0486]
26.578 [1.0464]
43.302 [1.7048]
16.5mm COMPONENT HEIGHT
LIMIT DEFINE BY DUCT DETAIL
SUPPORT AREA,
NO COMPONENT
ALLOWED
73.482
[2.8930]
14.0mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
97.846
[3.8522]
1.25mm COMPONENT HEIGHT
LIMIT DEFINE BY DUCT DETAIL
SUPPORT AREA,
NO COMPONENT
ALLOWED
143.732
[5.6588]
143.136 [5.6353]
145.600 [5.7323]
154.685 [6.0900]
NO COMPONENT ALLOWED
168.123 [6.6190]
178.578 [7.0306]
15.0mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
235.085 [9.2553]
9.0 mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
282.585
[11.1254]
27.0 mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
13.0 mm COMPONENT HEIGHT
LIMIT DEFINED BY DUCT DETAIL
320.040
[12.6000]
317.580 [12.5032]
Figure 8. CPU and Memory Duct Keepout
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Server Board Overview
Intel® Server Boards S5000PSL and S5000XSL TPS
2.2.3
Server Board ATX I/O Layout
The drawing below shows the layout of the rear I/O components for the server board.
A
B
C
D
E
G
F
H
AF000222
A. PS/2 mouse
B. PS/2 keyboard
C. Serial port
D. Video
E. NIC port 1 (1 Gb)
F. USB port 2 (top), 3 (bottom)
G. NIC port 2 (1 Gb)
H. USB port 0 (top), 1 (bottom)
Figure 9. ATX I/O Layout
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3. Functional Architecture
The architecture and design of the Intel® Server Boards S5000PSL and S5000XSL are based on the Intel® S5000P and S5000X
chipsets respectively. These chipsets are designed for systems that use the Intel® Xeon® processor with system bus speeds of 667
MHz, 1066 MHz, and 1333 MHz.
The chipset contains two main components: the Memory Controller Hub (MCH) for the host bridge and the I/O controller hub for the
I/O sub-system. The chipset uses the Enterprise South Bridge (ESB2-E) for the I/O controller hub. This chapter provides a high-level
description of the functionality associated with each chipset component and the architectural blocks that make up the server board.
For more information about the functional architecture blocks, see the Intel® S5000 Server Board Family Datasheet.
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3.1 Intel® 5000P / 5000X Memory Controller Hub (MCH)
The Memory Controller Hub (MCH) is a single 1432-pin FCBGA package, which includes the following core platform functions:
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System Bus Interface for the processor sub-system
Memory Controller
PCI-Express Ports including the Enterprise South Bridge Interface (ESI)
FBD Thermal Management
SMBUS Interface
This section provides a high-level overview of some of these core functions as they pertain to this server board. Additional
information can be obtained from the Intel S5000 Server Board Family Datasheet and the Intel 5000 Series Chipset Memory
Controller Hub Datasheet.
3.1.1
System Bus Interface
The MCH is configured for symmetric multi-processing across two independent front side bus interfaces that connect to the Dual-
Core Intel® Xeon® processors. Each front side bus on the MCH uses a 64-bit wide 667, 1066, or 1333-MHz data bus. The 1333-MHz
data bus is capable of transferring data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of addressing up
to 64 GB of memory. The MCH is the priority agent for both front side bus interfaces, and is optimized for one processor on each
bus.
3.1.2
Processor Support
The server board supports one or two Dual Core Intel® Xeon® processors 5000 sequence, with system bus speeds of 667 MHz, 1066
MHz, and1333 MHz, and core frequencies starting at 3.73 GHz. Previous generations of the Intel® Xeon® processor are not
supported on this server board.
Note: Only Dual Core Intel® Xeon® processors 5000 Sequence that support system bus speeds of 667 MHz, 1066 MHz and 1333
MHz are supported on this server board. See the following table for a list of supported processors.
Table 2. Processor Support Matrix
Processor Family
System Bus Speed Core Frequency
667MHz 2.67 GHz
Cache
2x 2 MB
Watts
95
Support
Yes
Intel® Xeon® Processor 5030
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Intel® Xeon® Processor 5050
667 MHz
1066 MHz
1066 MHz
1066 MHz
1066 MHz
1066 MHz
1333
3.0 GHz
3.2 GHz
3.2 GHz
3.73 GHz
1.60
2x 2 MB
2x 2 MB
2x 2 MB
2x 2 MB
4 MB
95
130
95
130
65
65
65
65
40
65
80
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Intel® Xeon® Processor 5060
Intel® Xeon® Processor 5063
Intel® Xeon® Processor 5080
Intel® Xeon® Processor 5110
Intel® Xeon® Processor 5120
Intel® Xeon® Processor 5130
Intel® Xeon® Processor 5140
Intel® Xeon® Processor 5148
Intel® Xeon® Processor 5150
Intel® Xeon® Processor 5160
1.86
4 MB
2.00
4 MB
1333
2.33
4 MB
1333
2.33
4 MB
1333
2.66
4 MB
1333
3.00
4 MB
3.1.2.1
Processor Population Rules
When two processors are installed, both must be of identical revision, core voltage, and bus/core speed. When only one processor is
installed, it must be in the socket labeled CPU1. The other socket must be empty.
The board is designed to provide up to 130A of current per processor. Processors with higher current requirements are not
supported.
No terminator is required in the second processor socket when using a single processor configuration.
3.1.2.2
Common Enabling Kit (CEK) Design Support
The server board complies with Intel’s Common Enabling Kit (CEK) processor mounting and heatsink retention solution. The server
board ships with a CEK spring snapped onto the underside of the server board, beneath each processor socket. The heatsink
attaches to the CEK, over the top of the processor and the thermal interface material (TIM). See the figure below for the stacking
order of the chassis, CEK spring, server board, TIM, and heatsink.
The CEK spring is removable, allowing for the use of non-Intel heatsink retention solutions.
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Note: The processor heat sink and CEK spring shown in the following diagram are for reference purposes only. The actual
processor heat sink and CEK solutions compatible with this generation server board may be of a different design.
Heatsink assembly
Thermal Interface
Material (TIM)
Server Board
CEK Spring
Chassis
AF000196
Figure 11. CEK Processor Mounting
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3.1.3
Memory Sub-system
The MCH masters four fully buffered DIMM (FBD) memory channels. FBD memory utilizes a narrow high speed frame oriented
interface referred to as a channel. The four FBD channels are organized into two branches of two channels per branch. Each branch
is supported by a separate memory controller. The two channels on each branch operate in lock-step to increase FBD bandwidth.
The four channels are routed to sixteen DIMM sockets and are capable of supporting registered DDR2-533 and DDR2-667 FBDIMM
memory (stacked or unstacked). The read bandwidth of each FBDIMM channel 4.25 GB/s for DDR2-533 FBDIMM memory which
gives a total read bandwidth of 17 GB/s for four DIMM channels. The read bandwidth of each FBDIMM channel 5.35 GB/s for DDR2-
667 FBDIMM memory which gives a total read bandwidth of 21.4 GB/s for four DIMM channels.
On the Intel® Server Boards S5000PSL and S5000XSL, a pair of channels becomes a branch where Branch 0 consists of channels A
and B, and Branch 1 consists of channels C and D. FBD memory channels are organized into two branches for support of RAID 1
(mirroring).
Channel B
Channel A
Channel C
Channel D
Branch 0
Branch 1
TP02299
Figure 12. Memory Layout
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To boot the system, the system BIOS on the server board uses a dedicated I2C bus to retrieve DIMM information needed to program
the MCH memory registers. The following table provides the I2C addresses for each DIMM socket.
Table 3. I2C Addresses for Memory Module SMB
Device
Address
DIMM A1 0xA0
DIMM A2 0xA2
DIMM B1 0xA0
DIMM B2 0xA2
DIMM C1 0xA0
DIMM C2 0xA2
DIMM D1 0xA0
DIMM D2 0xA2
3.1.3.1
Memory RASUM Features
The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features. These
features include the Intel® x4 Single Device Data Correction (Intel® x4 SDDC) for the following:
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Memory error detection and correction
Memory scrubbing
Retry on correctable errors
Memory built-in self-test
DIMM sparing
Memory mirroring
See the Intel® S5000 Server Board Family Datasheet for more information about these features.
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3.1.3.2
Supported Memory
The server board supports up to eight DDR2-533 or DDR2-667 fully-buffered DIMMs (FBD memory). The following tables show the
maximum memory configurations supported with the specified memory technology.
Table 4. Maximum Eight-DIMM System Memory Configruation – x8 Single Rank
DRAM Technology
x8 Single Rank
256 Mb
Maximum Capacity
Mirrored Mode
1 GB
Maximum Capacity
Non-mirrored Mode
2 GB
512 Mb
2 GB
4 GB
8 GB
4 GB
8 GB
16 GB
1024 Mb
2048 Mb
Table 5. Maximum Eight-DIMM System Memory Configuration – x4 Dual Rank
DRAM Technology
x4 Dual Rank
256 Mb
Maximum Capacity
Mirrored Mode
4 GB
Maximum Capacity
Non-mirrored Mode
8 GB
512 Mb
8 GB
16 GB
32 GB
32 GB
1024 Mb
2048 Mb
16 GB
16 GB
Note: Only fully buffered DDR2 DIMMs (FBDIMMs) are supported on this server board. See the Intel® Server Board
S5000PSL/S5000XSL Tested Memory List for a list of supported memory for this server board.
3.1.3.3
DIMM Population Rules and Supported DIMM Configurations
DIMM population rules depend on the operating mode of the memory controller, which is determined by the number of DIMMs
installed. DIMMs must be populated in pairs. DIMM pairs are populated in the following DIMM slot order: A1 & B1, C1 & D1, A2 &
B2, C2 & D2. DIMMs within a given pair must be identical with respect to size, speed, and organization. However, DIMM capacities
can be different between different DIMM pairs.
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For example, a valid mixed DIMM configuration may have 512MB DIMMs installed in DIMM Slots A1 & B1, and 1GB DIMMs installed
in DIMM slots C1 & D1.
Intel supported DIMM configurations for this server board are shown in the following table.
Supported and Validated configuration : Slot is populated
Supported but not validated configuration : Slot is
populated
Slot is not populated
Mirroring: Y = Yes. Indicates that configuration supports Memory Mirroring.
Sparing:
Y(x) = Yes. Indicates that configuration supports Memory Sparing.
Where x = 0 : Sparing supported on Branch0 only
1 : Sparing supported on Branch1 only
0,1 : Sparing supported on both branches
Branch 0
Branch 1
Mirroring
Possible
Sparing
Possible
Channel A
Channel B
DIMM_B1 DIMM B2
Channel C
DIMM C1 DIMM C2
Channel D
DIMM D1 DIMM D2
DIMM_A1
DIMM_A2
Y (0)
Y
Y
Y (0)
Y (0, 1)
Notes:
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Single channel mode is only tested and supported with a 512MB x8 FBDIMM installed in DIMM Slot A1.
The supported memory configurations must meet population rules defined above.
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-
For best performance, the number of DIMMs installed should be balanced across both memory branches. For Example: a four
DIMM configuration will perform better than a two DIMM configuration and should be installed in DIMM Slots A1, B1, C1, and D1.
An eight DIMM configuration will perform better then a six DIMM configuration.
Although mixed DIMM capacities between channels is supported, Intel does not validate DIMMs in mixed DIMM configurations.
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3.1.3.3.1
Minimum Non-Mirrored Mode Configuration
The server board is capable of supporting a minimum of one DIMM installed. However, for
system performance reasons, Intel’s recommendation is that at least 2 DIMMs be installed.
The following diagram shows the recommended minimum DIMM memory configuration.
Populated DIMM slots are shown in Grey.
Channel B
Channel A
Channel C
Channel D
Branch 0
Branch 1
TP02300
Figure 13. Minimum Two DIMM Memory Configuration
Note: The server board supports single DIMM mode operation. Intel will only validate and
support this configuration with a single 512 MB x8 FBDIMM installed in DIMM socket A1.
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3.1.3.4
Non-mirrored Mode Memory Upgrades
The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must cover the
same slot position on both channels. DIMMs pairs must be identical with respect to size, speed,
and organization. DIMMs that cover adjacent slot positions do not need to be identical.
populated in DIMM sockets C1 and D1 as shown in the following diagram. Populated DIMM
sockets are shown in Grey.
Channel B
Channel A
Channel C
Channel D
Branch 0
Branch 1
TP02301
Figure 14. Recommended Four DIMM Configuration
Functionally, DIMM sockets A2 and B2 could also have been populated instead of DIMM
on the previous page, shows the supported DIMM configuration that is recommended because it
allows both branches to operate independently and simultaneously. FBD bandwidth is doubled
when both branches operate in parallel.
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3.1.3.4.1
Mirrored Mode Memory Configuration
When operating in mirrored mode, both branches operate in lock step. In mirrored mode, branch
1 contains a replicate copy of the data in branch 0. The minimum DIMM configuration to support
be identical with respect to size, speed, and organization.
To upgrade a four DIMM mirrored memory configuration, four additional DIMMs must be added
to the system. All four DIMMs in the second set must be identical to the first with the exception
of speed. The MCH will adjust to the lowest speed DIMM.
3.1.3.4.2
Sparing Mode Memory Configuration
The MCH provides memory sparing capabilities. Sparing is a RAS feature that involves
configuring a DIMM to be placed in reserve so it can be use to replace a DIMM that fails. DIMM
sparing occurs within a given bank of memory and is not supported across branches. There are
two supported Memory Sparing configurations.
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Single Branch Mode Sparing
Dual Branch Mode Sparing
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3.1.3.4.2.1
Single Branch Mode Sparing
DIMM_A2
DIMM_A1
DIMM_B2
DIMM_B1
DIMM_C2
DIMM_C1
DIMM_D2
DIMM_D1
Slot 2
Slot 1
Channel A
Channel B
Channel C
Channel D
Branch 0
Branch 1
Intel® 5000P/5000X Memory Controller Hub
Figure 15. Single Branch Mode Sparing DIMM Configuration
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DIMM_A1 and DIMM_B1 must be identical in organization, size and speed.
DIMM_A2 and DIMM_B2 must be identical in organization, size and speed.
DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed.
DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed.
Sparing should be enabled in BIOS setup.
The BIOS will configure Rank Sparing Mode.
The larger of the pairs {DIMM_A1, DIMM_B1} and {DIMM_A2, DIMM_B2} will be
selected as the spare pair unit.
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3.1.3.4.2.2
Dual Branch Mode Sparing
Dual branch mode sparing requires that all eight DIMM sockets be populated and must comply
with the following population rules.
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DIMM_A1 and DIMM_B1 must be identical in organization, size and speed.
DIMM_A2 and DIMM_B2 must be identical in organization, size and speed.
DIMM_C1 and DIMM_D1 must be identical in organization, size and speed.
DIMM_C2 and DIMM_D2 must be identical in organization, size and speed.
DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed.
DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed.
DIMM_C1 and DIMM_C2 need not be identical in organization, size and speed.
DIMM_D1 and DIMM_D2 need not be identical in organization, size and speed.
Sparing should be enabled in BIOS setup.
The BIOS will configure Rank Sparing Mode.
The larger of the pairs {DIMM_A1, DIMM_B1}, {DIMM_A2, DIMM_B2},
{DIMM_C1, DIMM_D1}, and {DIMM_C2, DIMM_D2} are selected as the spare pair units.
3.1.4
Snoop Filter (5000X MCH only)
The 5000X version of the MCH includes a snoop filter. Depending on the application of the
server, this feature can be used to enhance the performance of the server by eliminating traffic
on the snooped system bus of the processor being snooped. By removing snoops form the
snooped bus, the full bandwidth is available for other transactions.
3.2 Enterprise South Bridge (ESB2-E)
The ESB2-E is a multi-function device that provides four distinct functions: an I/O controller, a
PCI-X* bridge, a GB Ethernet controller, and a baseboard management controller (BMC). Each
function has its own set of configuration registers. Once configured, each appears to the system
as a distinct hardware controller.
The ESB2-E provides the gateway to all PC-compatible I/O devices and features. The server
boards use the following ESB2-E features:
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PCI-X bus interface
Six-channel SATA interface with SATA Busy LED Control
Dual GbE MAC
Baseboard Management Controller (BMC)
Single ATA interface, with Ultra DMA 100 capability
Universal Serial Bus 2.0 (USB) interface
Removable media drives
LPC bus interface
PC-compatible timer/counter and DMA controllers
APIC and 8259 interrupt controller
Power management
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System RTC
General purpose I/O
This section describes the function of most of the listed features as they pertain to these server
boards. For more detail information, see the Intel S5000 Server Board Family Datasheet or the
Intel 631xESB/632xESB I/O Controller Hub Datasheet.
3.2.1
PCI Sub-system
The primary I/O buses for the server board are PCI, PCI Express*, and PCI-X,* with six
independent PCI bus segments. The PCI buses comply with the PCI Local Bus Specification,
Revision 2.3. The table below lists the characteristics of the PCI bus segments. Details about
each bus segment follow the table.
Table 6. PCI Bus Segment Characteristics
PCI Bus Segment
PCI32
Voltage
3.3 V
Width
32 bit
Speed
33 MHz
Type
PCI
PCI I/O Card Slots
None. Used internally for video controller
ESB2-E
PXA
3.3 V / 5.0 V 64 bit
3.3 V / 5.0 V 64 bit
100 MHz PCI-X*
133 MHz PCI-X*
PCI-X Slot 1
PCI-X Slot 2
ESB2-E
PXA
ESB2-E
PE0
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
X4
X4
X4
X8
X8
10 Gb/S
10 Gb/S
10 Gb/S
20 Gb/S
20 Gb/S
PCI
Express*
X4 throughput PCI Express* Slot 4 (ROMB
Slot)
ESB2-E PCI
Express* Port0
PE1
PCI
Express
x4 throughput PCI Express* Slot 3 (x8
throughput for server boards that do not
support SAS by combining PE2 with PE1)
ESB2-E PCI
Express* Port1
PE2
PCI
Express
x4 throughput to onboard SAS (re-routed
to Slot 3 for server boards that do not
support SAS)
ESB2-E PCI
Express* Port2
PE4, PE5
PCI
Express
X8 throughput PCI Express* Slot 5
BNB PCI Express*
Ports 4, 5
PE6, PE7
PCI
X8 throughput PCI Express* Slot 6
Express
BNB PCI Express*
Ports 6, 7
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3.2.1.1
PCI32: 32-bit, 33-MHz PCI Sub-system
All 32-bit, 33-MHz PCI I/O is directed through the ESB2-E ICH6. The 32-bit, 33-MHz PCI
segment created by the ESB2-E-ICH6 is known as the PCI32 segment. The PCI32 segment
supports the following embedded devices:
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2D Graphics Accelerator: ATI* ES1000 Video Controller
3.2.1.2
PXA: 64-bit, 133-MHz PCI Sub-system
One 64-bit PCI-X bus segment is directed through the ESB2-E ICH6. This PCI-X segment, PXA,
is routed to PCI-X Slots 1 and 2. With only one PCI-X adapter populated in Slot 2 and Slot 1 left
empty, PCI-X Slot 2 supports a maximum speed of 133MHz. With both Slot 1 and Slot 2
populated, Slot 2 supports a maximum speed of 100MHz. PCI-X Slot 1 supports a maximum
speed of 100MHz even when Slot 2 is not populated.
3.2.1.3
PE0: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment,
PE0, is routed to PCI Express* Slot 4 (ROMB Slot).
3.2.1.4
PE1: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment,
PE1, is routed to PCI Express* Slot 3. This becomes a x8 PCI Express* bus segment for server
boards that do not support SAS by combining PE2 with PE1.
3.2.1.5
PE2: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment,
PE2, is routed to PCI Express* Slot 3 for server boards that do not support SAS, or to the
onboard SAS controller for server boards that do support SAS.
3.2.1.6
PE4, PE5: Two x4 PCI Express* Bus Segments
Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express*
segments, PE4 and PE5, are routed to PCI Express* Slot 5.
3.2.1.7
PE6, PE7: Two x4 PCI Express* Bus Segments
Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express*
segments, PE6 and PE7, are routed to PCI Express* Slot 6.
3.2.1.8
PCI Express* Riser Slot
PCI Express* Slot 6 supports 3rd party riser cards for both 1U and 2U system configurations.
Two PCI Express* pins are designated as Riser Type pins with the definitions noted in the table
below.
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1
LP Riser TYPE 1
ESB2 GPI 28
LP Riser Type 0
GPI: ESB2 GPI 27
SLOT 6 SETUP
GPI:
PCI-E Pin: B48 [RSVD]
PCI-E Pin: B49 [GND]
2U Riser, 2 x4 PCI Express* Slots2
1U Riser, 1 x8 PCI Express* Slot3
Notes:
0
1
1
0
1
2
The server board contains a weak pull-up resistor on the two Riser Type nets.
The 2U riser card needs to pull-down the PCI Express* pin B48 with a 0 ohm resistor
and leave as a No-Connect (NC) PCI Express* pin B49.
3
The 1U riser card needs to follow the standard PCI Express* Adapter pin-out by leaving
pin B48 as a No-Connect (NC) and pin B49 as ground.
The following table provides the supported bus throughput for the given riser card used and the
number of add-in cards installed.
PCI Express* Slot 6 Riser
Support
1 add-in card
2 add-in cards
1U Riser Card
2U Riser Card
X8
X4
NA
X4
Note: There are no population rules for installing a single add-in card in the 2U riser card; a
single add in card can be installed in either PCI Express* slot.
3.2.2
Serial ATA Support
The ESB2-E has an integrated Serial ATA (SATA) controller that supports independent DMA
operation on six ports and supports data transfer rates of up to 3.0 Gb/s. The six SATA ports on
the server board are numbered SATA-0 thru SATA-5. The SATA ports can be enabled/disabled
and/or configured by accessing the BIOS Setup utility during POST.
3.2.2.1
Intel® Embedded Server RAID Technology II Support
The onboard storage capability of this server board includes support for Intel® Embedded
Server RAID Technology which provides three standard software RAID levels: data stripping
(RAID Level 0), data mirroring (RAID Level 1), and data stripping with mirroring (RAID Level
10). For higher performance, data stripping can be used to alleviate disk bottlenecks by taking
advantage of the dual independent DMA engines that each SATA port offers. Data mirroring is
used for data security. Should a disk fail, a mirrored copy of the failed disk is brought on-line.
There is no loss of either PCI resources (request/grant pair) or add-in card slots.
With the addition of an optional Intel RAID Activation Key, Intel® Embedded Server RAID
Technology is also capable of providing fault tolerant data stripping (software RAID Level 5),
such that if a SATA hard drive should fail, the lost data can be restored on a replacement drive
from the other drives that make up the RAID 5 pack.
See Figure 2 Major Board Components for the location of Intel RAID Activation Key connector
location.
Note: Availability of the Intel RAID Activation Key to support software RAID 5 will be deferred
until after product launch of this server board.
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Intel® Embedded Server RAID Technology functionality requires the following items:
•
•
•
•
Intel® ESB-2 IO Controller Hub
Intel® Embedded Server RAID Technology Option ROM
Intel® Embedded Server RAID Technology II drivers, most recent revision
At least two SATA hard disk drives
Intel® Embedded Server RAID Technology is not available in the following configurations:
•
•
The SATA controller in compatible mode
Intel® Embedded Server RAID Technology II has been disabled
3.2.2.2
Intel® Embedded Server RAID Technology Option ROM
The Intel® Embedded Server RAID Technology for SATA Option ROM provides a pre-OS user
interface for the Intel® Embedded Server RAID Technology implementation and provides the
ability for an Intel® Embedded Server RAID Technology volume to be used as a boot disk as
well as to detect any faults in the Intel® Embedded Server RAID Technology volume(s) attached
to the Intel® RAID controller.
3.2.3
Parallel ATA (PATA) Support
The integrated IDE controller of the ESB2-E ICH6 provides one IDE channel. It redefines
signals on the IDE cable to allow both host and target throttling of data and transfer rates of up
to 100 MB/s. For this server board, the IDE channel was designed to provide optical drive
support to the platform. The BIOS initializes and supports ATAPI devices such as LS-120/240,
CD-ROM, CD-RW and DVD-ROM. The IDE channel is accessed through a single standard 40-
pin IDE connector (J2J2) that provides the I/O signals. The ATA channel can be configured and
enabled or disabled by accessing the BIOS Setup utility during POST.
3.2.4
USB 2.0 Support
The USB controller functionality integrated into ESB2-E provides the server board with the
interface for up to eight USB 2.0 ports. Four external connectors are located on the back edge
of the server board. One internal 2x5 header (J3J1) is provided, capable of supporting two
optional USB 2.0 ports. One USB port Type A connector (J3G1) is provided to support
installation of a USB device inside the server chassis. An additional USB port is dedicated to the
Intel® Remote Management Module (Intel® RMM) connector.
3.3 Video Support
The server board provides an ATI* ES1000 PCI graphics accelerator, along with 16 MB of video
DDR SDRAM and support circuitry for an embedded SVGA video sub-system. The ATI ES1000
chip contains an SVGA video controller, clock generator, 2D engine, and RAMDAC in a 359-pin
BGA. One 4M x 16 x 4-bank DDR SDRAM chip provides 16 MB of video memory.
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The SVGA sub-system supports a variety of modes, up to 1024 x 768 resolution in 8 / 16 /
32 bpp modes under 2D. It also supports both CRT and LCD monitors up to a 100 Hz vertical
refresh rate.
Video is accessed using a standard 15-pin VGA connector found on the back edge of the server
board. The on-board video controller can be disabled using the BIOS Setup Utility or when an
add-in video card is installed. The system BIOS provides the option for dual-video operation
when an add-in video card is configured in the system.
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3.3.1
Video Modes
The ATI* ES1000 chip supports all standard IBM* VGA modes. The following table shows the
2D modes supported for both CRT and LCD.
Table 7. Video Modes
2D Mode
640x480
Refresh Rate (Hz)
2D Video Mode Support
16 bpp
8 bpp
Supported
32 bpp
60, 72, 75, 85, 90,
100, 120, 160, 200
Supported
Supported
Supported
Supported
Supported
Supported
800x600
60, 70, 72, 75, 85,
90, 100, 120,160
Supported
Supported
1024x768
60, 70, 72,
75,85,90,100
1152x864
1280x1024
1600x1200
43,47,60,70,75,80,85 Supported
Supported
Supported
Supported
Supported
Supported
Supported
60,70,74,75
52
Supported
Supported
3.3.2
Video Memory Interface
The memory controller sub-system of the ES1000 arbitrates requests from the direct memory
interface, the VGA graphics controller, the drawing co-processor, the display controller, the
video scalar, and the hardware cursor. Requests are serviced in a manner that ensures display
integrity and maximum CPU/co-processor drawing performance.
The server board supports a 16 MB (4 Meg x 16-bit x 4 banks) DDR SDRAM device for video
memory.
3.3.3
Dual Video
The BIOS supports single- and dual-video modes. The dual-video mode is enabled by default.
ƒ
ƒ
In single mode (Dual Monitor Video = disabled), the on-board video controller is disabled
when an add-in video card is detected.
In dual mode (On-board Video = enabled, Dual Monitor Video = enabled), the on-board
video controller is enabled and will be the primary video device. The external video card
will be allocated resources and is considered the secondary video device. The BIOS
Setup utility provides options to configure the feature as follows.
On-board Video
Enabled
Disabled
Enabled
Disabled
Dual Monitor Video
Shaded if on-board video is set to "Disabled"
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3.4 SAS Controller
The SAS1064e controller supports x4 PCI Express* link widths and is a single-function PCI
Express end-point device. The SAS controller supports the SAS protocol as described in the
Serial Attached SCSI Standard, version 1.0. The controller also supports SAS 1.1 features.
The SAS1064e controller supports a 32-bit external memory bus that provides an interface for
Flash ROM and NVSRAM devices.
3.4.1
SAS RAID Support
RAID modes 0, 1, and 10 are supported. An optional SAS RAID Key can be used to support SW
RAID 5.
3.4.2
SAS / SATA Connector Sharing
Four SATA connectors are shared between SATA and SAS, depending on the version of the
server board. For SAS server boards, four of the six SATA connectors are used for SAS
functionality. For SATA server boards, all six SATA connectors are used for SATA functionality.
3.5 Network Interface Controller (NIC)
Network interface support is provided from the built in Dual GbE MAC features of the ESB2 in
conjunction with the Intel® 82563EB compact Physical Layer Transceiver (PHY). Together, they
provide the server board with support for dual LAN ports designed for 10/100/1000 Mbps
operation.
The 82563EB device is based upon proven PHY technology integrated into Intel’s gigabit
Ethernet controllers. The physical layer circuitry provides a standard IEEE 802.3 Ethernet
interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and
802.3ab). The 82563EB device is capable of transmitting and receiving data at rates of
1000 Mbps, 100 Mbps, or 10 Mbps.
Each network interface controller (NIC) drives two LEDs located on each network interface
connector. The link / activity LED (at the right of the connector) indicates network connection
when on, and transmit / receive activity when blinking. The speed LED (at the left of the
connector) indicates 1000-Mbps operation when amber, 100-Mbps operation when green, and
10-Mbps when off. The table below provides an overview of the LEDs.
Table 8. NIC2 Status LED
LED Color
LED State
NIC State
Off
10 Mbps
Green/Amber (Left)
Green
Amber
On
100 Mbps
1000 Mbps
Active Connection
Green (Right)
Blinking
Transmit / Receive activity
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3.5.1
Intel® I/O Acceleration Technolgy
Intel® I/O Acceleration Technology moves network data more efficiently through Dual-Core
Intel® Xeon® processor 5000 sequence-based servers for improved application responsiveness
across diverse operating systems and virtualized environments. Intel® I/OAT improves network
application responsiveness by unleashing the power of Dual-Core Intel® Xeon® processors 5000
sequence through more efficient network data movement and reduced system overhead. Intel
multi-port network adapters with Intel® I/OAT provide high-performance I/O for server
consolidation and virtualization via stateless network acceleration that seamlessly scales across
multiple ports and virtual machines. Intel® I/OAT provides safe and flexible network acceleration
through tight integration into popular operating systems & virtual machine monitors, avoiding the
support risks of 3rd-party network stacks and preserving existing network requirements such as
teaming and failover.
3.5.2
MAC Address Definition
Each Intel® Server Board S5000PSL / S5000XSL has four MAC addresses assigned to it at the
Intel factory. During the manufacturing process, each server board will have a white MAC
address sticker placed on the board. The sticker will display the MAC address in both bar code
and alpha numeric formats. The printed MAC address is assigned to NIC 1 on the server board.
NIC 2 is assigned the NIC 1 MAC address + 1.
Two additional MAC addresses are assigned to the Baseboard Management Controller (BMC)
embedded in the ESB-2. These MAC addresses are used by the BMC’s embedded network
stack to enable IPMI remote management over LAN. BMC LAN Channel 1 is assigned the NIC1
MAC address + 2, and BMC LAN Channel 2 is assigned the NIC1 MAC address + 3
3.6 Super I/O
Legacy I/O support is provided by using a National Semiconductor* PC87427 Super I/O device.
This chip contains all of the necessary circuitry to support the following functions:
ƒ
ƒ
ƒ
ƒ
ƒ
GPIOs
Two serial ports
Keyboard and mouse support
Wake up control
System health support
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3.6.1
Serial Ports
The server board provides two serial ports: an external DB9 serial port and an internal DH10
serial header. The rear DB9 serial A port is a fully-functional serial port that can support any
standard serial device.
Serial B is an optional port that is accessed through a 9-pin internal DH-10 header. A standard
DH10 to DB9 cable can be used to direct serial B to the rear of a chassis. The serial B interface
follows the standard RS232 pin-out as defined in the following table.
Table 9. Serial B Header Pin-out
Pin
Signal Name
Serial Port B Header Pin-out
1
2
3
4
5
6
7
8
9
DCD
DSR
RX
RTS
TX
CTS
DTR
RI
GND
3.6.2
Floppy Disk Controller
The server board does not support a floppy disk controller interface. However, the system BIOS
recognizes USB floppy devices.
3.6.3
Keyboard and Mouse Support
Dual-stacked PS/2* ports are provided on the back edge of the server board for keyboard and
mouse support. Either port can support a mouse or keyboard. Neither port supports hot
plugging.
3.6.4
Wake-up Control
The super I/O contains functionality that allows various events to power on and power off the
system.
3.6.5
System Health Support
The super I/O provides an interface via GPIOs for BIOS and system management firmware to
activate the diagnostic LEDs, the FRU fault indicator LEDs for processors, FBDIMMS, fans and
The super I/O provides PMW fan control to the system fans, monitors tach and presence signals
for the system fans and monitors server board and front panel temperature.
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Design and Environmental Specifications
4. Platform Management
The platform management sub-system is based on the integrated Baseboard Management
Controller features of the ESB2-E. The on-board platform management sub-system consists of
communication buses, sensors, system BIOS, and server management firmware. The following
diagram provides an overview of the Server Management Bus (SMBUS) architecture used on
this server board.
See Appendix B for on-board sensor data.
For more detailed platform management information, see the Intel® S5000 Server Board Family
Datasheet.
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5. Connector / Header Locations and Pin-outs
5.1 Board Connector Information
The following section provides detailed information regarding all connectors, headers and
jumpers on the server board. Table 10. Board Connector Matrix
lists all connector types available on the board and the corresponding reference designators
printed on the silkscreen.
Table 10. Board Connector Matrix
Connector
Quantity
Reference Designators
Connector Type
Pin
Count
Power supply
4
J9B5
Main power
CPU power
P/S aux / IPMB
P12V4 power
CPU sockets
DIMM sockets
Card edge
24
J3J2
8
J9D1
5
J5A2
4
CPU
2
8
2
2
2
1
1
2
1
4
2
2
1
1
2
J8G1, J5G1
771
240
Main memory
PCI-X
J7B1, J7B2, J7B3, J8B1, J8B2, J8B3, J9B1, J9B2
J1B2, J2B1
J2B2, J3B1
J4B2, J4B1
J5B1
PCI Express* x8
PCI Express* x16
Intel® RMM
RMM NIC
Card edge
Card edge
Mezzanine
Mezzanine
Key holder
120
40
3
J3B2
RAID Key
J1E1, J1D3
J2J2
IDE
Shrouded header 40
System fans
System fans
CPU fans
J3H1, J3H2, J3H3, J3H4
J9B3, J9B4
J9J1, J5J1
XBT4D1
Header
6
Header
4
Header
4
Battery
Battery holder
PS2, stacked
3
Keyboard / mouse
J9A1
12
22
Stacked RJ45 /
2xUSB
JA6A1, JA6A2
External LAN
built-in magnetic
and dual USB
Stacked video /
verial port A
1
J7A1
External DSub /
DB9
24
Serial port B
Front panel
Internal USB
Internal USB
1
1
1
1
J1B1
J1E4
J3J1
J3G1
Header
Header
Header
10
24
10
4
Type A
connector
Chassis Intrusion
Serial ATA / SAS
HSBP / SGPIO
SES I2C
1
6
4
1
J1A1
Header
Header
Header
Header
2
7
4
3
J1G1, J1F2, J1H1, J1G2, J1J1, J1H2
J1J2, J1J7, J2H1, J1J5
J1J3
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Connector
Quantity
Reference Designators
Connector Type
Pin
Count
LCP/AUX IPMB
IPMB
1
1
1
4
J2J1
J4J1
J2J3
Header
Header
Header
Jumper
4
3
2
3
HDD Activity
Configuration
jumpers
J1D2 (Password Clear), J1D1 (CMOS Clear), J1C3
(BIOS Bank Select), J1E3 (BMC Force Update)
5.2 Power Connectors
The main power supply connection uses an SSI-compliant 2x12 pin connector (J9B5). In
addition, there are three additional power related connectors:
ƒ
ƒ
ƒ
One SSI-compliant 2x4 pin power connector (J3J2) provides 12V power to the CPU
Voltage Regulators
One SSI-compliant 1x5 pin connector (J9D1) provides I2C monitoring of the power
supply
One SSI-compliant 2x2 pin connector (J5A2) provides additional 12V power to the
server board
The following tables define the connector pin-outs.
Table 11. Power Connector Pin-out (J9B5)
Pin
Signal
Color
Pin
13
Signal
Color
1
+3.3 Vdc
Orange
+3.3 Vdc
Orange
2
+3.3 Vdc
GND
Orange
Black
Red
14
15
16
17
18
19
20
21
22
23
24
-12 Vdc
GND
Blue
3
Black
Green
Black
Black
Black
White
Red
4
+5 Vdc
GND
PS_ON#
GND
5
Black
Red
6
+5 Vdc
GND
GND
7
Black
Gray
GND
8
PWR_OK
5 VSB
RSVD_(-5 V)
+5 Vdc
+5 Vdc
+5 Vdc
GND
9
Purple
Yellow
Yellow
Orange
10
11
12
+12 Vdc
+12 Vdc
+3.3 Vdc
Red
Red
Black
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Table 12. 12 V Power Connector Pin-out (J3J2)
Pin
1
Signal
GND
Color
Black
2
3
4
5
6
7
8
GND
Black
GND
Black
GND
Black
+12 Vdc
+12 Vdc
+12 Vdc
+12 Vdc
Yellow / black
Yellow / black
Yellow / black
Yellow / black
Table 13. Power Supply Signal Connector Pin-out (J9D1)
Pin
1
Signal
Color
Orange
SMB_CLK_ESB_FP_PWR_R
2
3
4
5
SMB_DAT_ESB_FP_PWR_R
SMB_ALRT_3_ESB_R
3.3 V SENSE-
Black
Red
Yellow
Green
3.3 V SENSE+
Table 14. P12V4 Power Connector Pin-out (J5A2)
Pin
Signal
Color
1
GND
Black
2
3
4
GND
Black
+12 Vdc
+12 Vdc
Yellow / black
Yellow / black
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5.3 System Management Headers
5.3.1
Intel® Remote Management Module (Intel® RMM) Connector
A 120-pin Intel® RMM connector (J5B1) is included on the server board to support the optional
Intel® Remote Management Module. There is no support for third party ASMI cards on this
server board.
Note: This connector is not compatible with the Intel® Server Management Module Professional
Edition (Product Code AXXIMMPRO) or the Intel® Server Management Module Advanced
Edition (Product Code AXXIMMADV).
Table 15. RMM Connector Pin-out (J5B1)
Pin
Signal Name
Pin
Signal Name
1
Reserved - NC
2
GND
3
ESB_PLT_RST_G1_N
GND
4
Reserved - NC
Reserved - NC
GND
5
6
7
Reserved - NC
Reserved - NC
GND
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
56
60
GND
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
Reserved - NC
IRQ_SERIAL_R
GND
GND
USB_ESB_P7P
USB_ESB_P7N
GND
GND
Reserved - NC
Reserved - NC
GND
P3V3
LPC_LAD<0>
LPC_LAD<1>
P3V3
LPC_FRAME_N
LPC_LAD<2>
LPC_LCLK
LPC_LAD<3>
P3V3
P3V3
SMB_1_3V3SB_MS_DAT
SMB_1_3V3SB_SL_DAT
SMB_1_3V3SB_MS_CLK
SMB_1_3V3SB_INT
P3V3_AUX
SMB_IPMB_3V3SB_DAT
SMB_IPMB_3V3SB_CLK
SMB_0_3V3SB_MS_CLK
SMB_0_3V3SB_INT
SMB_0_3V3SB_MS_DAT
SMB_0_3V3SB_SL_DAT
P3V3_AUX
SPB_IMM_DSR_N
SPB_IMM_RTS_N
SPB_IMM_CTS_N
SPB_IMM_DCD_N
SPB_RI_N
FM_IMM_PRESENT_N
SPB_IMM_DTR_N
SPB_IMM_SIN
P3V3_AUX
SPB_IMM_SOUT
P3V3_AUX
V_LCDDATA7
V_LCDDATA6
V_LCDDATA5
V_LCDCNTL3
P3V3_AUX
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Pin
Signal Name
Pin
Signal Name
61
Reserved - NC
62
V_LCDDATA4
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Reserved - NC
GND
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
V_LCDDATA3
V_LCDCNTL1
GND
V_LCDCNTL0
Reserved - NC
GND
V_LCDDATA15
V_LCDDATA714
V_LCDDATA13
V_LCDDATA12
V_LCDDATA11
GND
V_LCDDATA23
V_LCDDATA22
V_LCDDATA21
V_LCDDATA20
V_LCDDATA19
GND
V_LCDCNTL2
V_DVO_DDC_SDA
V_DVO_DDC_SCL
RST_PS_PWRGD
Reserved - NC
Reserved - NC
Reserved - NC
GND
FM_MAN_LAN_TYPE1
FM_MAN_LAN_TYPE2
Reserved - NC
Reserved - NC
MII_MDC_RMII_SPARE
MII_COL_RMIIB_RXER
GND
MII_CRS_RMIIB_CRS
MII_TXER_RMIIB_TXEN
100 MII_TXCLK_RMIIB_RXCLK
101 MII_MDIO_RMIIB_PRESENT 102
GND
103
105
107
109
111
113
115
117
119
GND
104
106
108
110
112
114
116
118
120
MII_TXD3_RMIIB_TXD1
MII_TXD2_RMIIB_TXD0
GND
MII_RXD3_RMIIB_RXD1
MII_RXD2_RMIIB_RXD0
GND
MII_TXD1_RMIIA_TXD1
MII_TXD0_RMIIA_TXD0
GND
MII_RXD1_RMIIA_RXD1
MII_RXD0_RMIIA_RXD0
GND
MII_TXEN_RMIIA_TXEN
MII_RXER_RMIIA_TXER
GND
MII_RXCLK
MII_RXDV_RMIIA_CRS
5.3.2
LCP / AUX IPMB Header
Table 16. LPC / AUX IPMB Header Pin-out (J2J1)
Pin
Signal Name
Description
1
SMB_IPMB_5VSB_DAT
BMC IMB 5V standby data line
2
3
4
GND
Ground
SMB_IPMB_5VSB_CLK
P5V_STBY
BMC IMB 5V standby clock line
+5 V standby power
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5.3.3
IPMB Header
Table 17. IPMB Header Pin-out (J4J1)
Pin
Signal Name
Description
1
2
3
SMB_IPMB_5VSB_DAT
BMC IMB 5V Standby Data Line
GND
Ground
SMB_IPMB_5VSB_CLK
BMC IMB 5V Standby Clock Line
5.3.4
HSBP Header
Table 18. HSBP Header Pin-out (J1J7, J1J2)
Pin
Signal Name
Description
1
2
3
4
SMB_IPMB_5V_DAT
BMC IMB 5V Data Line
GND
Ground
SMB_IPMB_5V_CLK
GND – HSBP_A
P5V – HSBP_B
BMC IMB 5V Clock Line
Ground for HSBP A
+5V for HSBP B
5.3.5
SGPIO Header
Table 19. SGPIO Header Pin-out (J2H1, J1J5)
Pin
Signal Name
Description
1
SGPIO_CLOCK
SGPIO Clock Signal
2
3
4
SGPIO_LOAD
SGPIO Load Signal
SGPIO Data Out
SGPIO Data In
SGPIO_DATAOUT
SGPIO_DATAIN
5.3.6
SES I2C
Table 20. SES I2C Header Pin-out (J1J3)
Pin
Signal Name
Description
1
SMB_SAS_3V3_DAT
BMC SAS 3V Data Line
2
3
GND
Ground
SMB_SAS_3V3_CLK
BMC SAS 3V Clock Line
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5.3.7
HDD Activity LED Header
Table 21. HDD Activity LED Header Pin-out (J2J3)
Pin
Signal Name
Description
1
2
LED_SCSI_CONN_N
HDD Activity LED Input
GND
Ground
5.4 Front Panel Connector
The server board provides a 24-pin SSI front panel connector (J1E4) for use with Intel® and
third-party chassis. The following table provides the pin-out for this connector.
Table 22. Front Panel SSI Standard 24-pin Connector Pin-out (J1E4)
Pin
Signal Name
P3V3_STBY
Pin
Signal Name
P3V3_STBY
1
3
5
7
9
2
4
6
8
Key
P5V_STBY
FP_PWR_LED_N
P3V3
FP_ID_LED_BUF_N
FP_LED_STATUS_GREEN_N
FP_LED_STATUS_A MBER_N
NIC1_ACT_LED_N
LED_HDD_ACTIVITY_N
FP_PWR_BTN_N
GND
10
12
14
16
18
20
22
24
11
13
15
17
19
21
23
NIC1_LINK_LED_N
BMC_RST_BTN_N
GND
SMB_SENSOR_3V3STB_DATA
SMB_SENSOR_3V3STB_CLK
FP_CHASSIS_INTRU
NIC2_ACT_LED_N
FP_ID_BTN_N
FM_SIO_TEMP_SENSOR
FP_NMI_BTN_N
NIC2_LINK_LED_N
5.5 I/O Connectors
5.5.1
VGA Connector
The following table details the pin-out definition of the VGA connector (J7A1) that is part of the
stacked video / serial port A connector.
Table 23. VGA Connector Pin-out (J7A1)
Pin
Signal Name
V_IO_R_CONN
Description
Red (analog color signal R)
1
2
3
4
5
6
7
8
9
V_IO_G_CONN
V_IO_B_CONN
TP_VID_CONN_B4
GND
Green (analog color signal G)
Blue (analog color signal B)
No connection
Ground
GND
Ground
GND
Ground
GND
Ground
TP_VID_CONN_B9
No connection
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Pin
10
Signal Name
Description
GND
Ground
11
12
13
14
15
TP_VID_CONN_B11
V_IO_DDCDAT
No connection
DDCDAT
V_IO_HSYNC_CONN
V_IO_VSYNC_CONN
V_IO_DDCCLK
HSYNC (horizontal sync)
VSYNC (vertical sync)
DDCCLK
5.5.2
NIC Connectors
The server board provides two stacked RJ45 / 2xUSB connectors side-by-side on the back
edge of the board (JA6A1, JA6A2). The pin-out for NIC connectors are identical and are defined
in the following table.
Table 24. RJ-45 10/100/1000 NIC Connector Pin-out (JA6A1, JA6A2)
Pin
Signal Name
1
2
3
4
5
6
7
8
9
10
GND
P1V8_NIC
NIC_A_MDI3P
NIC_A_MDI3N
NIC_A_MDI2P
NIC_A_MDI2N
NIC_A_MDI1P
NIC_A_MDI1N
NIC_A_MDI0P
NIC_A_MDI0N
NIC_LINKA_1000_N (LED
NIC_LINKA_100_N (LED)
NIC_ACT_LED_N
NIC_LINK_LED_N
GND
11 (D1)
12 (D2)
13 (D3)
14
15
16
GND
5.5.3
IDE Connector
The server board provides one legacy IDE ATA100 40-pin connector (J2J2). The pin-out is
defined in the following table.
Table 25. IDE 40-pin Connector Pin-out (J2J2)
Pin
Signal Name
Pin
Signal Name
1
3
5
ESB_PLT_RST_IDE_N
2
4
6
GND
RIDE_DD_7
RIDE_DD_6
RIDE_DD_8
RIDE_DD_9
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Pin
Signal Name
RIDE_DD_5
Pin
Signal Name
RIDE_DD_10
7
9
8
RIDE_DD_4
RIDE_DD_3
RIDE_DD_2
RIDE_DD_1
RIDE_DD_0
GND
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
RIDE_DD_11
RIDE_DD_12
RIDE_DD_13
RIDE_DD_14
RIDE_DD_15
KEY
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
RIDE_DDREQ
RIDE_DIOW_N
RIDE_DIOR_N
RIDE_PIORDY
RIDE_DDACK_N
IRQ_IDE
GND
GND
GND
GND
GND
TP_PIDE_32
IDE_PRI_CBLSNS
RIDE_DA2
RIDE_DCS3_N
GND
RIDE_DA1
RIDE_DA0
RIDE_DCS1_N
LED_IDE_N
5.5.4
Intel® Remote Management Module NIC Connector
The server board provides an internal 40-pin connector (J3B2) to accommodate a proprietary
form factor Intel® Remote Management Module NIC module. The following table details the pin-
out of the Intel® RMM NIC module connector.
Table 26. 40-pin RMM NIC Module Connector Pin-out (J3B2)
Pin
Signal Name
Pin
Signal Name
1
3
5
7
9
FM_MAN_LAN_TYPE2
2
4
6
8
FM_MAN_LAN_TYPE1
P3V3_AUX
P3V3_AUX
GND
MII_MDIO_RMIIB_PRESENT
MII_MDC_RMII_SPARE
MII_RXD3_RMIIB_RXD1
MII_RXD2_RMIIB_RXD0
MII_RXD1_RMIIA_RXD1
MII_RXD0_RMIIA_RXD0
MII_RXDV_RMIIA_CRS
MII_RXCLK
GND
10
12
14
16
18
20
22
24
26
28
30
32
34
11
13
15
17
19
21
23
25
27
29
31
33
GND
GND
GND
GND
GND
MII_RXER_RMIIA_RXER
KEY
GND
GND
MII_TXCLK_RMIIB_RXCLK
MII_TXEN_RMIIA_TXEN
MII_TXD0_RMIIA_TXD0
MII_TXD1_RMIIA_TXD1
MII_TXD2_RMIIB_TXD0
MII_TXD3_RMIIB_TXD1
GND
GND
GND
GND
GND
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Pin
35
Signal Name
P3V3_AUX
Pin
36
Signal Name
MII_COL_RMIIB_RXER
37
39
P3V3_AUX
P3V3_AUX
38
40
MII_CRS_RMIIB_CRS
MII_TXER_RMIIB_TXEN
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5.5.5
SATA / SAS Connectors
The server board provides up to six SATA / SAS connectors:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
SATA-0 (J1J1)
SATA-1 (J1H2)
SATA-2 / SAS-0 (J1H1)
SATA-3 / SAS-1 (J1G2)
SATA-4 / SAS-2 (J1G1)
SATA-5 / SAS-3 (J1F2)
The pin configuration for each connector is identical and is defined in the following table.
Table 27. SATA / SAS Connector Pin-out (J1J1, J1H2, J1H1, J1G2, J1G1, J1F2)
Pin
Signal Name
Description
1
2
3
4
5
6
7
GND
Ground
SATA/SAS_TX_P_C
SATA/SAS_TX_N_C
GND
Positive side of transmit differential pair
Negative side of transmit differential pair
Ground
SATA/SAS_RX_N_C
SATA/SAS_RX_P_C
GND
Negative side of receive differential pair
Positive side of receive differential pair
Ground
5.5.6
Serial Port Connectors
The server board provides one external DB9 Serial A port (J7A1) and one internal 9-pin serial B
header (J1B1). The following tables define the pin-outs.
Table 28. External DB9 Serial A Port Pin-out (J7A1)
Pin
Signal Name
Description
1
2
3
4
5
6
7
8
9
SPA_DCD
DCD (carrier detect)
SPA_SIN_L
SPA_SOUT_N
SPA_DTR
GND
RXD (receive data)
TXD (Transmit data)
DTR (Data terminal ready)
Ground
SPA_DSR
SPA_RTS
SPA_CTS
SPA_RI
DSR (data set ready)
RTS (request to send)
CTS (clear to send)
RI (Ring Indicate)
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Table 29. Internal 9-pin Serial B Header Pin-out (J1B1)
Pin
Signal Name
Description
1
SPB_DCD
DCD (carrier detect)
2
3
4
5
6
7
8
9
SPB_DSR
SPB_SIN_L
SPB_RTS
SPB_SOUT_N
SPB_CTS
SPB_DTR
SPB_RI
DSR (data set ready)
RXD (receive data)
RTS (request to send)
TXD (Transmit data)
CTS (clear to send)
DTR (Data terminal ready)
RI (Ring indicate)
SPB_EN_N
Enable
5.5.7
Keyboard and Mouse Connector
Two stacked PS/2* ports (J9A1) support a keyboard and a mouse. Either PS/2 port can support
a mouse or keyboard. The following table details the pin-out of the PS/2 connectors.
Table 30. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1)
Pin
1
Signal Name
KB_DATA_F
Description
Keyboard data
2
TP_PS2_2
GND
Test point – keyboard
Ground
3
4
P5V_KB_F
KB_CLK_F
TP_PS2_6
MS_DAT_F
TP_PS2_8
GND
Keyboard / mouse power
Keyboard clock
Test point – keyboard / mouse
Mouse data
5
6
7
8
Test point – keyboard / mouse
Ground
9
10
11
12
13
14
15
16
17
P5V_KB_F
MS_CLK_F
TP_PS2_12
GND
Keyboard / mouse power
Mouse clock
Test point – keyboard / mouse
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
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5.5.8
USB Connector
The following table details the pin-out of the external USB connectors (JA6A1, JA6A2) found on
the back edge of the server board.
Table 31. External USB Connector Pin-out (JA6A1, JA6A2)
Pin
Signal Name
Description
1
USB_OC
USB_PWR
2
3
4
USB_PN
USB_PP
GND
DATAL0 (Differential data line paired with DATAH0)
DATAH0 (Differential data line paired with DATAL0)
Ground
One 2x5 connector on the server board (J3J1) provides an option to support an additional two
USB ports. The pin-out of the connector is detailed in the following table.
Table 32. Internal USB Connector Pin-out (J3J1)
Pin
1
Signal Name
USB2_VBUS5
Description
USB power (port 5)
2
USB2_VBUS4
USB power (port 4)
3
USB_ESB_P5N_CONN
USB_ESB_P4N_CONN
USB_ESB_P5P_CONN
USB_ESB_P4P_CONN
Ground
USB port 5 negative signal
USB port 4 negative signal
USB port 5 positive signal
USB port 4 positive signal
4
5
6
7
8
Ground
9
Key
No pin
10
TP_USB_ESB_NC
Test point
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5.6 Fan Headers
The server board provides four SSI-compliant 4-pin and four SSI-compliant 6-pin fan headers to
be used as CPU, and IO cooling fans. 3-pin fans are supported on all fan headers. 6-pin fans
are supported on header J3H4, J3H3, J3H2, and J3H1. 4-pin fans are supported on header
J9J1, J5J1, J3H4, J3H3, J9B4, and J9B3. 4-pin fans are not supported on header J3H2, and
J3H1, since these headers are tied to the CPU1 PWM. These fan headers should also not be
used for CPU cooling fans. The pin configuration for each of the 4-pin and 6-pin fan headers is
identical and is defined in the following tables.
ƒ
Two 4-pin fan headers are designated as processor cooling fans:
-
-
CPU1 fan (J9J1)
CPU2 fan (J5J1)
ƒ
Four 6-pin fan headers are designated as hot-swap system fans:
-
-
-
-
Hot-swap system fan 1 (J3H4)
Hot-swap system fan 2 (J3H3)
Hot-swap system fan 3 (J3H2)
Hot-swap system fan 4 (J3H1)
ƒ
Two 4-pin fan headers are designated as rear system fans:
-
-
System fan 5 (J9B4)
System fan 6 (J9B3)
Table 33. SSI 4-pin Fan Header Pin-out (J9J1, J5J1, J9B3, J9B4)
Pin
Signal Name
Ground
Type
GND
Description
Ground is the power supply ground
1
2
3
4
12V
Power
In
Power supply 12 V
Fan Tach
Fan PWM
FAN_TACH signal is connected to the BMC to monitor the fan speed
FAN_PWM signal to control fan speed
Out
Table 34. SSI 6-pin Fan Header Pin-out (J3H1, J3H2, J3H3, J3H4)
Pin
Signal Name
Ground
Type
GND
Description
Ground is the power supply ground
1
2
3
4
5
6
12V
Power
In
Power supply 12 V
Fan Tach
Fan PWM
Fan Presence
Fan Fault LED
FAN_TACH signal is connected to the BMC to monitor the fan speed
FAN_PWM signal to control fan speed
Indicates the fan is present
Out
In
Out
Lights the fan fault LED
Note: Intel Corporation server boards support peripheral components and contain a number of
high-density VLSI and power delivery components that need adequate airflow to cool. Intel’s
own chassis are designed and tested to meet the intended thermal requirements of these
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components when the fully integrated system is used together. It is the responsibility of the
system integrator that chooses not to use Intel developed server building blocks to consult
vendor datasheets and operating parameters to determine the amount of air flow required for
their specific application and environmental conditions. Intel Corporation can not be held
responsible if components fail or the server board does not operate correctly when used outside
any of their published operating or non-operating limits.
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6. Jumper Blocks
The server board has several 3-pin jumper blocks that can be used to configure, protect, or
recover specific features of the server board.
Pin 1 on each jumper block can be identified by the following symbol on the silkscreen: ▼
BIOS Bank Select
Force Lower
Bank
Normal
2
Operation
3
(default)
J1C3
CMOS Clear
Disable
2
Enable
3
J1D1
Password Clear
Protect
2
Clear
3
J1D2
BMC Force Update
Disable
2
Enable
3
J1E3
AF000422
Figure 17. Jumper Blocks (J1C3, J1D1, J1D2, J1E32)
Table 35. Server Board Jumpers (J1C3, J1D1, J1D2, J1E3)
Jumper Name
J1C3: BIOS Bank
Select
Pins
1-2
System Results
If these pins are jumper the system will boot from an alternate BIOS image.
2-3
System is configured for normal operation. (Default)
J1D1: CMOS Clear 1-2
2-3
These pins should have a jumper in place for normal system operation. (Default)
If these pins are jumpered, the CMOS settings will be cleared immediately. These pins
should not be jumpered for normal operation
J1D2: Password
Clear
1-2
2-3
These pins should have a jumper in place for normal system operation. (Default)
If these pins are jumpered, administrator and user passwords will be cleared
immediately. These pins should not be jumpered for normal operation.
J1E3: BMC Forced 1-2
BMC Firmware Force Update Mode – Disabled (Default)
Update
2-3
BMC Firmware Force Update Mode – Enabled
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6.1 CMOS Clear and Password Reset Usage Procedure
The CMOS Clear (J1D1) and Password Reset (J1D2) recovery features are designed such that
the desired operation can be achieved with minimal system down time. The usage procedure for
these two features has changed from previous generation Intel server boards. The following
procedure outlines the new usage model.
1. Power down server. Do not unplug the power cord.
2. Open the server chassis. For instructions, see your server chassis documentation.
3. Move jumper from the default operating position, covering pins 1 and 2, to the reset /
clear position, covering pins 2 and 3.
4. Wait 5 seconds.
5. Move the jumper back to default position, covering pins 1 and 2.
6. Close the server chassis.
7. Power up the server.
The password and/or CMOS is now cleared and can be reset by going into BIOS setup.
Note: Removing AC Power before performing the CMOS Clear operation will cause the system
to automatically power up and immediately power down, after the procedure is followed and AC
power is re-applied. If this happens,, remove the AC power cord again, wait 30 seconds, and re-
install the AC power cord. Power up system and proceed to the <F2> BIOS Setup Utility to reset
the desired settings.
6.2 BMC Force Update Procedure
When performing a standard BMC firmware update procedure, the update utility places the
BMC into an update mode, allowing the firmware to load safely onto the flash device. In the
unlikely event that the BMC firmware update process fails due to the BMC not being in the
proper update state, the server board provides a BMC Force Update jumper (J1E3) which will
force the BMC into the proper update state. The following procedure should be following in the
event the standard BMC firmware update process fails.
1. Power down and remove the AC power cord.
2. Open the server chassis. See your server chassis documentation for instructions.
3. Move jumper from the default operating position, covering pins1 and 2, to the enabled
position, covering pins 2 and 3.
4. Close the server chassis.
5. Reconnect the AC cord and power up the server.
6. Perform the BMC firmware update procedure as documented in the README.TXT file
that is included in the given BMC firmware update package. After successful completion
of the firmware update process, the firmware update utility may generate an error stating
that the BMC is still in update mode.
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7. Power down and remove the AC power cord.
8. Open the server chassis.
9. Move jumper from the enabled position, covering pins 2 and 3 to the disabled position,
covering pins 1 and 2.
10. Close the server chassis.
11. Reconnect the AC cord and power up the server.
Note: Normal BMC functionality is disabled with the Force BMC Update jumper is set to the
enabled position. The server should never be run with the BMC Force Update jumper set in this
position. This jumper setting should only be used when the standard firmware update process
fails. This jumper should remain in the default / disabled position when the server is running
normally.
6.3 BIOS Select Jumper
The jumper block at J1C3, located at the left of PCI-X* slot 1, is used to select which BIOS
image the system will boot to. Pin 1 on the jumper is identified with a ‘▼’. This jumper should
only be moved if you want to force the BIOS to boot to the secondary bank, which may hold a
different version of BIOS.
The rolling BIOS feature of the server board will automatically alternate the boot BIOS to the
secondary bank if the BIOS image in the primary bank is corrupted and cannot boot.
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7. Intel® Light Guided Diagnostics
The server boards have several on-board diagnostic LEDs to assist in troubleshooting board-
level issues. This section provides a description the location and function of each LED on the
server board. For a more detailed description of what drives the diagnostic LED operation, see
the Intel® S5000 Server Board Family Datasheet.
7.1 5 Volt Standby LED
Several server management features of this server board require that a 5 volt stand-by voltage
be supplied from the power supply. Some of the features and components that require this
voltage be present when the system is “Off” include the BMC within the ESB2-E, onboard NICs,
and optional RMM connector with Intel RMM installed.
The LED is located just to the right of the CMOS Battery in the center of the server board and is
labeled “5VSB_LED” is illuminated when AC power is applied to the platform and 5 volt standby
voltage is supplied to the server board by the power supply.
AF000224
Figure 18. 5 Volt Standby Status LED Location
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7.2 Fan Fault LEDs
Fan fault LEDs are present for the two CPU fans and the two rear system fans. The two CPU
fan fault LEDs are located next to each CPU fan header. The two rear system fan fault LEDs
are located next to each rear system fan header are shown in the following figure.
AF000203
Figure 19. Fan Fault LED Locations
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7.3 System ID LED and System Status LED
The server board provides LEDs for both system ID and system status. These LEDs are located
in the rear I/O area of the server board between the PS/2* mouse / keyboard stacked
connectors and the video / serial stacked connectors. The location of these LEDs are shown in
the following figure.
A
B
AF000204
A. System ID LED
B. System Status LED
Figure 20. System ID LED and System Status LED Locations
The blue System ID LED can be illuminated using either of two mechanisms.
ƒ
ƒ
By pressing the System ID Button on the system front panel the ID LED will display a
solid blue color, until the button is pressed again.
By issuing the appropriate hex IPMI “Chassis Identify” value, the ID LED will either Blink
Blue for 15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI
Chassis Identify value is issued to turn it off.
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The bi-color System Status LED operates as follows:
Table 36. System Status LED
Color
Off
Green / Alternating
State
N/A
Criticality
Not ready
Not ready
Description
AC power off
Pre DC Power On – 20-30 second BMC Initialization when AC is
applied to the server. Control Panel buttons are disabled until BMC
initialization is complete.
Amber
Blink
Green
Green
Solid on
Blink
System OK
Degraded
System booted and ready.
System degraded
•
Unable to use all of the installed memory (more than one
DIMM installed).
•
Correctable errors over a threshold of 10 and migrating to a
spare DIMM (memory sparing). This indicates that the user
no longer has spared DIMMs indicating a redundancy lost
condition. Corresponding DIMM LED should light up.
In mirrored configuration, when memory mirroring takes
place and system loses memory redundancy. This is not
covered by (2).
•
•
Redundancy loss such as power-supply or fan. This does
not apply to non-redundant sub-systems.
•
•
PCI-e link errors
CPU failure / disabled – if there are two processors and one
of them fails
•
Fan alarm – Fan failure. Number of operational fans should
be more than minimum number needed to cool the system
Non-critical threshold crossed – Temperature and voltage
•
Amber
Amber
Blink
Non-critical
Non-fatal alarm – system is likely to fail
•
•
•
Critical voltage threshold crossed
VRD hot asserted
Minimum number of fans to cool the system not present or
failed
•
In non-sparing and non-mirroring mode if the threshold of
ten correctable errors is crossed within the window
Solid on
Critical, non-
recoverable
Fatal alarm – system has failed or shutdown
•
DIMM failure when there is one DIMM present, no good
memory present
•
Run-time memory uncorrectable error in non-redundant
mode
•
•
•
IERR signal asserted
Processor 1 missing
Temperature (CPU ThermTrip, memory TempHi, critical
threshold crossed)
•
•
No power good – power fault
Processor configuration error (for instance, processor
stepping mismatch)
7.3.1
System Status LED – BMC Initialization
When the AC power is first applied to the system and 5V-STBY is present, the BMC
controller on the server board requires 5-10 seconds to initialize. During this time, the
system status LED will blink, alternating between amber and green, and the power button
functionality of the control panel is disabled preventing the server from powering up. Once
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BMC initialization has completed, the status LED will stop blinking and the power button
functionality is restored and can be used to turn on the server.
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7.4 DIMM Fault LEDs
The server board provides a memory fault LED for each DIMM socket. These LEDs are located
towards the rear of the server board next to each DIMM connector.
AF000205
Figure 21. DIMM Fault LED Locations
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7.5 Processor Fault LEDs
The server board provides a fault LED for each processor socket. These LEDs are located near
the processor sockets.
AF000206
Figure 22. Processor Fault LED Locations
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7.6 Post Code Diagnostic LEDs
POST code diagnostic LEDs are located on the back edge of the server board in the rear I/O
area of the server board between the PS/2 mouse / keyboard stacked connectors and the video
/ serial stacked connectors.
During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS will display the given POST code to the POST code diagnostic
LEDs on the back edge of the server board. To assist in troubleshooting a system hang during
the POST process, the Diagnostic LEDs can be used to identify the last POST process to be
executed. See Appendix C for a complete description of how these LEDs are read, and for a list
of all supported POST codes.
A. Status LED
D. Bit 2 LED (POST LED)
E. Bit 1 LED (POST LED)
F. LSB LED (POST LED)
B. ID LED
C. MSB LED (POST LED)
Figure 23. POST Code Diagnostic LED Location
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8. Design and Environmental Specifications
8.1 Server Boards S5000PSL and S5000XSL Design Specifications
The operation of the server boards at conditions beyond those shown in the following table may
cause permanent damage to the system. Exposure to absolute maximum rating conditions for
extended periods may affect system reliability.
Table 37. Server Board Design Specifications
Operating Temperature
Non-Operating Temperature
DC Voltage
0º C to 55º C 1 (32º F to 131º F)
-40º C to 70º C (-40º F to 158º F)
± 5% of all nominal voltages
Shock (Unpackaged)
Shock (Packaged)
<20 pounds
Trapezoidal, 50 G, 170 inches / sec
36 inches
20 to <40 pounds
40 to <80 pounds
80 to <100 pounds
100 to <120 pounds
120 pounds
30 inches
24 inches
18 inches
12 inches
9 inches
Vibration (Unpackaged)
5 Hz to 500 Hz 3.13 g RMS random
Note:
1 Chassis design must provide proper airflow to avoid exceeding the Dual-Core Intel® Xeon®
processor 5000 sequence maximum case temperature.
Disclaimer Note: Intel Corporation server boards contain a number of high-density VLSI and
power delivery components that need adequate airflow to cool. Intel ensures through its own
chassis development and testing that when Intel server building blocks are used together, the
fully integrated system will meet the intended thermal requirements of these components. It is
the responsibility of the system integrator who chooses not to use Intel developed server
building blocks to consult vendor datasheets and operating parameters to determine the amount
of air flow required for their specific application and environmental conditions. Intel Corporation
cannot be held responsible, if components fail or the server board does not operate correctly
when used outside any of their published operating or non-operating limits.
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8.2 Server Board Power Requirements
This section provides power supply design guidelines for a system using the Intel® Server Boards S5000PSL and S5000XSL,
including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the
power distribution implemented on these server boards.
Figure 24. Power Distribution Block Diagram
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8.2.1
Processor Power Support
The server board supports the Thermal Design Point (TDP) guideline for Intel® Xeon®
processors. The Flexible Motherboard Guidelines (FMB) has also been followed to help
determine the suggested thermal and current design values for anticipating future processor
needs. The following table provides maximum values for Icc, TDP power and T
core Intel® Xeon® processor 5000 sequence family.
for the dual
CASE
Table 38. Intel® Xeon® Processor Dual Processor TDP Guidelines
TDP Power
Max TCASE
Icc MAX
130 W
70º C
150 A
Note: These values are for reference only. The Dual-Core Intel® Xeon®) processor 5000
sequence Datasheet contains the actual specifications for the processor. If the values found in
the Dual-Core Intel(r) Xeon(r) processor 5000 sequence Datasheet are different than those
published here, the Dual-Core Intel(r) Xeon(r) processor 5000 sequence Datasheet values will
supersede these, and should be used.
8.3 Power Supply Output Requirements
This section is for reference purposes only. The intent is to provide guidance to system
designers to determine a power supply for use with this server board. This section specifies the
power supply requirements Intel used to develop a power supply for its 5U server system.
The combined power of all outputs shall not exceed the rated output power of the power supply.
The power supply must meet both static and dynamic voltage regulation requirements for the
minimum loading conditions.
Table 39. 550 W Load Ratings
Voltage
Minimum
Maximum
Peak
Continuous
Continuous
+3.3 V
+5 V
1.5 A
1.0 A
0.5 A
0.5 A
0.5 A
0.5 A
0 A
24 A
24 A
16 A
16 A
14 A
8 A
+12 V1
+12 V2
+12 V3
+12 V4
-12 V
18 A
18 A
13 A
0.5 A
3.0 A
+5 VSB
0.1 A
3.5 A
1. Maximum continuous total DC output power should not exceed 550 W.
2. Maximum continuous combined load on +3.3 VDC and +5 VDC outputs shall not exceed 140W.
3. Maximum peak total DC output power should not exceed 660W.
4. Peak power and current loading shall be supported for a minimum of 12 seconds.
5. Maximum combined current for the 12 V outputs shall be 41 A.
6. Peak current for the combined 12 V outputs shall be 50A.
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8.3.1
Grounding
The grounds of the pins of the power supply output connector provide the power return path.
The output connector ground pins is connected to safety ground (power supply enclosure). This
grounding should is designed to ensure passing the maximum allowed common mode noise
levels.
8.3.2
Standby Outputs
The 5 VSB output shall be present when an AC input greater than the power supply turn on
voltage is applied.
8.3.3
Remote Sense
The power supply has remote sense return to regulate out ground drops for all output voltages:
+3.3 V, +5 V, +12 V1, +12 V2, +12 V3, -12 V, and 5 VSB. The power supply uses remote sense
(3.3 VS) to regulate out drops in the system for the +3.3 V output.
The +5 V, +12 V1, +12 V2, +12 V3, –12 V and 5 VSB outputs only use remote sense referenced
to the remote sense return signal. The remote sense input impedance to the power supply must
be greater than 200 Ω on 3.3 VS and 5 VS. This is the value of the resistor connecting the
remote sense to the output voltage internal to the power supply.
Remote sense must be able to regulate out a minimum of a 200 mV drop on the +3.3 V output.
The remote sense return must be able to regulate out a minimum of a 200 mV drop in the power
ground return. The current in any remote sense line shall be less than 5 mA to prevent voltage
sensing errors.
The power supply must operate within specification over the full range of voltage drops from the
power supply’s output connector to the remote sense points.
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8.3.4
Voltage Regulation
The power supply output voltages must stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple / noise.
Table 40. Voltage Regulation Limits
Parameter
Tolerance
Minimum
Nominal
Maximum
Units
+3.3V
- 5% / +5%
+3.14
+3.30
+3.46
Vrms
+5V
- 5% / +5%
- 5% / +5%
- 5% / +5%
- 5% / +5%
- 5% / +5%
- 5% / +9%
- 5% / +5%
+4.75
+5.00
+5.25
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
+12V 1
+12V 2
+12V 3
+12V 4
- 12V
+11.40
+11.40
+11.40
+11.40
- 11.40
+4.75
+12.00
+12.00
+12.00
+12.00
-12.00
+5.00
+12.60
+12.60
+12.60
+12.60
-13.08
+5.25
+5VSB
1. Maximum continuous total output power should not exceed 670 W.
2. Maximum continuous load on the combined 12 V output shall not exceed 48 A.
3. Peak load on the combined 12 V output shall not exceed 52 A.
4. Peak total DC output power should not exceed 730 W.
8.3.5
Dynamic Loading
The output voltages shall remain within limits for the step loading and capacitive loading
specified in the table below. The load transient repetition rate shall be tested between 50 Hz
and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The Δ step load may occur anywhere within the minimum load to the maximum
load conditions.
Table 41. Transient Load Requirements
Δ Step Load Size 1
7.0A
Output
+3.3V
Load Slew Rate
Test Capacitive Load
0.25 A/μsec
4700 μF
+5V
7.0A
25A
0.25 A/μsec
0.25 A/μsec
0.25 A/μsec
1000 μF
4700 μF
20 μF
+12V
+5VSB
0.5A
1. Step loads on each 12V output may happen simultaneously.
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8.3.6
Capacitive Loading
The power supply shall be stable and meet all requirements with the following capacitive
loading ranges.
Table 42. Capacitive Loading Conditions
Output
+3.3 V
Minimum
250
Maximum
6800
Units
μF
+5 V
+12 V 1, 2, 3, 4
400
4700
11,000
350
μF
μF
μF
μF
500 each
-12 V
1
+5 VSB
20
350
1. Maximum continuous total output power should not exceed 670 W.
2. Maximum continuous load on the combined 12 V output shall not exceed 48 A.
3. Peak load on the combined 12 V output shall not exceed 52 A.
4. Peak total DC output power should not exceed 730 W.
8.3.7
Ripple / Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 0Hz to 20MHz at the power supply output connectors. A
10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor are placed at the point of
measurement.
Table 43. Ripple and Noise
+3.3 V
50mVp-p
+5 V
50mVp-p
+12 V 1, 2, 3, 4
120mVp-p
-12 V
120mVp-p
+5 VSB
50mVp-p
1. Maximum continuous total output power should not exceed 670 W.
2. Maximum continuous load on the combined 12 V output shall not exceed 48 A.
3. Peak load on the combined 12 V output shall not exceed 52 A.
4. Peak total DC output power should not exceed 730 W.
8.3.8
Timing Requirements
The following are the timing requirements for the power supply operation. The output voltages
must rise from 10% to within regulation limits (Tvout_rise) within 5 to 70 ms. 5 VSB is allowed to
rise from 1.0 to 25 ms. All outputs must rise monotonically. Each output voltage shall reach
regulation within 50 ms (Tvout_on) of each other during turn on of the power supply. Each output
voltage shall fall out of regulation within 400 msec (Tvout_off) of each other during turn off.
The following tables and diagrams show the timing requirements for the power supply being
turned on and off via the AC input with PSON held low, and the PSON signal with the AC input
applied.
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Table 44. Output Voltage Timing
Item
Tvout_rise
Description
Output voltage rise time from each main output.
Minimum
5.0 1
Maximum
70 1
Units
ms
Tvout_on
All main outputs must be within regulation of each other within this
time.
50
ms
Tvout_off
All main outputs must leave regulation within this time.
400
ms
1. The 5VSB output voltage rise time is from 1.0 ms to 25 ms
V out
10% V out
V1
V2
V3
V4
T
vout_off
T
vout_rise
T
vout_on
TP02313
Figure 25. Output Voltage Timing
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Table 45. Turn On/Off Timing
Item
Tsb_on_delay
Description
Minimum
Maximum
1500
Units
ms
Delay from AC being applied to 5VSB being within regulation.
Tac_on_delay
Delay from AC being applied to all output voltages being within
regulation.
ms
2500
Tvout_holdup
Tpwok_holdup
Time all output voltages stay within regulation after loss of AC.
Delay from loss of AC to de-assertion of PWOK
21
ms
ms
ms
20
Tpson_on_delay Delay from PSON# active to output voltages within regulation
limits.
5
400
50
Tpson_pwok
Tpwok_on
Delay from PSON# deactivate to PWOK being de-asserted.
ms
ms
Delay from output voltages within regulation limits to PWOK
asserted at turn on.
100
1
500
Tpwok_off
Delay from PWOK de-asserted to output voltages (3.3V, 5V,
12V, -12V) dropping out of regulation limits.
ms
ms
ms
ms
Tpwok_low
Tsb_vout
Duration of PWOK being in the de-asserted state during an
off/on cycle using AC or the PSON signal.
100
50
70
Delay from 5VSB being in regulation to O/Ps being in
regulation at AC turn on.
1000
T5VSB_holdup
Time the 5VSB output voltage stays within regulation after loss
of AC.
AC Input
Tvout_holdup
Vout
Tpwok_low
TAC_on_delay
Tpwok_off
Tsb_on_delay
Tpwok_on
Tsb_on_delay
PWOK
Tpwok_off
Tpwok_on
Tpson_pwok
Tpwok_holdup
5VSB
PSON
Tsb_vout
T5VSB_holdup
Tpson_on_delay
AC turn on/off cycle
PSON turn on/off cycle
Figure 26. Turn On/Off Timing (Power Supply Signals)
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8.3.9
Residual Voltage Immunity in Standby Mode
The power supply should be immune to any residual voltage placed on its outputs (typically, a
leakage voltage through the system from standby output) up to 500 mV. There shall be no
additional heat generated, nor stressing of any internal components with this voltage applied to
any individual output, and all outputs simultaneously. It also should not trip the power supply
protection circuits during turn on.
Residual voltage at the power supply outputs for a no load condition shall not exceed 100 mV
when AC voltage is applied and the PSON# signal is de-asserted.
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9. Regulatory and Certification Information
To help ensure EMC compliance with your local regional rules and regulations, before computer
integration, make sure that the chassis, power supply, and other modules have passed EMC
testing using a server board with a microprocessor from the same family (or higher) and
operating at the same (or higher) speed as the microprocessor used on this server board. The
final configuration of your end system product may require additional EMC compliance testing.
For more information please contact your local Intel Representative.
This is an FCC Class A device. Integration of it into a Class B chassis does not result in a Class
B device.
9.1 Product Regulatory Compliance
Intended Application – This product was evaluated as Information Technology Equipment
(ITE), which may be installed in offices, schools, computer rooms, and similar commercial type
locations. The suitability of this product for other product categories and environments (such as:
medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment,
etc.), other than an ITE application, may require further evaluation.
9.1.1
Product Safety Compliance
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UL60950 – CSA 60950(USA / Canada)
EN60950 (Europe)
IEC60950 (International)
CB Certificate & Report, IEC60950 (report to include all country national deviations)
GOST R 50377-92 – Listed on one System License (Russia)
Belarus License – Listed on System License (Belarus)
CE - Low Voltage Directive 73/23/EEE (Europe)
IRAM Certification (Argentina)
9.1.2
Product EMC Compliance – Class A Compliance
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FCC /ICES-003 - Emissions (USA/Canada) Verification
CISPR 22 – Emissions (International)
EN55022 - Emissions (Europe)
EN55024 - Immunity (Europe)
CE – EMC Directive 89/336/EEC (Europe)
VCCI Emissions (Japan)
AS/NZS 3548 Emissions (Australia / New Zealand)
BSMI CNS13438 Emissions (Taiwan)
GOST R 29216-91 Emissions - Listed on one System License (Russia)
GOST R 50628-95 Immunity –Listed on one System License (Russia)
Belarus License – Listed on one System License (Belarus)
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RRL MIC Notice No. 1997-41 (EMC) & 1997-42 (EMI) (Korea)
9.1.3
Certifications / Registrations / Declarations
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UL Certification or NRTL (US/Canada)
CB Certifications (International)
CE Declaration of Conformity (CENELEC Europe)
FCC/ICES-003 Class A Attestation (USA/Canada)
C-Tick Declaration of Conformity (Australia)
MED Declaration of Conformity (New Zealand)
BSMI Certification (Taiwan)
RRL Certification (Korea)
Ecology Declaration (International)
9.2 Product Regulatory Compliance Markings
The Intel® Server Board bears the following regulatory marks.
Regulatory Compliance
Region
Marking
UL Mark
USA/Canada
CE Mark
Europe
EMC Marking (Class A)
BSMI Marking (Class A)
Canada
Taiwan
CANADA ICES-003 CLASS A
CANADA NMB-003 CLASSE A
C-tick Marking
RRL MIC Mark
Australia / New Zealand
Korea
Country of Origin
Model Designation
Exporting Requirements
Regulatory Identification
Made in xxxxx (Provided by label, not silkscreen)
Examples (Server Board S5000PSL) for boxed
type boards; or Board PB number for non-boxed
boards (typically high-end boards)
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9.3 Electromagnetic Compatibility Notices
9.3.1
FCC Verification Statement (USA)
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must accept
any interference received, including interference that may cause undesired operation.
Intel Corporation
5200 N.E. Elam Young Parkway
Hillsboro, OR 97124-6497
Phone: 1-800-628-8686
This equipment has been tested and found to comply with the limits for a Class B digital device,
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses, and can radiate radio frequency energy and, if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is no
guarantee that interference will not occur in a particular installation. If this equipment does
cause harmful interference to radio or television reception, which can be determined by turning
the equipment off and on, the user is encouraged to try to correct the interference by one or
more of the following measures:
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Reorient or relocate the receiving antenna.
Increase the separation between the equipment and the receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver
is connected.
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Consult the dealer or an experienced radio/TV technician for help.
Any changes or modifications not expressly approved by the grantee of this device could void
the user’s authority to operate the equipment. The customer is responsible for ensuring
compliance of the modified product.
All cables used to connect to peripherals must be shielded and grounded. Operation with
cables, connected to peripherals that are not shielded and grounded may result in interference
to radio and TV reception.
9.3.2
ICES-003 (Canada)
Cet appareil numérique respecte les limites bruits radioélectriques applicables aux
appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur:
“Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications.
English translation of the notice above:
This digital apparatus does not exceed the Class B limits for radio noise emissions from digital
apparatus set out in the interference-causing equipment standard entitled “Digital Apparatus,”
ICES-003 of the Canadian Department of Communications.
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9.3.3
Europe (CE Declaration of Conformity)
This product has been tested in accordance too, and complies with the Low Voltage Directive
(73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark
to illustrate its compliance.
9.3.4
VCCI (Japan)
English translation of the notice above:
This is a Class B product based on the standard of the Voluntary Control Council for
Interference (VCCI) from Information Technology Equipment. If this is used near a radio or
television receiver in a domestic environment, it may cause radio interference. Install and use
the equipment according to the instruction manual.
9.3.5
BSMI (Taiwan)
The BSMI Certification Marking and EMC warning is located on the outside rear area of
the product.
9.3.6
RRL (Korea)
Following is the RRL certification information for Korea.
English translation of the notice above:
1. Type of Equipment (Model Name): On License and Product
2. Certification No.: On RRL certificate. Obtain certificate from local Intel representative
3. Name of Certification Recipient: Intel Corporation
4. Date of Manufacturer: Refer to date code on product
5. Manufacturer/Nation: Intel Corporation/Refer to country of origin marked on product
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9.3.7
CNCA (CCC-China)
The CCC Certification Marking and EMC warning is located on the outside rear area of
the product.
A
9.4 Restriction of Hazardous Substances (RoHS)
Compliance
Intel has a system in place to restrict the use of banned substances in accordance with the
European Directive 2002/95/EC. Compliance is based on declaration that materials banned in
the RoHS Directive are either (1) below all applicable substance threshold limits or (2) an
approved/pending RoHS exemption applies.
Note: RoHS implementation details are not fully defined and may change.
Threshold limits and banned substances are noted below.
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Quantity limit of 0.1% by mass (1000 PPM) for:
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Lead
Mercury
Hexavalent Chromium
Polybrominated Biphenyls Diphenyl Ethers (PBDE)
Quantity limit of 0.01% by mass (100 PPM) for:
Cadmium
-
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Appendix A: Integration and Usage Tips
Appendix A: Integration and Usage Tips
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When adding or removing components or peripherals from the server board, AC power
must be removed. With AC power plugged into the server board, 5-volt standby is still
present even though the server board is powered off.
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Processors must be installed in order. CPU 1 is located near the edge of the server
board and must be populated to operate the board.
On the back edge of the server board are four diagnostic LEDs that display a sequence
of red, green, or amber POST codes during the boot process. If the server board hangs
during POST, the LEDs will display the last POST event run before the hang.
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Only Fully Buffered DIMMs (FBDIMMs) are supported on this server board. For a list of
supported memory for this server board, see the Intel® S5000PSL / S5000XSL Tested
Memory List.
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For a list of Intel supported operating systems, add-in cards, and peripherals for this
server board, see the Intel® S5000PSL / S5000XSL Tested Hardware and OS List.
Only Dual-Core Intel® Xeon® processors 5000 Series, with system bus speeds of 667,
1066, or 1333 MHz are supported on this server board. Previous generation Intel® Xeon®
processors are not supported.
ƒ
For the best performance, the number of FBDIMMs installed should be balanced across
both memory branches. For example: a four-DIMM configuration will perform better than
a two DIMM configuration. In a four-DIMM configuration, FBDIMMs should be installed in
DIMM sockets A1, B1, C1, and D1. An eight-DIMM configuration will perform better then
a six DIMM configuration.
ƒ
ƒ
The Intel® RMM connector is not compatible with the Intel® Server Management Module
Professional Edition (Product Code AXXIMMPRO) or with the Intel® Server Management
Module Advanced Edition (Product Code AXXIMMADV)
Removing AC power before performing the CMOS Clear operation will cause the system
to automatically power up and immediately power down after the CMOS Clear procedure
is followed and AC power is re-applied. If this happens, remove the AC power cord, wait
30 seconds, and then re-connect the AC power cord. Power up the system and proceed
to the <F2> BIOS Setup Utility to reset the desired settings.
ƒ
ƒ
Normal BMC functionality is disabled with the force BMC update jumper set to the
“enabled” position (pins 2-3). The server should never be run with the BMC force update
jumper set in this position and should only be used when the standard firmware update
process fails. This jumper should remain in the default (disabled) position (pins 1-2)
when the server is running normally.
When performing a BIOS update procedure, the BIOS select jumper must be set to its
default position (pins 2-3).
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Appendix B: BMC Sensor Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Appendix B: BMC Sensor Tables
This appendix lists the sensor identification numbers and information about the sensor type,
name, supported thresholds, assertion and de-assertion information, and a brief description of
the sensor purpose. See the Intelligent Platform Management Interface Specification, Version
2.0, for sensor and event/reading-type table information.
ƒ
ƒ
ƒ
Sensor Type
The Sensor Type is the values enumerated in the Sensor Type Codes table in the IPMI
specification. The Sensor Type provides the context in which to interpret the sensor,
such as the physical entity or characteristic that is represented by this sensor.
Event / Reading Type
The Event/Reading Type values are from the Event/Reading Type Code Ranges and
Generic Event/Reading Type Codes tables in the IPMI specification. Digital sensors are
a specific type of discrete sensor, which have only two states.
Event Offset/Triggers
Event Thresholds are event-generating thresholds for threshold types of sensors.
-
[u,l][nr,c,nc]: upper nonrecoverable, upper critical, upper noncritical, lower
nonrecoverable, lower critical, lower noncritical
-
uc, lc: upper critical, lower critical
Event Triggers are supported event-generating offsets for discrete type sensors. The
offsets can be found in the Generic Event/Reading Type Codes or Sensor Type Codes
tables in the IPMI specification, depending on whether the sensor event/reading type is
generic or a sensor-specific response.
ƒ
ƒ
Assertion / De-assertion Enables
Assertion and de-assertion indicators reveal the type of events the sensor generates:
-
-
As: Assertions
De: De-assertion
Readable Value / Offsets
-
Readable Value indicates the type of value returned for threshold and other non-
discrete type sensors.
-
Readable Offsets indicate the offsets for discrete sensors that are readable with the
Get Sensor Reading command. Unless otherwise indicated, all event triggers are
readable; Readable Offsets consist of the reading type offsets that do not generate
events.
ƒ
Event Data
Event data is the data that is included in an event message generated by the sensor. For
threshold-based sensors, the following abbreviations are used:
-
-
R: Reading value
T: Threshold value
94
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Appendix B: BMC Sensor Tables
ƒ
Rearm Sensors
The rearm is a request for the event status for a sensor to be rechecked and updated
upon a transition between good and bad states. Rearming the sensors can be done
manually or automatically. This column indicates the type supported by the sensor. The
following abbreviations are used in the comment column to describe a sensor:
-
-
A: Auto-rearm
M: Manual rearm
ƒ
ƒ
ƒ
Default Hysteresis
The hysteresis setting applies to all thresholds of the sensor. This column provides the
count of hysterisis for the sensor, which can be 1 or 2 (positive or negative hysteresis).
Criticality
Criticality is a classification of the severity and nature of the condition. It also controls the
behavior of the Control Panel Status LED
Standby
Some sensors operate on standby power. These sensors may be accessed and / or
generate events when the main (system) power is off, but AC power is present.
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Appendix B: BMC Sensor Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Table 46. BMC Sensors
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
Power Unit 01h
Status
All
Power Unit
09h
Sensor
Specific
Power down
Power cycle
A/C lost
OK
As
–
Trig Offset
A
X
6Fh
Soft power
Crit
control failure
Power unit
failure
Predictive
failure
Non-Crit
OK
Power Unit 02h
Redun-
dancy
Chassis-
specific
Power Unit
09h
Generic
0Bh
Redundancy
regained
As
–
Trig Offset
A
X
Non-red: suff
res from redund
Redundancy
lost
Degraded
Redundancy
degraded
Non-red: suff
from insuff
OK
Non-red:
Critical
insufficient
Redun degrade OK
from full
Redun degrade
from non-
redundant
96
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Intel® Server Boards S5000PSL and S5000XSL TPS
Appendix B: BMC Sensor Tables
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
Watchdog 03h
All
Watchdog 2
23h
Sensor
Specific
Timer expired,
status only
OK
As
–
Trig Offset
Trig Offset
A
A
X
X
6Fh
Hard reset
Power down
Power cycle
Timer interrupt
Platform
Security
Violation
04h
All
Platform
Security
Violation
Attempt
Sensor
Specific
Secure mode
violation
attempt
OK
OK
As
–
6Fh
Out-of-band
access
password
violation
06h
Physical
Security
05h
07h
Chassis
Intrusion
is chassis-
specific
Physical
Security
Sensor
Specific
Chassis
intrusion
As and De
–
–
Trig Offset
Trig Offset
A
A
X
–
05h
6Fh
LAN leash lost
1
FP Diag
Interrupt
(NMI)
All
Critical
Interrupt
Sensor
Specific
Front panel NMI OK
/ diagnostic
interrupt
As
13h
6Fh
Bus
uncorrectable
error
System
Event Log
09h
0Ah
0Bh
All
All
All
Event
Logging
Disabled
Sensor
Specific
Log area reset / OK
cleared
As
As
As
–
–
–
Trig Offset
A
A
A
X
X
X
6Fh
10h
Session
Audit
Session Audit Sensor
00h – Session
activation
OK
OK
As defined
by IPMI
Specific
2Ah
6Fh
01h – Session
deactivation
System
Event
('System
Event')
System Event Sensor
00 – System
reconfigured
Trig Offset
Specific
12h
6Fh
04 – PEF action
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Appendix B: BMC Sensor Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
BB +1.2V
Vtt
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Eh
All
All
All
All
All
All
All
All
All
All
All
All
All
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
A
A
A
A
A
A
A
A
A
A
A
A
A
–
01h
BB+1.9V
NIC Core
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
X
01h
BB +1.5V
AUX
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
–
01h
BB +1.5V
BB +1.8V
BB +3.3V
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
–
01h
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
–
01h
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
–
X
X
–
–
–
–
X
01h
BB +3.3V
STB
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
01h
BB +1.5V
ESB
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
01h
BB +5V
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
01h
BB +1.2V
NIC
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
01h
BB +12V
AUX
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
01h
BB 0.9V
Voltage
02h
Threshold [u,l] [c,nc]
01h
Threshold
defined
BB Vbat
Voltage
02h
Digital
Discrete
01h – Limit
exceeded
Critical
As and De
–
05h
BB Temp
30h
32h
All
All
Temperature Threshold [u,l] [c,nc]
01h 01h
Temperature Threshold [u,l] [c,nc]
01h 01h
Threshold
defined
As and De Analog
As and De Analog
R, T
R, T
A
A
X
X
Front
Panel
Temp
Threshold
defined
98
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Appendix B: BMC Sensor Tables
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
BNB Temp 33h
All
Temperature Threshold [u,l] [c,nc]
Threshold
defined
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
T
A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
01h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
01h
Tach Fan
1
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
60h
61h
62h
63h
Chassis-
specific
Threshold [l] [c,nc]
Threshold
defined
M
M
M
M
M
M
M
M
M
M
A
01h
Tach Fan
2
Chassis-
specific
Threshold [l] [c,nc]
Threshold
defined
01h
Tach Fan
3
Chassis-
specific
Threshold [l] [c,nc]
Threshold
defined
01h
Tach Fan
4
Chassis-
specific
Threshold [l] [c,nc]
Threshold
defined
01h
Tach Fan
5
Chassis-
specific
Threshold [l] [c,nc]
Threshold
defined
01h
Tach Fan
6
Chassis-
specific
Threshold [l] [c,nc]
Threshold
defined
01h
Tach Fan
7
Chassis-
specific
Threshold [l] [c,nc]
Threshold
defined
01h
Tach Fan
8
Chassis-
specific
Threshold [l] [c,nc]
Threshold
defined
01h
Tach Fan
9
Chassis-
specific
Threshold [l] [c,nc]
Threshold
defined
01h
Tach Fan
10
Chassis-
specific
Threshold [l] [c,nc]
01h
Threshold
defined
Fan 1
Present
Chassis-
specific
Generic
08h
Device present OK
As and De
As and De
As and De
As and De
–
–
–
–
Fan 2
Present
Chassis-
specific
Generic
08h
Device present OK
T
A
Fan 3
Present
Chassis-
specific
Generic
08h
Device present OK
Device present OK
T
A
Fan 4
Chassis-
specific
Generic
08h
T
A
Present
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Appendix B: BMC Sensor Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
Fan 5
Present
64h
65h
66h
67h
68h
69h
6Fh
Chassis-
specific
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Generic
Device present OK
Device present OK
Device present OK
Device present OK
Device present OK
Device present OK
As and De
As and De
As and De
As and De
As and De
As and De
As
–
–
–
–
–
–
–
T
A
A
A
A
A
A
A
–
–
–
–
–
–
X
08h
Fan 6
Present
Chassis-
specific
Generic
08h
T
Fan 7
Present
Chassis-
specific
Generic
08h
T
Fan 8
Present
Chassis-
specific
Generic
08h
T
Fan 9
Present
Chassis-
specific
Generic
08h
T
Fan 10
Present
Chassis-
specific
Generic
08h
T
Fan
Redun-
dancy
Chassis-
specific
Generic
0Bh
Redundancy
regained
OK
Trig Offset
Redundancy
lost
Degraded
Redundancy
degraded
Non-red: suff
OK
res from redund
Non-red: suff
from insuff
Non-red:
Critical
insufficient
Redun degrade OK
from full
Redun degrade
from non-
redundant
Power
Supply
Status 1
70h
Chassis-
specific
Power Supply Sensor
Presence
Failure
OK
As and De
–
Trig Offset
A
X
Specific
08h
Critical
Non-Crit
Critical
6Fh
Predictive fail
A/C lost
100
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Appendix B: BMC Sensor Tables
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
Configuration
error
Non-Crit
Power
Supply
Status 2
71h
Chassis-
specific
Power Supply Sensor
Presence
Failure
OK
As and De
–
Trig Offset
A
X
Specific
08h
Critical
Non-Crit
Critical
Non-Crit
6Fh
Predictive fail
A/C lost
Configuration
error
Power
Nozzle
78h
79h
7Ah
Chassis-
specific
Current
03h
Threshold [u] [c,nc]
01h
Threshold
defined
As and De Analog
As and De Analog
As and De Analog
R, T
R, T
R, T
A
A
A
–
–
–
Power
Supply 1
Power
Nozzle
Chassis-
specific
Current
03h
Threshold [u] [c,nc]
01h
Threshold
defined
Power
Supply 2
Power
Gauge
V1 rail
(+12v)
Chassis-
specific
Current
03h
Threshold [u] [c,nc]
01h
Threshold
defined
Power
Supply 1
Power
Gauge
V1 rail
(+12v)
7Bh
7Ch
Chassis-
specific
Current
03h
Threshold [u] [c,nc]
01h
Threshold
defined
As and De Analog
As and De Analog
R, T
R, T
A
A
–
–
Power
Supply 2
Power
Gauge
(aggre-
gate
Chassis-
specific
Other Units
0Bh
Threshold [u] [c,nc]
01h
Threshold
defined
power)
Power
Supply 1
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Appendix B: BMC Sensor Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
Power
Gauge
(aggregate
power)
7Dh
Chassis-
specific
Other Units
0Bh
Threshold [u] [c,nc]
Threshold
defined
As and De Analog
R, T
A
A
–
01h
Power
Supply 2
System
ACPI
Power
State
82h
All
System ACPI Sensor
Power State
S0 / G0
S1
OK
As
–
Trig Offset
X
Specific
22h
6Fh
S3
S4
S5 / G2
G3 mechanical
off
Button
84h
85h
86h
All
All
All
Button
14h
Sensor
Specific
Power button
Reset button
OK
As
–
–
–
Trig Offset
Trig Offset
Trig Offset
A
A
A
X
–
6Fh
SMI
Timeout
SMI Timeout Digital
01h – State
asserted
Critical
OK
As and De
As
Discrete
F3h
03h
Sensor
Failure
Sensor
Failure
OEM
Sensor
Specific
I2C device not
found
I2C device error
detected
I2C bus timeout
X
F6h
73h
NMI Signal 87h
State
All
All
All
OEM
C0h
Digital
Discrete
01h – State
asserted
OK
OK
–
–
01h
01h
–
–
–
–
–
–
X
03h
SMI Signal 88h
State
OEM
C0h
Digital
Discrete
01h – State
asserted
03h
Proc 1
Status
90h
Processor
07h
Sensor
Specific
IERR
Critical
Non-rec
Critical
OK
As and De
–
Trig Offset
M
Thermal trip
Config error
Presence
6Fh
102
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Appendix B: BMC Sensor Tables
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
Disabled
Degraded
Proc 2
Status
91h
All
Processor
07h
Sensor
Specific
IERR
Critical
Non-rec
Critical
OK
As and De
–
Trig Offset
M
X
Thermal trip
Config error
Presence
Disabled
6Fh
Degraded
Proc 1
Temp
98h
9Ah
All
All
Temperature Threshold [u,l] [c,nc]
01h 01h
Temperature Threshold [u,l] [c,nc]
Threshold
defined
As and De Analog
As and De Analog
R, T
R, T
A
A
A
–
–
–
Proc 2
Temp
Threshold
defined
01h
01h
PCIe Link0 A0h
PCIe Link1 A1h
PCIe Link2 A2h
PCIe Link3 A3h
PCIe Link4 A4h
Critical
Interrupt
Sensor
Specific
PCIe
Link0
Bus correctable OK
error
As
As
As
As
As
–
–
–
–
–
See the
BIOS EPS
13F
6Fh
Bus
Degraded
uncorrectable
error
Critical
Interrupt
Sensor
Specific
PCIe
Link1
Bus correctable OK
error
See the
BIOS EPS
A
A
A
A
–
–
–
–
13F
6Fh
Bus
Degraded
uncorrectable
error
Critical
Interrupt
Sensor
Specific
PCIe
Link2
Bus correctable OK
error
See the
BIOS EPS
13F
6Fh
Bus
Degraded
uncorrectable
error
Critical
Interrupt
Sensor
Specific
PCIe
Link3
Bus correctable OK
error
See the
BIOS EPS
13F
6Fh
Bus
Degraded
uncorrectable
error
Critical
Interrupt
Sensor
Specific
PCIe
Link4
Bus correctable OK
error
See the
BIOS EPS
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Appendix B: BMC Sensor Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name
Sensor
Number Applica-
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
bility
13F
6Fh
Bus
Degraded
uncorrectable
error
PCIe Link5 A5h
PCIe Link6 A6h
PCIe Link7 A7h
PCIe Link8 A8h
PCIe Link9 A9h
Critical
Interrupt
Sensor
Specific
PCIe
Link5
Bus correctable OK
error
As
–
–
–
–
–
–
–
See the
BIOS EPS
A
A
A
A
A
A
A
–
–
–
–
–
–
13F
6Fh
Bus
Degraded
uncorrectable
error
Critical
Interrupt
Sensor
Specific
PCIe
Link6
Bus correctable OK
error
As
As
As
As
As
As
See the
BIOS EPS
13F
6Fh
Bus
Degraded
uncorrectable
error
Critical
Interrupt
Sensor
Specific
PCIe
Link7
Bus correctable OK
error
See the
BIOS EPS
13F
6Fh
Bus
Degraded
uncorrectable
error
Critical
Interrupt
Sensor
Specific
PCIe
Link8
Bus correctable OK
error
See the
BIOS EPS
13F
6Fh
Bus
Degraded
uncorrectable
error
Critical
Interrupt
Sensor
Specific
PCIe
Link9
Bus correctable OK
error
See the
BIOS EPS
13F
6Fh
Bus
Degraded
uncorrectable
error
PCIe
Link10
AAh
ABh
Critical
Interrupt
Sensor
Specific
PCIe
Link10
Bus correctable OK
error
See the
BIOS EPS
13F
6Fh
Bus
Degraded
uncorrectable
error
PCIe
Critical
Interrupt
Sensor
Specific
PCIe
Link11
Bus correctable OK
error
See the
BIOS EPS
–
Link11
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Appendix B: BMC Sensor Tables
Sensor
Name
Sensor
Number Applica-
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
bility
13F
6Fh
Bus
Degraded
uncorrectable
error
PCIe
Link12
ACh
ADh
Critical
Interrupt
Sensor
Specific
PCIe
Link12
Bus correctable OK
error
As
–
–
See the
BIOS EPS
A
A
–
–
13F
6Fh
Bus
Degraded
uncorrectable
error
PCIe
Link13
Critical
Interrupt
Sensor
Specific
PCIe
Link13
Bus correctable OK
error
As
See the
BIOS EPS
13F
6Fh
Bus
Degraded
uncorrectable
error
Proc 1
Thermal
Control
C0h
C1h
C8h
All
Temperature Threshold [u] [c,nc]
01h 01h
Threshold
defined
As and De Analog
As and De Analog
Trig Offset
Trig Offset
Trig Offset
M
M
M
–
–
–
Proc 2
Thermal
Control
All
Temperature Threshold [u] [c,nc]
01h 01h
Threshold
defined
Proc 1
VRD Over
Temp
All
Temperature Digital
01h – Limit
exceeded
Non-Critical
Non-Critical
As and De
As and De
–
–
Discrete
01h
05h
Proc 2
VRD Over
Temp
C9h
All
Temperature Digital
01h – Limit
exceeded
Trig Offset
M
–
Discrete
01h
05h
Proc 1 Vcc D0h
All
All
All
Voltage
02h
Threshold [u,l] [c,nc]
Threshold
defined
As and De Analog
As and De Analog
As and De Discrete
R, T
R, T
R, T
A
A
A
–
–
–
01h
Proc 2 Vcc D1h
Voltage
02h
Threshold [u,l] [c,nc]
01h
Threshold
defined
Proc 1 Vcc D2h
Out-of-
Range
Voltage
02h
Digital
Discrete
01h – Limit
exceeded
Non-Critical
05h
Proc 2
D3h
All
Voltage
02h
Digital
Discrete
01h – Limit
exceeded
Non-Critical
As and De Discrete
R, T
A
–
Vcc Out-
of-Range
05h
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Appendix B: BMC Sensor Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
CPU
Population
Error
D8h
All
Processor
07h
Generic
01h –- State
asserted
Critical
As and De
As
–
R, T
A
A
–
–
03h
DIMM A1
E0h
All
Slot
Connector
Sensor
Specific
Fault status
asserted
Degraded
–
Trig Offset
21h
6Fh
Device installed OK
Disabled
Sparing
Degraded
OK
DIMM A2
DIMM B1
DIMM B2
DIMM C1
DIMM C2
E1h
E2h
E3h
E4h
E5h
All
All
All
All
All
Slot
Connector
Sensor
Specific
Fault status
asserted
Degraded
As
As
As
As
As
–
–
–
–
–
Trig Offset
Trig Offset
Trig Offset
Trig Offset
Trig Offset
A
A
A
A
A
–
–
–
–
–
21h
6Fh
Device installed OK
Disabled
Sparing
Degraded
OK
Slot
Connector
Sensor
Specific
Fault status
asserted
Degraded
21h
6Fh
Device installed OK
Disabled
Sparing
Degraded
OK
Slot
Connector
Sensor
Specific
Fault status
asserted
Degraded
21h
6Fh
Device installed OK
Disabled
Sparing
Degraded
OK
Slot
Connector
Sensor
Specific
Fault status
asserted
Degraded
21h
6Fh
Device installed OK
Disabled
Sparing
Degraded
OK
Slot
Connector
Sensor
Specific
Fault status
asserted
Degraded
21h
6Fh
Device installed OK
Disabled Degraded
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Appendix B: BMC Sensor Tables
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
Sparing
OK
Degraded
DIMM D1
E6h
All
All
All
Slot
Connector
Sensor
Specific
Fault status
asserted
As
–
Trig Offset
Trig Offset
A
A
–
–
21h
6Fh
Device installed OK
Disabled
Sparing
Degraded
OK
DIMM D2
E7h
Slot
Connector
Sensor
Specific
Fault status
asserted
Degraded
As
–
21h
6Fh
Device installed OK
Disabled
Sparing
Degraded
OK
OK
Memory A ECh
Error
Memory
0Ch
Sensor
Specific
Correctable
ECC
As
As
As
As
–
–
–
–
Trig Offset
Trig Offset
Trig Offset
Trig Offset
A
A
A
A
–
–
–
–
6Fh
Uncorrectable
ECC
Memory B EDh
Error
System-
specific
Memory
0Ch
Sensor
Specific
Correctable
ECC
OK
OK
OK
OK
6Fh
Uncorrectable
ECC
Memory C EEh
Error
System-
specific
Memory
0Ch
Sensor
Specific
Correctable
ECC
6Fh
Uncorrectable
ECC
Memory D EFh
Error
System-
specific
Memory
0Ch
Sensor
Specific
Correctable
ECC
6Fh
Uncorrectable
ECC
B0 DIMM
Sparing
Enabled
F0h
F1h
All
All
Entity
Presence
Sensor
Specific
Entity present
As
As
–
–
Trig Offset
Trig Offset
A
A
–
–
25h
6Fh
B0 DIMM
Memory
Discrete
Fully redundant OK
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Appendix B: BMC Sensor Tables
Intel® Server Boards S5000PSL and S5000XSL TPS
Sensor
Name
Sensor
Number Applica-
bility
System Sensor Type
Event /
Reading
Type
Event Offset
Triggers
Criticality
Assert /
De-assert
Readable Event Data Rearm Standby
Value /
Offsets
Sparing
Redun-
dancy
0Ch
0Bh
Non-red: suff
res from redund
Degraded
Non-red: suff
res from insuff
res
Non-red: Insuff Crtical
res
B1 DIMM
Sparing
Enabled
F2h
F3h
All
All
Entity
Presence
Sensor
Specific
Entity present
OK
As
–
–
Trig Offset
Trig Offset
A
A
–
–
25h
6Fh
B1 DIMM
Sparing
Redun-
dancy
Memory
0Ch
Discrete
0Bh
Fully redundant OK
As
Non-red: suff
res from redund
Degraded
Non-red: suff
res from insuff
res
Non-red: insuff Crtical
res
B01 DIMM F4h
Mirroring
Enabled
All
All
Entity
Presence
Sensor
Specific
Entity present
OK
As
As
–
–
Trig Offset
Trig Offset
A
A
–
–
25h
6Fh
B01 DIMM F5h
Mirroring
Redun-
Memory
0Ch
Discrete
0Bh
Fully redundant OK
Non-red:suff res Degraded
from redund
dancy
Non-red:suff res
from insuff res
Non-red: insuff Crtical
res
Note 1: Not supported except for ESB2 embedded NICs
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Intel® Server Boards S5000PSL and S5000XSL TPSAppendix C: POST Code Diagnostic LED Decoder
Appendix C: POST Code Diagnostic LED Decoder
During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the
back edge of the server board. To assist in troubleshooting a system hang during the POST
process, the Diagnostic LEDs can be used to identify the last POST process that was executed.
Each POST code is represented by a combination of colors from the four LEDs. The LEDs are
capable of displaying three colors: green, red, and amber. The POST codes are divided into two
nibbles, an upper nibble and a lower nibble. Each bit in the upper nibble is represented by a red
LED and each bit in the lower nibble is represented by a green LED. If both bits are set in the
upper and lower nibbles then both red and green LEDs are lit, resulting in an amber color. If
both bits are clear, then the LED is off.
A. Status LED
D. Bit 2 LED (POST LED)
E. Bit 1 LED (POST LED)
F. LSB LED (POST LED)
B. ID LED
C. MSB LED (POST LED)
Figure 27. Diagnostic LED Placement Diagram
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Appendix C: POST Code Diagnostic LED DecoderIntel® Server Boards S5000PSL and S5000XSL TPS
In the below example, BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs
are decoded as follows:
ƒ
ƒ
Red bits = 1010b = Ah
Green bits = 1100b = Ch
Since the red bits correspond to the upper nibble and the green bits correspond to the lower
nibble, the two are concatenated as ACh.
Table 47. POST Progress Code LED Example
8h
4h
2h
1h
LEDs
ACh
Red
Green
Red
Green
Red
Green
Red
Green
1
1
0
1
1
0
0
0
Result
Amber
Green
Bit 2
Red
Bit 1
Off
MSB
LSB
Table 48. Diagnostic LED POST Code Decoder
Diagnostic LED Decoder
Description
Checkpoint
G=Green, R=Red, A=Amber
MSB
Host Processor
Off
Bit 2 Bit 1 LSB
0x10h
0x11h
0x12h
0x13h
Chipset
0x21h
Memory
0x22h
0x23h
0x24h
0x25h
0x26h
0x27h
0x28h
PCI Bus
0x50h
0x51h
0x52h
0x53h
0x54h
0x55h
0x56h
Off
Off
Off
Off
Off
Off
G
R
A
R
A
Power-on initialization of the host processor (bootstrap processor)
Host processor cache initialization (including AP)
Starting application processor initialization
SMM initialization
Off
Off
Off
G
Off
Off
R
G
Initializing a chipset component
Off
Off
Off
Off
Off
Off
G
Off
Off
G
A
A
R
R
A
A
R
Off
G
Reading configuration data from memory (SPD on DIMM)
Detecting presence of memory
Off
G
Programming timing parameters in the memory controller
Configuring memory parameters in the memory controller
Optimizing memory controller settings
G
G
Off
G
G
Initializing memory, such as ECC init
Off
Off
Testing memory
Off
Off
Off
Off
Off
Off
Off
R
R
R
R
A
A
A
Off
Off
G
R
A
R
A
R
A
R
Enumerating PCI busses
Allocating resources to PCI busses
Hot Plug PCI controller initialization
Reserved for PCI bus
G
Off
Off
G
Reserved for PCI bus
Reserved for PCI bus
Reserved for PCI bus
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Intel® Server Boards S5000PSL and S5000XSL TPSAppendix C: POST Code Diagnostic LED Decoder
Diagnostic LED Decoder
Description
Checkpoint
G=Green, R=Red, A=Amber
MSB
Off
Bit 2 Bit 1 LSB
0x57h
USB
A
G
A
Reserved for PCI bus
0x58h
0x59h
G
G
R
R
Off
Off
R
A
Resetting USB bus
Reserved for USB devices
ATA / ATAPI / SATA
0x5Ah
0x5Bh
G
G
R
R
G
G
R
A
Resetting PATA / SATA bus and all devices
Reserved for ATA
SMBUS
0x5Ch
G
G
A
A
Off
Off
R
A
Resetting SMBUS
0x5Dh
Reserved for SMBUS
Local Console
0x70h
0x71h
0x72h
Off
R
R
R
R
R
A
R
A
R
Resetting the video controller (VGA)
Disabling the video controller (VGA)
Enabling the video controller (VGA)
Off
Off
Remote Console
0x78h
0x79h
0x7Ah
G
G
G
R
R
R
R
R
A
R
A
R
Resetting the console controller
Disabling the console controller
Enabling the console controller
Keyboard (PS2 or USB)
0x90h
0x91h
0x92h
0x93h
0x94h
0x95h
R
R
R
R
R
R
Off
Off
Off
Off
G
Off
Off
G
R
A
R
A
R
A
Resetting the keyboard
Disabling the keyboard
Detecting the presence of the keyboard
Enabling the keyboard
G
Off
Off
Clearing keyboard input buffer
Instructing keyboard controller to run Self Test (PS2 only)
G
Mouse (PS2 or USB)
0x98h
0x99h
A
A
A
A
Off
Off
Off
Off
Off
Off
G
R
A
R
A
Resetting the mouse
Detecting the mouse
0x9Ah
Detecting the presence of mouse
Enabling the mouse
0x9Bh
G
Fixed Media
0xB0h
R
R
Off
Off
R
R
R
A
Resetting fixed media device
Disabling fixed media device
0xB1h
0xB2h
Detecting presence of a fixed media device (IDE hard drive detection,
etc.)
R
Off
Off
A
A
R
A
0xB3h
R
Enabling / configuring a fixed media device
Removable Media
0xB8h
0xB9h
0xBAh
A
A
Off
Off
R
R
R
A
Resetting removable media device
Disabling removable media device
Detecting presence of a removable media device (IDE CDROM
detection, etc.)
A
Off
G
A
R
R
R
0xBCh
A
Enabling / configuring a removable media device
Boot Device Selection
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Appendix C: POST Code Diagnostic LED DecoderIntel® Server Boards S5000PSL and S5000XSL TPS
Diagnostic LED Decoder
Description
Checkpoint
G=Green, R=Red, A=Amber
MSB
Bit 2 Bit 1 LSB
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0XDA
0xDB
0xDC
0xDE
0xDF
R
R
R
R
R
A
A
A
A
R
R
R
R
A
A
A
Off
Off
G
R
A
R
A
R
A
R
A
R
A
R
A
R
R
A
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
Trying boot device selection
R
R
R
R
R
R
R
A
A
A
A
A
A
A
G
Off
Off
G
G
Off
Off
G
G
Off
G
G
Pre-EFI Initialization (PEI) Core
0xE0h
0xE2h
0xE1h
0xE3h
R
R
R
R
R
R
R
R
R
A
R
A
Off
Off
G
Started dispatching early initialization modules (PEIM)
Initial memory found, configured, and installed correctly
Reserved for initialization module use (PEIM)
G
Reserved for initialization module use (PEIM)
Driver Execution Environment (DXE) Core
0xE4h
0xE5h
R
R
R
A
A
A
R
R
A
Off
G
Entered EFI driver execution phase (DXE)
Started dispatching drivers
0xE6h
Off
Started connecting drivers
DXE Drivers
0xE7h
R
A
A
A
A
A
A
R
R
R
A
A
A
R
R
A
A
A
G
Waiting for user input
0xE8h
Off
G
Checking password
0xE9h
Entering BIOS setup
0xEAh
Off
Off
G
Flash Update
0xEEh
Calling Int 19. One beep unless silent boot is enabled.
Unrecoverable boot failure / S3 resume failure
0xEFh
Runtime Phase / EFI Operating System Boot
0xF4h
0xF5h
0xF8h
R
R
A
A
R
R
R
A
Entering Sleep state
Exiting Sleep state
Operating system has requested EFI to close boot services
(ExitBootServices ( ) has been called)
A
A
A
R
R
R
R
R
A
R
A
R
0xF9h
0xFAh
Operating system has switched to virtual address mode
(SetVirtualAddressMap ( ) has been called)
Operating system has requested the system to reset (ResetSystem ()
has been called)
Pre-EFI Initialization Module (PEIM) / Recovery
0x30h
0x31h
Off
Off
Off
Off
R
R
R
A
Crisis recovery has been initiated because of a user request
Crisis recovery has been initiated by software (corrupt flash)
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Intel® Server Boards S5000PSL and S5000XSL TPSAppendix C: POST Code Diagnostic LED Decoder
Diagnostic LED Decoder
Description
Checkpoint
G=Green, R=Red, A=Amber
MSB
Off
Bit 2 Bit 1 LSB
0x34h
0x35h
0x3Fh
G
G
G
R
R
A
R
A
A
Loading crisis recovery capsule
Off
G
Handing off control to the crisis recovery capsule
Unable to complete crisis recovery.
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Appendix D: POST Code Errors
Intel® Server Boards S5000PSL and S5000XSL TPS
Appendix D: POST Code Errors
Whenever possible, the BIOS will output the current boot progress codes on the video screen.
Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class,
subclass, and operation information. The class and subclass fields point to the type of hardware
that is being initialized. The operation field represents the specific initialization activity. Based on
the data bit availability to display progress codes, a progress code can be customized to fit the
data width. The higher the data bit, the higher the granularity of information that can be sent on
the progress port. The progress codes may be reported by the system BIOS or option ROMs.
The response column in the following table is divided into two types:
ƒ
Pause: The message is displayed in the Error Manager screen, an error is logged to the
SEL, and user input is required to continue. The user can take immediate corrective
action or choose to continue booting.
ƒ
Halt: The message is displayed in the Error Manager screen, an error is logged to the
SEL, and the system cannot boot unless the error is resolved. The user needs to replace
the faulty part and restart the system.
Table 49. POST Error Messages and Handling
Error Code
Error Message
Response
004C
Keyboard / interface error
CMOS date / time not set
Configuration cleared by jumper
Passwords cleared by jumper
Configuration default loaded
Password check failed
Pause
0012
5220
5221
5223
0048
0141
0146
8110
8111
8120
8121
8130
8131
8160
8161
8190
8198
0192
0194
0195
0197
8300
8306
8305
Pause
Pause
Pause
Pause
Halt
PCI resource conflict
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Halt
Insufficient memory to shadow PCI ROM
Processor 01 internal error (IERR) on last boot
Processor 02 internal error (IERR) on last boot
Processor 01 thermal trip error on last boot
Processor 02 thermal trip error on last boot
Processor 01 disabled
Processor 02 disabled
Processor 01 unable to apply BIOS update
Processor 02 unable to apply BIOS update
Watchdog timer failed on last boot
Operating system boot watchdog timer expired on last boot
L3 cache size mismatch
CPUID, processor family are different
Front side bus mismatch
Halt
Pause
Pause
Pause
Pause
Pause
Processor speeds mismatched
Baseboard management controller failed self-test
Front panel controller locked
Hotswap controller failed
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Appendix D: POST Code Errors
Error Code
Error Message
Response
84F2
Baseboard management controller failed to respond
Baseboard management controller in update mode
Sensor data record empty
Pause
84F3
84F4
84FF
8500
8520
8521
8522
8523
8524
8525
8526
8527
8528
8529
852A
852B
852C
852D
852E
852F
8540
8580
8581
8582
8583
8584
8585
8586
8587
8588
8589
858A
858B
858C
858D
858E
858F
8600
8601
8602
8603
Pause
Pause
Pause
System event log full
Memory Component could not be configured in the selected RAS mode.
DIMM_A1 failed Self Test (BIST).
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
DIMM_A2 failed Self Test (BIST).
DIMM_A3 failed Self Test (BIST).
DIMM_A4 failed Self Test (BIST).
DIMM_B1 failed Self Test (BIST).
DIMM_B2 failed Self Test (BIST).
DIMM_B3 failed Self Test (BIST).
DIMM_B4 failed Self Test (BIST).
DIMM_C1 failed Self Test (BIST).
DIMM_C2 failed Self Test (BIST).
DIMM_C3 failed Self Test (BIST).
DIMM_C4 failed Self Test (BIST).
DIMM_D1 failed Self Test (BIST).
DIMM_D2 failed Self Test (BIST).
DIMM_D3 failed Self Test (BIST).
DIMM_D4 failed Self Test (BIST).
Memory component lost redundancy during the last boot.
DIMM_A1 correctable ECC error encountered.
DIMM_A2 correctable ECC error encountered.
DIMM_A3 correctable ECC error encountered.
DIMM_A4 correctable ECC error encountered.
DIMM_B1 correctable ECC error encountered.
DIMM_B2 correctable ECC error encountered.
DIMM_B3 correctable ECC error encountered.
DIMM_B4 correctable ECC error encountered.
DIMM_C1 correctable ECC error encountered.
DIMM_C2 correctable ECC error encountered.
DIMM_C3 correctable ECC error encountered.
DIMM_C4 correctable ECC error encountered.
DIMM_D1 correctable ECC error encountered.
DIMM_D2 correctable ECC error encountered.
DIMM_D3 correctable ECC error encountered.
DIMM_D4 correctable ECC error encountered.
Primary and secondary BIOS IDs do not match.
Override jumper is set to force boot from lower alternate BIOS bank of flash ROM
Watchdog timer expired (secondary BIOS may be bad!)
Secondary BIOS checksum fail
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Appendix D: POST Code Errors
Intel® Server Boards S5000PSL and S5000XSL TPS
POST Error Beep Codes
The following table lists POST error beep codes. Prior to system Video initialization, BIOS uses
these beep codes to inform users on error conditions. The beep code is followed by a user
visible code on POST Progress LEDs.
Table 50. POST Error Beep Codes
Beeps
3
Error Message
Memory error
POST Progress Code
Description
System halted because a fatal error related to the memory
was detected.
6
BIOS rolling back
error
The system has detected a corrupted BIOS in the flash
part, and is rolling back to the last good BIOS.
The BMC may generate beep codes upon detection of failure conditions. Beep codes are
sounded each time the problem is discovered, such as on each power-up attempt, but are not
sounded continuously. Codes that are common across all Intel® server boards and systems that
use the Intel® 5000 chipset are listed in the following table. Each digit in the code is represented
by a sequence of beeps whose count is equal to the digit.
Table 51. BMC Beep Codes
Code
1-5-2-1
Reason for Beep
CPU: Empty slot / population error – Processor
slot 1 is not populated.
Associated Sensors
CPU Population Error
Supported?
Yes
1-5-2-2
1-5-2-3
1-5-2-4
1-5-4-2
CPU: No processors (terminators only)
N/A
N/A
No
No
No
Yes
CPU: Configuration error (e.g., VID mismatch)
CPU: Configuration error (e.g, BSEL mismatch) N/A
Power fault: DC power unexpectedly lost (power Power Unit – power unit
good dropout)
failure offset
1-5-4-3
1-5-4-4
Chipset control failure
Power control fault
N/A
No
Power Unit – soft power
control failure offset
Yes
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Intel® Server Boards S5000PSL and S5000XSL TPS
Appendix D: POST Code Errors
Appendix E: Supported Intel® Server Chassis
The Intel® Server Boards S5000PSL and S5000XSL are supported in the following Intel®
pedestal server chassis:
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Intel® Server Chassis SC5400 BASE
Intel® Server Chassis SC5400 BRP
Intel® Server Chassis SC5400 LX
Intel® Entry Server Chassis SC5299-E DP
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Glossary
Intel® Server Boards S5000PSL and S5000XSL TPS
Glossary
This appendix contains important terms used in the preceding chapters. For ease of use,
numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”).
Acronyms are then entered in their respective place, with non-acronyms following.
Term
ACPI
Definition
Advanced Configuration and Power Interface
Application Processor
AP
APIC
ASIC
ASMI
BIOS
BIST
BMC
Bridge
BSP
byte
Advanced Programmable Interrupt Control
Application Specific Integrated Circuit
Advanced Server Management Interface
Basic Input / Output System
Built-In Self Test
Baseboard Management Controller
Circuitry connecting one computer bus to another, allowing an agent on one to access the other
Bootstrap Processor
8-bit quantity.
CBC
Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they
bridge the IPMB buses of multiple chassis.
CEK
Common Enabling Kit
CHAP
CMOS
Challenge Handshake Authentication Protocol
In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes
of memory, which normally resides on the server board.
DPC
EEPROM
EHCI
EMP
EPS
ESB2
FBD
F MB
FRB
FRU
FSB
GB
Direct Platform Control
Electrically Erasable Programmable Read-Only Memory
Enhanced Host Controller Interface
Emergency Management Port
External Product Specification
Enterprise South Bridge 2
Fully Buffered DIMM
Flexible Mother Board
Fault Resilient Booting
Field Replaceable Unit
Front Side Bus
1024 MB
GPIO
GTL
HSC
Hz
General Purpose I/O
Gunning Transceiver Logic
Hot-Swap Controller
Hertz (1 cycle / second)
Inter-Integrated Circuit Bus
Intel® Architecture
I2C
IA
IBF
Input Buffer
ICH
I/O Controller Hub
IC MB
IERR
Intelligent Chassis Management Bus
Internal Error
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Intel® Server Boards S5000PSL and S5000XSL TPS
Term
Glossary
Definition
IFB
I/O and Firmware Bridge
INTR
IP
Interrupt
Internet Protocol
IPMB
IPMI
IR
Intelligent Platform Management Bus
Intelligent Platform Management Interface
Infrared
ITP
In-Target Probe
KB
1024 bytes
KCS
LAN
LCD
LED
LPC
LUN
MAC
MB
Keyboard Controller Style
Local Area Network
Liquid Crystal Display
Light Emitting Diode
Low Pin Count
Logical Unit Number
Media Access Control
1024KB
MCH
MD2
MD5
ms
Memory Controller Hub
Message Digest 2 – Hashing Algorithm
Message Digest 5 – Hashing Algorithm – Higher Security
milliseconds
MTTR
Mux
Memory Type Range Register
Multiplexor
NIC
Network Interface Controller
NMI
Nonmaskable Interrupt
OBF
OEM
Ohm
PEF
PEP
PIA
Output Buffer
Original Equipment Manufacturer
Unit of electrical resistance
Platform Event Filtering
Platform Event Paging
Platform Information Area (This feature configures the firmware for the platform hardware)
Programmable Logic Device
PLD
PMI
Platform Management Interrupt
Power-On Self Test
POST
PSMI
PWM
RAM
RASUM
RISC
ROM
RTC
SDR
SECC
SEEPROM
SEL
Power Supply Management Interface
Pulse-Width Modulation
Random Access Memory
Reliability, Availability, Serviceability, Usability, and Manageability
Reduced Instruction Set Computing
Read Only Memory
Real-Time Clock (Component of ICH peripheral chip on the server board)
Sensor Data Record
Single Edge Connector Cartridge
Serial Electrically Erasable Programmable Read-Only Memory
System Event Log
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Glossary
Intel® Server Boards S5000PSL and S5000XSL TPS
Definition
Term
SIO
Server Input / Output
SMI
Server Management Interrupt (SMI is the highest priority nonmaskable interrupt)
Server Management Mode
SMM
SMS
SNMP
TBD
TIM
Server Management Software
Simple Network Management Protocol
To Be Determined
Thermal Interface Material
UART
UDP
UHCI
UTC
VID
Universal Asynchronous Receiver / Transmitter
User Datagram Protocol
Universal Host Controller Interface
Universal time coordinare
Voltage Identification
VRD
Word
ZIF
Voltage Regulator Down
16-bit quantity
Zero Insertion Force
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Intel® Server Boards S5000PSL and S5000XSL TPS
Reference Documents
Reference Documents
See the following documents for additional information:
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Intel® S5000 Server Board Family Datasheet
Intel Server Boards S5000PSL and S5000XSL Specification Update
Intel 5000 Series Chipset Memory Controller Hub Datasheet.
Intel 631xESB/632xESB I/O Controller Hub Datasheet.
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