80960HA/HD/HT 32-Bit High-Performance
Superscalar Processor
Datasheet
Product Features
■ 32-Bit Parallel Architecture
—Load/Store Architecture
■ 3.3 V Supply Voltage
—5 V Tolerant Inputs
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers
—TTL Compatible Outputs
■ Guarded Memory Unit
—Provides Memory Protection
—User/Supervisor Read/Write/Execute
■ 32-Bit Demultiplexed Burst Bus
—Per-Byte Parity Generation/Checking
—Address Pipelining Option
—1.28 Gbyte Internal Bandwidth
(80 MHz)
—On-Chip Register Cache
■ Processor Core Clock
—80960HA is 1x Bus Clock
—80960HD is 2x Bus Clock
—80960HT is 3x Bus Clock
—Fully Programmable Wait State Generator
—Supports 8-, 16- or 32-Bit Bus Widths
■ Binary Compatible with Other 80960
—160 Mbyte/s External Bandwidth
(40 MHz)
Processors
■ Issue Up To 150 Million Instructions per
■ High-Speed Interrupt Controller
—Up to 240 External Interrupts
Second
■ High-Performance On-Chip Storage
—31 Fully Programmable Priorities
—Separate, Non-maskable Interrupt Pin
■ Dual On-Chip 32-Bit Timers
—16 Kbyte Four-Way Set-Associative
Instruction Cache
—8 Kbyte Four-Way Set-Associative Data
Cache
—Auto Reload Capability and One-Shot
—CLKIN Prescaling, divided by 1, 2, 4 or 8
—JTAG Support - IEEE 1149.1 Compliant
—2 Kbyte General Purpose RAM
■ Separate 128-Bit Internal Paths For
Instructions/Data
Order Number: 272495-008
September 2002
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Contents
Contents
1.0 About This Document ...................................................................................................................9
2.0 Intel 80960Hx Processor...............................................................................................................9
2.1
2.2
The i960® Processor Family...............................................................................................10
Key 80960Hx Features.......................................................................................................10
2.2.1 Execution Architecture...........................................................................................10
2.2.2 Pipelined, Burst Bus ..............................................................................................10
2.2.3 On-Chip Caches and Data RAM............................................................................11
2.2.4 Priority Interrupt Controller.....................................................................................11
2.2.5 Guarded Memory Unit ...........................................................................................11
2.2.6 Dual Programmable Timers...................................................................................12
2.2.7 Processor Self Test ...............................................................................................12
Instruction Set Summary ....................................................................................................13
2.3
3.0 Package Information ...................................................................................................................14
3.1
3.2
Pin Descriptions..................................................................................................................15
80960Hx Mechanical Data..................................................................................................20
3.2.1 80960Hx PGA Pinout.............................................................................................20
3.2.2 80960Hx PQ4 Pinout .............................................................................................26
Package Thermal Specifications ........................................................................................31
Heat Sink Adhesives...........................................................................................................34
PowerQuad4 Plastic Package ............................................................................................34
Stepping Register Information ............................................................................................34
Sources for Accessories.....................................................................................................36
3.3
3.4
3.5
3.6
3.7
4.0 Electrical Specifications .............................................................................................................37
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Absolute Maximum Ratings................................................................................................37
Operating Conditions..........................................................................................................37
Recommended Connections ..............................................................................................38
VCC5 Pin Requirements (VDIFF) ........................................................................................38
VCCPLL Pin Requirements ................................................................................................39
DC Specifications ...............................................................................................................40
AC Specifications................................................................................................................42
4.7.1 AC Test Conditions................................................................................................45
AC Timing Waveforms........................................................................................................46
4.8
5.0 Bus Waveforms ...........................................................................................................................54
5.1
5.2
80960Hx Boundary Scan Chain .........................................................................................84
Boundary Scan Description Language Example ................................................................88
Figures
1
2
3
4
5
6
80960Hx Block Diagram...............................................................................................................9
80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing Down).........................................20
80960Hx 168-Pin PGA Pinout—View from Bottom (Pins Facing Up) ........................................21
80960Hx 208-Pin PQ4 Pinout.....................................................................................................26
Measuring 80960Hx PGA Case Temperature............................................................................31
80960Hx Device Identification Register......................................................................................34
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7
8
9
VCC5 Current-Limiting Resistor .................................................................................................38
AC Test Load..............................................................................................................................45
CLKIN Waveform........................................................................................................................46
10 Output Delay Waveform .............................................................................................................46
11 Output Delay Waveform .............................................................................................................46
12 Output Float Waveform ..............................................................................................................47
13 Input Setup and Hold Waveform ................................................................................................47
14 NMI, XINT7:0 Input Setup and Hold Waveform..........................................................................47
15 Hold Acknowledge Timings ........................................................................................................48
16 Bus Backoff (BOFF) Timings......................................................................................................48
17 TCK Waveform...........................................................................................................................49
18 Input Setup and Hold Waveforms for TBSIS1 and TBSIH1..........................................................49
19 Output Delay and Output Float for TBSOV1 and TBSOF1 ........................................................50
20 Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 .......................................50
21 Input Setup and Hold Waveform for TBSIS2 and TBSIH2 .........................................................50
22 Rise and Fall Time Derating at 85 ° C and Minimum VCC..........................................................51
23
ICC Active (Power Supply) vs. Frequency...................................................................................51
24 ICC Active (Thermal) vs. Frequency............................................................................................52
25 Output Delay or Hold vs. Load Capacitance ..............................................................................52
26 Output Delay vs. Temperature ...................................................................................................53
27 Output Hold Times vs. Temperature ..........................................................................................53
28 Output Delay vs. VCC ................................................................................................................53
29 Cold Reset Waveform ................................................................................................................54
30 Warm Reset Waveform ..............................................................................................................55
31 Entering ONCE Mode.................................................................................................................56
32 Non-Burst, Non-Pipelined Requests without Wait States...........................................................57
33 Non-Burst, Non-Pipelined Read Request with Wait States........................................................58
34 Non-Burst, Non-Pipelined Write Request with Wait States ........................................................59
35 Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus ........................................60
36 Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus .............................................61
37 Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus ........................................62
38 Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus .............................................63
39 Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus .............................................64
40 Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus ...............................................65
41 Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus ........................................66
42 Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus .............................................67
43 Burst, Pipelined Read Request without Wait States, 32-Bit Bus................................................68
44 Burst, Pipelined Read Request with Wait States, 32-Bit Bus.....................................................69
45 Burst, Pipelined Read Request with Wait States, 8-Bit Bus.......................................................70
46 Burst, Pipelined Read Request with Wait States, 16-Bit Bus.....................................................71
47 Using External READY...............................................................................................................72
48 Terminating a Burst with BTERM ...............................................................................................73
49 BREQ and BSTALL Operation ...................................................................................................74
50 BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle.........................75
51 HOLD Functional Timing ............................................................................................................76
52 LOCK Delays HOLDA Timing.....................................................................................................77
53 FAIL Functional Timing...............................................................................................................77
54 A Summary of Aligned and Unaligned Transfers for 32-Bit Regions..........................................78
55 A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued)......................79
56 A Summary of Aligned and Unaligned Transfers for 16-Bit Bus.................................................80
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Contents
57 A Summary of Aligned and Unaligned Transfers for 8-Bit Bus...................................................81
58 Idle Bus Operation......................................................................................................................82
59 Bus States ..................................................................................................................................83
Tables
1
80960Hx Product Description.......................................................................................................9
2
3
4
5
6
7
8
9
Fail Codes For BIST (bit 7 = 1)...................................................................................................12
Remaining Fail Codes (bit 7 = 0)................................................................................................12
80960Hx Instruction Set .............................................................................................................13
80960HA/HD/HT Package Types and Speeds...........................................................................14
Pin Description Nomenclature ....................................................................................................15
80960Hx Processor Family Pin Descriptions..............................................................................16
80960Hx 168-Pin PGA Pinout—Signal Name Order..................................................................22
80960Hx 168-Pin PGA Pinout—Pin Number Order ...................................................................24
10 80960Hx PQ4 Pinout—Signal Name Order................................................................................27
11 80960Hx PQ4 Pinout—Pin Number Order .................................................................................29
13 80960Hx 168-Pin PGA Package Thermal Characteristics .........................................................32
12 Maximum TA at Various Airflows in ° C (PGA Package Only) .....................................................32
15 80960Hx 208-Pin PQ4 Package Thermal Characteristics..........................................................33
14 Maximum TA at Various Airflows in ° C (PQ4 Package Only)......................................................33
17 80960Hx Device ID Model Types ...............................................................................................35
18 Device ID Version Numbers for Different Steppings...................................................................35
16 Fields of 80960Hx Device ID ......................................................................................................35
19 Absolute Maximum Ratings........................................................................................................37
20 Operating Conditions..................................................................................................................37
21
VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) ......................................39
22 80960Hx DC Characteristics ......................................................................................................40
23 80960Hx AC Characteristics.......................................................................................................42
25 80960Hx Boundary Scan Test Signal Timings ...........................................................................44
24 AC Characteristics Notes............................................................................................................44
26 80960Hx Boundary Scan Chain .................................................................................................84
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Contents
Revision History
Date
Revision
History
Formatted the datasheet in a new template.
In “32-Bit Parallel Architecture” on page 1:
•
•
Removed operating frequency of 16/32 (bus/core) from 80960HD.
Removed operating frequency of 20/60 (bus/core) from 80960HT.
In Table 5 “80960HA/HD/HT Package Types and Speeds” on page 14:
•
Removed core speed of 32 MHz and bus speed of 16 MHz, and order
number A80960HD32-S-L2GG from the 168L PGA package, 80960HD
device.
September 2002
008
•
•
Removed core speed of 60 MHz and bus speed of 20 MHz, and order
number A80960HT60 from the 168L PGA package, 80960HT device.
Removed core speed of 32 MHz and bus speed of 16 MHz, and order
number FC80960HD32-S-L2GL from the 208L PQFP package,
80960HD device.
•
Removed core speed of 60 MHz and bus speed of 20 MHz, and order
number FC80960HT60-S-L2G2 from the 208L PQFP package,
80960HT device.
In “32-Bit Parallel Architecture” on page 1:
•
Revised 1.2 Gbyte Internal Bandwidth (75 MHz) to 1.28 Gbyte Internal
Bandwidth (80 MHz).
In Section 3.0, “Package Information” on page 14:
•
Added paragraph two and Table 5 “80960HA/HD/HT Package Types
and Speeds” on page 14.
In Table 7 “80960Hx Processor Family Pin Descriptions” on page 16:
•
•
•
•
Corrected minor typeset and spacing errors.
BREQ; Revised description.
ONCE; last sentence, changed ‘low’ to ‘high’.
TDI and TMS; removed last sentence stating, “Pull this pin low when
not in use.”
In Figure 2 “80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing
Down)” on page 20:
July 1998
007
•
Added insert package marking diagram.
In Figure 4 “80960Hx 208-Pin PQ4 Pinout” on page 26:
Added insert package marking diagram.
In Table 10 “80960Hx PQ4 Pinout—Signal Name Order” on page 27:
Corrected TDO (‘O’ was zero) and revised alphabetical ordering.
In Table 11 “80960Hx PQ4 Pinout—Pin Number Order” on page 29:
Corrected TDO (‘O’ was zero) and revised alphabetical ordering.
In Section 4.1, “Absolute Maximum Ratings” on page 37:
Revised V to VCC5 for Voltage on Other Pins with respect to V
•
•
•
•
.
SS
CC
In Section 4.5, “VCCPLL Pin Requirements” on page 39:
Added section.
In Table 22 “80960Hx DC Characteristics” on page 40:
•
•
•
Added footnote (1) to I notes column for TDO pin.
LO
Added footnote (10) to C , C
and C pin.
I/O
IN
OUT
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Date
Revision
History
In Table 23 “80960Hx AC Characteristics” on page 42:
•
•
•
Added overbars where required.
Modified T
Modified T
to list separate specifications for 3.3 V and 5 V.
DVNH
, T
and T
to reflect specific 80960HA, 80960HD
OV2 OH2
TVEL
and 80960HT values.
July 1998
007
(continued)
(continued) In Figure 23 “ICC Active (Power Supply) vs. Frequency” on page 51:
Changed ‘5’ to ‘0’ on the CLKIN Frequency axis.
In Figure 49 “BREQ and BSTALL Operation” on page 74:
Added figure and following text.
•
•
August 1997
006
Fixed several font and format issues.
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8
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80960HA/HD/HT
1.0
About This Document
This document describes the parametric performance of Intel’s 80960Hx embedded superscalar
microprocessors. Detailed descriptions for functional topics, other than parametric performance,
are published in the i960® Hx Microprocessor User’s Guide (272484).
In this document, ‘80960Hx’ and ‘i960 Hx processor’ refer to the products described in Table 1.
Throughout this document, information that is specific to each is clearly indicated.
Figure 1. 80960Hx Block Diagram
Instruction Prefetch Queue
Guarded Memory Unit
Control
JTAG Port
Timers
Instruction Cache
Memory Region Configuration
Bus Controller
16 Kbyte, Four-Way Set-Associative
Address
Data
128-Bit Cache Bus
Bus Request Queues
Interrupt
Port
Programmable
Interrupt Controller
Parallel Instruction Scheduler
Data Cache
8 Kbyte, Four-Way Set-Associative
Multiply/Divide Unit
Execution Unit
Data RAM - 2 Kbyte
Memory-Side
Machine Bus
Register-Side
Machine Bus
Register Cache - 5 to 15 sets
Six-Port Register File
Address Generation Unit
64-bit SRC1 Bus 32-bit Base Bus
64-bit SRC2 Bus 128-bit Load Bus
128-bit Store Bus
64-bit DST Bus
2.0
Intel 80960Hx Processor
The Intel 80960Hx processor provides new performance levels while maintaining backward
compatibility (pin1 and software) with the i960 CA/CF processor. This newest member of the
family of i960 32-bit, RISC-style, embedded processors allows customers to create scalable
designs that meet multiple price and performance points. This is accomplished by providing
processors that may run at the bus speed or faster using Intel’s clock multiplying technology
(see Table 1). The 80960Hx core is capable of issuing 150 million instructions per second, using a
sophisticated instruction scheduler that allows the processor to sustain a throughput of two
instructions every core clock, with a peak performance of three instructions per clock. The
80960Hx-series comprises three processors, which differ in the ratio of core clock speed to external
bus speed.
Table 1. 80960Hx Product Description
Product
80960HA
Core
1x
Voltage
Operating Frequency (bus/core)
3.3 V†
3.3 V†
3.3 V†
25/25, 33/33, 40/40
25/50, 33/66, 40/80
25/75
80960HD
80960HT
2x
3x
†
Processor inputs are 5 V tolerant.
1. The 80960Hx is not “drop-in” compatible in an 80960Cx-based system. Customers may design systems that accept either 80960Hx or Cx
processors.
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80960HA/HD/HT
In addition to expanded clock frequency options, the 80960Hx provides essential enhancements for
an emerging class of high-performance embedded applications. Features include a larger
instruction cache, data cache, and data RAM than any other 80960 processor to date. It also boasts
a 32-bit demultiplexed and pipelined burst bus, fast interrupt mechanism, guarded memory unit,
wait state generator, dual programmable timers, ONCE and IEEE 1149.1-compliant boundary scan
test and debug support, and new instructions.
2.1
The i960® Processor Family
The i960® processor family is a 32-bit RISC architecture created by Intel to serve the needs of
embedded applications. The embedded market includes applications as diverse as industrial
automation, avionics, image processing, graphics and communications.
Because all members of the i960 processor family share a common core architecture, i960
applications are code-compatible. Each new processor in the family adds its own special set of
functions to the core to satisfy the needs of a specific application or range of applications in the
embedded market.
2.2
Key 80960Hx Features
2.2.1
Execution Architecture
Independent instruction paths inside the processor allow the execution of multiple, out-of-sequence
instructions per clock. Register and resource scoreboarding interlocks maintain the logical integrity
of sequential instructions that are being executed in parallel. To sustain execution of multiple
instructions in each clock cycle, the processor decodes multiple instructions in parallel and
simultaneously issues these instructions to parallel processing units. The various processing units
are then able to independently access instruction operands in parallel from a common register set.
Local Register Cache integrated on-chip provides automatic register management on call/return
instructions. Upon a call instruction, the processor allocates a set of local registers for the called
procedure, then stores the registers for the previous procedure in the on-chip register cache. As
additional procedures are called, the cache stores the associated registers such that the most recently
called procedure is the first available by the next return (ret) instruction. The processor may store up
to fifteen register sets, after which the oldest sets are stored (spilled) into external memory.
The 80960Hx supports the 80960 architecturally-defined branch prediction mechanism. This
allows many branches to execute with no pipeline break. With the 80960Hx’s efficient pipeline, a
branch may take as few as zero clocks to execute. The maximum penalty for an incorrect prediction
is two core clocks.
2.2.2
Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces the 80960Hx core to the external memory and
peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at a
40 MHz external bus clock frequency). A key advantage of this design is its versatility. The user
may independently program the physical and logical attributes of system memory. Physical
attributes include wait state profile, bus width, and parity. Logical attributes include cacheability
and Big or Little Endian byte order. Internally programmable wait states and 16 separately
configurable physical memory regions allow the processor to interface with a variety of memory
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80960HA/HD/HT
subsystems with minimum system complexity. To reduce the effect of wait states, the bus design is
decoupled from the core. This lets the processor execute instructions while the bus performs
memory accesses independently.
The Bus Controller’s key features include:
• Demultiplexed, Burst Bus to support most efficient DRAM access modes
• Address Pipelining to reduce memory cost while maintaining performance
• 32-, 16- and 8-bit modes to facilitate I/O interfacing
• Full internal wait state generation to reduce system cost
• Little and Big Endian support
• Unaligned Access support implemented in hardware
• Three-deep request queue to decouple the bus from the core
• Independent physical and logical address space characteristics
2.2.3
2.2.4
On-Chip Caches and Data RAM
As shown in Figure 1, the 80960Hx provides generous on-chip cache and storage features to
decouple CPU execution from the external bus. The processor includes a 16 Kbyte instruction
cache, an 8 Kbyte data cache and 2 Kbytes of Data RAM. The caches are organized as 4-way set
associative. Stores that hit the data cache are written through to memory. The data cache performs
write allocation on cache misses. A fifteen-set stack frame cache allows the processor to rapidly
allocate and deallocate local registers. All of the on-chip RAM sustains a 4-word (128-bit) access
every clock cycle.
Priority Interrupt Controller
The interrupt unit provides the mechanism for the low latency and high throughput interrupt
service essential for embedded applications. A priority interrupt controller provides full
programmability of 240 interrupt sources with a typical interrupt task switch (latency) time of 17
core clocks. The controller supports 31 priority levels. Interrupts are prioritized and signaled within
10 core clocks of the request. When the interrupt has a higher priority than the processor priority,
the context switch to the interrupt routine would typically complete in another seven bus clocks.
External agents post interrupts through the 8-bit external interrupt port. The Interrupt unit also
handles the two internal sources from the Timers. Interrupts may be level- or edge-triggered.
2.2.5
Guarded Memory Unit
The Guarded Memory Unit (GMU) provides memory protection without the address translation
found in Memory Management Units. The GMU contains two memory protection schemes: one
prevents illegal memory accesses, the other detects memory access violations. Both signal a fault
to the processor. The programmable protection modes are: user read, write or execute; and
supervisor read, write or execute.
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80960HA/HD/HT
2.2.6
Dual Programmable Timers
The processor provides two independent 32-bit timers, with four programmable clock rates. The
user configures the timers through the Timer Unit registers. These registers are memory-mapped
within the 80960Hx, addressable on 32-bit boundaries. The timers have a single-shot mode and
auto-reload capabilities for continuous operation. Each timer has an independent interrupt request
to the processor’s interrupt controller.
2.2.7
Processor Self Test
When a system error is detected, the FAIL pin is asserted, a fail code message is driven onto the
address bus, and the processor stops execution at the point of failure. The only way to resume
normal operation is to perform a RESET operation. Because System Error generation may occur
sometime after the bus confidence test and even after initialization during normal processor
operation, the FAIL pin is HIGH (logic “1”) before the detection of a System Error.
The processor uses only one read bus-transaction to signal the fail code message; the address of the
bus transaction is the fail code itself. The fail code is of the form: 0xfeffffnn; bits 6 to 0 contain a
mask recording the possible failures. Bit 7, when set to 1, indicates that the mask contains failures
from the internal Built-In Self-Test (BIST); when 0, the mask indicates other failures.
Ignore reserved bits 0 and 1. Also ignore bits 5 and 6 when bit 7 is clear (=0).
The mask is shown in Table 2 and Table 3.
Table 2. Fail Codes For BIST (bit 7 = 1)
Bit
When Set
6
5
4
3
2
1
0
On-chip Data-RAM failure detected by BIST.
Internal Microcode ROM failure detected by BIST.
Instruction cache failure detected by BIST.
Data cache failure detected by BIST.
Local-register cache or processor core failure detected by BIST.
Reserved. Always zero.
Reserved. Always zero.
Table 3. Remaining Fail Codes (bit 7 = 0)
Bit
When Set
6
5
4
3
2
1
0
Reserved. Always one.
Reserved. Always one.
A data structure within the IMI is not aligned to a word boundary.
A System Error during normal operation has occurred.
The Bus Confidence test has failed.
Reserved. Always zero.
Reserved. Always zero.
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80960HA/HD/HT
2.3
Instruction Set Summary
Table 4 summarizes the 80960Hx instruction set by logical groupings.
Table 4. 80960Hx Instruction Set
Data Movement
Arithmetic
Logical
Bit / Bit Field / Byte
Add
Subtract
Multiply
Divide
And
Set Bit
Not And
And Not
Or
Clear Bit
Remainder
Not Bit
Load
Modulo
Alter Bit
Store
Shift
Exclusive Or
Not Or
Scan For Bit
Span Over Bit
Extract
Move
Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
Rotate
Load Address
Conditional Select2
Or Not
Nor
Modify
Exclusive Nor
Not
Scan Byte for Equal
Byte Swap2
Nand
Conditional Add2
Conditional Subtract2
Comparison
Branch
Call/Return
Fault
Compare
Conditional Compare
Compare and Increment
Compare and Decrement
Compare Byte2
Compare Short2
Test Condition Code
Check Bit
Call
Unconditional Branch
Conditional Branch
Compare and Branch
Call Extended
Call System
Return
Conditional Fault
Synchronize Faults
Branch and Link
Debug
Processor Mgmt
Atomic
Cache Control
Flush Local Registers
Modify Arithmetic Controls
Modify Process Controls
Interrupt Enable/ Disable1, 2
System Control1
Modify Trace Controls
Mark
Instruction Cache
Control1, 2
Data Cache Control1, 2
Atomic Add
Atomic Modify
Force Mark
NOTES:
1. 80960Hx extensions to the 80960 core instruction set.
2. 80960Hx extensions to the 80960Cx instruction set.
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80960HA/HD/HT
3.0
Package Information
This section describes the pins, pinouts and thermal characteristics for the 80960Hx in the 168-pin
ceramic Pin Grid Array (PGA) package, 208-pin PowerQuad2* (PQ4). For complete package
specifications and information, see the Intel Packaging Handbook (Order# 240800).
The 80960HA/HD/HT is offered with eight speeds and two package types (Table 5). Both the
168-pin ceramic Pin Grid Array (PGA) and the 208-pin PowerQuad2* (PQ4) devices are specified
for operation at VCC = 3.3 V ± 0.15 V over a case temperature range of 0 °C to 85 °C.
Table 5. 80960HA/HD/HT Package Types and Speeds
Core Speed
Bus Speed
(MHz)
Package/Name
Device
Order #
(MHz)
25
33
40
A80960HA25 S L2GX
A80960HA33 S L2GY
A80960HA40 S L2GZ
A80960HD50 S L2GH
A80960HD66 S L2GJ
A80960HD80 S L2GK
A80960HT75 S L2GP
80960HA
168L PGA
50
66
80
75
25
33
40
25
80960HD
80960HT
25
33
40
FC80960HA25 S L2GU
FC80960HA33 S L2GV
FC80960HA40 S L2GW
FC80960HD50 S L2GM
FC80960HD66 S L2GN
FC80960HD80 S L2LZ
FC80960HT75 S L2GT
80960HA
208L PQFP
(also known as PQ4)
50
66
80
75
25
33
40
25
80960HD
80960HT
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80960HA/HD/HT
3.1
Pin Descriptions
This section defines the 80960Hx pins. Table 6 presents the legend for interpreting the pin
descriptions in Table 7. All pins float while the processor is in the ONCE mode, except TDO,
which may be driven active according to normal JTAG specifications.
Table 6. Pin Description Nomenclature
Symbol
Description
I
O
I/O
-
Input only pin.
Output only pin.
Pin may be input or output.
Pin must be connected as indicated for proper device functionality.
Synchronous edge sensitive input. This input must meet the setup and hold times relative to
CLKIN to ensure proper operation of the processor.
S(E)
S(L)
Synchronous level sensitive input. This input must meet the setup and hold times relative to
CLKIN to ensure proper operation of the processor.
A(E)
A(L)
Asynchronous edge-sensitive input.
Asynchronous level-sensitive input.
While the processor bus is in the HOLD state (HOLDA asserted), the pin:
H(1) is driven to V
H(0) is driven to V
H(Z) floats
CC
SS
H(...)
B(...)
R(...)
H(Q) continues to be a valid output
While the processor is in the bus backoff state (BOFF asserted), the pin:
B(1) is driven to V
B(0) is driven to V
B(Z) floats
CC
SS
B(Q) continues to be a valid output
While the processor’s RESET pin is asserted, the pin:
R(1) is driven to V
R(0) is driven to V
R(Z) floats
CC
SS
R(Q) continues to be a valid output
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80960HA/HD/HT
Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4)
Name
Type
Description
ADDRESS BUS carries the upper 30 bits of the physical address. A31 is the most
significant address bit and A2 is the least significant. During a bus access, A31:2
identify all external addresses to word (4-byte) boundaries. The byte enable
signals indicate the selected byte in each word. During burst accesses, A3 and
A2 increment to indicate successive addresses.
O
H(Z)
B(Z)
R(Z)
A31:2
I/O
DATA BUS carries 32, 16, or 8-bit data quantities depending on bus width
configuration. The least significant bit of the data is carried on D0 and the most
significant on D31. The lower eight data lines (D7:0) are used when the bus is
configured for 8-bit data. When configured for 16-bit data, D15:0 are used.
S(L)
H(Z)
B(Z)
R(Z)
D31:0
DATA PARITY carries parity information for the data bus. Each parity bit is
assigned a group of eight data bus pins as follows:
I/O
DP3 generates/checks parity for D31:24
DP2 generates/checks parity for D23:16
DP1 generates/checks parity for D15:8
DP0 generates/checks parity for D7:0
S(L)
H(Z)
B(Z)
R(Z)
DP3:0
PCHK
Parity information is generated for a processor write cycle and is checked for a
processor read cycle. Parity checking and polarity are programmable. Parity
generation/checking is only performed for the size of the data accessed.
O
PARITY CHECK indicates the result of a parity check operation. An asserted
PCHK indicates that the previous bus read access resulted in a parity check error.
H(Q)
B(Q)
R(1)
BYTE ENABLES select which of the four bytes addressed by A31:2 are active
during a bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
32-bit bus:
BE3 enables D31:24
BE2 enables D23:16
BE1 enables D15:8
BE0 enables D7:0
O
H(Z)
B(Z)
R(1)
16-bit bus:
BE3:0
BE3 becomes Byte High Enable (enables D15:8)
BE2 is not used (state is undefined)
BE1 becomes Address Bit 1 (A1)
BE0 becomes Byte Low Enable (enables D7:0)
8-bit bus:
BE3 is not used (state is undefined)
BE2 is not used (state is undefined)
BE1 Address Bit 1 (A1)
BE0 Address Bit 0 (A0)
WRITE/READ is low for read accesses and high for write accesses.
W/R becomes valid during the address phase of a bus cycle and remains valid
until the end of the cycle for non-pipelined accesses. For pipelined accesses, W/
R changes state when the next address is presented.
O
H(Z)
B(Z)
R(0)
W/R
D/C
0= Read
1= Write
O
DATA/CODE indicates that a bus access is a data access or an instruction
access. D/C has the same timing as W/R.
H(Z)
B(Z)
R(0)
0 = Code
1 = Data
16
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80960HA/HD/HT
Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 2 of 4)
Name
Type
Description
SUPERVISOR ACCESS indicates whether the current bus access originates
from a request issued while in supervisor mode or user mode. SUP may be used
by the memory subsystem to isolate supervisor code and data structures from
non-supervisor access.
O
H(Z)
B(Z)
R(1)
SUP
0 = Supervisor Mode
1 = User Mode
O
ADDRESS STROBE indicates a valid address and the start of a new bus access.
ADS is asserted for the first clock of a bus access.
H(Z)
B(Z)
R(1)
ADS
READY, when enabled for a memory region, is asserted by the memory
subsystem to indicate the completion of a data transfer. READY is used to
indicate that read data on the bus is valid, or that a write transfer has completed.
READY works in conjunction with the internal wait state generator to
accommodate various memory speeds. READY is sampled after any
programmed wait states:
I
READY
S(L)
During each data cycle of a burst access
During the data cycle of a non-burst access
BURST TERMINATE, when enabled for a memory region, is asserted by the
memory subsystem to terminate a burst access in progress. When BTERM is
asserted, the current burst access is terminated and another address cycle
occurs.
I
BTERM
WAIT
S(L)
O
WAIT indicates the status of the internal wait-state generator. WAIT is asserted
H(Z)
B(Z)
R(1)
when the internal wait state generator generates N
, N
, N
and N
WAD
RAD
WDD RDD
wait states. WAIT may be used to derive a write data strobe.
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in
the last data transfer of burst and non-burst accesses after the internal wait-state
generator reaches zero. BLAST remains active as long as wait states are inserted
through the READY pin. BLAST becomes inactive after the final data transfer in a
bus cycle.
O
H(Z)
B(Z)
R(1)
BLAST
DT/R
DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is
used with DEN to provide control for data transceivers connected to the data bus.
DT/R is driven low to indicate the processor expects data (a read cycle). DT/R is
driven high when the processor is “transmitting” data (a store cycle). DT/R only
changes state when DEN is high.
O
H(Z)
B(Z)
R(0)
0 = Data Receive
1 = Data Transmit
DATA ENABLE indicates data transfer cycles during a bus access. DEN is
asserted at the start of the first data cycle in a bus access and de-asserted at the
end of the last data cycle. DEN remains asserted for an entire bus request, even
when that request spans several bus accesses. For example, a ldq instruction
starting at an unaligned quad word boundary is one bus request spanning at least
two bus accesses. DEN remains asserted throughout all the accesses (including
ADS states) and de-asserts when the Iqd instruction request is satisfied. DEN is
used with DT/R to provide control for data transceivers connected to the data bus.
DEN remains asserted for sequential reads from pipelined memory regions.
O
H(Z)
B(Z)
R(1)
DEN
BUS LOCK indicates that an atomic read-modify-write operation is in progress.
LOCK may be used by the memory subsystem to prevent external agents from
accessing memory that is currently involved in an atomic operation (e.g., a
semaphore). LOCK is asserted in the first clock of an atomic operation and de-
asserted when BLAST is deasserted in the last bus cycle.
O
H(Z)
B(Z)
R(1)
LOCK
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80960HA/HD/HT
Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)
Name
Type
Description
HOLD REQUEST signals that an external agent requests access to the
processor’s address, data, and control buses. When HOLD is asserted, the
processor:
I
Completes the current bus request.
HOLD
S(L)
Asserts HOLDA and floats the address, data, and control buses.
When HOLD is deasserted, the HOLDA pin is deasserted and the processor
reassumes control of the address, data, and control pins.
O
HOLD ACKNOWLEDGE indicates to an external master that the processor has
relinquished control of the bus. The processor grants HOLD requests and enters
the HOLDA state while the RESET pin is asserted.
H(1)
B(0)
R(Q)
HOLDA
BOFF
HOLDA is never granted while LOCK is asserted.
BUS BACKOFF forces the processor to immediately relinquish control of the bus
on the next clock cycle. When READY/BTERM is enabled and:
When BOFF is asserted, the address, data, and control buses are floated on the
next clock cycle and the current access is aborted.
I
S(L)
When BOFF is deasserted, the processor resumes by regenerating the aborted
bus access.
See Figure 16 on page 48 for BOFF timing requirements.
O
BUS REQUEST indicates that a bus request is pending in the bus controller.
BREQ does not indicate whether or not the processor is stalled. See BSTALL for
processor stall status. BREQ may be used with BSTALL to indicate to an external
bus arbiter the processor’s bus ownership requirements.
H(Q)
B(Q)
R(0)
BREQ
O
BUS STALL indicates that the processor has stalled pending the result of a
request in the bus controller. When BSTALL is asserted, the processor must
regain bus ownership to continue processing (i.e., it may no longer execute
strictly out of on-chip cache memory).
H(Q)
B(Q)
R(0)
BSTALL
CYCLE TYPE indicates the type of bus cycle currently being started or processor
state. CT3:0 encoding follows:
Cycle Type
ADSCT3:0
Program-initiated access using 8-bit bus
Program-initiated access using 16-bit bus
Program-initiated access using 32-bit bus
Event-initiated access using 8-bit bus
Event-initiated access using 16-bit bus
Event-initiated access using 32-bit bus
Reserved
00000
00001
00010
00100
00101
00110
00X11
01XXX
1XXXX
O
H(Z)
B(Z)
R(Z)
CT3:0
Reserved for future products
Reserved
EXTERNAL INTERRUPT pins are used to request interrupt service. These pins
may be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated
inputs may be programmed to be level (low or high) or edge (rising or falling)
sensitive.
I
XINT7:0
A(E)
A(L)
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt
pins are level sensitive in this mode.
Mixed Mode: The XINT7:5 pins act as dedicated sources and the XINT4:0 pins
act as the five most significant bits of a vectored source. The least significant bits
of the vectored source are set to “010” internally.
I
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source. NMI is falling edge triggered.
NMI
A(E)
18
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80960HA/HD/HT
Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 4 of 4)
Name
Type
Description
CLOCK INPUT provides the time base for the 80960Hx. All internal circuitry is
synchronized to CLKIN. All input and output timings are specified relative to
CLKIN.
CLKIN
I
For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN
frequency by two. For the 80960HT, the 3x internal clock is derived by multiplying
the CLKIN frequency by three.
RESET forces the device into reset. RESET causes all external and internal
signals to return to their reset state (when defined). The rising edge of RESET
starts the processor boot sequence.
I
RESET
STEST
A(L)
I
SELF TEST, when asserted during the rising edge of RESET, causes the
processor to execute its built in self-test.
S(L)
FAIL indicates a failure of the processor’s built-in self-test performed during
initialization. FAIL is asserted immediately out of reset and toggles during self-test
to indicate the status of individual tests. When self-test passes, FAIL is de-
asserted and the processor branches to the user’s initialization code. When self-
test fails, the FAIL pin asserts and the processor ceases execution.
O
H(Q)
B(Q)
R(0)
FAIL
ON-CIRCUIT EMULATION control: the processor samples this pin during reset.
When it is asserted low at the end of reset, the processor enters ONCE mode. In
ONCE mode, the processor stops all clocks and floats all output pins except the
ONCE
I
TDO pin. ONCE uses an internal pull-up resistor; see R definition in Table 22,
PU
“80960Hx DC Characteristics” on page 40. Pull this pin high when not in use.
TEST CLOCK provides the clocking function for IEEE 1149.1 Boundary Scan
testing.
TCK
TDI
I
I
TEST DATA INPUT is the serial input pin for IEEE 1149.1 Boundary Scan testing.
TDI uses an internal pull-up resistor; see R definition in Table 22, “80960Hx DC
PU
Characteristics” on page 40.
TEST DATA OUTPUT is the serial output pin for IEEE 1149.1 Boundary Scan
testing. ONCE does not disable this pin.
TDO
O
TEST RESET asynchronously resets the Test Access Port (TAP) controller. TRST
must be held low at least 10,000 clock cycles after power-up. One method is to
provide TRST with a separate power-on-reset circuit. TRST includes an internal
TRST
TMS
I
I
pull-up resistor; see R definition in Table 22, “80960Hx DC Characteristics” on
PU
page 40. Pull this pin low when not in use.
TEST MODE SELECT is sampled at the rising edge of TCK. TCK controls the
sequence of TAP controller state changes for IEEE 1149.1 Boundary Scan
testing. TMS uses an internal pull-up resistor; see R definition in Table 22,
PU
“80960Hx DC Characteristics” on page 40.
5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O
buffers. Connect this signal to +5 V for use with inputs which exceed 3.3 V. When
all inputs are from 3.3 V components, connect this signal to 3.3 V.
VCC5
I
I
VCCPLL
PLL VOLTAGE is the +3.3 VDC analog input for the PLL.
VOLTAGE DETECT signal allows external system logic to distinguish between a
5 V 80960Cx processor and the 3.3 V 80960Hx processor. This signal is active
low for a 3.3 V 80960Hx (it is high impedance for 5 V 80960Cx). This pin is
available only on the PGA version.
VOLDET
O
0 = 80960Hx
1 = 80960Cx
Datasheet
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80960HA/HD/HT
3.2
80960Hx Mechanical Data
3.2.1
80960Hx PGA Pinout
Figure 2 depicts the complete 80960Hx PGA pinout as viewed from the top side of the component
(i.e., pins facing down). Figure 3 shows the complete 80960Hx PGA pinout as viewed from the
pin-side of the package (i.e., pins facing up). Table 9 lists the 80960Hx pin names with package
location. See Section 4.3, “Recommended Connections” on page 38 for specifications and
recommended connections.
Figure 2. 80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing Down)
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
1
2
D25
D29
D24
D27
D21
D23
D26
D19
D20
D22
D17
D18
D16
D15
D14
D13
D12
D11
D10
D9
D8
D6
D7
D4
D0
D5
D2
NC
D3
BOFF
V
SS
V
V
V
V
D1 STEST FAIL
CC
SS
CC
SS
CC
CC
3
3
READY D31
V
V
V
V
V
V
V
V
CC
ONCE DP1
DP0
DP2
CC
SS
SS
SS
SS
4
4
V
DP3
HOLDA BTERM D28
SS
5
5
HOLD D30
BE3
VCC5 TCK VOLDET
6
6
V
V
TMS
CC
TRST
TDI
CC
BE2
ADS
7
7
V
V
V
V
V
CC
SS
SS
SS
SS
CC
BE1
8
8
A80960Hx
V
CC
V
V
V
V
V
PCHK
TDO
NC
BLAST
9
9
V
SS
V
DEN
W/R
BE0
SS
SS
SS
CC
M
© 19xx
i
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
V
V
V
VCCPLL
CC
SS
SS
NC
CTO
CT1
V
V
XXXXXXXX SS
CC
CC
DT/R
V
WAIT BSTALL SUP
D/C BREQ A30
SS
CC
CLKIN
NC
NC
CT2
CT3
LOCK A29
A28
V
CC
A31
A27
A26
A23
A24
A21
A20
A19
V
V
V
V
V
V
V
V
V
V
V
V
CC
NMI XINT4 XINT0 XINT1
CC
SS
SS
SS
SS
SS
SS
SS
A16
V
A13
V
A7
A4
A2
A3
CC
CC
CC
CC
CC
XINT6 XINT3 RESET
XINT7 XINT5 XINT2
A25
A22
A18
A17
A15
A14
A12
A11
A10
A9
A8
A6
A5
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
20
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80960HA/HD/HT
Figure 3. 80960Hx 168-Pin PGA Pinout—View from Bottom (Pins Facing Up)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
1
2
1
2
V
BOFF
D3
D1
D5
D2
NC
D7
D4
D0
D8
D6
D9
D11
D10
D12
D13
D15
D14
D16
D17
D18
D19
D20
D22
D21
D23
D26
D24
D27
D25
D29
SS
FAIL
STEST
V
V
V
V
V
V
V
CC
CC
CC
CC
3
3
DP0
DP2
DP1 ONCE
DP3
V
V
V
V
SS
V
CC
D31 READY
CC
SS
SS
SS
SS
SS
4
4
V
SS
D28 BTERM HOLDA
D30 HOLD BE3
5
5
VOLDET TCK VCC5
6
6
TRST
TDI
V
TMS
CC
SS
V
V
ADS
BE2
BE1
CC
7
7
V
V
CC
V
V
SS
CC
CC
8
8
TDO
NC
PCHK
V
V
V
V
BLAST
DEN
SS
SS
SS
SS
Package Lid
9
9
V
CC
BE0
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
V
VCCPLL
SS
NC
V
V
V
V
W/R
SS
SS
CC
CT0
CT1
V
V
V
V
DT/R
CC
CC
SS
SS
CC
SUP BSTALL WAIT
A30 BREQ D/C
CT2
CT3
NC
NC
CLKIN
V
A28
A24
A21
A29
A26
A23
LOCK
A31
CC
XINT1 XINT0 XINT4 NMI
V
V
V
V
V
V
V
V
V
SS
V
V
CC
A20
A19
CC
SS
SS
SS
SS
SS
SS
RESET XINT3 XINT6
XINT2 XINT5 XINT7
A2
A4
V
A7
V
A13
V
A16
A27
CC
CC
CC
CC
CC
A3
A5
A6
A8
A9
A10
A11
A12
A14
A15
A17
A18
A22
A25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
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80960HA/HD/HT
Table 8. 80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet 1 of 2)
PGA
Pin
PGA
Pin
PGA
Pin
PGA
Pin
Signal Name
Signal Name
Signal Name
Signal Name
A2
A3
D16
D17
E16
E17
F17
G16
G17
H17
J17
ADS
BE0
BE1
BE2
BE3
BLAST
BOFF
BREQ
BSTALL
BTERM
CLKIN
CT0
CT1
CT2
CT3
D/C
R6
R9
S7
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
DEN
DP0
DP1
DP2
DP3
DT/R
FAIL
—
L2
L1
LOCK
NC
S14
A9
A4
M1
N1
N2
P1
P2
Q1
P3
Q2
R1
S1
Q3
R2
Q4
S2
Q5
R3
S9
A3
B3
A4
B4
S11
A2
—
NC
A10
B13
B14
D3
A5
S6
NC
A6
S5
NC
A7
S8
NC
A8
B1
NMI
D15
C3
A9
R13
R12
R4
C13
A11
A12
A13
A14
S13
E3
ONCE
PCHK
READY
RESET
STEST
SUP
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
B8
K17
L17
L16
M17
N17
N16
P17
Q17
P16
P15
Q16
R17
R16
Q15
S17
R15
S16
Q14
R14
Q13
S15
S3
A16
B2
Q12
B5
TCK
TDI
A7
TDO
TMS
TRST
A8
D0
B6
D1
C2
D2
C1
E2
A6
D2
V
V
V
V
V
V
V
V
V
V
V
V
B7
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
D3
B9
D4
B11
B12
C6
D5
D1
F2
D6
D7
E1
C14
E15
F3
D8
F1
D9
G1
H2
H1
J1
D10
D11
—
—
F16
G2
—
—
D12
D13
HOLD
HOLDA
R5
S4
H16
J2
K1
22
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80960HA/HD/HT
Table 8. 80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet 2 of 2)
PGA
Pin
PGA
Pin
PGA
Pin
PGA
Pin
Signal Name
Signal Name
Signal Name
Signal Name
V
V
V
V
V
V
V
V
V
V
V
V
J16
K2
VCCPLL
VOLDET
B10
A5
V
V
V
V
V
V
V
V
V
V
V
V
V
H3
H15
J3
V
V
Q10
Q11
S10
S12
B15
A15
A17
B16
C15
B17
C16
C17
—
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
K16
M2
V
V
V
V
V
V
V
V
V
V
V
A1
W/R
WAIT
XINT0
XINT1
XINT2
XINT3
XINT4
XINT5
XINT6
XINT7
—
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
C4
J15
K3
M16
N3
C7
C8
K15
L3
N15
Q6
C9
C10
C11
C12
F15
G3
L15
M3
M15
Q7
R7
R8
R10
R11
C5
Q8
VCC5
G15
Q9
Datasheet
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80960HA/HD/HT
Table 9. 80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet 1 of 2)
PGA
Pin
PGA
Pin
PGA
Pin
PGA
Pin
Signal Name
Signal Name
Signal Name
Signal Name
A1
A2
V
B14
B15
B16
B17
C1
NC
XINT0
XINT3
XINT5
D3
E15
E16
E17
F1
V
K15
K16
K17
L1
V
SS
CC
SS
FAIL
DP0
A4
V
CC
A3
A5
D8
D6
A11
D15
D14
A4
DP2
A5
VOLDET
TRST
TDI
F2
L2
A6
C2
D1
F3
V
L3
V
V
CC
SS
CC
SS
SS
A7
C3
ONCE
F15
F16
F17
G1
V
V
L15
L16
L17
M1
A8
TDO
NC
C4
V
A13
A12
D16
SS
A9
C5
VCC5
A6
D9
A10
A11
A12
A13
A14
A15
A16
A17
B1
NC
C6
V
V
V
V
V
V
V
CC
SS
SS
SS
SS
SS
SS
CT0
C7
G2
V
M2
V
CC
CC
SS
SS
CT1
C8
G3
V
V
M3
V
V
SS
SS
CC
CT2
C9
G15
G16
G17
H1
M15
M16
M17
N1
CT3
C10
C11
C12
C13
C14
C15
C16
C17
D1
A7
V
XINT1
RESET
XINT2
BOFF
STEST
DP1
A8
A14
D17
D18
D11
D10
CLKIN
H2
N2
V
H3
V
V
V
N3
V
V
CC
SS
SS
CC
CC
CC
B2
XINT4
XINT6
XINT7
D5
H15
H16
H17
J1
N15
N16
N17
P1
B3
A16
A15
D19
D20
D22
A20
A19
A17
D21
D23
D26
B4
DP3
A9
D12
B5
TCK
B6
TMS
D2
D2
J2
V
V
V
V
P2
CC
SS
SS
CC
B7
V
D3
NC
J3
P3
CC
B8
PCHK
D15
D16
D17
E1
NMI
A2
J15
J16
J17
K1
P15
P16
P17
Q1
B9
V
CC
B10
B11
B12
B13
VCCPLL
A3
A10
D13
V
V
D7
CC
CC
E2
D4
K2
V
V
Q2
CC
SS
NC
E3
D0
K3
Q3
24
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80960HA/HD/HT
Table 9. 80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet 2 of 2)
PGA
Pin
PGA
Pin
PGA
Pin
PGA
Pin
Signal Name
Signal Name
Signal Name
Signal Name
Q4
Q5
D28
D30
Q16
Q17
R1
A21
A18
R11
R12
R13
R14
R15
R16
R17
S1
V
S6
BE2
BE1
CC
BSTALL
BREQ
A29
S7
Q6
V
D24
S8
BLAST
DEN
W/R
CC
Q7
V
V
V
V
V
R2
D27
S9
SS
SS
SS
SS
SS
Q8
R3
D31
A26
S10
S11
S12
S13
S14
S15
S16
S17
Q9
R4
BTERM
HOLD
ADS
A23
DT/R
WAIT
D/C
Q10
Q11
Q12
Q13
Q14
Q15
R5
A22
R6
D25
SUP
A30
A28
A24
R7
V
V
S2
D29
LOCK
A31
CC
CC
R8
S3
READY
HOLDA
BE3
R9
BE0
S4
A27
R10
V
S5
A25
CC
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80960HA/HD/HT
3.2.2
80960Hx PQ4 Pinout
Figure 4. 80960Hx 208-Pin PQ4 Pinout
PIN 105
PIN 104
PIN 156
PIN 157
VSS
VCC
A31
VSS
VCC
VCC
NMI
XINT7
BREQ
LOCK
VSS
XINT6
XINT5
XINT4
VSS
SUP
D/C
VCC
VSS
VSS
VCC
VCC
XINT3
XINT2
XINT1
XINT0
VSS
BSTALL
WAIT
VCC
VSS
DT/R
VCC
W/R
VCC
VSS
RESET
CLKIN
VCC
DEN
BLAST
BE0
VCCPLL
VSS
®
VCC
BE1
CT3
VCC
CT2
CT1
i960
VSS
BE2
BE3
ADS
VCC
CT0
VSS
VCC
VSS
VSS
VCC
VSS
VCC
FC80960Hx
TDO
PCHK
HOLDA
VCC
VSS
TDI
TMS
XXXXXXXX SS
VSS
HOLD
TRST
READY
BTERM
VCC
M
© 19xx
TCK
VSS
VCC
i
VSS
D31
D30
D29
D28
VCC
VCC
VSS
VCC5
VSS
VCC
VSS
VCC
DP3
DP2
VCC
VSS
D27
D26
D25
D24
VSS
DP0
DP1
STEST
PIN 53
PIN 208
PIN 1
PIN 52
26
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80960HA/HD/HT
Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet 1 of 2)
PQ4
Pin
PQ4
Pin
PQ4
Pin
PQ4
Pin
Signal Name
Signal Name
Signal Name
Signal Name
A2
A3
151
150
147
146
145
144
141
140
139
138
135
134
133
132
127
126
125
124
121
120
119
118
113
112
111
110
107
106
105
104
77
BE0
BE1
BE2
BE3
BLAST
BOFF
BREQ
BSTALL
BTERM
CLKIN
CT0
CT1
CT2
CT3
D/C
83
82
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
DEN
DP0
DP1
DP2
DP3
DT/R
FAIL
—
39
40
41
42
45
50
51
52
54
55
56
57
61
62
63
64
85
206
207
203
202
89
5
PCHK
READY
RESET
STEST
SUP
189
68
174
208
97
194
191
188
192
193
1
A4
79
A5
78
A6
84
A7
10
TCK
A8
100
91
TDI
A9
TDO
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
ADS
67
TMS
175
183
182
181
180
96
TRST
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
4
9
11
17
19
25
31
33
38
44
46
49
59
60
66
71
74
76
81
87
D0
12
D1
13
D2
14
D3
15
D4
20
D5
21
D6
22
D7
23
D8
26
—
D9
27
—
—
D10
D11
28
—
—
29
HOLD
HOLDA
LOCK
NMI
ONCE
69
72
99
159
6
D12
D13
D14
D15
34
35
36
37
Datasheet
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80960HA/HD/HT
Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet 2 of 2)
PQ4
Pin
PQ4
Pin
PQ4
Pin
PQ4
Pin
Signal Name
Signal Name
Signal Name
Signal Name
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
92
V
V
V
V
V
187
196
199
201
204
197
177
2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
70
73
V
V
V
V
V
V
V
V
V
V
V
164
170
172
178
184
186
190
195
198
200
205
88
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
95
101
102
109
115
117
123
128
131
137
143
149
153
154
158
165
171
173
176
179
185
75
80
86
VCC5
93
VCCPLL
94
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
98
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
3
103
108
114
116
122
129
130
136
142
148
152
155
156
157
7
8
16
18
24
30
32
43
47
48
53
58
65
W/R
WAIT
XINT0
XINT1
XINT2
XINT3
XINT4
XINT5
XINT6
XINT7
—
90
169
168
167
166
163
162
161
160
—
28
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80960HA/HD/HT
Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet 1 of 2)
PQ4
Pin
PQ4
Pin
PQ4
Pin
PQ4
Pin
Signal Name
Signal Name
Signal Name
Signal Name
1
V
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
V
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
D28
D29
D30
D31
91
92
BSTALL
CC
CC
2
V
V
V
CC
SS
SS
CC
SS
CC
3
V
V
93
V
V
SS
SS
CC
4
V
D12
D13
D14
D15
94
5
FAIL
V
95
V
SS
CC
6
ONCE
V
96
D/C
7
V
V
BTERM
READY
HOLD
97
SUP
SS
SS
CC
8
V
98
V
SS
CC
9
V
D16
D17
D18
D19
99
LOCK
BREQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
BOFF
V
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
SS
CC
V
V
V
V
CC
CC
CC
D0
D1
D2
D3
HOLDA
V
V
V
SS
SS
CC
SS
CC
V
V
A31
A30
A29
A28
D20
V
SS
CC
V
V
V
SS
CC
CC
V
V
V
ADS
BE3
BE2
SS
SS
CC
V
V
SS
CC
SS
CC
V
V
V
D4
D5
D6
D7
D21
D22
D23
V
A27
A26
A25
A24
SS
CC
V
BE1
BE0
V
SS
V
D24
D25
D26
D27
BLAST
DEN
V
SS
CC
SS
CC
V
V
D8
D9
V
V
SS
CC
SS
CC
V
V
D10
D11
V
W/R
DT/R
WAIT
A23
A22
A21
SS
CC
CC
V
V
V
SS
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80960HA/HD/HT
Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet 2 of 2)
PQ4
Pin
PQ4
Pin
PQ4
Pin
PQ4
Pin
Signal Name
Signal Name
Signal Name
Signal Name
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
A20
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
V
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
V
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
V
CC
CC
CC
V
V
A7
XINT3
XINT2
XINT1
XINT0
TDO
SS
CC
A6
A5
A4
PCHK
A19
A18
A17
A16
V
SS
TDI
TMS
TRST
TCK
V
V
V
V
V
SS
CC
SS
CC
SS
CC
V
V
V
V
V
A3
A2
CC
SS
SS
CC
V
V
SS
CC
V
RESET
CLKIN
SS
CC
CC
SS
SS
SS
CC
V
V
V
V
V
V
VCC5
A15
A14
A13
A12
V
V
V
V
V
CC
SS
CC
SS
CC
VCCPLL
V
V
SS
CC
V
V
CT3
CT2
CT1
CT0
DP3
DP2
SS
CC
NMI
A11
A10
A9
XINT7
XINT6
XINT5
XINT4
V
V
CC
SS
V
V
V
DP0
DP1
SS
CC
SS
A8
V
V
STEST
SS
SS
30
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80960HA/HD/HT
3.3
Package Thermal Specifications
The 80960Hx is specified for operation when TC (case temperature) is within the range of
0 °C to 85 °C. TC may be measured in any environment to determine whether the 80960Hx is
within the specified operating range. Measure the case temperature at the center of the top surface,
opposite the pins. Refer to Figure 5.
TA (ambient temperature) is calculated from θCA (thermal resistance from case to ambient) using
Equation 1:
Equation 1. Calculation of Ambient Temperature (TA)
TA = TC – (P ⋅ θCA
)
Table 12 shows the maximum TA allowable (without exceeding TC) at various airflows and
operating frequencies (fCLKIN).
Note that TA is greatly improved by attaching fins or a heatsink to the package. P (maximum power
consumption) is calculated by using the typical ICC as tabulated in Section 4.6, “DC
Specifications” on page 40 and VCC of 3.3 V.
Figure 5. Measuring 80960Hx PGA Case Temperature
Measure PGA/PQ4 temperature at
center of top surface
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80960HA/HD/HT
Table 12. Maximum TA at Various Airflows in ° C (PGA Package Only)
Airflow-ft/min (m/sec)
f
0
200
400
600
800
1000
CLKIN
(MHz)
(0)
(1.01)
(2.03)
(3.04)
(4.06)
(5.07)
25
33
40
69
63
59
74
70
67
78
75
73
79
77
75
80
79
77
80
79
77
T
with
A
Heatsink†
Core
1X Bus
Clock
T
25
33
40
64
56
50
67
62
56
71
67
63
74
70
67
75
72
69
76
74
71
A
without
Heatsink
16
25
33
40
68
58
49
41
73
66
60
55
77
73
69
65
79
75
71
68
80
77
74
72
80
77
74
72
T
with
A
Heatsink†
Core
2X Bus
Clock
16
25
33
40
62
49
38
27
66
56
46
38
71
62
55
48
73
66
60
55
75
68
63
58
76
71
66
62
T
A
without
Heatsink
T
with
20
25
53
45
63
58
71
67
73
70
76
73
76
73
A
Heatsink†
Core
3X Bus
Clock
T
A
20
25
43
33
51
42
58
51
63
58
66
61
68
64
without
Heatsink
†
*0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
Table 13. 80960Hx 168-Pin PGA Package Thermal Characteristics
Thermal Resistance — ° C/Watt
Airflow — ft./min (m/sec)
Parameter
0
200
400
600
800
1000
(0)
(1.01) (2.03) (3.07) (4.06) (5.07)
θ Junction-to-Case
(Case measured as
shown in Figure 5.)
θ
JA
1.5
1.5
1.5
1.5
1.5
1.5
θ
JC
θ Case-to-Ambient
17
13
14
9
11
6
9
5
8
4
7
4
(No Heatsink)
θ Case-to-Ambient
(With Heatsink)3
NOTES:
1. This table applies to 80960Hx PGA plugged into socket or soldered directly to board.
2. θ = θ + θ
JA
JC
CA
3. 0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
32
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80960HA/HD/HT
Table 14. Maximum TA at Various Airflows in ° C (PQ4 Package Only)
Airflow-ft/min (m/sec)
f
0
200
400
600
800
1000
CLKIN
(MHz)
(0)
(1.01)
(2.03)
(3.04)
(4.06)
(5.07)
25
33
40
71
67
63
76
74
71
79
77
75
79
77
75
80
79
77
80
79
77
T
with
A
Heatsink†
Core
1X Bus
Clock
T
25
33
40
70
65
61
73
68
65
75
72
69
75
72
69
76
74
71
76
74
71
A
without
Heatsink
16
25
33
40
71
62
55
48
76
71
66
62
79
75
71
68
79
75
71
68
80
77
74
72
80
77
74
72
T
with
A
Heatsink†
Core
2X Bus
Clock
16
25
33
40
69
60
52
42
72
64
57
51
75
68
63
58
75
68
63
58
76
71
66
62
76
71
66
62
T
A
without
Heatsink
T
with
20
25
58
51
68
64
73
70
73
70
76
73
76
73
A
Heatsink†
Core
3X Bus
Clock
T
A
20
25
56
48
61
55
66
61
66
61
68
64
68
64
without
Heatsink
†
0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
Table 15. 80960Hx 208-Pin PQ4 Package Thermal Characteristics
Thermal Resistance — ° C/Watt
Airflow — ft./min (m/sec)
Parameter
0
200
400
600
800
1000
(0)
(1.01) (2.03) (3.07) (4.06) (5.07)
θ Junction-to-Case
(Case measured as
shown in Figure 5.)
θ
JA
1
1
1
1
1
1
θ
JC
θ Case-to-Ambient
12
11
10
7
8
5
8
5
7
4
7
4
(No Heatsink)
θ Case-to-Ambient
(With Heatsink)3
NOTES:
1. This table applies to 80960Hx PQ4 plugged into socket or soldered directly to board.
2. θ = θ + θ
JA
JC
CA
3. 0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).
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80960HA/HD/HT
3.4
3.5
Heat Sink Adhesives
Intel recommends silicone-based adhesives to attach heat sinks to the PGA package. There is no
particular recommendation concerning the PQ4 package.
PowerQuad4 Plastic Package
The 80960Hx family is available in an improved version of the common 208-lead SQFP plastic
package called the PowerQuad4* (PQ4). The PQ4 package dimensions and lead pitch are identical
to the SQFP package and the former PQ2 package, so the PQ4 fits into the same board footprint.
The advantage of the PQ4 package is the superior thermal conductivity that allows the plastic
version of the 80960Hx to operate with the same 0 °C to 85 °C temperature specifications as the
more expensive ceramic PGA package.
The PQ4 package integrates a copper heat sink within the package to dissipate heat effectively. See
Table 14 and Table 15 for more information.
3.6
Stepping Register Information
The memory-mapped register at FF008710H contains the 80960Hx Device ID. The ID is identical
to the ID obtained from a JTAG Query. Figure 6 defines the current 80960Hx Device IDs. The
value for device identification is compliant with the IEEE 1149.1 specification and Intel standards.
Table 16 describes the fields of the device ID.
Figure 6. 80960Hx Device Identification Register
Part Number
Product
VCC
Type
Version
Gen
Model
Manufacturer ID
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
1
28
24
20
16
12
8
4
0
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Table 16. Fields of 80960Hx Device ID
Field
Version
Value
Definition
See Table 18.
Indicates major stepping changes.
Indicates that a device is 3.3 V.
V
1 = 3.3 V device
CC
00 0100
(Indicates i960 CPU)
Product Type
Generation Type
Model
Designates type of product.
0010 = H-series
See Table 17.
Indicates the generation (or series) the product belongs to.
Indicates member within a series and specific model
information.
000 0000 1001
(Indicates Intel)
Manufacturer ID
Manufacturer ID assigned by IEEE.
Table 17. 80960Hx Device ID Model Types
Device
Version
V
Product
Gen.
Model
Manufacturer ID
‘1’
CC
80960HA
80960HD
80960HT
1
000100
000100
000100
0010
0010
0010
00000
00001
00010
00000001001
00000001001
00000001001
1
1
1
See Table 18.
1
1
Table 18. Device ID Version Numbers for Different Steppings
Stepping
Version
A0
A1
0000
0001
0001
0010
A2
B0, B2
NOTE: This data sheet applies to the B2 stepping.
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80960HA/HD/HT
3.7
Sources for Accessories
The following is a list of suggested sources for 80960Hx accessories. This is neither an
endorsement nor a warranty of the performance of any of the listed products and/or companies.
Sockets
• 3M Textool Test and Interconnection Products
6801 River Place Blvd. MS 130-3N-29
Austin, TX 78726-9000
(800) 328-0411 FAX: (800) 932-9373
• Concept Mfg, Inc. (Decoupling Sockets)
400 Walnut St. Suite 609
Redwood City, CA 94063
(415) 365-1162 FAX: (415) 365-1164
Heatsinks/Fins
• Thermalloy, Inc.
2021 West Valley View Lane
Dallas, TX 75234-8993
(972) 243-4321 FAX: (972) 241-4656
• Wakefield Engineering, Inc.
60 Audubon Road
Wakefield, MA 01880
(617) 245-5900 FAX: (617) 246-0874
• Aavid Thermal Technologies, Inc.
One Kool Path
Laconia, NH 03247-0400
(603) 523-3400
36
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80960HA/HD/HT
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
Table 19. Absolute Maximum Ratings
Parameter
Maximum Rating
Storage Temperature
–65 ºC to +150 ºC
–65 ºC to +110 ºC
–0.5 V to + 4.6 V
Case Temperature Under Bias
Supply Voltage with respect to V
SS
Voltage on VCC5 with respect to V
–0.5 V to + 6.5 V
SS
Voltage on Other Pins with respect to V
–0.5 V to VCC5 + 0.5 V
SS
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
4.2
Operating Conditions
Table 20. Operating Conditions
Symbol
Parameter
Min
Max
Units
V
Supply Voltage
3.15
3.15
16
3.45
5.5
40
V
CC
VCC5
Input Protection Bias
V
f
f
f
1xcore
2xcore
3xcore
Input Clock Frequency - 1x Core (80960HA)
Input Clock Frequency - 2x Core (80960HD)
Input Clock Frequency - 3x Core (80960HT)
Case Temp Under Bias (PGA and PQ4 Packages)
MHz
MHz
MHz
oC
CLKIN
CLKIN
CLKIN
16
40
16
25
T
0
85
C
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80960HA/HD/HT
4.3
Recommended Connections
Power and ground connections must be made to multiple VCC and VSS (GND) pins. Every
80960Hx-based circuit board should include power (VCC) and ground (VSS) planes for power
distribution. Every VCC pin must be connected to the power plane; every VSS pin must be
connected to the ground plane. Pins identified as “NC” —no connect pins—must not be connected
in the system.
Liberal decoupling capacitance should be placed near the 80960Hx. The processor may cause
transient power surges when its output buffers transition, particularly when connected to large
capacitive loads.
Low inductance capacitors and interconnects are recommended for best high-frequency electrical
performance. Inductance may be reduced by shortening the board traces between the processor and
decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages
offer the lowest possible inductance.
For reliable operation, always connect unused inputs to an appropriate signal level. In particular,
any unused interrupt (XINT7:0, NMI) input should be connected to VCC through a pull-up resistor,
as should BTERM when not used. Pull-up resistors should be in the range of 20 KΩ for each pin
tied high. When READY or HOLD are not used, the unused input should be connected to ground.
N.C. pins must always remain unconnected.
4.4
VCC5 Pin Requirements (V
)
DIFF
In mixed-voltage systems that drive 80960Hx processor inputs in excess of 3.3 V, the VCC5 pin
must be connected to the system’s 5 V supply. To limit current flow into the VCC5 pin, there is a
limit to the voltage differential between the VCC5 pin and the other VCC pins. The voltage
differential between the 80960Hx VCC5 pin and its 3.3 V VCC pins should never exceed 2.25 V.
This limit applies to power-up, power-down, and steady-state operation. Table 21 outlines this
requirement.
Meeting this requirement ensures proper operation and ensures that the current draw into the VCC5
pin does not exceed the ICC5 specification.
When the voltage difference requirements cannot be met due to system design limitations, an
alternate solution may be employed. As shown in Figure 7, a minimum of 100 Ω series resistor
may be used to limit the current into the VCC5 pin. This resistor ensures that current drawn by the
VCC5 pin does not exceed the maximum rating for this pin.
Figure 7. VCC5 Current-Limiting Resistor
+5 V (±0.25 V)
VCC5 Pin
100 Ω
(±5%, 0.5 W)
This resistor is not necessary in systems that may ensure the VDIFF specification.
In 3.3 V-only systems and systems that drive 80960Hx pins from 3.3 V logic, connect the VCC5
pin directly to the 3.3 V VCC plane.
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Table 21. VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)
Sym
Parameter
VCC5-V
Min Max Units
2.25
Notes
VCC5 input should not exceed V by more than 2.25 V during
CC
CC
V
V
DIFF
Difference
power-up and power-down, or during steady-state operation.
4.5
VCCPLL Pin Requirements
When the voltage on the VCCPLL power supply pin exceeds the VCC pin voltage by 0.5 V at any
time, including the power up and power down sequences, excessive currents may permanently
damage on-chip electrostatic discharge (ESD) protection diodes. The damage may accumulate over
multiple episodes.
Pragmatically, this problem only occurs when the VCCPLL and VCC pins are driven by separate
power supplies or voltage regulators. Applications that use one power supply for VCCPLL and
VCC are not typically at risk. Verify that your application does not allow the VCCPLL voltage to
exceed VCC by 0.5 V.
The VCCPL low-pass filter recommended in the Developer’s Manual does not promote this
problem.
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80960HA/HD/HT
4.6
D.C.Specifications
Table 22. 80960Hx D.C. Characteristics (Sheet 1 of 2)
Per the conditions described in Section 4.3, “Recommended Connections” on page 38.
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
V
Input Low Voltage
Input High Voltage
– 0.3
2.0
+0.8
V
V
IL
VCC5 + 0.3
IH
Output Low Voltage
0.4
0.2
I
I
= 3 mA
= 100 µA
OL
OL
V
V
V
OL
All outputs except FAIL
V
V
Output Low Voltage FAIL pin
Output High Voltage
0.4
I
= 5 mA
OL
OL
2.4
V
V
I
I
= –3 mA
= –100 µA
OH
OH
OH
V
– 0.2
CC
Input Leakage Current
Non-Test Inputs
I
-1
1
µA
µA
0 ≤ V ≤ V
IN CC
LI
TDI, TMS, TRST and ONCE
-110
V
= 0 V
IN
Output Leakage Current
Non-Test Outputs
TDO pin
I
1
5
µA
µA
0.45 ≤ V
0.45 ≤ V
≤ V
LO
OUT
OUT
CC
≤ V
CC
80960HA 25
579
765
927
33
40
I
Active
80960HD 32
631
985
1300
1578
CC
(Power
Supply)
50
66
80
mA 4, 5
mA 4, 6
mA 7, 8
80960HT 60
75
1165
1455
80960HA 25
392
518
628
33
40
80960HD 32
413
645
851
I
Active
CC
50
66
80
(Thermal)
1034
80960HT 60
75
752
938
80960HA 25
330
436
528
33
40
I
Test
80960HD 32
382
595
785
955
CC
(Reset
Mode)
50
66
80
80960HT 60
75
702
878
I
Test
CC
(ONCE
mode)
25
mA
7
40
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80960HA/HD/HT
Table 22. 80960Hx D.C. Characteristics (Sheet 2 of 2)
Per the conditions described in Section 4.3, “Recommended Connections” on page 38.
Symbol
Parameter
Min
Typ
Max
Units
Notes
I
CC5
80960HA
80960HD
80960HT
200
200
200
Current on
the VCC5
Pin
µA
9
Input Capacitance for:
C
F
= 1 MHz10
PQ4
PGA
12
12
pF
pF
IN
C
Output Capacitance of each
output pin
C
12
12
pF
pF
F
F
= 1 MHz3, 10
= 1 MHz10
OUT
C
C
I/O Pin Capacitance
I/O
C
Internal Pull-Up Resistance
for ONCE, TMS, TDI and
TRST
R
30
65
100
kΩ
PU
NOTES:
1. I Maximum is measured at worst case frequency, V , and temperature, with device operating and
CC
CC
outputs loaded to the test conditions described in Section 4.7.1, “AC Test Conditions” on page 45.
2. I Typical is not tested.
CC
3. Output Capacitance is the capacitive load of a floating output.
4. Measured with device operating and outputs loaded to the test conditions in Figure 8, “AC Test Load” on
page 45. Input signals rise to V and fall to V
.
CC
SS
5. I Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using
CC
one of the worst case instruction mixes with V = 3.45 V. This parameter is characterized but not tested.
CC
6. I Active (Thermal) value is provided for your system’s thermal management. Typical I is measured with
CC
CC
V
= 3.3 V and temperature = 25° C. This parameter is characterized but not tested.
CC
7. I Test (Power modes) refers to the I values that are tested when the 80960HA/HD/HT is in Reset mode
CC
CC
or ONCE mode with V = 3.45 V.
CC
8. Worst case is V = 3.45 V, 0 ° C.
CC
9. I
is tested at V = 3.0 V, VCC5 = 5.25 V.
CC5
CC
10.Pin capacitance is characterized, but not tested.
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4.7
A.C. Specifications
Table 23. 80960Hx A.C. Characteristics (Sheet 1 of 2)
Per conditions in Section 4.2, “Operating Conditions” on page 37 and Section 4.7.1, “AC Test Conditions” on page 45.
Symbol
Parameter
Min
Max
Units
Notes
Input Clock1, 7
CLKIN Frequency
80960HD
80960HA
16
16
16
40
40
25
MHz
MHz
MHz
T
T
F
80960HT
80960HT
CLKIN Period
80960HA
25
25
40
62.5
62.5
62.5
ns
ns
ns
80960HD
T
T
CLKIN Period Stability
CLKIN High Time
CLKIN Low Time
80960HD
-250
8
+250
ps
ns
11
11
CS
CH
80960HA
80960HT
8
8
8
ns
ns
ns
T
11
CL
T
T
CLKIN Rise Time
CLKIN Fall Time
0
0
4
4
ns
ns
11
11
CR
CF
Synchronous Outputs1, 2, 3, 6
Output Valid Delay and Output Hold for all
outputs except DT/R, BLAST and BREQ for
3.3 V and 5 V inputs and I/Os.
T
T
, T
1.5
9.5
ns
OV1 OH1
Output Valid Delay and Output Hold for DT/R
80960HA
T/2 + 1.5
T/2 + 9.5
3T/4 + 9.5
5T/6 + 9.5
ns
ns
ns
, T
OV2 OH2
80960HD 3T/4 + 1.5
80960HT 5T/6 + 1.5
T
T
T
T
, T
Output Valid Delay and Output Hold for BLAST
1.5
0.5
1.5
1.5
9
9
ns
ns
OV3 OH3
, T
OV4 OH4
Output Valid Delay and Output Hold for BREQ
Output Valid Delay and Output Hold for A3:2
Output Float for all outputs
, T
8.5
9
OV5 OH5
ns
11
OF
Synchronous Inputs1, 7, 8, 9
Input Setup for all inputs except READY, BTERM,
HOLD, and BOFF
T
T
2.5
2.5
ns
ns
IS1
IH1
Input Hold for all inputs except READY, BTERM,
HOLD, and BOFF
NOTE: See Table 24, “AC Characteristics Notes” on page 44 for all notes related to AC specifications.
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Table 23. 80960Hx A.C. Characteristics (Sheet 2 of 2)
Per conditions in Section 4.2, “Operating Conditions” on page 37 and Section 4.7.1, “AC Test Conditions” on page 45.
Symbol
Parameter
Min
Max
Units
Notes
Input Setup for READY, BTERM, HOLD, and
BOFF
T
T
6
ns
IS2
Input Hold for READY, BTERM, HOLD, and
BOFF
2.5
ns
IH2
Relative Output Timings1, 2, 3, 6, 10
T
A31:2 Valid to ADS Rising
T – 5
T – 5
T + 5
T + 5
T + 5
T + 5
5
ns
ns
ns
ns
ns
ns
ns
10
10
AVSH1
T
BE3:0, W/R, SUP, D/C Valid to ADS Rising
A31:2 Valid to DEN Falling
AVSH2
T
T – 5
10
AVEL1
T
BE3:0, W/R, SUP Valid to DEN Falling
WAIT Falling to Output Data Valid
Output Data Valid to WAIT Rising
WAIT Falling to WAIT Rising
T – 5
10
AVEL2
T
-5
10
NLQV
DVNH
NLNH
T
T
-5 + N*T
-4 + N*T
5 + N*T
4 + N*T
4, 10
4, 10
-5 +
(N+1)*T
T
Output Data Hold after WAIT Rising
5 + (N+1)*T
Infinite
ns
ns
5, 10
10
NHQX
EHTV
T
DT/R Hold after DEN High
DT/R Valid to DEN Falling
T/2 – 5
80960HA
80960HD
80960HT
T/2 – 4
T/4 – 4
T/6 – 4
ns
ns
ns
T
10
TVEL
Relative Input Timings1, 7, 10
T
T
T
T
XINT7:0, NMI Input Setup
XINT7:0, NMI Input Hold
RESET Input Setup
6
ns
ns
ns
ns
9
9
8
8
IS7
IH7
IS8
IH8
2.5
3
RESET Input Hold
T/4 + 1
NOTE: See Table 24, “AC Characteristics Notes” on page 44 for all notes related to AC specifications.
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Table 24. A.C. Characteristics Notes
NOTES:
1. See Section 4.8, “AC Timing Waveforms” on page 46 for waveforms and definitions.
2. See Figure 25, “Output Delay or Hold vs. Load Capacitance” on page 52 for capacitive derating information
for output delays and hold times.
3. See Figure 22, “Rise and Fall Time Derating at 85 ° C and Minimum VCC” on page 51 for capacitive
derating information for rise and fall times.
4. Where N is the number of N
, N
, N
or N
wait states that are programmed in the Bus
RAD
RDD
WAD
WDD
Controller Region Table. WAIT never goes active when there are no wait states in an access.
5. N = Number of wait states inserted with READY.
6. These specifications are ensured by the processor.
7. These specifications must be met by the system for proper operation of the processor.
8. RESET is an asynchronous input that has no required setup and hold time for proper operation. However,
to ensure the device exits the reset mode synchronized to a particular clock edge, the rising edge of
RESET must meet setup and hold times to the rising edge of the CLKIN.
9. The interrupt pins are synchronized internally by the 80960Hx. They have no required setup or hold times
for proper operation. These pins are sampled by the interrupt controller every clock and must be active for
at least two consecutive CLKIN rising edges when asserting them asynchronously. To ensure recognition at
a particular clock edge, the setup and hold times shown must be met.
10.Relative Output timings are not tested.
11.Not tested.
12.The processor minimizes changes to the bus signals when transitioning from a bus cycle to an idle bus for
the following signals: A31:4, SUP, CT3:0, D/C, LOCK, W/R, BE3:0.
Table 25. 80960Hx Boundary Scan Test Signal Timings
Symbol
Parameter
TCK Frequency
TCK Period
Min
0
Max
8
Units
MHz
ns
Notes
T
T
T
T
T
T
T
BSF
125
40
Infinite
BSC
TCK High Time
TCK Low Time
TCK Rise Time
TCK Fall Time
ns
Measured at 1.5 V†
BSCH
BSCL
BSCR
BSCF
BSIS1
40
ns
Measured at 1.5 V†
0.8 V to 2.0 V†
8
8
ns
ns
2.0 V to 0.8 V†
Input Setup to TCK —
TDI, TMS
8
ns
ns
T
Input Hold from TCK —
TDI, TMS
BSIH1
10
3
T
T
T
TDO Valid Delay
TDO Float Delay
30
36
ns
ns
BSOV1
BSOF1
BSOV2
†
All Outputs (Non-Test)
Valid Delay
Relative to TCK
3
30
36
ns
ns
T
T
T
†
All Outputs (Non-Test)
Float Delay
Relative to TCK†
BSOF2
BSIS2
Input Setup to TCK - All
Inputs (Non-Test)
8
ns
ns
Input Hold from TCK - All
Inputs (Non-Test)
10
BSIH2
Not tested.
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4.7.1
A.C. Test Conditions
A.C. values are derived using the 50 pF load shown in Figure 8. Figure 25, “Output Delay or Hold vs.
Load Capacitance” on page 52, shows how timings vary with load capacitance. Input waveforms
(except for CLKIN) are assumed to have a rise and fall time of ≤ 2 ns from 0.8 V to 2.0 V.
Figure 8. A.C. Test Load
Output Pin
CL
C
L = 50 pF for all signals
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4.8
A.C. Timing Waveforms
Figure 9. CLKIN Waveform
T
T
CR
CF
2.0 V
1.5 V
0.8 V
T
CH
T
CL
T
Figure 10. Output Delay Waveform
1.5 V
Min
1.5 V
CLKIN
TOV1
Max
Outputs:
A31:2, D31:0 write only,
DP3:0 write only
PCHK, BE3:0, W/R, D/C,
SUP, ADS, DEN,
TOH1
1.5 V
1.5 V
LOCK, HOLDA, BREQ, BSTALL,
CT3:0, FAIL, WAIT, BLAST
Figure 11. Output Delay Waveform
1.5 V
1.5 V
CLKIN
TOV2
TOH2
Max
1.5 V
Min
DT/R
1.5 V
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Figure 12. Output Float Waveform
1.5 V
1.5 V
CLKIN
Outputs:
A31:2, D31:0 write only,
DP3:0 write only
TOF
Max
Min
PCHK, BE3:0, W/R, D/C,
SUP, ADS, DEN,
LOCK, HOLDA,
CT3:0, WAIT, BLAST, DT/R
Figure 13. Input Setup and Hold Waveform
CLKIN
1.5 V
1.5 V
TIH
1.5 V
TIS
Min
Min
Inputs:
READY, HOLD, BTERM,
Valid
BOFF, D31:0 on reads,
DP3:0 on reads, RESET
Figure 14. NMI, XINT7:0 Input Setup and Hold Waveform
A
B
A
CLKIN
1.5 V
1.5 V
1.5 V
TIH
TIS
Min
Min
NMI, XINT7:0
1.5 V
Valid
1.5 V
NOTE: A and B edges are established by de-assertion of RESET. See Figure 29, “Cold Reset Waveform” on page 54.
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Figure 15. Hold Acknowledge Timings
CLKIN
1.5 V
1.5 V
1.5 V
TIH
Min
TIH
TIS
TIS
Min
Min
Min
1.5 V
1.5 V
1.5 V
HOLD
TOV1
Min
TOV1
Max
Max
TOH1
1.5 V
TOH1
Min
HOLDA
1.5 V
1.5 V
T
T
— OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay (T ).
O
V
O
H
O
V
The minimum output delay is referred to as the Output Hold (T ).
OH
T
T
— INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window
IS IH
during which synchronous inputs must be stable for correct processor operation.
Figure 16. Bus Backoff (BOFF) Timings
1.5 V
1.5 V
1.5 V
CLKIN
TIS
TIS
TIH
TIH
BOFF
1.5 V
1.5 V
1.5 V
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Figure 17. TCK Waveform
T
T
BSCR
BSCF
2.0 V
1.5 V
0.8 V
T
BSCH
T
BSCL
T
BSC
Figure 18. Input Setup and Hold Waveforms for TBSIS1 and TBSIH1
1.5 V
1.5 V
1.5 V
TCLK
TBSIH1
TBSIS1
Inputs:
TMS
TDI
1.5 V
Valid
1.5 V
Datasheet
49
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80960HA/HD/HT
Figure 19. Output Delay and Output Float for TBSOV1 and TBSOF1
TCK
1.5 V
1.5 V
1.5 V
TBSOV1
TBSOF1
Valid
1.5 V
TDO
Figure 20. Output Delay and Output Float Waveform for TBSOV2 and TBSOF2
TCK
1.5 V
1.5 V
1.5 V
TBSOV2
TBSOF2
Non-Test
Outputs
Valid
1.5 V
Figure 21. Input Setup and Hold Waveform for TBSIS2 and TBSIH2
1.5 V
1.5 V
1.5 V
TCK
TBSIH2
TBSIS2
Non-Test
Inputs
Valid
1.5 V
1.5 V
50
Datasheet
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80960HA/HD/HT
Figure 22. Rise and Fall Time Derating at 85 ° C and Minimum VCC
5
4
3
2.0 to 0.8 V
0.8 to 2.0 V
2
1
50pF
100pF
150pF
CL (pF)
Figure 23. ICC Active (Power Supply) vs. Frequency
1800
1600
1400
1200
1000
800
600
400
200
0
HA
HD
HT
0
10
20
30
40
CLKIN Frequency (MHz)
Datasheet
51
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80960HA/HD/HT
Figure 24. ICC Active (Thermal) vs. Frequency
1400
1200
1000
800
HA
HD
HT
600
400
200
10
20
30
40
CLKIN Frequency (MHz)
Figure 25. Output Delay or Hold vs. Load Capacitance
nom + 10
5.5 V Input Signals
3.3 V Input Signals
nom + 5
nom
50
100
150
C
L (pF)
52
Datasheet
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80960HA/HD/HT
Figure 26. Output Delay vs. Temperature
Processor Case Temperature (°C)
0° C
85° C
nom - 0.0
nom - 0.1
nom - 0.2
nom - 0.3
nom - 0.4
nom - 0.5
Figure 27. Output Hold Times vs. Temperature
Processor Case Temperature (°C)
0° C
85° C
nom + 0.5
nom + 0.4
nom + 0.3
nom + 0.2
nom + 0.1
nom + 0
Figure 28. Output Delay vs. VCC
nom + 0.5
nom + 0.3
nom + 0.1
-nom + 0.1
-nom + 0.3
-nom + 0.5
3.15
3.45
VCC (volts)
Datasheet
53
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A
B
A
B
CLKIN
VCC, VCC5,
ONCE
CT3:0, ADS,
LOCK, WAIT,
DEN, BLAST
W/R, DT/R,
BREQ, FAIL,
BSTALL
A31:2, SUP
D/C, BE3:0
Invalid
D31:0,
DP3:0
Inputs
Valid
STEST
RESET
Thold
1CLKIN
Tsetup
1CLKIN
CLKIN and VCC Stable to RESET high, RESET high to First Bus Activity,
minimum 10,000 CLKIN periods
HA=67, HD=34, HT=23
for PLL stabilization.
CLKIN periods
NOTE: VCC stable: As specified in Table 21, “VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)” on page 39
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CLKIN
ADS,
LOCK, WAIT,
DEN, BLAST,
W/R, BREQ, FAIL,
BSTALL
DT/R
SUP,
A31:2,
D/C, BE3:0
D31:0,
DP3:0
Valid
STEST
RESET
Maximum RESET Low to RESET State
16 CLKIN Periods
Thold
Tsetup
1 CLKIN
1 CLKIN
RESET High to First Bus Activity,
HA=67, HD=34, HT=23
CLKIN Periods
Minimum RESET Low Time
16 CLKIN Periods
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CLKIN may neither float nor remain idle.
It must continue to run.
CLKIN
VCC, VCC5
ADS, BE3:0, A31:2,
D31:0, LOCK, WAIT,
BLAST,W/R, D/C, DEN,
DT/R, HOLDA,
BLAST, FAIL, SUP,BREQ,
CT3:0, BSTALL, DP3:0,
PCHK
ONCE mode is entered within 1 CLKIN
period after ONCE becomes low while
RESET is low.
RESET
ONCE
CLKIN and V Stable and RESET low and ONCE low to
CC
10,000 CLKIN Periods.
RESET high, minimum
NOTES:
1. ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising
edge of RESET.
2. The ONCE input may be removed after the processor enters ONCE mode.
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80960HA/HD/HT
Figure 32. Non-Burst, Non-Pipelined Requests without Wait States
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
29
24
23-22
21
20
19-16
15-14
12-8
7-6
4-0
Disabled
0
OFF
0
0
00
0
Disabled
0
X
x
Enabled
1
X
xx
0
0
0
00
Value
00000
0000
00000
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
D
A
D
A
D
CLKIN
ADS
A31:2, SUP,
D/C, BE3:0,
LOCK, CT3:0
Valid
Valid
Valid
W/R
BLAST
DT/R
DEN
WAIT
D31:0,
DP3:0
In
Out
In
PCHK
Datasheet
57
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80960HA/HD/HT
Figure 33. Non-Burst, Non-Pipelined Read Request with Wait States
PMCON
External
Ready
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
NRAD
4-0
Function
Bit
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
24
23-22
21
20
19-16
15-14
12-8
7-6
29
Disabled
0
OFF
0
X
xx
X
xxxxx
X
x
Enabled
1
Disabled
0
X
xx
1
0001
3
X
xx
Value
00011
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
D
1
3
A
2
1
CLKIN
ADS
A31:2, BE3:0
Valid
W/R
BLAST
DT/R
DEN
D/C, SUP,
LOCK, CT3:0
Valid
WAIT
D31:0,
DP3:0
In
PCHK
58
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80960HA/HD/HT
Figure 34. Non-Burst, Non-Pipelined Write Request with Wait States
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
OFF
0
3
X
xxxxx
X
x
Enabled
1
Disabled Disabled
X
xx
1
X
xxxxx
X
xx
Value
00011
0
0
0001
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
3
2
1
D
1
A
CLKIN
ADS
A31:2,
BE3:0
Valid
W/R
BLAST
DT/R
DEN
D/C, SUP,
LOCK, CT3:0
Valid
WAIT
D31:0,
DP3:0
Out
PCHK
Datasheet
59
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80960HA/HD/HT
Figure 35. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
OFF
0
X
xxxxx
X
xx
Enabled
1
X
x
Enabled
1
Disabled
0
32-Bit
10
0
0000
0
0
00
Value
00000
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
D
D
D
D
A
CLKIN
ADS
A31:4, SUP,
CT3:0,D/C,
Valid
BE3:0, LOCK
W/R
BLAST
DT/R
DEN
A3:2
00
01
10
11
WAIT
D31:0,
DP3:0
In1
In2
In3
In0
PCHK
60
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80960HA/HD/HT
Figure 36. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
N
Function
Burst
28
N
N
N
WAD
RDD
XDA
WDD
Parity
Control
Bit
29
24
23-22
21
20
19-16
15-14
12-8
7-6
4-0
OFF
0
X
xxxxx
X
xx
Enabled
1
X
x
Enabled
1
Disabled
0
32-Bit
10
1
0001
2
1
01
Value
00010
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
2
1
D
1
D
1
D
1
D
1
A
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
A3:2
WAIT
00
01
10
11
D31:0,
DP3:0
In2
In3
In0
In1
PCHK
Datasheet
61
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80960HA/HD/HT
Figure 37. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
OFF
0
0
0
00
Enabled
1
X
x
Enabled
1
Disabled
0
32-Bit
10
0
0000
X
xxxxx
X
xx
Value
00000
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
D
D
D
A
A
D
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
00
01
10
11
A3:2
WAIT
D31:0,
DP3:0
Out1
Out0
Out2
Out3
PCHK
62
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80960HA/HD/HT
Figure 38. Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
OFF
0
32-bit
10
2
1
01
X
x
Enabled
1
Enabled
1
Disabled
0
1
X
xxxxx
X
xx
Value
00010
0001
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
2
1
D
1
D
1
D
1
D
1
A
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
A3:2
WAIT
00
01
10
11
D31:0,
DP3:0
Out3
Out0
Out1
Out2
PCHK
Datasheet
63
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80960HA/HD/HT
Figure 39. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
N
Function
Burst
28
N
N
N
WAD
RDD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
OFF
0
X
xxxxx
X
xx
Enabled
1
X
x
Enabled
1
Disabled
0
16-Bit
01
1
0001
2
1
01
Value
00010
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
2
1
D
1
D
1
D
1
D
1
A
CLKIN
ADS
SUP, CT3:0,
D/C, LOCK,
A31:4, BE3/BHE,
BE0/BLE
Valid
W/R
BLAST
DT/R
DEN
A3:2
A3:2 = 00 or 10
A3:2 = 01 or 11
BE1/A1
WAIT
D15:0
A1=1
D15:0
A1=0
D15:0
A1=1
D15:0
A1=0
D31:0,
DP3:0
PCHK
64
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80960HA/HD/HT
Figure 40. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
OFF
0
8-Bit
00
X
xxxxx
X
xx
X
x
Enabled
1
Disabled Enabled
1
0001
2
1
01
Value
1
0
00010
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A
2
1
D
1
D
1
D
1
D
1
A
CLKIN
ADS
SUP, CT3:0,
D/C, LOCK,
A31:4
Valid
W/R
BLAST
DT/R
DEN
A3:2
A3:2 = 00, 01, 10 or 11
BE1/A1,
BE0/A0
A1:0 = 00
A1:0 = 01
A1:0 = 10
A1:0 =11
WAIT
D7:0
Byte 1
D7:0
Byte 2
D7:0
Byte 3
D7:0
Byte 0
D31:0,
DP3:0
PCHK
Datasheet
65
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80960HA/HD/HT
Figure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
29
24
23-22
21
20
19-16
15-14
12-8
7-6
ON
1
32-Bit
10
X
xxxxx
X
xx
X
xx
Disabled
0
X
x
Enabled
1
X
x
X
0
Value
xxxx
00000
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A’’’’
D’’’
A’
D
A’’
D’
A’’’
D’’
A
D’’’’
1
2
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
LOCK
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
W/R
A3:2
BE3:0
Valid
Valid
Valid
Valid
Valid
Invalid
IN
D31:0,
DP3:0
IN
D
IN
D’
IN
D’’
IN
D’’’
D’’’’
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin.
2. Pipelined reads conclude, non-pipelined requests begin.
66
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80960HA/HD/HT
Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
ON
1
32-Bit
10
X
xxxxx
X
xx
X
xx
X
x
Enabled
1
X
x
Disabled
0
X
1
Value
xxxx
00001
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A’
D
1
A
1
1
’
2
D
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
LOCK
Valid
Valid
Valid
Invalid
Invalid
Invalid
W/R
A3:2
BE3:0
Valid
D31:0,
DP3:0
IN
D
IN
D’
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
Datasheet
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80960HA/HD/HT
Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
ON
1
32-Bit
10
X
xxxxx
X
xx
0
00
X
x
Enabled
1
X
x
Enabled
1
X
0
Value
xxxx
00000
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1
2
A
D
D
D
A’
D’
D’
D
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
In-
Valid
Valid
Valid
W/R
In-
Valid
A3:2
00
01
10
11
Valid
Valid
IN
D
IN
D
IN
D
IN
D
IN
D
IN
D
D31:0,
DP3:0
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
68
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80960HA/HD/HT
Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit Bus
PMCON
Function
External
Ready
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
NRAD
4-0
N
Burst
28
N
N
N
WAD
RDD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
ON
1
32-Bit
10
X
xxxxx
2
X
xx
1
01
X
x
Enabled
1
X
x
Enabled
1
X
Value
xxxx
00010
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A’
D
D’
1
A
2
1
D
1
D
1
D
1
2
1
2
CLKIN
ADS
A31:4, SUP,
In-
valid
CT3:0, D/C,
Valid
Valid
BE3:0, LOCK
In-
valid
W/R
A3:2
In-
valid
00
01
10
11
Valid
D31:0,
DP3:0
IN
D
IN
D
IN
D
IN
D’
IN
D
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin.
2. Pipelined reads conclude, non-pipelined requests begin.
Datasheet
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80960HA/HD/HT
Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
ON
1
8-Bit
00
X
xxxxx
2
X
xx
1
01
X
x
Enabled
1
Enabled
1
X
x
X
Value
xxxx
00010
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
A’
D
2
A
2
1
D
1
D
1
D
1
2
1
D’
1
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
LOCK
In-
valid
Valid
Valid
In-
W/R
A3:2
valid
In-
valid
A3:2 = 00, 01, 10, or 11
Valid
BE1/A1,
BE0/A0
In-
valid
A1:0 = 00
A1:0 = 01
A1:0 = 10 A1:0 = 11
Valid
D31:0,
DP3:0
D7:0
Byte 0
D7:0
Byte 1
D7:0
D’
D7:0
Byte 2
D7:0
Byte 3
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
70
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80960HA/HD/HT
Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit Bus
PMCON
External
Pipe-
Lining
Parity
Enable
Bus
Width
Odd
Ready
NRAD
4-0
Function
Burst
28
N
RDD
N
N
N
WAD
XDA
WDD
Parity
Control
Bit
24
23-22
21
20
19-16
15-14
12-8
7-6
29
ON
1
16-Bit
01
X
xxxxx
2
X
xx
1
01
X
x
Enabled
1
X
x
Enabled
1
X
Value
xxxx
00010
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
1
2
A’
D
A
2
1
D
1
D
1
D
1
2
1
D’
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE0/BLC,
BE3/BHE,
LOCK
In-
valid
Valid
Valid
In-
valid
W/R
In-
valid
A3:2 = 00 or 10
A3:2 = 01 or 11
Valid
Valid
A3:2
In-
valid
BE1/A1
D15:0
A1=1
D15:0
A1=0
D15:0
A1=0
D15:0
D’
D15:0
A1=1
D31:0,
DP3:0
WAIT
BLAST
DT/R
DEN
PCHK
1. Non-pipelined request concludes, pipelined reads begin
2. Pipelined reads conclude, non-pipelined requests begin
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80960HA/HD/HT
Figure 47. Using External READY
Quad-Word Read Request
RAD = 0, NRDD = 0, NXDA = 0
Ready Enabled
Quad-Word Write Request
WAD = 1, NWDD = 0, NWDA = 0
Ready Enabled
N
A
N
2
1
D
D
D
D
A
1
D
1
D
1
D
1
D
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
Valid
W/R
BLAST
DT/R
DEN
READY
BTERM
A3:2
00
01 10
11
00
01
10
11
WAIT
D31:0,
DP3:0
D0 D1 D2 D3
D0
D1
D2
D3
PCHK
NOTE: Pipelining must be disabled to use READY.
72
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80960HA/HD/HT
Figure 48. Terminating a Burst with BTERM
Quad-Word Read Request
NRAD = 0, NRDD = 0, NRDA = 0
Ready Enabled
A
D
1
A
D
1
A
D
1
D
1
CLKIN
ADS
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Valid
W/R
BLAST
DT/R
DEN
READY
BTERM
See Note
A3:2
00
01
10
11
WAIT
D31:0,
DP3:0
D1
D2
D3
D0
PCHK
Note: READY adds memory access time to data transfers, whether or not the
bus access is a burst access. BTERM interrupts a bus access, whether or not
the bus access has more data transfers pending. Either the READY signal or
the BTERM signal terminates a bus access when the signal is asserted during
the last (or only) data transfer of the bus access.
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80960HA/HD/HT
Figure 49. BREQ and BSTALL Operation
CLKIN
ADS
BLAST
BREQ
BSTALL
The processor may stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted).
Depending on the instruction stream and memory wait states, the two signals may be separated by
several CLKIN cycles.
Bus arbitration logic that logically ‘ANDs’ BSTALL and BREQ will not correctly grant the bus to
the processor in all stall cases, potentially degrading processor performance.
Do not logically ‘AND’ BSTALL and BREQ together in arbitration logic. Instead, the simplest bus
arbitration should logically “OR” BSTALL and BREQ to determine the processor’s bus ownership
requirements.
More sophisticated arbitration should recognize the priority nature of these two signals. Using a
traffic light analogy, BREQ is a ‘yellow light’ warning of a possible processor stall and BSTALL is
a ‘red light’ indicating a stall in progress.
74
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80960HA/HD/HT
Figure 50. BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle.
BOFF Mode
A
D
A
CLKIN
Regenerate ADS
ADS
BLAST
READY
Burst
Non-Burst
May Change
Resume Request
BOFF
Suspend Request
A31:2, SUP,
CT3:0, D/C,
BE3:0, WAIT,
DEN, DT/R
DP3:0 & D31:0,
(WRITES)
Valid
Valid
PCHK
Begin Request
End Request
BOFF may be asserted to suspend request
BOFF may not
be asserted
BOFF may not
be asserted
Note: READY/BTERM must be enabled; NRAD, NRDD, NWAD, NWDD= 0
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80960HA/HD/HT
Figure 51. HOLD Functional Timing
Word Read
Request
Word Read Request
=1, NXDA=1
N
=0,
=0
Hold State
Hold State
N
RAD
RAD
N
XDA
CLKIN
ADS
A31:2, SUP,
CT3:0, D/C,
Valid
Valid
BE3:0, WAIT,
DEN, DT/R
BLAST
LOCK
HOLD
HOLDA
76
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80960HA/HD/HT
Figure 52. LOCK Delays HOLDA Timing
CLKIN
ADS
W/R
BLAST
LOCK
HOLD
HOLDA
Figure 53. FAIL Functional Timing
RESET
(Bus Test)
Pass
(Internal Self-Test)
Pass
FAIL
Fail
Fail
113 Cycles
94 Cycles
257,517 Cycles
128,761 Cycles
30 Cycles
80960HA:
80960HD:
80960HT:
15 Cycles
85,840 Cycles
10 Cycles
90 Cycles
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80960HA/HD/HT
Figure 54. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions
0
0
4
8
12
3
16
4
20
5
24
6
Byte Offset
Word Offset
1
2
Short Request (Aligned)
Short Requests (Unaligned)
Short Request (Aligned)
Short-Word
Load/Store
Byte, Byte Requests
Word Request (Aligned)
Trey, Byte, Requests
Word
Load/Store
Short, Short Requests
Byte, Trey, Requests
One Double-Word Burst (Aligned)
Trey, Byte, Trey, Byte, Requests
Short, Short, Short, Short Requests
Byte, Trey, Byte, Trey, Requests
Word, Word Requests
Double-Word
Load/Store
One Double-Word
Request (Aligned)
NOTES:
1. All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes
adjacent requests to occur for full words to the same address.
78
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80960HA/HD/HT
Figure 55. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued)
0
4
8
12
16
20
24
Byte Offset
Word Offset
0
1
2
3
4
5
6
One Three-Word
Request (Aligned)
Trey, Byte, Trey, Byte,
Trey, Byte Requests
Short, Short, Short, Short
Short, Short, Short Requests
Triple-Word
Load/Store
Byte, Trey, Byte, Trey, Byte, Trey Requests
Word, Word,
Word Requests
Word, Word,
Word Requests
Word,
Word,
Word
Requests
One Four-Word
Request (Aligned)
Trey, Byte, Trey, Byte, Trey, Byte
Trey, Byte Requests
8 Short Requests
Quad-Word
Load/Store
Byte, Trey, Byte, Trey,
Byte, Trey, Byte, Trey, Requests
4 Word
Requests
4 Word
Requests
NOTES:
1. All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes
adjacent requests to occur for full words to the same address.
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80960HA/HD/HT
Figure 56. A Summary of Aligned and Unaligned Transfers for 16-Bit Bus
0
0
4
8
2
12
3
16
4
20
5
24
6
Byte Offset
Word Offset
1
Short
Byte, Byte
Short
Short
16-Bit Bus
Byte, Byte
Two Short Burst
Byte, Short, Byte
Word
(Short)*2
16-Bit Bus
Byte, Short, Byte
Two Short Burst
Four Short Burst
(Byte, Short, Byte) *2
(Short) *4
Double Word
16-Bit Bus
(Byte, Short, Byte)*2
(Two Short Burst)*2
Four Short Burst
Four Short Burst, Two Short Burst
(Byte, Short, Byte) *3
(Short) *6
Triple Word
16-Bit Bus
(Byte, Short, Byte) *3
(Two Short Burst) *3
(Two Short Burst) *3
(Four Short Burst)*2
(Byte, Short, Byte) *4
(Short) *8
(Byte, Short, Byte) *4
(Two Short Burst)*4
(Two Short Burst) *4
Quad Word
16-Bit Bus
80
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80960HA/HD/HT
Figure 57. A Summary of Aligned and Unaligned Transfers for 8-Bit Bus
Byte Offset
Word Offset
0
0
4
8
2
12
3
16
4
20
5
24
6
1
Two Byte Burst
Two Byte Burst
Short
Two Byte Burst
Byte, Byte
8-Bit Bus
Four Byte Burst
Three Byte Burst, Byte
(Two Byte Burst)*2
Word
8-Bit Bus
Byte, Three Byte Burst
Four Byte Burst
(Four Byte Burst) *2
(Three Byte Burst, Byte)*2
(Two Byte Burst) *4
Double Word
8-Bit Bus
(Byte, Three Byte Burst) *2
(Four Byte Burst) *2
(Four Byte Burst) *2
(Four Byte Burst)*3
(Three Byte Burst, Byte)*3
(Two Byte Burst) *6
Triple Word
8-Bit Bus
(Byte, Three Byte Burst) *3
(Four Byte Burst)*3
(Four Byte Burst)*3
(Four Byte Burst)*4
(Three Byte Burst, Byte)*4
(Two Byte Burst) *8
Quad Word
16-Bit Bus
(Byte, Three Byte Burst) *4
(Four Byte Burst)*4
(Four Byte Burst) *4
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80960HA/HD/HT
Figure 58. Idle Bus Operation
Read Request
=2, N =0
Write Request
=2, N = 0
Idle Bus
(not in Hold Acknowledge state)
N
RAD
XDA
N
WAD
XDA
Ready Disabled
Ready Disabled
CLKIN
ADS
A31:4, SUP, D/C,
BE3:0, CT3:0
Valid
Valid
Valid
Valid
LOCK
W/R
BLAST
DT/R
DEN
A3:2
Valid
Valid
WAIT
D31:0
Out
In
READY,
BTERM
PCHK
82
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80960HA/HD/HT
Figure 59. Bus States
Tb
BOFF
W CNT > 1
d
BOFF
Tdw3
BOFF
Ta
W CNT = 1
d
!BOFF and READY and !BLAST or
!BOFF
!BOFF and BTERM and !BLAST or !BOFF and
READ and N > 0 or
rdd
!HOLD and BLAST and REQUEST and N
= 0
XDA
WRITE and N
> 0
wdd
Td1
!BOFF and READ and N = 0
rdd
and !BLAST or !BOFF and
!BOFF and READ and N = 0 or
rad
!RESET and
!HOLD and
REQUEST
!BOFF and WRITE and N
= 0
wad
WRITE and N
READY!
= 0 and !BLAST or
wdd
READ and N > 0 or
rad
WRITE and N
> 0
wad
!BOFF and
BLAST and
N
> 0
xda
Taw2
W CNT = 1
a
Trw4
W CNT > 1
x
W CNT > 1
a
!BOFF and !HOLD and
= 0
!HOLD and W CNT=1
x
N
xda
BLAST and
and REQUEST
and !REQUEST
To
!BOFF and
W CNT=1 and
x
RESET and
!ONCE
HOLD and BLAST
and N = 0
xda
HOLD
!HOLD and W CNT=1
x
and !REQUEST
ONCE and
RESET
HOLD
KEY:
To = ONCE
Ti = IDLE
Ti
HOLD
Th
Th = HOLD
Ta = ADDRESS
Td = DATA
!HOLD
Tb = BOFF’ed
Taw= address to data wait
Tdw= data to data wait
RESET
Tdw= data to address wait
REQUEST= One or more
requests in the bus queue.
READ= The current
access is a read.
WRITE= The current
access is a write.
NOTES:
1. When the PMCON for the region has External Ready Control enabled, wait states are inserted as long
as READY and BTERM are de-asserted. When Read Pipelining is enabled, the Ta state of the
subsequent read access is concurrent with the last data cycle of the access. Because External Ready
Control is disabled for Read Pipelining, the address cycle occurs during BLAST.
2. W CNT is decremented during T
a
aw.
3. W CNT is decremented during T
d
dw.
rw.
4. W CNT is decremented during T
x
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80960HA/HD/HT
5.1
80960Hx Boundary Scan Chain
Table 26. 80960Hx Boundary Scan Chain (Sheet 1 of 4)
#
Boundary Scan Cell
Cell Type
Comment
DP3
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Input
DP2
DP0
DP1
STEST
FAILBAR
Output
Enable for FAILBAR, BSTALL and
BREQ
Control
ONCEBAR
Input
BOFFBAR
Input
D0
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Control
D1
D2
D3
D4
D5
D6
D7
Enable for DP(3:0) and D(31:0)
D8
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
NOTES:
1. Cell#1 connects to TDO and cell #112 connects to TDI.
2. All outputs are tri-state.
3. In output and bidirectional signals, a logical 1 on the enable signal enables the output. A logical 0
tri-states the output.
84
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80960HA/HD/HT
Table 26. 80960Hx Boundary Scan Chain (Sheet 2 of 4)
#
Boundary Scan Cell
Cell Type
Comment
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Input
BTERMBAR
RDYBAR
Appears as READYBAR in BSDL
file.
Input
HOLD
Input
HOLDA
Output
Control
Output
Enable for HOLDA control
ADSBAR
Appears as BEBAR(3:0) in BSDL
file.
BE3BAR
Output
BE2BAR
Output
Output
Output
Output
Output
Output
Output
Control
Output
Output
Output
Output
BE1BAR
BE0BAR
BLASTBAR
DENBAR
WRRDBAR
DTRBAR
Appears as WRBAR in BSDL file.
Enable for DTRBAR
WAITBAR
BSTALL
DATACODBAR
USERSUPBAR
Appears as DCBAR in BSDL file.
Appears as SUPBAR in BSDL file.
Enable for ADSBAR, BEBAR,
BLASTBAR, DENBAR, WRRDBAR,
WAITBAR, DCBAR, SUPBAR and
LOCKBAR,
Control
NOTES:
1. Cell#1 connects to TDO and cell #112 connects to TDI.
2. All outputs are tri-state.
3. In output and bidirectional signals, a logical 1 on the enable signal enables the output. A logical 0
tri-states the output.
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80960HA/HD/HT
Table 26. 80960Hx Boundary Scan Chain (Sheet 3 of 4)
#
Boundary Scan Cell
LOCKBAR
Cell Type
Output
Comment
BREQ
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Control
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
Enable for A(31:0) and CT(3:0)
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
NMIBAR
NOTES:
1. Cell#1 connects to TDO and cell #112 connects to TDI.
2. All outputs are tri-state.
3. In output and bidirectional signals, a logical 1 on the enable signal enables the output. A logical 0
tri-states the output.
86
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80960HA/HD/HT
Table 26. 80960Hx Boundary Scan Chain (Sheet 4 of 4)
#
Boundary Scan Cell
XINT7BAR
Cell Type
Input
Comment
Appears as XINTBAR(7:0) in
BSDL file.
XINT6BAR
XINT5BAR
XINT4BAR
XINT3BAR
XINT2BAR
XINT1BAR
XINT0BAR
RESETBAR
CLKIN
Input
Input
Input
Input
Input
Input
Input
Input
Input
CT3
Output
Output
Output
Output
Appears as CT(3:0) in BSDL file.
CT2
CT1
CT0
Appears as PCHKBAR in BSDL
file.
PCHK
Output
Control
PCHK enable
NOTES:
1. Cell#1 connects to TDO and cell #112 connects to TDI.
2. All outputs are tri-state.
3. In output and bidirectional signals, a logical 1 on the enable signal enables the output. A logical 0
tri-states the output.
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80960HA/HD/HT
5.2
Boundary Scan Description Language Example
The Boundary-Scan Description Language (BSDL) for PGA Package Example, as shown in
Example 1, meets the de-facto standard means of describing essential features of ANSI/IEEE
1149.1-1993 compliant devices.
The Boundary-Scan Description Language (BSDL) for PQ2 Package Example is shown in
Example 2 on page 96.
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 1 of 8)
-- Copyright Intel Corp. 1995
- - ***************************************************************************
- - Intel Corporation makes no warranty for the use of its products and assumes no
responsibility for any errors which may appear in this document nor does it make
a commitment to update the information contained herein.
- - ***************************************************************************
- - Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto standard
means of describing essential features of ANSI/IEEE 1149.1-1990 compliant
devices. This language is under consideration by the IEEE for formal inclusion
within a supplement to the 1149.1-1990 standard. The generation of the supplement
entails an extensive IEEE review and a formal acceptance balloting procedure
which may change the resultant form of the language. Be aware that this process
may extend well into 1993, and at this time the IEEE does not endorse or hold an
opinion on the language.
- - ***************************************************************************
--
-- i960(R) Processor BSDL Model
88
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80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 2 of 8)
-- Project code HA
-- File **NOT** verified electrically
-- ------------------------------------------------
-- Rev 0.7
-- Rev 0.6
-- Rev 0.5
-- Rev 0.4
-- Rev 0.3
-- Rev 0.2
-- Rev 0.1
-- Rev 0.0
18 Dec 1995 Updated for A-1 stepping.
08 Dec 1994
21 Nov 1994
31 Oct 1994
26 July 1994
22 June 1994
16 Mar 1994
30 Aug 1993
entity Ha_Processor is
generic(PHYSICAL_PIN_MAP : string:= “PGA”);
port (A
ADSBAR
BEBAR
: out
: out
: out
bit_vector(2 to 31);
bit;
bit_vector(0 to 3);
BLASTBAR : out
bit;
BOFFBAR
BREQ
: in
bit;
: out
: out
bit;
BSTALL
bit;
BTERMBAR : in
bit;
CT
: out
: in
bit_vector(0 to 3);
CLKIN
D
bit;
: inout
: out
: inout
: out
: out
: out
: in
bit_vector(0 to 31);
DENBAR
DP
bit;
bit_vector(0 to 3);
DTRBAR
DCBAR
FAILBAR
HOLD
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
HOLDA
LOCKBAR
NMIBAR
ONCEBAR
PCHKBAR
: out
: out
: in
: in
: out
READYBAR : in
RESETBAR : in
STEST
: in
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80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 3 of 8)
SUPBAR
TCK
: out
: in
bit;
bit;
TDI
: in
bit;
TDO
: out
: in
bit;
TMS
bit;
TRST
: in
bit;
WAITBAR
WRBAR
XINTBAR
: out
: out
: in
bit;
bit;
bit_vector(0 to 7);
FIVEVREF : linkage bit;
VCCPLL
VOLTDET
VCC1
: linkage bit;
: out bit;
: linkage bit_vector(0 to 23);
: linkage bit_vector(0 to 20);
: linkage bit_vector(0 to 25);
: linkage bit_vector(0 to 22);
: linkage bit_vector(0 to 4)
VCC2
VSS1
VSS2
NC
);
use STD_1149_1_1990.all;
use i960ha_a.all;
attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP;
constant PGA:PIN_MAP_STRING :=
“A
: (D16, D17, E16, E17, F17, G16, G17, H17, J17,”&
“
K17, L17, L16, M17, N17, N16, P17, Q17, P16,”&
P15, Q16, R17, R16, Q15, S17, R15, S16, Q14, ”&
“
“
R14, Q13, S15),
: R06,”&
: (R09, S07, S06, S05),”&
“ADSBAR
“BEBAR
“BLASTBAR : S08,”&
“BOFFBAR
“BREQ
: B01,”&
: R13,”&
: R12,”&
“BSTALL
“BTERMBAR : R04,”&
“CT
: (A11, A12, A13, A14),”&
: C13,”&
“CLKIN
90
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80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 4 of 8)
“D
: (E03, C02, D02, C01, E02, D01, F02, E01, F01,”&
G01, H02, H01, J01, K01, L02, L01, M01, N01,”&
N02, P01, P02, Q01, P03, Q02, R01, S01, Q03,”&
R02, Q04, S02, Q05, R03),”&
“
“
“
“DENBAR
“DP
: S09,”&
: (A03, B03, A04, B04),”&
: S11,”&
“DTRBAR
“DCBAR
“FAILBAR
“HOLD
“HOLDA
“LOCKBAR
“NMIBAR
“ONCEBAR
“PCHKBAR
: S13,”&
: A02,”&
: R05,”&
: S04,”&
: S14,”&
: D15,”&
: C03,”&
: B08,”&
“READYBAR : S03,”&
“RESETBAR : A16,”&
“STEST
“SUPBAR
“TCK
: B02,”&
: Q12,”&
: B05,”&
“TDI
: A07,”&
“TDO
: A08,”&
“TMS
: B06,”&
“TRST
: A06,”&
“WAITBAR
“WRBAR
“ XINTBAR
: S12,”&
: S10,”&
: (B15, A15, A17, B16, C15, B17, C16, C17),”&
“FIVEVREF : C05,”&
“VOLTDET
: A05,”&
“VCCPLL
: B10,”&
“ VCC1
: (M02, K02, J02, G02, N03, F03, C06, B07, B09, B11,”&
B12, C14, E15, F16, H16, J16, K16, M16, N15, Q06,”&
R07, R08, R10, R11),”&
“
“
“ VSS1
: (G03, H03, J03, K03, L03, M03, C07, C08, C09, C10,”&
C11, C12, Q07, Q08, Q09, Q10, Q11, F15, G15, H15,”&
J15, K15, L15, M15, A01, C04),”&
: (A09, A10, B13, B14, D03)”;
“
“
“NC
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80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 5 of 8)
attribute Tap_Scan_In
attribute Tap_Scan_Mode of TMS
attribute Tap_Scan_Out of TDO
of TDI
: signal is true;
: signal is true;
: signal is true;
attribute Tap_Scan_Reset of TRST : signal is true;
attribute Tap_Scan_Clock of TCK
: signal is (66.0e6, BOTH);
attribute Instruction_Length of Ha_Processor: entity is 4;
attribute Instruction_Opcode of Ha_Processor: entity is
“BYPASS
“EXTEST
“SAMPLE
“IDCODE
“RUBIST
“CLAMP
(1111),” &
(0000),” &
(0001),” &
(0010),” &
(0111),” &
(0100),” &
(1000),” &
(1011, 1100)”;
“HIGHZ
“Reserved
attribute Instruction_Capture of Ha_Processor: entity is “0001”;
attribute Instruction_Private of Ha_Processor: entity is “Reserved” ;
attribute Idcode_Register of Ha_Processor: entity is
“0010”
& --version,
“1000100001000000” & --part number
“00000001001”
“1”;
& --manufacturers identity
--required by the standard
attribute Register_Access of Ha_Processor: entity is
“Runbist[32]
“Bypass
(RUBIST),” &
(CLAMP, HIGHZ)”;
{***************************************************************************}
{ The first cell, cell 0, is closest to TDO
}
}
{ BC_1:Control, Output3 CBSC_1:Bidir BC_4: Input, Clock
{***************************************************************************}
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80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 6 of 8)
attribute Boundary_Cells of Ha_Processor: entity is “BC_4, BC_1, CBSC_1”;
attribute Boundary_Length of Ha_Processor: entity is 112;
attribute Boundary_Register of Ha_Processor: entity is
“0 (CBSC_1, DP(3),
“1 (CBSC_1, DP(2),
“2 (CBSC_1, DP(0),
“3 (CBSC_1, DP(1),
bidir,
bidir,
bidir,
bidir,
input,
X,
17, 1, Z),”
&
&
&
&
X,
17, 1, Z),”
X,
17, 1, Z),”
X,
17, 1, Z),”
“4 (BC_4,
“5 (BC_1,
“6 (BC_1,
“7 (BC_4,
“8 (BC_4,
STEST,
FAILBAR,
*,
X),”
&
output3, X,
6, 1, Z),”
&
control, 1),”
&
&
&
ONCEBAR,
BOFFBAR,
input,
input,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
X),”
X),”
“9 (CBSC_1, D(0),
“10 (CBSC_1, D(1),
“11 (CBSC_1, D(2),
“12 (CBSC_1, D(3),
“13 (CBSC_1, D(4),
“14 (CBSC_1, D(5),
“15 (CBSC_1, D(6),
“16 (CBSC_1, D(7),
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
&
&
&
&
&
&
&
&
“17 (BC_1,
*,
control, 1),”
&
“18 (CBSC_1, D(8),
“19 (CBSC_1, D(9),
“20 (CBSC_1, D(10),
“21 (CBSC_1, D(11),
“22 (CBSC_1, D(12),
“23 (CBSC_1, D(13),
“24 (CBSC_1, D(14),
“25 (CBSC_1, D(15),
“26 (CBSC_1, D(16),
“27 (CBSC_1, D(17),
“28 (CBSC_1, D(18),
“29 (CBSC_1, D(19),
“30 (CBSC_1, D(20),
“31 (CBSC_1, D(21),
“32 (CBSC_1, D(22),
“33 (CBSC_1, D(23),
“34 (CBSC_1, D(24),
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
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80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 7 of 8)
“35 (CBSC_1, D(25),
“36 (CBSC_1, D(26),
“37 (CBSC_1, D(27),
“38 (CBSC_1, D(28),
“39 (CBSC_1, D(29),
“40 (CBSC_1, D(30),
“41 (CBSC_1, D(31),
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
input,
input,
input,
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
&
&
&
&
&
&
&
“42 (BC_4,
“43 (BC_4,
“44 (BC_4,
“45 (BC_1,
“46 (BC_1,
“47 (BC_1,
“48 (BC_1,
“49 (BC_1,
“50 (BC_1,
“51 (BC_1,
“52 (BC_1,
“53 (BC_1,
“54 (BC_1,
“55 (BC_1,
“56 (BC_1,
“57 (BC_1,
“58 (BC_1,
“59 (BC_1,
“60 (BC_1,
“61 (BC_1,
“62 (BC_1,
“63 (BC_1,
“64 (BC_1,
“65 (BC_1,
“66 (BC_1,
“67 (BC_1,
“68 (BC_1,
“69 (BC_1,
“70 (BC_1,
“71 (BC_1,
BTERMBAR,
X),”
X),”
X),”
&
&
&
READYBAR,
HOLD,
HOLDA,
*,
output3, X, 46, 1, Z),”
control, 1),”
&
&
ADSBAR,
BEBAR(3),
BEBAR(2),
BEBAR(1),
BEBAR(0),
BLASTBAR,
DENBAR,
WRBAR,
DTRBAR,
*,
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 56, 1, Z),”
&
&
&
&
&
&
&
&
&
control, 1),”
&
WAITBAR,
BSTALL,
DCBAR,
SUPBAR,
*,
output3, X, 61, 1, Z),”
output3, X, 6, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
&
&
&
&
control, 1),”
&
LOCKBAR,
BREQ,
output3, X, 61, 1, Z),”
output3, X, 6, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
&
&
&
&
&
&
&
&
&
&
A(31),
A(30),
A(29),
A(28),
A(27),
A(26),
A(25),
A(24),
“72 (BC_1, A(23),
“73 (BC_1, A(22),
&
&
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80960HA/HD/HT
Example 1. Boundary-Scan Description Language (BSDL) for PGA
Package Example (Sheet 8 of 8)
“74 (BC_1, A(21),
“75 (BC_1, A(20),
“76 (BC_1, A(19),
“77 (BC_1, A(18),
“78 (BC_1, A(17),
“79 (BC_1, A(16),
“80 (BC_1, *,
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
&
&
&
&
&
&
control, 1),”
&
“81 (BC_1, A(15),
“82 (BC_1, A(14),
“83 (BC_1, A(13),
“84 (BC_1, A(12),
“85 (BC_1, A(11),
“86 (BC_1, A(10),
“87 (BC_1, A(9),
“88 (BC_1, A(8),
“89 (BC_1, A(7),
“90 (BC_1, A(6),
“91 (BC_1, A(5),
“92 (BC_1, A(4),
“93 (BC_1, A(3),
“94 (BC_1, A(2),
“95 (BC_4, NMIBAR,
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
&
&
&
&
&
&
&
&
&
&
&
&
&
&
input,
X),”
X),”
X),”
X),”
X),”
X),”
X),”
X),”
X),”
X),”
X),”
&
&
&
&
&
&
&
&
&
&
&
“96 (BC_4, XINTBAR(7), input,
“97 (BC_4, XINTBAR(6), input,
“98 (BC_4, XINTBAR(5), input,
“99 (BC_4, XINTBAR(4), input,
“100(BC_4, XINTBAR(3), input,
“101(BC_4, XINTBAR(2), input,
“102(BC_4, XINTBAR(1), input,
“103(BC_4, XINTBAR(0), input,
“104(BC_4, RESETBAR,
“105(BC_4, CLKIN,
“106(BC_1, CT(3),
“107(BC_1, CT(2),
“108(BC_1, CT(1),
“109(BC_1, CT(0),
“110(BC_1, PCHKBAR,
“111(BC_1, *,
input,
input,
output3, X, 80, 1, Z),”
&
&
&
&
&
output3, X,
output3, X,
output3, X,
80, 1, Z),”
80, 1, Z),”
80, 1, Z),”
output3, X, 111, 1, Z),”
control, 1)”;
end Ha_Processor;
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80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 1 of 8)
-- Copyright Intel Corporation 1995, 1996
-- *****************************************************************************
-- Intel Corporation makes no warranty for the use of its products and assumes no
responsibility for any errors which may appear in this document nor does it make
a commitment to update the information contained herein.
-- *****************************************************************************
-- Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto
-- standard means of describing essential features of ANSI/IEEE 1149.1-1990
compliant devices. This language is under consideration by the IEEE for formal
inclusion within a supplement to the 1149.1-1990 standard. The generation of the
supplement entails an extensive IEEE review and a formal acceptance balloting
procedure which may change the resultant form of the language. Be aware that this
process may extend well into 1993, and at this time the IEEE does not endorse or
hold an opinion on the language.
-- i960(R) Processor BSDL Model
-- Project code HA
-- File **NOT** verified electrically
-- -----------------------------------------------
-- Rev 0.8
-- Rev 0.7
-- Rev 0.6
-- Rev 0.5
-- Rev 0.4
-- Rev 0.3
-- Rev 0.2
-- Rev 0.1
-- Rev 0.0
4 Apr 1996 Changed for PQ2 Package
18 Dec 1995 Updated for A-1 stepping.
08 Dec 1994
21 Nov 1994
31 Oct 1994
26 July 1994
22 June 1994
16 Mar 1994
30 Aug 1993
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80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 2 of 8)
entity Ha_Processor is
generic(PHYSICAL_PIN_MAP : string:= “PQ2”);
port (A
ADSBAR
BEBAR
: out
: out
: out
bit_vector(2 to 31);
bit;
bit_vector(0 to 3);
BLASTBAR : out
bit;
BOFFBAR
BREQ
: in
bit;
: out
: out
bit;
BSTALL
bit;
BTERMBAR : in
bit;
CT
: out
: in
bit_vector(0 to 3);
CLKIN
D
bit;
: inout
: out
: inout
: out
: out
: out
: in
bit_vector(0 to 31);
DENBAR
DP
bit;
bit_vector(0 to 3);
DTRBAR
DCBAR
FAILBAR
HOLD
bit;
bit;
bit;
bit;
HOLDA
LOCKBAR
NMIBAR
ONCEBAR
PCHKBAR
: out
: out
: in
bit;
bit;
bit;
: in
bit;
: out
bit;
READYBAR : in
RESETBAR : in
bit;
bit;
STEST
SUPBAR
TCK
: in
bit;
: out
: in
bit;
bit;
TDI
: in
bit;
TDO
: out
: in
bit;
TMS
bit;
TRST
: in
bit;
WAITBAR
WRBAR
XINTBAR
: out
: out
: in
bit;
bit;
bit_vector(0 to 7);
FIVEVREF : linkage bit;
VCCPLL : linkage bit;
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80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 3 of 8)
VCC1
VCC2
VSS1
VSS2
: linkage bit_vector(0 to 23);
: linkage bit_vector(0 to 23);
: linkage bit_vector(0 to 23);
: linkage bit_vector(0 to 23)
);
use STD_1149_1_1990.all;
use i960ha_a.all;
attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP;
constant PQ2:PIN_MAP_STRING :=
“A
: (151, 150, 147, 146, 145, 144, 141, 140, 139, 138,”&
135, 134, 133, 132, 127, 126, 125, 124, 121, 120,”&
119, 118, 113, 112, 111, 110, 107, 106, 105, 104),”&
: 77,”&
“
“
“ADSBAR
“BEBAR
: (83, 82, 79, 78),”&
“BLASTBAR : 84,”&
“BOFFBAR
“BREQ
: 10,”&
: 100,”&
: 91,”&
“BSTALL
“BTERMBAR : 67,”&
“CT
: (183, 182, 181, 180),”&
“CLKIN
“D
: 175,”&
: (12, 13, 14, 15, 20, 21, 22, 23, 26, 27, 28, 29,”&
“
34, 35, 36, 37, 39, 40, 41, 42, 45, 50, 51, 52,”&
“
54, 55, 56, 57, 61, 62, 63, 64),”&
“DENBAR
“DP
: 85,”&
: (206, 207, 203, 202),”&
: 89,”&
“DTRBAR
“DCBAR
“FAILBAR
“HOLD
“HOLDA
“LOCKBAR
“NMIBAR
: 96,”&
: 5,”&
: 69,”&
: 72,”&
: 99,”&
: 159,”&
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80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 4 of 8)
“ONCEBAR
“PCHKBAR
: 6,”&
: 189,”&
“READYBAR : 68,”&
“RESETBAR : 174,”&
“STEST
“SUPBAR
“TCK
: 208,”&
: 97,”&
: 194,”&
“TDI
: 191,”&
“TDO
: 188,”&
“TMS
: 192,”&
“TRST
: 193,”&
“WAITBAR
“WRBAR
“XINTBAR
: 90,”&
: 88,”&
: (169, 168, 167, 166, 163, 162, 161, 160),”&
“FIVEVREF : 197,”&
“VCCPLL
: 177,”&
“VCC1
: (1, 4, 9, 11, 17, 19, 25, 31, 33, 38, 44, 46,”&
49, 59, 60, 66, 71, 74, 76, 81, 87, 92, 95, 101),”&
: (102, 109, 115, 117, 123, 128, 131, 137, 143, 149,”&
153, 154, 158, 165, 171, 173, 176, 179, 185, 187,”&
196, 199, 201, 204),”&
“
“VCC2
“
“
“VSS1
: (2, 3, 7, 8, 16, 18, 24, 30, 32, 43, 47, 48,”&
53, 58, 65, 70, 73, 75, 80, 86, 93, 94, 98, 103),”&
: (108, 114, 116, 122, 129, 130, 136, 142, 148, 152,”&
155, 156, 157, 164, 170, 172, 178, 184, 186, 190,”&
195, 198, 200, 205)”;
“
“VSS2
“
“
attribute Tap_Scan_In
attribute Tap_Scan_Mode of TMS
attribute Tap_Scan_Out of TDO
of TDI
: signal is true;
: signal is true;
: signal is true;
attribute Tap_Scan_Reset of TRST : signal is true;
attribute Tap_Scan_Clock of TCK
: signal is (66.0e6, BOTH);
attribute Instruction_Length of Ha_Processor: entity is 4;
attribute Instruction_Opcode of Ha_Processor: entity is
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80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 5 of 8)
“BYPASS
“EXTEST
“SAMPLE
“IDCODE
“RUBIST
“CLAMP
(1111),” &
(0000),” &
(0001),” &
(0010),” &
(0111),” &
(0100),” &
(1000),” &
(1011, 1100)”;
“HIGHZ
“Reserved
attribute Instruction_Capture of Ha_Processor: entity is “0001”;
attribute Instruction_Private of Ha_Processor: entity is “Reserved” ;
attribute Idcode_Register of Ha_Processor: entity is
“0001”& version,
“1000100001000000”
“00000001001”& manufacturers identity
“1”; required by the standard
& part number
attribute Register_Access of Ha_Processor: entity is
“Runbist[32]
“Bypass
(RUBIST),” &
(CLAMP, HIGHZ)”;
*******************************************************************************
{ The first cell, cell 0, is closest to TDO
}
}
{ BC_1:Control, Output3 CBSC_1:Bidir BC_4: Input, Clock
*******************************************************************************
attribute Boundary_Cells of Ha_Processor: entity is “BC_4, BC_1, CBSC_1”;
attribute Boundary_Length of Ha_Processor: entity is 112;
attribute Boundary_Register of Ha_Processor: entity is
“0 (CBSC_1, DP(3),
“1 (CBSC_1, DP(2),
“2 (CBSC_1, DP(0),
“3 (CBSC_1, DP(1),
“4 (BC_4, STEST,
“5 (BC_1, FAILBAR,
bidir,
bidir,
bidir,
bidir,
input,
X,
17, 1, Z),”
17, 1, Z),”
17, 1, Z),”
17, 1, Z),”
&
&
&
&
&
X,
X,
X,
X),”
output3, X,
6, 1, Z),”
&
100
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Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 6 of 8)
“6 (BC_1,
“7 (BC_4,
“8 (BC_4,
*,
control, 1),”
&
&
&
ONCEBAR,
BOFFBAR,
input,
input,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
X),”
X),”
“9 (CBSC_1, D(0),
“10 (CBSC_1, D(1),
“11 (CBSC_1, D(2),
“12 (CBSC_1, D(3),
“13 (CBSC_1, D(4),
“14 (CBSC_1, D(5),
“15 (CBSC_1, D(6),
“16 (CBSC_1, D(7),
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
&
&
&
&
&
&
&
&
“17 (BC_1,
*,
control, 1),”
&
“18 (CBSC_1, D(8),
“19 (CBSC_1, D(9),
“20 (CBSC_1, D(10),
“21 (CBSC_1, D(11),
“22 (CBSC_1, D(12),
“23 (CBSC_1, D(13),
“24 (CBSC_1, D(14),
“25 (CBSC_1, D(15),
“26 (CBSC_1, D(16),
“27 (CBSC_1, D(17),
“28 (CBSC_1, D(18),
“29 (CBSC_1, D(19),
“30 (CBSC_1, D(20),
“31 (CBSC_1, D(21),
“32 (CBSC_1, D(22),
“33 (CBSC_1, D(23),
“34 (CBSC_1, D(24),
“35 (CBSC_1, D(25),
“36 (CBSC_1, D(26),
“37 (CBSC_1, D(27),
“38 (CBSC_1, D(28),
“39 (CBSC_1, D(29),
“40 (CBSC_1, D(30),
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
X, 17, 1, Z),”
&
&
&
&
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&
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&
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&
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Datasheet
101
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80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 7 of 8)
“41 (CBSC_1, D(31),
“42 (BC_4, BTERMBAR,
“43 (BC_4, READYBAR,
“44 (BC_4, HOLD,
“45 (BC_1, HOLDA,
“46 (BC_1, *,
bidir,
input,
input,
input,
X, 17, 1, Z),”
X),” &
&
&
X),” &
X),” &
output3, X, 46, 1, Z),”
control, 1),” &
“47 (BC_1, ADSBAR,
“48 (BC_1, BEBAR(3),
“49 (BC_1, BEBAR(2),
“50 (BC_1, BEBAR(1),
“51 (BC_1, BEBAR(0),
“52 (BC_1, BLASTBAR,
“53 (BC_1, DENBAR,
“54 (BC_1, WRBAR,
“55 (BC_1, DTRBAR,
“56 (BC_1, *,
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 56, 1, Z),”
control, 1),” &
&
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&
&
&
&
&
&
“57 (BC_1, WAITBAR,
“58 (BC_1, BSTALL,
“59 (BC_1, DCBAR,
“60 (BC_1, SUPBAR,
“61 (BC_1, *,
output3, X, 61, 1, Z),”
output3, X, 6, 1, Z),”
output3, X, 61, 1, Z),”
output3, X, 61, 1, Z),”
control, 1),” &
&
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&
&
“62 (BC_1, LOCKBAR,
“63 (BC_1, BREQ,
“64 (BC_1, A(31),
“65 (BC_1, A(30),
“66 (BC_1, A(29),
“67 (BC_1, A(28),
“68 (BC_1, A(27),
“69 (BC_1, A(26),
“70 (BC_1, A(25),
“71 (BC_1, A(24),
“72 (BC_1, A(23),
“73 (BC_1, A(22),
“74 (BC_1, A(21),
“75 (BC_1, A(20),
output3, X, 61, 1, Z),”
output3, X, 6, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
&
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&
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&
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&
&
102
Datasheet
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80960HA/HD/HT
Example 2. Boundary-Scan Description Language (BSDL) for PQ2
Package Example (Sheet 8 of 8)
“76 (BC_1, A(19),
“77 (BC_1, A(18),
“78 (BC_1, A(17),
“79 (BC_1, A(16),
“80 (BC_1, *,
output3, X, 80, 1, Z),”
&
&
&
&
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
control, 1),”
&
“81 (BC_1, A(15),
“82 (BC_1, A(14),
“83 (BC_1, A(13),
“84 (BC_1, A(12),
“85 (BC_1, A(11),
“86 (BC_1, A(10),
“87 (BC_1, A(9),
“88 (BC_1, A(8),
“89 (BC_1, A(7),
“90 (BC_1, A(6),
“91 (BC_1, A(5),
“92 (BC_1, A(4),
“93 (BC_1, A(3),
“94 (BC_1, A(2),
“95 (BC_4, NMIBAR,
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
&
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&
&
&
&
&
&
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&
&
&
&
&
input,
X),”
X),”
X),”
X),”
X),”
X),”
X),”
X),”
X),”
X),”
X),”
&
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&
&
“96 (BC_4, XINTBAR(7), input,
“97 (BC_4, XINTBAR(6), input,
“98 (BC_4, XINTBAR(5), input,
“99 (BC_4, XINTBAR(4), input,
“100(BC_4, XINTBAR(3), input,
“101(BC_4, XINTBAR(2), input,
“102(BC_4, XINTBAR(1), input,
“103(BC_4, XINTBAR(0), input,
“104(BC_4, RESETBAR,
“105(BC_4, CLKIN,
“106(BC_1, CT(3),
“107(BC_1, CT(2),
“108(BC_1, CT(1),
“109(BC_1, CT(0),
“110(BC_1, PCHKBAR,
“111(BC_1, *,
input,
input,
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 80, 1, Z),”
output3, X, 111,1, Z),”
control, 1)”;
&
&
&
&
&
end Ha_Processor;
Datasheet
103
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80960HA/HD/HT
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104
Datasheet
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