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Intel Xeon™ Processor with 800
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MHz System Bus, Intel E7520
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Chipset, and Intel 6300ESB ICH
Development Kit
User’s Manual
September 2004
Reference Number: 300281-003
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Contents
Contents
Product Overview ............................................................................................................................7
Related Documents ..............................................................................................................7
Product Contents..................................................................................................................7
Products Feature List............................................................................................................8
1.4.1 Memory Subsystem ...............................................................................................11
1.4.2 DIMM Placement DDR2 400..................................................................................11
Memory Population Rules and Configurations ...................................................................12
Platform Management ...................................................................................................................13
Soft Off................................................................................................................................13
Sleep States Supported......................................................................................................13
2.3.1 S0 State .................................................................................................................13
2.3.2 S1 State .................................................................................................................14
2.3.3 S2 State .................................................................................................................14
2.3.4 S3 State .................................................................................................................14
2.3.5 S4 State .................................................................................................................14
2.3.6 S5 State .................................................................................................................15
2.3.7 Wake-Up Events....................................................................................................15
2.3.8 Wake-Up from S1 Sleep State...............................................................................15
2.3.9 Wake-Up from S4 and S5 States...........................................................................15
PCI PM Support..................................................................................................................15
2.5.1 Processor Thermal Management...........................................................................16
System Fan Operation........................................................................................................16
Equipment Required for CRB Usage.............................................................................................17
Precautions.........................................................................................................................17
Driver and OS Requirements..............................................................................................18
3.2.1 Drivers included on CD..........................................................................................18
Jumpers and Headers ...................................................................................................................21
4.1 Jumpers..............................................................................................................................21
Power Diagrams .................................................................................................................25
Platform Clocking................................................................................................................26
Platform Resets ..................................................................................................................27
SMBus ................................................................................................................................28
Platform IRQ Routing..........................................................................................................29
Miscellaneous Buttons........................................................................................................32
Debug Procedure ..........................................................................................................................33
Level 2 Debug (Power Sequence)......................................................................................34
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Contents
Level 3 Debug (Voltage References)..................................................................................34
Heatsink Assembly........................................................................................................................35
7.1 Processor Heat Sink Installation Instructions .....................................................................36
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Contents
Figures
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6300ESB Customer Reference Board Block Diagram .................................................................9
Placement - Top View.................................................................................................................10
DDR2 400 Memory - DIMM Ordering .........................................................................................12
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6300ESB Customer Reference Board Jumper...........................................................................21
Power Distribution Block Diagram ..............................................................................................25
Clock Block Diagram ..................................................................................................................26
Platform Reset Diagram .............................................................................................................27
SMBus Block Diagram................................................................................................................28
IRQ Routing Diagram .................................................................................................................29
10 Power Buttons ............................................................................................................................32
11 Components Requiring Heat Sink Assembly..............................................................................35
12 Inserting Processor in Socket.....................................................................................................36
13 Cleaning the Processor Surface.................................................................................................36
14 Installing the Processor Backplate..............................................................................................37
15 Removing the Protective Covers ................................................................................................37
16 Installing the Heatsink.................................................................................................................38
Tables
Supported DIMM Module Types.................................................................................................11
DIMM Placement DDR2 400 ......................................................................................................11
Jumper Settings..........................................................................................................................22
Processor VRD Settings.............................................................................................................30
Level 1 Debug (Port 80/BIOS)....................................................................................................33
Level 2 Debug (Power Sequence)..............................................................................................34
Components Requiring Heat Sink Assembly..............................................................................35
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Contents
Revision History
Date
Revision
Description
Changed figures that referenced PCI-X to PCI-X 133 MHz;
changed jumpers on Figure 4; made other miscellaneous
changes.
August 2004
003
July 2004
002
001
Changed code names to public names; clarified illustrations.
Initial release of this document.
December 2003
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Product Overview
Product Overview
1
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The Intel Xeon™ Processor with 800 MHz System Bus, Intel E7520 Chipset, and Intel
6300ESB ICH Development Kit comprise an IA-32 based dual-processor platform. This platform
serves as a reference for OEMs development platform. This and other development kits from Intel
provide a fully working product with range of performance options which can be modified or used
immediately for product development.
1.1
Related Documents
Table 1.
Related Documents
Document/Reference Title
Source/Document Number
Intel® E7520 Memory Controller Hub (MCH) Datasheet
Intel® E7520 Memory Controller Hub (MCH) Specification Update
Intel® Xeon™ Processor with 800 MHz System Bus Datasheet
Intel 6300ESB I/O Controller Datasheet
Intel® Xeon™ Processor Debug Port Design Guide
Extended Debug Port Design Guide: for UP and DP platforms
Schematics file
Contact your Intel Sales
Representative for access
1.2
Product Contents
The Reference Board is shipped with the following components and features:
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• Two Intel Xeon™ processors (2.8 GHz and 3.2 GHz) capable of 800 MT/s
• One 550 W SSI EPS12V power supply
• Two Heat sinks for the two processors
• Two pieces of DDR2 400 [256 Mbytes]
• Blank Hard drive
• CD with necessary drivers
— Red Hat 8.0 Compatible Driver Package Contents
— Red-Hat Advanced Server 2.1 Compatible Driver Package Contents
— Windows* Compatible Driver Package Contents
— ATI Rage* Mobility-M Graphics Accelerator
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Product Overview
1.3
Products Feature List
• Processor Support
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— Dual Intel Xeon™ Processors
— On-board processor voltage regulators compatible with VRM/EVRD 10.1 Design Guide
• Clocking
— CK409B clock synthesizer that generates all host clock and the PCI Express* interface
clock for the MCH PHY Layer
— DB800 generates the PCI Express differential pair clocks to the onboard PCI Express
components and the dedicated PCI Express slots
• Memory Support
— Registered, ECC, DDR2 400
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— Each of the two memory channels on the Intel E7520 in this CRB supports a maximum
of two DDR2 400 DIMMs per channel
— The maximum supported DDR2 400 memory configuration is 8 Gbyte using different
combinations of single and dual ranked, x4, 1 Gbyte technology DIMMs (limit of up to
four ranks per channel)
— 3.2 Gbytes/s bus per channel bandwidth with DDR2 400
• I/O slot support
— One PCI-X 133 MHz slot from PXH
— Two PCI-X 100 MHz slots from PXH
— One PCI Express x8 slot
— One PCI Express x4 slot
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— One 5 V PCI-32/33 slot connected through the Intel 6300ESB I/O Controller
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— Two 3.3 V PCI-X 64/66 slots connected through the Intel 6300ESB I/O Controller
• Low Pin Count Bus
— National* LPC 47M172 Super I/O residing on LPC bus
— LPC card header for debug purposes only
— Firmware hub
• IDE ATA 100 support
— Two ATA-100 IDE connectors supported
• S-ATA support
— Two S-ATA connectors
• USB Support (Four Channels)
— Two USB 2.0 connectors
— Two USB 2.0 headers
• Back Panel I/O
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Product Overview
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— Two RS-232 serial ports from the Intel 6300ESB I/O Controller
— Two PS/2 connectors for mouse and keyboard
— On-board VGA Video, ATI Rage Mobility* video controller
— Parallel port
• Dual Watchdog Timer
• Miscellaneous
— National LM93* for fan control and temperature/voltage monitoring
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system bus and Intel E7520 and Intel 6300ESB Customer Reference Board (CRB).
1.4
Block Diagram
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Figure 1.
Intel Xeon™ Processor with 800 MHz System Bus and Intel E7520 and Intel
6300ESB Customer Reference Board Block Diagram
Intel®
Xeon
Intel®
Xeon
ITP
PCI-X
133 MHz
PCI-E
DDR2 400
PXH
Intel®
E7520
MCH
PCI-X 100MHz
PCI-E
DDR2400
LM 93
PCI-E x4
PCI-E x8
CK409B
DB800
HI 1.5
PCI-X 66MHz
IDE
IDE
PCI-X
PCI
Intel®
6300ESB
ICH
PCI 33MHz
S-ATA
S-ATA
VGA
UART 1
UART 2
USB 2.0
USB 2.0
USB 2.0
USB 2.0
Floppy
SIO
Parallel
FWH
LPC Debug
PS2
UART 3
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Product Overview
1.4.1
Memory Subsystem
The memory subsystem is designed to support Double Data Rate2(DDR2) Synchronous Dynamic
Random Access Memory (SDRAM) using the Intel(R) E7520 MCH. The MCH provides two
independent DDR channels, which support DDR2 400 DIMMs. The peak bandwidth of each
DDR2 branch channel is 3.2 Gbyte/s (8 bytes x 400 MT/s) with DDR2 400. The two DDR2
channels from the MCH operate in lock step; the effective overall peak bandwidth of the DDR2
memory subsystem is 6.4 Gbyte/s for DDR2 400.
Table 2.
Supported DIMM Module Types
Technology
Organization
SDRAM Chips/DIMM
8 Mbytes x 8 x 4 banks
16 Mbytes x 4 x 4 banks
16 Mbytes x 8 x 4 banks
32 Mbytes x 4 x 4 banks
32 Mbytes x 8 x 4 banks
64 Mbytes x 4 x 4 banks
8
16
8
256 Mbit
512 Mbit
1 Gbit
16
8
16
1.4.2
DIMM Placement DDR2 400
Table 3.
DIMM Placement DDR2 400
DIMM Configuration
DIMM1
DIMM2
1 Single Rank
1 Dual Rank
Empty
Empty
Single Rank
Dual Rank
Single Rank
Dual Rank
Dual Rank
2 Single Rank
Single Rank
Single Rank
Dual Rank
1 Dual Rank, 1 Single Rank
2 Dual Rank
NOTES:
1. Populate DIMMs starting with the sockets farthest away from the MCH (DIMM slots A2 and B2).
2. When populating both channels, always place identical DIMMs in sockets that have the same position on
channel A and channel B (i.e., DIMM A2 should be identical to DIMM B2).
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Product Overview
1.5
Memory Population Rules and Configurations
The system supports two DDR2 400 DIMM slots for Channel A and two DDR2 400 DIMM slots
for Channel B. The four slots are interleaved and placed in a row in the following order: A1, B1,
A2, B2, with A1 being closest to the MCH. This design supports only registered ECC-enabled
DIMMs.
When populating both channels, always place identical DIMMs in sockets that have the same
position on Channel A and Channel B (i.e., DIMM A2 should be identical to DIMM B2).
In addition, single-rank DIMMs should be populated furthest when a combination of single-rank
and double-rank DIMMs are used. This recommendation is based on the signal integrity
requirements of the DDR2 interface.
Figure 3.
DDR2 400 Memory - DIMM Ordering
+
+
+
MCH
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Platform Management
Platform Management
2
The following sections describe how the system power management operates and how the different
ACPI states are implemented. Platform management involves:
• ACPI implementation specific details
• System monitoring, control and response to thermal, voltage and intrusion events
• BIOS security
2.1
Power Button
The system power button is connected to the I/O controller component. When the button is pressed,
the I/O controller receives the signal and transitions the system to the proper sleep state as
determined by the operating system and software. If the power button is pressed and held for four
seconds, the system powers off (S5 state). This feature is called power button override and is
particularly helpful in case of system hang and system lock.
2.2
2.3
Soft Off
The I/O controller incorporates a SLP_S4 output signal which routes to the power supply. This
signal has register access that allows software to deactivate the power supply. When SLP_S4 goes
active, the power supply cuts main power but keeps 5 V auxiliary power rails available. 5 V
auxiliary voltage is active while the power supply receives AC power.
Sleep States Supported
The I/O controller controls the system sleep states. States S0, S1, S3, S4, and S5 are supported. The
platform enters sleep states in response to BIOS, operating system or user actions. Normally the
operating system determines which sleep state to transition into. However, a four-second power
button override event places the system immediately into S5. When transitioning into a software-
invoked sleep state, the I/O controller attempts to gracefully put the system to sleep by first going
into the processor C2 state.
2.3.1
S0 State
This is the normal operating state, even though there are some power savings modes in this state
using processor Halt and Stop Clock (processor C1 and C2 states). S0 affords the fastest wake-up
response time of any sleep state because the system remains fully powered and memory is intact.
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Platform Management
2.3.2
S1 State
This state is entered via a processor Sleep signal from the I/O controller (processor C3 state). The
system remains fully powered with memory contents intact but the processors enter their lowest
power state. The operating system disables bus masters for uniprocessor configurations while
flushing and invalidating caches before entering this state in multiprocessor configurations. Wake-
up latency is slightly longer in this state than in S0; however, power savings are improved from S0.
2.3.3
2.3.4
S2 State
This state is not supported.
S3 State
This state is called Suspend to RAM (STR). The system context is maintained in system DRAM,
but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks
stop except the RTC. S3 is entered when the I/O controller asserts the SLP_S3# signal to
downstream circuitry to control 1.8 V power plane switching. Power must be switched from the
normal 1.8 V rail to standby 1.8 V, because the EPS-12V 550 W power supply does not directly
supply a standby 1.8 V rail. The sequence to enter Suspend to RAM is as follows:
1. The OS and BIOS prepare for S3 sleep state.
2. The OS sets the appropriate sleep bits in the I/O controller.
3. The I/O controller drives STPCLK to the processors.
4. The processors respond with a Stop-Grant cycle, passed over hub interface by MCH.
5. The I/O controller indicates an S3 (STR) sleep mode to the MCH via Hub Interface A.
6. The MCH puts DDR memory into the self-refresh mode.
7. The MCH drives DDR CMDCLK differential pairs and all DDR outputs low.
8. The MCH drives a completion message via Hub Interface A to the I/O controller.
9. The I/O controller turns off all voltage rails (except Standby 5V) from the main power supply
by asserting the SLP_S3_N signal.
— When in the S3 state, only the Standby 5 V rail is available from the power supply. The
board uses this standby source to generate 1.8 V standby rail to power the DIMMs.
— The asserted SLP_S3_N signal also controls the logic to switch the DIMM power source
from main 1.8 V to standby 1.8 V.
2.3.5
S4 State
This state is called Suspend to Disk. From a hardware perspective, it is equivalent to an S5 state.
The operating system is responsible for saving the system context in a special partition on the hard
drive. Although the system must power up and fully boot, boot time to an application is reduced
because the platform is returned to the same system state as when the preceding power off
occurred.
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Platform Management
2.3.6
2.3.7
S5 State
This state is the normal off state whether entered through the Power Button or Soft Off. All power
is shut off except for the logic required to restart. The system remains in the S5 State only while the
power supply is plugged into the electrical outlet. If the power supply is unplugged, this is
considered a Mechanical OFF or G3.
Wake-Up Events
The types of wake-up events and wake-up latencies are related to the actual power rails available to
the system in a particular sleep state, as well as to the location in which the system context is
stored. Regardless of the Sleep State, Wake on the Power Button is always supported except in a
mechanical off situation. When in a Sleep State, the system complies with the PCI specification by
supplying the optional 3.3 V standby voltage to each PCI slot as well as the PME# signal. This
enables any compliant PCI card to wake up the system from supported sleep states except
Mechanical Off.
Note: Wake on USB, Wake on PS/2, and Wake on LAN are not supported.
2.3.8
Wake-Up from S1 Sleep State
During S1, the system is fully powered, permitting support for PCI Express* Wake and Wake on
PCI PME#.
2.3.9
Wake-Up from S4 and S5 States
The power button is used to wake from S4 and S5.
2.4
PCI PM Support
This design holds the system reset signal low when in a sleep state. The system supports the PCI
PME# signal and provides 3.3 V standby to the PCI and PCI Express slots. This support allows any
compliant PCI or PCI Express card to wake up the system from any sleep state except mechanical
off. The user and the operating system must configure the system carefully following the PCI
power management interface specification because of the limited amount of power available on
3.3 V standby.
2.5
Platform Management
The LM 93 monitors the majority of the system voltages. The VID signals from the processors are
also monitored by LM 93. All voltage levels can be read via the SMBus.
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Platform Management
2.5.1
Processor Thermal Management
Each processor monitors its own core temperature and thermally manages itself when it reaches a
certain temperature. The system also uses the internal processor diode to monitor the die
temperature. The diode pins are routed to the diode input pins in the LM 93. The LM 93 can be
programmed to force the processor fans to full speed operation when it senses the processor core
temperature exceeding a specific value. In addition, the LM 93 has an on chip thermal monitor
which allows it to monitor the incoming ambient temperature. Additional processor thermal
management requires the system to communicate to the processors when the VRD reaches a
critical temperature. The VR thermal monitor asserts FORCEPR_N signal to the processor. The
thermal monitor, an LM26, is a ±3° C precision thermostat used to sense high temperature
conditions and drive a digital output active low. This circuit works as an external PROCHOT event
to further protect the processor during high current/temperature conditions. This forces the
processor to activate a thermal protection circuit that reduces the current consumption of the
processor.
2.6
System Fan Operation
The system uses both the LM 93 and the National* 87427 Super I/O to monitor and control the fans
in the system.The LM93 uses pulse width modulated (PWM) outputs that can modulate the voltage
across the fans, providing a variable duty cycle to effect a reduced DC voltage from nominal 12
VDC. The fan headers are the standard 12V, three-pin type, used in previous Servers, which
support tachometer out. The LM 93 also has four tachometer inputs that it can use to monitor the
fans that it is controlling. All fan tachometer data can be extracted from the controllers via the
SMBus. The system fan speed control circuit does not control the power supply fan. Each PWM
output has a bypass jumper that causes all fans to run at full speed and ignore the PWM control.
Each processor fan has its own dedicated PWM output and tachometer input, so each fan is
controlled and monitored independently, depending on the core temperature. The LM 93 is
dedicated to processor fan speed control and monitor, and can be programmed with temperature
limit values that allow it to speed up or idle the processor fans, depending upon the input
temperature.
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Equipment Required for CRB Usage
Equipment Required for CRB Usage 3
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The following components are required for the Intel Xeon™ Processor with 800 MHz System
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Bus and Intel E7520 and Intel 6300ESB Customer Reference Board (CRB) usage:
• A 550 W SSI EPS 12 V power supply. The CRB is shipped with the power supply.
• At least two modules of DDR2 400 DIMM. The CRB is shipped with 2 x 256 Mbytes of
DDR2 400.
1
• Hard drive loaded with Operating System
• Monitor
• PS/2 mouse and keyboard
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Visually inspect the board and ensure that the MCH, Intel 6300ESB I/O Controller, PXH, and
other components did not shake loose during shipment. If the board has any loose or missing
components, contact your Intel representative.
Caution: Powering up without all components installed correctly could lead to a power-up failure that could
damage the board. Do not power up the board until the source of any loose component is
determined and the component has been replaced on the board.
3.1
Precautions
The following precautions will reduce the chances of damaging the board:
• Ensure that a 550 W SSI EPV 12 V power supply is used to power up the CRB. Refer to
Section 5.1, “Power Diagrams” on page 25 for details on the SSI power supply interface on the
CRB.
• This platform supports DDR2 400 DIMMs; ensure that the same speed DIMM is plugged in
all slots of the platform.
• Ensure that each processor has heat sinks attached before powering up the board.
• Ensure that the heat sink is attached to the MCH and PXH before powering up the board.
Never attach a heat sink while the board is powered.
1. Note The hard disk provided with the development kit is not pre-loaded with any software.
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Equipment Required for CRB Usage
3.2
Driver and OS Requirements
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The required INF driver for the CRB supports the functionality of the Intel 6300ESB I/O
Controller and PXH. The INF file will be included with Red Hat compatible drivers on the CD
shipped with the kit.
The CRB supports these operating systems:
• Microsoft Windows* XP, Windows Embedded XP, 2000 Pro, 2000 Server, 2000 Advanced
Server, 2003 Standard Edition
• Red Hat Linux Advanced Server 2.1, Red Hat 8.0 on kernel 2.4.x
• Wind River VxWorks* real-time operating system
• QNX Neutrino* real-time operating system
• Customer operating systems when applicable
3.2.1
Drivers included on CD
3.2.1.1
Red Hat 8.0 Compatible Driver Package Contents
This operating system compatible driver package is available from:
Detail_Desc.asp?agr=Y&ProductID=1706&DwnldID=7249
esb_rh8.txt Release notes
sources/ac97/alsa-driver-0.9.0rc5.bz2 alsa-driver sources
sources/ac97/alsa-lib-0.9.0rc5.bz2 alsa-lib sources
sources/ac97/alsa-util-0.9.0rc5.bz2 alsa-util sources
sources/ac97/alsa-xmms-0.9.9b.tar.gz alsa plugin for xmms
sources/ac97/xmms-mpg123-1.2.7-13.i386.rpm mpeg plugin for xmms
sources/kernel/linux-2.4.20.tar.gz 2.4.20 kernel sources
sources/kernel/config-2.4.20-p4-upapic-i2c-apm-nooss UP Kernel Config File
sources/kernel/config-2.4.20-p4-upapic-i2c-acpi-nooss UP Kernel Config File
sources/kernel/config-2.4.20-p4-smp-i2c-apm-nooss MP Kernel Config File
sources/smbus/i2c-2.7.0.tar.gz latest I2C-core driver sources
sources/smbus/lm_sensors-2.7.0.tar.gz latest smbus adapter/sensor sources
sources/esbwdt/LICENSElicense for Intel WDT driver
sources/esbwdt/esbwdt-doc.txt Linux WDT Driver release notes
sources/esbwdt/driver/esbwdt.c Linux WDT Driver source file
sources/esbwdt/driver/esbwdt.h Linux WDT Driver header file
sources/esbwdt/driver/Makefile Linux WDT Driver Makefile
sources/esbwdt/demoapp/esbwdt-demo.c WDT driver demo application
patches/COPYING GPL-v2 license for Intel patches
patches/ac97/alsa-hr.patch enables ESB AC97 AC in ALSA
patches/ac97/alsa-hr-ich5.patch enables ICH5 AC97 AC in ALSA
patches/ide-sata/pci_ids-hr.patch enables ICH5 AC97 AC in ALSA
patches/ide-sata/pci_ids-hr-ich5.patch patches to 2.4.20 IDE driver
patches/ide-sata/piix.c-hr.patch to enable support for PATA & SATA storage interfaces
patches/ide-sata/piix.c-hr-ich5.patch to enable support for PATA & SATA storage
interfaces
patches/ide-sata/ide_pci-hr.patch integrated into the ESB & ICH5 Southbridges
patches/ide-sata/ide_pci-hr-ich5.patch integrated into the ESB & ICH5 Southbridges
patches/ide-sata/pci_irq-hr.patch integrated into the ESB & ICH5 Southbridges
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Equipment Required for CRB Usage
patches/ide-sata/pci_irq-hr-ich5.patch integrated into the ESB & ICH5 Southbridges
patches/lspci/pciids-112202.patch patch to update 2.4.20 pci.ids file
patches/lspci/pciids-112202-hr.patch patch to add ESB dev IDs to pci.ids
patches/lspci/pciids-112202-hr-ich5.patch patch to add ICH5 dev IDs to pci.ids
patches/ioapic/irqbalance-2.4.20-MRC.patch patch for use with P4 Hyper-Threading
patches/smbus/i2c-hr.patch enables ESB SMBUS dev in I2C driver
patches/smbus/i2c-hr-ich5.patch enables ICH5 SMBUS dev in I2C driver
patches/smbus/i2c-2.7.0-Makefile.patch customizations for I2C-2.7.0 Makefile
patches/smbus/lm_sensors-2.7.0-Makefile.patch customizations for lm_sensors
Makefile
patches/smbus/readme.txt build/install instruction for lm_sensors
binaries/binaries.tar.gz pre-build kernel and modules
utils/ks.cfg-raid015-hd-acd raid0, 1, & 5 enabled kickstart file
utils/ks.cfg-noraid-hda non-RAID kickstart file
utils/debug/readme-up.txt Instructions on using UP install scripts
ks.cfg-noraid-hda-cdrom-text-interactiveinteractive kickstart file
install-bin.pl script to automate UP pkg install
bldsrcs.pl script to automate UP pkg install
readme-smp.txt instructions on using SMP install scripts
bldsmpkernel.pl script to automate SMP kernel bld/install
bldsmpdrivers.pl script to automate SMP driver modules bld
3.2.1.2
Red Hat Advanced Server 2.1 Compatible Driver Package Contents
This operating system compatible driver package is available from:
Detail_Desc.asp?agr=Y&ProductID=1706&DwnldID=7248
esb_rhas.txt Release notes
sources/ac97/alsa-driver-0.9.0rc5.bz2 alsa-driver sources
sources/ac97/alsa-lib-0.9.0rc5.bz2 alsa-lib sources
sources/ac97/alsa-util-0.9.0rc5.bz2 alsa-util sources
sources/ac97/alsa-xmms-0.9.9b.tar.gz alsa plugin for xmms
sources/ac97/README build/install instructions for ac97
sources/kernel/config-2.4.9-e.24-p4-smp-i2c Optimized MP Kernel Config File
sources/kernel/config-2.4.9-e.24-p4-upapic-i2c Optimized UP Kernel Config File
sources/kernel/install-2.4.9-e.24esb-grub.conf.patch Patch to install UP kernel
sources/kernel/install-2.4.9-e.24esbsmp.patch Patch to install SMP kernel
sources/kernel/rhas21-q2u-gold-iso origin of RHAS Q2-03 updates
sources/smbus/i2c-2.7.0.tar.gz latest i2c-core driver sources
sources/smbus/lm_sensors-2.7.0.tar.gz latest smbus adapter/sensor sources
sources/esbwdt/LICENSE license for Intel WDT driver
sources/esbwdt/esbwdt-doc.txt esbwdt driver/demoapp release notes
sources/esbwdt/driver/esbwdt.c esbwdt driver sources
sources/esbwdt/driver/esbwdt.h esbwdt driver header file
sources/esbwdt/driver/Makefile esbwdt driver Makefile
sources/esbwdt/demoapp/esbwdt-demo.c esbwdt driver demo app
patches/COPYING GPL-v2 license for Intel patches
patches/ac97/alsa-hr.patch enables ESB AC97 AC in alsa
patches/ac97/alsa-hr-ich5.patch enables ICH5 AC97 AC in alsa
patches/ide-sata/pci_ids-hr.patchpatches to 2.4.9-e.24 ide driver
patches/ide-sata/pci_ids-hr-ich5.patch patches to 2.4.9-e.24 ide driver
patches/ide-sata/piix.c-hr.patch to enable support for pata & sata storage interfaces
patches/ide-sata/piix.c-hr-ich5.patch to enable support for pata & sata storage
interfaces
patches/ide-sata/ide_pci-hr.patch integrated into the esb6300 & ich5 southbridges
patches/ide-sata/ide_pci-hr-ich5.patch integrated into the esb6300 & ich5 southbridges
patches/ide-sata/pci_irq-hr.patch integrated into the esb6300 & ich5 southbridges
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Equipment Required for CRB Usage
patches/ide-sata/pci_irq-hr-ich5.patch integrated into the esb6300 & ich5 southbridges
patches/lspci/pci.ids-hr.patch adds esb dev ids to 2.4.9-e.24 pci.ids
patches/lspci/pci.ids-hr-ich5.patch adds ich5 dev ids to 2.4.9-e.24 pci.ids
patches/smbus/i2c-hr.patch enables esb smbus dev in i2c driver
patches/smbus/i2c-hr-ich5.patch enables ich5 smbus dev in i2c driver
patches/smbus/i2c-2.7.0-Makefile.patch customizations for i2c-2.7.0 Makefile
patches/smbus/lm_sensors-2.7.0-Makefile.patch customizations for lm_sensors
Makefile
sources/smbus/lm_sensors-2.7.0-Module.mk-patch patch to fix bld errs on rhas v21
patches/smbus/readme.txt build/install instructions for smbus
utils/debug/ks.cfg-yyyy basic kickstart file to install from ftp to hda
utils/debug/bldkernel.pl script to build/install esb enabled UP kernel
utils/debug/bldsrcs.pl script to build/install esb enabled UP drivers
utils/debug/readme.txt BKM (aka EASIEST) way to install UP kernel & drivers
utils/debug/bldsmpkern.pl script to build/install esb enabled SMP kernel
utils/debug/bldsmpdrivers.pl script to build/install esb enabled SMP drivers
utils/debug/readme-smp.txt BKM (aka EASIEST) way to install SMP kernel & drivers
3.2.1.3
Windows Compatible Driver Package Contents
This operating system compatible driver package is available from:
Detail_Desc.asp?agr=Y&ProductID=1706&DwnldID=7246
ESB_windows_Relnotes.txt Release notes for Windows* compatible drivers
SMB.SYS SMBus Driver
SMB.INF Install file for SMBus driver
SMB.CAT SMBus driver security catalog file
STAC97.SYS AC'97 audio code driver provided by SigmaTel*
SLAoemisv1.doc Single-user and OEM license for SigmaTel STA97 driver
WDTDRVR.SYS Watchdog Timer driver
WDTDRVR.INF Install file for Watchdog Timer driver
WDT_LICENSE.TXT Generic Alpha license for Watchdog Timer components
WDTDEMO.EXE Demo program for exercising Watchdog Timer features
Mfc42.dll Microsoft C++ runtime library
Mfco42.dll Microsoft C++ runtime library
Msvcrtd.dll Mircosoft C++ runtime library
wdtdemoAppSpec.pdf WdtDemo App user documentation
wdtdriverspec.pdf Overview of Watchdog Timer driver
Intelwdtapi.pdf Watchdog Timer driver interface API document
IWDTLIB.DLL Watchdog Timer Interface Dynamic Link Library
CWESB.slx eXP Configuration file
WESB.log log of OS build for eXP
eXP-README.DOC readme of eXP build
infinst_enu.exe Intel INF update utility
3.2.1.4
Third Party Drivers
Included on the CD is software compatible with the ATI Rage* Mobility-M Graphics Accelerator
021112a-006561C-ATI.zip.
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Jumpers and Headers
Jumpers and Headers
4
This section describes the platform component placement as well as configuration, test and debug
®
®
®
features of the Intel Xeon™ Processor with 800 MHz System Bus and Intel E7520 and Intel
6300ESB Customer Reference Board.
4.1
Jumpers
®
®
®
Figure 4.
Intel Xeon™ Processor with 800 MHz System Bus and Intel E7520 and Intel
6300ESB Customer Reference Board Jumper
+
+
+
MCH
®
Intel
6300ESB
I/O
PXH
Controller
+
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Jumpers and Headers
Table 4.
Jumper Settings (Sheet 1 of 3)
Default
Position
Jumper Name
Ref Des
Description/Settings
Enables 3.3 V AUX
3.3V Aux Enable
J1A1
1-2: Enable 3.3 V AUX for wake events
Open: 3.3 V Operation Only
1-2
1-2
Enable PXH
1-2: Enable
Enable PXH
No Reboot
J2G2
J2G3
Open: Disable
Prevents the system from rebooting following
a reset from Intel 6300ESB I/O Controller
Open
1-2: No Reboot
Open: Normal
Enable on SIO
1-2: Enable
Enable Super I/O Chip
5V Aux Enable
J2J1
J3A1
1-2
1-2
Open: Disable
Enables 5 V AUX
1-2: Enable 5 V VAUX for wake events
Open: 3.3 V Operation Only
Override VRM disable if no CPU0 installed
1-2 Override
CPU0 Present Override
Enable Video
J2H114
J4A1
Open
1-2
Open : Normal
Enable on Board video
1-2: Enable
(not
populated)
Open: Disable
LED Control
J3J1
J3J2
J4G5
J4G6
1-2
1-2
1-2 : Illuminate LED CR4J1 when EDT expires
ICH WDT Output
Reset Control
1-2 : Reset board when WDT Expires
Access to ICH VSWING pin
Do not Install Jumper
ICH VSWING Header
ICH VREF Header
Open
Open
Access to ICH VREF pin
Do not Install Jumper
Access to PCI SMbus
Do not install Jumper
1: PCI _SMBDAT
2. Ground
PCI SMBus Header
DDR SMBus Header
J4H1
J4H3
Open
Open
3. PCI_SMBCLK
Access to DDR SMbus
Do not install Jumper
1: DIMM _SMBDAT
2. Ground
3. DIMM_SMBCLK
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Jumpers and Headers
Table 4.
Jumper Settings (Sheet 2 of 3)
Default
Position
Jumper Name
Ref Des
Description/Settings
BSEL0
1-2
BSEL1
1-2
SPEED
Normal
FSB Clock Frequency
Override
2-3
2-3
RSVD
BSEL1: J4H4
BSEL0: J4J3
BSEL0: 1-2
BSEL1: 1-2
2-3
Open
Open
1-2
133 MHz
167 MHz
200 MHz
(Host Clock Jumpers)
Open
Open
Inject SMI Signal
SMI Inject
J4H5
J4H6
J4J1
J4J2
Open
Open
Open
Open
Do Not Install Jumper
Inject FORCEPR0 Signal
Do Not Install Jumper
FORCEPR0 inject
STPCLK Inject
FORCEPR1 inject
Inject STPCLK Signal
Do Not Install Jumper
Inject FORCEPR1 Signal
Do Not Install Jumper
Override VRM disable if CPU1 is not present
1-2: Override
CPU1 Present Override
BSEL Match Override
J4J5
J4J7
Open
Open
Open: Normal
Override VRM disable if BSELs do not match
1-2: Override
Open: Normal
1-2: VID[5]
3-4: VID[4]
5-6: VID[3]
7-8: VID[2]
9-10: VID[1]
11-12: VID[0]
As
Required
CPU1 VID
J4K1
Manual VID select
1-2: Manual select
Open: CPU select
CPU1 VID Override
J4K2
J5D3
Open
Open
Access to MCH SMbus
Do not install Jumper
1: MCH _SMBDAT
2. Ground
MCH SMBus Header
PLLS0
3. MCH_SMBCLK
See MCH Documentation for alternative Gear
Ratios for MCH FSB/Memory
J5E112
J5F1
Short
Open
Short
®
Intel 6300ESB I/O Controller Top Swap
1-2: Top Swap
Intel 6300ESB I/O
Controller Top Swap (FWH
Memory Swap)
Open: Normal
See MCH Documentation for alternative Gear
Ratios for MCH FSB/Memory
PLLS1
J5F113
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Jumpers and Headers
Table 4.
Jumper Settings (Sheet 3 of 3)
Default
Position
Jumper Name
Ref Des
Description/Settings
Intel 6300ESB I/O Controller Safe Mode
1-2: Safe Mode
Intel 6300ESB I/O Controller
Safe Mode
J5F3
Open
Open: Normal Mode
Clears CMOS
1-2: Normal
CMOS Clear
J5H1
J5H2
1-2
2-3: Configure
Validation only
Validation Only
Open
Do Not Install Jumper
Access to ICH SMBus
Do not Install Jumper
1: ICH_SMBDAT
2. Ground
ICH SMBUS header
J5H3
Open
3. ICH_SMBCLK
1-2: S3 Enable
S3 Enable
J7F1
J7K1
J8J1
1-2
1-2
1-2
Open S3 Disable
1-2: Full Speed
CPU1 Fan Override
CPU0 Fan Override
ITP Configuration
CPU0 Boot Select
Open: LM93 Controlled
1-2: Full Speed
Open: LM93 Controlled
J9 G4
J9G3
2-2: Uniprocessor
1-2
1-2
1-2: Dual Processor
1-2: Other processor support (RSVD)
Open: Intel Xeon support
J9H2
Open
Manual VID select
1-2: Manual select
Open: CPU select
CPU0 VID Override
J9K1
Open
1-2: VID[5]
3-4: VID[4]
5-6: VID[3]
7-8: VID[2]
9-10: VID[1]
11-12: VID[0]
As
Required
CPU0 VID
J9K2
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System Overview
System Overview
5
5.1
Power Diagrams
Figure 5 shows the power distribution for the CRB. Refer to the CRB schematics for details on the
power distribution logic. (Contact your Intel field sales representative to obtain the schematics
file.)
Figure 5.
Power Distribution Block Diagram
May be Shared
VRM 10.1
650WSI
(EPS12V)
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System Overview
5.2
Platform Clocking
The CRB uses one CK409B Clock Synthesizer to generate the host differential pair clocks and the
100 MHz differential clock to the DB800. The DB800 then generates the 100 MHz differential pair
Figure 6.
Clock Block Diagram
CPU0
CPU1
ITP
DDRA
DDRB
MCH
PCI-X
PCI-X
Intel
6300ESB
I/O
Controller
Hub
PXH
SIO
HI LAI
Video
FWH
PCI Express Slot
PCI Express Slot
Port 80
PCI 2.2
DB800
CK-409
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System Overview
5.3
Platform Resets
Figure 7 depicts the reset logic for the CRB. The Intel 6300ESB I/O Controller provides most of
the reset following assertion of power good and system reset. However, the glue logic within the
SIO is also used to buffer reset to PXH, MCH, FWH, and IDE.
Figure 7.
Platform Reset Diagram
PCI 32
SIO
IDE
PCI-X
PCI-X
CPU 0
CPU 1
FWH
MCH
Port 80
ITP-700
Intel
6300ESB
I/O
Controller
Hub
PCI-X
PCI-X
PCI-X
PXH
PCI-E
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System Overview
5.4
SMBus
Figure 8 below illustrates the routing of the SMBus signal among the components.
Figure 8.
SMBus Block Diagram
Intel 6300ESB I/O
Controller Hub
PCI-X 133 MHz
Slot (Slot #1)
PCI-X 100 MHz
Slot (Slot #2)
LM 93
SMBus
Repeater
PCI-X 100 MHz
Slot (Slot #3)
ITP-XDP
SMBus
Master Only
PCI Express
Slot (Slot #4)
PCI Express
Slot (Slot #5)
Intel E7520
Chipset
SMBus
Repeater
PCI-X 66 MHz
Slot (Slot #6)
PXH-D
CK409B
DB800
DIMM #A1
Addr 0xA0
DIMM #B1
Addr 0xA8
PCI-X 66 MHz
Slot (Slot #7)
DIMM #A2
Addr 0xA2
DIMM #B2
Addr 0xAA
PCI 32-bit /
33 MHz (Slot #8)
DDR CH A
DDR CH B
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System Overview
5.5
Platform IRQ Routing
Figure 9 shows that the Intel 6300ESB I/O Controller uses these segments:
• IRQ14 and 15 for IDE segment
• SERIRQ for SIOPIXRQ segment
• PCRIRQ for the PCI-X segment
• PIRQ for the PCI 32/33 segment
A Message Signalled Interrupt (MSI) scheme is used between the MCH and PXH over the PCI
Express bus. The PXH uses PAIRQ for the Channel A interface to PCI-X 64-bit/100 MHz
peripherals and PBIRQ for the Channel B interface to PCI-X 64/133. MSI and Non Maskable
Interrupt (NMI) are connected from the Intel 6300ESB I/O Controller to CPU0 and CPU1. The
platform also supports MSI for maskable and non-maskable interrupts.
Figure 9.
IRQ Routing Diagram
PCI-X SLOT
REQ/GNT: 0
PCI-X SLOT
REQ/GNT: 0
PCI-X SLOT
REQ/GNT: 1
PCI-E
4x
PCI-E
8x
IDSEL: AD17 IDSEL: AD17 IDSEL: AD18
MSI
MSI
A
B
C
D
A
B
C
D
A
B
C
D
0
1
2
3
CPU0
0
1
2
3
4
5
6
7
PXH
MCH
PCI-X SLOT
REQ/GNT: 0
IDSEL: AD16
Video
REQ/GNT: 1
IDSEL: AD17
IDE
A
B
C
D
A
IRQ14/15
A
B
C
D
E
F
PCI-X SLOT
REQ/GNT: 0
PCI-X SLOT
REQ/GNT: 1
Intel
6300ESB
I/O
Controller
Hub
IDSEL: AD17 IDSEL: AD18
CPU0
A
B
C
D
A
B
C
D
G
H
A
B
C
D
SERIRQ
SIO
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System Overview
5.6
VRD VID Headers
Provides for manual control of the processor core voltage regulator output level(s). Normally, the
processor should be run at its default VID (voltage identification) value as set during
manufacturing. However, in the event the user needs to set a different VID value from the default
value, it can be accomplished through a jumper block found on the board. Note that these headers
are not populated by default.
the VID settings available via the VID headers.
Table 5.
Processor VRD Settings (Sheet 1 of 2)
VCC_MAX
(V)
VCC_MAX
(V)
VID5 VID4 VID3 VID2 VID1 VID0
VID5 VID4 VID3 VID2 VID1 VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
OFF
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.400
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
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System Overview
Table 5.
Processor VRD Settings (Sheet 2 of 2)
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
OFF
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
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System Overview
5.7
Miscellaneous Buttons
Figure 10 below shows the location of the power buttons within the platform.
Figure 10.
Power Buttons
+
+
+
MCH
®
Intel
6300ESB
I/O
PXH
Controller
+
®
®
®
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Debug Procedure
Debug Procedure
6
®
The debug procedures in this section are used to determine baseline functionality for the Intel
®
®
Xeon™ Processor with 800 MHz System Bus, Intel E7520 Chipset, and Intel 6300ESB ICH
Development Kit. This is a cursory set of tests designed to provide a level of confidence in the
platform operation.
6.1
Level 1 Debug (Port 80/BIOS)
Level 1 Debug (Port 80/BIOS)
Table 6.
Item
Test
Pass/Fail Criteria
Cause of Failure
Power Sequence Failure—go immediately to Level 2
debug
1
Verify “SYSTEM PWRGD” LED CR2H1: Green
Is “PCI Reset” LED (decimal on Decimal on Port 80 display
2
3
PCI Reset Stuck—go to Level 3 debug
CPU Reset Stuck—go to Level 3 debug
DS1J2) illuminated?
Red
Verify CPURST LED is off
CR7K3: Off
System Hang—Check BIOS go to level 3 debug. Refer
to AMI* BIOS documentation for details. Also refer to
Schematic Page 68, Coord. D5.
Port 80 LEDs are posting
boot codes and stopping
4
Verify Port 80 Posting
Contact your Intel Representative for the latest BIOS
image.
5
6
Check BIOS revision
Latest BIOS installed
See default settings
Verify default Jumper settings
Improper Jumper settings
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Debug Procedure
6.2
Level 2 Debug (Power Sequence)
Table 7.
Level 2 Debug (Power Sequence)
Item
Test
Pass/Fail Criteria
Cause of Failure
Measure voltage across:
•
•
•
•
•
C3K2: 3.3 V
C3K1: -12 V
C4K3: 5 V
1
Primary power supply voltages
External power supply failure
C4K2: 5 V
C4K5: 12 V
2
3
4
5
6
7
8
1.8 V
C9E14: 1.8 V
DDR2 power supply failure
MCH/PXH/ICH core power supply failure
DDR2 standby power supply failure
CPU_VTT power supply failure
CPU0 VRD Failure
1.5 V
C5C5: 1.5 V
1.8 VSBY
C9G5: 1.8 V
CPU VTT power supply
CPU0 VRD
CPU1 VRD
C9H10: 1.2 V
L9J2: 1.2 V - 1.4 V
L5J1: 1.2 V – 1.4 V
CPU1 VRD Failure
Verify “SYSTEM PWRGD” LED CR2H1: Green
Power Sequence Failure
6.3
Level 3 Debug (Voltage References)
Table 8.
Level 3 Debug (Voltage References)
Item
Test
Pass/Fail Criteria
Cause of Failure
1
2
3
4
5
6
MCH DDR2 Channel A Vref
MCHDDR2 Channel B Vref
MCH Hublink Vref
R6D4: 0.9 V
Vref incorrect: check resistor values
Vref incorrect: check resistor values
Vref incorrect: check resistor values
Vswing incorrect: check resistor values
Vref incorrect: check resistor values
Vswing incorrect: check resistor values
R6B3: 0.9 V
R5F11: 0.354 V
R5F8: 0.804 V
R4G7: 0.347 V
R4G4: 0.696 V
MCH Hublink Vswing
ICH Hublink Vref
ICH Hublink Vswing
CPU0 VTT Vref
(Back side of board)
R2U5: 0.775 V
R2V2: 0.775 V
7
8
Vref incorrect: check resistor values
Vref incorrect: check resistor values
CPU1 VTT Vref
(Back side of board)
R4U5: 0.754
R5V1: 0.754
9
10
11
MCH VTT Vref
R6F2: 0.775 V
R3M1: 0.9 V
R2M1: 0.9 V
Vref incorrect: check resistor values
Vref incorrect: check resistor values
Vref incorrect: check resistor values
DIMM A DDR2 Vref
DIMM B DDR2 Vref
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Heatsink Assembly
Heatsink Assembly
7
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This section provides heatsink assembly instructions for the Intel Xeon™ Processor with 800
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MHz System Bus, Intel E7520 Chipset, and Intel 6300ESB ICH Development Kit:
Table 9.
Components Requiring Heat Sink Assembly
Quantity per
Board
Heat Sink
Manufacturer
Component
Part Number
Comments
Processors
Up to 2
Cooler Master
E3W-N73CS-I1 Active heat sink + back plate.
Figure 11.
Components Requiring Heat Sink Assembly
Processors
(2)
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Heatsink Assembly
7.1
Processor Heat Sink Installation Instructions
Note: Tools/items needed include Phillips screwdriver, disposable towels, and isopropyl alcohol.
1. Ensure the processor is firmly seated in the socket and the socket latch is closed. (See
Figure 12.
Inserting Processor in Socket
Figure 13.
Cleaning the Processor Surface
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Heatsink Assembly
3. Insert the processor heat sink back plate into the four mounting holes near the processor. The
Figure 14.
Installing the Processor Backplate
4. Remove the protective covers from the processor heat sink. There is a cover that protects the
fan, and another that protects the preapplied thermal interface material on the bottom of the
Figure 15.
Removing the Protective Covers
Remove
plastic
5. Place the heat sink on top of the CPU and align the four screws to the threads of the backplate.
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Heatsink Assembly
Figure 16.
Installing the Heatsink
Tighten screw 1
Tighten screw 4
Tighten screw 3
Tighten screw 2
screws are shoulder screws and will stop threading once completely tightened.
7. Plug the fan connector into the nearest fan connector on the PCB.
8. If applicable, repeat this process for the second processor.
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